Archived
18 lines
1.6 KiB
Markdown
18 lines
1.6 KiB
Markdown
# Vivado Git Repository
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Since the day I was admitted to my lab, the vivado project management has always been a pain in the ass for me and my lab fellows. And I didn't realize how vital revision control is to a software/hardware developer until the day I accidentally overwrote the initial version of one of my modules and it's gone ever since. So after couple of days learning vivado revision control tricks, this repository came out.
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The target of this repository is to stores vivado-related project and verilog/vhdl files, and maybe associated MATLAB files, or even related documentations explaining how the modules work and things needed to be taken care of when interfacing with the modules.
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## How this repository is constructed?
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This repository include all the design sources and third-party reference used in my vivado project.
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| Directory Name | Description | Synthesis Required | Implementation Required | Bitstream Required |
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| :------------: | :--------------------------------------------------------------- | :--: | :--: | :--: |
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| adi_library | ADI no-OS IP Library, build with Xilinx Vivado 2019.1. | N/A | N/A | N/A |
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| common | Common Verilog/VHDL modules that can work solely without other IPs. | Yes | No | No |
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| modules | Verilog/VHDL modules that work with other IPs, thus the modules are FPGA-specific and they are managed in project mode. In the future the modules may also be categorised by different Vivado versions. | Yes | No | No |
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| projects | Project or board specific vivado projects, that can be run on hardware. | Yes | Yes | Yes |
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| template | Project initialization template. | N/A | N/A | N/A |
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