Archived
josh
cd256a8cd6
gitignore structure is updated to work with single and multi project situation under a single project directory
596 lines
26 KiB
Verilog
596 lines
26 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 08/06/2022 04:20:01 PM
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// Design Name:
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// Module Name: system_top
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module system_top(
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/***************************************************************************
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* Interface Content
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* 01 - Clocks & Reset
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* 02 - DDR and Fixed-io
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***************************************************************************/
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// *************************************************************************
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// ***************************** PS Fixed IOs ******************************
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// ************************************************************************
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inout [14:0] DDR_addr ,
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inout [2:0] DDR_ba ,
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inout DDR_cas_n ,
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inout DDR_ck_n ,
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inout DDR_ck_p ,
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inout DDR_cke ,
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inout DDR_cs_n ,
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inout [3:0] DDR_dm ,
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inout [31:0] DDR_dq ,
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inout [3:0] DDR_dqs_n ,
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inout [3:0] DDR_dqs_p ,
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inout DDR_odt ,
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inout DDR_ras_n ,
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inout DDR_reset_n ,
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inout DDR_we_n ,
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inout FIXED_IO_ddr_vrn ,
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inout FIXED_IO_ddr_vrp ,
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inout [53:0] FIXED_IO_mio ,
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inout FIXED_IO_ps_clk ,
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inout FIXED_IO_ps_porb ,
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inout FIXED_IO_ps_srstb ,
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// *************************************************************************
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// *************************** Clocks and Resets ***************************
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// *************************************************************************
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input CLK_25M , // pl clock, 25mhz
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// glink gt reference clock
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input glink_refclk_p , // generated by oscillator, 125mhz
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input glink_refclk_n ,
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// *************************************************************************
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// ************************************ LVDS *******************************
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// *************************************************************************
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input Din1 ,
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output Dout1 ,
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input Din2 ,
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output Dout2 ,
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input DCLK_in ,
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output DCLK_out ,
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input TR ,
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input DARY ,
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// *************************************************************************
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// *********************************beam ctrl*******************************
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// *************************************************************************
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output [3:0] CLK_TR ,
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output [3:0] TR_TR ,
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output [3:0] DATA_TR ,
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output [3:0] SYN_TR ,
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output [3:0] SEL_TR ,
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output [3:0] SEL4_TR ,
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output [3:0] SEL3_TR ,
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output [3:0] SEL2_TR ,
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output [3:0] SEL1_TR ,
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output T_DLY ,
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output R_DLY ,
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output PW_DOWN ,
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// *************************************************************************
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// ************************************ GLINK *******************************
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// *************************************************************************
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input rx_datain_p_ch_a ,
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input rx_datain_n_ch_a ,
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input rx_datain_p_ch_b ,
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input rx_datain_n_ch_b ,
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output tx_dataout_p_ch_a ,
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output tx_dataout_n_ch_a ,
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output tx_dataout_p_ch_b ,
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output tx_dataout_n_ch_b
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);
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/*******************************************************************************
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*******************************************************************************/
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//supply1 const_high;
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//assign PW_DOWN = const_high;
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//******************************************************************************
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//******************************* Clock & Reset *********************************
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//******************************************************************************
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wire CLK_25M_1;
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wire CLK_25M_2;
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wire CLK_25M_3;
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clk_wiz_25m_1to3 u_clk_wiz_25m_1to3
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(
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// Clock out ports
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.clk_out1(CLK_25M_1), // output clk_out1
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.clk_out2(CLK_25M_2), // output clk_out2
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.clk_out3(CLK_25M_3), // output clk_out3
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// Clock in ports
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.clk_in1(CLK_25M)); // input clk_in1
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//////clk_lvds
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wire pl_clk_96m;
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wire lvds_rst;
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wire lvds_locked;
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clk_wiz_lvds u_clk_wiz_lvds
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(
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// Clock out ports
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.clk_out1(pl_clk_96m), // output clk_out1
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// Status and control signals
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.locked(lvds_locked), // output locked
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// Clock in ports
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.clk_in1(CLK_25M_1)); // input clk_in1
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assign lvds_rst = ~lvds_locked;
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//////clk_glink
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wire glink_logic_clk ;
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wire glink_ila_clk ;
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wire glink_rst;
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wire glink_locked;
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clk_wiz_glink u_clk_wiz_glink
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(
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// Clock out ports
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.clk_out1(glink_logic_clk), // output clk_out1 25m
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.clk_out2(glink_ila_clk), // output clk_out2 125m
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// Status and control signals
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.locked(glink_locked), // output locked
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// Clock in ports
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.clk_in1(CLK_25M_2)); // input clk_in1
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assign glink_rst = ~glink_locked;
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//////clk_beam
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wire clk_beam_100m;
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wire clk_beam_12_5m;
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wire clk_beam_50m;
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wire beam_locked;
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clk_wiz_beam u_clk_wiz_beam
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(
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// Clock out ports
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.clk_out1(clk_beam_100m), // output clk_out1
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.clk_out2(clk_beam_12_5m), // output clk_out2
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.clk_out3(clk_beam_50m), // output clk_out3
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// Status and control signals
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.locked(beam_locked), // output locked
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// Clock in ports
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.clk_in1(CLK_25M_3)); // input clk_in1
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//******************************************************************************
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//********************************* selectio ************************************
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//******************************************************************************
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wire lvds_clkin;
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wire lvds_rx_clk;
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clk_wiz_96m_1to1 u_clk_wiz_96m_1to1
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(
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// Clock out ports
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.clk_out1(lvds_rx_clk), // output clk_out1
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// Clock in ports
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.clk_in1(lvds_clkin)); // input clk_in1
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assign lvds_clkin = DCLK_in;
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wire [3:0] lvds_din;
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wire [3:0] lvds_rx_data;
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selectio_lvds_rx u_selectio_lvds_rx
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(
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.data_in_from_pins(lvds_din), // input [3:0] data_in_from_pins
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.data_in_to_device(lvds_rx_data), // output [3:0] data_in_to_device
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.clk_in(lvds_rx_clk), // input clk_in
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.io_reset(lvds_rst) // input io_reset
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);
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assign lvds_din[0] = Din1;
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assign lvds_din[1] = Din2;
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assign lvds_din[2] = TR;
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assign lvds_din[3] = DARY;
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wire lvds_dout;
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wire lvds_tx_data;
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wire lvds_clkout;
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wire lvds_tx_clk;
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selectio_lvds_tx u_selectio_lvds_tx
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(
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.data_out_from_device(lvds_tx_data), // input [0:0] data_out_from_device
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.data_out_to_pins(lvds_dout), // output [0:0] data_out_to_pins
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.clk_in(lvds_tx_clk), // input clk_in
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.clk_out(lvds_clkout), // output clk_out
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.io_reset(lvds_rst) // input io_reset
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);
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assign Dout1 = lvds_dout;
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assign DCLK_out = lvds_clkout;
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//******************************************************************************
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//**************************** System Block Design ******************************
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//******************************************************************************
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wire c2c_rst_n ;
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wire c2c_rx_clk ;
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wire c2c_tx_clk ;
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wire [31:0] c2c_tx_fifo_tdata ;
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wire c2c_tx_fifo_tlast ;
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wire c2c_tx_fifo_tready ;
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wire c2c_tx_fifo_tvalid ;
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wire [31:0] c2c_rx_fifo_tdata ;
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wire c2c_rx_fifo_tlast ;
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wire c2c_rx_fifo_tready ;
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wire c2c_rx_fifo_tvalid ;
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wire ps_clk ;
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wire glink_ip_clk ;
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wire [31:0] glink_gpio_i_0 ;
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wire [31:0] glink_gpio_i_1 ;
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wire [31:0] glink_gpio_o_0 ;
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wire [31:0] glink_gpio_o_1 ;
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wire [15:0] glink_tx_fifo_tdata ;
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wire glink_tx_fifo_tlast ;
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wire glink_tx_fifo_tready ;
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wire glink_tx_fifo_tvalid ;
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wire [15:0] glink_rx_fifo_tdata ;
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wire glink_rx_fifo_tlast ;
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wire glink_rx_fifo_tready ;
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wire glink_rx_fifo_tvalid ;
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wire pwdown_gpio_o ;
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system_bd_wrapper u_system_bd_wrapper
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(.DDR_addr (DDR_addr[14:0] ),
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.DDR_ba (DDR_ba[2:0] ),
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.DDR_cas_n (DDR_cas_n ),
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.DDR_ck_n (DDR_ck_n ),
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.DDR_ck_p (DDR_ck_p ),
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.DDR_cke (DDR_cke ),
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.DDR_cs_n (DDR_cs_n ),
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.DDR_dm (DDR_dm[3:0] ),
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.DDR_dq (DDR_dq[31:0] ),
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.DDR_dqs_n (DDR_dqs_n[3:0] ),
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.DDR_dqs_p (DDR_dqs_p[3:0] ),
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.DDR_odt (DDR_odt ),
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.DDR_ras_n (DDR_ras_n ),
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.DDR_reset_n (DDR_reset_n ),
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.DDR_we_n (DDR_we_n ),
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.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn ),
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.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp ),
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.FIXED_IO_mio (FIXED_IO_mio[53:0] ),
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.FIXED_IO_ps_clk (FIXED_IO_ps_clk ),
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.FIXED_IO_ps_porb (FIXED_IO_ps_porb ),
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.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb ),
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//C2C
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.c2c_rst_n (c2c_rst_n ),
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.c2c_rx_clk (c2c_rx_clk ),
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.c2c_tx_clk (c2c_tx_clk ),
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.m_axis_fifo_c2c_out_tdata (c2c_tx_fifo_tdata[31:0] ),
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.m_axis_fifo_c2c_out_tlast (c2c_tx_fifo_tlast ),
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.m_axis_fifo_c2c_out_tready (c2c_tx_fifo_tready ),
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.m_axis_fifo_c2c_out_tvalid (c2c_tx_fifo_tvalid ),
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.s_axis_fifo_c2c_in_tdata (c2c_rx_fifo_tdata[31:0] ),
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.s_axis_fifo_c2c_in_tlast (c2c_rx_fifo_tlast ),
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.s_axis_fifo_c2c_in_tready (c2c_rx_fifo_tready ),
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.s_axis_fifo_c2c_in_tvalid (c2c_rx_fifo_tvalid ),
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//PS CLK
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.ps_clk (ps_clk ),
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// Glink Ports
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.glink_ip_clk (glink_ip_clk ),
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.glink_ip_rst_n (~glink_rst ),
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.glink_gpio_i_0 (glink_gpio_i_0[31:0] ),// PS <- Glink
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.glink_gpio_i_1 (glink_gpio_i_1[31:0] ),// PS <- Glink
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.glink_gpio_o_0 (glink_gpio_o_0[31:0] ),// PS -> Glink
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.glink_gpio_o_1 (glink_gpio_o_1[31:0] ),// PS -> Glink
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.m_axis_fifo_glink_out_tdata (glink_tx_fifo_tdata[15:0] ),// PS -> Glink
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.m_axis_fifo_glink_out_tlast (glink_tx_fifo_tlast ),// PS -> Glink
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.m_axis_fifo_glink_out_tready (glink_tx_fifo_tready ),// PS -> Glink
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.m_axis_fifo_glink_out_tvalid (glink_tx_fifo_tvalid ),// PS -> Glink
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.s_axis_fifo_glink_in_tdata (glink_rx_fifo_tdata[15:0] ),// PS <- Glink
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.s_axis_fifo_glink_in_tlast (glink_rx_fifo_tlast ),// PS <- Glink
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.s_axis_fifo_glink_in_tready (glink_rx_fifo_tready ),// PS <- Glink
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.s_axis_fifo_glink_in_tvalid (glink_rx_fifo_tvalid ),// PS <- Glink
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.pwdown_gpio_o (pwdown_gpio_o )
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);
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assign c2c_rst_n = ~lvds_rst;
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assign c2c_rx_clk = lvds_rx_clk;
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assign c2c_tx_clk = lvds_tx_clk;
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reg pwdown_gpio_o_100M_d1;
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reg pwdown_gpio_o_100M_d2;
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reg pwdown_gpio_o_100M_d3;
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always @ ( posedge clk_beam_100m ) begin
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if ( ~beam_locked ) begin
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pwdown_gpio_o_100M_d1 <= 1'd0;
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pwdown_gpio_o_100M_d2 <= 1'd0;
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pwdown_gpio_o_100M_d3 <= 1'd0;
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end
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else begin
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pwdown_gpio_o_100M_d1 <= pwdown_gpio_o;
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pwdown_gpio_o_100M_d2 <= pwdown_gpio_o_100M_d1;
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pwdown_gpio_o_100M_d3 <= pwdown_gpio_o_100M_d2;
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end
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end
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assign PW_DOWN = pwdown_gpio_o_100M_d3;
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//******************************************************************************
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//*********************************** Glink *************************************
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//******************************************************************************
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glink_top u_glink_top(
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// glink gt reference clock
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.glink_refclk_p (glink_refclk_p ), //in,125mhz
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.glink_refclk_n (glink_refclk_n ),
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// glink pk clock
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.glink_logic_clk (glink_logic_clk ), //in,25mhz
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.pl_rst (glink_rst ),
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.rx_datain_p_ch_a (rx_datain_p_ch_a ),
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.rx_datain_n_ch_a (rx_datain_n_ch_a ),
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.rx_datain_p_ch_b (rx_datain_p_ch_b ),
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.rx_datain_n_ch_b (rx_datain_n_ch_b ),
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.tx_dataout_p_ch_a (tx_dataout_p_ch_a ),
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.tx_dataout_n_ch_a (tx_dataout_n_ch_a ),
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.tx_dataout_p_ch_b (tx_dataout_p_ch_b ),
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.tx_dataout_n_ch_b (tx_dataout_n_ch_b ),
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//glink_ctrl
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.glink_gpio_i_0 (glink_gpio_i_0 ),
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.glink_gpio_i_1 (glink_gpio_i_1 ),
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.glink_gpio_o_0 (glink_gpio_o_0 ),
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.glink_gpio_o_1 (glink_gpio_o_1 ),
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//DMA_send_fifo
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.glink_tx_fifo_tdata (glink_tx_fifo_tdata ),
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.glink_tx_fifo_tlast (glink_tx_fifo_tlast ),
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.glink_tx_fifo_tready (glink_tx_fifo_tready ),
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.glink_tx_fifo_tvalid (glink_tx_fifo_tvalid ),
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//DMA_recv_fifo
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.glink_rx_fifo_tdata (glink_rx_fifo_tdata ),
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.glink_rx_fifo_tlast (glink_rx_fifo_tlast ),
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.glink_rx_fifo_tready (glink_rx_fifo_tready ),
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.glink_rx_fifo_tvalid (glink_rx_fifo_tvalid ),
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.glink_ip_clk (glink_ip_clk )//out,31.25mhz
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);
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//******************************************************************************
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//***************************** C2C DMA Control *******************************
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//******************************************************************************
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c2c_bridge_dma u_c2c_bridge_dma(
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.clk (pl_clk_96m ), // input clk, 96Mhz
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.rst (lvds_rst ), // input rst, active high
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//interface data
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.c2c_clkin (lvds_rx_clk ),
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.c2c_clkout (lvds_tx_clk ),
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.c2c_din (lvds_rx_data[0] ),
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.c2c_dout (lvds_tx_data ),
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//dma fifo interface
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.c2c_tx_fifo_tdata (c2c_tx_fifo_tdata ),
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.c2c_tx_fifo_tlast (c2c_tx_fifo_tlast ),
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.c2c_tx_fifo_tready (c2c_tx_fifo_tready ),
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.c2c_tx_fifo_tvalid (c2c_tx_fifo_tvalid ),
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.c2c_rx_fifo_tdata (c2c_rx_fifo_tdata ),
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.c2c_rx_fifo_tlast (c2c_rx_fifo_tlast ),
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.c2c_rx_fifo_tready (c2c_rx_fifo_tready ),
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.c2c_rx_fifo_tvalid (c2c_rx_fifo_tvalid )
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);
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//******************************************************************************
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//************************************* beam ctrl*********************************
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//******************************************************************************
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wire beam_clk;
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wire en_out;
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wire data_out;
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wire tr_out;
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wire dary_out;
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wire [15:0] debug_freq ;
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wire debug_freq_change ;
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wire [63:0] debug_tr_count ;
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antenna_interface u_antenna_interface
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(
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.clk_in (lvds_rx_clk ),
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.data_in (lvds_rx_data[1]),
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.tr_in (lvds_rx_data[2]),
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.dary_in (lvds_rx_data[3]),
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.rst (lvds_rst ),
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.ant_clk (beam_clk ),
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.en_out (en_out ),
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.clk_out (clk_beam_100m ),
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.data_out (data_out ),
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.tr_out (tr_out ),
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.dary_out (dary_out ),
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.debug_freq (debug_freq ),
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.debug_freq_change (debug_freq_change),
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.debug_tr_count (debug_tr_count )
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);
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ttop_S_005X u_ttop_S_005X(
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.clock100 (clk_beam_100m ),
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.clkdv (clk_beam_12_5m ),
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.clk50 (clk_beam_50m ),
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.n_rst (pwdown_gpio_o_100M_d3),
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//interface Vio
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.CLK (beam_clk ),
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.DATA (data_out ),
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.EN (en_out ),
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.DARY (dary_out ),
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.TR (tr_out ),
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//TR Com_Tr_TR_N ,
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.CLK_TR ({CLK_TR[0] ,CLK_TR[1] ,CLK_TR[2] ,CLK_TR[3] } ),
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.DATA_TR ({DATA_TR[0],DATA_TR[1],DATA_TR[2],DATA_TR[3] } ),
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.SYN_TR ({SYN_TR[0] ,SYN_TR[1] ,SYN_TR[2] ,SYN_TR[3] } ),
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.SEL_TR ({SEL_TR[0] ,SEL_TR[1] ,SEL_TR[2] ,SEL_TR[3] } ),
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.SEL4_TR ({SEL1_TR[3],SEL2_TR[3],SEL3_TR[3],SEL4_TR[3] } ),
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.SEL3_TR ({SEL1_TR[2],SEL2_TR[2],SEL3_TR[2],SEL4_TR[2] } ),
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.SEL2_TR ({SEL1_TR[1],SEL2_TR[1],SEL3_TR[1],SEL4_TR[1] } ),
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.SEL1_TR ({SEL1_TR[0],SEL2_TR[0],SEL3_TR[0],SEL4_TR[0] } ),//sel4是高使
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.TR_TR ({TR_TR[0],TR_TR[1],TR_TR[2],TR_TR[3] } ),
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//DLY
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.T_DLY(T_DLY),
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.R_DLY(R_DLY),
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//test
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.LED0 ( ),
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.LED1 ( ),
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.test1( ),
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.test2( ),
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.test3( ),
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.test4( ),
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.test5( ),
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.test6( ),
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.test7( ),
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.test8( )
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);
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//******************************************************************************
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//******************************* ILAs and VIOs *******************************
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//******************************************************************************
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ila_c2c_dma_tx u_ila_c2c_dma_tx (
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.clk (u_c2c_bridge_dma.clk ), // input wire clk
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.probe0 (u_c2c_bridge_dma.c2c_tx_fifo_tdata ), // input wire [31:0] probe0
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.probe1 (u_c2c_bridge_dma.c2c_tx_fifo_tlast ), // input wire [0:0] probe1
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.probe2 (u_c2c_bridge_dma.c2c_tx_fifo_tready), // input wire [0:0] probe2
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|
.probe3 (u_c2c_bridge_dma.c2c_tx_fifo_tvalid), // input wire [0:0] probe3
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.probe4 (u_c2c_bridge_dma.rst ), // input wire [0:0] probe4
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|
.probe5 (u_c2c_bridge_dma.c2c_dout ), // input wire [0:0] probe5
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.probe6 (u_c2c_bridge_dma.tx_data_32 ) // input wire [31:0] probe6
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);
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|
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ila_c2c_dma_rx u_ila_c2c_dma_rx (
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.clk (u_c2c_bridge_dma.c2c_clkin ), // input wire clk
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|
.probe0 (u_c2c_bridge_dma.c2c_rx_fifo_tdata ), // input wire [31:0] probe0
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|
.probe1 (u_c2c_bridge_dma.c2c_rx_fifo_tlast ), // input wire [0:0] probe1
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|
.probe2 (u_c2c_bridge_dma.c2c_rx_fifo_tready), // input wire [0:0] probe2
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|
.probe3 (u_c2c_bridge_dma.c2c_rx_fifo_tvalid), // input wire [0:0] probe3
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|
.probe4 (u_c2c_bridge_dma.rx_state ), // input wire [3:0] probe4
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|
.probe5 (u_c2c_bridge_dma.rx_state_next ), // input wire [3:0] probe5
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|
.probe6 (u_c2c_bridge_dma.rx_data_cnt ), // input wire [36:0] probe6
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|
.probe7 (u_c2c_bridge_dma.rx_frame_length ), // input wire [31:0] probe7
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|
.probe8 (u_c2c_bridge_dma.rx_data_32 ), // input wire [31:0] probe8
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|
.probe9 (u_c2c_bridge_dma.c2c_din ) // input wire [0:0] probe9
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|
);
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|
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ila_glink u_ila_glink (
|
|
.clk (glink_ila_clk ), // input wire clk
|
|
.probe0 (u_glink_top.glink_rst ), // input wire [0:0] probe0
|
|
.probe1 (u_glink_top.smartnc_trans_trig ), // input wire [0:0] probe1
|
|
.probe2 (u_glink_top.smartnc_trans_reset ), // input wire [0:0] probe2
|
|
.probe3 (u_glink_top.smartnc_trans_idle ), // input wire [0:0] probe3
|
|
.probe4 (u_glink_top.smartnc_trans_err ), // input wire [0:0] probe4
|
|
.probe5 (u_glink_top.smartnc_intf_tx_fifo_wdata ), // input wire [15:0] probe5
|
|
.probe6 (u_glink_top.smartnc_intf_tx_fifo_wr_en ), // input wire [0:0] probe6
|
|
.probe7 (u_glink_top.smartnc_intf_tx_fifo_afull ), // input wire [0:0] probe7
|
|
.probe8 (u_glink_top.smartnc_intf_rx_fifo_empty ), // input wire [0:0] probe8
|
|
.probe9 (u_glink_top.smartnc_intf_rx_fifo_rdata ), // input wire [15:0] probe9
|
|
.probe10(u_glink_top.smartnc_intf_rx_fifo_rd_en ), // input wire [0:0] probe10
|
|
.probe11(u_glink_top.smartnt_intf_cmd_proc_req ), // input wire [0:0] probe11
|
|
.probe12(u_glink_top.smartnt_intf_cmd_proc_ack ), // input wire [0:0] probe12
|
|
.probe13(u_glink_top.smartnt_intf_rx_fifo_empty ), // input wire [0:0] probe13
|
|
.probe14(u_glink_top.smartnt_intf_rx_fifo_rdata ), // input wire [15:0] probe14
|
|
.probe15(u_glink_top.smartnt_intf_rx_fifo_rd_en ), // input wire [0:0] probe15
|
|
.probe16(u_glink_top.smartnt_intf_tx_fifo_wdata ), // input wire [15:0] probe16
|
|
.probe17(u_glink_top.smartnt_intf_tx_fifo_wr_en ), // input wire [0:0] probe17
|
|
.probe18(u_glink_top.glink_ip_clk ), // input wire [0:0] probe18
|
|
.probe19(u_glink_top.glink_ip_rst_n ) // input wire [0:0] probe19
|
|
);
|
|
|
|
ila_glink_2 u_ila_glink_2 (
|
|
.clk (ps_clk ), // input wire clk
|
|
.probe0(u_glink_top.i_node_id ), // input wire [11:0] probe0
|
|
.probe1(u_glink_top.i_node_id_par ), // input wire [0:0] probe1
|
|
.probe2(u_glink_top.i_smartnc_2nd_cfg), // input wire [15:0] probe2
|
|
.probe3(u_glink_top.i_smartnc_3rd_cfg), // input wire [15:0] probe3
|
|
.probe4(u_glink_top.i_smartnt_cfg ) // input wire [15:0] probe4
|
|
);
|
|
|
|
ila_dma_fifo u_ila_dma_fifo (
|
|
.clk (glink_ip_clk ), // input wire clk
|
|
.probe0(glink_tx_fifo_tdata ), // input wire [15:0] probe0
|
|
.probe1(glink_tx_fifo_tlast ), // input wire [0:0] probe1
|
|
.probe2(glink_tx_fifo_tready), // input wire [0:0] probe2
|
|
.probe3(glink_tx_fifo_tvalid), // input wire [0:0] probe3
|
|
.probe4(glink_rx_fifo_tdata ), // input wire [15:0] probe4
|
|
.probe5(glink_rx_fifo_tlast ), // input wire [0:0] probe5
|
|
.probe6(glink_rx_fifo_tready), // input wire [0:0] probe6
|
|
.probe7(glink_rx_fifo_tvalid) // input wire [0:0] probe7
|
|
);
|
|
|
|
ila_beam u_ila_beam (
|
|
.clk (clk_beam_100m ), // input wire clk
|
|
.probe0 (clk_beam_12_5m ), // input wire [0:0] probe0
|
|
.probe1 (clk_beam_50m ), // input wire [0:0] probe1
|
|
.probe2 (beam_locked ), // input wire [0:0] probe2
|
|
.probe3 (beam_clk ), // input wire [0:0] probe3
|
|
.probe4 (data_out ), // input wire [0:0] probe4
|
|
.probe5 (en_out ), // input wire [0:0] probe5
|
|
.probe6 (dary_out ), // input wire [0:0] probe6
|
|
.probe7 (tr_out ), // input wire [0:0] probe7
|
|
.probe8 (CLK_TR ), // input wire [3:0] probe8
|
|
.probe9 (DATA_TR ), // input wire [3:0] probe9
|
|
.probe10(SYN_TR ), // input wire [3:0] probe10
|
|
.probe11(SEL_TR ), // input wire [3:0] probe11
|
|
.probe12(SEL1_TR ), // input wire [3:0] probe12
|
|
.probe13(SEL2_TR ), // input wire [3:0] probe13
|
|
.probe14(SEL3_TR ), // input wire [3:0] probe14
|
|
.probe15(SEL4_TR ), // input wire [3:0] probe15
|
|
.probe16(TR_TR ), // input wire [3:0] probe16
|
|
.probe17(T_DLY ), // input wire [0:0] probe17
|
|
.probe18(R_DLY ), // input wire [0:0] probe18
|
|
.probe19(debug_freq ), // input wire [15:0] probe19
|
|
.probe20(debug_freq_change), // input wire [0:0] probe20
|
|
.probe21(debug_tr_count ) // input wire [63:0] probe21
|
|
);
|
|
|
|
ila_en_creat_in u_ila_en_creat_in (
|
|
.clk (u_antenna_interface.clk_in ), // input wire clk
|
|
.probe0(u_antenna_interface.data_in ), // input wire [0:0] probe0
|
|
.probe1(u_antenna_interface.tr_in ), // input wire [0:0] probe1
|
|
.probe2(u_antenna_interface.dary_in ), // input wire [0:0] probe2
|
|
.probe3(u_antenna_interface.data_in_9 ), // input wire [8:0] probe0
|
|
.probe4(u_antenna_interface.rx_bitcnt ), // input wire [15:0] probe1
|
|
.probe5(u_antenna_interface.rx_state ), // input wire [3:0] probe4
|
|
.probe6(u_antenna_interface.recv_down ), // input wire [0:0] probe6
|
|
.probe7(u_antenna_interface.fifo_data_in), // input wire [0:0] probe8
|
|
.probe8(u_antenna_interface.fifo_wr_en ) // input wire [0:0] probe9
|
|
);
|
|
|
|
ila_en_creat_out u_ila_en_creat_out (
|
|
.clk (u_antenna_interface.clk_out ), // input wire clk
|
|
.probe0 (u_antenna_interface.en_out ), // input wire [0:0] probe0
|
|
.probe1 (u_antenna_interface.data_out ), // input wire [0:0] probe1
|
|
.probe2 (u_antenna_interface.tr_out ), // input wire [0:0] probe2
|
|
.probe3 (u_antenna_interface.dary_out ), // input wire [0:0] probe3
|
|
.probe4 (u_antenna_interface.tx_bitcnt ), // input wire [15:0] probe2
|
|
.probe5 (u_antenna_interface.rest_cnt ), // input wire [15:0] probe3
|
|
.probe6 (u_antenna_interface.tx_state ), // input wire [3:0] probe5
|
|
.probe7 (u_antenna_interface.recv_down_d3 ), // input wire [0:0] probe7
|
|
.probe8 (u_antenna_interface.data_out_reg ), // input wire [0:0] probe10
|
|
.probe9 (u_antenna_interface.fifo_rd_en ), // input wire [0:0] probe11
|
|
.probe10(u_antenna_interface.en_out_reg ), // input wire [0:0] probe12
|
|
.probe11(u_antenna_interface.beam_clk_reg ), // input wire [0:0] probe13
|
|
.probe12(u_antenna_interface.beam_clk_reg_d2) // input wire [0:0] probe14
|
|
);
|
|
|
|
|
|
endmodule
|