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change phase comp to cordic; combine some vios

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This commit is contained in:
josh
2023-06-15 18:39:46 +08:00
parent d7cca991f1
commit 0729aa40a3
150 changed files with 2488 additions and 5983 deletions
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projects/dl814_k7/dl814_k7_cal_coarse/rtl/rx_pre_process/rx_pre_process.v
+79 -80
View File
@@ -153,56 +153,17 @@ ad9361_phase_cal_coarse u_ad9361_phase_cal
////////////////////////////// Phase Compensation //////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// input data
// wire phase_comp_din_valid;
// wire [CHANNEL_NUM*PHASE_WIDTH-1 : 0] phase_comp_phase;
// wire [CHANNEL_NUM*ADC_DATA_WIDTH-1 : 0] phase_comp_din_real;
// wire [CHANNEL_NUM*ADC_DATA_WIDTH-1 : 0] phase_comp_din_imag;
wire phase_comp_din_valid;
wire [CHANNEL_NUM*PHASE_WIDTH-1 : 0] phase_comp_phase;
wire [CHANNEL_NUM*ADC_DATA_WIDTH-1 : 0] phase_comp_din_real;
wire [CHANNEL_NUM*ADC_DATA_WIDTH-1 : 0] phase_comp_din_imag;
// assign phase_comp_din_valid = ad9361_cal_valid;
// assign phase_comp_phase = {phase_ch4, phase_ch3, phase_ch2, phase_ch1};
// assign phase_comp_din_real = {rx_cal_ch4_i, rx_cal_ch3_i, rx_cal_ch2_i, rx_cal_ch1_i};
// assign phase_comp_din_imag = {rx_cal_ch4_q, rx_cal_ch3_q, rx_cal_ch2_q, rx_cal_ch1_q};
assign phase_comp_din_valid = ad9361_cal_valid;
assign phase_comp_phase = {phase_ch4, phase_ch3, phase_ch2, phase_ch1};
assign phase_comp_din_real = {rx_cal_ch4_i, rx_cal_ch3_i, rx_cal_ch2_i, rx_cal_ch1_i};
assign phase_comp_din_imag = {rx_cal_ch4_q, rx_cal_ch3_q, rx_cal_ch2_q, rx_cal_ch1_q};
// output data
wire phase_comp_dout_valid;
wire [CHANNEL_NUM*ADC_DATA_WIDTH-1:0] phase_comp_dout_real;
wire [CHANNEL_NUM*ADC_DATA_WIDTH-1:0] phase_comp_dout_imag;
// phase_comp #(
// .DATA_WIDTH (ADC_DATA_WIDTH ),
// .CORDIC_WIDTH (PHASE_WIDTH ),
// .CHANNEL_NUM (CHANNEL_NUM )
// ) u_phase_comp
// (
// // clock & reset
// .clk (sys_clk ),
// .rst (sys_rst ),
// // input data
// .din_valid (phase_comp_din_valid ),
// .phase (phase_comp_phase ),
// .din_real (phase_comp_din_real ),
// .din_imag (phase_comp_din_imag ),
// // output data
// .dout_valid (phase_comp_dout_valid ),
// .dout_real (phase_comp_dout_real ),
// .dout_imag (phase_comp_dout_imag )
// );
(*dont_touch = "true"*) wire [11:0] vio_sin_0;
(*dont_touch = "true"*) wire [11:0] vio_sin_1;
(*dont_touch = "true"*) wire [11:0] vio_sin_2;
(*dont_touch = "true"*) wire [11:0] vio_sin_3;
(*dont_touch = "true"*) wire [11:0] vio_cos_0;
(*dont_touch = "true"*) wire [11:0] vio_cos_1;
(*dont_touch = "true"*) wire [11:0] vio_cos_2;
(*dont_touch = "true"*) wire [11:0] vio_cos_3;
(*dont_touch = "true"*) wire [ 4:0] vio_trunc;
(*dont_touch = "true"*) wire trunc_overflow;
(*dont_touch = "true"*) wire [11:0] rx_comp_ch1_i;
(*dont_touch = "true"*) wire [11:0] rx_comp_ch1_q;
(*dont_touch = "true"*) wire [11:0] rx_comp_ch2_i;
@@ -212,45 +173,83 @@ wire [CHANNEL_NUM*ADC_DATA_WIDTH-1:0] phase_comp_dout_imag;
(*dont_touch = "true"*) wire [11:0] rx_comp_ch4_i;
(*dont_touch = "true"*) wire [11:0] rx_comp_ch4_q;
assign phase_comp_dout_valid = ad9361_cal_valid;
assign phase_comp_dout_real = {rx_comp_ch4_i, rx_comp_ch3_i, rx_comp_ch2_i, rx_comp_ch1_i};
assign phase_comp_dout_imag = {rx_comp_ch4_q, rx_comp_ch3_q, rx_comp_ch2_q, rx_comp_ch1_q};
wire phase_comp_dout_valid;
wire [CHANNEL_NUM*ADC_DATA_WIDTH-1:0] phase_comp_dout_real;
wire [CHANNEL_NUM*ADC_DATA_WIDTH-1:0] phase_comp_dout_imag;
phase_compensate u_phase_compensate
// assign phase_comp_dout_valid = ad9361_cal_valid;
assign {rx_comp_ch4_i, rx_comp_ch3_i, rx_comp_ch2_i, rx_comp_ch1_i} = phase_comp_dout_real;
assign {rx_comp_ch4_q, rx_comp_ch3_q, rx_comp_ch2_q, rx_comp_ch1_q} = phase_comp_dout_imag;
phase_comp #(
.DATA_WIDTH (ADC_DATA_WIDTH ),
.CORDIC_WIDTH (PHASE_WIDTH ),
.CHANNEL_NUM (CHANNEL_NUM )
) u_phase_comp
(
.clk (sys_clk ),
.rst (sys_rst ),
// clock & reset
.clk (sys_clk ),
.rst (sys_rst ),
.vio_sin_0 (vio_sin_0 ),
.vio_sin_1 (vio_sin_1 ),
.vio_sin_2 (vio_sin_2 ),
.vio_sin_3 (vio_sin_3 ),
.vio_cos_0 (vio_cos_0 ),
.vio_cos_1 (vio_cos_1 ),
.vio_cos_2 (vio_cos_2 ),
.vio_cos_3 (vio_cos_3 ),
// input data
.din_valid (phase_comp_din_valid ),
.phase (phase_comp_phase ),
.din_real (phase_comp_din_real ),
.din_imag (phase_comp_din_imag ),
.din_i_0 (rx_cal_ch1_i ),
.din_i_1 (rx_cal_ch2_i ),
.din_i_2 (rx_cal_ch3_i ),
.din_i_3 (rx_cal_ch4_i ),
.din_q_0 (rx_cal_ch1_q ),
.din_q_1 (rx_cal_ch2_q ),
.din_q_2 (rx_cal_ch3_q ),
.din_q_3 (rx_cal_ch4_q ),
.vio_trunc (vio_trunc ),
.dout_0_i (rx_comp_ch1_i ),
.dout_1_i (rx_comp_ch2_i ),
.dout_2_i (rx_comp_ch3_i ),
.dout_3_i (rx_comp_ch4_i ),
.dout_0_q (rx_comp_ch1_q ),
.dout_1_q (rx_comp_ch2_q ),
.dout_2_q (rx_comp_ch3_q ),
.dout_3_q (rx_comp_ch4_q ),
.trunc_overflow (trunc_overflow )
// output data
.dout_valid (phase_comp_dout_valid ),
.dout_real (phase_comp_dout_real ),
.dout_imag (phase_comp_dout_imag )
);
// (*dont_touch = "true"*) wire [11:0] vio_sin_0;
// (*dont_touch = "true"*) wire [11:0] vio_sin_1;
// (*dont_touch = "true"*) wire [11:0] vio_sin_2;
// (*dont_touch = "true"*) wire [11:0] vio_sin_3;
// (*dont_touch = "true"*) wire [11:0] vio_cos_0;
// (*dont_touch = "true"*) wire [11:0] vio_cos_1;
// (*dont_touch = "true"*) wire [11:0] vio_cos_2;
// (*dont_touch = "true"*) wire [11:0] vio_cos_3;
// (*dont_touch = "true"*) wire [ 4:0] vio_trunc;
// (*dont_touch = "true"*) wire trunc_overflow;
// phase_compensate u_phase_compensate
// (
// .clk (sys_clk ),
// .rst (sys_rst ),
// .vio_sin_0 (vio_sin_0 ),
// .vio_sin_1 (vio_sin_1 ),
// .vio_sin_2 (vio_sin_2 ),
// .vio_sin_3 (vio_sin_3 ),
// .vio_cos_0 (vio_cos_0 ),
// .vio_cos_1 (vio_cos_1 ),
// .vio_cos_2 (vio_cos_2 ),
// .vio_cos_3 (vio_cos_3 ),
// .din_i_0 (rx_cal_ch1_i ),
// .din_i_1 (rx_cal_ch2_i ),
// .din_i_2 (rx_cal_ch3_i ),
// .din_i_3 (rx_cal_ch4_i ),
// .din_q_0 (rx_cal_ch1_q ),
// .din_q_1 (rx_cal_ch2_q ),
// .din_q_2 (rx_cal_ch3_q ),
// .din_q_3 (rx_cal_ch4_q ),
// .vio_trunc (vio_trunc ),
// .dout_0_i (rx_comp_ch1_i ),
// .dout_1_i (rx_comp_ch2_i ),
// .dout_2_i (rx_comp_ch3_i ),
// .dout_3_i (rx_comp_ch4_i ),
// .dout_0_q (rx_comp_ch1_q ),
// .dout_1_q (rx_comp_ch2_q ),
// .dout_2_q (rx_comp_ch3_q ),
// .dout_3_q (rx_comp_ch4_q ),
// .trunc_overflow (trunc_overflow )
// );
////////////////////////////////////////////////////////////////////////////////
//////////////////////// Autocorrelation State Machine /////////////////////////
////////////////////////////////////////////////////////////////////////////////
projects/dl814_k7/dl814_k7_cal_coarse/rtl/rx_pre_process/rx_pre_test.v
+1 -1
View File
@@ -105,7 +105,7 @@ always @(posedge sys_clk_4x) begin
hop_flag_manual <= 'b0;
end
else if (ad9361_cal_valid_cdc) begin
if (~hop_trigger_d1 && hop_trigger) begin
if (hop_trigger_d1 ^ hop_trigger) begin
hop_flag_manual <= 1'b1;
end
else begin
projects/dl814_k7/dl814_k7_cal_coarse/rtl/system_top.v
+11 -22
View File
@@ -1002,30 +1002,19 @@ vio_manual_ctrl u_vio_manual_ctrl
.probe_out5 (rx_test_en ) // output wire [0 : 0] probe_out5
);
vio_hop u_vio_hop
(
.clk (sys_clk_4x ), // input wire clk
.probe_out0 (hop_trigger ), // output wire [0 : 0] probe_out1
.probe_out1 (hop_trigger_en ) // output wire [0 : 0] probe_out2
);
vio_phase_comp u_vio_phase_comp
(
.clk (sys_clk ), // input wire clk
.probe_in0 (var ), // output wire [31 : 0] probe_in0
.probe_in1 (var_cal_busy ), // output wire [0 : 0] probe_in1
.probe_in2 (u_rx_pre_process.trunc_overflow), // output wire [0 : 0] probe_in1
.probe_out0 (var_cal_start ), // output wire [0 : 0] probe_out0
.probe_out1 (cal_auto_en ), // output wire [0 : 0] probe_out1
.probe_out2 (u_rx_pre_process.vio_sin_0 ), // output wire [11 : 0] probe_out2
.probe_out3 (u_rx_pre_process.vio_sin_1 ), // output wire [11 : 0] probe_out3
.probe_out4 (u_rx_pre_process.vio_sin_2 ), // output wire [11 : 0] probe_out4
.probe_out5 (u_rx_pre_process.vio_sin_3 ), // output wire [11 : 0] probe_out5
.probe_out6 (u_rx_pre_process.vio_cos_0 ), // output wire [11 : 0] probe_out6
.probe_out7 (u_rx_pre_process.vio_cos_1 ), // output wire [11 : 0] probe_out7
.probe_out8 (u_rx_pre_process.vio_cos_2 ), // output wire [11 : 0] probe_out8
.probe_out9 (u_rx_pre_process.vio_cos_3 ), // output wire [11 : 0] probe_out9
.probe_out10(u_rx_pre_process.vio_trunc ) // output wire [4 : 0] probe_out10
.clk (sys_clk ), // input wire clk
.probe_in0 (var ), // output wire [31 : 0] probe_in0
.probe_in1 (var_cal_busy ), // output wire [0 : 0] probe_in1
.probe_out0 (var_cal_start ), // output wire [0 : 0] probe_out0
.probe_out1 (cal_auto_en ), // output wire [0 : 0] probe_out1
.probe_out2 (hop_trigger_en ), // output wire [0 : 0] probe_out2
.probe_out3 (hop_trigger ), // output wire [0 : 0] probe_out3
.probe_out4 (phase_ch1 ), // output wire [15 : 0] probe_out4
.probe_out5 (phase_ch2 ), // output wire [15 : 0] probe_out5
.probe_out6 (phase_ch3 ), // output wire [15 : 0] probe_out6
.probe_out7 (phase_ch4 ) // output wire [15 : 0] probe_out7
);
endmodule