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update online acq auto freq switch

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更新频点自动切换程序;修改频偏补偿的ILA输出,增加当前频点;修改接收数据ILA,增加当前频点和码相位计数器
This commit is contained in:
josh
2023-05-10 18:52:19 +08:00
parent 866b718eb3
commit 1083b3c7e3
208 changed files with 13944 additions and 1214 deletions
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projects/duifei/duifei_online_acq_par/rtl/rf_auto_switch_freq.v
+84 -15
View File
@@ -21,22 +21,27 @@
module rf_auto_switch_freq(
input clk ,
input rst ,
input clk ,
input rst ,
// vio control
input start , // rise-edge active, if start, change freq word to the first
input rf_ctrl_mode , // 1 : auto switch, 0 : manual switch
input switch_next_freq , // rise-edge active
input switch_last_freq , // rise-edge active
input [15:0] cnt_valid_to_switch , // clock number from valid to switch
input start , // rise-edge active, if start, change freq word to the first
input rf_ctrl_mode , // 1 : auto switch, 0 : manual switch
input switch_next_freq , // rise-edge active
input switch_last_freq , // rise-edge active
input [15:0] cnt_valid_to_switch , // clock number from valid to switch
input [15:0] cnt_switch_to_freq_start ,
input [31:0] cnt_sync_in ,
input [31:0] cnt_sync_in_high ,
// input
input [15:0] freq_hop_words_vio ,
input hop_words_valid_vio ,
input freq_hop_switch_vio ,
input sync_in , // rise-edge or down-edge active
input [15:0] freq_hop_words_vio ,
input hop_words_valid_vio ,
input freq_hop_switch_vio ,
// output
output reg [15:0] freq_hop_words_auto = 11'd0 ,
output reg hop_words_valid_auto = 1'd0 ,
output reg freq_hop_switch_auto = 1'd0
output reg [15:0] freq_hop_words_auto = 11'd0,
output reg hop_words_valid_auto = 1'd0 ,
output reg freq_hop_switch_auto = 1'd0 ,
output reg freq_comp_start = 1'b0 // rise-edge or down-edge active
);
//************************* rise-edge detect ***********************************
@@ -73,6 +78,46 @@ always @ (posedge clk)
switch_last_freq_pulse[0] <= switch_last_freq_d1 & ~switch_last_freq_d2;
switch_last_freq_pulse[9:1] <= switch_last_freq_pulse[8:0];
end
//*********************** sync signal detect ***********************************
reg sync_in_reg = 1'b0;
reg [31:0] sync_in_cnt = 32'd0;
reg sync_in_high_cnt = 32'd0;
reg sync_in_valid = 1'b0;
reg sync_in_valid_d1 = 1'b0;
always @ (posedge clk)
if(rst | start_pulse) begin
sync_in_cnt <= 32'd0;
sync_in_high_cnt <= 32'd0;
end else if(sync_in_cnt == cnt_sync_in) begin
sync_in_cnt <= 32'd0;
sync_in_high_cnt <= 32'd0;
end else if(sync_in == 1'b1) begin
sync_in_cnt <= sync_in_cnt + 1'b1;
sync_in_high_cnt <= sync_in_high_cnt + 1'b1;
end else begin
sync_in_cnt <= sync_in_cnt + 1'b1;
end
always @ (posedge clk)
if(rst | start_pulse)
sync_in_reg <= 1'b0;
else if(sync_in_cnt == cnt_sync_in && sync_in_high_cnt > cnt_sync_in_high)
sync_in_reg <= 1'b1;
else if(sync_in_cnt == cnt_sync_in)
sync_in_reg <= 1'b0;
always @ (posedge clk)
if(rst | start_pulse)
sync_in_valid <= 1'b0;
else if(sync_in_reg != sync_in_valid)
sync_in_valid <= ~sync_in_valid;
always @ (posedge clk)
if(rst | start_pulse)
sync_in_valid_d1 <= 1'b0;
else
sync_in_valid_d1 <= sync_in_valid;
//******************** local freq word control *********************************
reg [15:0] local_freq_word = 16'd0;
@@ -89,13 +134,17 @@ rom_freq_word rom_freq_word_inst(
always @ (posedge clk)
if(rst | start_pulse)
freq_word_cnt <= 8'd0;
freq_word_cnt <= 8'd80;
else if(freq_word_cnt == 8'd80 && switch_next_freq_pulse[0])
freq_word_cnt <= 8'd0;
else if(freq_word_cnt == 8'd80 && sync_in_valid != sync_in_valid_d1)
freq_word_cnt <= 8'd0;
else if(freq_word_cnt == 8'd0 && switch_last_freq_pulse[0])
freq_word_cnt <= 8'd80;
else if(switch_next_freq_pulse[0])
freq_word_cnt <= freq_word_cnt + 1'b1;
else if(sync_in_valid != sync_in_valid_d1)
freq_word_cnt <= freq_word_cnt + 1'b1;
else if(switch_last_freq_pulse[0])
freq_word_cnt <= freq_word_cnt - 1'b1;
else
@@ -104,7 +153,7 @@ always @ (posedge clk)
always @ (posedge clk)
if(rst | start_pulse)
local_freq_word_valid <= 1'b0;
else if(switch_next_freq_pulse[4] | switch_last_freq_pulse[4])
else if(switch_next_freq_pulse[4] | switch_last_freq_pulse[4] | sync_in_valid != sync_in_valid_d1)
local_freq_word_valid <= 1'b1;
else
local_freq_word_valid <= 1'b0;
@@ -164,4 +213,24 @@ always @ (posedge clk)
else
freq_hop_switch_auto <= freq_hop_switch_vio;
// freq_comp_start
reg [15:0] freq_comp_start_cnt = 16'd0;
always @ (posedge clk)
if(rst | start_pulse)
freq_comp_start_cnt <= 16'd0;
else if(freq_comp_start_cnt == cnt_switch_to_freq_start)
freq_comp_start_cnt <= 16'd0;
else if(freq_word_valid_cnt == cnt_valid_to_switch)
freq_comp_start_cnt <= freq_comp_start_cnt + 1'b1;
else if(freq_comp_start_cnt != 16'd0)
freq_comp_start_cnt <= freq_comp_start_cnt + 1'b1;
else
freq_comp_start_cnt <= freq_comp_start_cnt;
always @ (posedge clk)
if(rst | start_pulse)
freq_comp_start <= 1'b0;
else if(freq_comp_start_cnt == cnt_switch_to_freq_start)
freq_comp_start <= ~freq_comp_start;
endmodule
projects/duifei/duifei_online_acq_par/rtl/system_top.v
+59 -30
View File
@@ -419,30 +419,39 @@ wire rf_ctrl_mode_vio ;
wire switch_next_freq_vio;
wire switch_last_freq_vio;
wire [15:0] cnt_valid_to_switch_vio;
wire [15:0] cnt_switch_to_freq_start_vio;
wire [31:0] cnt_sync_in_vio;
wire [31:0] cnt_sync_in_high_vio;
(*dont_touch = "true"*) wire vio_switch;
(*dont_touch = "true"*) wire vio_switch_auto;
(*dont_touch = "true"*) wire [15:0] vio_frequency;
(*dont_touch = "true"*) wire [15:0] vio_frequency_auto;
wire hop_words_valid_auto;
wire freq_comp_start_auto ;
rf_auto_switch_freq u_rf_auto_switch_freq(
.clk (clk_48m ),
.rst (sys_rst ),
.clk (clk_48m ),
.rst (sys_rst ),
// vio control
.start (rf_auto_start_vio ), // rise-edge active, if start, change freq word to the first
.rf_ctrl_mode (rf_ctrl_mode_vio ), // 1 : auto switch, 0 : manual switch
.switch_next_freq (switch_next_freq_vio ), // rise-edge active
.switch_last_freq (switch_last_freq_vio ), // rise-edge active
.cnt_valid_to_switch (cnt_valid_to_switch_vio ),
.start (rf_auto_start_vio ), // rise-edge active, if start, change freq word to the first
.rf_ctrl_mode (rf_ctrl_mode_vio ), // 1 : auto switch, 0 : manual switch
.switch_next_freq (switch_next_freq_vio ), // rise-edge active
.switch_last_freq (switch_last_freq_vio ), // rise-edge active
.cnt_valid_to_switch (cnt_valid_to_switch_vio ),
.cnt_switch_to_freq_start (cnt_switch_to_freq_start_vio ),
.cnt_sync_in (cnt_sync_in_vio[31:0] ),
.cnt_sync_in_high (cnt_sync_in_high_vio[31:0] ),
// input
.freq_hop_words_vio (vio_frequency[15:0] ),
.hop_words_valid_vio (1'b0 ),
.freq_hop_switch_vio (vio_switch ),
.sync_in (debug_io_3 ),
.freq_hop_words_vio (vio_frequency[15:0] ),
.hop_words_valid_vio (1'b0 ),
.freq_hop_switch_vio (vio_switch ),
// output
.freq_hop_words_auto (vio_frequency_auto[15:0] ),
.hop_words_valid_auto (hop_words_valid_auto ),
.freq_hop_switch_auto (vio_switch_auto )
.freq_hop_words_auto (vio_frequency_auto[15:0] ),
.hop_words_valid_auto (hop_words_valid_auto ),
.freq_hop_switch_auto (vio_switch_auto ),
.freq_comp_start (freq_comp_start_auto )
);
ant_rf_ctrl u_ant_rf_ctrl
@@ -664,6 +673,8 @@ ad9361_phase_cal_coarse u_ad9361_phase_cal
// <----------------------- insert receiver logic below ----------------------->
// <--------------------------------------------------------------------------->
wire freq_comp_start ;
wire freq_comp_auto_enable_vio;
wire freq_comp_start_vio;
wire freq_comp_busy ;
wire [7:0] dmf_num_per_ch ;
wire [31:0] freq_manual ;
@@ -689,6 +700,8 @@ wire [17:0] ch4_peak_value_i ;
wire [17:0] ch4_peak_value_q ;
wire [ 9:0] ch4_peak_index ;
assign freq_comp_start = (freq_comp_auto_enable_vio == 1'b1) ? freq_comp_start_auto : freq_comp_start_vio;
freq_comp #(
.FREQ_WORD_LOWER (-4194304 ),
.FREQ_WORD_UPPER (4194303 ),
@@ -747,7 +760,16 @@ freq_comp #(
.ch4_peak_index (ch4_peak_index ) // output reg [$clog2(PRBS_POS-1) : 0] ch4_peak_index
);
reg [9:0] chip_cnt = 'b0;
always @(posedge sys_clk) begin
if (sys_rst) begin
chip_cnt <= 'b0;
end
else begin
chip_cnt <= chip_cnt + 1'b1;
end
end
////////////////////////////////////////////////////////////////////////////////
//////////////////////////////// ILAs and VIOs /////////////////////////////////
@@ -780,7 +802,11 @@ vio_rfcontrl u_vio_rfcontrl
.probe_out15(switch_next_freq_vio ), // output wire [0 : 0] probe_out15
.probe_out16(switch_last_freq_vio ), // output wire [0 : 0] probe_out16
.probe_out17(cnt_valid_to_switch_vio[15:0] ), // output wire [15: 0] probe_out17
.probe_in0 (vio_frequency_auto[15:0] ) // input wire [10: 0] probe_in0
.probe_out18(cnt_switch_to_freq_start_vio[15:0] ), // output wire [15: 0] probe_out18
.probe_out19(cnt_sync_in_vio[31:0] ), // output wire [31: 0] probe_out19
.probe_out20(cnt_sync_in_high_vio[31:0] ), // output wire [31: 0] probe_out20
.probe_in0 (vio_frequency_auto[15:0] ), // input wire [15: 0] probe_in0
.probe_in1 (debug_io_3 ) // input wire [0: 0] probe_in1
);
vio_ant_test u_vio_ant_test
@@ -896,17 +922,19 @@ ila_2x12x1024 u_ila_tx
.probe1 (tx_ch1_q ) // input wire [11:0] probe1
);
ila_8x12x8192 u_ila_rx
ila_rx_data_cnt u_ila_rx
(
.clk (sys_clk ), // input wire clk
.probe0 (rx_cal_ch1_i ), // input wire [11:0] probe0
.probe1 (rx_cal_ch1_q ), // input wire [11:0] probe1
.probe2 (rx_cal_ch2_i ), // input wire [11:0] probe2
.probe3 (rx_cal_ch2_q ), // input wire [11:0] probe3
.probe4 (rx_cal_ch3_i ), // input wire [11:0] probe4
.probe5 (rx_cal_ch3_q ), // input wire [11:0] probe5
.probe6 (rx_cal_ch4_i ), // input wire [11:0] probe6
.probe7 (rx_cal_ch4_q ) // input wire [11:0] probe7
.clk (sys_clk ), // input wire clk
.probe0 (rx_cal_ch1_i ), // input wire [11:0] probe0
.probe1 (rx_cal_ch1_q ), // input wire [11:0] probe1
.probe2 (rx_cal_ch2_i ), // input wire [11:0] probe2
.probe3 (rx_cal_ch2_q ), // input wire [11:0] probe3
.probe4 (rx_cal_ch3_i ), // input wire [11:0] probe4
.probe5 (rx_cal_ch3_q ), // input wire [11:0] probe5
.probe6 (rx_cal_ch4_i ), // input wire [11:0] probe6
.probe7 (rx_cal_ch4_q ), // input wire [11:0] probe7
.probe8 (vio_frequency_auto[11:0] ), // input wire [11:0] probe8
.probe9 (chip_cnt ) // input wire [9:0] probe9
);
ila_cal u_ila_cal
@@ -941,12 +969,13 @@ vio_manual_ctrl u_vio_manual_ctrl
vio_freq_comp u_vio_freq_comp
(
.clk (sys_clk ), // input wire clk
.probe_in0 (freq_comp_busy ), // input wire [0 : 0] probe_in0
.probe_out0 (freq_comp_start ), // output wire [0 : 0] probe_out0
.probe_out1 (dmf_num_per_ch ), // output wire [7 : 0] probe_out1
.probe_out2 (freq_manual_en ), // output wire [0 : 0] probe_out2
.probe_out3 (freq_manual ) // output wire [31 : 0] probe_out3
.clk (sys_clk ), // input wire clk
.probe_in0 (freq_comp_busy ), // input wire [0 : 0] probe_in0
.probe_out0 (freq_comp_start_vio ), // output wire [0 : 0] probe_out0
.probe_out1 (dmf_num_per_ch ), // output wire [7 : 0] probe_out1
.probe_out2 (freq_manual_en ), // output wire [0 : 0] probe_out2
.probe_out3 (freq_manual ), // output wire [31 : 0] probe_out3
.probe_out4 (freq_comp_auto_enable_vio ) // output wire [0 : 0] probe_out4
);
ila_freq_comp u_ila_freq_comp