update online acq auto freq switch

更新频点自动切换程序;修改频偏补偿的ILA输出,增加当前频点;修改接收数据ILA,增加当前频点和码相位计数器
2023-05-10 18:52:19 +08:00
parent 866b718eb3
commit 1083b3c7e3
208 changed files with 13944 additions and 1214 deletions
@@ -1,6 +1,6 @@
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@@ -1,12 +1,12 @@
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@@ -1,3 +1,3 @@
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@@ -3,7 +3,7 @@
 <!--The data in this file is primarily intended for consumption by Xilinx tools.
 The structure and the elements are likely to change over the next few releases.
 This means code written to parse this file will need to be revisited each subsequent release.-->
-<application name="pa" timeStamp="Mon May  8 17:50:26 2023">
+<application name="pa" timeStamp="Wed May 10 12:58:54 2023">
 <section name="Project Information" visible="false">
 <property name="ProjectID" value="ce818763e31a4de8ac7850431f15fb5a" type="ProjectID"/>
 <property name="ProjectIteration" value="1" type="ProjectIteration"/>
@@ -18,19 +18,19 @@ This means code written to parse this file will need to be revisited each subseq
 </item>
 <item name="Java Command Handlers">
 <property name="AddExistingIPHandler" value="9" type="JavaHandler"/>
-<property name="CloseProject" value="11" type="JavaHandler"/>
+<property name="CloseProject" value="12" type="JavaHandler"/>
 <property name="CopyIPHandler" value="7" type="JavaHandler"/>
 <property name="CustomizeCore" value="14" type="JavaHandler"/>
 <property name="EditDelete" value="14" type="JavaHandler"/>
 <property name="ManageCompositeTargets" value="4" type="JavaHandler"/>
 <property name="NewIPLocationHandler" value="1" type="JavaHandler"/>
 <property name="OpenIPLocationHandler" value="3" type="JavaHandler"/>
-<property name="OpenPreviousIPHandler" value="17" type="JavaHandler"/>
+<property name="OpenPreviousIPHandler" value="18" type="JavaHandler"/>
 <property name="RecustomizeCore" value="77" type="JavaHandler"/>
 </item>
 <item name="Gui Handlers">
 <property name="BaseDialog_CANCEL" value="31" type="GuiHandlerData"/>
-<property name="BaseDialog_OK" value="81" type="GuiHandlerData"/>
+<property name="BaseDialog_OK" value="82" type="GuiHandlerData"/>
 <property name="CmdMsgDialog_OK" value="6" type="GuiHandlerData"/>
 <property name="CommandsInput_TYPE_TCL_COMMAND_HERE" value="2" type="GuiHandlerData"/>
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@@ -44,33 +44,34 @@ This means code written to parse this file will need to be revisited each subseq
 <property name="HJFileChooserHelpers_JUMP_TO_RECENT_PROJECT_DIRECTORY" value="2" type="GuiHandlerData"/>
 <property name="IPCoreView_TABBED_PANE" value="2" type="GuiHandlerData"/>
 <property name="MainMenuMgr_EXPORT" value="1" type="GuiHandlerData"/>
-<property name="MainMenuMgr_FILE" value="22" type="GuiHandlerData"/>
+<property name="MainMenuMgr_FILE" value="24" type="GuiHandlerData"/>
 <property name="MainMenuMgr_IP" value="2" type="GuiHandlerData"/>
 <property name="MainMenuMgr_OPEN_RECENT_PROJECT" value="2" type="GuiHandlerData"/>
-<property name="MainMenuMgr_PROJECT" value="12" type="GuiHandlerData"/>
+<property name="MainMenuMgr_PROJECT" value="13" type="GuiHandlerData"/>
 <property name="MainMenuMgr_TEXT_EDITOR" value="2" type="GuiHandlerData"/>
 <property name="MsgView_CLEAR_MESSAGES_RESULTING_FROM_USER_EXECUTED" value="1" type="GuiHandlerData"/>
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-<property name="PACommandNames_CLOSE_PROJECT" value="11" type="GuiHandlerData"/>
+<property name="PACommandNames_CLOSE_PROJECT" value="12" type="GuiHandlerData"/>
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 <property name="PACommandNames_GENERATE_COMPOSITE_FILE" value="4" type="GuiHandlerData"/>
 <property name="PACommandNames_OPEN_IP_LOCATION" value="3" type="GuiHandlerData"/>
+<property name="ProgressDialog_CANCEL" value="1" type="GuiHandlerData"/>
 <property name="RemoveSourcesDialog_ALSO_DELETE" value="12" type="GuiHandlerData"/>
 <property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="48" type="GuiHandlerData"/>
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 <property name="SrcMenu_IP_DOCUMENTATION" value="7" type="GuiHandlerData"/>
-<property name="SyntheticaGettingStartedView_RECENT_IP_LOCATIONS" value="20" type="GuiHandlerData"/>
+<property name="SyntheticaGettingStartedView_RECENT_IP_LOCATIONS" value="21" type="GuiHandlerData"/>
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 <property name="BatchMode" value="0" type="BatchMode"/>
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+<property name="TclMode" value="87" type="TclMode"/>
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@@ -0,0 +1,78 @@
+// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+// DO NOT MODIFY THIS FILE.
+
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+
+ila_rx_data_cnt your_instance_name (
+	.clk(clk), // input wire clk
+
+
+	.probe0(probe0), // input wire [11:0]  probe0  
+	.probe1(probe1), // input wire [11:0]  probe1 
+	.probe2(probe2), // input wire [11:0]  probe2 
+	.probe3(probe3), // input wire [11:0]  probe3 
+	.probe4(probe4), // input wire [11:0]  probe4 
+	.probe5(probe5), // input wire [11:0]  probe5 
+	.probe6(probe6), // input wire [11:0]  probe6 
+	.probe7(probe7), // input wire [11:0]  probe7 
+	.probe8(probe8), // input wire [11:0]  probe8 
+	.probe9(probe9) // input wire [9:0]  probe9
+);
+
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file ila_rx_data_cnt when simulating
+// the core, ila_rx_data_cnt. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+
+
@@ -0,0 +1,31 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+// Date        : Wed May 10 18:23:01 2023
+// Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
+// Command     : write_verilog -force -mode synth_stub
+//               /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.v
+// Design      : ila_rx_data_cnt
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z100ffg900-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* X_CORE_INFO = "ila,Vivado 2019.1.3" *)
+module ila_rx_data_cnt(clk, probe0, probe1, probe2, probe3, probe4, probe5, 
+  probe6, probe7, probe8, probe9)
+/* synthesis syn_black_box black_box_pad_pin="clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0],probe8[11:0],probe9[9:0]" */;
+  input clk;
+  input [11:0]probe0;
+  input [11:0]probe1;
+  input [11:0]probe2;
+  input [11:0]probe3;
+  input [11:0]probe4;
+  input [11:0]probe5;
+  input [11:0]probe6;
+  input [11:0]probe7;
+  input [11:0]probe8;
+  input [9:0]probe9;
+endmodule
@@ -0,0 +1,40 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+-- Date        : Wed May 10 18:23:01 2023
+-- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
+-- Command     : write_vhdl -force -mode synth_stub
+--               /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.vhdl
+-- Design      : ila_rx_data_cnt
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7z100ffg900-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity ila_rx_data_cnt is
+  Port ( 
+    clk : in STD_LOGIC;
+    probe0 : in STD_LOGIC_VECTOR ( 11 downto 0 );
+    probe1 : in STD_LOGIC_VECTOR ( 11 downto 0 );
+    probe2 : in STD_LOGIC_VECTOR ( 11 downto 0 );
+    probe3 : in STD_LOGIC_VECTOR ( 11 downto 0 );
+    probe4 : in STD_LOGIC_VECTOR ( 11 downto 0 );
+    probe5 : in STD_LOGIC_VECTOR ( 11 downto 0 );
+    probe6 : in STD_LOGIC_VECTOR ( 11 downto 0 );
+    probe7 : in STD_LOGIC_VECTOR ( 11 downto 0 );
+    probe8 : in STD_LOGIC_VECTOR ( 11 downto 0 );
+    probe9 : in STD_LOGIC_VECTOR ( 9 downto 0 )
+  );
+
+end ila_rx_data_cnt;
+
+architecture stub of ila_rx_data_cnt is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0],probe8[11:0],probe9[9:0]";
+attribute X_CORE_INFO : string;
+attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3";
+begin
+end;
@@ -0,0 +1,80 @@
+// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+// DO NOT MODIFY THIS FILE.
+`timescale 1ns / 1ps
+module ila_rx_data_cnt (
+clk,
+
+
+probe0,
+probe1,
+probe2,
+probe3,
+probe4,
+probe5,
+probe6,
+probe7,
+probe8,
+probe9
+);
+
+input clk;
+
+
+input [11 : 0] probe0;
+input [11 : 0] probe1;
+input [11 : 0] probe2;
+input [11 : 0] probe3;
+input [11 : 0] probe4;
+input [11 : 0] probe5;
+input [11 : 0] probe6;
+input [11 : 0] probe7;
+input [11 : 0] probe8;
+input [9 : 0] probe9;
+
+
+endmodule
@@ -1,283 +0,0 @@
-`pragma protect begin_protected
-`pragma protect version = 1
-`pragma protect encrypt_agent = "XILINX"
-`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1"
-`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
-`pragma protect key_block
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-
-`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
-`pragma protect key_block
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-
-`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
-`pragma protect key_block
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-
-`pragma protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
-`pragma protect key_block
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-`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
-`pragma protect key_block
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-
-`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
-`pragma protect key_block
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-`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
-`pragma protect key_block
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-`pragma protect data_method = "AES128-CBC"
-`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12464)
-`pragma protect data_block
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-`pragma protect end_protected
@@ -52,7 +52,8 @@ probe_in0,
 probe_out0,
 probe_out1,
 probe_out2,
-probe_out3
+probe_out3,
+probe_out4
 );

 input clk;
@@ -62,6 +63,7 @@ output reg [0 : 0] probe_out0 = 'h0 ;
 output reg [7 : 0] probe_out1 = 'h0A ;
 output reg [0 : 0] probe_out2 = 'h0 ;
 output reg [31 : 0] probe_out3 = 'h00000000 ;
+output reg [0 : 0] probe_out4 = 'h0 ;


 endmodule
@@ -60,7 +60,8 @@ vio_freq_comp your_instance_name (
  .probe_out0(probe_out0),  // output wire [0 : 0] probe_out0
  .probe_out1(probe_out1),  // output wire [7 : 0] probe_out1
  .probe_out2(probe_out2),  // output wire [0 : 0] probe_out2
-  .probe_out3(probe_out3)  // output wire [31 : 0] probe_out3
+  .probe_out3(probe_out3),  // output wire [31 : 0] probe_out3
+  .probe_out4(probe_out4)  // output wire [0 : 0] probe_out4
 );
 // INST_TAG_END ------ End INSTANTIATION Template ---------

@@ -59,7 +59,8 @@ COMPONENT vio_freq_comp
    probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    probe_out1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
    probe_out2 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
-    probe_out3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+    probe_out3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    probe_out4 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
  );
 END COMPONENT;
 -- COMP_TAG_END ------ End COMPONENT Declaration ------------
@@ -75,7 +76,8 @@ your_instance_name : vio_freq_comp
    probe_out0 => probe_out0,
    probe_out1 => probe_out1,
    probe_out2 => probe_out2,
-    probe_out3 => probe_out3
+    probe_out3 => probe_out3,
+    probe_out4 => probe_out4
  );
 -- INST_TAG_END ------ End INSTANTIATION Template ---------

@@ -1,10 +1,10 @@
 // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 // --------------------------------------------------------------------------------
 // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
-// Date        : Mon May  8 13:15:24 2023
+// Date        : Wed May 10 18:23:14 2023
 // Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
 // Command     : write_verilog -force -mode synth_stub
-//               /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.v
+//               /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.v
 // Design      : vio_freq_comp
 // Purpose     : Stub declaration of top-level module interface
 // Device      : xc7z100ffg900-2
@@ -15,12 +15,13 @@
 // Please paste the declaration into a Verilog source file or add the file as an additional source.
 (* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
 module vio_freq_comp(clk, probe_in0, probe_out0, probe_out1, 
-  probe_out2, probe_out3)
-/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_out0[0:0],probe_out1[7:0],probe_out2[0:0],probe_out3[31:0]" */;
+  probe_out2, probe_out3, probe_out4)
+/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_out0[0:0],probe_out1[7:0],probe_out2[0:0],probe_out3[31:0],probe_out4[0:0]" */;
  input clk;
  input [0:0]probe_in0;
  output [0:0]probe_out0;
  output [7:0]probe_out1;
  output [0:0]probe_out2;
  output [31:0]probe_out3;
+  output [0:0]probe_out4;
 endmodule
@@ -1,10 +1,10 @@
 -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 -- --------------------------------------------------------------------------------
 -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
-- Date        : Mon May  8 13:15:24 2023
+-- Date        : Wed May 10 18:23:14 2023
 -- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
 -- Command     : write_vhdl -force -mode synth_stub
--               /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.vhdl
+--               /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.vhdl
 -- Design      : vio_freq_comp
 -- Purpose     : Stub declaration of top-level module interface
 -- Device      : xc7z100ffg900-2
@@ -19,7 +19,8 @@ entity vio_freq_comp is
    probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    probe_out1 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 );
-    probe_out3 : out STD_LOGIC_VECTOR ( 31 downto 0 )
+    probe_out3 : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    probe_out4 : out STD_LOGIC_VECTOR ( 0 to 0 )
  );

 end vio_freq_comp;
@@ -28,7 +29,7 @@ architecture stub of vio_freq_comp is
 attribute syn_black_box : boolean;
 attribute black_box_pad_pin : string;
 attribute syn_black_box of stub : architecture is true;
-attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[0:0],probe_out0[0:0],probe_out1[7:0],probe_out2[0:0],probe_out3[31:0]";
+attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[0:0],probe_out0[0:0],probe_out1[7:0],probe_out2[0:0],probe_out3[31:0],probe_out4[0:0]";
 attribute X_CORE_INFO : string;
 attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
 begin
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-HzIaED7RvsGxFpR26+1akJ1/8bReaeZFhca9QQVHRvj1X698r4C/XUsrSc+05XtjMx6HM5q1yZwu
-pU7X3s5l0gEMjqTKe4cxHPW2hjvKhiEEb66pzjN7HK0y5nrjMJxzwtfqbNV7b76TcDtX27W08c9U
-hsEprM3gDA7yAWiwAy3nxW57jdofbM5LfU0HVc1mK3FN0pfA/Fg0HWk0RX6K1vbYorZ2YFYwkpIK
-Spx8l1Y/4Kpd/0yvO9c4f8OcsEc6LfaQSV83l2H8v6NalHbhaZ2gKxmDZi/k03xDyL8v6GCn18bp
-dB5LUUJUKbnsl6q5E9b8DkJqSnAaHRLJDnEvMp6EfGlpc52On3lCg0wI5XERerziamjcMH44VZfd
-j8z1WUyHlyOSmkvZdJ66PfYWu5BxCG7hfdtSGROPtIxs36iLmesyYm4yHKwwbWgNIrLgra92DF2L
-R6e0RM1WWkcJHei4v89Nmwym4k0dKMTX1HkfTogoprrdIyDYj4qMmeTqfl0U8pRehVs6/zy4x8HS
-0V2+smFFQ/BZxLQ4eV8NHKeszc4kI6jJ3OCncsP57tfkE6TmVTtWKiimERISYB4KhUpblsbN6zyX
-Bni5ezNwl9XdaBq9c90k+QQmaMGeyQbczdGy9ufcC269vB1FU5+a67Ew8h0jPAPeYHvsw4kGsTSh
-xnhGNUHRuPoNmQYBjI2LztvnbGuoucUVntUi5quKpKAK1fOZerZTh+kr5PjaW0YlozpL5CtElvS3
-eqqkVT8a5mdW+sWTxJxTjqronag0QACsSwbA9qurCW9IdcOO+0D7nzfIJIFrWKx+D71JhKNvOmUa
-NmCy9l+wzdpcLs1zvS3o3zwEgUWOOHzITgzOxtDhIuBcJkg9lS+o5b+W+U9fplCbVFjYd5ZDa2sX
-90/8XCJA0a9VcsSrh1LoO0V3YX80VWdNPY79OUOlqftl3rNXVXE=
-`pragma protect end_protected
@@ -48,7 +48,7 @@
 `timescale 1ns / 1ps
 module vio_rfcontrl (
 clk,
-probe_in0,
+probe_in0,probe_in1,
 probe_out0,
 probe_out1,
 probe_out2,
@@ -66,11 +66,15 @@ probe_out13,
 probe_out14,
 probe_out15,
 probe_out16,
-probe_out17
+probe_out17,
+probe_out18,
+probe_out19,
+probe_out20
 );

 input clk;
 input [15 : 0] probe_in0;
+input [0 : 0] probe_in1;

 output reg [0 : 0] probe_out0 = 'h0 ;
 output reg [0 : 0] probe_out1 = 'h0 ;
@@ -90,6 +94,9 @@ output reg [0 : 0] probe_out14 = 'h0 ;
 output reg [0 : 0] probe_out15 = 'h0 ;
 output reg [0 : 0] probe_out16 = 'h0 ;
 output reg [15 : 0] probe_out17 = 'h0000 ;
+output reg [15 : 0] probe_out18 = 'h0000 ;
+output reg [31 : 0] probe_out19 = 'h00000000 ;
+output reg [31 : 0] probe_out20 = 'h00000000 ;


 endmodule
@@ -57,6 +57,7 @@
 vio_rfcontrl your_instance_name (
  .clk(clk),                  // input wire clk
  .probe_in0(probe_in0),      // input wire [15 : 0] probe_in0
+  .probe_in1(probe_in1),      // input wire [0 : 0] probe_in1
  .probe_out0(probe_out0),    // output wire [0 : 0] probe_out0
  .probe_out1(probe_out1),    // output wire [0 : 0] probe_out1
  .probe_out2(probe_out2),    // output wire [15 : 0] probe_out2
@@ -74,7 +75,10 @@ vio_rfcontrl your_instance_name (
  .probe_out14(probe_out14),  // output wire [0 : 0] probe_out14
  .probe_out15(probe_out15),  // output wire [0 : 0] probe_out15
  .probe_out16(probe_out16),  // output wire [0 : 0] probe_out16
-  .probe_out17(probe_out17)  // output wire [15 : 0] probe_out17
+  .probe_out17(probe_out17),  // output wire [15 : 0] probe_out17
+  .probe_out18(probe_out18),  // output wire [15 : 0] probe_out18
+  .probe_out19(probe_out19),  // output wire [31 : 0] probe_out19
+  .probe_out20(probe_out20)  // output wire [31 : 0] probe_out20
 );
 // INST_TAG_END ------ End INSTANTIATION Template ---------

@@ -56,6 +56,7 @@ COMPONENT vio_rfcontrl
  PORT (
    clk : IN STD_LOGIC;
    probe_in0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+    probe_in1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    probe_out1 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    probe_out2 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
@@ -73,7 +74,10 @@ COMPONENT vio_rfcontrl
    probe_out14 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    probe_out15 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    probe_out16 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
-    probe_out17 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+    probe_out17 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+    probe_out18 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+    probe_out19 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    probe_out20 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
  );
 END COMPONENT;
 -- COMP_TAG_END ------ End COMPONENT Declaration ------------
@@ -86,6 +90,7 @@ your_instance_name : vio_rfcontrl
  PORT MAP (
    clk => clk,
    probe_in0 => probe_in0,
+    probe_in1 => probe_in1,
    probe_out0 => probe_out0,
    probe_out1 => probe_out1,
    probe_out2 => probe_out2,
@@ -103,7 +108,10 @@ your_instance_name : vio_rfcontrl
    probe_out14 => probe_out14,
    probe_out15 => probe_out15,
    probe_out16 => probe_out16,
-    probe_out17 => probe_out17
+    probe_out17 => probe_out17,
+    probe_out18 => probe_out18,
+    probe_out19 => probe_out19,
+    probe_out20 => probe_out20
  );
 -- INST_TAG_END ------ End INSTANTIATION Template ---------

@@ -1,10 +1,10 @@
 // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 // --------------------------------------------------------------------------------
 // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
-// Date        : Mon May  8 13:15:25 2023
+// Date        : Wed May 10 18:20:13 2023
 // Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
 // Command     : write_verilog -force -mode synth_stub
-//               /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.v
+//               /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.v
 // Design      : vio_rfcontrl
 // Purpose     : Stub declaration of top-level module interface
 // Device      : xc7z100ffg900-2
@@ -14,13 +14,14 @@
 // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
 // Please paste the declaration into a Verilog source file or add the file as an additional source.
 (* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
-module vio_rfcontrl(clk, probe_in0, probe_out0, probe_out1, 
-  probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9, 
-  probe_out10, probe_out11, probe_out12, probe_out13, probe_out14, probe_out15, probe_out16, 
-  probe_out17)
-/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[15:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[15:0]" */;
+module vio_rfcontrl(clk, probe_in0, probe_in1, probe_out0, 
+  probe_out1, probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, 
+  probe_out9, probe_out10, probe_out11, probe_out12, probe_out13, probe_out14, probe_out15, 
+  probe_out16, probe_out17, probe_out18, probe_out19, probe_out20)
+/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[15:0],probe_in1[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[15:0],probe_out18[15:0],probe_out19[31:0],probe_out20[31:0]" */;
  input clk;
  input [15:0]probe_in0;
+  input [0:0]probe_in1;
  output [0:0]probe_out0;
  output [0:0]probe_out1;
  output [15:0]probe_out2;
@@ -39,4 +40,7 @@ module vio_rfcontrl(clk, probe_in0, probe_out0, probe_out1,
  output [0:0]probe_out15;
  output [0:0]probe_out16;
  output [15:0]probe_out17;
+  output [15:0]probe_out18;
+  output [31:0]probe_out19;
+  output [31:0]probe_out20;
 endmodule
@@ -1,10 +1,10 @@
 -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 -- --------------------------------------------------------------------------------
 -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
-- Date        : Mon May  8 13:15:25 2023
+-- Date        : Wed May 10 18:20:13 2023
 -- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
 -- Command     : write_vhdl -force -mode synth_stub
--               /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.vhdl
+--               /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.vhdl
 -- Design      : vio_rfcontrl
 -- Purpose     : Stub declaration of top-level module interface
 -- Device      : xc7z100ffg900-2
@@ -16,6 +16,7 @@ entity vio_rfcontrl is
  Port ( 
    clk : in STD_LOGIC;
    probe_in0 : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 );
    probe_out2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
@@ -33,7 +34,10 @@ entity vio_rfcontrl is
    probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 );
    probe_out15 : out STD_LOGIC_VECTOR ( 0 to 0 );
    probe_out16 : out STD_LOGIC_VECTOR ( 0 to 0 );
-    probe_out17 : out STD_LOGIC_VECTOR ( 15 downto 0 )
+    probe_out17 : out STD_LOGIC_VECTOR ( 15 downto 0 );
+    probe_out18 : out STD_LOGIC_VECTOR ( 15 downto 0 );
+    probe_out19 : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    probe_out20 : out STD_LOGIC_VECTOR ( 31 downto 0 )
  );

 end vio_rfcontrl;
@@ -42,7 +46,7 @@ architecture stub of vio_rfcontrl is
 attribute syn_black_box : boolean;
 attribute black_box_pad_pin : string;
 attribute syn_black_box of stub : architecture is true;
-attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[15:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[15:0]";
+attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[15:0],probe_in1[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[15:0],probe_out18[15:0],probe_out19[31:0],probe_out20[31:0]";
 attribute X_CORE_INFO : string;
 attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
 begin
@@ -0,0 +1,83 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required
+#             to simulate the design for a simulator, the directory structure
+#             and the generated exported files.
+#
+################################################################################
+
+1. Simulate Design
+
+To simulate design, cd to the simulator directory and execute the script.
+
+For example:-
+
+% cd questa
+% ./top.sh
+
+The export simulation flow requires the Xilinx pre-compiled simulation library
+components for the target simulator. These components are referred using the
+'-lib_map_path' switch. If this switch is specified, then the export simulation
+will automatically set this library path in the generated script and update,
+copy the simulator setup file(s) in the exported directory.
+
+If '-lib_map_path' is not specified, then the pre-compiled simulation library
+information will not be included in the exported scripts and that may cause
+simulation errors when running this script. Alternatively, you can provide the
+library information using this switch while executing the generated script.
+
+For example:-
+
+% ./top.sh -lib_map_path /design/questa/clibs
+
+Please refer to the generated script header 'Prerequisite' section for more details.
+
+2. Directory Structure
+
+By default, if the -directory switch is not specified, export_simulation will
+create the following directory structure:-
+
+<current_working_directory>/export_sim/<simulator>
+
+For example, if the current working directory is /tmp/test, export_simulation
+will create the following directory path:-
+
+/tmp/test/export_sim/questa
+
+If -directory switch is specified, export_simulation will create a simulator
+sub-directory under the specified directory path.
+
+For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
+command will create the following directory:-
+
+/tmp/test/my_test_area/func_sim/questa
+
+By default, if -simulator is not specified, export_simulation will create a
+simulator sub-directory for each simulator and export the files for each simulator
+in this sub-directory respectively.
+
+IMPORTANT: Please note that the simulation library path must be specified manually
+in the generated script for the respective simulator. Please refer to the generated
+script header 'Prerequisite' section for more details.
+
+3. Exported script and files
+
+Export simulation will create the driver shell script, setup files and copy the
+design sources in the output directory path.
+
+By default, when the -script_name switch is not specified, export_simulation will
+create the following script name:-
+
+<simulation_top>.sh  (Unix)
+When exporting the files for an IP using the -of_objects switch, export_simulation
+will create the following script name:-
+
+<ip-name>.sh  (Unix)
+Export simulation will create the setup files for the target simulator specified
+with the -simulator switch.
+
+For example, if the target simulator is "ies", export_simulation will create the
+'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
+file.
+
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Wed May 10 18:21:39 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./ila_rx_data_cnt.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './ila_rx_data_cnt.sh' script.
+
+./ila_rx_data_cnt.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./ila_rx_data_cnt.sh -noclean_files
+
+For more information on the script, please type './ila_rx_data_cnt.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
@@ -0,0 +1,22 @@
+vlib work
+vlib activehdl
+
+vlib activehdl/xil_defaultlib
+vlib activehdl/xpm
+
+vmap xil_defaultlib activehdl/xil_defaultlib
+vmap xpm activehdl/xpm
+
+vlog -work xil_defaultlib  -sv2k12 "+incdir+../../../ip/ila_rx_data_cnt/hdl/verilog" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+../../../ip/ila_rx_data_cnt/hdl/verilog" \
+"../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
@@ -0,0 +1,5 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog"
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog"
+ila_rx_data_cnt.v,verilog,xil_defaultlib,../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog"
+glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif
@@ -0,0 +1,152 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : ila_rx_data_cnt.sh
+# Simulator   : Aldec Active-HDL Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Wed May 10 18:21:39 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: ila_rx_data_cnt.sh [-help]
+# usage: ila_rx_data_cnt.sh [-lib_map_path]
+# usage: ila_rx_data_cnt.sh [-noclean_files]
+# usage: ila_rx_data_cnt.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'ila_rx_data_cnt.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "ila_rx_data_cnt.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rx_data_cnt.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  lib_map_path=""
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rx_data_cnt.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: ila_rx_data_cnt.sh [-help]\n\
+Usage: ila_rx_data_cnt.sh [-lib_map_path]\n\
+Usage: ila_rx_data_cnt.sh [-reset_run]\n\
+Usage: ila_rx_data_cnt.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim -t 1ps +access +r +m+ila_rx_data_cnt -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.ila_rx_data_cnt xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {ila_rx_data_cnt.udo}
+
+run -all
+
+endsim
+
+quit -force
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Wed May 10 18:21:39 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./ila_rx_data_cnt.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './ila_rx_data_cnt.sh' script.
+
+./ila_rx_data_cnt.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./ila_rx_data_cnt.sh -noclean_files
+
+For more information on the script, please type './ila_rx_data_cnt.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
@@ -0,0 +1,5 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog"
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog"
+ila_rx_data_cnt.v,verilog,xil_defaultlib,../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog"
+glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif
@@ -0,0 +1,176 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : ila_rx_data_cnt.sh
+# Simulator   : Cadence Incisive Enterprise Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Wed May 10 18:21:39 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: ila_rx_data_cnt.sh [-help]
+# usage: ila_rx_data_cnt.sh [-lib_map_path]
+# usage: ila_rx_data_cnt.sh [-noclean_files]
+# usage: ila_rx_data_cnt.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'ila_rx_data_cnt.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xil_defaultlib xpm)
+
+# Simulation root library directory
+sim_lib_dir="ies_lib"
+
+# Script info
+echo -e "ila_rx_data_cnt.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  irun $irun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.ila_rx_data_cnt \
+       -f run.f \
+       -top glbl \
+       glbl.v \
+       +incdir+"../../../ip/ila_rx_data_cnt/hdl/verilog"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rx_data_cnt.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rx_data_cnt.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: ila_rx_data_cnt.sh [-help]\n\
+Usage: ila_rx_data_cnt.sh [-lib_map_path]\n\
+Usage: ila_rx_data_cnt.sh [-reset_run]\n\
+Usage: ila_rx_data_cnt.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
@@ -0,0 +1,14 @@
+-makelib ies_lib/xil_defaultlib -sv \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+-endlib
+-makelib ies_lib/xpm \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  glbl.v
+-endlib
+
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Wed May 10 18:21:39 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./ila_rx_data_cnt.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './ila_rx_data_cnt.sh' script.
+
+./ila_rx_data_cnt.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./ila_rx_data_cnt.sh -noclean_files
+
+For more information on the script, please type './ila_rx_data_cnt.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
@@ -0,0 +1,14 @@
+vlib modelsim_lib/work
+vlib modelsim_lib/msim
+
+vlib modelsim_lib/msim/xil_defaultlib
+
+vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
+
+vlog -work xil_defaultlib -64 -incr "+incdir+../../../ip/ila_rx_data_cnt/hdl/verilog" \
+"../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v" \
+
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
@@ -0,0 +1,2 @@
+ila_rx_data_cnt.v,verilog,xil_defaultlib,../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog"
+glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif
@@ -0,0 +1,167 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : ila_rx_data_cnt.sh
+# Simulator   : Mentor Graphics ModelSim Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Wed May 10 18:21:39 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: ila_rx_data_cnt.sh [-help]
+# usage: ila_rx_data_cnt.sh [-lib_map_path]
+# usage: ila_rx_data_cnt.sh [-noclean_files]
+# usage: ila_rx_data_cnt.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'ila_rx_data_cnt.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "ila_rx_data_cnt.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rx_data_cnt.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/josh/Software/Xilinx/CompLib/Model/2019.1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="modelsim_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rx_data_cnt.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: ila_rx_data_cnt.sh [-help]\n\
+Usage: ila_rx_data_cnt.sh [-lib_map_path]\n\
+Usage: ila_rx_data_cnt.sh [-reset_run]\n\
+Usage: ila_rx_data_cnt.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.ila_rx_data_cnt xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {ila_rx_data_cnt.udo}
+
+run -all
+
+quit -force
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Wed May 10 18:21:39 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./ila_rx_data_cnt.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './ila_rx_data_cnt.sh' script.
+
+./ila_rx_data_cnt.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./ila_rx_data_cnt.sh -noclean_files
+
+For more information on the script, please type './ila_rx_data_cnt.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
@@ -0,0 +1,22 @@
+vlib questa_lib/work
+vlib questa_lib/msim
+
+vlib questa_lib/msim/xil_defaultlib
+vlib questa_lib/msim/xpm
+
+vmap xil_defaultlib questa_lib/msim/xil_defaultlib
+vmap xpm questa_lib/msim/xpm
+
+vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/ila_rx_data_cnt/hdl/verilog" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -64 -93 \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work xil_defaultlib -64 "+incdir+../../../ip/ila_rx_data_cnt/hdl/verilog" \
+"../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
@@ -0,0 +1 @@
+vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.ila_rx_data_cnt xil_defaultlib.glbl -o ila_rx_data_cnt_opt
@@ -0,0 +1,5 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog"
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog"
+ila_rx_data_cnt.v,verilog,xil_defaultlib,../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog"
+glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif
@@ -0,0 +1,174 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : ila_rx_data_cnt.sh
+# Simulator   : Mentor Graphics Questa Advanced Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Wed May 10 18:21:39 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: ila_rx_data_cnt.sh [-help]
+# usage: ila_rx_data_cnt.sh [-lib_map_path]
+# usage: ila_rx_data_cnt.sh [-noclean_files]
+# usage: ila_rx_data_cnt.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'ila_rx_data_cnt.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "ila_rx_data_cnt.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  source elaborate.do 2>&1 | tee -a elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rx_data_cnt.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="questa_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rx_data_cnt.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: ila_rx_data_cnt.sh [-help]\n\
+Usage: ila_rx_data_cnt.sh [-lib_map_path]\n\
+Usage: ila_rx_data_cnt.sh [-reset_run]\n\
+Usage: ila_rx_data_cnt.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -t 1ps -lib xil_defaultlib ila_rx_data_cnt_opt
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {ila_rx_data_cnt.udo}
+
+run -all
+
+quit -force
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Wed May 10 18:21:39 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./ila_rx_data_cnt.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './ila_rx_data_cnt.sh' script.
+
+./ila_rx_data_cnt.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./ila_rx_data_cnt.sh -noclean_files
+
+For more information on the script, please type './ila_rx_data_cnt.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
@@ -0,0 +1,22 @@
+vlib work
+vlib riviera
+
+vlib riviera/xil_defaultlib
+vlib riviera/xpm
+
+vmap xil_defaultlib riviera/xil_defaultlib
+vmap xpm riviera/xpm
+
+vlog -work xil_defaultlib  -sv2k12 "+incdir+../../../ip/ila_rx_data_cnt/hdl/verilog" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work xil_defaultlib  -v2k5 "+incdir+../../../ip/ila_rx_data_cnt/hdl/verilog" \
+"../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
@@ -0,0 +1,5 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog"
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog"
+ila_rx_data_cnt.v,verilog,xil_defaultlib,../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog"
+glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif
@@ -0,0 +1,153 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : ila_rx_data_cnt.sh
+# Simulator   : Aldec Riviera-PRO Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Wed May 10 18:21:39 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: ila_rx_data_cnt.sh [-help]
+# usage: ila_rx_data_cnt.sh [-lib_map_path]
+# usage: ila_rx_data_cnt.sh [-noclean_files]
+# usage: ila_rx_data_cnt.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'ila_rx_data_cnt.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "ila_rx_data_cnt.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rx_data_cnt.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rx_data_cnt.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: ila_rx_data_cnt.sh [-help]\n\
+Usage: ila_rx_data_cnt.sh [-lib_map_path]\n\
+Usage: ila_rx_data_cnt.sh [-reset_run]\n\
+Usage: ila_rx_data_cnt.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim -t 1ps +access +r +m+ila_rx_data_cnt -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.ila_rx_data_cnt xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {ila_rx_data_cnt.udo}
+
+run -all
+
+endsim
+
+quit -force
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Wed May 10 18:21:39 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./ila_rx_data_cnt.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './ila_rx_data_cnt.sh' script.
+
+./ila_rx_data_cnt.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./ila_rx_data_cnt.sh -noclean_files
+
+For more information on the script, please type './ila_rx_data_cnt.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
@@ -0,0 +1,2 @@
+ila_rx_data_cnt.v,verilog,xil_defaultlib,../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog"
+glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif
@@ -0,0 +1,221 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : ila_rx_data_cnt.sh
+# Simulator   : Synopsys Verilog Compiler Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Wed May 10 18:21:39 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: ila_rx_data_cnt.sh [-help]
+# usage: ila_rx_data_cnt.sh [-lib_map_path]
+# usage: ila_rx_data_cnt.sh [-noclean_files]
+# usage: ila_rx_data_cnt.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'ila_rx_data_cnt.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Command line options
+vlogan_opts="-full64"
+vhdlan_opts="-full64"
+vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log"
+vcs_sim_opts="-ucli -licqueue -l simulate.log"
+
+# Design libraries
+design_libs=(xil_defaultlib)
+
+# Simulation root library directory
+sim_lib_dir="vcs_lib"
+
+# Script info
+echo -e "ila_rx_data_cnt.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ip/ila_rx_data_cnt/hdl/verilog" \
+    "$ref_dir/../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v" \
+  2>&1 | tee -a vlogan.log
+
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k \
+    glbl.v \
+  2>&1 | tee -a vlogan.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  vcs $vcs_elab_opts xil_defaultlib.ila_rx_data_cnt xil_defaultlib.glbl -o ila_rx_data_cnt_simv
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  ./ila_rx_data_cnt_simv $vcs_sim_opts -do simulate.do
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rx_data_cnt.sh -help\" for more information)\n"
+        exit 1
+      fi
+      create_lib_mappings $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+      create_lib_mappings $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Define design library mappings
+create_lib_mappings()
+{
+  file="synopsys_sim.setup"
+  if [[ -e $file ]]; then
+    if [[ ($1 == "") ]]; then
+      return
+    else
+      rm -rf $file
+    fi
+  fi
+
+  touch $file
+
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/josh/Software/Xilinx/CompLib/VCS/2019.1"
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    mapping="$lib:$sim_lib_dir/$lib"
+    echo $mapping >> $file
+  done
+
+  if [[ ($lib_map_path != "") ]]; then
+    incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup"
+    echo $incl_ref >> $file
+  fi
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ucli.key ila_rx_data_cnt_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc ila_rx_data_cnt_simv.daidir)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rx_data_cnt.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: ila_rx_data_cnt.sh [-help]\n\
+Usage: ila_rx_data_cnt.sh [-lib_map_path]\n\
+Usage: ila_rx_data_cnt.sh [-reset_run]\n\
+Usage: ila_rx_data_cnt.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
@@ -0,0 +1,2 @@
+run
+quit
@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Wed May 10 18:21:39 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./ila_rx_data_cnt.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './ila_rx_data_cnt.sh' script.
+
+./ila_rx_data_cnt.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./ila_rx_data_cnt.sh -noclean_files
+
+For more information on the script, please type './ila_rx_data_cnt.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
@@ -0,0 +1,5 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog"
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog"
+xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog"
+ila_rx_data_cnt.v,verilog,xil_defaultlib,../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog"
+glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif
@@ -0,0 +1,176 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : ila_rx_data_cnt.sh
+# Simulator   : Cadence Xcelium Parallel Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Wed May 10 18:21:39 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: ila_rx_data_cnt.sh [-help]
+# usage: ila_rx_data_cnt.sh [-lib_map_path]
+# usage: ila_rx_data_cnt.sh [-noclean_files]
+# usage: ila_rx_data_cnt.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'ila_rx_data_cnt.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xil_defaultlib xpm)
+
+# Simulation root library directory
+sim_lib_dir="xcelium_lib"
+
+# Script info
+echo -e "ila_rx_data_cnt.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  xrun $xrun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.ila_rx_data_cnt \
+       -f run.f \
+       -top glbl \
+       glbl.v \
+       +incdir+"../../../ip/ila_rx_data_cnt/hdl/verilog"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rx_data_cnt.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rx_data_cnt.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: ila_rx_data_cnt.sh [-help]\n\
+Usage: ila_rx_data_cnt.sh [-lib_map_path]\n\
+Usage: ila_rx_data_cnt.sh [-reset_run]\n\
+Usage: ila_rx_data_cnt.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
@@ -0,0 +1,14 @@
+-makelib xcelium_lib/xil_defaultlib -sv \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+-endlib
+-makelib xcelium_lib/xpm \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  glbl.v
+-endlib
+
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Wed May 10 18:21:39 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./ila_rx_data_cnt.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './ila_rx_data_cnt.sh' script.
+
+./ila_rx_data_cnt.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./ila_rx_data_cnt.sh -noclean_files
+
+For more information on the script, please type './ila_rx_data_cnt.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
@@ -0,0 +1,12 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+  if { [llength [get_objects]] > 0} {
+    add_wave /
+    set_property needs_save false [current_wave_config]
+  } else {
+     send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+  }
+}
+
+run -all
+quit
@@ -0,0 +1,2 @@
+ila_rx_data_cnt.v,verilog,xil_defaultlib,../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v,incdir="../../../ip/ila_rx_data_cnt/hdl/verilog"
+glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif
@@ -0,0 +1,212 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : ila_rx_data_cnt.sh
+# Simulator   : Xilinx Vivado Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Wed May 10 18:21:39 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: ila_rx_data_cnt.sh [-help]
+# usage: ila_rx_data_cnt.sh [-lib_map_path]
+# usage: ila_rx_data_cnt.sh [-noclean_files]
+# usage: ila_rx_data_cnt.sh [-reset_run]
+#
+#*********************************************************************************************************
+
+# Command line options
+xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0
+xvlog_opts="--relax"
+
+
+# Script info
+echo -e "ila_rx_data_cnt.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  xelab --relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot ila_rx_data_cnt xil_defaultlib.ila_rx_data_cnt xil_defaultlib.glbl -log elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  xsim ila_rx_data_cnt -key {Behavioral:sim_1:Functional:ila_rx_data_cnt} -tclbatch cmd.tcl -log simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rx_data_cnt.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy xsim.ini file
+copy_setup_file()
+{
+  file="xsim.ini"
+  lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      cp $src_file .
+    fi
+
+    # Map local design libraries to xsim.ini
+    map_local_libs
+
+  fi
+}
+
+# Map local design libraries
+map_local_libs()
+{
+  updated_mappings=()
+  local_mappings=()
+
+  # Local design libraries
+  local_libs=()
+
+  if [[ 0 == ${#local_libs[@]} ]]; then
+    return
+  fi
+
+  file="xsim.ini"
+  file_backup="xsim.ini.bak"
+
+  if [[ -e $file ]]; then
+    rm -f $file_backup
+    # Create a backup copy of the xsim.ini file
+    cp $file $file_backup
+    # Read libraries from backup file and search in local library collection
+    while read -r line
+    do
+      IN=$line
+      # Split mapping entry with '=' delimiter to fetch library name and mapping
+      read lib_name mapping <<<$(IFS="="; echo $IN)
+      # If local library found, then construct the local mapping and add to local mapping collection
+      if `echo ${local_libs[@]} | grep -wq $lib_name` ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        local_mappings+=("$lib_name")
+      fi
+      # Add to updated library mapping collection
+      updated_mappings+=("$line")
+    done < "$file_backup"
+    # Append local libraries not found originally from xsim.ini
+    for (( i=0; i<${#local_libs[*]}; i++ )); do
+      lib_name="${local_libs[i]}"
+      if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        updated_mappings+=("$line")
+      fi
+    done
+    # Write updated mappings in xsim.ini
+    rm -f $file
+    for (( i=0; i<${#updated_mappings[*]}; i++ )); do
+      lib_name="${updated_mappings[i]}"
+      echo $lib_name >> $file
+    done
+  else
+    for (( i=0; i<${#local_libs[*]}; i++ )); do
+      lib_name="${local_libs[i]}"
+      mapping="$lib_name=xsim.dir/$lib_name"
+      echo $mapping >> $file
+    done
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb ila_rx_data_cnt.wdb xsim.dir)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rx_data_cnt.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: ila_rx_data_cnt.sh [-help]\n\
+Usage: ila_rx_data_cnt.sh [-lib_map_path]\n\
+Usage: ila_rx_data_cnt.sh [-reset_run]\n\
+Usage: ila_rx_data_cnt.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
@@ -0,0 +1,6 @@
+verilog xil_defaultlib --include "../../../ip/ila_rx_data_cnt/hdl/verilog" \
+"../../../ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v" \
+
+verilog xil_defaultlib "glbl.v"
+
+nosort
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Mon May 08 13:15:17 CST 2023
+# Generated by export_simulation on Wed May 10 18:22:56 CST 2023
 #
 ################################################################################

@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Mon May 08 13:15:17 CST 2023
+# Generated by Vivado on Wed May 10 18:22:56 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Mon May 08 13:15:17 CST 2023
+# Generated by export_simulation on Wed May 10 18:22:56 CST 2023
 #
 ################################################################################

@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Mon May 08 13:15:17 CST 2023
+# Generated by Vivado on Wed May 10 18:22:56 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Mon May 08 13:15:17 CST 2023
+# Generated by export_simulation on Wed May 10 18:22:56 CST 2023
 #
 ################################################################################

@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Mon May 08 13:15:17 CST 2023
+# Generated by Vivado on Wed May 10 18:22:56 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Mon May 08 13:15:17 CST 2023
+# Generated by export_simulation on Wed May 10 18:22:56 CST 2023
 #
 ################################################################################

@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Mon May 08 13:15:17 CST 2023
+# Generated by Vivado on Wed May 10 18:22:56 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
@@ -105,7 +105,7 @@ copy_setup_file()
  if [[ ($1 != "") ]]; then
    lib_map_path="$1"
  else
-    lib_map_path="/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa"
+    lib_map_path="/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa"
  fi
  if [[ ($lib_map_path != "") ]]; then
    src_file="$lib_map_path/$file"
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Mon May 08 13:15:17 CST 2023
+# Generated by export_simulation on Wed May 10 18:22:56 CST 2023
 #
 ################################################################################

@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Mon May 08 13:15:17 CST 2023
+# Generated by Vivado on Wed May 10 18:22:56 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
@@ -96,7 +96,7 @@ map_setup_file()
  if [[ ($1 != "") ]]; then
    lib_map_path="$1"
  else
-    lib_map_path="/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera"
+    lib_map_path="/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera"
  fi
  if [[ ($lib_map_path != "") ]]; then
    src_file="$lib_map_path/$file"
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Mon May 08 13:15:17 CST 2023
+# Generated by export_simulation on Wed May 10 18:22:56 CST 2023
 #
 ################################################################################

@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Mon May 08 13:15:17 CST 2023
+# Generated by Vivado on Wed May 10 18:22:56 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Mon May 08 13:15:17 CST 2023
+# Generated by export_simulation on Wed May 10 18:22:56 CST 2023
 #
 ################################################################################

@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Mon May 08 13:15:17 CST 2023
+# Generated by Vivado on Wed May 10 18:22:56 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Mon May 08 13:15:17 CST 2023
+# Generated by export_simulation on Wed May 10 18:22:56 CST 2023
 #
 ################################################################################

@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Mon May 08 13:15:17 CST 2023
+# Generated by Vivado on Wed May 10 18:22:56 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Mon May 08 13:15:28 CST 2023
+# Generated by export_simulation on Wed May 10 18:19:54 CST 2023
 #
 ################################################################################

@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Mon May 08 13:15:28 CST 2023
+# Generated by Vivado on Wed May 10 18:19:54 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
--- a/Show More
+++ b/Show More
				`@@ -0,0 +1 @@`
				`vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.ila_rx_data_cnt xil_defaultlib.glbl -o ila_rx_data_cnt_opt`