finish coding and testing of online acq; add sample data

串行在线捕获程序已经完成编写,并进行了仿真和测试(对飞和814均可用);增加了在电子所使用转台测试的幅相采集数据
2023-05-08 19:13:53 +08:00
parent e07389e326
commit 2d4650a3b6
2835 changed files with 408373 additions and 181193 deletions
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+// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+// DO NOT MODIFY THIS FILE.
+
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+
+ila_8x12_8192 your_instance_name (
+	.clk(clk), // input wire clk
+
+
+	.probe0(probe0), // input wire [11:0]  probe0  
+	.probe1(probe1), // input wire [11:0]  probe1 
+	.probe2(probe2), // input wire [11:0]  probe2 
+	.probe3(probe3), // input wire [11:0]  probe3 
+	.probe4(probe4), // input wire [11:0]  probe4 
+	.probe5(probe5), // input wire [11:0]  probe5 
+	.probe6(probe6), // input wire [11:0]  probe6 
+	.probe7(probe7) // input wire [11:0]  probe7
+);
+
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file ila_8x12_8192 when simulating
+// the core, ila_8x12_8192. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+
+
@@ -0,0 +1,29 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+// Date        : Sun May  7 16:49:27 2023
+// Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
+// Command     : write_verilog -force -mode synth_stub
+//               /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12_8192_synth_1/ila_8x12_8192_stub.v
+// Design      : ila_8x12_8192
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7k410tffg900-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* X_CORE_INFO = "ila,Vivado 2019.1.3" *)
+module ila_8x12_8192(clk, probe0, probe1, probe2, probe3, probe4, probe5, 
+  probe6, probe7)
+/* synthesis syn_black_box black_box_pad_pin="clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0]" */;
+  input clk;
+  input [11:0]probe0;
+  input [11:0]probe1;
+  input [11:0]probe2;
+  input [11:0]probe3;
+  input [11:0]probe4;
+  input [11:0]probe5;
+  input [11:0]probe6;
+  input [11:0]probe7;
+endmodule
@@ -0,0 +1,38 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+-- Date        : Sun May  7 16:49:27 2023
+-- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
+-- Command     : write_vhdl -force -mode synth_stub
+--               /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12_8192_synth_1/ila_8x12_8192_stub.vhdl
+-- Design      : ila_8x12_8192
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7k410tffg900-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity ila_8x12_8192 is
+  Port ( 
+    clk : in STD_LOGIC;
+    probe0 : in STD_LOGIC_VECTOR ( 11 downto 0 );
+    probe1 : in STD_LOGIC_VECTOR ( 11 downto 0 );
+    probe2 : in STD_LOGIC_VECTOR ( 11 downto 0 );
+    probe3 : in STD_LOGIC_VECTOR ( 11 downto 0 );
+    probe4 : in STD_LOGIC_VECTOR ( 11 downto 0 );
+    probe5 : in STD_LOGIC_VECTOR ( 11 downto 0 );
+    probe6 : in STD_LOGIC_VECTOR ( 11 downto 0 );
+    probe7 : in STD_LOGIC_VECTOR ( 11 downto 0 )
+  );
+
+end ila_8x12_8192;
+
+architecture stub of ila_8x12_8192 is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0]";
+attribute X_CORE_INFO : string;
+attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3";
+begin
+end;
@@ -0,0 +1,76 @@
+// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+// DO NOT MODIFY THIS FILE.
+`timescale 1ns / 1ps
+module ila_8x12_8192 (
+clk,
+
+
+probe0,
+probe1,
+probe2,
+probe3,
+probe4,
+probe5,
+probe6,
+probe7
+);
+
+input clk;
+
+
+input [11 : 0] probe0;
+input [11 : 0] probe1;
+input [11 : 0] probe2;
+input [11 : 0] probe3;
+input [11 : 0] probe4;
+input [11 : 0] probe5;
+input [11 : 0] probe6;
+input [11 : 0] probe7;
+
+
+endmodule