Archived
finish coding and testing of online acq; add sample data
串行在线捕获程序已经完成编写,并进行了仿真和测试(对飞和814均可用);增加了在电子所使用转台测试的幅相采集数据
This commit is contained in:
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@@ -0,0 +1,83 @@
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MEMORY_INITIALIZATION_RADIX = 10;
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MEMORY_INITIALIZATION_VECTOR =
|
||||
2124,
|
||||
2111,
|
||||
2098,
|
||||
2085,
|
||||
2072,
|
||||
2059,
|
||||
2046,
|
||||
2033,
|
||||
2020,
|
||||
2007,
|
||||
1994,
|
||||
1981,
|
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1968,
|
||||
1955,
|
||||
1942,
|
||||
1929,
|
||||
1916,
|
||||
1903,
|
||||
1890,
|
||||
1877,
|
||||
1864,
|
||||
1851,
|
||||
1838,
|
||||
1825,
|
||||
1812,
|
||||
1799,
|
||||
1786,
|
||||
1773,
|
||||
1760,
|
||||
1747,
|
||||
1734,
|
||||
1721,
|
||||
1708,
|
||||
1695,
|
||||
1682,
|
||||
1669,
|
||||
1656,
|
||||
1643,
|
||||
1630,
|
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1617,
|
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1604,
|
||||
1591,
|
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1578,
|
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1565,
|
||||
1552,
|
||||
1539,
|
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1526,
|
||||
1513,
|
||||
1500,
|
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1487,
|
||||
1474,
|
||||
1461,
|
||||
1448,
|
||||
1435,
|
||||
1422,
|
||||
1409,
|
||||
1396,
|
||||
1383,
|
||||
1370,
|
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1357,
|
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1344,
|
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1331,
|
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1318,
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1305,
|
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1292,
|
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1279,
|
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1266,
|
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1253,
|
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1240,
|
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1227,
|
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1214,
|
||||
1201,
|
||||
1188,
|
||||
1175,
|
||||
1162,
|
||||
1149,
|
||||
1136,
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1123,
|
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1110,
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1097,
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1084,
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@@ -0,0 +1,514 @@
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RADIX = 10;
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COEFDATA =
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1,
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1,
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1,
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1,
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||||
1,
|
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1,
|
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1,
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1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
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-1,
|
||||
-1,
|
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1,
|
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1,
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1,
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1,
|
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1,
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1,
|
||||
1,
|
||||
1,
|
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-1,
|
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-1,
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-1,
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-1,
|
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1,
|
||||
1,
|
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1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
1,
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||||
1,
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||||
1,
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||||
1,
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||||
1,
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||||
1,
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1,
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||||
1,
|
||||
-1,
|
||||
-1,
|
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-1,
|
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-1,
|
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-1,
|
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-1,
|
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-1,
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-1,
|
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-1,
|
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-1,
|
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-1,
|
||||
-1,
|
||||
1,
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1,
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||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
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-1,
|
||||
-1,
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1,
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1,
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||||
1,
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||||
1,
|
||||
-1,
|
||||
-1,
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-1,
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-1,
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1,
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||||
1,
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||||
1,
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||||
1,
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1,
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1,
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1,
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1,
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1,
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1,
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1,
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1,
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1,
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1,
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||||
1,
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1,
|
||||
-1,
|
||||
-1,
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||||
-1,
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||||
-1,
|
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-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
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1,
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1,
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1,
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1,
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1,
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1,
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1,
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1,
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1,
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1,
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1,
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1,
|
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-1,
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-1,
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-1,
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||||
-1,
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1,
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1,
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1,
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1,
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||||
1,
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1,
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1,
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||||
1,
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-1,
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-1,
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-1,
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1,
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||||
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||||
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||||
1,
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||||
1,
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||||
1,
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||||
-1,
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||||
-1,
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-1,
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-1,
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-1,
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||||
-1,
|
||||
-1,
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||||
-1,
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||||
1,
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||||
1,
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1,
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1,
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-1,
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-1,
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-1,
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-1,
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-1,
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-1,
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-1,
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-1,
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1,
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1,
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1,
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1,
|
||||
-1,
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-1,
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-1,
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-1,
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1,
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1,
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1,
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1,
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-1,
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-1,
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-1,
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-1,
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-1,
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-1,
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-1,
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-1,
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1,
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1,
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1,
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1,
|
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-1,
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-1,
|
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-1,
|
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-1,
|
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-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
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-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
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||||
1,
|
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1,
|
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1,
|
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1,
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1,
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1,
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1,
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1,
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1,
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1,
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1,
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1,
|
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-1,
|
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-1,
|
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-1,
|
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-1,
|
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-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
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1,
|
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1,
|
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1,
|
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1,
|
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-1,
|
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-1,
|
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-1,
|
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-1,
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1,
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1,
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1,
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1,
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1,
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1,
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1,
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1,
|
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-1,
|
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-1,
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-1,
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-1,
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1,
|
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1,
|
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1,
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1,
|
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-1,
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-1,
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-1,
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-1,
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-1,
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-1,
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-1,
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-1,
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-1,
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-1,
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-1,
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-1,
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1,
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1,
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1,
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1,
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-1,
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-1,
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-1,
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-1,
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-1,
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-1,
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-1,
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-1,
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-1,
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-1,
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-1,
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-1,
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1,
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1,
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1,
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1,
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1,
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1,
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1,
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1,
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-1,
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-1,
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-1,
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-1,
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-1,
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-1,
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-1,
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-1,
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1,
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1,
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1,
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1,
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1,
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1,
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1,
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1,
|
||||
-1,
|
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-1,
|
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-1,
|
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-1,
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1,
|
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1,
|
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1,
|
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1,
|
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-1,
|
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-1,
|
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-1,
|
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-1,
|
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1,
|
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1,
|
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1,
|
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1,
|
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-1,
|
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-1,
|
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-1,
|
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-1,
|
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1,
|
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1,
|
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1,
|
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1,
|
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-1,
|
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-1,
|
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-1,
|
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-1,
|
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-1,
|
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-1,
|
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-1,
|
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-1,
|
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-1,
|
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-1,
|
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-1,
|
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-1,
|
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-1,
|
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-1,
|
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-1,
|
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-1,
|
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-1,
|
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-1,
|
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-1,
|
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-1,
|
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-1,
|
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-1,
|
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-1,
|
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-1,
|
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-1,
|
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-1,
|
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-1,
|
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-1,
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1,
|
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1,
|
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1,
|
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1,
|
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1,
|
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1,
|
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1,
|
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1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
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1,
|
||||
1,
|
||||
1,
|
||||
1,
|
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1,
|
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-1,
|
||||
-1,
|
||||
-1,
|
||||
-1;
|
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+12
-9
@@ -46,23 +46,26 @@
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||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
// IP VLNV: xilinx.com:ip:vio:3.0
|
||||
// IP Revision: 20
|
||||
// IP VLNV: xilinx.com:ip:cmpy:6.0
|
||||
// IP Revision: 17
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
vio_cal your_instance_name (
|
||||
.clk(clk), // input wire clk
|
||||
.probe_in0(probe_in0), // input wire [4 : 0] probe_in0
|
||||
.probe_in1(probe_in1), // input wire [15 : 0] probe_in1
|
||||
.probe_in2(probe_in2) // input wire [15 : 0] probe_in2
|
||||
cmpy_12x8 your_instance_name (
|
||||
.aclk(aclk), // input wire aclk
|
||||
.s_axis_a_tvalid(s_axis_a_tvalid), // input wire s_axis_a_tvalid
|
||||
.s_axis_a_tdata(s_axis_a_tdata), // input wire [31 : 0] s_axis_a_tdata
|
||||
.s_axis_b_tvalid(s_axis_b_tvalid), // input wire s_axis_b_tvalid
|
||||
.s_axis_b_tdata(s_axis_b_tdata), // input wire [15 : 0] s_axis_b_tdata
|
||||
.m_axis_dout_tvalid(m_axis_dout_tvalid), // output wire m_axis_dout_tvalid
|
||||
.m_axis_dout_tdata(m_axis_dout_tdata) // output wire [47 : 0] m_axis_dout_tdata
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file vio_cal.v when simulating
|
||||
// the core, vio_cal. When compiling the wrapper file, be sure to
|
||||
// You must compile the wrapper file cmpy_12x8.v when simulating
|
||||
// the core, cmpy_12x8. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
+20
-14
@@ -46,18 +46,21 @@
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:vio:3.0
|
||||
-- IP Revision: 20
|
||||
-- IP VLNV: xilinx.com:ip:cmpy:6.0
|
||||
-- IP Revision: 17
|
||||
|
||||
-- The following code must appear in the VHDL architecture header.
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
COMPONENT vio_cal
|
||||
COMPONENT cmpy_12x8
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
probe_in0 : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
|
||||
probe_in1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
probe_in2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0)
|
||||
aclk : IN STD_LOGIC;
|
||||
s_axis_a_tvalid : IN STD_LOGIC;
|
||||
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axis_b_tvalid : IN STD_LOGIC;
|
||||
s_axis_b_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
m_axis_dout_tvalid : OUT STD_LOGIC;
|
||||
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
@@ -66,16 +69,19 @@ END COMPONENT;
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : vio_cal
|
||||
your_instance_name : cmpy_12x8
|
||||
PORT MAP (
|
||||
clk => clk,
|
||||
probe_in0 => probe_in0,
|
||||
probe_in1 => probe_in1,
|
||||
probe_in2 => probe_in2
|
||||
aclk => aclk,
|
||||
s_axis_a_tvalid => s_axis_a_tvalid,
|
||||
s_axis_a_tdata => s_axis_a_tdata,
|
||||
s_axis_b_tvalid => s_axis_b_tvalid,
|
||||
s_axis_b_tdata => s_axis_b_tdata,
|
||||
m_axis_dout_tvalid => m_axis_dout_tvalid,
|
||||
m_axis_dout_tdata => m_axis_dout_tdata
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
-- You must compile the wrapper file vio_cal.vhd when simulating
|
||||
-- the core, vio_cal. When compiling the wrapper file, be sure to
|
||||
-- You must compile the wrapper file cmpy_12x8.vhd when simulating
|
||||
-- the core, cmpy_12x8. When compiling the wrapper file, be sure to
|
||||
-- reference the VHDL simulation library.
|
||||
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
@@ -0,0 +1,27 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Sat May 6 15:10:00 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8_stub.v
|
||||
// Design : cmpy_12x8
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "cmpy_v6_0_17,Vivado 2019.1.3" *)
|
||||
module cmpy_12x8(aclk, s_axis_a_tvalid, s_axis_a_tdata,
|
||||
s_axis_b_tvalid, s_axis_b_tdata, m_axis_dout_tvalid, m_axis_dout_tdata)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_a_tvalid,s_axis_a_tdata[31:0],s_axis_b_tvalid,s_axis_b_tdata[15:0],m_axis_dout_tvalid,m_axis_dout_tdata[47:0]" */;
|
||||
input aclk;
|
||||
input s_axis_a_tvalid;
|
||||
input [31:0]s_axis_a_tdata;
|
||||
input s_axis_b_tvalid;
|
||||
input [15:0]s_axis_b_tdata;
|
||||
output m_axis_dout_tvalid;
|
||||
output [47:0]m_axis_dout_tdata;
|
||||
endmodule
|
||||
+36
@@ -0,0 +1,36 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Sat May 6 15:10:00 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/cmpy_12x8_synth_1/cmpy_12x8_stub.vhdl
|
||||
-- Design : cmpy_12x8
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity cmpy_12x8 is
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
s_axis_a_tvalid : in STD_LOGIC;
|
||||
s_axis_a_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axis_b_tvalid : in STD_LOGIC;
|
||||
s_axis_b_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
m_axis_dout_tvalid : out STD_LOGIC;
|
||||
m_axis_dout_tdata : out STD_LOGIC_VECTOR ( 47 downto 0 )
|
||||
);
|
||||
|
||||
end cmpy_12x8;
|
||||
|
||||
architecture stub of cmpy_12x8 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_a_tvalid,s_axis_a_tdata[31:0],s_axis_b_tvalid,s_axis_b_tdata[15:0],m_axis_dout_tvalid,m_axis_dout_tdata[47:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "cmpy_v6_0_17,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+387
@@ -0,0 +1,387 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--------------------------------------------------------------------------------
|
||||
-- Description:
|
||||
-- This is an example testbench for the Complex Multiplier IP core.
|
||||
-- The testbench has been generated by Vivado to accompany the IP core
|
||||
-- instance you have generated.
|
||||
--
|
||||
-- This testbench is for demonstration purposes only. See note below for
|
||||
-- instructions on how to use it with your core.
|
||||
--
|
||||
-- See the Complex Multiplier product guide for further information
|
||||
-- about this core.
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Using this testbench
|
||||
--
|
||||
-- This testbench instantiates your generated Complex Multiplier core
|
||||
-- instance named "cmpy_12x8".
|
||||
--
|
||||
-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado
|
||||
-- documentation for details.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee.math_real.all;
|
||||
|
||||
entity tb_cmpy_12x8 is
|
||||
end tb_cmpy_12x8;
|
||||
|
||||
architecture tb of tb_cmpy_12x8 is
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Timing constants
|
||||
-----------------------------------------------------------------------
|
||||
constant CLOCK_PERIOD : time := 100 ns;
|
||||
constant T_HOLD : time := 10 ns;
|
||||
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
|
||||
constant TEST_CYCLES : integer := 3000;
|
||||
constant PHASE_CYCLES : integer := 1000;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- DUT input signals
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
-- General inputs
|
||||
signal aclk : std_logic := '0'; -- the master clock
|
||||
|
||||
-- Slave channel A inputs
|
||||
signal s_axis_a_tvalid : std_logic := '0'; -- TVALID for channel A
|
||||
signal s_axis_a_tdata : std_logic_vector(31 downto 0) := (others => '0'); -- TDATA for channel A
|
||||
|
||||
-- Slave channel B inputs
|
||||
signal s_axis_b_tvalid : std_logic := '0'; -- TVALID for channel B
|
||||
signal s_axis_b_tdata : std_logic_vector(15 downto 0) := (others => '0'); -- TDATA for channel B
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- DUT output signals
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
-- Master channel DOUT outputs
|
||||
signal m_axis_dout_tvalid : std_logic := '0'; -- TVALID for channel DOUT
|
||||
signal m_axis_dout_tdata : std_logic_vector(47 downto 0) := (others => '0'); -- TDATA for channel DOUT
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Aliases for AXI channel TDATA fields
|
||||
-- These are a convenience for viewing data in a simulator waveform viewer.
|
||||
-- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
|
||||
-- to prevent the simulator optimizing away these signals.
|
||||
-----------------------------------------------------------------------
|
||||
signal s_axis_a_tdata_real : std_logic_vector(11 downto 0) := (others => '0');
|
||||
signal s_axis_a_tdata_imag : std_logic_vector(11 downto 0) := (others => '0');
|
||||
signal s_axis_b_tdata_real : std_logic_vector(7 downto 0) := (others => '0');
|
||||
signal s_axis_b_tdata_imag : std_logic_vector(7 downto 0) := (others => '0');
|
||||
signal m_axis_dout_tdata_real : std_logic_vector(20 downto 0) := (others => '0');
|
||||
signal m_axis_dout_tdata_imag : std_logic_vector(20 downto 0) := (others => '0');
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Testbench signals
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
signal cycles : integer := 0; -- Clock cycle counter
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Constants, types and functions to create input data
|
||||
-- Treat the complex multiplier as a mixer that is combining two
|
||||
-- sinusoids exp(+/-jwt) of different frequencies and amplitudes:
|
||||
-- channel A: exp(+jwt), frequency = clock / 30, amplitude = fullscale >> 3
|
||||
-- channel B: exp(-jwt), frequency = clock / 32, amplitude = fullscale
|
||||
-- The output of the complex multiplier is a sinusoid with a frequency
|
||||
-- equal to the difference between the input frequencies.
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
constant IP_A_DEPTH : integer := 30;
|
||||
constant IP_A_WIDTH : integer := 12;
|
||||
constant IP_A_SHIFT : integer := 3; -- bit shift for amplitude
|
||||
constant IP_B_DEPTH : integer := 32;
|
||||
constant IP_B_WIDTH : integer := 8;
|
||||
constant IP_B_SHIFT : integer := 0; -- no bit shift, max amplitude
|
||||
type T_IP_INT_ENTRY is record
|
||||
re : integer;
|
||||
im : integer;
|
||||
end record;
|
||||
type T_IP_A_ENTRY is record
|
||||
re : std_logic_vector(IP_A_WIDTH-1 downto 0);
|
||||
im : std_logic_vector(IP_A_WIDTH-1 downto 0);
|
||||
end record;
|
||||
type T_IP_B_ENTRY is record
|
||||
re : std_logic_vector(IP_B_WIDTH-1 downto 0);
|
||||
im : std_logic_vector(IP_B_WIDTH-1 downto 0);
|
||||
end record;
|
||||
type T_IP_A_TABLE is array (0 to IP_A_DEPTH-1) of T_IP_A_ENTRY;
|
||||
type T_IP_B_TABLE is array (0 to IP_B_DEPTH-1) of T_IP_B_ENTRY;
|
||||
|
||||
-- Common function to calculate sine and cosine values
|
||||
function create_ip_entry(index, depth, width : integer) return T_IP_INT_ENTRY is
|
||||
variable result : T_IP_INT_ENTRY;
|
||||
variable theta : real;
|
||||
variable limited_width : integer := width - 2;
|
||||
begin
|
||||
if limited_width > 30 then
|
||||
limited_width := 30;
|
||||
end if;
|
||||
theta := real(index) / real(depth) * 2.0 * MATH_PI;
|
||||
result.re := integer(round(cos(theta) * real(2**limited_width-1)));
|
||||
result.im := integer(round(sin(theta) * real(2**limited_width-1)));
|
||||
return result;
|
||||
end function create_ip_entry;
|
||||
|
||||
-- Use separate functions to calculate channel A and B sinusoids as they return different types
|
||||
function create_ip_a_table return T_IP_A_TABLE is
|
||||
variable result : T_IP_A_TABLE;
|
||||
variable entry_int : T_IP_INT_ENTRY;
|
||||
begin
|
||||
for i in 0 to IP_A_DEPTH-1 loop
|
||||
entry_int := create_ip_entry(i, IP_A_DEPTH, IP_A_WIDTH - IP_A_SHIFT);
|
||||
result(i).re := std_logic_vector(to_signed(entry_int.re, IP_A_WIDTH));
|
||||
result(i).im := std_logic_vector(to_signed(entry_int.im, IP_A_WIDTH));
|
||||
end loop;
|
||||
return result;
|
||||
end function create_ip_a_table;
|
||||
|
||||
function create_ip_b_table return T_IP_B_TABLE is
|
||||
variable result : T_IP_B_TABLE;
|
||||
variable entry_int : T_IP_INT_ENTRY;
|
||||
begin
|
||||
for i in 0 to IP_B_DEPTH-1 loop
|
||||
entry_int := create_ip_entry(IP_B_DEPTH-1-i, IP_B_DEPTH, IP_B_WIDTH - IP_B_SHIFT); -- note rotation direction
|
||||
result(i).re := std_logic_vector(to_signed(entry_int.re, IP_B_WIDTH));
|
||||
result(i).im := std_logic_vector(to_signed(entry_int.im, IP_B_WIDTH));
|
||||
end loop;
|
||||
return result;
|
||||
end function create_ip_b_table;
|
||||
|
||||
-- Call the functions to create the data
|
||||
constant IP_A_DATA : T_IP_A_TABLE := create_ip_a_table;
|
||||
constant IP_B_DATA : T_IP_B_TABLE := create_ip_b_table;
|
||||
|
||||
|
||||
begin
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Instantiate the DUT
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
dut : entity work.cmpy_12x8
|
||||
port map (
|
||||
aclk => aclk,
|
||||
s_axis_a_tvalid => s_axis_a_tvalid,
|
||||
s_axis_a_tdata => s_axis_a_tdata,
|
||||
s_axis_b_tvalid => s_axis_b_tvalid,
|
||||
s_axis_b_tdata => s_axis_b_tdata,
|
||||
m_axis_dout_tvalid => m_axis_dout_tvalid,
|
||||
m_axis_dout_tdata => m_axis_dout_tdata
|
||||
);
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Generate clock
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
clock_gen : process
|
||||
begin
|
||||
aclk <= '0';
|
||||
wait for CLOCK_PERIOD;
|
||||
loop
|
||||
cycles <= cycles + 1;
|
||||
aclk <= '0';
|
||||
wait for CLOCK_PERIOD/2;
|
||||
aclk <= '1';
|
||||
wait for CLOCK_PERIOD/2;
|
||||
if cycles >= TEST_CYCLES then
|
||||
report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;
|
||||
wait;
|
||||
end if;
|
||||
end loop;
|
||||
end process clock_gen;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Generate inputs
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
stimuli : process
|
||||
variable ip_a_index : integer := 0;
|
||||
variable ip_b_index : integer := 0;
|
||||
variable a_tvalid_nxt : std_logic := '0';
|
||||
variable b_tvalid_nxt : std_logic := '0';
|
||||
variable phase2_cycles : integer := 1;
|
||||
variable phase2_count : integer := 0;
|
||||
constant PHASE2_LIMIT : integer := 30;
|
||||
begin
|
||||
|
||||
-- Test is stopped in clock_gen process, use endless loop here
|
||||
loop
|
||||
|
||||
-- Drive inputs T_HOLD time after rising edge of clock
|
||||
wait until rising_edge(aclk);
|
||||
wait for T_HOLD;
|
||||
|
||||
-- Drive AXI TVALID signals to demonstrate different types of operation
|
||||
case cycles is -- do different types of operation at different phases of the test
|
||||
when 0 to PHASE_CYCLES * 1 - 1 =>
|
||||
-- Phase 1: inputs always valid, no missing input data
|
||||
a_tvalid_nxt := '1';
|
||||
b_tvalid_nxt := '1';
|
||||
when PHASE_CYCLES * 1 to PHASE_CYCLES * 2 - 1 =>
|
||||
-- Phase 2: deprive channel A of valid transactions at an increasing rate
|
||||
b_tvalid_nxt := '1';
|
||||
if phase2_count < phase2_cycles then
|
||||
a_tvalid_nxt := '0';
|
||||
else
|
||||
a_tvalid_nxt := '1';
|
||||
end if;
|
||||
phase2_count := phase2_count + 1;
|
||||
if phase2_count >= PHASE2_LIMIT then
|
||||
phase2_count := 0;
|
||||
phase2_cycles := phase2_cycles + 1;
|
||||
end if;
|
||||
when PHASE_CYCLES * 2 to PHASE_CYCLES * 3 - 1 =>
|
||||
-- Phase 3: deprive channel A of 1 out of 2 transactions, and channel B of 1 out of 3 transactions
|
||||
if cycles mod 2 = 0 then
|
||||
a_tvalid_nxt := '0';
|
||||
else
|
||||
a_tvalid_nxt := '1';
|
||||
end if;
|
||||
if cycles mod 3 = 0 then
|
||||
b_tvalid_nxt := '0';
|
||||
else
|
||||
b_tvalid_nxt := '1';
|
||||
end if;
|
||||
when others =>
|
||||
-- Test will stop imminently - do nothing
|
||||
null;
|
||||
end case;
|
||||
|
||||
-- Drive handshake signals with local variable values
|
||||
s_axis_a_tvalid <= a_tvalid_nxt;
|
||||
s_axis_b_tvalid <= b_tvalid_nxt;
|
||||
|
||||
-- Drive AXI slave channel A payload
|
||||
-- Drive '0's on payload signals when not valid
|
||||
if a_tvalid_nxt /= '1' then
|
||||
s_axis_a_tdata <= (others => '0');
|
||||
else
|
||||
-- TDATA: Real and imaginary components are each 12 bits wide and byte-aligned at their LSBs
|
||||
s_axis_a_tdata(11 downto 0) <= IP_A_DATA(ip_a_index).re;
|
||||
s_axis_a_tdata(15 downto 12) <= (others => IP_A_DATA(ip_a_index).re(11)); -- sign-extend;
|
||||
s_axis_a_tdata(27 downto 16) <= IP_A_DATA(ip_a_index).im;
|
||||
s_axis_a_tdata(31 downto 28) <= (others => IP_A_DATA(ip_a_index).im(11)); -- sign-extend;
|
||||
end if;
|
||||
|
||||
-- Drive AXI slave channel B payload
|
||||
-- Drive '0's on payload signals when not valid
|
||||
if b_tvalid_nxt /= '1' then
|
||||
s_axis_b_tdata <= (others => '0');
|
||||
else
|
||||
-- TDATA: Real and imaginary components are each 8 bits wide and byte-aligned at their LSBs
|
||||
s_axis_b_tdata(7 downto 0) <= IP_B_DATA(ip_b_index).re;
|
||||
s_axis_b_tdata(15 downto 8) <= IP_B_DATA(ip_b_index).im;
|
||||
end if;
|
||||
|
||||
-- Increment input data indices
|
||||
if a_tvalid_nxt = '1' then
|
||||
ip_a_index := ip_a_index + 1;
|
||||
if ip_a_index = IP_A_DEPTH then
|
||||
ip_a_index := 0;
|
||||
end if;
|
||||
end if;
|
||||
if b_tvalid_nxt = '1' then
|
||||
ip_b_index := ip_b_index + 1;
|
||||
if ip_b_index = IP_B_DEPTH then
|
||||
ip_b_index := 0;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end loop;
|
||||
|
||||
end process stimuli;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Check outputs
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
check_outputs : process
|
||||
variable check_ok : boolean := true;
|
||||
begin
|
||||
|
||||
-- Check outputs T_STROBE time after rising edge of clock
|
||||
wait until rising_edge(aclk);
|
||||
wait for T_STROBE;
|
||||
|
||||
-- Do not check the output payload values, as this requires the behavioral model
|
||||
-- which would make this demonstration testbench unwieldy.
|
||||
-- Instead, check the protocol of the DOUT channel:
|
||||
-- check that the payload is valid (not X) when TVALID is high
|
||||
|
||||
if m_axis_dout_tvalid = '1' then
|
||||
if is_x(m_axis_dout_tdata) then
|
||||
report "ERROR: m_axis_dout_tdata is invalid when m_axis_dout_tvalid is high" severity error;
|
||||
check_ok := false;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
assert check_ok
|
||||
report "ERROR: terminating test with failures." severity failure;
|
||||
|
||||
end process check_outputs;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Assign TDATA fields to aliases, for easy simulator waveform viewing
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
s_axis_a_tdata_real <= s_axis_a_tdata(11 downto 0);
|
||||
s_axis_a_tdata_imag <= s_axis_a_tdata(27 downto 16);
|
||||
s_axis_b_tdata_real <= s_axis_b_tdata(7 downto 0);
|
||||
s_axis_b_tdata_imag <= s_axis_b_tdata(15 downto 8);
|
||||
m_axis_dout_tdata_real <= m_axis_dout_tdata(20 downto 0);
|
||||
m_axis_dout_tdata_imag <= m_axis_dout_tdata(44 downto 24);
|
||||
|
||||
end tb;
|
||||
|
||||
+202
@@ -0,0 +1,202 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:cmpy:6.0
|
||||
-- IP Revision: 17
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY cmpy_v6_0_17;
|
||||
USE cmpy_v6_0_17.cmpy_v6_0_17;
|
||||
|
||||
ENTITY cmpy_12x8 IS
|
||||
PORT (
|
||||
aclk : IN STD_LOGIC;
|
||||
s_axis_a_tvalid : IN STD_LOGIC;
|
||||
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axis_b_tvalid : IN STD_LOGIC;
|
||||
s_axis_b_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
m_axis_dout_tvalid : OUT STD_LOGIC;
|
||||
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
|
||||
);
|
||||
END cmpy_12x8;
|
||||
|
||||
ARCHITECTURE cmpy_12x8_arch OF cmpy_12x8 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF cmpy_12x8_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT cmpy_v6_0_17 IS
|
||||
GENERIC (
|
||||
C_VERBOSITY : INTEGER;
|
||||
C_XDEVICEFAMILY : STRING;
|
||||
C_XDEVICE : STRING;
|
||||
C_A_WIDTH : INTEGER;
|
||||
C_B_WIDTH : INTEGER;
|
||||
C_OUT_WIDTH : INTEGER;
|
||||
C_LATENCY : INTEGER;
|
||||
C_MULT_TYPE : INTEGER;
|
||||
C_OPTIMIZE_GOAL : INTEGER;
|
||||
HAS_NEGATE : INTEGER;
|
||||
SINGLE_OUTPUT : INTEGER;
|
||||
ROUND : INTEGER;
|
||||
USE_DSP_CASCADES : INTEGER;
|
||||
C_THROTTLE_SCHEME : INTEGER;
|
||||
C_HAS_ACLKEN : INTEGER;
|
||||
C_HAS_ARESETN : INTEGER;
|
||||
C_HAS_S_AXIS_A_TUSER : INTEGER;
|
||||
C_HAS_S_AXIS_A_TLAST : INTEGER;
|
||||
C_HAS_S_AXIS_B_TUSER : INTEGER;
|
||||
C_HAS_S_AXIS_B_TLAST : INTEGER;
|
||||
C_HAS_S_AXIS_CTRL_TUSER : INTEGER;
|
||||
C_HAS_S_AXIS_CTRL_TLAST : INTEGER;
|
||||
C_TLAST_RESOLUTION : INTEGER;
|
||||
C_S_AXIS_A_TDATA_WIDTH : INTEGER;
|
||||
C_S_AXIS_A_TUSER_WIDTH : INTEGER;
|
||||
C_S_AXIS_B_TDATA_WIDTH : INTEGER;
|
||||
C_S_AXIS_B_TUSER_WIDTH : INTEGER;
|
||||
C_S_AXIS_CTRL_TDATA_WIDTH : INTEGER;
|
||||
C_S_AXIS_CTRL_TUSER_WIDTH : INTEGER;
|
||||
C_M_AXIS_DOUT_TDATA_WIDTH : INTEGER;
|
||||
C_M_AXIS_DOUT_TUSER_WIDTH : INTEGER
|
||||
);
|
||||
PORT (
|
||||
aclk : IN STD_LOGIC;
|
||||
aclken : IN STD_LOGIC;
|
||||
aresetn : IN STD_LOGIC;
|
||||
s_axis_a_tvalid : IN STD_LOGIC;
|
||||
s_axis_a_tready : OUT STD_LOGIC;
|
||||
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axis_a_tlast : IN STD_LOGIC;
|
||||
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axis_b_tvalid : IN STD_LOGIC;
|
||||
s_axis_b_tready : OUT STD_LOGIC;
|
||||
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axis_b_tlast : IN STD_LOGIC;
|
||||
s_axis_b_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
s_axis_ctrl_tvalid : IN STD_LOGIC;
|
||||
s_axis_ctrl_tready : OUT STD_LOGIC;
|
||||
s_axis_ctrl_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axis_ctrl_tlast : IN STD_LOGIC;
|
||||
s_axis_ctrl_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
m_axis_dout_tvalid : OUT STD_LOGIC;
|
||||
m_axis_dout_tready : IN STD_LOGIC;
|
||||
m_axis_dout_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axis_dout_tlast : OUT STD_LOGIC;
|
||||
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT cmpy_v6_0_17;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TDATA";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_dout_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_DOUT, TDATA_NUM_BYTES 6, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_b_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_B, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_a_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_A, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_CTRL:S_AXIS_B:S_AXIS_A:M_AXIS_DOUT, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 10000000, PHASE 0.000, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
|
||||
BEGIN
|
||||
U0 : cmpy_v6_0_17
|
||||
GENERIC MAP (
|
||||
C_VERBOSITY => 0,
|
||||
C_XDEVICEFAMILY => "kintex7",
|
||||
C_XDEVICE => "xc7k410t",
|
||||
C_A_WIDTH => 12,
|
||||
C_B_WIDTH => 8,
|
||||
C_OUT_WIDTH => 21,
|
||||
C_LATENCY => 4,
|
||||
C_MULT_TYPE => 0,
|
||||
C_OPTIMIZE_GOAL => 0,
|
||||
HAS_NEGATE => 0,
|
||||
SINGLE_OUTPUT => 0,
|
||||
ROUND => 0,
|
||||
USE_DSP_CASCADES => 1,
|
||||
C_THROTTLE_SCHEME => 3,
|
||||
C_HAS_ACLKEN => 0,
|
||||
C_HAS_ARESETN => 0,
|
||||
C_HAS_S_AXIS_A_TUSER => 0,
|
||||
C_HAS_S_AXIS_A_TLAST => 0,
|
||||
C_HAS_S_AXIS_B_TUSER => 0,
|
||||
C_HAS_S_AXIS_B_TLAST => 0,
|
||||
C_HAS_S_AXIS_CTRL_TUSER => 0,
|
||||
C_HAS_S_AXIS_CTRL_TLAST => 0,
|
||||
C_TLAST_RESOLUTION => 0,
|
||||
C_S_AXIS_A_TDATA_WIDTH => 32,
|
||||
C_S_AXIS_A_TUSER_WIDTH => 1,
|
||||
C_S_AXIS_B_TDATA_WIDTH => 16,
|
||||
C_S_AXIS_B_TUSER_WIDTH => 1,
|
||||
C_S_AXIS_CTRL_TDATA_WIDTH => 8,
|
||||
C_S_AXIS_CTRL_TUSER_WIDTH => 1,
|
||||
C_M_AXIS_DOUT_TDATA_WIDTH => 48,
|
||||
C_M_AXIS_DOUT_TUSER_WIDTH => 1
|
||||
)
|
||||
PORT MAP (
|
||||
aclk => aclk,
|
||||
aclken => '1',
|
||||
aresetn => '1',
|
||||
s_axis_a_tvalid => s_axis_a_tvalid,
|
||||
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axis_a_tlast => '0',
|
||||
s_axis_a_tdata => s_axis_a_tdata,
|
||||
s_axis_b_tvalid => s_axis_b_tvalid,
|
||||
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axis_b_tlast => '0',
|
||||
s_axis_b_tdata => s_axis_b_tdata,
|
||||
s_axis_ctrl_tvalid => '0',
|
||||
s_axis_ctrl_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axis_ctrl_tlast => '0',
|
||||
s_axis_ctrl_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
|
||||
m_axis_dout_tvalid => m_axis_dout_tvalid,
|
||||
m_axis_dout_tready => '0',
|
||||
m_axis_dout_tdata => m_axis_dout_tdata
|
||||
);
|
||||
END cmpy_12x8_arch;
|
||||
+71
@@ -0,0 +1,71 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
// IP VLNV: xilinx.com:ip:dds_compiler:6.0
|
||||
// IP Revision: 18
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
dds_32b_8b_comp your_instance_name (
|
||||
.aclk(aclk), // input wire aclk
|
||||
.s_axis_config_tvalid(s_axis_config_tvalid), // input wire s_axis_config_tvalid
|
||||
.s_axis_config_tdata(s_axis_config_tdata), // input wire [63 : 0] s_axis_config_tdata
|
||||
.m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata(m_axis_data_tdata), // output wire [15 : 0] m_axis_data_tdata
|
||||
.m_axis_phase_tvalid(m_axis_phase_tvalid), // output wire m_axis_phase_tvalid
|
||||
.m_axis_phase_tdata(m_axis_phase_tdata) // output wire [31 : 0] m_axis_phase_tdata
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file dds_32b_8b_comp.v when simulating
|
||||
// the core, dds_32b_8b_comp. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
+87
@@ -0,0 +1,87 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:dds_compiler:6.0
|
||||
-- IP Revision: 18
|
||||
|
||||
-- The following code must appear in the VHDL architecture header.
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
COMPONENT dds_32b_8b_comp
|
||||
PORT (
|
||||
aclk : IN STD_LOGIC;
|
||||
s_axis_config_tvalid : IN STD_LOGIC;
|
||||
s_axis_config_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
m_axis_data_tvalid : OUT STD_LOGIC;
|
||||
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
m_axis_phase_tvalid : OUT STD_LOGIC;
|
||||
m_axis_phase_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : dds_32b_8b_comp
|
||||
PORT MAP (
|
||||
aclk => aclk,
|
||||
s_axis_config_tvalid => s_axis_config_tvalid,
|
||||
s_axis_config_tdata => s_axis_config_tdata,
|
||||
m_axis_data_tvalid => m_axis_data_tvalid,
|
||||
m_axis_data_tdata => m_axis_data_tdata,
|
||||
m_axis_phase_tvalid => m_axis_phase_tvalid,
|
||||
m_axis_phase_tdata => m_axis_phase_tdata
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
-- You must compile the wrapper file dds_32b_8b_comp.vhd when simulating
|
||||
-- the core, dds_32b_8b_comp. When compiling the wrapper file, be sure to
|
||||
-- reference the VHDL simulation library.
|
||||
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
+28
@@ -0,0 +1,28 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Mon May 8 00:29:10 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp_stub.v
|
||||
// Design : dds_32b_8b_comp
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "dds_compiler_v6_0_18,Vivado 2019.1.3" *)
|
||||
module dds_32b_8b_comp(aclk, s_axis_config_tvalid,
|
||||
s_axis_config_tdata, m_axis_data_tvalid, m_axis_data_tdata, m_axis_phase_tvalid,
|
||||
m_axis_phase_tdata)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_config_tvalid,s_axis_config_tdata[63:0],m_axis_data_tvalid,m_axis_data_tdata[15:0],m_axis_phase_tvalid,m_axis_phase_tdata[31:0]" */;
|
||||
input aclk;
|
||||
input s_axis_config_tvalid;
|
||||
input [63:0]s_axis_config_tdata;
|
||||
output m_axis_data_tvalid;
|
||||
output [15:0]m_axis_data_tdata;
|
||||
output m_axis_phase_tvalid;
|
||||
output [31:0]m_axis_phase_tdata;
|
||||
endmodule
|
||||
+36
@@ -0,0 +1,36 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Mon May 8 00:29:10 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/dds_32b_8b_comp_synth_1/dds_32b_8b_comp_stub.vhdl
|
||||
-- Design : dds_32b_8b_comp
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity dds_32b_8b_comp is
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
s_axis_config_tvalid : in STD_LOGIC;
|
||||
s_axis_config_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
|
||||
m_axis_data_tvalid : out STD_LOGIC;
|
||||
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
m_axis_phase_tvalid : out STD_LOGIC;
|
||||
m_axis_phase_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
|
||||
end dds_32b_8b_comp;
|
||||
|
||||
architecture stub of dds_32b_8b_comp is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_config_tvalid,s_axis_config_tdata[63:0],m_axis_data_tvalid,m_axis_data_tdata[15:0],m_axis_phase_tvalid,m_axis_phase_tdata[31:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "dds_compiler_v6_0_18,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+261
@@ -0,0 +1,261 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--------------------------------------------------------------------------------
|
||||
-- Description:
|
||||
-- This is an example testbench for the DDS Compiler IP core.
|
||||
-- The testbench has been generated by Vivado to accompany the IP core
|
||||
-- instance you have generated.
|
||||
--
|
||||
-- This testbench is for demonstration purposes only. See note below for
|
||||
-- instructions on how to use it with your core.
|
||||
--
|
||||
-- See the DDS Compiler product guide for further information
|
||||
-- about this core.
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Using this testbench
|
||||
--
|
||||
-- This testbench instantiates your generated DDS Compiler core
|
||||
-- instance named "dds_32b_8b_comp".
|
||||
--
|
||||
-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado
|
||||
-- documentation for details.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee.math_real.all;
|
||||
|
||||
entity tb_dds_32b_8b_comp is
|
||||
end tb_dds_32b_8b_comp;
|
||||
|
||||
architecture tb of tb_dds_32b_8b_comp is
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Timing constants
|
||||
-----------------------------------------------------------------------
|
||||
constant CLOCK_PERIOD : time := 100 ns;
|
||||
constant T_HOLD : time := 10 ns;
|
||||
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- DUT input signals
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
-- General inputs
|
||||
signal aclk : std_logic := '0'; -- the master clock
|
||||
|
||||
-- Config slave channel signals
|
||||
signal s_axis_config_tvalid : std_logic := '0'; -- payload is valid
|
||||
signal s_axis_config_tdata : std_logic_vector(63 downto 0) := (others => '0'); -- data payload
|
||||
|
||||
-- Data master channel signals
|
||||
signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid
|
||||
signal m_axis_data_tdata : std_logic_vector(15 downto 0) := (others => '0'); -- data payload
|
||||
|
||||
-- Phase master channel signals
|
||||
signal m_axis_phase_tvalid : std_logic := '0'; -- payload is valid
|
||||
signal m_axis_phase_tdata : std_logic_vector(31 downto 0) := (others => '0'); -- data payload
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Aliases for AXI channel TDATA and TUSER fields
|
||||
-- These are a convenience for viewing data in a simulator waveform viewer.
|
||||
-- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
|
||||
-- to prevent the simulator optimizing away these signals.
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
-- Config slave channel alias signals
|
||||
signal s_axis_config_tdata_inc : std_logic_vector(31 downto 0) := (others => '0');
|
||||
signal s_axis_config_tdata_off : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
-- Data master channel alias signals
|
||||
signal m_axis_data_tdata_cosine : std_logic_vector(7 downto 0) := (others => '0');
|
||||
signal m_axis_data_tdata_sine : std_logic_vector(7 downto 0) := (others => '0');
|
||||
|
||||
-- Phase master channel alias signals
|
||||
signal m_axis_phase_tdata_phase : std_logic_vector(31 downto 0) := (others => '0');
|
||||
|
||||
|
||||
signal end_of_simulation : boolean := false;
|
||||
|
||||
begin
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Instantiate the DUT
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
dut : entity work.dds_32b_8b_comp
|
||||
port map (
|
||||
aclk => aclk
|
||||
,s_axis_config_tvalid => s_axis_config_tvalid
|
||||
,s_axis_config_tdata => s_axis_config_tdata
|
||||
,m_axis_data_tvalid => m_axis_data_tvalid
|
||||
,m_axis_data_tdata => m_axis_data_tdata
|
||||
,m_axis_phase_tvalid => m_axis_phase_tvalid
|
||||
,m_axis_phase_tdata => m_axis_phase_tdata
|
||||
);
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Generate clock
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
clock_gen : process
|
||||
begin
|
||||
aclk <= '0';
|
||||
if (end_of_simulation) then
|
||||
wait;
|
||||
else
|
||||
wait for CLOCK_PERIOD;
|
||||
loop
|
||||
aclk <= '0';
|
||||
wait for CLOCK_PERIOD/2;
|
||||
aclk <= '1';
|
||||
wait for CLOCK_PERIOD/2;
|
||||
end loop;
|
||||
end if;
|
||||
end process clock_gen;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Generate inputs
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
stimuli : process
|
||||
begin
|
||||
|
||||
-- Drive inputs T_HOLD time after rising edge of clock
|
||||
wait until rising_edge(aclk);
|
||||
wait for T_HOLD;
|
||||
|
||||
-- Program the core with the initial configuration.
|
||||
-- The phase increment and phase offset values here are derived from the output frequency and
|
||||
-- phase offset angle values set in the CORE Generator GUI.
|
||||
s_axis_config_tvalid <= '1';
|
||||
s_axis_config_tdata <= (others => '0'); -- set unused TDATA bits to zero
|
||||
s_axis_config_tdata(31 downto 0) <= "00000000000000001101000110110111"; -- phase increment
|
||||
s_axis_config_tdata(63 downto 32) <= "00000000000000000000000000000000"; -- phase offset
|
||||
wait for CLOCK_PERIOD;
|
||||
s_axis_config_tvalid <= '0';
|
||||
|
||||
-- Run for long enough to produce 5 periods of outputs
|
||||
wait for CLOCK_PERIOD * 400001;
|
||||
|
||||
-- Configure the core with a different configuration:
|
||||
-- set phase increment to half of its current value
|
||||
-- set phase offset to its current value plus PI radians
|
||||
s_axis_config_tvalid <= '1';
|
||||
s_axis_config_tdata <= (others => '0'); -- set unused TDATA bits to zero
|
||||
s_axis_config_tdata(31 downto 0) <= "00000000000000000110100011011011"; -- current phase increment / 2
|
||||
s_axis_config_tdata(63 downto 32) <= "10000000000000000000000000000000"; -- current phase offset + PI radians
|
||||
wait for CLOCK_PERIOD;
|
||||
s_axis_config_tvalid <= '0';
|
||||
|
||||
-- Run for long enough to produce 5 periods of outputs
|
||||
wait for CLOCK_PERIOD * 800002;
|
||||
|
||||
-- End of test
|
||||
end_of_simulation <= true;
|
||||
report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;
|
||||
wait;
|
||||
|
||||
end process stimuli;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Check outputs
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
check_outputs : process
|
||||
variable check_ok : boolean := true;
|
||||
begin
|
||||
|
||||
-- Check outputs T_STROBE time after rising edge of clock
|
||||
wait until rising_edge(aclk);
|
||||
wait for T_STROBE;
|
||||
|
||||
-- Do not check the output payload values, as this requires the behavioral model
|
||||
-- which would make this demonstration testbench unwieldy.
|
||||
-- Instead, check the protocol of the data and phase master channels:
|
||||
-- check that the payload is valid (not X) when TVALID is high
|
||||
|
||||
if m_axis_data_tvalid = '1' then
|
||||
if is_x(m_axis_data_tdata) then
|
||||
report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error;
|
||||
check_ok := false;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
if m_axis_phase_tvalid = '1' then
|
||||
if is_x(m_axis_phase_tdata) then
|
||||
report "ERROR: m_axis_phase_tdata is invalid when m_axis_phase_tvalid is high" severity error;
|
||||
check_ok := false;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
assert check_ok
|
||||
report "ERROR: terminating test with failures." severity failure;
|
||||
|
||||
end process check_outputs;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Assign TDATA fields to aliases, for easy simulator waveform viewing
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
-- Config slave channel alias signals
|
||||
s_axis_config_tdata_inc <= s_axis_config_tdata(31 downto 0);
|
||||
s_axis_config_tdata_off <= s_axis_config_tdata(63 downto 32);
|
||||
|
||||
-- Data master channel alias signals: update these only when they are valid
|
||||
m_axis_data_tdata_cosine <= m_axis_data_tdata(7 downto 0) when m_axis_data_tvalid = '1';
|
||||
m_axis_data_tdata_sine <= m_axis_data_tdata(15 downto 8) when m_axis_data_tvalid = '1';
|
||||
|
||||
-- Phase master channel alias signals: update these only when they are valid
|
||||
m_axis_phase_tdata_phase <= m_axis_phase_tdata(31 downto 0) when m_axis_phase_tvalid = '1';
|
||||
|
||||
end tb;
|
||||
|
||||
+239
@@ -0,0 +1,239 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:dds_compiler:6.0
|
||||
-- IP Revision: 18
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY dds_compiler_v6_0_18;
|
||||
USE dds_compiler_v6_0_18.dds_compiler_v6_0_18;
|
||||
|
||||
ENTITY dds_32b_8b_comp IS
|
||||
PORT (
|
||||
aclk : IN STD_LOGIC;
|
||||
s_axis_config_tvalid : IN STD_LOGIC;
|
||||
s_axis_config_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
m_axis_data_tvalid : OUT STD_LOGIC;
|
||||
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
m_axis_phase_tvalid : OUT STD_LOGIC;
|
||||
m_axis_phase_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END dds_32b_8b_comp;
|
||||
|
||||
ARCHITECTURE dds_32b_8b_comp_arch OF dds_32b_8b_comp IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF dds_32b_8b_comp_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT dds_compiler_v6_0_18 IS
|
||||
GENERIC (
|
||||
C_XDEVICEFAMILY : STRING;
|
||||
C_MODE_OF_OPERATION : INTEGER;
|
||||
C_MODULUS : INTEGER;
|
||||
C_ACCUMULATOR_WIDTH : INTEGER;
|
||||
C_CHANNELS : INTEGER;
|
||||
C_HAS_PHASE_OUT : INTEGER;
|
||||
C_HAS_PHASEGEN : INTEGER;
|
||||
C_HAS_SINCOS : INTEGER;
|
||||
C_LATENCY : INTEGER;
|
||||
C_MEM_TYPE : INTEGER;
|
||||
C_NEGATIVE_COSINE : INTEGER;
|
||||
C_NEGATIVE_SINE : INTEGER;
|
||||
C_NOISE_SHAPING : INTEGER;
|
||||
C_OUTPUTS_REQUIRED : INTEGER;
|
||||
C_OUTPUT_FORM : INTEGER;
|
||||
C_OUTPUT_WIDTH : INTEGER;
|
||||
C_PHASE_ANGLE_WIDTH : INTEGER;
|
||||
C_PHASE_INCREMENT : INTEGER;
|
||||
C_PHASE_INCREMENT_VALUE : STRING;
|
||||
C_RESYNC : INTEGER;
|
||||
C_PHASE_OFFSET : INTEGER;
|
||||
C_PHASE_OFFSET_VALUE : STRING;
|
||||
C_OPTIMISE_GOAL : INTEGER;
|
||||
C_USE_DSP48 : INTEGER;
|
||||
C_POR_MODE : INTEGER;
|
||||
C_AMPLITUDE : INTEGER;
|
||||
C_HAS_ACLKEN : INTEGER;
|
||||
C_HAS_ARESETN : INTEGER;
|
||||
C_HAS_TLAST : INTEGER;
|
||||
C_HAS_TREADY : INTEGER;
|
||||
C_HAS_S_PHASE : INTEGER;
|
||||
C_S_PHASE_TDATA_WIDTH : INTEGER;
|
||||
C_S_PHASE_HAS_TUSER : INTEGER;
|
||||
C_S_PHASE_TUSER_WIDTH : INTEGER;
|
||||
C_HAS_S_CONFIG : INTEGER;
|
||||
C_S_CONFIG_SYNC_MODE : INTEGER;
|
||||
C_S_CONFIG_TDATA_WIDTH : INTEGER;
|
||||
C_HAS_M_DATA : INTEGER;
|
||||
C_M_DATA_TDATA_WIDTH : INTEGER;
|
||||
C_M_DATA_HAS_TUSER : INTEGER;
|
||||
C_M_DATA_TUSER_WIDTH : INTEGER;
|
||||
C_HAS_M_PHASE : INTEGER;
|
||||
C_M_PHASE_TDATA_WIDTH : INTEGER;
|
||||
C_M_PHASE_HAS_TUSER : INTEGER;
|
||||
C_M_PHASE_TUSER_WIDTH : INTEGER;
|
||||
C_DEBUG_INTERFACE : INTEGER;
|
||||
C_CHAN_WIDTH : INTEGER
|
||||
);
|
||||
PORT (
|
||||
aclk : IN STD_LOGIC;
|
||||
aclken : IN STD_LOGIC;
|
||||
aresetn : IN STD_LOGIC;
|
||||
s_axis_phase_tvalid : IN STD_LOGIC;
|
||||
s_axis_phase_tready : OUT STD_LOGIC;
|
||||
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axis_phase_tlast : IN STD_LOGIC;
|
||||
s_axis_phase_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axis_config_tvalid : IN STD_LOGIC;
|
||||
s_axis_config_tready : OUT STD_LOGIC;
|
||||
s_axis_config_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
|
||||
s_axis_config_tlast : IN STD_LOGIC;
|
||||
m_axis_data_tvalid : OUT STD_LOGIC;
|
||||
m_axis_data_tready : IN STD_LOGIC;
|
||||
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
m_axis_data_tlast : OUT STD_LOGIC;
|
||||
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axis_phase_tvalid : OUT STD_LOGIC;
|
||||
m_axis_phase_tready : IN STD_LOGIC;
|
||||
m_axis_phase_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axis_phase_tlast : OUT STD_LOGIC;
|
||||
m_axis_phase_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
event_pinc_invalid : OUT STD_LOGIC;
|
||||
event_poff_invalid : OUT STD_LOGIC;
|
||||
event_phase_in_invalid : OUT STD_LOGIC;
|
||||
event_s_phase_tlast_missing : OUT STD_LOGIC;
|
||||
event_s_phase_tlast_unexpected : OUT STD_LOGIC;
|
||||
event_s_phase_chanid_incorrect : OUT STD_LOGIC;
|
||||
event_s_config_tlast_missing : OUT STD_LOGIC;
|
||||
event_s_config_tlast_unexpected : OUT STD_LOGIC
|
||||
);
|
||||
END COMPONENT dds_compiler_v6_0_18;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_phase_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_PHASE TDATA";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_phase_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_PHASE, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_phase_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_PHASE TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_DATA, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_config_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CONFIG TDATA";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_config_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_CONFIG, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_config_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CONFIG TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF M_AXIS_PHASE:S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_PHASE, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
|
||||
BEGIN
|
||||
U0 : dds_compiler_v6_0_18
|
||||
GENERIC MAP (
|
||||
C_XDEVICEFAMILY => "kintex7",
|
||||
C_MODE_OF_OPERATION => 0,
|
||||
C_MODULUS => 9,
|
||||
C_ACCUMULATOR_WIDTH => 32,
|
||||
C_CHANNELS => 1,
|
||||
C_HAS_PHASE_OUT => 1,
|
||||
C_HAS_PHASEGEN => 1,
|
||||
C_HAS_SINCOS => 1,
|
||||
C_LATENCY => 4,
|
||||
C_MEM_TYPE => 1,
|
||||
C_NEGATIVE_COSINE => 0,
|
||||
C_NEGATIVE_SINE => 0,
|
||||
C_NOISE_SHAPING => 0,
|
||||
C_OUTPUTS_REQUIRED => 2,
|
||||
C_OUTPUT_FORM => 0,
|
||||
C_OUTPUT_WIDTH => 8,
|
||||
C_PHASE_ANGLE_WIDTH => 8,
|
||||
C_PHASE_INCREMENT => 1,
|
||||
C_PHASE_INCREMENT_VALUE => "1101000110110111,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
|
||||
C_RESYNC => 0,
|
||||
C_PHASE_OFFSET => 1,
|
||||
C_PHASE_OFFSET_VALUE => "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
|
||||
C_OPTIMISE_GOAL => 0,
|
||||
C_USE_DSP48 => 0,
|
||||
C_POR_MODE => 0,
|
||||
C_AMPLITUDE => 0,
|
||||
C_HAS_ACLKEN => 0,
|
||||
C_HAS_ARESETN => 0,
|
||||
C_HAS_TLAST => 0,
|
||||
C_HAS_TREADY => 0,
|
||||
C_HAS_S_PHASE => 0,
|
||||
C_S_PHASE_TDATA_WIDTH => 1,
|
||||
C_S_PHASE_HAS_TUSER => 0,
|
||||
C_S_PHASE_TUSER_WIDTH => 1,
|
||||
C_HAS_S_CONFIG => 1,
|
||||
C_S_CONFIG_SYNC_MODE => 0,
|
||||
C_S_CONFIG_TDATA_WIDTH => 64,
|
||||
C_HAS_M_DATA => 1,
|
||||
C_M_DATA_TDATA_WIDTH => 16,
|
||||
C_M_DATA_HAS_TUSER => 0,
|
||||
C_M_DATA_TUSER_WIDTH => 1,
|
||||
C_HAS_M_PHASE => 1,
|
||||
C_M_PHASE_TDATA_WIDTH => 32,
|
||||
C_M_PHASE_HAS_TUSER => 0,
|
||||
C_M_PHASE_TUSER_WIDTH => 1,
|
||||
C_DEBUG_INTERFACE => 0,
|
||||
C_CHAN_WIDTH => 1
|
||||
)
|
||||
PORT MAP (
|
||||
aclk => aclk,
|
||||
aclken => '1',
|
||||
aresetn => '1',
|
||||
s_axis_phase_tvalid => '0',
|
||||
s_axis_phase_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axis_phase_tlast => '0',
|
||||
s_axis_phase_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axis_config_tvalid => s_axis_config_tvalid,
|
||||
s_axis_config_tdata => s_axis_config_tdata,
|
||||
s_axis_config_tlast => '0',
|
||||
m_axis_data_tvalid => m_axis_data_tvalid,
|
||||
m_axis_data_tready => '0',
|
||||
m_axis_data_tdata => m_axis_data_tdata,
|
||||
m_axis_phase_tvalid => m_axis_phase_tvalid,
|
||||
m_axis_phase_tready => '0',
|
||||
m_axis_phase_tdata => m_axis_phase_tdata
|
||||
);
|
||||
END dds_32b_8b_comp_arch;
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
+26
-15
@@ -60,7 +60,7 @@
|
||||
-- Using this testbench
|
||||
--
|
||||
-- This testbench instantiates your generated FIR Compiler core
|
||||
-- instance named "fir_dmf_invert_prbs7_deci8".
|
||||
-- instance named "fir_prbs7_invert_rep4".
|
||||
--
|
||||
-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado
|
||||
-- documentation for details.
|
||||
@@ -70,10 +70,10 @@ library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity tb_fir_dmf_invert_prbs7_deci8 is
|
||||
end tb_fir_dmf_invert_prbs7_deci8;
|
||||
entity tb_fir_prbs7_invert_rep4 is
|
||||
end tb_fir_prbs7_invert_rep4;
|
||||
|
||||
architecture tb of tb_fir_dmf_invert_prbs7_deci8 is
|
||||
architecture tb of tb_fir_prbs7_invert_rep4 is
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Timing constants
|
||||
@@ -88,6 +88,7 @@ architecture tb of tb_fir_dmf_invert_prbs7_deci8 is
|
||||
|
||||
-- General signals
|
||||
signal aclk : std_logic := '0'; -- the master clock
|
||||
signal aresetn : std_logic := '1'; -- synchronous active low reset
|
||||
|
||||
-- Data slave channel signals
|
||||
signal s_axis_data_tvalid : std_logic := '0'; -- payload is valid
|
||||
@@ -109,7 +110,7 @@ architecture tb of tb_fir_dmf_invert_prbs7_deci8 is
|
||||
signal s_axis_data_tdata_data : std_logic_vector(11 downto 0) := (others => '0');
|
||||
|
||||
-- Data master channel alias signals
|
||||
signal m_axis_data_tdata_data : std_logic_vector(18 downto 0) := (others => '0');
|
||||
signal m_axis_data_tdata_data : std_logic_vector(20 downto 0) := (others => '0');
|
||||
|
||||
|
||||
begin
|
||||
@@ -118,9 +119,10 @@ begin
|
||||
-- Instantiate the DUT
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
dut : entity work.fir_dmf_invert_prbs7_deci8
|
||||
dut : entity work.fir_prbs7_invert_rep4
|
||||
port map (
|
||||
aclk => aclk,
|
||||
aresetn => aresetn,
|
||||
s_axis_data_tvalid => s_axis_data_tvalid,
|
||||
s_axis_data_tready => s_axis_data_tready,
|
||||
s_axis_data_tdata => s_axis_data_tdata,
|
||||
@@ -167,9 +169,9 @@ begin
|
||||
end loop;
|
||||
ip_count := ip_count + 1;
|
||||
wait for T_HOLD;
|
||||
-- Input rate is 1 input each 8 clock cycles: drive valid inputs at this rate
|
||||
-- Input rate is 1 input each 2 clock cycles: drive valid inputs at this rate
|
||||
s_axis_data_tvalid <= '0';
|
||||
wait for CLOCK_PERIOD * 7;
|
||||
wait for CLOCK_PERIOD * 1;
|
||||
exit when ip_count >= samples;
|
||||
end loop;
|
||||
end procedure drive_data;
|
||||
@@ -183,7 +185,7 @@ begin
|
||||
|
||||
-- Procedure to drive an impulse and let the impulse response emerge on the data master channel
|
||||
-- samples is the number of input samples to drive; default is enough for impulse response output to emerge
|
||||
procedure drive_impulse ( samples : natural := 136 ) is
|
||||
procedure drive_impulse ( samples : natural := 651 ) is
|
||||
variable impulse : std_logic_vector(15 downto 0);
|
||||
begin
|
||||
impulse := (others => '0'); -- initialize unused bits to zero
|
||||
@@ -197,7 +199,7 @@ begin
|
||||
begin
|
||||
|
||||
-- Drive inputs T_HOLD time after rising edge of clock
|
||||
wait until rising_edge(aclk);
|
||||
wait until rising_edge(aclk) and aresetn = '1';
|
||||
wait for T_HOLD;
|
||||
|
||||
-- Drive a single impulse and let the impulse response emerge
|
||||
@@ -206,11 +208,20 @@ begin
|
||||
-- Drive another impulse, during which demonstrate use and effect of AXI handshaking signals
|
||||
drive_impulse(2); -- start of impulse; data is now zero
|
||||
s_axis_data_tvalid <= '0';
|
||||
wait for CLOCK_PERIOD * 40; -- provide no data for 5 input samples worth
|
||||
wait for CLOCK_PERIOD * 10; -- provide no data for 5 input samples worth
|
||||
drive_zeros(2); -- 2 normal input samples
|
||||
s_axis_data_tvalid <= '1';
|
||||
wait for CLOCK_PERIOD * 40; -- provide data as fast as the core can accept it for 5 input samples worth
|
||||
drive_zeros(127); -- back to normal operation
|
||||
wait for CLOCK_PERIOD * 10; -- provide data as fast as the core can accept it for 5 input samples worth
|
||||
drive_zeros(642); -- back to normal operation
|
||||
|
||||
-- Drive another impulse, during which demonstrate:
|
||||
-- reset (aresetn)
|
||||
drive_impulse(262); -- to partway through impulse response
|
||||
s_axis_data_tvalid <= '0';
|
||||
aresetn <= '0'; -- assert reset (active low)
|
||||
wait for CLOCK_PERIOD * 2; -- hold reset active for 2 clock cycles, as recommended in FIR Compiler Datasheet
|
||||
aresetn <= '1'; -- deassert reset
|
||||
drive_impulse; -- send new impulse, following reset
|
||||
|
||||
-- End of test
|
||||
report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;
|
||||
@@ -235,7 +246,7 @@ begin
|
||||
-- Instead, check the protocol of the master DATA channel:
|
||||
-- check that the payload is valid (not X) when TVALID is high
|
||||
|
||||
if m_axis_data_tvalid = '1' then
|
||||
if m_axis_data_tvalid = '1' and aresetn = '1' then
|
||||
if is_x(m_axis_data_tdata) then
|
||||
report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error;
|
||||
check_ok := false;
|
||||
@@ -256,6 +267,6 @@ begin
|
||||
s_axis_data_tdata_data <= s_axis_data_tdata(11 downto 0);
|
||||
|
||||
-- Data master channel alias signals: update these only when they are valid
|
||||
m_axis_data_tdata_data <= m_axis_data_tdata(18 downto 0) when m_axis_data_tvalid = '1';
|
||||
m_axis_data_tdata_data <= m_axis_data_tdata(20 downto 0) when m_axis_data_tvalid = '1';
|
||||
|
||||
end tb;
|
||||
+4
-3
@@ -54,7 +54,8 @@
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
fir_dmf_invert_prbs7_deci8 your_instance_name (
|
||||
fir_prbs7_invert_rep4 your_instance_name (
|
||||
.aresetn(aresetn), // input wire aresetn
|
||||
.aclk(aclk), // input wire aclk
|
||||
.s_axis_data_tvalid(s_axis_data_tvalid), // input wire s_axis_data_tvalid
|
||||
.s_axis_data_tready(s_axis_data_tready), // output wire s_axis_data_tready
|
||||
@@ -64,7 +65,7 @@ fir_dmf_invert_prbs7_deci8 your_instance_name (
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file fir_dmf_invert_prbs7_deci8.v when simulating
|
||||
// the core, fir_dmf_invert_prbs7_deci8. When compiling the wrapper file, be sure to
|
||||
// You must compile the wrapper file fir_prbs7_invert_rep4.v when simulating
|
||||
// the core, fir_prbs7_invert_rep4. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
+6
-4
@@ -52,8 +52,9 @@
|
||||
-- The following code must appear in the VHDL architecture header.
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
COMPONENT fir_dmf_invert_prbs7_deci8
|
||||
COMPONENT fir_prbs7_invert_rep4
|
||||
PORT (
|
||||
aresetn : IN STD_LOGIC;
|
||||
aclk : IN STD_LOGIC;
|
||||
s_axis_data_tvalid : IN STD_LOGIC;
|
||||
s_axis_data_tready : OUT STD_LOGIC;
|
||||
@@ -68,8 +69,9 @@ END COMPONENT;
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : fir_dmf_invert_prbs7_deci8
|
||||
your_instance_name : fir_prbs7_invert_rep4
|
||||
PORT MAP (
|
||||
aresetn => aresetn,
|
||||
aclk => aclk,
|
||||
s_axis_data_tvalid => s_axis_data_tvalid,
|
||||
s_axis_data_tready => s_axis_data_tready,
|
||||
@@ -79,7 +81,7 @@ your_instance_name : fir_dmf_invert_prbs7_deci8
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
-- You must compile the wrapper file fir_dmf_invert_prbs7_deci8.vhd when simulating
|
||||
-- the core, fir_dmf_invert_prbs7_deci8. When compiling the wrapper file, be sure to
|
||||
-- You must compile the wrapper file fir_prbs7_invert_rep4.vhd when simulating
|
||||
-- the core, fir_prbs7_invert_rep4. When compiling the wrapper file, be sure to
|
||||
-- reference the VHDL simulation library.
|
||||
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
+8
-7
@@ -1,11 +1,11 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Thu May 4 17:18:49 2023
|
||||
// Date : Sun May 7 09:32:08 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_dmf_invert_prbs7_deci8_synth_1/fir_dmf_invert_prbs7_deci8_stub.v
|
||||
// Design : fir_dmf_invert_prbs7_deci8
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top fir_prbs7_invert_rep4 -prefix
|
||||
// fir_prbs7_invert_rep4_ fir_prbs7_invert_rep4_stub.v
|
||||
// Design : fir_prbs7_invert_rep4
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
@@ -14,9 +14,10 @@
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "fir_compiler_v7_2_12,Vivado 2019.1.3" *)
|
||||
module fir_dmf_invert_prbs7_deci8(aclk, s_axis_data_tvalid, s_axis_data_tready,
|
||||
s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[15:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]" */;
|
||||
module fir_prbs7_invert_rep4(aresetn, aclk, s_axis_data_tvalid,
|
||||
s_axis_data_tready, s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aresetn,aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[15:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]" */;
|
||||
input aresetn;
|
||||
input aclk;
|
||||
input s_axis_data_tvalid;
|
||||
output s_axis_data_tready;
|
||||
+9
-8
@@ -1,19 +1,20 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Thu May 4 17:18:49 2023
|
||||
-- Date : Sun May 7 09:32:08 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/fir_dmf_invert_prbs7_deci8_synth_1/fir_dmf_invert_prbs7_deci8_stub.vhdl
|
||||
-- Design : fir_dmf_invert_prbs7_deci8
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top fir_prbs7_invert_rep4 -prefix
|
||||
-- fir_prbs7_invert_rep4_ fir_prbs7_invert_rep4_stub.vhdl
|
||||
-- Design : fir_prbs7_invert_rep4
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity fir_dmf_invert_prbs7_deci8 is
|
||||
entity fir_prbs7_invert_rep4 is
|
||||
Port (
|
||||
aresetn : in STD_LOGIC;
|
||||
aclk : in STD_LOGIC;
|
||||
s_axis_data_tvalid : in STD_LOGIC;
|
||||
s_axis_data_tready : out STD_LOGIC;
|
||||
@@ -22,13 +23,13 @@ entity fir_dmf_invert_prbs7_deci8 is
|
||||
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 )
|
||||
);
|
||||
|
||||
end fir_dmf_invert_prbs7_deci8;
|
||||
end fir_prbs7_invert_rep4;
|
||||
|
||||
architecture stub of fir_dmf_invert_prbs7_deci8 is
|
||||
architecture stub of fir_prbs7_invert_rep4 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[15:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]";
|
||||
attribute black_box_pad_pin of stub : architecture is "aresetn,aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[15:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "fir_compiler_v7_2_12,Vivado 2019.1.3";
|
||||
begin
|
||||
+24
-21
@@ -56,8 +56,9 @@ USE ieee.numeric_std.ALL;
|
||||
LIBRARY fir_compiler_v7_2_12;
|
||||
USE fir_compiler_v7_2_12.fir_compiler_v7_2_12;
|
||||
|
||||
ENTITY fir_dmf_invert_prbs7_deci8 IS
|
||||
ENTITY fir_prbs7_invert_rep4 IS
|
||||
PORT (
|
||||
aresetn : IN STD_LOGIC;
|
||||
aclk : IN STD_LOGIC;
|
||||
s_axis_data_tvalid : IN STD_LOGIC;
|
||||
s_axis_data_tready : OUT STD_LOGIC;
|
||||
@@ -65,11 +66,11 @@ ENTITY fir_dmf_invert_prbs7_deci8 IS
|
||||
m_axis_data_tvalid : OUT STD_LOGIC;
|
||||
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
|
||||
);
|
||||
END fir_dmf_invert_prbs7_deci8;
|
||||
END fir_prbs7_invert_rep4;
|
||||
|
||||
ARCHITECTURE fir_dmf_invert_prbs7_deci8_arch OF fir_dmf_invert_prbs7_deci8 IS
|
||||
ARCHITECTURE fir_prbs7_invert_rep4_arch OF fir_prbs7_invert_rep4 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fir_dmf_invert_prbs7_deci8_arch: ARCHITECTURE IS "yes";
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fir_prbs7_invert_rep4_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT fir_compiler_v7_2_12 IS
|
||||
GENERIC (
|
||||
C_XDEVICEFAMILY : STRING;
|
||||
@@ -185,21 +186,23 @@ ARCHITECTURE fir_dmf_invert_prbs7_deci8_arch OF fir_dmf_invert_prbs7_deci8 IS
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF aresetn: SIGNAL IS "XIL_INTERFACENAME aresetn_intf, POLARITY ACTIVE_LOW, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 aresetn_intf RST";
|
||||
BEGIN
|
||||
U0 : fir_compiler_v7_2_12
|
||||
GENERIC MAP (
|
||||
C_XDEVICEFAMILY => "kintex7",
|
||||
C_ELABORATION_DIR => "./",
|
||||
C_COMPONENT_NAME => "fir_dmf_invert_prbs7_deci8",
|
||||
C_COEF_FILE => "fir_dmf_invert_prbs7_deci8.mif",
|
||||
C_COEF_FILE_LINES => 128,
|
||||
C_COMPONENT_NAME => "fir_prbs7_invert_rep4",
|
||||
C_COEF_FILE => "fir_prbs7_invert_rep4.mif",
|
||||
C_COEF_FILE_LINES => 512,
|
||||
C_FILTER_TYPE => 0,
|
||||
C_INTERP_RATE => 1,
|
||||
C_DECIM_RATE => 1,
|
||||
C_ZERO_PACKING_FACTOR => 1,
|
||||
C_SYMMETRY => 0,
|
||||
C_NUM_FILTS => 1,
|
||||
C_NUM_TAPS => 128,
|
||||
C_NUM_TAPS => 512,
|
||||
C_NUM_CHANNELS => 1,
|
||||
C_CHANNEL_PATTERN => "fixed",
|
||||
C_ROUND_MODE => 0,
|
||||
@@ -207,7 +210,7 @@ BEGIN
|
||||
C_NUM_RELOAD_SLOTS => 1,
|
||||
C_COL_MODE => 1,
|
||||
C_COL_PIPE_LEN => 4,
|
||||
C_COL_CONFIG => "16",
|
||||
C_COL_CONFIG => "140,116",
|
||||
C_OPTIMIZATION => 0,
|
||||
C_DATA_PATH_WIDTHS => "12",
|
||||
C_DATA_IP_PATH_WIDTHS => "12",
|
||||
@@ -220,18 +223,18 @@ BEGIN
|
||||
C_PX_PATH_SRC => "0",
|
||||
C_DATA_PATH_SIGN => "0",
|
||||
C_COEF_PATH_SIGN => "0",
|
||||
C_ACCUM_PATH_WIDTHS => "19",
|
||||
C_OUTPUT_WIDTH => 19,
|
||||
C_OUTPUT_PATH_WIDTHS => "19",
|
||||
C_ACCUM_OP_PATH_WIDTHS => "19",
|
||||
C_ACCUM_PATH_WIDTHS => "21",
|
||||
C_OUTPUT_WIDTH => 21,
|
||||
C_OUTPUT_PATH_WIDTHS => "21",
|
||||
C_ACCUM_OP_PATH_WIDTHS => "21",
|
||||
C_EXT_MULT_CNFG => "none",
|
||||
C_DATA_PATH_PSAMP_SRC => "0",
|
||||
C_OP_PATH_PSAMP_SRC => "0",
|
||||
C_NUM_MADDS => 16,
|
||||
C_NUM_MADDS => 256,
|
||||
C_OPT_MADDS => "none",
|
||||
C_OVERSAMPLING_RATE => 8,
|
||||
C_INPUT_RATE => 8,
|
||||
C_OUTPUT_RATE => 8,
|
||||
C_OVERSAMPLING_RATE => 2,
|
||||
C_INPUT_RATE => 2,
|
||||
C_OUTPUT_RATE => 2,
|
||||
C_DATA_MEMTYPE => 0,
|
||||
C_COEF_MEMTYPE => 2,
|
||||
C_IPBUFF_MEMTYPE => 2,
|
||||
@@ -241,8 +244,8 @@ BEGIN
|
||||
C_DATA_MEM_PACKING => 0,
|
||||
C_COEF_MEM_PACKING => 0,
|
||||
C_FILTS_PACKED => 0,
|
||||
C_LATENCY => 30,
|
||||
C_HAS_ARESETn => 0,
|
||||
C_LATENCY => 269,
|
||||
C_HAS_ARESETn => 1,
|
||||
C_HAS_ACLKEN => 0,
|
||||
C_DATA_HAS_TLAST => 0,
|
||||
C_S_DATA_HAS_FIFO => 0,
|
||||
@@ -260,7 +263,7 @@ BEGIN
|
||||
C_RELOAD_TDATA_WIDTH => 1
|
||||
)
|
||||
PORT MAP (
|
||||
aresetn => '1',
|
||||
aresetn => aresetn,
|
||||
aclk => aclk,
|
||||
aclken => '1',
|
||||
s_axis_data_tvalid => s_axis_data_tvalid,
|
||||
@@ -278,4 +281,4 @@ BEGIN
|
||||
m_axis_data_tready => '1',
|
||||
m_axis_data_tdata => m_axis_data_tdata
|
||||
);
|
||||
END fir_dmf_invert_prbs7_deci8_arch;
|
||||
END fir_prbs7_invert_rep4_arch;
|
||||
+90
@@ -0,0 +1,90 @@
|
||||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
|
||||
ila_freq_comp your_instance_name (
|
||||
.clk(clk), // input wire clk
|
||||
|
||||
|
||||
.probe0(probe0), // input wire [17:0] probe0
|
||||
.probe1(probe1), // input wire [17:0] probe1
|
||||
.probe2(probe2), // input wire [17:0] probe2
|
||||
.probe3(probe3), // input wire [17:0] probe3
|
||||
.probe4(probe4), // input wire [17:0] probe4
|
||||
.probe5(probe5), // input wire [17:0] probe5
|
||||
.probe6(probe6), // input wire [17:0] probe6
|
||||
.probe7(probe7), // input wire [17:0] probe7
|
||||
.probe8(probe8), // input wire [17:0] probe8
|
||||
.probe9(probe9), // input wire [2:0] probe9
|
||||
.probe10(probe10), // input wire [0:0] probe10
|
||||
.probe11(probe11), // input wire [0:0] probe11
|
||||
.probe12(probe12), // input wire [0:0] probe12
|
||||
.probe13(probe13), // input wire [31:0] probe13
|
||||
.probe14(probe14), // input wire [0:0] probe14
|
||||
.probe15(probe15), // input wire [31:0] probe15
|
||||
.probe16(probe16), // input wire [11:0] probe16
|
||||
.probe17(probe17), // input wire [11:0] probe17
|
||||
.probe18(probe18), // input wire [9:0] probe18
|
||||
.probe19(probe19), // input wire [9:0] probe19
|
||||
.probe20(probe20), // input wire [9:0] probe20
|
||||
.probe21(probe21) // input wire [9:0] probe21
|
||||
);
|
||||
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file ila_freq_comp when simulating
|
||||
// the core, ila_freq_comp. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
|
||||
LFS
BIN
Binary file not shown.
BIN
Binary file not shown.
+44
@@ -0,0 +1,44 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Mon May 8 12:16:12 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_stub.v
|
||||
// Design : ila_freq_comp
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "ila,Vivado 2019.1.3" *)
|
||||
module ila_freq_comp(clk, probe0, probe1, probe2, probe3, probe4, probe5,
|
||||
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
|
||||
probe18, probe19, probe20, probe21)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[17:0],probe1[17:0],probe2[17:0],probe3[17:0],probe4[17:0],probe5[17:0],probe6[17:0],probe7[17:0],probe8[17:0],probe9[2:0],probe10[0:0],probe11[0:0],probe12[0:0],probe13[31:0],probe14[0:0],probe15[31:0],probe16[11:0],probe17[11:0],probe18[9:0],probe19[9:0],probe20[9:0],probe21[9:0]" */;
|
||||
input clk;
|
||||
input [17:0]probe0;
|
||||
input [17:0]probe1;
|
||||
input [17:0]probe2;
|
||||
input [17:0]probe3;
|
||||
input [17:0]probe4;
|
||||
input [17:0]probe5;
|
||||
input [17:0]probe6;
|
||||
input [17:0]probe7;
|
||||
input [17:0]probe8;
|
||||
input [2:0]probe9;
|
||||
input [0:0]probe10;
|
||||
input [0:0]probe11;
|
||||
input [0:0]probe12;
|
||||
input [31:0]probe13;
|
||||
input [0:0]probe14;
|
||||
input [31:0]probe15;
|
||||
input [11:0]probe16;
|
||||
input [11:0]probe17;
|
||||
input [9:0]probe18;
|
||||
input [9:0]probe19;
|
||||
input [9:0]probe20;
|
||||
input [9:0]probe21;
|
||||
endmodule
|
||||
+52
@@ -0,0 +1,52 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Mon May 8 12:16:12 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_stub.vhdl
|
||||
-- Design : ila_freq_comp
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity ila_freq_comp is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 17 downto 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 17 downto 0 );
|
||||
probe2 : in STD_LOGIC_VECTOR ( 17 downto 0 );
|
||||
probe3 : in STD_LOGIC_VECTOR ( 17 downto 0 );
|
||||
probe4 : in STD_LOGIC_VECTOR ( 17 downto 0 );
|
||||
probe5 : in STD_LOGIC_VECTOR ( 17 downto 0 );
|
||||
probe6 : in STD_LOGIC_VECTOR ( 17 downto 0 );
|
||||
probe7 : in STD_LOGIC_VECTOR ( 17 downto 0 );
|
||||
probe8 : in STD_LOGIC_VECTOR ( 17 downto 0 );
|
||||
probe9 : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
probe10 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe11 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe12 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe13 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe14 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe15 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe16 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe17 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe18 : in STD_LOGIC_VECTOR ( 9 downto 0 );
|
||||
probe19 : in STD_LOGIC_VECTOR ( 9 downto 0 );
|
||||
probe20 : in STD_LOGIC_VECTOR ( 9 downto 0 );
|
||||
probe21 : in STD_LOGIC_VECTOR ( 9 downto 0 )
|
||||
);
|
||||
|
||||
end ila_freq_comp;
|
||||
|
||||
architecture stub of ila_freq_comp is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe0[17:0],probe1[17:0],probe2[17:0],probe3[17:0],probe4[17:0],probe5[17:0],probe6[17:0],probe7[17:0],probe8[17:0],probe9[2:0],probe10[0:0],probe11[0:0],probe12[0:0],probe13[31:0],probe14[0:0],probe15[31:0],probe16[11:0],probe17[11:0],probe18[9:0],probe19[9:0],probe20[9:0],probe21[9:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+48
-10
@@ -1,4 +1,4 @@
|
||||
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
@@ -46,21 +46,59 @@
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
`timescale 1ns / 1ps
|
||||
module vio_null_phase (
|
||||
module ila_freq_comp (
|
||||
clk,
|
||||
|
||||
probe_out0,
|
||||
probe_out1,
|
||||
probe_out2,
|
||||
probe_out3
|
||||
|
||||
probe0,
|
||||
probe1,
|
||||
probe2,
|
||||
probe3,
|
||||
probe4,
|
||||
probe5,
|
||||
probe6,
|
||||
probe7,
|
||||
probe8,
|
||||
probe9,
|
||||
probe10,
|
||||
probe11,
|
||||
probe12,
|
||||
probe13,
|
||||
probe14,
|
||||
probe15,
|
||||
probe16,
|
||||
probe17,
|
||||
probe18,
|
||||
probe19,
|
||||
probe20,
|
||||
probe21
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
output reg [15 : 0] probe_out0 = 'h0000 ;
|
||||
output reg [15 : 0] probe_out1 = 'h0000 ;
|
||||
output reg [15 : 0] probe_out2 = 'h0000 ;
|
||||
output reg [15 : 0] probe_out3 = 'h0000 ;
|
||||
|
||||
input [17 : 0] probe0;
|
||||
input [17 : 0] probe1;
|
||||
input [17 : 0] probe2;
|
||||
input [17 : 0] probe3;
|
||||
input [17 : 0] probe4;
|
||||
input [17 : 0] probe5;
|
||||
input [17 : 0] probe6;
|
||||
input [17 : 0] probe7;
|
||||
input [17 : 0] probe8;
|
||||
input [2 : 0] probe9;
|
||||
input [0 : 0] probe10;
|
||||
input [0 : 0] probe11;
|
||||
input [0 : 0] probe12;
|
||||
input [31 : 0] probe13;
|
||||
input [0 : 0] probe14;
|
||||
input [31 : 0] probe15;
|
||||
input [11 : 0] probe16;
|
||||
input [11 : 0] probe17;
|
||||
input [9 : 0] probe18;
|
||||
input [9 : 0] probe19;
|
||||
input [9 : 0] probe20;
|
||||
input [9 : 0] probe21;
|
||||
|
||||
|
||||
endmodule
|
||||
+9
-8
@@ -46,22 +46,23 @@
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
// IP VLNV: xilinx.com:ip:vio:3.0
|
||||
// IP Revision: 20
|
||||
// IP VLNV: xilinx.com:ip:mult_gen:12.0
|
||||
// IP Revision: 15
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
vio_hop your_instance_name (
|
||||
.clk(clk), // input wire clk
|
||||
.probe_out0(probe_out0), // output wire [0 : 0] probe_out0
|
||||
.probe_out1(probe_out1) // output wire [0 : 0] probe_out1
|
||||
mult_18x18 your_instance_name (
|
||||
.CLK(CLK), // input wire CLK
|
||||
.A(A), // input wire [17 : 0] A
|
||||
.B(B), // input wire [17 : 0] B
|
||||
.P(P) // output wire [35 : 0] P
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file vio_hop.v when simulating
|
||||
// the core, vio_hop. When compiling the wrapper file, be sure to
|
||||
// You must compile the wrapper file mult_18x18.v when simulating
|
||||
// the core, mult_18x18. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
+14
-12
@@ -46,17 +46,18 @@
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:vio:3.0
|
||||
-- IP Revision: 20
|
||||
-- IP VLNV: xilinx.com:ip:mult_gen:12.0
|
||||
-- IP Revision: 15
|
||||
|
||||
-- The following code must appear in the VHDL architecture header.
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
COMPONENT vio_hop
|
||||
COMPONENT mult_18x18
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe_out1 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
CLK : IN STD_LOGIC;
|
||||
A : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
|
||||
B : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
|
||||
P : OUT STD_LOGIC_VECTOR(35 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
@@ -65,15 +66,16 @@ END COMPONENT;
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : vio_hop
|
||||
your_instance_name : mult_18x18
|
||||
PORT MAP (
|
||||
clk => clk,
|
||||
probe_out0 => probe_out0,
|
||||
probe_out1 => probe_out1
|
||||
CLK => CLK,
|
||||
A => A,
|
||||
B => B,
|
||||
P => P
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
-- You must compile the wrapper file vio_hop.vhd when simulating
|
||||
-- the core, vio_hop. When compiling the wrapper file, be sure to
|
||||
-- You must compile the wrapper file mult_18x18.vhd when simulating
|
||||
-- the core, mult_18x18. When compiling the wrapper file, be sure to
|
||||
-- reference the VHDL simulation library.
|
||||
|
||||
BIN
Binary file not shown.
LFS
BIN
Binary file not shown.
+10
-9
@@ -1,11 +1,11 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Wed Apr 19 12:04:19 2023
|
||||
// Date : Sun May 7 00:47:19 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_stub.v
|
||||
// Design : vio_hop
|
||||
// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18_stub.v
|
||||
// Design : mult_18x18
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
@@ -13,10 +13,11 @@
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
|
||||
module vio_hop(clk, probe_out0, probe_out1)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[0:0],probe_out1[0:0]" */;
|
||||
input clk;
|
||||
output [0:0]probe_out0;
|
||||
output [0:0]probe_out1;
|
||||
(* x_core_info = "mult_gen_v12_0_15,Vivado 2019.1.3" *)
|
||||
module mult_18x18(CLK, A, B, P)
|
||||
/* synthesis syn_black_box black_box_pad_pin="CLK,A[17:0],B[17:0],P[35:0]" */;
|
||||
input CLK;
|
||||
input [17:0]A;
|
||||
input [17:0]B;
|
||||
output [35:0]P;
|
||||
endmodule
|
||||
+13
-12
@@ -1,32 +1,33 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Wed Apr 19 12:04:19 2023
|
||||
-- Date : Sun May 7 00:47:19 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_stub.vhdl
|
||||
-- Design : vio_hop
|
||||
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/mult_18x18_synth_1/mult_18x18_stub.vhdl
|
||||
-- Design : mult_18x18
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity vio_hop is
|
||||
entity mult_18x18 is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
CLK : in STD_LOGIC;
|
||||
A : in STD_LOGIC_VECTOR ( 17 downto 0 );
|
||||
B : in STD_LOGIC_VECTOR ( 17 downto 0 );
|
||||
P : out STD_LOGIC_VECTOR ( 35 downto 0 )
|
||||
);
|
||||
|
||||
end vio_hop;
|
||||
end mult_18x18;
|
||||
|
||||
architecture stub of vio_hop is
|
||||
architecture stub of mult_18x18 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[0:0],probe_out1[0:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
|
||||
attribute black_box_pad_pin of stub : architecture is "CLK,A[17:0],B[17:0],P[35:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "mult_gen_v12_0_15,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+145
@@ -0,0 +1,145 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:mult_gen:12.0
|
||||
-- IP Revision: 15
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY mult_gen_v12_0_15;
|
||||
USE mult_gen_v12_0_15.mult_gen_v12_0_15;
|
||||
|
||||
ENTITY mult_18x18 IS
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
A : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
|
||||
B : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
|
||||
P : OUT STD_LOGIC_VECTOR(35 DOWNTO 0)
|
||||
);
|
||||
END mult_18x18;
|
||||
|
||||
ARCHITECTURE mult_18x18_arch OF mult_18x18 IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF mult_18x18_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT mult_gen_v12_0_15 IS
|
||||
GENERIC (
|
||||
C_VERBOSITY : INTEGER;
|
||||
C_MODEL_TYPE : INTEGER;
|
||||
C_OPTIMIZE_GOAL : INTEGER;
|
||||
C_XDEVICEFAMILY : STRING;
|
||||
C_HAS_CE : INTEGER;
|
||||
C_HAS_SCLR : INTEGER;
|
||||
C_LATENCY : INTEGER;
|
||||
C_A_WIDTH : INTEGER;
|
||||
C_A_TYPE : INTEGER;
|
||||
C_B_WIDTH : INTEGER;
|
||||
C_B_TYPE : INTEGER;
|
||||
C_OUT_HIGH : INTEGER;
|
||||
C_OUT_LOW : INTEGER;
|
||||
C_MULT_TYPE : INTEGER;
|
||||
C_CE_OVERRIDES_SCLR : INTEGER;
|
||||
C_CCM_IMP : INTEGER;
|
||||
C_B_VALUE : STRING;
|
||||
C_HAS_ZERO_DETECT : INTEGER;
|
||||
C_ROUND_OUTPUT : INTEGER;
|
||||
C_ROUND_PT : INTEGER
|
||||
);
|
||||
PORT (
|
||||
CLK : IN STD_LOGIC;
|
||||
A : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
|
||||
B : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
|
||||
CE : IN STD_LOGIC;
|
||||
SCLR : IN STD_LOGIC;
|
||||
P : OUT STD_LOGIC_VECTOR(35 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT mult_gen_v12_0_15;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF P: SIGNAL IS "XIL_INTERFACENAME p_intf, LAYERED_METADATA undef";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF P: SIGNAL IS "xilinx.com:signal:data:1.0 p_intf DATA";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF B: SIGNAL IS "XIL_INTERFACENAME b_intf, LAYERED_METADATA undef";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF A: SIGNAL IS "XIL_INTERFACENAME a_intf, LAYERED_METADATA undef";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF CLK: SIGNAL IS "XIL_INTERFACENAME clk_intf, ASSOCIATED_BUSIF p_intf:b_intf:a_intf, ASSOCIATED_RESET sclr, ASSOCIATED_CLKEN ce, FREQ_HZ 10000000, PHASE 0.000, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_intf CLK";
|
||||
BEGIN
|
||||
U0 : mult_gen_v12_0_15
|
||||
GENERIC MAP (
|
||||
C_VERBOSITY => 0,
|
||||
C_MODEL_TYPE => 0,
|
||||
C_OPTIMIZE_GOAL => 1,
|
||||
C_XDEVICEFAMILY => "kintex7",
|
||||
C_HAS_CE => 0,
|
||||
C_HAS_SCLR => 0,
|
||||
C_LATENCY => 5,
|
||||
C_A_WIDTH => 18,
|
||||
C_A_TYPE => 0,
|
||||
C_B_WIDTH => 18,
|
||||
C_B_TYPE => 0,
|
||||
C_OUT_HIGH => 35,
|
||||
C_OUT_LOW => 0,
|
||||
C_MULT_TYPE => 0,
|
||||
C_CE_OVERRIDES_SCLR => 0,
|
||||
C_CCM_IMP => 0,
|
||||
C_B_VALUE => "10000001",
|
||||
C_HAS_ZERO_DETECT => 0,
|
||||
C_ROUND_OUTPUT => 0,
|
||||
C_ROUND_PT => 0
|
||||
)
|
||||
PORT MAP (
|
||||
CLK => CLK,
|
||||
A => A,
|
||||
B => B,
|
||||
CE => '1',
|
||||
SCLR => '0',
|
||||
P => P
|
||||
);
|
||||
END mult_18x18_arch;
|
||||
+5
-5
@@ -54,14 +54,14 @@
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
rom_hop_data your_instance_name (
|
||||
rom_freq_word your_instance_name (
|
||||
.clka(clka), // input wire clka
|
||||
.addra(addra), // input wire [13 : 0] addra
|
||||
.douta(douta) // output wire [95 : 0] douta
|
||||
.addra(addra), // input wire [6 : 0] addra
|
||||
.douta(douta) // output wire [15 : 0] douta
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file rom_hop_data.v when simulating
|
||||
// the core, rom_hop_data. When compiling the wrapper file, be sure to
|
||||
// You must compile the wrapper file rom_freq_word.v when simulating
|
||||
// the core, rom_freq_word. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
+6
-6
@@ -52,11 +52,11 @@
|
||||
-- The following code must appear in the VHDL architecture header.
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
COMPONENT rom_hop_data
|
||||
COMPONENT rom_freq_word
|
||||
PORT (
|
||||
clka : IN STD_LOGIC;
|
||||
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
|
||||
douta : OUT STD_LOGIC_VECTOR(95 DOWNTO 0)
|
||||
addra : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
|
||||
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
@@ -65,7 +65,7 @@ END COMPONENT;
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : rom_hop_data
|
||||
your_instance_name : rom_freq_word
|
||||
PORT MAP (
|
||||
clka => clka,
|
||||
addra => addra,
|
||||
@@ -73,7 +73,7 @@ your_instance_name : rom_hop_data
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
-- You must compile the wrapper file rom_hop_data.vhd when simulating
|
||||
-- the core, rom_hop_data. When compiling the wrapper file, be sure to
|
||||
-- You must compile the wrapper file rom_freq_word.vhd when simulating
|
||||
-- the core, rom_freq_word. When compiling the wrapper file, be sure to
|
||||
-- reference the VHDL simulation library.
|
||||
|
||||
LFS
BIN
Binary file not shown.
BIN
Binary file not shown.
+7
-7
@@ -1,11 +1,11 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Mon Apr 17 13:39:39 2023
|
||||
// Date : Mon May 8 11:44:03 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/rom_hop_data_stub.v
|
||||
// Design : rom_hop_data
|
||||
// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v
|
||||
// Design : rom_freq_word
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
@@ -14,9 +14,9 @@
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *)
|
||||
module rom_hop_data(clka, addra, douta)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clka,addra[13:0],douta[95:0]" */;
|
||||
module rom_freq_word(clka, addra, douta)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clka,addra[6:0],douta[15:0]" */;
|
||||
input clka;
|
||||
input [13:0]addra;
|
||||
output [95:0]douta;
|
||||
input [6:0]addra;
|
||||
output [15:0]douta;
|
||||
endmodule
|
||||
+9
-9
@@ -1,31 +1,31 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Mon Apr 17 13:39:39 2023
|
||||
-- Date : Mon May 8 11:44:03 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/rom_hop_data_stub.vhdl
|
||||
-- Design : rom_hop_data
|
||||
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl
|
||||
-- Design : rom_freq_word
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity rom_hop_data is
|
||||
entity rom_freq_word is
|
||||
Port (
|
||||
clka : in STD_LOGIC;
|
||||
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
|
||||
douta : out STD_LOGIC_VECTOR ( 95 downto 0 )
|
||||
addra : in STD_LOGIC_VECTOR ( 6 downto 0 );
|
||||
douta : out STD_LOGIC_VECTOR ( 15 downto 0 )
|
||||
);
|
||||
|
||||
end rom_hop_data;
|
||||
end rom_freq_word;
|
||||
|
||||
architecture stub of rom_hop_data is
|
||||
architecture stub of rom_freq_word is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clka,addra[13:0],douta[95:0]";
|
||||
attribute black_box_pad_pin of stub : architecture is "clka,addra[6:0],douta[15:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3";
|
||||
begin
|
||||
+22
-22
@@ -53,7 +53,7 @@
|
||||
`timescale 1ns/1ps
|
||||
|
||||
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||
module rom_hop_data (
|
||||
module rom_freq_word (
|
||||
clka,
|
||||
addra,
|
||||
douta
|
||||
@@ -62,10 +62,10 @@ module rom_hop_data (
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
|
||||
input wire clka;
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
|
||||
input wire [13 : 0] addra;
|
||||
input wire [6 : 0] addra;
|
||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *)
|
||||
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
|
||||
output wire [95 : 0] douta;
|
||||
output wire [15 : 0] douta;
|
||||
|
||||
blk_mem_gen_v8_4_3 #(
|
||||
.C_FAMILY("kintex7"),
|
||||
@@ -84,8 +84,8 @@ output wire [95 : 0] douta;
|
||||
.C_ALGORITHM(1),
|
||||
.C_PRIM_TYPE(1),
|
||||
.C_LOAD_INIT_FILE(1),
|
||||
.C_INIT_FILE_NAME("rom_hop_data.mif"),
|
||||
.C_INIT_FILE("rom_hop_data.mem"),
|
||||
.C_INIT_FILE_NAME("rom_freq_word.mif"),
|
||||
.C_INIT_FILE("rom_freq_word.mem"),
|
||||
.C_USE_DEFAULT_DATA(0),
|
||||
.C_DEFAULT_DATA("0"),
|
||||
.C_HAS_RSTA(0),
|
||||
@@ -97,11 +97,11 @@ output wire [95 : 0] douta;
|
||||
.C_USE_BYTE_WEA(0),
|
||||
.C_WEA_WIDTH(1),
|
||||
.C_WRITE_MODE_A("WRITE_FIRST"),
|
||||
.C_WRITE_WIDTH_A(96),
|
||||
.C_READ_WIDTH_A(96),
|
||||
.C_WRITE_DEPTH_A(9600),
|
||||
.C_READ_DEPTH_A(9600),
|
||||
.C_ADDRA_WIDTH(14),
|
||||
.C_WRITE_WIDTH_A(16),
|
||||
.C_READ_WIDTH_A(16),
|
||||
.C_WRITE_DEPTH_A(81),
|
||||
.C_READ_DEPTH_A(81),
|
||||
.C_ADDRA_WIDTH(7),
|
||||
.C_HAS_RSTB(0),
|
||||
.C_RST_PRIORITY_B("CE"),
|
||||
.C_RSTRAM_B(0),
|
||||
@@ -111,12 +111,12 @@ output wire [95 : 0] douta;
|
||||
.C_USE_BYTE_WEB(0),
|
||||
.C_WEB_WIDTH(1),
|
||||
.C_WRITE_MODE_B("WRITE_FIRST"),
|
||||
.C_WRITE_WIDTH_B(96),
|
||||
.C_READ_WIDTH_B(96),
|
||||
.C_WRITE_DEPTH_B(9600),
|
||||
.C_READ_DEPTH_B(9600),
|
||||
.C_ADDRB_WIDTH(14),
|
||||
.C_HAS_MEM_OUTPUT_REGS_A(0),
|
||||
.C_WRITE_WIDTH_B(16),
|
||||
.C_READ_WIDTH_B(16),
|
||||
.C_WRITE_DEPTH_B(81),
|
||||
.C_READ_DEPTH_B(81),
|
||||
.C_ADDRB_WIDTH(7),
|
||||
.C_HAS_MEM_OUTPUT_REGS_A(1),
|
||||
.C_HAS_MEM_OUTPUT_REGS_B(0),
|
||||
.C_HAS_MUX_OUTPUT_REGS_A(0),
|
||||
.C_HAS_MUX_OUTPUT_REGS_B(0),
|
||||
@@ -140,9 +140,9 @@ output wire [95 : 0] douta;
|
||||
.C_EN_SHUTDOWN_PIN(0),
|
||||
.C_EN_SAFETY_CKT(0),
|
||||
.C_DISABLE_WARN_BHV_RANGE(0),
|
||||
.C_COUNT_36K_BRAM("26"),
|
||||
.C_COUNT_36K_BRAM("0"),
|
||||
.C_COUNT_18K_BRAM("1"),
|
||||
.C_EST_POWER_SUMMARY("Estimated Power for IP : 23.399606 mW")
|
||||
.C_EST_POWER_SUMMARY("Estimated Power for IP : 2.7096 mW")
|
||||
) inst (
|
||||
.clka(clka),
|
||||
.rsta(1'D0),
|
||||
@@ -150,15 +150,15 @@ output wire [95 : 0] douta;
|
||||
.regcea(1'D0),
|
||||
.wea(1'B0),
|
||||
.addra(addra),
|
||||
.dina(96'B0),
|
||||
.dina(16'B0),
|
||||
.douta(douta),
|
||||
.clkb(1'D0),
|
||||
.rstb(1'D0),
|
||||
.enb(1'D0),
|
||||
.regceb(1'D0),
|
||||
.web(1'B0),
|
||||
.addrb(14'B0),
|
||||
.dinb(96'B0),
|
||||
.addrb(7'B0),
|
||||
.dinb(16'B0),
|
||||
.doutb(),
|
||||
.injectsbiterr(1'D0),
|
||||
.injectdbiterr(1'D0),
|
||||
@@ -180,7 +180,7 @@ output wire [95 : 0] douta;
|
||||
.s_axi_awburst(2'B0),
|
||||
.s_axi_awvalid(1'D0),
|
||||
.s_axi_awready(),
|
||||
.s_axi_wdata(96'B0),
|
||||
.s_axi_wdata(16'B0),
|
||||
.s_axi_wstrb(1'B0),
|
||||
.s_axi_wlast(1'D0),
|
||||
.s_axi_wvalid(1'D0),
|
||||
LFS
BIN
Binary file not shown.
projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_hop_data/rom_hop_data_sim_netlist.vhdl
LFS
BIN
Binary file not shown.
-283
@@ -1,283 +0,0 @@
|
||||
`pragma protect begin_protected
|
||||
`pragma protect version = 1
|
||||
`pragma protect encrypt_agent = "XILINX"
|
||||
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1"
|
||||
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
|
||||
`pragma protect key_block
|
||||
GbQWy7xyRnDVKNEgu/syxcQSo3KIIWjSBPIwi/pSAYCe9sIQf1xA0ykhHf7s3r7GRWRS+sel+0Xx
|
||||
XWe4lBDDrw==
|
||||
|
||||
`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`pragma protect key_block
|
||||
rLh670IEMVEjBamdsB+LhhoxrK6I5H9wfmPCOFqaLelJt08QWbH7WNvjIhNNz7hnkT7w+wDWT6AH
|
||||
9ZJgOGPSJmj9pWoXHAojkkRBTIXpFT11+IDyFQ4FgN2TPXWILoYGY+uZG1GlGN7dsEIm5HUCUy2c
|
||||
eVhT3XSIJDvufMyiJUc=
|
||||
|
||||
`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
KgKxjU+tI9TXRZLkaaosEf4JcTfzGtF82aOinFlVe78eUyHdMvwHHcKsxUKAjkhYW491bZ0jTKit
|
||||
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|
||||
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|
||||
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|
||||
sz4nRUsC3Yg3/CybYyPjvVJDirIzWRzSD6l1DQ==
|
||||
|
||||
`pragma protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
4QexKWP16Ghv319FCz4KExZ6lY+7HuoO55lf4A==
|
||||
|
||||
`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
R19uHYIhWP+7IpmjTiQ=
|
||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
|
||||
`pragma protect data_method = "AES128-CBC"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12464)
|
||||
`pragma protect data_block
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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90/8XCJA0a9VcsSrh1LoO0V3YX80VWdNPY79OUOlqftl3rNXVXE=
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||||
`pragma protect end_protected
|
||||
BIN
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BIN
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@@ -1,23 +0,0 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
// Date : Sat Mar 18 23:34:21 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_cal_synth_1/vio_cal_stub.v
|
||||
// Design : vio_cal
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
|
||||
module vio_cal(clk, probe_in0, probe_in1, probe_in2)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[4:0],probe_in1[15:0],probe_in2[15:0]" */;
|
||||
input clk;
|
||||
input [4:0]probe_in0;
|
||||
input [15:0]probe_in1;
|
||||
input [15:0]probe_in2;
|
||||
endmodule
|
||||
@@ -1,33 +0,0 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019
|
||||
-- Date : Sat Mar 18 23:34:21 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- D:/vivado-git/projects/datalink_814/dl814_cmos/ip/managed_ip_project/managed_ip_project.runs/vio_cal_synth_1/vio_cal_stub.vhdl
|
||||
-- Design : vio_cal
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity vio_cal is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe_in0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
|
||||
probe_in1 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_in2 : in STD_LOGIC_VECTOR ( 15 downto 0 )
|
||||
);
|
||||
|
||||
end vio_cal;
|
||||
|
||||
architecture stub of vio_cal is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[4:0],probe_in1[15:0],probe_in2[15:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+9
-4
@@ -46,17 +46,22 @@
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
`timescale 1ns / 1ps
|
||||
module vio_hop (
|
||||
module vio_freq_comp (
|
||||
clk,
|
||||
|
||||
probe_in0,
|
||||
probe_out0,
|
||||
probe_out1
|
||||
probe_out1,
|
||||
probe_out2,
|
||||
probe_out3
|
||||
);
|
||||
|
||||
input clk;
|
||||
input [0 : 0] probe_in0;
|
||||
|
||||
output reg [0 : 0] probe_out0 = 'h0 ;
|
||||
output reg [0 : 0] probe_out1 = 'h0 ;
|
||||
output reg [7 : 0] probe_out1 = 'h0A ;
|
||||
output reg [0 : 0] probe_out2 = 'h0 ;
|
||||
output reg [31 : 0] probe_out3 = 'h00000000 ;
|
||||
|
||||
|
||||
endmodule
|
||||
+8
-7
@@ -54,16 +54,17 @@
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
vio_null_phase your_instance_name (
|
||||
vio_freq_comp your_instance_name (
|
||||
.clk(clk), // input wire clk
|
||||
.probe_out0(probe_out0), // output wire [15 : 0] probe_out0
|
||||
.probe_out1(probe_out1), // output wire [15 : 0] probe_out1
|
||||
.probe_out2(probe_out2), // output wire [15 : 0] probe_out2
|
||||
.probe_out3(probe_out3) // output wire [15 : 0] probe_out3
|
||||
.probe_in0(probe_in0), // input wire [0 : 0] probe_in0
|
||||
.probe_out0(probe_out0), // output wire [0 : 0] probe_out0
|
||||
.probe_out1(probe_out1), // output wire [7 : 0] probe_out1
|
||||
.probe_out2(probe_out2), // output wire [0 : 0] probe_out2
|
||||
.probe_out3(probe_out3) // output wire [31 : 0] probe_out3
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file vio_null_phase.v when simulating
|
||||
// the core, vio_null_phase. When compiling the wrapper file, be sure to
|
||||
// You must compile the wrapper file vio_freq_comp.v when simulating
|
||||
// the core, vio_freq_comp. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
+10
-8
@@ -52,13 +52,14 @@
|
||||
-- The following code must appear in the VHDL architecture header.
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
COMPONENT vio_null_phase
|
||||
COMPONENT vio_freq_comp
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
probe_out0 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
probe_out1 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
probe_out2 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
probe_out3 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
|
||||
probe_in0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe_out1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
probe_out2 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe_out3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
@@ -67,9 +68,10 @@ END COMPONENT;
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : vio_null_phase
|
||||
your_instance_name : vio_freq_comp
|
||||
PORT MAP (
|
||||
clk => clk,
|
||||
probe_in0 => probe_in0,
|
||||
probe_out0 => probe_out0,
|
||||
probe_out1 => probe_out1,
|
||||
probe_out2 => probe_out2,
|
||||
@@ -77,7 +79,7 @@ your_instance_name : vio_null_phase
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
-- You must compile the wrapper file vio_null_phase.vhd when simulating
|
||||
-- the core, vio_null_phase. When compiling the wrapper file, be sure to
|
||||
-- You must compile the wrapper file vio_freq_comp.vhd when simulating
|
||||
-- the core, vio_freq_comp. When compiling the wrapper file, be sure to
|
||||
-- reference the VHDL simulation library.
|
||||
|
||||
LFS
BIN
Binary file not shown.
BIN
Binary file not shown.
+11
-10
@@ -1,11 +1,11 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Tue Apr 25 17:41:14 2023
|
||||
// Date : Sun May 7 16:51:33 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_null_phase_synth_1/vio_null_phase_stub.v
|
||||
// Design : vio_null_phase
|
||||
// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.v
|
||||
// Design : vio_freq_comp
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
@@ -14,12 +14,13 @@
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
|
||||
module vio_null_phase(clk, probe_out0, probe_out1, probe_out2,
|
||||
probe_out3)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[15:0],probe_out1[15:0],probe_out2[15:0],probe_out3[15:0]" */;
|
||||
module vio_freq_comp(clk, probe_in0, probe_out0, probe_out1,
|
||||
probe_out2, probe_out3)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_out0[0:0],probe_out1[7:0],probe_out2[0:0],probe_out3[31:0]" */;
|
||||
input clk;
|
||||
output [15:0]probe_out0;
|
||||
output [15:0]probe_out1;
|
||||
output [15:0]probe_out2;
|
||||
output [15:0]probe_out3;
|
||||
input [0:0]probe_in0;
|
||||
output [0:0]probe_out0;
|
||||
output [7:0]probe_out1;
|
||||
output [0:0]probe_out2;
|
||||
output [31:0]probe_out3;
|
||||
endmodule
|
||||
+12
-11
@@ -1,33 +1,34 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Tue Apr 25 17:41:14 2023
|
||||
-- Date : Sun May 7 16:51:33 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_null_phase_synth_1/vio_null_phase_stub.vhdl
|
||||
-- Design : vio_null_phase
|
||||
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.vhdl
|
||||
-- Design : vio_freq_comp
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity vio_null_phase is
|
||||
entity vio_freq_comp is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe_out0 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out1 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out3 : out STD_LOGIC_VECTOR ( 15 downto 0 )
|
||||
probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out1 : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out3 : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
|
||||
end vio_null_phase;
|
||||
end vio_freq_comp;
|
||||
|
||||
architecture stub of vio_null_phase is
|
||||
architecture stub of vio_freq_comp is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[15:0],probe_out1[15:0],probe_out2[15:0],probe_out3[15:0]";
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[0:0],probe_out0[0:0],probe_out1[7:0],probe_out2[0:0],probe_out3[31:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
|
||||
begin
|
||||
-283
@@ -1,283 +0,0 @@
|
||||
`pragma protect begin_protected
|
||||
`pragma protect version = 1
|
||||
`pragma protect encrypt_agent = "XILINX"
|
||||
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1"
|
||||
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
|
||||
`pragma protect key_block
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||||
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|
||||
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|
||||
|
||||
`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`pragma protect key_block
|
||||
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||||
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||||
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||||
|
||||
`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
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||||
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||||
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||||
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||||
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||||
sz4nRUsC3Yg3/CybYyPjvVJDirIzWRzSD6l1DQ==
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||||
|
||||
`pragma protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
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||||
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||||
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||||
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||||
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||||
|
||||
`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
FGUAaXx6dK7W5dgDUXY6j9xLpCHdbPvbaH+O+ozu9kcNjL5BJcGWnTdooAxaZdBsOZBvrVuXUU4v
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||||
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||||
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||||
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||||
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||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`pragma protect key_block
|
||||
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||||
R19uHYIhWP+7IpmjTiQ=
|
||||
|
||||
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
|
||||
AI09c0Va0j6swrG6tMKXPaWcjMpXDnvuIze3bAe9Cj0tCXFumugM/pZL81X53kMwmKPvRCpTi8DM
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||||
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|
||||
|
||||
`pragma protect data_method = "AES128-CBC"
|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12464)
|
||||
`pragma protect data_block
|
||||
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||||
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90/8XCJA0a9VcsSrh1LoO0V3YX80VWdNPY79OUOlqftl3rNXVXE=
|
||||
`pragma protect end_protected
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
+2
-4
@@ -53,18 +53,16 @@ probe_out0,
|
||||
probe_out1,
|
||||
probe_out2,
|
||||
probe_out3,
|
||||
probe_out4,
|
||||
probe_out5
|
||||
probe_out4
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
output reg [1 : 0] probe_out0 = 'h2 ;
|
||||
output reg [1 : 0] probe_out0 = 'h1 ;
|
||||
output reg [0 : 0] probe_out1 = 'h0 ;
|
||||
output reg [31 : 0] probe_out2 = 'h00000000 ;
|
||||
output reg [1 : 0] probe_out3 = 'h3 ;
|
||||
output reg [3 : 0] probe_out4 = 'h0 ;
|
||||
output reg [0 : 0] probe_out5 = 'h0 ;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
+1
-2
@@ -60,8 +60,7 @@ vio_manual_ctrl your_instance_name (
|
||||
.probe_out1(probe_out1), // output wire [0 : 0] probe_out1
|
||||
.probe_out2(probe_out2), // output wire [31 : 0] probe_out2
|
||||
.probe_out3(probe_out3), // output wire [1 : 0] probe_out3
|
||||
.probe_out4(probe_out4), // output wire [3 : 0] probe_out4
|
||||
.probe_out5(probe_out5) // output wire [0 : 0] probe_out5
|
||||
.probe_out4(probe_out4) // output wire [3 : 0] probe_out4
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
|
||||
+2
-4
@@ -59,8 +59,7 @@ COMPONENT vio_manual_ctrl
|
||||
probe_out1 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe_out2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe_out3 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe_out4 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe_out5 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
probe_out4 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
@@ -76,8 +75,7 @@ your_instance_name : vio_manual_ctrl
|
||||
probe_out1 => probe_out1,
|
||||
probe_out2 => probe_out2,
|
||||
probe_out3 => probe_out3,
|
||||
probe_out4 => probe_out4,
|
||||
probe_out5 => probe_out5
|
||||
probe_out4 => probe_out4
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
+4
-5
@@ -1,10 +1,10 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Sun Apr 23 16:19:11 2023
|
||||
// Date : Sun May 7 19:23:21 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v
|
||||
// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v
|
||||
// Design : vio_manual_ctrl
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
@@ -15,13 +15,12 @@
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
|
||||
module vio_manual_ctrl(clk, probe_out0, probe_out1, probe_out2,
|
||||
probe_out3, probe_out4, probe_out5)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0],probe_out5[0:0]" */;
|
||||
probe_out3, probe_out4)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]" */;
|
||||
input clk;
|
||||
output [1:0]probe_out0;
|
||||
output [0:0]probe_out1;
|
||||
output [31:0]probe_out2;
|
||||
output [1:0]probe_out3;
|
||||
output [3:0]probe_out4;
|
||||
output [0:0]probe_out5;
|
||||
endmodule
|
||||
|
||||
+4
-5
@@ -1,10 +1,10 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Sun Apr 23 16:19:11 2023
|
||||
-- Date : Sun May 7 19:23:21 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl
|
||||
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl
|
||||
-- Design : vio_manual_ctrl
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
@@ -19,8 +19,7 @@ entity vio_manual_ctrl is
|
||||
probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_out3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe_out5 : out STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 )
|
||||
);
|
||||
|
||||
end vio_manual_ctrl;
|
||||
@@ -29,7 +28,7 @@ architecture stub of vio_manual_ctrl is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0],probe_out5[0:0]";
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
|
||||
begin
|
||||
|
||||
-283
@@ -1,283 +0,0 @@
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
`pragma protect key_block
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`pragma protect key_block
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|
||||
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|
||||
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`pragma protect key_block
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||||
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||||
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||||
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|
||||
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JeKFlv86ZJ1h39w2Zj+8gJ4U4AZbOygG4bLImMVZigruDqvkaOxNreC1k+1vLgOPtZ/kWzXOwH+O
|
||||
/KlC0MjIWmtLxc4WQHgphsph364TvIk2pNXhw0kVpwDtyTQQTZ0uelX9+IewGOhxjBSp71WJ3KS6
|
||||
vd6oUylWNSjtHxK7eVyclTxCvy8AwzP5K+8lwRzhDkWw2j7nriqzZ6sBQ8sc55H3/PkQ1nhDvP3S
|
||||
Y4mETg95nQKorrqSDgb6WO6YmD7apM6gCf2H5/4poh7YLqjOw7ajEzyPcoHqdJRC+6dswNNb8pdu
|
||||
Eynk1RGGG3fnXVSGn5SSGA2S8xxJpeOPXqhwWm47l709TR53pdlNgeNlLSat/LE3Yr6f3dzCO3+M
|
||||
mLQSSv4FDwGW+hU2bHZPiUhUUQSmaa9T19pbpa6s8ZJ0xLEbS3z1xEajwM0bFGEGE+lodnN0Ziu+
|
||||
StlkG0O7ozjg6V6hRnz8KkJqNDirqESfbjE6WMHtc599lGztc/77jnBfdHd3VIuf4IgUcezITMqj
|
||||
5MGygT2/VAEb4BZAbcRxPGqKcLfYnJZ63t3QEqbgblMA1vFo4VgSV1ajLUyoDGBGLV28ExlwTut1
|
||||
HzIaED7RvsGxFpR26+1akJ1/8bReaeZFhca9QQVHRvj1X698r4C/XUsrSc+05XtjMx6HM5q1yZwu
|
||||
pU7X3s5l0gEMjqTKe4cxHPW2hjvKhiEEb66pzjN7HK0y5nrjMJxzwtfqbNV7b76TcDtX27W08c9U
|
||||
hsEprM3gDA7yAWiwAy3nxW57jdofbM5LfU0HVc1mK3FN0pfA/Fg0HWk0RX6K1vbYorZ2YFYwkpIK
|
||||
Spx8l1Y/4Kpd/0yvO9c4f8OcsEc6LfaQSV83l2H8v6NalHbhaZ2gKxmDZi/k03xDyL8v6GCn18bp
|
||||
dB5LUUJUKbnsl6q5E9b8DkJqSnAaHRLJDnEvMp6EfGlpc52On3lCg0wI5XERerziamjcMH44VZfd
|
||||
j8z1WUyHlyOSmkvZdJ66PfYWu5BxCG7hfdtSGROPtIxs36iLmesyYm4yHKwwbWgNIrLgra92DF2L
|
||||
R6e0RM1WWkcJHei4v89Nmwym4k0dKMTX1HkfTogoprrdIyDYj4qMmeTqfl0U8pRehVs6/zy4x8HS
|
||||
0V2+smFFQ/BZxLQ4eV8NHKeszc4kI6jJ3OCncsP57tfkE6TmVTtWKiimERISYB4KhUpblsbN6zyX
|
||||
Bni5ezNwl9XdaBq9c90k+QQmaMGeyQbczdGy9ufcC269vB1FU5+a67Ew8h0jPAPeYHvsw4kGsTSh
|
||||
xnhGNUHRuPoNmQYBjI2LztvnbGuoucUVntUi5quKpKAK1fOZerZTh+kr5PjaW0YlozpL5CtElvS3
|
||||
eqqkVT8a5mdW+sWTxJxTjqronag0QACsSwbA9qurCW9IdcOO+0D7nzfIJIFrWKx+D71JhKNvOmUa
|
||||
NmCy9l+wzdpcLs1zvS3o3zwEgUWOOHzITgzOxtDhIuBcJkg9lS+o5b+W+U9fplCbVFjYd5ZDa2sX
|
||||
90/8XCJA0a9VcsSrh1LoO0V3YX80VWdNPY79OUOlqftl3rNXVXE=
|
||||
`pragma protect end_protected
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
+39
-6
@@ -46,17 +46,50 @@
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
`timescale 1ns / 1ps
|
||||
module vio_cal (
|
||||
module vio_rfcontrl (
|
||||
clk,
|
||||
probe_in0,probe_in1,probe_in2
|
||||
|
||||
probe_in0,
|
||||
probe_out0,
|
||||
probe_out1,
|
||||
probe_out2,
|
||||
probe_out3,
|
||||
probe_out4,
|
||||
probe_out5,
|
||||
probe_out6,
|
||||
probe_out7,
|
||||
probe_out8,
|
||||
probe_out9,
|
||||
probe_out10,
|
||||
probe_out11,
|
||||
probe_out12,
|
||||
probe_out13,
|
||||
probe_out14,
|
||||
probe_out15,
|
||||
probe_out16,
|
||||
probe_out17
|
||||
);
|
||||
|
||||
input clk;
|
||||
input [4 : 0] probe_in0;
|
||||
input [15 : 0] probe_in1;
|
||||
input [15 : 0] probe_in2;
|
||||
input [15 : 0] probe_in0;
|
||||
|
||||
output reg [0 : 0] probe_out0 = 'h0 ;
|
||||
output reg [0 : 0] probe_out1 = 'h0 ;
|
||||
output reg [15 : 0] probe_out2 = 'h05DC ;
|
||||
output reg [7 : 0] probe_out3 = 'h00 ;
|
||||
output reg [3 : 0] probe_out4 = 'h0 ;
|
||||
output reg [3 : 0] probe_out5 = 'h0 ;
|
||||
output reg [3 : 0] probe_out6 = 'h0 ;
|
||||
output reg [3 : 0] probe_out7 = 'h0 ;
|
||||
output reg [7 : 0] probe_out8 = 'h00 ;
|
||||
output reg [7 : 0] probe_out9 = 'h04 ;
|
||||
output reg [15 : 0] probe_out10 = 'h0000 ;
|
||||
output reg [15 : 0] probe_out11 = 'h0000 ;
|
||||
output reg [15 : 0] probe_out12 = 'h1680 ;
|
||||
output reg [0 : 0] probe_out13 = 'h0 ;
|
||||
output reg [0 : 0] probe_out14 = 'h0 ;
|
||||
output reg [0 : 0] probe_out15 = 'h0 ;
|
||||
output reg [0 : 0] probe_out16 = 'h0 ;
|
||||
output reg [15 : 0] probe_out17 = 'h0000 ;
|
||||
|
||||
|
||||
endmodule
|
||||
+84
@@ -0,0 +1,84 @@
|
||||
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
//
|
||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
// DO NOT MODIFY THIS FILE.
|
||||
|
||||
// IP VLNV: xilinx.com:ip:vio:3.0
|
||||
// IP Revision: 20
|
||||
|
||||
// The following must be inserted into your Verilog file for this
|
||||
// core to be instantiated. Change the instance name and port connections
|
||||
// (in parentheses) to your own signal names.
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
vio_rfcontrl your_instance_name (
|
||||
.clk(clk), // input wire clk
|
||||
.probe_in0(probe_in0), // input wire [15 : 0] probe_in0
|
||||
.probe_out0(probe_out0), // output wire [0 : 0] probe_out0
|
||||
.probe_out1(probe_out1), // output wire [0 : 0] probe_out1
|
||||
.probe_out2(probe_out2), // output wire [15 : 0] probe_out2
|
||||
.probe_out3(probe_out3), // output wire [7 : 0] probe_out3
|
||||
.probe_out4(probe_out4), // output wire [3 : 0] probe_out4
|
||||
.probe_out5(probe_out5), // output wire [3 : 0] probe_out5
|
||||
.probe_out6(probe_out6), // output wire [3 : 0] probe_out6
|
||||
.probe_out7(probe_out7), // output wire [3 : 0] probe_out7
|
||||
.probe_out8(probe_out8), // output wire [7 : 0] probe_out8
|
||||
.probe_out9(probe_out9), // output wire [7 : 0] probe_out9
|
||||
.probe_out10(probe_out10), // output wire [15 : 0] probe_out10
|
||||
.probe_out11(probe_out11), // output wire [15 : 0] probe_out11
|
||||
.probe_out12(probe_out12), // output wire [15 : 0] probe_out12
|
||||
.probe_out13(probe_out13), // output wire [0 : 0] probe_out13
|
||||
.probe_out14(probe_out14), // output wire [0 : 0] probe_out14
|
||||
.probe_out15(probe_out15), // output wire [0 : 0] probe_out15
|
||||
.probe_out16(probe_out16), // output wire [0 : 0] probe_out16
|
||||
.probe_out17(probe_out17) // output wire [15 : 0] probe_out17
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
// You must compile the wrapper file vio_rfcontrl.v when simulating
|
||||
// the core, vio_rfcontrl. When compiling the wrapper file, be sure to
|
||||
// reference the Verilog simulation library.
|
||||
|
||||
+113
@@ -0,0 +1,113 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:vio:3.0
|
||||
-- IP Revision: 20
|
||||
|
||||
-- The following code must appear in the VHDL architecture header.
|
||||
|
||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||
COMPONENT vio_rfcontrl
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
probe_in0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe_out1 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe_out2 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
probe_out3 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
probe_out4 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe_out5 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe_out6 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe_out7 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe_out8 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
probe_out9 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
probe_out10 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
probe_out11 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
probe_out12 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
probe_out13 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe_out14 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe_out15 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe_out16 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe_out17 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
|
||||
-- The following code must appear in the VHDL architecture
|
||||
-- body. Substitute your own instance name and net names.
|
||||
|
||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||
your_instance_name : vio_rfcontrl
|
||||
PORT MAP (
|
||||
clk => clk,
|
||||
probe_in0 => probe_in0,
|
||||
probe_out0 => probe_out0,
|
||||
probe_out1 => probe_out1,
|
||||
probe_out2 => probe_out2,
|
||||
probe_out3 => probe_out3,
|
||||
probe_out4 => probe_out4,
|
||||
probe_out5 => probe_out5,
|
||||
probe_out6 => probe_out6,
|
||||
probe_out7 => probe_out7,
|
||||
probe_out8 => probe_out8,
|
||||
probe_out9 => probe_out9,
|
||||
probe_out10 => probe_out10,
|
||||
probe_out11 => probe_out11,
|
||||
probe_out12 => probe_out12,
|
||||
probe_out13 => probe_out13,
|
||||
probe_out14 => probe_out14,
|
||||
probe_out15 => probe_out15,
|
||||
probe_out16 => probe_out16,
|
||||
probe_out17 => probe_out17
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
-- You must compile the wrapper file vio_rfcontrl.vhd when simulating
|
||||
-- the core, vio_rfcontrl. When compiling the wrapper file, be sure to
|
||||
-- reference the VHDL simulation library.
|
||||
|
||||
LFS
BIN
Binary file not shown.
projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_sim_netlist.vhdl
LFS
BIN
Binary file not shown.
+42
@@ -0,0 +1,42 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Mon May 8 10:18:46 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.v
|
||||
// Design : vio_rfcontrl
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
|
||||
module vio_rfcontrl(clk, probe_in0, probe_out0, probe_out1,
|
||||
probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9,
|
||||
probe_out10, probe_out11, probe_out12, probe_out13, probe_out14, probe_out15, probe_out16,
|
||||
probe_out17)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[15:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[15:0]" */;
|
||||
input clk;
|
||||
input [15:0]probe_in0;
|
||||
output [0:0]probe_out0;
|
||||
output [0:0]probe_out1;
|
||||
output [15:0]probe_out2;
|
||||
output [7:0]probe_out3;
|
||||
output [3:0]probe_out4;
|
||||
output [3:0]probe_out5;
|
||||
output [3:0]probe_out6;
|
||||
output [3:0]probe_out7;
|
||||
output [7:0]probe_out8;
|
||||
output [7:0]probe_out9;
|
||||
output [15:0]probe_out10;
|
||||
output [15:0]probe_out11;
|
||||
output [15:0]probe_out12;
|
||||
output [0:0]probe_out13;
|
||||
output [0:0]probe_out14;
|
||||
output [0:0]probe_out15;
|
||||
output [0:0]probe_out16;
|
||||
output [15:0]probe_out17;
|
||||
endmodule
|
||||
+49
@@ -0,0 +1,49 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Mon May 8 10:18:46 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.vhdl
|
||||
-- Design : vio_rfcontrl
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity vio_rfcontrl is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe_in0 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out3 : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe_out5 : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe_out6 : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe_out7 : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe_out8 : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe_out9 : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe_out10 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out11 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out12 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out13 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out15 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out16 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out17 : out STD_LOGIC_VECTOR ( 15 downto 0 )
|
||||
);
|
||||
|
||||
end vio_rfcontrl;
|
||||
|
||||
architecture stub of vio_rfcontrl is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[15:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[15:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+12017
File diff suppressed because it is too large
Load Diff
+27417
File diff suppressed because it is too large
Load Diff
+17045
File diff suppressed because it is too large
Load Diff
+1367
File diff suppressed because it is too large
Load Diff
+1317
File diff suppressed because it is too large
Load Diff
+1127
File diff suppressed because it is too large
Load Diff
+2403
File diff suppressed because it is too large
Load Diff
+418
@@ -0,0 +1,418 @@
|
||||
`protect begin_protected
|
||||
`protect version = 1
|
||||
`protect encrypt_agent = "XILINX"
|
||||
`protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1"
|
||||
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
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||||
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||||
`protect key_block
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||||
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||||
|
||||
`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
|
||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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||||
`protect key_block
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`protect key_block
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||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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||||
`protect end_protected
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+512
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|
||||
00000001 0 173 0 0 347 0
|
||||
ffffffff 0 174 0 0 348 0
|
||||
ffffffff 0 174 0 0 349 0
|
||||
ffffffff 0 175 0 0 350 0
|
||||
ffffffff 0 175 0 0 351 0
|
||||
ffffffff 0 176 0 0 352 0
|
||||
ffffffff 0 176 0 0 353 0
|
||||
ffffffff 0 177 0 0 354 0
|
||||
ffffffff 0 177 0 0 355 0
|
||||
00000001 0 178 0 0 356 0
|
||||
00000001 0 178 0 0 357 0
|
||||
00000001 0 179 0 0 358 0
|
||||
00000001 0 179 0 0 359 0
|
||||
ffffffff 0 180 0 0 360 0
|
||||
ffffffff 0 180 0 0 361 0
|
||||
ffffffff 0 181 0 0 362 0
|
||||
ffffffff 0 181 0 0 363 0
|
||||
00000001 0 182 0 0 364 0
|
||||
00000001 0 182 0 0 365 0
|
||||
00000001 0 183 0 0 366 0
|
||||
00000001 0 183 0 0 367 0
|
||||
00000001 0 184 0 0 368 0
|
||||
00000001 0 184 0 0 369 0
|
||||
00000001 0 185 0 0 370 0
|
||||
00000001 0 185 0 0 371 0
|
||||
ffffffff 0 186 0 0 372 0
|
||||
ffffffff 0 186 0 0 373 0
|
||||
ffffffff 0 187 0 0 374 0
|
||||
ffffffff 0 187 0 0 375 0
|
||||
00000001 0 188 0 0 376 0
|
||||
00000001 0 188 0 0 377 0
|
||||
00000001 0 189 0 0 378 0
|
||||
00000001 0 189 0 0 379 0
|
||||
ffffffff 0 190 0 0 380 0
|
||||
ffffffff 0 190 0 0 381 0
|
||||
ffffffff 0 191 0 0 382 0
|
||||
ffffffff 0 191 0 0 383 0
|
||||
ffffffff 0 192 0 0 384 0
|
||||
ffffffff 0 192 0 0 385 0
|
||||
ffffffff 0 193 0 0 386 0
|
||||
ffffffff 0 193 0 0 387 0
|
||||
ffffffff 0 194 0 0 388 0
|
||||
ffffffff 0 194 0 0 389 0
|
||||
ffffffff 0 195 0 0 390 0
|
||||
ffffffff 0 195 0 0 391 0
|
||||
00000001 0 196 0 0 392 0
|
||||
00000001 0 196 0 0 393 0
|
||||
00000001 0 197 0 0 394 0
|
||||
00000001 0 197 0 0 395 0
|
||||
ffffffff 0 198 0 0 396 0
|
||||
ffffffff 0 198 0 0 397 0
|
||||
ffffffff 0 199 0 0 398 0
|
||||
ffffffff 0 199 0 0 399 0
|
||||
ffffffff 0 200 0 0 400 0
|
||||
ffffffff 0 200 0 0 401 0
|
||||
ffffffff 0 201 0 0 402 0
|
||||
ffffffff 0 201 0 0 403 0
|
||||
ffffffff 0 202 0 0 404 0
|
||||
ffffffff 0 202 0 0 405 0
|
||||
ffffffff 0 203 0 0 406 0
|
||||
ffffffff 0 203 0 0 407 0
|
||||
00000001 0 204 0 0 408 0
|
||||
00000001 0 204 0 0 409 0
|
||||
00000001 0 205 0 0 410 0
|
||||
00000001 0 205 0 0 411 0
|
||||
00000001 0 206 0 0 412 0
|
||||
00000001 0 206 0 0 413 0
|
||||
00000001 0 207 0 0 414 0
|
||||
00000001 0 207 0 0 415 0
|
||||
ffffffff 0 208 0 0 416 0
|
||||
ffffffff 0 208 0 0 417 0
|
||||
ffffffff 0 209 0 0 418 0
|
||||
ffffffff 0 209 0 0 419 0
|
||||
ffffffff 0 210 0 0 420 0
|
||||
ffffffff 0 210 0 0 421 0
|
||||
ffffffff 0 211 0 0 422 0
|
||||
ffffffff 0 211 0 0 423 0
|
||||
00000001 0 212 0 0 424 0
|
||||
00000001 0 212 0 0 425 0
|
||||
00000001 0 213 0 0 426 0
|
||||
00000001 0 213 0 0 427 0
|
||||
00000001 0 214 0 0 428 0
|
||||
00000001 0 214 0 0 429 0
|
||||
00000001 0 215 0 0 430 0
|
||||
00000001 0 215 0 0 431 0
|
||||
ffffffff 0 216 0 0 432 0
|
||||
ffffffff 0 216 0 0 433 0
|
||||
ffffffff 0 217 0 0 434 0
|
||||
ffffffff 0 217 0 0 435 0
|
||||
00000001 0 218 0 0 436 0
|
||||
00000001 0 218 0 0 437 0
|
||||
00000001 0 219 0 0 438 0
|
||||
00000001 0 219 0 0 439 0
|
||||
ffffffff 0 220 0 0 440 0
|
||||
ffffffff 0 220 0 0 441 0
|
||||
ffffffff 0 221 0 0 442 0
|
||||
ffffffff 0 221 0 0 443 0
|
||||
00000001 0 222 0 0 444 0
|
||||
00000001 0 222 0 0 445 0
|
||||
00000001 0 223 0 0 446 0
|
||||
00000001 0 223 0 0 447 0
|
||||
ffffffff 0 224 0 0 448 0
|
||||
ffffffff 0 224 0 0 449 0
|
||||
ffffffff 0 225 0 0 450 0
|
||||
ffffffff 0 225 0 0 451 0
|
||||
00000001 0 226 0 0 452 0
|
||||
00000001 0 226 0 0 453 0
|
||||
00000001 0 227 0 0 454 0
|
||||
00000001 0 227 0 0 455 0
|
||||
ffffffff 0 228 0 0 456 0
|
||||
ffffffff 0 228 0 0 457 0
|
||||
ffffffff 0 229 0 0 458 0
|
||||
ffffffff 0 229 0 0 459 0
|
||||
ffffffff 0 230 0 0 460 0
|
||||
ffffffff 0 230 0 0 461 0
|
||||
ffffffff 0 231 0 0 462 0
|
||||
ffffffff 0 231 0 0 463 0
|
||||
ffffffff 0 232 0 0 464 0
|
||||
ffffffff 0 232 0 0 465 0
|
||||
ffffffff 0 233 0 0 466 0
|
||||
ffffffff 0 233 0 0 467 0
|
||||
ffffffff 0 234 0 0 468 0
|
||||
ffffffff 0 234 0 0 469 0
|
||||
ffffffff 0 235 0 0 470 0
|
||||
ffffffff 0 235 0 0 471 0
|
||||
ffffffff 0 236 0 0 472 0
|
||||
ffffffff 0 236 0 0 473 0
|
||||
ffffffff 0 237 0 0 474 0
|
||||
ffffffff 0 237 0 0 475 0
|
||||
ffffffff 0 238 0 0 476 0
|
||||
ffffffff 0 238 0 0 477 0
|
||||
ffffffff 0 239 0 0 478 0
|
||||
ffffffff 0 239 0 0 479 0
|
||||
ffffffff 0 240 0 0 480 0
|
||||
ffffffff 0 240 0 0 481 0
|
||||
ffffffff 0 241 0 0 482 0
|
||||
ffffffff 0 241 0 0 483 0
|
||||
00000001 0 242 0 0 484 0
|
||||
00000001 0 242 0 0 485 0
|
||||
00000001 0 243 0 0 486 0
|
||||
00000001 0 243 0 0 487 0
|
||||
00000001 0 244 0 0 488 0
|
||||
00000001 0 244 0 0 489 0
|
||||
00000001 0 245 0 0 490 0
|
||||
00000001 0 245 0 0 491 0
|
||||
00000001 0 246 0 0 492 0
|
||||
00000001 0 246 0 0 493 0
|
||||
00000001 0 247 0 0 494 0
|
||||
00000001 0 247 0 0 495 0
|
||||
00000001 0 248 0 0 496 0
|
||||
00000001 0 248 0 0 497 0
|
||||
00000001 0 249 0 0 498 0
|
||||
00000001 0 249 0 0 499 0
|
||||
00000001 0 250 0 0 500 0
|
||||
00000001 0 250 0 0 501 0
|
||||
00000001 0 251 0 0 502 0
|
||||
00000001 0 251 0 0 503 0
|
||||
00000001 0 252 0 0 504 0
|
||||
00000001 0 252 0 0 505 0
|
||||
00000001 0 253 0 0 506 0
|
||||
00000001 0 253 0 0 507 0
|
||||
ffffffff 0 254 0 0 508 0
|
||||
ffffffff 0 254 0 0 509 0
|
||||
ffffffff 0 255 0 0 510 0
|
||||
ffffffff 0 255 0 0 511 0
|
||||
+83
@@ -0,0 +1,83 @@
|
||||
MEMORY_INITIALIZATION_RADIX = 10;
|
||||
MEMORY_INITIALIZATION_VECTOR =
|
||||
1076,
|
||||
1088,
|
||||
1100,
|
||||
1112,
|
||||
1124,
|
||||
1136,
|
||||
1148,
|
||||
1160,
|
||||
1172,
|
||||
1184,
|
||||
1196,
|
||||
1208,
|
||||
1220,
|
||||
1232,
|
||||
1244,
|
||||
1256,
|
||||
1268,
|
||||
1280,
|
||||
1292,
|
||||
1304,
|
||||
1316,
|
||||
1328,
|
||||
1340,
|
||||
1352,
|
||||
1364,
|
||||
1376,
|
||||
1388,
|
||||
1400,
|
||||
1412,
|
||||
1424,
|
||||
1436,
|
||||
1448,
|
||||
1460,
|
||||
1472,
|
||||
1484,
|
||||
1496,
|
||||
1508,
|
||||
1520,
|
||||
1532,
|
||||
1544,
|
||||
1556,
|
||||
1568,
|
||||
1580,
|
||||
1592,
|
||||
1604,
|
||||
1616,
|
||||
1628,
|
||||
1640,
|
||||
1652,
|
||||
1664,
|
||||
1676,
|
||||
1688,
|
||||
1700,
|
||||
1712,
|
||||
1724,
|
||||
1736,
|
||||
1748,
|
||||
1760,
|
||||
1772,
|
||||
1784,
|
||||
1796,
|
||||
1808,
|
||||
1820,
|
||||
1832,
|
||||
1844,
|
||||
1856,
|
||||
1868,
|
||||
1880,
|
||||
1892,
|
||||
1904,
|
||||
1916,
|
||||
1928,
|
||||
1940,
|
||||
1952,
|
||||
1964,
|
||||
1976,
|
||||
1988,
|
||||
2000,
|
||||
2012,
|
||||
2024,
|
||||
2036,
|
||||
Executable
+514
@@ -0,0 +1,514 @@
|
||||
RADIX = 10;
|
||||
COEFDATA =
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
-1,
|
||||
-1,
|
||||
-1,
|
||||
-1;
|
||||
+81
@@ -0,0 +1,81 @@
|
||||
0000010000110100
|
||||
0000010001000000
|
||||
0000010001001100
|
||||
0000010001011000
|
||||
0000010001100100
|
||||
0000010001110000
|
||||
0000010001111100
|
||||
0000010010001000
|
||||
0000010010010100
|
||||
0000010010100000
|
||||
0000010010101100
|
||||
0000010010111000
|
||||
0000010011000100
|
||||
0000010011010000
|
||||
0000010011011100
|
||||
0000010011101000
|
||||
0000010011110100
|
||||
0000010100000000
|
||||
0000010100001100
|
||||
0000010100011000
|
||||
0000010100100100
|
||||
0000010100110000
|
||||
0000010100111100
|
||||
0000010101001000
|
||||
0000010101010100
|
||||
0000010101100000
|
||||
0000010101101100
|
||||
0000010101111000
|
||||
0000010110000100
|
||||
0000010110010000
|
||||
0000010110011100
|
||||
0000010110101000
|
||||
0000010110110100
|
||||
0000010111000000
|
||||
0000010111001100
|
||||
0000010111011000
|
||||
0000010111100100
|
||||
0000010111110000
|
||||
0000010111111100
|
||||
0000011000001000
|
||||
0000011000010100
|
||||
0000011000100000
|
||||
0000011000101100
|
||||
0000011000111000
|
||||
0000011001000100
|
||||
0000011001010000
|
||||
0000011001011100
|
||||
0000011001101000
|
||||
0000011001110100
|
||||
0000011010000000
|
||||
0000011010001100
|
||||
0000011010011000
|
||||
0000011010100100
|
||||
0000011010110000
|
||||
0000011010111100
|
||||
0000011011001000
|
||||
0000011011010100
|
||||
0000011011100000
|
||||
0000011011101100
|
||||
0000011011111000
|
||||
0000011100000100
|
||||
0000011100010000
|
||||
0000011100011100
|
||||
0000011100101000
|
||||
0000011100110100
|
||||
0000011101000000
|
||||
0000011101001100
|
||||
0000011101011000
|
||||
0000011101100100
|
||||
0000011101110000
|
||||
0000011101111100
|
||||
0000011110001000
|
||||
0000011110010100
|
||||
0000011110100000
|
||||
0000011110101100
|
||||
0000011110111000
|
||||
0000011111000100
|
||||
0000011111010000
|
||||
0000011111011100
|
||||
0000011111101000
|
||||
0000011111110100
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user