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finish coding and testing of online acq; add sample data

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串行在线捕获程序已经完成编写,并进行了仿真和测试(对飞和814均可用);增加了在电子所使用转台测试的幅相采集数据
This commit is contained in:
josh
2023-05-08 19:13:53 +08:00
parent e07389e326
commit 2d4650a3b6
2835 changed files with 408373 additions and 181193 deletions
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projects/dl814_k7/dl814_k7_online_acq/project.tcl
+109 -172
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@@ -3,7 +3,7 @@
#
# project.tcl: Tcl script for re-creating project 'project'
#
# Generated by Vivado on Mon Apr 24 11:12:47 CST 2023
# Generated by Vivado on Mon May 08 18:52:13 CST 2023
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
@@ -27,90 +27,80 @@
#
# 3. The following remote source files that were added to the original project:-
#
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/vio_hop/vio_hop.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/vio_manual_ctrl/vio_manual_ctrl.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/ila_rx_pre_ant/ila_rx_pre_ant.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/ila_rx_pre_sys/ila_rx_pre_sys.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ila_freq_comp/ila_freq_comp.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/vio_freq_comp/vio_freq_comp.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/vio_manual_ctrl/vio_manual_ctrl.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/ila_cal/ila_cal.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/basic_driver/ila_8x12_2x30_131072/ila_8x12_2x30_131072.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/basic_driver/ila_2x12x131072/ila_2x12x131072.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/basic_driver/ila_8x12_8192/ila_8x12_8192.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/basic_driver/ila_2x12x1024/ila_2x12x1024.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/ant_rf_interface/vio_rf_rd/vio_rf_rd.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/ant_rf_interface/ila_AntCtrl/ila_AntCtrl.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/ant_rf_interface/ila_rfcontrl/ila_rfcontrl.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/ant_rf_interface/vio_ant_test/vio_ant_test.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/ant_rf_interface/vio_rfcontrl/vio_rfcontrl.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/rx_pre_process/rom_hop_data/rom_hop_data.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/cmpy_16x12/cmpy_16x12.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/ram_hop_data/ram_hop_data.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/fifo_accor_cdc/fifo_accor_cdc.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/add_s24_s32_s32/add_s24_s32_s32.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/cmpy_12x12/cmpy_12x12.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/vio_rfcontrl/vio_rfcontrl.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/mult_18x18/mult_18x18.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/fir_prbs7_invert_rep4/fir_prbs7_invert_rep4.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/cmpy_12x8/cmpy_12x8.xci"
# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci"
# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xci"
# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8.xci"
# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci"
# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/hop_rom/hop_rom.xci"
# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/hrc_64_12_025/hrc_64_12_025.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/ant_rf_interface/fifo_AntCtrl/fifo_AntCtrl.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/rom_freq_word/rom_freq_word.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ipi-bd/basic_driver_bd/system_bd.bd"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/sys_clock_gen/ant_clk_gen_stg2/ant_clk_gen_stg2.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/sys_clock_gen/ant_clk_gen_stg1/ant_clk_gen_stg1.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/sys_clock_gen/ad9361_clk_gen_cmos_2t2r/ad9361_clk_gen_cmos_2t2r.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/Sisyif_src/ADF4351_2.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/Sisyif_src/FRAC1.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/Sisyif_src/INT_ROMb.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/Sisyif_src/R_CAL_1.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/Sisyif_src/R_CAL_2.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/Sisyif_src/R_CAL_3.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/Sisyif_src/R_CAL_4.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/Sisyif_src/Sisyif.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/Sisyif_src/T_CAL.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/rx_pre_process/accor_mat_formatting.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/rx_pre_process/accum_cmplx_mat.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/rx_pre_process/acorr_cmplx_col_vec.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/rx_pre_process/ad9361_phase_cal_coarse.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/rtl/Sisyif_src/ADF4351_2.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/rtl/Sisyif_src/FRAC1.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/rtl/Sisyif_src/INT_ROMb.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/rtl/Sisyif_src/R_CAL_1.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/rtl/Sisyif_src/R_CAL_2.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/rtl/Sisyif_src/R_CAL_3.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/rtl/Sisyif_src/R_CAL_4.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/rtl/Sisyif_src/Sisyif.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/rtl/Sisyif_src/T_CAL.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/rtl/rx_pre_process/ad9361_phase_cal_coarse.v"
# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_rx_map_cmos_dual.v"
# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_tx_map_cmos_dual.v"
# "/home/josh/Workspace/vivado-git/common/adder_tree_ppl.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/Sisyif_src/adf4371_a.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/Sisyif_src/adf4371_b.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/ant_rf_ctrl.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/Sisyif_src/band_rom_a.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/Sisyif_src/band_rom_b.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/clk_dist.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/Sisyif_src/ds18b20_temp.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/Sisyif_src/frac2_rom.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/Sisyif_src/fre_caliatt.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/Sisyif_src/mgc_ctrl.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/Sisyif_src/mod2_rom.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/rx_pre_process/rx_pre_process.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/rx_pre_process/rx_pre_test.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/rx_pre_process/spatial_filter.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/Sisyif_src/spi_master.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/Sisyif_src/spi_salve.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/Sisyif_src/spi_tx.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/rtl/Sisyif_src/adf4371_a.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/rtl/Sisyif_src/adf4371_b.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/rtl/ant_rf_ctrl.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/rtl/Sisyif_src/band_rom_a.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/rtl/Sisyif_src/band_rom_b.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/rtl/clk_dist.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/rtl/Sisyif_src/ds18b20_temp.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/rtl/Sisyif_src/frac2_rom.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/rtl/Sisyif_src/fre_caliatt.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/rtl/freq_comp.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/rtl/Sisyif_src/mgc_ctrl.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/rtl/Sisyif_src/mod2_rom.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/rtl/rf_auto_switch_freq.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/rtl/rx_dmf.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/rtl/Sisyif_src/spi_master.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/rtl/Sisyif_src/spi_salve.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/rtl/Sisyif_src/spi_tx.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ipi-bd/basic_driver_bd/hdl/system_bd_wrapper.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/tx_pre_process.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/rtl/tx_pre_process.v"
# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/rtl/tx_qpsk.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/rx_pre_process/weight_vec_formatting.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/system_top.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/rtl/system_top.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/rotate_16b/rotate_16b.xci"
# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/coe/sweep_freq.coe"
# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/coe/hrc_64_12_025.coe"
# "/home/josh/Workspace/vivado-git/common/ApproxModuli_26bit.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/rx_pre_process/ad9361_phase_cal_fine.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/vio_cal/vio_cal.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/rx_pre_process/coe/one_hop_data.coe"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/rtl/rx_pre_process/ad9361_phase_cal_fine.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/ant_rf_interface/vio_ant_rd/vio_ant_rd.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/atan2_16b/atan2_16b.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/rotate_16b/rotate_16b.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/basic_driver/vio_clk_ld_rd/vio_clk_ld_rd.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/constraints/k7401t_ad9516_2ad9361_physical.xdc"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/constraints/k7410t_ad9516_2ad9361_timing.xdc"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/testbenches/tb_rx_pre_test.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/testbenches/tb_rx_test.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/testbenches/tb_rx_pre.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/testbenches/tb_tx_pre_process.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/testbenches/tb_xpm_cdc_pulse.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/coe/freq_word.coe"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/coe/prbs7_invert_rep4.coe"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/constraints/k7401t_ad9516_2ad9361_physical.xdc"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/constraints/k7410t_ad9516_2ad9361_timing.xdc"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/testbenches/tb_freq_comp.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/testbenches/tb_rx_dmf.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/testbenches/tb_tx_pre_process.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/testbenches/tb_xpm_cdc_pulse.v"
#
#*****************************************************************************************
@@ -189,7 +179,7 @@ set proj_dir [get_property directory [current_project]]
# Set project properties
set obj [current_project]
set_property -name "compxlib.modelsim_compiled_library_dir" -value "/home/josh/Mentor/CompLib/2019.1.3" -objects $obj
set_property -name "compxlib.modelsim_compiled_library_dir" -value "/home/josh/Software/Xilinx/CompLib/Model/2019.1" -objects $obj
set_property -name "compxlib.vcs_compiled_library_dir" -value "/home/josh/Software/Xilinx/CompLib/VCS/2019.1" -objects $obj
set_property -name "corecontainer.enable" -value "1" -objects $obj
set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
@@ -217,15 +207,17 @@ set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_use
set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
set_property -name "simulator_language" -value "Mixed" -objects $obj
set_property -name "target_simulator" -value "VCS" -objects $obj
set_property -name "webtalk.activehdl_export_sim" -value "89" -objects $obj
set_property -name "webtalk.ies_export_sim" -value "89" -objects $obj
set_property -name "webtalk.modelsim_export_sim" -value "89" -objects $obj
set_property -name "webtalk.modelsim_launch_sim" -value "2" -objects $obj
set_property -name "webtalk.questa_export_sim" -value "89" -objects $obj
set_property -name "webtalk.riviera_export_sim" -value "89" -objects $obj
set_property -name "webtalk.vcs_export_sim" -value "89" -objects $obj
set_property -name "webtalk.vcs_launch_sim" -value "69" -objects $obj
set_property -name "webtalk.xsim_export_sim" -value "89" -objects $obj
set_property -name "webtalk.activehdl_export_sim" -value "105" -objects $obj
set_property -name "webtalk.ies_export_sim" -value "105" -objects $obj
set_property -name "webtalk.modelsim_export_sim" -value "106" -objects $obj
set_property -name "webtalk.modelsim_launch_sim" -value "4" -objects $obj
set_property -name "webtalk.questa_export_sim" -value "106" -objects $obj
set_property -name "webtalk.riviera_export_sim" -value "105" -objects $obj
set_property -name "webtalk.vcs_export_sim" -value "105" -objects $obj
set_property -name "webtalk.vcs_launch_sim" -value "256" -objects $obj
set_property -name "webtalk.xcelium_export_sim" -value "11" -objects $obj
set_property -name "webtalk.xsim_export_sim" -value "106" -objects $obj
set_property -name "webtalk.xsim_launch_sim" -value "2" -objects $obj
set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj
# Create 'sources_1' fileset (if not found)
@@ -243,31 +235,27 @@ update_ip_catalog -rebuild
# Set 'sources_1' fileset object
set obj [get_filesets sources_1]
set files [list \
[file normalize "${origin_dir}/ip/vio_hop/vio_hop.xci"] \
[file normalize "${origin_dir}/ip/ila_freq_comp/ila_freq_comp.xci"] \
[file normalize "${origin_dir}/ip/vio_freq_comp/vio_freq_comp.xci"] \
[file normalize "${origin_dir}/ip/vio_manual_ctrl/vio_manual_ctrl.xci"] \
[file normalize "${origin_dir}/../common_ip/rx_pre_process/ila_rx_pre_ant/ila_rx_pre_ant.xci"] \
[file normalize "${origin_dir}/../common_ip/rx_pre_process/ila_rx_pre_sys/ila_rx_pre_sys.xci"] \
[file normalize "${origin_dir}/../common_ip/rx_pre_process/ila_cal/ila_cal.xci"] \
[file normalize "${origin_dir}/../common_ip/basic_driver/ila_8x12_2x30_131072/ila_8x12_2x30_131072.xci"] \
[file normalize "${origin_dir}/../common_ip/basic_driver/ila_2x12x131072/ila_2x12x131072.xci"] \
[file normalize "${origin_dir}/../common_ip/basic_driver/ila_8x12_8192/ila_8x12_8192.xci"] \
[file normalize "${origin_dir}/../common_ip/basic_driver/ila_2x12x1024/ila_2x12x1024.xci"] \
[file normalize "${origin_dir}/../common_ip/ant_rf_interface/vio_rf_rd/vio_rf_rd.xci"] \
[file normalize "${origin_dir}/../common_ip/ant_rf_interface/ila_AntCtrl/ila_AntCtrl.xci"] \
[file normalize "${origin_dir}/../common_ip/ant_rf_interface/ila_rfcontrl/ila_rfcontrl.xci"] \
[file normalize "${origin_dir}/../common_ip/ant_rf_interface/vio_ant_test/vio_ant_test.xci"] \
[file normalize "${origin_dir}/../common_ip/ant_rf_interface/vio_rfcontrl/vio_rfcontrl.xci"] \
[file normalize "${origin_dir}/ip/rx_pre_process/rom_hop_data/rom_hop_data.xci"] \
[file normalize "${origin_dir}/../common_ip/rx_pre_process/cmpy_16x12/cmpy_16x12.xci"] \
[file normalize "${origin_dir}/../common_ip/rx_pre_process/ram_hop_data/ram_hop_data.xci"] \
[file normalize "${origin_dir}/../common_ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc.xci"] \
[file normalize "${origin_dir}/../common_ip/rx_pre_process/fifo_accor_cdc/fifo_accor_cdc.xci"] \
[file normalize "${origin_dir}/../common_ip/rx_pre_process/add_s24_s32_s32/add_s24_s32_s32.xci"] \
[file normalize "${origin_dir}/../common_ip/rx_pre_process/cmpy_12x12/cmpy_12x12.xci"] \
[file normalize "${origin_dir}/ip/vio_rfcontrl/vio_rfcontrl.xci"] \
[file normalize "${origin_dir}/ip/mult_18x18/mult_18x18.xci"] \
[file normalize "${origin_dir}/ip/fir_prbs7_invert_rep4/fir_prbs7_invert_rep4.xci"] \
[file normalize "${origin_dir}/ip/cmpy_12x8/cmpy_12x8.xci"] \
[file normalize "${origin_dir}/../../../modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci"] \
[file normalize "${origin_dir}/../../../modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xci"] \
[file normalize "${origin_dir}/../../../modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8.xci"] \
[file normalize "${origin_dir}/../../../modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci"] \
[file normalize "${origin_dir}/../../../modules/xc7k410tffg900-2/tx_qpsk/ip/hop_rom/hop_rom.xci"] \
[file normalize "${origin_dir}/../../../modules/xc7k410tffg900-2/tx_qpsk/ip/hrc_64_12_025/hrc_64_12_025.xci"] \
[file normalize "${origin_dir}/../common_ip/ant_rf_interface/fifo_AntCtrl/fifo_AntCtrl.xci"] \
[file normalize "${origin_dir}/ip/rom_freq_word/rom_freq_word.xci"] \
[file normalize "${origin_dir}/../common_ipi-bd/basic_driver_bd/system_bd.bd"] \
[file normalize "${origin_dir}/../common_ip/sys_clock_gen/ant_clk_gen_stg2/ant_clk_gen_stg2.xci"] \
[file normalize "${origin_dir}/../common_ip/sys_clock_gen/ant_clk_gen_stg1/ant_clk_gen_stg1.xci"] \
@@ -281,13 +269,9 @@ set files [list \
[file normalize "${origin_dir}/rtl/Sisyif_src/R_CAL_4.v"] \
[file normalize "${origin_dir}/rtl/Sisyif_src/Sisyif.v"] \
[file normalize "${origin_dir}/rtl/Sisyif_src/T_CAL.v"] \
[file normalize "${origin_dir}/rtl/rx_pre_process/accor_mat_formatting.v"] \
[file normalize "${origin_dir}/rtl/rx_pre_process/accum_cmplx_mat.v"] \
[file normalize "${origin_dir}/rtl/rx_pre_process/acorr_cmplx_col_vec.v"] \
[file normalize "${origin_dir}/rtl/rx_pre_process/ad9361_phase_cal_coarse.v"] \
[file normalize "${origin_dir}/../../../modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_rx_map_cmos_dual.v"] \
[file normalize "${origin_dir}/../../../modules/xc7k410tffg900-2/ad9361_mapping/rtl/ad9361_tx_map_cmos_dual.v"] \
[file normalize "${origin_dir}/../../../common/adder_tree_ppl.v"] \
[file normalize "${origin_dir}/rtl/Sisyif_src/adf4371_a.v"] \
[file normalize "${origin_dir}/rtl/Sisyif_src/adf4371_b.v"] \
[file normalize "${origin_dir}/rtl/ant_rf_ctrl.v"] \
@@ -297,34 +281,42 @@ set files [list \
[file normalize "${origin_dir}/rtl/Sisyif_src/ds18b20_temp.v"] \
[file normalize "${origin_dir}/rtl/Sisyif_src/frac2_rom.v"] \
[file normalize "${origin_dir}/rtl/Sisyif_src/fre_caliatt.v"] \
[file normalize "${origin_dir}/rtl/freq_comp.v"] \
[file normalize "${origin_dir}/rtl/Sisyif_src/mgc_ctrl.v"] \
[file normalize "${origin_dir}/rtl/Sisyif_src/mod2_rom.v"] \
[file normalize "${origin_dir}/rtl/rx_pre_process/rx_pre_process.v"] \
[file normalize "${origin_dir}/rtl/rx_pre_process/rx_pre_test.v"] \
[file normalize "${origin_dir}/rtl/rx_pre_process/spatial_filter.v"] \
[file normalize "${origin_dir}/rtl/rf_auto_switch_freq.v"] \
[file normalize "${origin_dir}/rtl/rx_dmf.v"] \
[file normalize "${origin_dir}/rtl/Sisyif_src/spi_master.v"] \
[file normalize "${origin_dir}/rtl/Sisyif_src/spi_salve.v"] \
[file normalize "${origin_dir}/rtl/Sisyif_src/spi_tx.v"] \
[file normalize "${origin_dir}/../common_ipi-bd/basic_driver_bd/hdl/system_bd_wrapper.v"] \
[file normalize "${origin_dir}/rtl/tx_pre_process.v"] \
[file normalize "${origin_dir}/../../../modules/xc7k410tffg900-2/tx_qpsk/rtl/tx_qpsk.v"] \
[file normalize "${origin_dir}/rtl/rx_pre_process/weight_vec_formatting.v"] \
[file normalize "${origin_dir}/rtl/system_top.v"] \
[file normalize "${origin_dir}/../common_ip/rx_pre_process/rotate_16b/rotate_16b.xci"] \
[file normalize "${origin_dir}/../../../modules/xc7k410tffg900-2/tx_qpsk/ip/coe/sweep_freq.coe"] \
[file normalize "${origin_dir}/../../../modules/xc7k410tffg900-2/tx_qpsk/ip/coe/hrc_64_12_025.coe"] \
[file normalize "${origin_dir}/../../../common/ApproxModuli_26bit.v"] \
[file normalize "${origin_dir}/rtl/rx_pre_process/ad9361_phase_cal_fine.v"] \
[file normalize "${origin_dir}/ip/vio_cal/vio_cal.xci"] \
[file normalize "${origin_dir}/ip/rx_pre_process/coe/one_hop_data.coe"] \
[file normalize "${origin_dir}/../common_ip/ant_rf_interface/vio_ant_rd/vio_ant_rd.xci"] \
[file normalize "${origin_dir}/../common_ip/rx_pre_process/atan2_16b/atan2_16b.xci"] \
[file normalize "${origin_dir}/../common_ip/rx_pre_process/rotate_16b/rotate_16b.xci"] \
[file normalize "${origin_dir}/../common_ip/basic_driver/vio_clk_ld_rd/vio_clk_ld_rd.xci"] \
[file normalize "${origin_dir}/ip/coe/freq_word.coe"] \
[file normalize "${origin_dir}/ip/coe/prbs7_invert_rep4.coe"] \
]
add_files -norecurse -fileset $obj $files
# Set 'sources_1' fileset file properties for remote files
set file "$origin_dir/ip/vio_hop/vio_hop.xci"
set file "$origin_dir/ip/ila_freq_comp/ila_freq_comp.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
set_property -name "registered_with_manager" -value "1" -objects $file_obj
if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
set file "$origin_dir/ip/vio_freq_comp/vio_freq_comp.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
@@ -342,24 +334,6 @@ if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
set file "$origin_dir/../common_ip/rx_pre_process/ila_rx_pre_ant/ila_rx_pre_ant.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
set_property -name "registered_with_manager" -value "1" -objects $file_obj
if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
set file "$origin_dir/../common_ip/rx_pre_process/ila_rx_pre_sys/ila_rx_pre_sys.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
set_property -name "registered_with_manager" -value "1" -objects $file_obj
if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
set file "$origin_dir/../common_ip/rx_pre_process/ila_cal/ila_cal.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
@@ -369,7 +343,7 @@ if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
set file "$origin_dir/../common_ip/basic_driver/ila_8x12_2x30_131072/ila_8x12_2x30_131072.xci"
set file "$origin_dir/../common_ip/basic_driver/ila_8x12_8192/ila_8x12_8192.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
@@ -378,7 +352,7 @@ if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
set file "$origin_dir/../common_ip/basic_driver/ila_2x12x131072/ila_2x12x131072.xci"
set file "$origin_dir/../common_ip/basic_driver/ila_2x12x1024/ila_2x12x1024.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
@@ -423,7 +397,7 @@ if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
set file "$origin_dir/../common_ip/ant_rf_interface/vio_rfcontrl/vio_rfcontrl.xci"
set file "$origin_dir/ip/vio_rfcontrl/vio_rfcontrl.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
@@ -432,7 +406,7 @@ if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
set file "$origin_dir/ip/rx_pre_process/rom_hop_data/rom_hop_data.xci"
set file "$origin_dir/ip/mult_18x18/mult_18x18.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
@@ -441,7 +415,7 @@ if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
set file "$origin_dir/../common_ip/rx_pre_process/cmpy_16x12/cmpy_16x12.xci"
set file "$origin_dir/ip/fir_prbs7_invert_rep4/fir_prbs7_invert_rep4.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
@@ -450,7 +424,7 @@ if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
set file "$origin_dir/../common_ip/rx_pre_process/ram_hop_data/ram_hop_data.xci"
set file "$origin_dir/ip/cmpy_12x8/cmpy_12x8.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
@@ -459,34 +433,7 @@ if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
set file "$origin_dir/../common_ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
set_property -name "registered_with_manager" -value "1" -objects $file_obj
if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
set file "$origin_dir/../common_ip/rx_pre_process/fifo_accor_cdc/fifo_accor_cdc.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
set_property -name "registered_with_manager" -value "1" -objects $file_obj
if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
set file "$origin_dir/../common_ip/rx_pre_process/add_s24_s32_s32/add_s24_s32_s32.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
set_property -name "registered_with_manager" -value "1" -objects $file_obj
if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
set file "$origin_dir/../common_ip/rx_pre_process/cmpy_12x12/cmpy_12x12.xci"
set file "$origin_dir/../../../modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
@@ -513,15 +460,6 @@ if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
set file "$origin_dir/../../../modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
set_property -name "registered_with_manager" -value "1" -objects $file_obj
if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
set file "$origin_dir/../../../modules/xc7k410tffg900-2/tx_qpsk/ip/hop_rom/hop_rom.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
@@ -549,6 +487,15 @@ if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
set file "$origin_dir/ip/rom_freq_word/rom_freq_word.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
set_property -name "registered_with_manager" -value "1" -objects $file_obj
if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
set file "$origin_dir/../common_ipi-bd/basic_driver_bd/system_bd.bd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
@@ -581,7 +528,7 @@ if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
set file "$origin_dir/ip/vio_cal/vio_cal.xci"
set file "$origin_dir/../common_ip/rx_pre_process/rotate_16b/rotate_16b.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
@@ -608,15 +555,6 @@ if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
set file "$origin_dir/../common_ip/rx_pre_process/rotate_16b/rotate_16b.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
set_property -name "registered_with_manager" -value "1" -objects $file_obj
if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
set file "$origin_dir/../common_ip/basic_driver/vio_clk_ld_rd/vio_clk_ld_rd.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
@@ -671,9 +609,8 @@ if {[string equal [get_filesets -quiet sim_1] ""]} {
# Set 'sim_1' fileset object
set obj [get_filesets sim_1]
set files [list \
[file normalize "${origin_dir}/testbenches/tb_rx_pre_test.v"] \
[file normalize "${origin_dir}/testbenches/tb_rx_test.v"] \
[file normalize "${origin_dir}/testbenches/tb_rx_pre.v"] \
[file normalize "${origin_dir}/testbenches/tb_freq_comp.v"] \
[file normalize "${origin_dir}/testbenches/tb_rx_dmf.v"] \
[file normalize "${origin_dir}/testbenches/tb_tx_pre_process.v"] \
[file normalize "${origin_dir}/testbenches/tb_xpm_cdc_pulse.v"] \
]
@@ -687,7 +624,7 @@ add_files -norecurse -fileset $obj $files
# Set 'sim_1' fileset properties
set obj [get_filesets sim_1]
set_property -name "top" -value "tb_rx_pre_test" -objects $obj
set_property -name "top" -value "tb_freq_comp" -objects $obj
set_property -name "top_auto_set" -value "0" -objects $obj
set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
set_property -name "vcs.compile.vlogan.more_options" -value "-v2005 -kdb" -objects $obj