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finish coding and testing of online acq; add sample data

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串行在线捕获程序已经完成编写,并进行了仿真和测试(对飞和814均可用);增加了在电子所使用转台测试的幅相采集数据
This commit is contained in:
josh
2023-05-08 19:13:53 +08:00
parent e07389e326
commit 2d4650a3b6
2835 changed files with 408373 additions and 181193 deletions
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projects/dl814_k7/dl814_k7_online_acq/testbenches/tb_freq_comp.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05/06/2023 03:39:20 PM
// Design Name:
// Module Name: tb_freq_comp
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_freq_comp;
reg clk = 1'b1;
reg rst = 1'b1;
reg freq_comp_start = 'b0;
wire [11:0] tx_data_i, tx_data_q;
wire [31:0] freq_target;
wire freq_target_valid;
initial begin
#102;
rst = 1'b0;
#1000;
freq_comp_start = ~freq_comp_start;
end
always #10 clk = ~clk;
tx_qpsk u_tx_qpsk
(
.clk (clk ),
.rst (rst ),
.tx_data_i (tx_data_i ),
.tx_data_q (tx_data_q ),
// debug ports
.waveform_sel (2'd1 ),
.sweep_on (1'b0 ),
.freq_set ('b0 ),
.iq_sel (2'b11 ),
.bb_rshift (4'd0 )
);
freq_comp #(
.FREQ_WORD_LOWER(-1024 ),
.FREQ_WORD_UPPER(10000 ),
.FREQ_WORD_STEP (1024 )
)u_freq_comp
(
.clk (clk ),
.rst (rst ),
.freq_comp_start (freq_comp_start ),
.freq_comp_busy (freq_comp_busy ),
.rx_data_valid (~rst ),
.rx_ch1_i (tx_data_i ),
.rx_ch1_q (tx_data_q ),
.rx_ch2_i (tx_data_q ),
.rx_ch2_q (tx_data_i ),
.rx_ch3_i (tx_data_i ),
.rx_ch3_q (tx_data_i ),
.rx_ch4_i (tx_data_q ),
.rx_ch4_q (tx_data_q ),
.dmf_num_per_ch (2 ),
.freq_manual (327680 ),
.freq_manual_en (1'b0 ),
.freq_target (freq_target ),
.freq_target_valid (freq_target_valid )
);
endmodule
projects/dl814_k7/dl814_k7_online_acq/testbenches/tb_phase_compensation.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04/25/2023 04:04:33 PM
// Design Name:
// Module Name: tb_phase_compensation
// Project Name:
// Target Devices:
// Tool Versions:
// Description: testbench for [phase_compensation]
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_phase_compensation;
localparam DATA_WIDTH = 20;
localparam PHASE_WIDTH = 16;
localparam CHANNEL_NUM = 4;
reg clk = 1'b1;
reg rst = 1'b1;
reg din_valid = 1'b0;
wire dout_valid;
reg [DATA_WIDTH-1 : 0] din_ch1_i = 'b0;
reg [DATA_WIDTH-1 : 0] din_ch1_q = 'b0;
reg [DATA_WIDTH-1 : 0] din_ch2_i = 'b0;
reg [DATA_WIDTH-1 : 0] din_ch2_q = 'b0;
reg [DATA_WIDTH-1 : 0] din_ch3_i = 'b0;
reg [DATA_WIDTH-1 : 0] din_ch3_q = 'b0;
reg [DATA_WIDTH-1 : 0] din_ch4_i = 'b0;
reg [DATA_WIDTH-1 : 0] din_ch4_q = 'b0;
reg [PHASE_WIDTH-1 : 0] din_phase_ch1 = 'b0;
reg [PHASE_WIDTH-1 : 0] din_phase_ch2 = 'b0;
reg [PHASE_WIDTH-1 : 0] din_phase_ch3 = 'b0;
reg [PHASE_WIDTH-1 : 0] din_phase_ch4 = 'b0;
wire [DATA_WIDTH-1 : 0] dout_ch1_i;
wire [DATA_WIDTH-1 : 0] dout_ch1_q;
wire [DATA_WIDTH-1 : 0] dout_ch2_i;
wire [DATA_WIDTH-1 : 0] dout_ch2_q;
wire [DATA_WIDTH-1 : 0] dout_ch3_i;
wire [DATA_WIDTH-1 : 0] dout_ch3_q;
wire [DATA_WIDTH-1 : 0] dout_ch4_i;
wire [DATA_WIDTH-1 : 0] dout_ch4_q;
// initial
initial begin
#102;
rst = 1'b0;
#100;
din_valid = 1'b1;
din_ch1_i = 20'd107;
din_ch1_q = 20'd222;
din_ch2_i = -20'd253;
din_ch2_q = 20'd812;
din_ch3_i = 20'd752;
din_ch3_q = -20'd563;
din_ch4_i = -20'd785;
din_ch4_q = -20'd1024;
din_phase_ch1 = 16'b001_00000_00000_000; // $+\pi$
din_phase_ch2 = 16'b000_10000_00000_000; // $+\pi/2$
din_phase_ch3 = 16'b111_00000_00000_000; // $-\pi$
din_phase_ch4 = 16'b111_10000_00000_000; // $-\pi/2$
#20
din_valid = 1'b0;
#100;
din_valid = 1'b1;
din_ch4_i = 20'd107;
din_ch4_q = 20'd222;
din_ch3_i = -20'd253;
din_ch3_q = 20'd812;
din_ch2_i = 20'd752;
din_ch2_q = -20'd563;
din_ch1_i = -20'd785;
din_ch1_q = -20'd1024;
din_phase_ch1 = 16'b000_01000_00000_000; // $+\pi/4$
din_phase_ch2 = 16'b000_00100_00000_000; // $+\pi/8$
din_phase_ch3 = 16'b111_11000_00000_000; // $-\pi/4$
din_phase_ch4 = 16'b111_11100_00000_000; // $-\pi/8$
#20
din_valid = 1'b0;
end
always #10 clk = ~clk;
// module & port
wire [CHANNEL_NUM*DATA_WIDTH - 1 : 0] din_data_real;
wire [CHANNEL_NUM*DATA_WIDTH - 1 : 0] din_data_imag;
wire [CHANNEL_NUM*DATA_WIDTH - 1 : 0] dout_data_real;
wire [CHANNEL_NUM*DATA_WIDTH - 1 : 0] dout_data_imag;
wire [CHANNEL_NUM*PHASE_WIDTH-1 : 0] din_phase;
assign din_data_real = {din_ch4_i, din_ch3_i, din_ch2_i, din_ch1_i};
assign din_data_imag = {din_ch4_q, din_ch3_q, din_ch2_q, din_ch1_q};
assign din_phase = {din_phase_ch4, din_phase_ch3, din_phase_ch2, din_phase_ch1};
assign {dout_ch4_i, dout_ch3_i, dout_ch2_i, dout_ch1_i} = dout_data_real;
assign {dout_ch4_q, dout_ch3_q, dout_ch2_q, dout_ch1_q} = dout_data_imag;
phase_compensation #(
.DATA_WIDTH (DATA_WIDTH ),
.PHASE_WIDTH (PHASE_WIDTH ),
.CHANNEL_NUM (CHANNEL_NUM )
) u_phase_compensation
(
// clock & reset
.clk (clk ),
.rst (rst ),
// input data
.din_valid (din_valid ),
.din_data_real (din_data_real ),
.din_data_imag (din_data_imag ),
.din_phase (din_phase ),
// output data
.dout_valid (dout_valid ),
.dout_data_real (dout_data_real ),
.dout_data_imag (dout_data_imag )
);
endmodule
projects/dl814_k7/dl814_k7_online_acq/testbenches/tb_rx_dmf.v
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@@ -22,18 +22,48 @@
module tb_rx_dmf;
// length of pseudorandom bit sequence, need to be a power of 2
localparam PRBS_LEN = 128;
// interpolation of input signal, need to be a power of 2
localparam INTERP_RATE = 8;
// signal processing interpolation, need to be a power of 2
localparam PROCESS_INTERP = 4;
localparam PRBS_LEN_INTERP = PRBS_LEN*PROCESS_INTERP;
// number of accumulated symbols, need to be a power of 2
localparam ACC_SYM_NUM = 4;
localparam DATA_I_WIDTH = 12;
localparam DATA_O_WIDTH = 18;
reg clk = 1'b1;
reg rst = 1'b1;
reg dmf_start = 'b0;
wire [11:0] tx_data_i, tx_data_q;
wire dout_valid;
wire [18 : 0] dout_real;
wire [18 : 0] dout_imag;
wire peak_valid ;
wire [DATA_O_WIDTH-1 : 0] peak_value_abs ;
wire [DATA_O_WIDTH-1 : 0] peak_value_i ;
wire [DATA_O_WIDTH-1 : 0] peak_value_q ;
wire [$clog2(PRBS_LEN_INTERP)-1 : 0] peak_index ;
initial begin
#102;
rst = 1'b0;
#1000;
dmf_start = ~dmf_start;
wait (peak_valid == 1);
#1000;
dmf_start = ~dmf_start;
wait (peak_valid == 1);
#1000;
dmf_start = ~dmf_start;
wait (peak_valid == 1);
#1000;
dmf_start = ~dmf_start;
end
always #10 clk = ~clk;
@@ -54,24 +84,24 @@ tx_qpsk u_tx_qpsk
);
rx_dmf #(
.CHANNEL_NUM (1 )
)u_rx_dmf
.ACC_SYM_NUM (ACC_SYM_NUM )
) u_rx_dmf
(
.clk (clk ),
.rst (rst ),
.dmf_start (dmf_start ),
.dmf_busy (dmf_busy ),
.din_valid (~rst ),
.din_real (tx_data_i ),
.din_imag (tx_data_q ),
.din_imag (tx_data_i ),
.dout_valid (dout_valid ),
.dout_real (dout_real ),
.dout_imag (dout_imag ),
.peak_index (),
.peak_value_i (),
.peak_value_q (),
.peak_valid ()
.peak_valid (peak_valid ),
.peak_value_abs (peak_value_abs ),
.peak_value_i (peak_value_i ),
.peak_value_q (peak_value_q ),
.peak_index (peak_index )
);
endmodule
projects/dl814_k7/dl814_k7_online_acq/testbenches/tb_rx_pre.m
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%%%%%%%%%%%%%%%%%%%%%%%%%%
%本仿真基于以下环境，64元矩形方阵，每若干个阵元通过TR通道和合路器，合成一路子阵信号，然后AD采样进入阵列信号处理单元；
% - 子阵分割均匀，（16，16，16，16），共有4个子阵
% - 1个已知方向的期望来波，3个未知方向的干扰信号；
% - 信干比60dB；
%θ表示俯仰角（来波与Z轴正向夹角）；φ表示方位角（来波在XOY平面投影与X轴正向夹角）；X轴与阵列每列平行，Y轴与阵列每行平行
%通过空域滤波得到抑制干扰后的信号
%%%%%%%%%%%%%%%%%%%%%%%%
clc;
clear all;
Tt=256;%快拍数，用于阵列信号处理的采样点数
Tmax = 32768;
t=1:Tmax;
%%%%%%%%%此处假设来波均为单频信号，可按自身定义修改
f1=0.1*pi;
f2=0.2*pi;
f3=0.3*pi;
f4=0.4*pi;
%% 通信基带信号
%% 窄带白噪声干扰信号
filter_name = 'lpf_fs100_fpass5_fstop6.mat';
%%
snr=0;%信噪比可根据应用场景确定
sjr=(60+snr);%干信比
s1=sqrt(2*10^(snr/10))*exp(1i*f1*t);
s2=sqrt(2*10^(sjr/10))*exp(1i*f2*t);
s3=sqrt(2*10^(sjr/10))*exp(1i*f3*t);
s4=sqrt(2*10^(sjr/10))*exp(1i*f4*t);
%%%%%%%由信噪比和干信比计算出信号的幅度
lamuda=1;%当前载频的波长，可根据载频输入实际值d
d=0.5;%阵元间距，需小于最高工作频率半波长，可根据实际情况输入实际值
theta1=20;%期望来波俯仰角
phi1=30;%期望来波方位角
theta2=-20;%干扰1俯仰角
phi2=50;%干扰1方位角
theta3=-40;%干扰2俯仰角
phi3=80;%干扰2方位角
theta4=-60;%干扰3俯仰角
phi4=120;%干扰3方位角
%%%%%%%%
m=8;%列
n=8;%行
L=m*n;
a1=exp(1i*2*pi*d/lamuda*(-(m/2-1/2):1:(m/2-1/2)).'*sin(theta1/180*pi)*sin(phi1/180*pi));
b1=exp(1i*2*pi*d/lamuda*(-(n/2-1/2):1:(n/2-1/2)).'*sin(theta1/180*pi)*cos(phi1/180*pi));
A1=kron(b1,a1);
a2=exp(1i*2*pi*d/lamuda*(-(m/2-1/2):1:(m/2-1/2)).'*sin(theta2/180*pi)*sin(phi2/180*pi));
b2=exp(1i*2*pi*d/lamuda*(-(n/2-1/2):1:(n/2-1/2)).'*sin(theta2/180*pi)*cos(phi2/180*pi));
A2=kron(b2,a2);
a3=exp(1i*2*pi*d/lamuda*(-(m/2-1/2):1:(m/2-1/2)).'*sin(theta3/180*pi)*sin(phi3/180*pi));
b3=exp(1i*2*pi*d/lamuda*(-(n/2-1/2):1:(n/2-1/2)).'*sin(theta3/180*pi)*cos(phi3/180*pi));
A3=kron(b3,a3);
a4=exp(1i*2*pi*d/lamuda*(-(m/2-1/2):1:(m/2-1/2)).'*sin(theta4/180*pi)*sin(phi4/180*pi));
b4=exp(1i*2*pi*d/lamuda*(-(n/2-1/2):1:(n/2-1/2)).'*sin(theta4/180*pi)*cos(phi4/180*pi));
A4=kron(b4,a4);
As=[A1,A2,A3,A4];%阵列流型
rng(0);
x=As*[s1;s2;s3;s4]+randn(L,Tmax);
%%%%%%%%%%%%%%%4元子阵
%
N1=4;
C1=zeros(N1,64);
D1=zeros(N1,64);
for kk=0:3
C1(1,(kk*8+1):(kk*8+4))=ones(1,4);
C1(2,(kk*8+5):(kk*8+8))=ones(1,4);
C1(3,(kk*8+33):(kk*8+36))=ones(1,4);
C1(4,(kk*8+37):(kk*8+40))=ones(1,4);
end
%}
%%%%%%%%%%%%%%%%%%%%%%
D1=C1*diag(A1');%4元 阵元通道移相后，每16路合路为一个子阵
% D2=C2*diag(A1');%6元 阵元通道移相后，每(16,8)路合路为一个子阵
% D3=C3*diag(A1');%8元 阵元通道移相后，每8路合路为一个子阵
% %%%%%%%%%%%%%%%%%
xs1=D1*x(:,1:Tt);
Rx1=xs1*xs1';%4元子阵协方差矩阵
Ax1=D1*A1;%期望来波方向的子阵导向矢量
wx1=inv(Rx1)*Ax1/(Ax1'*inv(Rx1)*Ax1);%4子阵的LCMV权值
xs1_long = D1*x;
s_new1=wx1'*xs1_long;%4子阵情况下的空域滤波后的信号
% s_new1=[1,1,1,1]*xs1;
%% 数据导出
xs1_long_12b = round(xs1_long/max(max(abs(xs1_long)))*(2^11-1));
xs1_real_12b = real(xs1_long_12b);
xs1_imag_12b = imag(xs1_long_12b);
% writematrix(xs1_real_12b,'./xs1_real.csv');
% writematrix(xs1_imag_12b,'./xs1_imag.csv');
tb_snap = xs1_long_12b(:,(0:255)+54);
tb_acorr = tb_snap*tb_snap';
wx1_32b = round(wx1/max(abs(wx1))*(2^31-1));
wx1_16b = floor(wx1_32b/2^16);
s_new1_30b = wx1_16b'*xs1_long_12b;
s_new1_12b = s_new1_30b/2^18;
projects/dl814_k7/dl814_k7_online_acq/testbenches/tb_rx_pre_test.v
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@@ -1,255 +0,0 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
// _ _ ____
// | | ___ ___| |__ / ___| __ _ ___
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
// \___/ \___/|___/_| |_| \____|\__,_|\___/
//
// Create Date: 2022/11/16 15:58:28
// Design Name:
// Module Name: tb_rx_pre_test
// Project Name:
// Target Devices:
// Tool Versions:
// Description: Co-simulation testbench for [rx_pre_process] and [rx_pre_test]
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_rx_pre_test;
localparam COL_NUM = 4;
localparam PS_PL_WIDTH = 32;
localparam FRAME_HEAD = 32'h7E7E7E7E;
localparam FRAME_BITS = (2+COL_NUM*2)*PS_PL_WIDTH;
reg [FRAME_BITS-1 : 0] weight_stream_buf =
{
FRAME_HEAD, 32'd40,
-32'd1145474114, 32'd1816473250,
32'd2059208152, -32'd254581925 ,
32'd2062565030, 32'd244279278 ,
-32'd1154406364, -32'd1806170603
};
reg sys_clk = 1'b1;
reg sys_clk_2x = 1'b1;
reg sys_clk_4x = 1'b1;
reg sys_rst = 1'b1;
wire clk_96m;
wire ant_rst;
reg ad9361_1_cal_start = 'b0;
wire ad9361_1_cal_done ;
reg ad9361_2_cal_start = 'b0;
wire ad9361_2_cal_done ;
wire ad9361_cal_result ;
wire ad9361_cal_valid ;
reg ad9361_recal = 'b0;
// phase difference of 0 degree
reg [11:0] rx_ch1_i = 0, rx_ch1_q = 0;
reg [11:0] rx_ch2_i = 0, rx_ch2_q = 0;
reg [11:0] rx_ch3_i = 0, rx_ch3_q = 0;
reg [11:0] rx_ch4_i = 0, rx_ch4_q = 0;
wire [11:0] rx_ch1_i_test, rx_ch1_q_test;
wire [11:0] rx_ch2_i_test, rx_ch2_q_test;
wire [11:0] rx_ch3_i_test, rx_ch3_q_test;
wire [11:0] rx_ch4_i_test, rx_ch4_q_test;
reg [11:0] rx_ch1_i_cal = 12'd2047;
reg [11:0] rx_ch1_q_cal = 12'd2047;
reg [11:0] rx_ch2_i_cal = -12'd2047;
reg [11:0] rx_ch2_q_cal = -12'd2047;
reg [11:0] rx_ch3_q_cal = 12'd2047;
reg [11:0] rx_ch3_i_cal = 12'd2047;
reg [11:0] rx_ch4_i_cal = -12'd2047;
reg [11:0] rx_ch4_q_cal = -12'd2047;
wire hop_start_flag;
wire accor_stream_valid;
wire accor_stream_data;
wire weight_stream_data;
wire rx_data_valid;
wire [29:0] rx_data_i, rx_data_q;
reg hop_trigger = 1'b0;
////////////////////////////////////////////////////////////////////////////////
/////////////////////////////// Clock Generation ///////////////////////////////
////////////////////////////////////////////////////////////////////////////////
always #5 sys_clk_4x = ~sys_clk_4x;
always @(posedge sys_clk_4x) begin
sys_clk_2x <= ~sys_clk_2x;
end
always @(posedge sys_clk_2x) begin
sys_clk <= ~sys_clk;
end
assign #3 clk_96m = sys_clk_2x;
assign #3 ant_rst = sys_rst;
////////////////////////////////////////////////////////////////////////////////
///////////////////////////// Stimulus Generation //////////////////////////////
////////////////////////////////////////////////////////////////////////////////
initial begin
#102
sys_rst = 1'b0;
#100
ad9361_1_cal_start = 1'b1;
wait(ad9361_cal_valid);
#1000
hop_trigger = 1'b1;
#100
hop_trigger = 1'b0;
#(19600*40-100) // after a long time, trig again
hop_trigger = 1'b1;
#100
hop_trigger = 1'b0;
end
always @(posedge sys_clk) begin
if (ad9361_1_cal_done) begin
ad9361_2_cal_start <= 1'b1;
end
else begin
ad9361_2_cal_start <= 1'b0;
end
end
always @(posedge sys_clk) begin
if (ad9361_cal_valid) begin
rx_ch1_i <= rx_ch1_i_test;
rx_ch1_q <= rx_ch1_q_test;
rx_ch2_i <= rx_ch2_i_test;
rx_ch2_q <= rx_ch2_q_test;
rx_ch3_i <= rx_ch3_i_test;
rx_ch3_q <= rx_ch3_q_test;
rx_ch4_i <= rx_ch4_i_test;
rx_ch4_q <= rx_ch4_q_test;
end
else begin
rx_ch1_i <= rx_ch1_i_cal;
rx_ch1_q <= rx_ch1_q_cal;
rx_ch2_i <= rx_ch2_i_cal;
rx_ch2_q <= rx_ch2_q_cal;
rx_ch3_i <= rx_ch3_i_cal;
rx_ch3_q <= rx_ch3_q_cal;
rx_ch4_i <= rx_ch4_i_cal;
rx_ch4_q <= rx_ch4_q_cal;
end
end
// 校准数据
always @(posedge sys_clk) begin
rx_ch1_i_cal = ~rx_ch1_i_cal;
rx_ch1_q_cal = ~rx_ch1_q_cal;
rx_ch2_i_cal = ~rx_ch2_i_cal;
rx_ch2_q_cal = ~rx_ch2_q_cal;
rx_ch3_i_cal = ~rx_ch3_i_cal;
rx_ch3_q_cal = ~rx_ch3_q_cal;
rx_ch4_i_cal = ~rx_ch4_i_cal;
rx_ch4_q_cal = ~rx_ch4_q_cal;
end
reg weight_stream_valid = 'b0;
always @(negedge accor_stream_valid) begin
#((48*50)*40+18); // 50us of 48M clock
weight_stream_valid = 'b1;
#(FRAME_BITS*20);
weight_stream_valid = 'b0;
end
reg [$clog2(FRAME_BITS)-1 : 0] weight_stream_cnt;
always @(posedge clk_96m) begin
if (sys_rst) begin
weight_stream_cnt <= 'b0;
end
else begin
weight_stream_cnt <= (weight_stream_valid & ~(weight_stream_cnt == FRAME_BITS - 1)) ? weight_stream_cnt + 1'b1 : 'b0;
end
end
assign weight_stream_data = weight_stream_buf[FRAME_BITS-1-weight_stream_cnt];
////////////////////////////////////////////////////////////////////////////////
/////////////////////// Simulation Module Instantiation ////////////////////////
////////////////////////////////////////////////////////////////////////////////
rx_pre_process #(
.OUTPUT_DATA_WIDTH (30 )
) u_rx_pre_process
(
// clock & reset
.sys_clk (sys_clk ), // sync to adc data
.sys_clk_4x (sys_clk_4x ), // sync to physical layer
.sys_rst (sys_rst ), // sync to [sys_clk]
.clk_96m (clk_96m ), // sync to c2c data
.ant_rst (ant_rst ), // sync to [clk_96m]
// input data interface
.rx_ch1_i (rx_ch1_i ),
.rx_ch1_q (rx_ch1_q ),
.rx_ch2_i (rx_ch2_i ),
.rx_ch2_q (rx_ch2_q ),
.rx_ch3_i (rx_ch3_i ),
.rx_ch3_q (rx_ch3_q ),
.rx_ch4_i (rx_ch4_i ),
.rx_ch4_q (rx_ch4_q ),
// ad9361 calibration interface
.ad9361_1_cal_start (ad9361_1_cal_start ),
.ad9361_1_cal_done (ad9361_1_cal_done ),
.ad9361_2_cal_start (ad9361_2_cal_start ),
.ad9361_2_cal_done (ad9361_2_cal_done ),
.ad9361_cal_result (ad9361_cal_result ),
.ad9361_cal_valid (ad9361_cal_valid ),
.ad9361_recal (ad9361_recal ),
// nulling algotithm interface
.hop_start_flag (hop_start_flag ), // sync to [sys_clk_4x]
.accor_stream_valid (accor_stream_valid ), // sync to [clk_96m]
.accor_stream_data (accor_stream_data ), // sync to [clk_96m]
.weight_stream_data (weight_stream_data ), // sync to [clk_96m]
.rx_data_valid (rx_data_valid ), // sync to [sys_clk]
.rx_data_i (rx_data_i ), // sync to [sys_clk]
.rx_data_q (rx_data_q ) // sync to [sys_clk]
);
// temporary test cases
rx_pre_test u_rx_pre_test
(
// clock & reset
.sys_clk (sys_clk ),
.sys_rst (sys_rst ),
.sys_clk_4x (sys_clk_4x ),
.hop_trigger (hop_trigger ),
.hop_trigger_en (1'b1 ),
// calc result
.ad9361_cal_result (ad9361_cal_result ),
.ad9361_cal_valid (ad9361_cal_valid ),
// output test data
.rx_ch1_i (rx_ch1_i_test ),
.rx_ch1_q (rx_ch1_q_test ),
.rx_ch2_i (rx_ch2_i_test ),
.rx_ch2_q (rx_ch2_q_test ),
.rx_ch3_i (rx_ch3_i_test ),
.rx_ch3_q (rx_ch3_q_test ),
.rx_ch4_i (rx_ch4_i_test ),
.rx_ch4_q (rx_ch4_q_test ),
.hop_start_flag (hop_start_flag )
);
endmodule
projects/dl814_k7/dl814_k7_online_acq/testbenches/tb_rx_test.m
-117
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@@ -1,117 +0,0 @@
%%%%%%%%%%%%%%%%%%%%%%%%%%
%本仿真基于以下环境，64元矩形方阵，每若干个阵元通过TR通道和合路器，合成一路子阵信号，然后AD采样进入阵列信号处理单元；
% - 子阵分割均匀，（16，16，16，16），共有4个子阵
% - 1个已知方向的期望来波，3个未知方向的干扰信号；
% - 信干比60dB；
%θ表示俯仰角（来波与Z轴正向夹角）；φ表示方位角（来波在XOY平面投影与X轴正向夹角）；X轴与阵列每列平行，Y轴与阵列每行平行
%通过空域滤波得到抑制干扰后的信号
%%%%%%%%%%%%%%%%%%%%%%%%
clc;
clear all;
Tt=256;%快拍数，用于阵列信号处理的采样点数
Tmax = 32768;
t=1:Tmax;
%%%%%%%%%此处假设来波均为单频信号，可按自身定义修改
f1=0.1*pi;
f2=0.2*pi;
f3=0.3*pi;
f4=0.4*pi;
%% 通信基带信号
%% 窄带白噪声干扰信号
filter_name = 'lpf_fs100_fpass5_fstop6.mat';
%%
snr=0;%信噪比可根据应用场景确定
sjr=(60+snr);%干信比
s1=sqrt(2*10^(snr/10))*exp(1i*f1*t);
s2=sqrt(2*10^(sjr/10))*exp(1i*f2*t);
s3=sqrt(2*10^(sjr/10))*exp(1i*f3*t);
s4=sqrt(2*10^(sjr/10))*exp(1i*f4*t);
%%%%%%%由信噪比和干信比计算出信号的幅度
lamuda=1;%当前载频的波长，可根据载频输入实际值d
d=0.5;%阵元间距，需小于最高工作频率半波长，可根据实际情况输入实际值
theta1=20;%期望来波俯仰角
phi1=30;%期望来波方位角
theta2=-20;%干扰1俯仰角
phi2=50;%干扰1方位角
theta3=-40;%干扰2俯仰角
phi3=80;%干扰2方位角
theta4=-60;%干扰3俯仰角
phi4=120;%干扰3方位角
%%%%%%%%
m=8;%列
n=8;%行
L=m*n;
a1=exp(1i*2*pi*d/lamuda*(-(m/2-1/2):1:(m/2-1/2)).'*sin(theta1/180*pi)*sin(phi1/180*pi));
b1=exp(1i*2*pi*d/lamuda*(-(n/2-1/2):1:(n/2-1/2)).'*sin(theta1/180*pi)*cos(phi1/180*pi));
A1=kron(b1,a1);
a2=exp(1i*2*pi*d/lamuda*(-(m/2-1/2):1:(m/2-1/2)).'*sin(theta2/180*pi)*sin(phi2/180*pi));
b2=exp(1i*2*pi*d/lamuda*(-(n/2-1/2):1:(n/2-1/2)).'*sin(theta2/180*pi)*cos(phi2/180*pi));
A2=kron(b2,a2);
a3=exp(1i*2*pi*d/lamuda*(-(m/2-1/2):1:(m/2-1/2)).'*sin(theta3/180*pi)*sin(phi3/180*pi));
b3=exp(1i*2*pi*d/lamuda*(-(n/2-1/2):1:(n/2-1/2)).'*sin(theta3/180*pi)*cos(phi3/180*pi));
A3=kron(b3,a3);
a4=exp(1i*2*pi*d/lamuda*(-(m/2-1/2):1:(m/2-1/2)).'*sin(theta4/180*pi)*sin(phi4/180*pi));
b4=exp(1i*2*pi*d/lamuda*(-(n/2-1/2):1:(n/2-1/2)).'*sin(theta4/180*pi)*cos(phi4/180*pi));
A4=kron(b4,a4);
As=[A1,A2,A3,A4];%阵列流型
rng(0);
x=As*[s1;s2;s3;s4]+randn(L,Tmax);
%%%%%%%%%%%%%%%4元子阵
%
N1=4;
C1=zeros(N1,64);
D1=zeros(N1,64);
for kk=0:3
C1(1,(kk*8+1):(kk*8+4))=ones(1,4);
C1(2,(kk*8+5):(kk*8+8))=ones(1,4);
C1(3,(kk*8+33):(kk*8+36))=ones(1,4);
C1(4,(kk*8+37):(kk*8+40))=ones(1,4);
end
%}
%%%%%%%%%%%%%%%%%%%%%%
D1=C1*diag(A1');%4元 阵元通道移相后，每16路合路为一个子阵
% D2=C2*diag(A1');%6元 阵元通道移相后，每(16,8)路合路为一个子阵
% D3=C3*diag(A1');%8元 阵元通道移相后，每8路合路为一个子阵
% %%%%%%%%%%%%%%%%%
xs1=D1*x(:,1:Tt);
Rx1=xs1*xs1';%4元子阵协方差矩阵
Ax1=D1*A1;%期望来波方向的子阵导向矢量
wx1=inv(Rx1)*Ax1/(Ax1'*inv(Rx1)*Ax1);%4子阵的LCMV权值
xs1_long = D1*x;
s_new1=wx1'*xs1_long;%4子阵情况下的空域滤波后的信号
% s_new1=[1,1,1,1]*xs1;
%% 数据导出
xs1_long_12b = round(xs1_long/max(max(abs(xs1_long)))*(2^11-1));
xs1_real_12b = real(xs1_long_12b);
xs1_imag_12b = imag(xs1_long_12b);
xs1_12b_bin_join = strings(9600,96);
for i = 1:9600
xs1_real_12b_bin = dec2bin(xs1_real_12b(:,i),16);
xs1_real_12b_bin_join_tmp = '';
xs1_imag_12b_bin = dec2bin(xs1_imag_12b(:,i),16);
xs1_imag_12b_bin_join_tmp = '';
for j = 1:4
xs1_real_12b_bin_trunc = xs1_real_12b_bin(j,5:16);
xs1_real_12b_bin_join_tmp = [xs1_real_12b_bin_join_tmp,xs1_real_12b_bin_trunc];
xs1_imag_12b_bin_trunc = xs1_imag_12b_bin(j,5:16);
xs1_imag_12b_bin_join_tmp = [xs1_imag_12b_bin_join_tmp,xs1_imag_12b_bin_trunc];
end
xs1_12b_bin_join(i) = [xs1_real_12b_bin_join_tmp,xs1_imag_12b_bin_join_tmp];
end
coe