Archived
finish coding and testing of online acq; add sample data
串行在线捕获程序已经完成编写,并进行了仿真和测试(对飞和814均可用);增加了在电子所使用转台测试的幅相采集数据
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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||||
// --------------------------------------------------------------------------------
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||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
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// Date : Mon May 8 13:18:11 2023
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// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
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// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
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// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_8x12x8192_stub.v
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// Design : ila_8x12x8192
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// Purpose : Stub declaration of top-level module interface
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// Device : xc7z100ffg900-2
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// --------------------------------------------------------------------------------
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// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
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// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
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// Please paste the declaration into a Verilog source file or add the file as an additional source.
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(* X_CORE_INFO = "ila,Vivado 2019.1.3" *)
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module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
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probe6, probe7)
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/* synthesis syn_black_box black_box_pad_pin="clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0]" */;
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input clk;
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input [11:0]probe0;
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input [11:0]probe1;
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input [11:0]probe2;
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input [11:0]probe3;
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input [11:0]probe4;
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input [11:0]probe5;
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input [11:0]probe6;
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input [11:0]probe7;
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endmodule
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+38
@@ -0,0 +1,38 @@
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-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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||||
-- --------------------------------------------------------------------------------
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||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
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-- Date : Mon May 8 13:18:11 2023
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-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
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-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
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-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_8x12x8192_stub.vhdl
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-- Design : ila_8x12x8192
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-- Purpose : Stub declaration of top-level module interface
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-- Device : xc7z100ffg900-2
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-- --------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
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Port (
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clk : in STD_LOGIC;
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probe0 : in STD_LOGIC_VECTOR ( 11 downto 0 );
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probe1 : in STD_LOGIC_VECTOR ( 11 downto 0 );
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probe2 : in STD_LOGIC_VECTOR ( 11 downto 0 );
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probe3 : in STD_LOGIC_VECTOR ( 11 downto 0 );
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probe4 : in STD_LOGIC_VECTOR ( 11 downto 0 );
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probe5 : in STD_LOGIC_VECTOR ( 11 downto 0 );
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probe6 : in STD_LOGIC_VECTOR ( 11 downto 0 );
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probe7 : in STD_LOGIC_VECTOR ( 11 downto 0 )
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);
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end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
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architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
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attribute syn_black_box : boolean;
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attribute black_box_pad_pin : string;
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attribute syn_black_box of stub : architecture is true;
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attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0]";
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attribute X_CORE_INFO : string;
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attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3";
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begin
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end;
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+9
-6
@@ -1,9 +1,11 @@
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version:1
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||||
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||||
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||||
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||||
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||||
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@@ -13,9 +15,10 @@ version:1
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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eof:529630187
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+5
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version:1
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||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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eof:2037959492
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||||
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||||
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||||
+1
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||||
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||||
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||||
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||||
eof:
|
||||
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||||
+5
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||||
version:1
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
+15
-9
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||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pa" timeStamp="Thu Apr 13 11:49:59 2023">
|
||||
<application name="pa" timeStamp="Mon May 8 13:23:37 2023">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="6592d23f40de4658b2271ad58dea1e34" type="ProjectID"/>
|
||||
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
|
||||
@@ -19,16 +19,21 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<item name="Java Command Handlers">
|
||||
<property name="AddExistingIPHandler" value="1" type="JavaHandler"/>
|
||||
<property name="CloseProject" value="1" type="JavaHandler"/>
|
||||
<property name="CopyIPHandler" value="1" type="JavaHandler"/>
|
||||
<property name="NewIPLocationHandler" value="1" type="JavaHandler"/>
|
||||
<property name="RecustomizeCore" value="3" type="JavaHandler"/>
|
||||
<property name="OpenIPLocationHandler" value="1" type="JavaHandler"/>
|
||||
<property name="OpenProject" value="1" type="JavaHandler"/>
|
||||
<property name="RecustomizeCore" value="4" type="JavaHandler"/>
|
||||
<property name="UpgradeIP" value="1" type="JavaHandler"/>
|
||||
</item>
|
||||
<item name="Gui Handlers">
|
||||
<property name="BaseDialog_OK" value="3" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_OK" value="5" type="GuiHandlerData"/>
|
||||
<property name="CmdMsgDialog_OK" value="1" type="GuiHandlerData"/>
|
||||
<property name="CopyIPHandler_DESTINATION_IP_NAME" value="1" type="GuiHandlerData"/>
|
||||
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="2" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="19" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_MANAGE_IP" value="1" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="34" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_MANAGE_IP" value="2" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_OPEN_PROJECT" value="1" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_EXPORT" value="1" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_FILE" value="2" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_IP" value="2" type="GuiHandlerData"/>
|
||||
@@ -38,16 +43,17 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="NewIPProjectWizard_IP_LOCATION" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_ADD_EXISTING_IP" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_CLOSE_PROJECT" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_OPEN_IP_LOCATION" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_COPY_IP" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_OPEN_IP_LOCATION" value="2" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_UPGRADE_IP" value="1" type="GuiHandlerData"/>
|
||||
<property name="ProgressDialog_BACKGROUND" value="1" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="1" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="2" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_ADD_CONFIGURABLE_IP_FILES" value="3" type="GuiHandlerData"/>
|
||||
</item>
|
||||
<item name="Other">
|
||||
<property name="GuiMode" value="90" type="GuiMode"/>
|
||||
<property name="GuiMode" value="117" type="GuiMode"/>
|
||||
<property name="BatchMode" value="0" type="BatchMode"/>
|
||||
<property name="TclMode" value="63" type="TclMode"/>
|
||||
<property name="TclMode" value="82" type="TclMode"/>
|
||||
</item>
|
||||
</section>
|
||||
</application>
|
||||
|
||||
+8
@@ -0,0 +1,8 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="ila_8x12x8192_synth_1" LaunchDir="/home/josh/Workspace/vivado-git/projects/duifei/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12x8192_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
+6
-11
@@ -1,14 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="ad9361_clk_gen_cmos_1t1r_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1681355353">
|
||||
<File Type="VDS-TIMING-PB" Name="ad9361_clk_gen_cmos_1t1r_timing_summary_synth.pb"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="ad9361_clk_gen_cmos_1t1r_timing_summary_synth.rpt"/>
|
||||
<File Type="RDS-DCP" Name="ad9361_clk_gen_cmos_1t1r.dcp"/>
|
||||
<File Type="REPORTS-TCL" Name="ad9361_clk_gen_cmos_1t1r_reports.tcl"/>
|
||||
<File Type="PA-TCL" Name="ad9361_clk_gen_cmos_1t1r.tcl"/>
|
||||
<File Type="RDS-RDS" Name="ad9361_clk_gen_cmos_1t1r.vds"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="ad9361_clk_gen_cmos_1t1r_drc_synth.rpt"/>
|
||||
<File Type="RDS-UTIL" Name="ad9361_clk_gen_cmos_1t1r_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ad9361_clk_gen_cmos_1t1r_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="ad9361_clk_gen_cmos_1t1r_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="ad9361_clk_gen_cmos_1t1r.vds"/>
|
||||
<File Type="RDS-DCP" Name="ad9361_clk_gen_cmos_1t1r.dcp"/>
|
||||
<File Type="PA-TCL" Name="ad9361_clk_gen_cmos_1t1r.tcl"/>
|
||||
<File Type="REPORTS-TCL" Name="ad9361_clk_gen_cmos_1t1r_reports.tcl"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ad9361_clk_gen_cmos_1t1r">
|
||||
<File Path="$PPRDIR/../sys_clock_gen/ad9361_clk_gen_cmos_1t1r/ad9361_clk_gen_cmos_1t1r.xci">
|
||||
<FileInfo>
|
||||
@@ -56,9 +53,7 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
|
||||
+6
-11
@@ -1,14 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="ad9361_clk_gen_cmos_2t2r_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1681355353">
|
||||
<File Type="VDS-TIMING-PB" Name="ad9361_clk_gen_cmos_2t2r_timing_summary_synth.pb"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="ad9361_clk_gen_cmos_2t2r_timing_summary_synth.rpt"/>
|
||||
<File Type="RDS-DCP" Name="ad9361_clk_gen_cmos_2t2r.dcp"/>
|
||||
<File Type="REPORTS-TCL" Name="ad9361_clk_gen_cmos_2t2r_reports.tcl"/>
|
||||
<File Type="PA-TCL" Name="ad9361_clk_gen_cmos_2t2r.tcl"/>
|
||||
<File Type="RDS-RDS" Name="ad9361_clk_gen_cmos_2t2r.vds"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="ad9361_clk_gen_cmos_2t2r_drc_synth.rpt"/>
|
||||
<File Type="RDS-UTIL" Name="ad9361_clk_gen_cmos_2t2r_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ad9361_clk_gen_cmos_2t2r_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="ad9361_clk_gen_cmos_2t2r_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="ad9361_clk_gen_cmos_2t2r.vds"/>
|
||||
<File Type="RDS-DCP" Name="ad9361_clk_gen_cmos_2t2r.dcp"/>
|
||||
<File Type="PA-TCL" Name="ad9361_clk_gen_cmos_2t2r.tcl"/>
|
||||
<File Type="REPORTS-TCL" Name="ad9361_clk_gen_cmos_2t2r_reports.tcl"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ad9361_clk_gen_cmos_2t2r">
|
||||
<File Path="$PPRDIR/../sys_clock_gen/ad9361_clk_gen_cmos_2t2r/ad9361_clk_gen_cmos_2t2r.xci">
|
||||
<FileInfo>
|
||||
@@ -56,9 +53,7 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
|
||||
+6
-11
@@ -1,14 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="ad9361_clk_gen_lvds_2t2r_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1681355353">
|
||||
<File Type="VDS-TIMING-PB" Name="ad9361_clk_gen_lvds_2t2r_timing_summary_synth.pb"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="ad9361_clk_gen_lvds_2t2r_timing_summary_synth.rpt"/>
|
||||
<File Type="RDS-DCP" Name="ad9361_clk_gen_lvds_2t2r.dcp"/>
|
||||
<File Type="REPORTS-TCL" Name="ad9361_clk_gen_lvds_2t2r_reports.tcl"/>
|
||||
<File Type="PA-TCL" Name="ad9361_clk_gen_lvds_2t2r.tcl"/>
|
||||
<File Type="RDS-RDS" Name="ad9361_clk_gen_lvds_2t2r.vds"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="ad9361_clk_gen_lvds_2t2r_drc_synth.rpt"/>
|
||||
<File Type="RDS-UTIL" Name="ad9361_clk_gen_lvds_2t2r_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ad9361_clk_gen_lvds_2t2r_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="ad9361_clk_gen_lvds_2t2r_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="ad9361_clk_gen_lvds_2t2r.vds"/>
|
||||
<File Type="RDS-DCP" Name="ad9361_clk_gen_lvds_2t2r.dcp"/>
|
||||
<File Type="PA-TCL" Name="ad9361_clk_gen_lvds_2t2r.tcl"/>
|
||||
<File Type="REPORTS-TCL" Name="ad9361_clk_gen_lvds_2t2r_reports.tcl"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ad9361_clk_gen_lvds_2t2r">
|
||||
<File Path="$PPRDIR/../sys_clock_gen/ad9361_clk_gen_lvds_2t2r/ad9361_clk_gen_lvds_2t2r.xci">
|
||||
<FileInfo>
|
||||
@@ -56,9 +53,7 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
|
||||
+6
-11
@@ -1,14 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="ant_clk_gen_stg1_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1681355354">
|
||||
<File Type="VDS-TIMING-PB" Name="ant_clk_gen_stg1_timing_summary_synth.pb"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="ant_clk_gen_stg1_timing_summary_synth.rpt"/>
|
||||
<File Type="RDS-DCP" Name="ant_clk_gen_stg1.dcp"/>
|
||||
<File Type="REPORTS-TCL" Name="ant_clk_gen_stg1_reports.tcl"/>
|
||||
<File Type="PA-TCL" Name="ant_clk_gen_stg1.tcl"/>
|
||||
<File Type="RDS-RDS" Name="ant_clk_gen_stg1.vds"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="ant_clk_gen_stg1_drc_synth.rpt"/>
|
||||
<File Type="RDS-UTIL" Name="ant_clk_gen_stg1_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ant_clk_gen_stg1_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="ant_clk_gen_stg1_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="ant_clk_gen_stg1.vds"/>
|
||||
<File Type="RDS-DCP" Name="ant_clk_gen_stg1.dcp"/>
|
||||
<File Type="PA-TCL" Name="ant_clk_gen_stg1.tcl"/>
|
||||
<File Type="REPORTS-TCL" Name="ant_clk_gen_stg1_reports.tcl"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ant_clk_gen_stg1">
|
||||
<File Path="$PPRDIR/../sys_clock_gen/ant_clk_gen_stg1/ant_clk_gen_stg1.xci">
|
||||
<FileInfo>
|
||||
@@ -56,9 +53,7 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
|
||||
+6
-11
@@ -1,14 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="ant_clk_gen_stg2_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1681355354">
|
||||
<File Type="VDS-TIMING-PB" Name="ant_clk_gen_stg2_timing_summary_synth.pb"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="ant_clk_gen_stg2_timing_summary_synth.rpt"/>
|
||||
<File Type="RDS-DCP" Name="ant_clk_gen_stg2.dcp"/>
|
||||
<File Type="REPORTS-TCL" Name="ant_clk_gen_stg2_reports.tcl"/>
|
||||
<File Type="PA-TCL" Name="ant_clk_gen_stg2.tcl"/>
|
||||
<File Type="RDS-RDS" Name="ant_clk_gen_stg2.vds"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="ant_clk_gen_stg2_drc_synth.rpt"/>
|
||||
<File Type="RDS-UTIL" Name="ant_clk_gen_stg2_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ant_clk_gen_stg2_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="ant_clk_gen_stg2_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="ant_clk_gen_stg2.vds"/>
|
||||
<File Type="RDS-DCP" Name="ant_clk_gen_stg2.dcp"/>
|
||||
<File Type="PA-TCL" Name="ant_clk_gen_stg2.tcl"/>
|
||||
<File Type="REPORTS-TCL" Name="ant_clk_gen_stg2_reports.tcl"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ant_clk_gen_stg2">
|
||||
<File Path="$PPRDIR/../sys_clock_gen/ant_clk_gen_stg2/ant_clk_gen_stg2.xci">
|
||||
<FileInfo>
|
||||
@@ -56,9 +53,7 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
|
||||
+6
-11
@@ -1,14 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="ila_2x12x1024_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1681355354">
|
||||
<File Type="VDS-TIMING-PB" Name="ila_2x12x1024_timing_summary_synth.pb"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="ila_2x12x1024_timing_summary_synth.rpt"/>
|
||||
<File Type="RDS-DCP" Name="ila_2x12x1024.dcp"/>
|
||||
<File Type="REPORTS-TCL" Name="ila_2x12x1024_reports.tcl"/>
|
||||
<File Type="PA-TCL" Name="ila_2x12x1024.tcl"/>
|
||||
<File Type="RDS-RDS" Name="ila_2x12x1024.vds"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="ila_2x12x1024_drc_synth.rpt"/>
|
||||
<File Type="RDS-UTIL" Name="ila_2x12x1024_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ila_2x12x1024_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="ila_2x12x1024_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="ila_2x12x1024.vds"/>
|
||||
<File Type="RDS-DCP" Name="ila_2x12x1024.dcp"/>
|
||||
<File Type="PA-TCL" Name="ila_2x12x1024.tcl"/>
|
||||
<File Type="REPORTS-TCL" Name="ila_2x12x1024_reports.tcl"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_2x12x1024">
|
||||
<File Path="$PPRDIR/../basic_driver/ila_2x12x1024/ila_2x12x1024.xci">
|
||||
<FileInfo>
|
||||
@@ -56,9 +53,7 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
|
||||
+6
-11
@@ -1,14 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="ila_2x12x131072_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1681355354">
|
||||
<File Type="VDS-TIMING-PB" Name="ila_2x12x131072_timing_summary_synth.pb"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="ila_2x12x131072_timing_summary_synth.rpt"/>
|
||||
<File Type="RDS-DCP" Name="ila_2x12x131072.dcp"/>
|
||||
<File Type="REPORTS-TCL" Name="ila_2x12x131072_reports.tcl"/>
|
||||
<File Type="PA-TCL" Name="ila_2x12x131072.tcl"/>
|
||||
<File Type="RDS-RDS" Name="ila_2x12x131072.vds"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="ila_2x12x131072_drc_synth.rpt"/>
|
||||
<File Type="RDS-UTIL" Name="ila_2x12x131072_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ila_2x12x131072_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="ila_2x12x131072_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="ila_2x12x131072.vds"/>
|
||||
<File Type="RDS-DCP" Name="ila_2x12x131072.dcp"/>
|
||||
<File Type="PA-TCL" Name="ila_2x12x131072.tcl"/>
|
||||
<File Type="REPORTS-TCL" Name="ila_2x12x131072_reports.tcl"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_2x12x131072">
|
||||
<File Path="$PPRDIR/../basic_driver/ila_2x12x131072/ila_2x12x131072.xci">
|
||||
<FileInfo>
|
||||
@@ -56,9 +53,7 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
|
||||
+6
-11
@@ -1,14 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="ila_4x12x131072_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1681355354">
|
||||
<File Type="VDS-TIMING-PB" Name="ila_4x12x131072_timing_summary_synth.pb"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="ila_4x12x131072_timing_summary_synth.rpt"/>
|
||||
<File Type="RDS-DCP" Name="ila_4x12x131072.dcp"/>
|
||||
<File Type="REPORTS-TCL" Name="ila_4x12x131072_reports.tcl"/>
|
||||
<File Type="PA-TCL" Name="ila_4x12x131072.tcl"/>
|
||||
<File Type="RDS-RDS" Name="ila_4x12x131072.vds"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="ila_4x12x131072_drc_synth.rpt"/>
|
||||
<File Type="RDS-UTIL" Name="ila_4x12x131072_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ila_4x12x131072_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="ila_4x12x131072_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="ila_4x12x131072.vds"/>
|
||||
<File Type="RDS-DCP" Name="ila_4x12x131072.dcp"/>
|
||||
<File Type="PA-TCL" Name="ila_4x12x131072.tcl"/>
|
||||
<File Type="REPORTS-TCL" Name="ila_4x12x131072_reports.tcl"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_4x12x131072">
|
||||
<File Path="$PPRDIR/../basic_driver/ila_4x12x131072/ila_4x12x131072.xci">
|
||||
<FileInfo>
|
||||
@@ -56,9 +53,7 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
|
||||
+6
-11
@@ -1,14 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="ila_8x12x131072_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1681355354">
|
||||
<File Type="VDS-TIMING-PB" Name="ila_8x12x131072_timing_summary_synth.pb"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="ila_8x12x131072_timing_summary_synth.rpt"/>
|
||||
<File Type="RDS-DCP" Name="ila_8x12x131072.dcp"/>
|
||||
<File Type="REPORTS-TCL" Name="ila_8x12x131072_reports.tcl"/>
|
||||
<File Type="PA-TCL" Name="ila_8x12x131072.tcl"/>
|
||||
<File Type="RDS-RDS" Name="ila_8x12x131072.vds"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="ila_8x12x131072_drc_synth.rpt"/>
|
||||
<File Type="RDS-UTIL" Name="ila_8x12x131072_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ila_8x12x131072_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="ila_8x12x131072_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="ila_8x12x131072.vds"/>
|
||||
<File Type="RDS-DCP" Name="ila_8x12x131072.dcp"/>
|
||||
<File Type="PA-TCL" Name="ila_8x12x131072.tcl"/>
|
||||
<File Type="REPORTS-TCL" Name="ila_8x12x131072_reports.tcl"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_8x12x131072">
|
||||
<File Path="$PPRDIR/../basic_driver/ila_8x12x131072/ila_8x12x131072.xci">
|
||||
<FileInfo>
|
||||
@@ -56,9 +53,7 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
|
||||
+5
@@ -0,0 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado" Owner="josh" Host="JOSH-ASUS-Z690" Pid="2009845" HostCore="20" HostMemory="65588996">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
+270
@@ -0,0 +1,270 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
// GLOBAL VARIABLES
|
||||
var ISEShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var ISERunDir = "";
|
||||
var ISELogFile = "runme.log";
|
||||
var ISELogFileStr = null;
|
||||
var ISELogEcho = true;
|
||||
var ISEOldVersionWSH = false;
|
||||
|
||||
|
||||
|
||||
// BOOTSTRAP
|
||||
ISEInit();
|
||||
|
||||
|
||||
|
||||
//
|
||||
// ISE FUNCTIONS
|
||||
//
|
||||
function ISEInit() {
|
||||
|
||||
// 1. RUN DIR setup
|
||||
var ISEScrFP = WScript.ScriptFullName;
|
||||
var ISEScrN = WScript.ScriptName;
|
||||
ISERunDir =
|
||||
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
|
||||
|
||||
// 2. LOG file setup
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
// 3. LOG echo?
|
||||
var ISEScriptArgs = WScript.Arguments;
|
||||
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
|
||||
if ( ISEScriptArgs(loopi) == "-quiet" ) {
|
||||
ISELogEcho = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// 4. WSH version check
|
||||
var ISEOptimalVersionWSH = 5.6;
|
||||
var ISECurrentVersionWSH = WScript.Version;
|
||||
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
|
||||
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
|
||||
ISEOptimalVersionWSH + " or higher. Downloads" );
|
||||
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
|
||||
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
|
||||
ISEStdErr( "" );
|
||||
|
||||
ISEOldVersionWSH = true;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEStep( ISEProg, ISEArgs ) {
|
||||
|
||||
// CHECK for a STOP FILE
|
||||
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "*** Halting run - EA reset detected ***" );
|
||||
ISEStdErr( "" );
|
||||
WScript.Quit( 1 );
|
||||
}
|
||||
|
||||
// WRITE STEP HEADER to LOG
|
||||
ISEStdOut( "" );
|
||||
ISEStdOut( "*** Running " + ISEProg );
|
||||
ISEStdOut( " with args " + ISEArgs );
|
||||
ISEStdOut( "" );
|
||||
|
||||
// LAUNCH!
|
||||
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
|
||||
if ( ISEExitCode != 0 ) {
|
||||
WScript.Quit( ISEExitCode );
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEExec( ISEProg, ISEArgs ) {
|
||||
|
||||
var ISEStep = ISEProg;
|
||||
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
|
||||
ISEProg += ".bat";
|
||||
}
|
||||
|
||||
var ISECmdLine = ISEProg + " " + ISEArgs;
|
||||
var ISEExitCode = 1;
|
||||
|
||||
if ( ISEOldVersionWSH ) { // WSH 5.1
|
||||
|
||||
// BEGIN file creation
|
||||
ISETouchFile( ISEStep, "begin" );
|
||||
|
||||
// LAUNCH!
|
||||
ISELogFileStr.Close();
|
||||
ISECmdLine =
|
||||
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
|
||||
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
} else { // WSH 5.6
|
||||
|
||||
// LAUNCH!
|
||||
ISEShell.CurrentDirectory = ISERunDir;
|
||||
|
||||
// Redirect STDERR to STDOUT
|
||||
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
|
||||
var ISEProcess = ISEShell.Exec( ISECmdLine );
|
||||
|
||||
// BEGIN file creation
|
||||
var wbemFlagReturnImmediately = 0x10;
|
||||
var wbemFlagForwardOnly = 0x20;
|
||||
var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
|
||||
var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var NOC = 0;
|
||||
var NOLP = 0;
|
||||
var TPM = 0;
|
||||
|
||||
var cpuInfos = new Enumerator(processor);
|
||||
for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
|
||||
var cpuInfo = cpuInfos.item();
|
||||
NOC += cpuInfo.NumberOfCores;
|
||||
NOLP += cpuInfo.NumberOfLogicalProcessors;
|
||||
}
|
||||
var csInfos = new Enumerator(computerSystem);
|
||||
for(;!csInfos.atEnd(); csInfos.moveNext()) {
|
||||
var csInfo = csInfos.item();
|
||||
TPM += csInfo.TotalPhysicalMemory;
|
||||
}
|
||||
|
||||
var ISEHOSTCORE = NOLP
|
||||
var ISEMEMTOTAL = TPM
|
||||
|
||||
var ISENetwork = WScript.CreateObject( "WScript.Network" );
|
||||
var ISEHost = ISENetwork.ComputerName;
|
||||
var ISEUser = ISENetwork.UserName;
|
||||
var ISEPid = ISEProcess.ProcessID;
|
||||
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
|
||||
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
|
||||
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
|
||||
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
|
||||
"\" Owner=\"" + ISEUser +
|
||||
"\" Host=\"" + ISEHost +
|
||||
"\" Pid=\"" + ISEPid +
|
||||
"\" HostCore=\"" + ISEHOSTCORE +
|
||||
"\" HostMemory=\"" + ISEMEMTOTAL +
|
||||
"\">" );
|
||||
ISEBeginFile.WriteLine( " </Process>" );
|
||||
ISEBeginFile.WriteLine( "</ProcessHandle>" );
|
||||
ISEBeginFile.Close();
|
||||
|
||||
var ISEOutStr = ISEProcess.StdOut;
|
||||
var ISEErrStr = ISEProcess.StdErr;
|
||||
|
||||
// WAIT for ISEStep to finish
|
||||
while ( ISEProcess.Status == 0 ) {
|
||||
|
||||
// dump stdout then stderr - feels a little arbitrary
|
||||
while ( !ISEOutStr.AtEndOfStream ) {
|
||||
ISEStdOut( ISEOutStr.ReadLine() );
|
||||
}
|
||||
|
||||
WScript.Sleep( 100 );
|
||||
}
|
||||
|
||||
ISEExitCode = ISEProcess.ExitCode;
|
||||
}
|
||||
|
||||
ISELogFileStr.Close();
|
||||
|
||||
// END/ERROR file creation
|
||||
if ( ISEExitCode != 0 ) {
|
||||
ISETouchFile( ISEStep, "error" );
|
||||
|
||||
} else {
|
||||
ISETouchFile( ISEStep, "end" );
|
||||
}
|
||||
|
||||
return ISEExitCode;
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// UTILITIES
|
||||
//
|
||||
function ISEStdOut( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdOut.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISEStdErr( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdErr.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISETouchFile( ISERoot, ISEStatus ) {
|
||||
|
||||
var ISETFile =
|
||||
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
|
||||
ISETFile.Close();
|
||||
}
|
||||
|
||||
function ISEOpenFile( ISEFilename ) {
|
||||
|
||||
// This function has been updated to deal with a problem seen in CR #870871.
|
||||
// In that case the user runs a script that runs impl_1, and then turns around
|
||||
// and runs impl_1 -to_step write_bitstream. That second run takes place in
|
||||
// the same directory, which means we may hit some of the same files, and in
|
||||
// particular, we will open the runme.log file. Even though this script closes
|
||||
// the file (now), we see cases where a subsequent attempt to open the file
|
||||
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
|
||||
// play? In any case, we try to work around this by first waiting if the file
|
||||
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
|
||||
// and try to open the file 10 times with a one second delay after each attempt.
|
||||
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
|
||||
// If there is an unrecognized exception when trying to open the file, we output
|
||||
// an error message and write details to an exception.log file.
|
||||
var ISEFullPath = ISERunDir + "/" + ISEFilename;
|
||||
if (ISEFileSys.FileExists(ISEFullPath)) {
|
||||
// File is already there. This could be a problem. Wait in case it is still in use.
|
||||
WScript.Sleep(5000);
|
||||
}
|
||||
var i;
|
||||
for (i = 0; i < 10; ++i) {
|
||||
try {
|
||||
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
|
||||
} catch (exception) {
|
||||
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
|
||||
if (error_code == 52) { // 52 is bad file name or number.
|
||||
// Wait a second and try again.
|
||||
WScript.Sleep(1000);
|
||||
continue;
|
||||
} else {
|
||||
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
var exceptionFilePath = ISERunDir + "/exception.log";
|
||||
if (!ISEFileSys.FileExists(exceptionFilePath)) {
|
||||
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
|
||||
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
|
||||
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
exceptionFile.WriteLine("\tException name: " + exception.name);
|
||||
exceptionFile.WriteLine("\tException error code: " + error_code);
|
||||
exceptionFile.WriteLine("\tException message: " + exception.message);
|
||||
exceptionFile.Close();
|
||||
}
|
||||
throw exception;
|
||||
}
|
||||
}
|
||||
}
|
||||
// If we reached this point, we failed to open the file after 10 attempts.
|
||||
// We need to error out.
|
||||
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
|
||||
WScript.Quit(1);
|
||||
}
|
||||
+67
@@ -0,0 +1,67 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# ISEWrap.sh: Vivado Runs Script for UNIX
|
||||
# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
HD_LOG=$1
|
||||
shift
|
||||
|
||||
# CHECK for a STOP FILE
|
||||
if [ -f .stop.rst ]
|
||||
then
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
exit 1
|
||||
fi
|
||||
|
||||
ISE_STEP=$1
|
||||
shift
|
||||
|
||||
# WRITE STEP HEADER to LOG
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Running $ISE_STEP" >> $HD_LOG
|
||||
echo " with args $@" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
|
||||
# LAUNCH!
|
||||
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
|
||||
|
||||
# BEGIN file creation
|
||||
ISE_PID=$!
|
||||
if [ X != X$HOSTNAME ]
|
||||
then
|
||||
ISE_HOST=$HOSTNAME #bash
|
||||
else
|
||||
ISE_HOST=$HOST #csh
|
||||
fi
|
||||
ISE_USER=$USER
|
||||
|
||||
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
|
||||
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
|
||||
|
||||
ISE_BEGINFILE=.$ISE_STEP.begin.rst
|
||||
/bin/touch $ISE_BEGINFILE
|
||||
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
|
||||
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
|
||||
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
|
||||
echo " </Process>" >> $ISE_BEGINFILE
|
||||
echo "</ProcessHandle>" >> $ISE_BEGINFILE
|
||||
|
||||
# WAIT for ISEStep to finish
|
||||
wait $ISE_PID
|
||||
|
||||
# END/ERROR file creation
|
||||
RETVAL=$?
|
||||
if [ $RETVAL -eq 0 ]
|
||||
then
|
||||
/bin/touch .$ISE_STEP.end.rst
|
||||
else
|
||||
/bin/touch .$ISE_STEP.error.rst
|
||||
fi
|
||||
|
||||
exit $RETVAL
|
||||
|
||||
+32
@@ -0,0 +1,32 @@
|
||||
# This file is automatically generated.
|
||||
# It contains project source information necessary for synthesis and implementation.
|
||||
|
||||
# IP: /home/josh/Workspace/vivado-git/projects/duifei/common_ip/basic_driver/ila_8x12x8192/ila_8x12x8192.xci
|
||||
# IP: The module: 'ila_8x12x8192' is the root of the design. Do not add the DONT_TOUCH constraint.
|
||||
|
||||
# XDC: /home/josh/Workspace/vivado-git/projects/duifei/common_ip/basic_driver/ila_8x12x8192/ila_v6_2/constraints/ila_impl.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'ila_8x12x8192'. Do not add the DONT_TOUCH constraint.
|
||||
set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet
|
||||
|
||||
# XDC: /home/josh/Workspace/vivado-git/projects/duifei/common_ip/basic_driver/ila_8x12x8192/ila_v6_2/constraints/ila.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'ila_8x12x8192'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet
|
||||
|
||||
# XDC: /home/josh/Workspace/vivado-git/projects/duifei/common_ip/basic_driver/ila_8x12x8192/ila_8x12x8192_ooc.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'ila_8x12x8192'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet
|
||||
|
||||
# IP: /home/josh/Workspace/vivado-git/projects/duifei/common_ip/basic_driver/ila_8x12x8192/ila_8x12x8192.xci
|
||||
# IP: The module: 'ila_8x12x8192' is the root of the design. Do not add the DONT_TOUCH constraint.
|
||||
|
||||
# XDC: /home/josh/Workspace/vivado-git/projects/duifei/common_ip/basic_driver/ila_8x12x8192/ila_v6_2/constraints/ila_impl.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'ila_8x12x8192'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet
|
||||
|
||||
# XDC: /home/josh/Workspace/vivado-git/projects/duifei/common_ip/basic_driver/ila_8x12x8192/ila_v6_2/constraints/ila.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'ila_8x12x8192'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet
|
||||
|
||||
# XDC: /home/josh/Workspace/vivado-git/projects/duifei/common_ip/basic_driver/ila_8x12x8192/ila_8x12x8192_ooc.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'ila_8x12x8192'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet
|
||||
+64
@@ -0,0 +1,64 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="ila_8x12x8192_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1683523013">
|
||||
<File Type="VDS-TIMING-PB" Name="ila_8x12x8192_timing_summary_synth.pb"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="ila_8x12x8192_timing_summary_synth.rpt"/>
|
||||
<File Type="RDS-DCP" Name="ila_8x12x8192.dcp"/>
|
||||
<File Type="REPORTS-TCL" Name="ila_8x12x8192_reports.tcl"/>
|
||||
<File Type="PA-TCL" Name="ila_8x12x8192.tcl"/>
|
||||
<File Type="RDS-RDS" Name="ila_8x12x8192.vds"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="ila_8x12x8192_drc_synth.rpt"/>
|
||||
<File Type="RDS-UTIL" Name="ila_8x12x8192_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ila_8x12x8192_utilization_synth.pb"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_8x12x8192">
|
||||
<File Path="$PPRDIR/../basic_driver/ila_8x12x8192/ila_8x12x8192.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../basic_driver/ila_8x12x8192.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="ila_8x12x8192"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_8x12x8192">
|
||||
<File Path="$PPRDIR/../basic_driver/ila_8x12x8192/ila_8x12x8192.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../basic_driver/ila_8x12x8192.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="ila_8x12x8192"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
+9
@@ -0,0 +1,9 @@
|
||||
#
|
||||
# Vivado(TM)
|
||||
# htr.txt: a Vivado-generated description of how-to-repeat the
|
||||
# the basic steps of a run. Note that runme.bat/sh needs
|
||||
# to be invoked for Vivado to track run status.
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
vivado -log ila_8x12x8192.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ila_8x12x8192.tcl
|
||||
BIN
Binary file not shown.
+159
@@ -0,0 +1,159 @@
|
||||
#
|
||||
# Synthesis run script generated by Vivado
|
||||
#
|
||||
|
||||
set TIME_start [clock seconds]
|
||||
proc create_report { reportName command } {
|
||||
set status "."
|
||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
|
||||
set fp [open $status w]
|
||||
close $fp
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
set_param simulator.modelsimInstallPath /home/josh/Software/Mentor/modeltech/bin
|
||||
set_param simulator.vcsmxInstallPath /usr/synopsys/vcs/T-2022.06/bin
|
||||
set_param project.vivado.isBlockSynthRun true
|
||||
set_msg_config -msgmgr_mode ooc_run
|
||||
create_project -in_memory -part xc7z100ffg900-2
|
||||
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
set_param project.compositeFile.enableAutoGeneration 0
|
||||
set_param synth.vivado.isSynthRun true
|
||||
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
|
||||
set_property webtalk.parent_dir /home/josh/Workspace/vivado-git/projects/duifei/common_ip/managed_ip_project/managed_ip_project.cache/wt [current_project]
|
||||
set_property parent.project_path /home/josh/Workspace/vivado-git/projects/duifei/common_ip/managed_ip_project/managed_ip_project.xpr [current_project]
|
||||
set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]
|
||||
set_property default_lib xil_defaultlib [current_project]
|
||||
set_property target_language Verilog [current_project]
|
||||
set_property ip_output_repo /home/josh/Workspace/vivado-git/projects/duifei/common_ip/managed_ip_project/managed_ip_project.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
read_ip -quiet /home/josh/Workspace/vivado-git/projects/duifei/common_ip/basic_driver/ila_8x12x8192/ila_8x12x8192.xci
|
||||
set_property used_in_synthesis false [get_files -all /home/josh/Workspace/vivado-git/projects/duifei/common_ip/basic_driver/ila_8x12x8192/ila_v6_2/constraints/ila_impl.xdc]
|
||||
set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/duifei/common_ip/basic_driver/ila_8x12x8192/ila_v6_2/constraints/ila_impl.xdc]
|
||||
set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/duifei/common_ip/basic_driver/ila_8x12x8192/ila_v6_2/constraints/ila.xdc]
|
||||
set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/duifei/common_ip/basic_driver/ila_8x12x8192/ila_8x12x8192_ooc.xdc]
|
||||
|
||||
# Mark all dcp files as not used in implementation to prevent them from being
|
||||
# stitched into the results of this synthesis run. Any black boxes in the
|
||||
# design are intentionally left as such for best results. Dcp files will be
|
||||
# stitched into the design at a later time, either when this synthesis run is
|
||||
# opened, or when it is stitched into a dependent implementation run.
|
||||
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||
set_property used_in_implementation false $dcp
|
||||
}
|
||||
read_xdc dont_touch.xdc
|
||||
set_property used_in_implementation false [get_files dont_touch.xdc]
|
||||
set_param ips.enableIPCacheLiteLoad 1
|
||||
|
||||
set cached_ip [config_ip_cache -export -no_bom -dir /home/josh/Workspace/vivado-git/projects/duifei/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12x8192_synth_1 -new_name ila_8x12x8192 -ip [get_ips ila_8x12x8192]]
|
||||
|
||||
if { $cached_ip eq {} } {
|
||||
close [open __synthesis_is_running__ w]
|
||||
|
||||
synth_design -top ila_8x12x8192 -part xc7z100ffg900-2 -mode out_of_context
|
||||
|
||||
#---------------------------------------------------------
|
||||
# Generate Checkpoint/Stub/Simulation Files For IP Cache
|
||||
#---------------------------------------------------------
|
||||
# disable binary constraint mode for IPCache checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
|
||||
catch {
|
||||
write_checkpoint -force -noxdef -rename_prefix ila_8x12x8192_ ila_8x12x8192.dcp
|
||||
|
||||
set ipCachedFiles {}
|
||||
write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_8x12x8192_stub.v
|
||||
lappend ipCachedFiles ila_8x12x8192_stub.v
|
||||
|
||||
write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_8x12x8192_stub.vhdl
|
||||
lappend ipCachedFiles ila_8x12x8192_stub.vhdl
|
||||
|
||||
write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_8x12x8192_sim_netlist.v
|
||||
lappend ipCachedFiles ila_8x12x8192_sim_netlist.v
|
||||
|
||||
write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_8x12x8192_sim_netlist.vhdl
|
||||
lappend ipCachedFiles ila_8x12x8192_sim_netlist.vhdl
|
||||
set TIME_taken [expr [clock seconds] - $TIME_start]
|
||||
|
||||
config_ip_cache -add -dcp ila_8x12x8192.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips ila_8x12x8192]
|
||||
}
|
||||
|
||||
rename_ref -prefix_all ila_8x12x8192_
|
||||
|
||||
# disable binary constraint mode for synth run checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
write_checkpoint -force -noxdef ila_8x12x8192.dcp
|
||||
create_report "ila_8x12x8192_synth_1_synth_report_utilization_0" "report_utilization -file ila_8x12x8192_utilization_synth.rpt -pb ila_8x12x8192_utilization_synth.pb"
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/duifei/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12x8192_synth_1/ila_8x12x8192_stub.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/duifei/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12x8192_synth_1/ila_8x12x8192_stub.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode funcsim /home/josh/Workspace/vivado-git/projects/duifei/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12x8192_synth_1/ila_8x12x8192_sim_netlist.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode funcsim /home/josh/Workspace/vivado-git/projects/duifei/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12x8192_synth_1/ila_8x12x8192_sim_netlist.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
|
||||
} else {
|
||||
|
||||
|
||||
}; # end if cached_ip
|
||||
|
||||
add_files /home/josh/Workspace/vivado-git/projects/duifei/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12x8192_synth_1/ila_8x12x8192_stub.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/common_ip/basic_driver/ila_8x12x8192/ila_8x12x8192.xci]
|
||||
|
||||
add_files /home/josh/Workspace/vivado-git/projects/duifei/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12x8192_synth_1/ila_8x12x8192_stub.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/common_ip/basic_driver/ila_8x12x8192/ila_8x12x8192.xci]
|
||||
|
||||
add_files /home/josh/Workspace/vivado-git/projects/duifei/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12x8192_synth_1/ila_8x12x8192_sim_netlist.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/common_ip/basic_driver/ila_8x12x8192/ila_8x12x8192.xci]
|
||||
|
||||
add_files /home/josh/Workspace/vivado-git/projects/duifei/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12x8192_synth_1/ila_8x12x8192_sim_netlist.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/common_ip/basic_driver/ila_8x12x8192/ila_8x12x8192.xci]
|
||||
|
||||
add_files /home/josh/Workspace/vivado-git/projects/duifei/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12x8192_synth_1/ila_8x12x8192.dcp -of_objects [get_files /home/josh/Workspace/vivado-git/projects/duifei/common_ip/basic_driver/ila_8x12x8192/ila_8x12x8192.xci]
|
||||
|
||||
if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/common_ip/ip_user_files/ip/ila_8x12x8192]} {
|
||||
catch {
|
||||
file copy -force /home/josh/Workspace/vivado-git/projects/duifei/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12x8192_synth_1/ila_8x12x8192_sim_netlist.v /home/josh/Workspace/vivado-git/projects/duifei/common_ip/ip_user_files/ip/ila_8x12x8192
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/common_ip/ip_user_files/ip/ila_8x12x8192]} {
|
||||
catch {
|
||||
file copy -force /home/josh/Workspace/vivado-git/projects/duifei/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12x8192_synth_1/ila_8x12x8192_sim_netlist.vhdl /home/josh/Workspace/vivado-git/projects/duifei/common_ip/ip_user_files/ip/ila_8x12x8192
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/common_ip/ip_user_files/ip/ila_8x12x8192]} {
|
||||
catch {
|
||||
file copy -force /home/josh/Workspace/vivado-git/projects/duifei/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12x8192_synth_1/ila_8x12x8192_stub.v /home/josh/Workspace/vivado-git/projects/duifei/common_ip/ip_user_files/ip/ila_8x12x8192
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir /home/josh/Workspace/vivado-git/projects/duifei/common_ip/ip_user_files/ip/ila_8x12x8192]} {
|
||||
catch {
|
||||
file copy -force /home/josh/Workspace/vivado-git/projects/duifei/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12x8192_synth_1/ila_8x12x8192_stub.vhdl /home/josh/Workspace/vivado-git/projects/duifei/common_ip/ip_user_files/ip/ila_8x12x8192
|
||||
}
|
||||
}
|
||||
file delete __synthesis_is_running__
|
||||
close [open __synthesis_is_complete__ w]
|
||||
+3015
File diff suppressed because it is too large
Load Diff
BIN
Binary file not shown.
BIN
Binary file not shown.
+29
@@ -0,0 +1,29 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Mon May 8 13:18:13 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/duifei/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12x8192_synth_1/ila_8x12x8192_stub.v
|
||||
// Design : ila_8x12x8192
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7z100ffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "ila,Vivado 2019.1.3" *)
|
||||
module ila_8x12x8192(clk, probe0, probe1, probe2, probe3, probe4, probe5,
|
||||
probe6, probe7)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0]" */;
|
||||
input clk;
|
||||
input [11:0]probe0;
|
||||
input [11:0]probe1;
|
||||
input [11:0]probe2;
|
||||
input [11:0]probe3;
|
||||
input [11:0]probe4;
|
||||
input [11:0]probe5;
|
||||
input [11:0]probe6;
|
||||
input [11:0]probe7;
|
||||
endmodule
|
||||
+38
@@ -0,0 +1,38 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Mon May 8 13:18:13 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/duifei/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12x8192_synth_1/ila_8x12x8192_stub.vhdl
|
||||
-- Design : ila_8x12x8192
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7z100ffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity ila_8x12x8192 is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe0 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe1 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe2 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe3 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe4 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe5 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe6 : in STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe7 : in STD_LOGIC_VECTOR ( 11 downto 0 )
|
||||
);
|
||||
|
||||
end ila_8x12x8192;
|
||||
|
||||
architecture stub of ila_8x12x8192 is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
BIN
Binary file not shown.
+192
@@ -0,0 +1,192 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
| Date : Mon May 8 13:18:13 2023
|
||||
| Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
| Command : report_utilization -file ila_8x12x8192_utilization_synth.rpt -pb ila_8x12x8192_utilization_synth.pb
|
||||
| Design : ila_8x12x8192
|
||||
| Device : 7z100ffg900-2
|
||||
| Design State : Synthesized
|
||||
---------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Slice Logic
|
||||
1.1 Summary of Registers by Type
|
||||
2. Memory
|
||||
3. DSP
|
||||
4. IO and GT Specific
|
||||
5. Clocking
|
||||
6. Specific Feature
|
||||
7. Primitives
|
||||
8. Black Boxes
|
||||
9. Instantiated Netlists
|
||||
|
||||
1. Slice Logic
|
||||
--------------
|
||||
|
||||
+----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+----------------------------+------+-------+-----------+-------+
|
||||
| Slice LUTs* | 3230 | 0 | 277400 | 1.16 |
|
||||
| LUT as Logic | 2511 | 0 | 277400 | 0.91 |
|
||||
| LUT as Memory | 719 | 0 | 108200 | 0.66 |
|
||||
| LUT as Distributed RAM | 128 | 0 | | |
|
||||
| LUT as Shift Register | 591 | 0 | | |
|
||||
| Slice Registers | 4154 | 0 | 554800 | 0.75 |
|
||||
| Register as Flip Flop | 4154 | 0 | 554800 | 0.75 |
|
||||
| Register as Latch | 0 | 0 | 554800 | 0.00 |
|
||||
| F7 Muxes | 123 | 0 | 138700 | 0.09 |
|
||||
| F8 Muxes | 18 | 0 | 69350 | 0.03 |
|
||||
+----------------------------+------+-------+-----------+-------+
|
||||
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
|
||||
|
||||
|
||||
1.1 Summary of Registers by Type
|
||||
--------------------------------
|
||||
|
||||
+-------+--------------+-------------+--------------+
|
||||
| Total | Clock Enable | Synchronous | Asynchronous |
|
||||
+-------+--------------+-------------+--------------+
|
||||
| 0 | _ | - | - |
|
||||
| 0 | _ | - | Set |
|
||||
| 0 | _ | - | Reset |
|
||||
| 0 | _ | Set | - |
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 0 | Yes | - | Set |
|
||||
| 0 | Yes | - | Reset |
|
||||
| 9 | Yes | Set | - |
|
||||
| 4145 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
2. Memory
|
||||
---------
|
||||
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
| Block RAM Tile | 22 | 0 | 755 | 2.91 |
|
||||
| RAMB36/FIFO* | 22 | 0 | 755 | 2.91 |
|
||||
| RAMB36E1 only | 22 | | | |
|
||||
| RAMB18 | 0 | 0 | 1510 | 0.00 |
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
|
||||
3. DSP
|
||||
------
|
||||
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| DSPs | 0 | 0 | 2020 | 0.00 |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
4. IO and GT Specific
|
||||
---------------------
|
||||
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Bonded IOB | 0 | 0 | 362 | 0.00 |
|
||||
| Bonded IPADs | 0 | 0 | 50 | 0.00 |
|
||||
| Bonded OPADs | 0 | 0 | 32 | 0.00 |
|
||||
| Bonded IOPADs | 0 | 0 | 130 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 8 | 0.00 |
|
||||
| PHASER_REF | 0 | 0 | 8 | 0.00 |
|
||||
| OUT_FIFO | 0 | 0 | 32 | 0.00 |
|
||||
| IN_FIFO | 0 | 0 | 32 | 0.00 |
|
||||
| IDELAYCTRL | 0 | 0 | 8 | 0.00 |
|
||||
| IBUFDS | 0 | 0 | 348 | 0.00 |
|
||||
| GTXE2_COMMON | 0 | 0 | 4 | 0.00 |
|
||||
| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 |
|
||||
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 |
|
||||
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 |
|
||||
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 |
|
||||
| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 |
|
||||
| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 |
|
||||
| ILOGIC | 0 | 0 | 362 | 0.00 |
|
||||
| OLOGIC | 0 | 0 | 362 | 0.00 |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
5. Clocking
|
||||
-----------
|
||||
|
||||
+------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+------------+------+-------+-----------+-------+
|
||||
| BUFGCTRL | 0 | 0 | 32 | 0.00 |
|
||||
| BUFIO | 0 | 0 | 32 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 8 | 0.00 |
|
||||
| PLLE2_ADV | 0 | 0 | 8 | 0.00 |
|
||||
| BUFMRCE | 0 | 0 | 16 | 0.00 |
|
||||
| BUFHCE | 0 | 0 | 168 | 0.00 |
|
||||
| BUFR | 0 | 0 | 32 | 0.00 |
|
||||
+------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
6. Specific Feature
|
||||
-------------------
|
||||
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| BSCANE2 | 0 | 0 | 4 | 0.00 |
|
||||
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
|
||||
| DNA_PORT | 0 | 0 | 1 | 0.00 |
|
||||
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
|
||||
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
|
||||
| ICAPE2 | 0 | 0 | 2 | 0.00 |
|
||||
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
|
||||
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
|
||||
| XADC | 0 | 0 | 1 | 0.00 |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
7. Primitives
|
||||
-------------
|
||||
|
||||
+----------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+------+---------------------+
|
||||
| FDRE | 4145 | Flop & Latch |
|
||||
| LUT6 | 1504 | LUT |
|
||||
| LUT4 | 533 | LUT |
|
||||
| SRL16E | 520 | Distributed Memory |
|
||||
| SRLC32E | 485 | Distributed Memory |
|
||||
| LUT3 | 355 | LUT |
|
||||
| LUT5 | 230 | LUT |
|
||||
| CARRY4 | 183 | CarryLogic |
|
||||
| RAMD64E | 128 | Distributed Memory |
|
||||
| MUXF7 | 123 | MuxFx |
|
||||
| LUT2 | 102 | LUT |
|
||||
| LUT1 | 85 | LUT |
|
||||
| RAMB36E1 | 22 | Block Memory |
|
||||
| MUXF8 | 18 | MuxFx |
|
||||
| FDSE | 9 | Flop & Latch |
|
||||
| SRLC16E | 2 | Distributed Memory |
|
||||
+----------+------+---------------------+
|
||||
|
||||
|
||||
8. Black Boxes
|
||||
--------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
9. Instantiated Netlists
|
||||
------------------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
+49
@@ -0,0 +1,49 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3134:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
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||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
|
||||
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||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
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||||
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||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:3132:00:00
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||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:74727565:00:00
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||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00
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||||
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||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
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||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c636c6b5f77697a5f76365f305f335c6164393336315f636c6b5f67656e5f636d6f735f31743172:636f72655f636f6e7461696e6572:74727565:00:00
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||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c636c6b5f77697a5f76365f305f335c6164393336315f636c6b5f67656e5f636d6f735f32743272:636f72655f636f6e7461696e6572:74727565:00:00
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||||
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||||
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|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c636c6b5f77697a5f76365f305f335c616e745f636c6b5f67656e5f73746732:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c6669666f5f67656e657261746f725f7631335f325f345c6669666f5f416e744374726c:636f72655f636f6e7461696e6572:74727565:00:00
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||||
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|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f3278313278313331303732:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f3478313278313331303732:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f3878313278313331303732:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f387831327838313932:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f416e744374726c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f7266636f6e74726c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f616e745f7264:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f616e745f74657374:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f6d616e75616c5f6374726c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f72665f7264:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f7266636f6e74726c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3237:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3237:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3237:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3237:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3237:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3237:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3237:00:00
|
||||
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3532343239366239313035323433306261313030396434643530666536343930:506172656e742050412070726f6a656374204944:00
|
||||
eof:1104763937
|
||||
+40
@@ -0,0 +1,40 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
echo "This script was generated under a different operating system."
|
||||
echo "Please update the PATH variable below, before executing this script"
|
||||
exit
|
||||
|
||||
var WshShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ProcEnv = WshShell.Environment( "Process" );
|
||||
var PathVal = ProcEnv("PATH");
|
||||
if ( PathVal.length == 0 ) {
|
||||
PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;";
|
||||
} else {
|
||||
PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;" + PathVal;
|
||||
}
|
||||
|
||||
ProcEnv("PATH") = PathVal;
|
||||
|
||||
var RDScrFP = WScript.ScriptFullName;
|
||||
var RDScrN = WScript.ScriptName;
|
||||
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
|
||||
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
|
||||
eval( EAInclude(ISEJScriptLib) );
|
||||
|
||||
|
||||
ISEStep( "vivado",
|
||||
"-log ila_8x12x8192.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ila_8x12x8192.tcl" );
|
||||
|
||||
|
||||
|
||||
function EAInclude( EAInclFilename ) {
|
||||
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
|
||||
var EAIFContents = EAInclFile.ReadAll();
|
||||
EAInclFile.Close();
|
||||
return EAIFContents;
|
||||
}
|
||||
+11
@@ -0,0 +1,11 @@
|
||||
@echo off
|
||||
|
||||
rem Vivado (TM)
|
||||
rem runme.bat: a Vivado-generated Script
|
||||
rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
|
||||
set HD_SDIR=%~dp0
|
||||
cd /d "%HD_SDIR%"
|
||||
set PATH=%SYSTEMROOT%\system32;%PATH%
|
||||
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
|
||||
Executable
+39
@@ -0,0 +1,39 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# runme.sh: a Vivado-generated Runs Script for UNIX
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
if [ -z "$PATH" ]; then
|
||||
PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin
|
||||
else
|
||||
PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin:$PATH
|
||||
fi
|
||||
export PATH
|
||||
|
||||
if [ -z "$LD_LIBRARY_PATH" ]; then
|
||||
LD_LIBRARY_PATH=
|
||||
else
|
||||
LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
|
||||
fi
|
||||
export LD_LIBRARY_PATH
|
||||
|
||||
HD_PWD='/home/josh/Workspace/vivado-git/projects/duifei/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12x8192_synth_1'
|
||||
cd "$HD_PWD"
|
||||
|
||||
HD_LOG=runme.log
|
||||
/bin/touch $HD_LOG
|
||||
|
||||
ISEStep="./ISEWrap.sh"
|
||||
EAStep()
|
||||
{
|
||||
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
|
||||
if [ $? -ne 0 ]
|
||||
then
|
||||
exit
|
||||
fi
|
||||
}
|
||||
|
||||
EAStep vivado -log ila_8x12x8192.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ila_8x12x8192.tcl
|
||||
BIN
Binary file not shown.
+6
-11
@@ -1,14 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="vio_manual_ctrl_synth_1" LaunchPart="xc7z100ffg900-2" LaunchTime="1681355354">
|
||||
<File Type="VDS-TIMING-PB" Name="vio_manual_ctrl_timing_summary_synth.pb"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="vio_manual_ctrl_timing_summary_synth.rpt"/>
|
||||
<File Type="RDS-DCP" Name="vio_manual_ctrl.dcp"/>
|
||||
<File Type="REPORTS-TCL" Name="vio_manual_ctrl_reports.tcl"/>
|
||||
<File Type="PA-TCL" Name="vio_manual_ctrl.tcl"/>
|
||||
<File Type="RDS-RDS" Name="vio_manual_ctrl.vds"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="vio_manual_ctrl_drc_synth.rpt"/>
|
||||
<File Type="RDS-UTIL" Name="vio_manual_ctrl_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="vio_manual_ctrl_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="vio_manual_ctrl_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="vio_manual_ctrl.vds"/>
|
||||
<File Type="RDS-DCP" Name="vio_manual_ctrl.dcp"/>
|
||||
<File Type="PA-TCL" Name="vio_manual_ctrl.tcl"/>
|
||||
<File Type="REPORTS-TCL" Name="vio_manual_ctrl_reports.tcl"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_manual_ctrl">
|
||||
<File Path="$PPRDIR/../basic_driver/vio_manual_ctrl/vio_manual_ctrl.xci">
|
||||
<FileInfo>
|
||||
@@ -56,9 +53,7 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
|
||||
@@ -39,13 +39,13 @@
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="27"/>
|
||||
<Option Name="WTModelSimExportSim" Val="27"/>
|
||||
<Option Name="WTQuestaExportSim" Val="27"/>
|
||||
<Option Name="WTIesExportSim" Val="27"/>
|
||||
<Option Name="WTVcsExportSim" Val="27"/>
|
||||
<Option Name="WTRivieraExportSim" Val="27"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="27"/>
|
||||
<Option Name="WTXSimExportSim" Val="28"/>
|
||||
<Option Name="WTModelSimExportSim" Val="28"/>
|
||||
<Option Name="WTQuestaExportSim" Val="28"/>
|
||||
<Option Name="WTIesExportSim" Val="28"/>
|
||||
<Option Name="WTVcsExportSim" Val="28"/>
|
||||
<Option Name="WTRivieraExportSim" Val="28"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="28"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
@@ -170,6 +170,7 @@
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
@@ -384,6 +385,26 @@
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="ila_8x12x8192" Type="BlockSrcs" RelSrcDir="$PSRCDIR/ila_8x12x8192">
|
||||
<File Path="$PPRDIR/../basic_driver/ila_8x12x8192.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../basic_driver/ila_8x12x8192/ila_8x12x8192.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="ila_8x12x8192"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
@@ -412,9 +433,7 @@
|
||||
<Runs Version="1" Minor="10">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z100ffg900-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
|
||||
@@ -422,9 +441,7 @@
|
||||
</Run>
|
||||
<Run Id="ad9361_clk_gen_cmos_1t1r_synth_1" Type="Ft3:Synth" SrcSet="ad9361_clk_gen_cmos_1t1r" Part="xc7z100ffg900-2" ConstrsSet="ad9361_clk_gen_cmos_1t1r" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ad9361_clk_gen_cmos_1t1r_synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
@@ -433,9 +450,7 @@
|
||||
</Run>
|
||||
<Run Id="ad9361_clk_gen_cmos_2t2r_synth_1" Type="Ft3:Synth" SrcSet="ad9361_clk_gen_cmos_2t2r" Part="xc7z100ffg900-2" ConstrsSet="ad9361_clk_gen_cmos_2t2r" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ad9361_clk_gen_cmos_2t2r_synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
@@ -444,9 +459,7 @@
|
||||
</Run>
|
||||
<Run Id="ad9361_clk_gen_lvds_2t2r_synth_1" Type="Ft3:Synth" SrcSet="ad9361_clk_gen_lvds_2t2r" Part="xc7z100ffg900-2" ConstrsSet="ad9361_clk_gen_lvds_2t2r" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ad9361_clk_gen_lvds_2t2r_synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
@@ -455,9 +468,7 @@
|
||||
</Run>
|
||||
<Run Id="ant_clk_gen_stg1_synth_1" Type="Ft3:Synth" SrcSet="ant_clk_gen_stg1" Part="xc7z100ffg900-2" ConstrsSet="ant_clk_gen_stg1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ant_clk_gen_stg1_synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
@@ -466,9 +477,7 @@
|
||||
</Run>
|
||||
<Run Id="ant_clk_gen_stg2_synth_1" Type="Ft3:Synth" SrcSet="ant_clk_gen_stg2" Part="xc7z100ffg900-2" ConstrsSet="ant_clk_gen_stg2" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ant_clk_gen_stg2_synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
@@ -477,9 +486,7 @@
|
||||
</Run>
|
||||
<Run Id="ila_2x12x1024_synth_1" Type="Ft3:Synth" SrcSet="ila_2x12x1024" Part="xc7z100ffg900-2" ConstrsSet="ila_2x12x1024" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ila_2x12x1024_synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
@@ -488,9 +495,7 @@
|
||||
</Run>
|
||||
<Run Id="ila_2x12x131072_synth_1" Type="Ft3:Synth" SrcSet="ila_2x12x131072" Part="xc7z100ffg900-2" ConstrsSet="ila_2x12x131072" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ila_2x12x131072_synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
@@ -499,9 +504,7 @@
|
||||
</Run>
|
||||
<Run Id="ila_4x12x131072_synth_1" Type="Ft3:Synth" SrcSet="ila_4x12x131072" Part="xc7z100ffg900-2" ConstrsSet="ila_4x12x131072" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ila_4x12x131072_synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
@@ -510,9 +513,7 @@
|
||||
</Run>
|
||||
<Run Id="ila_8x12x131072_synth_1" Type="Ft3:Synth" SrcSet="ila_8x12x131072" Part="xc7z100ffg900-2" ConstrsSet="ila_8x12x131072" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ila_8x12x131072_synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
@@ -520,6 +521,15 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="vio_manual_ctrl_synth_1" Type="Ft3:Synth" SrcSet="vio_manual_ctrl" Part="xc7z100ffg900-2" ConstrsSet="vio_manual_ctrl" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/vio_manual_ctrl_synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="ila_8x12x8192_synth_1" Type="Ft3:Synth" SrcSet="ila_8x12x8192" Part="xc7z100ffg900-2" ConstrsSet="ila_8x12x8192" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ila_8x12x8192_synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
@@ -532,9 +542,7 @@
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
@@ -550,9 +558,7 @@
|
||||
</Run>
|
||||
<Run Id="ad9361_clk_gen_cmos_1t1r_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="ad9361_clk_gen_cmos_1t1r" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ad9361_clk_gen_cmos_1t1r_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
@@ -568,9 +574,7 @@
|
||||
</Run>
|
||||
<Run Id="ad9361_clk_gen_cmos_2t2r_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="ad9361_clk_gen_cmos_2t2r" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ad9361_clk_gen_cmos_2t2r_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
@@ -586,9 +590,7 @@
|
||||
</Run>
|
||||
<Run Id="ad9361_clk_gen_lvds_2t2r_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="ad9361_clk_gen_lvds_2t2r" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ad9361_clk_gen_lvds_2t2r_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
@@ -604,9 +606,7 @@
|
||||
</Run>
|
||||
<Run Id="ant_clk_gen_stg1_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="ant_clk_gen_stg1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ant_clk_gen_stg1_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
@@ -622,9 +622,7 @@
|
||||
</Run>
|
||||
<Run Id="ant_clk_gen_stg2_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="ant_clk_gen_stg2" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ant_clk_gen_stg2_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
@@ -640,9 +638,7 @@
|
||||
</Run>
|
||||
<Run Id="ila_2x12x1024_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="ila_2x12x1024" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ila_2x12x1024_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
@@ -658,9 +654,7 @@
|
||||
</Run>
|
||||
<Run Id="ila_2x12x131072_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="ila_2x12x131072" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ila_2x12x131072_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
@@ -676,9 +670,7 @@
|
||||
</Run>
|
||||
<Run Id="ila_4x12x131072_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="ila_4x12x131072" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ila_4x12x131072_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
@@ -694,9 +686,7 @@
|
||||
</Run>
|
||||
<Run Id="ila_8x12x131072_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="ila_8x12x131072" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ila_8x12x131072_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
@@ -711,6 +701,22 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="vio_manual_ctrl_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="vio_manual_ctrl" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="vio_manual_ctrl_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
</Run>
|
||||
<Run Id="ila_8x12x8192_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="ila_8x12x8192" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ila_8x12x8192_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
|
||||
Reference in New Issue
Block a user