finish coding and testing of online acq; add sample data

串行在线捕获程序已经完成编写,并进行了仿真和测试(对飞和814均可用);增加了在电子所使用转台测试的幅相采集数据
2023-05-08 19:13:53 +08:00
parent e07389e326
commit 2d4650a3b6
2835 changed files with 408373 additions and 181193 deletions
@@ -0,0 +1,133 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+//
+// Create Date: 2022/11/01 11:15:25
+// Design Name:
+// Module Name: clk_dist
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description: Clock distribution module
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module clk_dist
+(
+    // input clocks
+    input           clk_250m_p          , // generated by ad9516, 250mhz
+    input           clk_250m_n          ,
+    input           ad9361_1_rx_data_clk, // ad9361 rx data clock, 83.3333mhz
+    input           ad9361_2_rx_data_clk, // ad9361 rx data clock, 83.3333mhz
+
+    // output clocks & reset
+    // global reset
+    output          sys_rst             , // global reset signal, active high
+    output          ant_rst             , // phased-array & rf control reset signal, active high
+
+    // pl signal processing clock
+    output          sys_clk             , // 41.6667mhz
+    output          sys_clk_2x          , // 83.3333mhz
+    output          sys_clk_3x          , // 125mhz
+    output          sys_clk_4x          , // 166.6667mhz
+    output          sys_clk_ld          , // system main clock locked indicator
+
+    // ad9361-1 clocks
+    output          ad9361_1_clk        , // 41.6667mhz
+    output          ad9361_1_clk_2x     , // 83.3333mhz
+    output          ad9361_1_clk_3x     , // 125mhz
+    output          ad9361_1_clk_4x     , // 166.6667mhz
+    output          ad9361_1_clk_ld     , // ad9361-1 clock group locked indicator
+
+    // ad9361-2 clocks
+    output          ad9361_2_clk        , // 41.6667mhz
+    output          ad9361_2_clk_2x     , // 83.3333mhz
+    output          ad9361_2_clk_3x     , // 125mhz
+    output          ad9361_2_clk_4x     , // 166.6667mhz
+    output          ad9361_2_clk_ld     , // ad9361-2 clock group locked indicator
+
+    // phased-array & rf control clocks
+    output          clk_96m             ,
+    output          clk_48m             ,
+    output          clk_32m             ,
+    output          clk_19p2m
+);
+
+assign sys_clk    = ad9361_1_clk   ;
+assign sys_clk_2x = ad9361_1_clk_2x;
+assign sys_clk_3x = ad9361_1_clk_3x;
+assign sys_clk_4x = ad9361_1_clk_4x;
+assign sys_clk_ld = ad9361_1_clk_ld;
+
+assign sys_rst = ~sys_clk_ld;
+
+ad9361_clk_gen_cmos_2t2r u_ad9361_1_clk_gen
+(
+    // Clock out ports
+    .clk_out1   (ad9361_1_clk           ), // output clk_out1
+    .clk_out2   (ad9361_1_clk_2x        ), // output clk_out2
+    .clk_out3   (ad9361_1_clk_3x        ), // output clk_out3
+    .clk_out4   (ad9361_1_clk_4x        ), // output clk_out4
+    // Status and control signals
+    .locked     (ad9361_1_clk_ld        ), // output locked
+    // Clock in ports
+    .clk_in1    (ad9361_1_rx_data_clk   )  // input clk_in1
+);
+
+ad9361_clk_gen_cmos_2t2r u_ad9361_2_clk_gen
+(
+    // Clock out ports
+    .clk_out1   (ad9361_2_clk           ), // output clk_out1
+    .clk_out2   (ad9361_2_clk_2x        ), // output clk_out2
+    .clk_out3   (ad9361_2_clk_3x        ), // output clk_out3
+    .clk_out4   (ad9361_2_clk_4x        ), // output clk_out4
+    // Status and control signals
+    .locked     (ad9361_2_clk_ld        ), // output locked
+    // Clock in ports
+    .clk_in1    (ad9361_2_rx_data_clk   )  // input clk_in1
+);
+
+wire            ant_clk_stg1_96m;
+wire            ant_clk_stg1_ld;
+wire            ant_clk_stg2_ld;
+
+assign ant_rst = ~ant_clk_stg2_ld;
+
+ant_clk_gen_stg1 u_ant_clk_gen_stg1
+(
+    // Clock out ports
+    .clk_out1   (ant_clk_stg1_96m       ), // output clk_out1
+    // Status and control signals
+    .locked     (ant_clk_stg1_ld        ), // output locked
+    // Clock in ports
+    .clk_in1_p  (clk_250m_p             ), // input clk_in1_p
+    .clk_in1_n  (clk_250m_n             )  // input clk_in1_n
+);
+
+ant_clk_gen_stg2 u_ant_clk_gen_stg2
+(
+    // Clock out ports
+    .clk_out1   (clk_96m                ), // output clk_out1
+    .clk_out2   (clk_48m                ), // output clk_out2
+    .clk_out3   (clk_32m                ), // output clk_out3
+    .clk_out4   (clk_19p2m              ), // output clk_out4
+    // Status and control signals
+    .locked     (ant_clk_stg2_ld        ), // output locked
+    // Clock in ports
+    .clk_in1    (ant_clk_stg1_96m       )  // input clk_in1
+);
+
+endmodule