finish coding and testing of online acq; add sample data

串行在线捕获程序已经完成编写,并进行了仿真和测试(对飞和814均可用);增加了在电子所使用转台测试的幅相采集数据

projects/duifei/duifei_online_acq/rtl/tx_pre_process.v

@@ -0,0 +1,138 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+//
+// Create Date: 2023/02/25 15:20:22
+// Design Name:
+// Module Name: tx_pre_process
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module tx_pre_process
+#(
+    parameter ADC_DATA_WIDTH = 12,
+    parameter PRBS = 128'b00000011000010100011110010001011001110101001111101000011100010010011011010110111101100011010010111011100110010101011111110000001, // inverse pseudorandom bit sequence, [0,flip(PRSB7)]
+    parameter PRBS_LEN = 128, // length of pseudorandom bit sequence
+    parameter INTERP_FACTOR = 8, // interpolation factor, max inter-channel delay ranges in [-INTERP_FACTOR+1,INTERP_FACTOR-1]
+    parameter CAL_MOD_FINE = 1
+)
+(
+    // clock & reset
+    input           clk                         ,
+    input           rst                         ,
+    // input data
+    input [ADC_DATA_WIDTH-1:0] tx_data_ch1_i    ,
+    input [ADC_DATA_WIDTH-1:0] tx_data_ch1_q    ,
+    input [ADC_DATA_WIDTH-1:0] tx_data_ch2_i    ,
+    input [ADC_DATA_WIDTH-1:0] tx_data_ch2_q    ,
+    // ad9361 calibration interface
+    input           ad9361_tx_switch            ,
+    //
+    input [$clog2(ADC_DATA_WIDTH)-1:0] bb_rshift,
+    // output data
+    output [ADC_DATA_WIDTH-1:0] tx_ch1_i        ,
+    output [ADC_DATA_WIDTH-1:0] tx_ch1_q        ,
+    output [ADC_DATA_WIDTH-1:0] tx_ch2_i        ,
+    output [ADC_DATA_WIDTH-1:0] tx_ch2_q
+);
+
+integer i;
+
+// square shaped bpsk signal
+reg [$clog2(PRBS_LEN*INTERP_FACTOR)-1 : 0] chip_interp_cnt = 'b0;
+reg signed [ADC_DATA_WIDTH-1:0] tx_pn_i = 'b0;
+reg signed [ADC_DATA_WIDTH-1:0] tx_pn_q = 'b0;
+
+if (CAL_MOD_FINE == 1) begin
+
+always @(posedge clk) begin
+    if (rst) begin
+        chip_interp_cnt <= 'b0;
+    end
+    else begin
+        chip_interp_cnt <= chip_interp_cnt + 1'b1;
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        tx_pn_i <= 'b0;
+        tx_pn_q <= 'b0;
+    end
+    else begin
+        tx_pn_i <= PRBS[chip_interp_cnt[$clog2(PRBS_LEN*INTERP_FACTOR)-1 -: $clog2(PRBS_LEN)]] ? {1'b0,{(ADC_DATA_WIDTH-1){1'b1}}} : {1'b1,{(ADC_DATA_WIDTH-2){1'b0}},1'b1}; // (1 or 0) ? 4'b0111 : 4'b1001
+        tx_pn_q <= PRBS[chip_interp_cnt[$clog2(PRBS_LEN*INTERP_FACTOR)-1 -: $clog2(PRBS_LEN)]] ? {1'b1,{(ADC_DATA_WIDTH-2){1'b0}},1'b1} : {1'b0,{(ADC_DATA_WIDTH-1){1'b1}}}; // (1 or 0) ? 4'b1001 : 4'b0111
+    end
+end
+
+end // if (CAL_MOD_FINE == 1)
+
+// buffer input control signals (clock domain crossing from ps to pl clock domain)
+reg ad9361_tx_switch_d1 = 'b0;
+reg ad9361_tx_switch_d2 = 'b0;
+
+wire signed [ADC_DATA_WIDTH-1:0] tx_dc_i = {1'b0,{(ADC_DATA_WIDTH-2){1'b1}},1'b1};
+wire signed [ADC_DATA_WIDTH-1:0] tx_dc_q = {1'b1,{(ADC_DATA_WIDTH-2){1'b0}},1'b1};
+
+always @(posedge clk) begin
+    ad9361_tx_switch_d1 <= ad9361_tx_switch;
+    ad9361_tx_switch_d2 <= ad9361_tx_switch_d1;
+end
+
+reg [ADC_DATA_WIDTH-1 : 0] tx_ch1_i_buf = 'b0;
+reg [ADC_DATA_WIDTH-1 : 0] tx_ch1_q_buf = 'b0;
+reg [ADC_DATA_WIDTH-1 : 0] tx_ch2_i_buf = 'b0;
+reg [ADC_DATA_WIDTH-1 : 0] tx_ch2_q_buf = 'b0;
+
+assign tx_ch1_i = tx_ch1_i_buf;
+assign tx_ch1_q = tx_ch1_q_buf;
+assign tx_ch2_i = tx_ch2_i_buf;
+assign tx_ch2_q = tx_ch2_q_buf;
+
+always @(posedge clk) begin
+    if (rst) begin
+        tx_ch1_i_buf <= 'b0;
+        tx_ch1_q_buf <= 'b0;
+        tx_ch2_i_buf <= 'b0;
+        tx_ch2_q_buf <= 'b0;
+    end
+    else if (ad9361_tx_switch_d2) begin
+if (CAL_MOD_FINE == 1) begin
+        tx_ch1_i_buf <= tx_pn_i >>> bb_rshift;
+        tx_ch1_q_buf <= tx_pn_q >>> bb_rshift;
+        tx_ch2_i_buf <= tx_pn_i >>> bb_rshift;
+        tx_ch2_q_buf <= tx_pn_q >>> bb_rshift;
+end // CAL_MOD_FINE == 1
+else begin
+        tx_ch1_i_buf <= tx_dc_i >>> bb_rshift;
+        tx_ch1_q_buf <= tx_dc_q >>> bb_rshift;
+        tx_ch2_i_buf <= tx_dc_i >>> bb_rshift;
+        tx_ch2_q_buf <= tx_dc_q >>> bb_rshift;
+end // CAL_MOD_FINE != 1
+    end
+    else begin
+        tx_ch1_i_buf <= tx_data_ch1_i;
+        tx_ch1_q_buf <= tx_data_ch1_q;
+        tx_ch2_i_buf <= tx_data_ch2_i;
+        tx_ch2_q_buf <= tx_data_ch2_q;
+    end
+end
+
+endmodule