Archived
finish coding and testing of online acq; add sample data
串行在线捕获程序已经完成编写,并进行了仿真和测试(对飞和814均可用);增加了在电子所使用转台测试的幅相采集数据
This commit is contained in:
@@ -0,0 +1,83 @@
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MEMORY_INITIALIZATION_RADIX = 10;
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MEMORY_INITIALIZATION_VECTOR =
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1624,
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1611,
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1598,
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948,
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883,
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BIN
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-532
@@ -1,532 +0,0 @@
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// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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||||||
// laws.
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||||||
//
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||||||
// DISCLAIMER
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||||||
// This disclaimer is not a license and does not grant any
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||||||
// rights to the materials distributed herewith. Except as
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||||||
// otherwise provided in a valid license issued to you by
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||||||
// Xilinx, and to the maximum extent permitted by applicable
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||||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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||||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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||||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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||||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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||||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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||||||
// including negligence, or under any other theory of
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||||||
// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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||||||
// reasonably foreseeable or Xilinx had been advised of the
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||||||
// possibility of the same.
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||||||
//
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||||||
// CRITICAL APPLICATIONS
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||||||
// Xilinx products are not designed or intended to be fail-
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||||||
// safe, or for use in any application requiring fail-safe
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||||||
// performance, such as life-support or safety devices or
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||||||
// systems, Class III medical devices, nuclear facilities,
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||||||
// applications related to the deployment of airbags, or any
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||||||
// other applications that could lead to death, personal
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||||||
// injury, or severe property or environmental damage
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|
||||||
// (individually and collectively, "Critical
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|
||||||
// Applications"). Customer assumes the sole risk and
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|
||||||
// liability of any use of Xilinx products in Critical
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||||||
// Applications, subject only to applicable laws and
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|
||||||
// regulations governing limitations on product liability.
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||||||
//
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||||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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||||||
// PART OF THIS FILE AT ALL TIMES.
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//
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// DO NOT MODIFY THIS FILE.
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// IP VLNV: xilinx.com:ip:fifo_generator:13.2
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// IP Revision: 4
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`timescale 1ns/1ps
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(* DowngradeIPIdentifiedWarnings = "yes" *)
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module fifo_48m_to_122p88m (
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wr_rst_busy,
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rd_rst_busy,
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m_aclk,
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s_aclk,
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s_aresetn,
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s_axis_tvalid,
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s_axis_tready,
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s_axis_tdata,
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m_axis_tvalid,
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m_axis_tready,
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m_axis_tdata
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);
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output wire wr_rst_busy;
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output wire rd_rst_busy;
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||||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME master_aclk, ASSOCIATED_BUSIF M_AXIS:M_AXI, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0" *)
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(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 master_aclk CLK" *)
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input wire m_aclk;
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(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME slave_aclk, ASSOCIATED_BUSIF S_AXIS:S_AXI, ASSOCIATED_RESET s_aresetn, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0" *)
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(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 slave_aclk CLK" *)
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||||||
input wire s_aclk;
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||||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME slave_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
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||||||
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 slave_aresetn RST" *)
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input wire s_aresetn;
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(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TVALID" *)
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input wire s_axis_tvalid;
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(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TREADY" *)
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output wire s_axis_tready;
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(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0" *)
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(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS TDATA" *)
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input wire [15 : 0] s_axis_tdata;
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(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TVALID" *)
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output wire m_axis_tvalid;
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(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TREADY" *)
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input wire m_axis_tready;
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||||||
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0" *)
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(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS TDATA" *)
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output wire [15 : 0] m_axis_tdata;
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fifo_generator_v13_2_4 #(
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.C_COMMON_CLOCK(0),
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.C_SELECT_XPM(0),
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.C_COUNT_TYPE(0),
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.C_DATA_COUNT_WIDTH(10),
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.C_DEFAULT_VALUE("BlankString"),
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.C_DIN_WIDTH(18),
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.C_DOUT_RST_VAL("0"),
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||||||
.C_DOUT_WIDTH(18),
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||||||
.C_ENABLE_RLOCS(0),
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.C_FAMILY("zynq"),
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|
||||||
.C_FULL_FLAGS_RST_VAL(1),
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|
||||||
.C_HAS_ALMOST_EMPTY(0),
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|
||||||
.C_HAS_ALMOST_FULL(0),
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|
||||||
.C_HAS_BACKUP(0),
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|
||||||
.C_HAS_DATA_COUNT(0),
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|
||||||
.C_HAS_INT_CLK(0),
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|
||||||
.C_HAS_MEMINIT_FILE(0),
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|
||||||
.C_HAS_OVERFLOW(0),
|
|
||||||
.C_HAS_RD_DATA_COUNT(0),
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|
||||||
.C_HAS_RD_RST(0),
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||||||
.C_HAS_RST(1),
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||||||
.C_HAS_SRST(0),
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||||||
.C_HAS_UNDERFLOW(0),
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||||||
.C_HAS_VALID(0),
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||||||
.C_HAS_WR_ACK(0),
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||||||
.C_HAS_WR_DATA_COUNT(0),
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||||||
.C_HAS_WR_RST(0),
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||||||
.C_IMPLEMENTATION_TYPE(0),
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||||||
.C_INIT_WR_PNTR_VAL(0),
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||||||
.C_MEMORY_TYPE(1),
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.C_MIF_FILE_NAME("BlankString"),
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||||||
.C_OPTIMIZATION_MODE(0),
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||||||
.C_OVERFLOW_LOW(0),
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.C_PRELOAD_LATENCY(1),
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.C_PRELOAD_REGS(0),
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||||||
.C_PRIM_FIFO_TYPE("4kx4"),
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||||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
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||||||
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
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||||||
.C_PROG_EMPTY_TYPE(0),
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.C_PROG_FULL_THRESH_ASSERT_VAL(1022),
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||||||
.C_PROG_FULL_THRESH_NEGATE_VAL(1021),
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||||||
.C_PROG_FULL_TYPE(0),
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|
||||||
.C_RD_DATA_COUNT_WIDTH(10),
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.C_RD_DEPTH(1024),
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.C_RD_FREQ(1),
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.C_RD_PNTR_WIDTH(10),
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.C_UNDERFLOW_LOW(0),
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||||||
.C_USE_DOUT_RST(1),
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.C_USE_ECC(0),
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.C_USE_EMBEDDED_REG(0),
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||||||
.C_USE_PIPELINE_REG(0),
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||||||
.C_POWER_SAVING_MODE(0),
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||||||
.C_USE_FIFO16_FLAGS(0),
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.C_USE_FWFT_DATA_COUNT(0),
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||||||
.C_VALID_LOW(0),
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.C_WR_ACK_LOW(0),
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||||||
.C_WR_DATA_COUNT_WIDTH(10),
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.C_WR_DEPTH(1024),
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.C_WR_FREQ(1),
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.C_WR_PNTR_WIDTH(10),
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.C_WR_RESPONSE_LATENCY(1),
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.C_MSGON_VAL(1),
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||||||
.C_ENABLE_RST_SYNC(1),
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||||||
.C_EN_SAFETY_CKT(1),
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.C_ERROR_INJECTION_TYPE(0),
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.C_SYNCHRONIZER_STAGE(2),
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.C_INTERFACE_TYPE(1),
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.C_AXI_TYPE(1),
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.C_HAS_AXI_WR_CHANNEL(1),
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.C_HAS_AXI_RD_CHANNEL(1),
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||||||
.C_HAS_SLAVE_CE(0),
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.C_HAS_MASTER_CE(0),
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||||||
.C_ADD_NGC_CONSTRAINT(0),
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.C_USE_COMMON_OVERFLOW(0),
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.C_USE_COMMON_UNDERFLOW(0),
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.C_USE_DEFAULT_SETTINGS(0),
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.C_AXI_ID_WIDTH(1),
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||||||
.C_AXI_ADDR_WIDTH(32),
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||||||
.C_AXI_DATA_WIDTH(64),
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||||||
.C_AXI_LEN_WIDTH(8),
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||||||
.C_AXI_LOCK_WIDTH(1),
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||||||
.C_HAS_AXI_ID(0),
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.C_HAS_AXI_AWUSER(0),
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||||||
.C_HAS_AXI_WUSER(0),
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||||||
.C_HAS_AXI_BUSER(0),
|
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||||||
.C_HAS_AXI_ARUSER(0),
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||||||
.C_HAS_AXI_RUSER(0),
|
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||||||
.C_AXI_ARUSER_WIDTH(1),
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||||||
.C_AXI_AWUSER_WIDTH(1),
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||||||
.C_AXI_WUSER_WIDTH(1),
|
|
||||||
.C_AXI_BUSER_WIDTH(1),
|
|
||||||
.C_AXI_RUSER_WIDTH(1),
|
|
||||||
.C_HAS_AXIS_TDATA(1),
|
|
||||||
.C_HAS_AXIS_TID(0),
|
|
||||||
.C_HAS_AXIS_TDEST(0),
|
|
||||||
.C_HAS_AXIS_TUSER(0),
|
|
||||||
.C_HAS_AXIS_TREADY(1),
|
|
||||||
.C_HAS_AXIS_TLAST(0),
|
|
||||||
.C_HAS_AXIS_TSTRB(0),
|
|
||||||
.C_HAS_AXIS_TKEEP(0),
|
|
||||||
.C_AXIS_TDATA_WIDTH(16),
|
|
||||||
.C_AXIS_TID_WIDTH(1),
|
|
||||||
.C_AXIS_TDEST_WIDTH(1),
|
|
||||||
.C_AXIS_TUSER_WIDTH(1),
|
|
||||||
.C_AXIS_TSTRB_WIDTH(2),
|
|
||||||
.C_AXIS_TKEEP_WIDTH(2),
|
|
||||||
.C_WACH_TYPE(0),
|
|
||||||
.C_WDCH_TYPE(0),
|
|
||||||
.C_WRCH_TYPE(0),
|
|
||||||
.C_RACH_TYPE(0),
|
|
||||||
.C_RDCH_TYPE(0),
|
|
||||||
.C_AXIS_TYPE(0),
|
|
||||||
.C_IMPLEMENTATION_TYPE_WACH(12),
|
|
||||||
.C_IMPLEMENTATION_TYPE_WDCH(11),
|
|
||||||
.C_IMPLEMENTATION_TYPE_WRCH(12),
|
|
||||||
.C_IMPLEMENTATION_TYPE_RACH(12),
|
|
||||||
.C_IMPLEMENTATION_TYPE_RDCH(11),
|
|
||||||
.C_IMPLEMENTATION_TYPE_AXIS(12),
|
|
||||||
.C_APPLICATION_TYPE_WACH(0),
|
|
||||||
.C_APPLICATION_TYPE_WDCH(0),
|
|
||||||
.C_APPLICATION_TYPE_WRCH(0),
|
|
||||||
.C_APPLICATION_TYPE_RACH(0),
|
|
||||||
.C_APPLICATION_TYPE_RDCH(0),
|
|
||||||
.C_APPLICATION_TYPE_AXIS(0),
|
|
||||||
.C_PRIM_FIFO_TYPE_WACH("512x36"),
|
|
||||||
.C_PRIM_FIFO_TYPE_WDCH("1kx36"),
|
|
||||||
.C_PRIM_FIFO_TYPE_WRCH("512x36"),
|
|
||||||
.C_PRIM_FIFO_TYPE_RACH("512x36"),
|
|
||||||
.C_PRIM_FIFO_TYPE_RDCH("1kx36"),
|
|
||||||
.C_PRIM_FIFO_TYPE_AXIS("512x36"),
|
|
||||||
.C_USE_ECC_WACH(0),
|
|
||||||
.C_USE_ECC_WDCH(0),
|
|
||||||
.C_USE_ECC_WRCH(0),
|
|
||||||
.C_USE_ECC_RACH(0),
|
|
||||||
.C_USE_ECC_RDCH(0),
|
|
||||||
.C_USE_ECC_AXIS(0),
|
|
||||||
.C_ERROR_INJECTION_TYPE_WACH(0),
|
|
||||||
.C_ERROR_INJECTION_TYPE_WDCH(0),
|
|
||||||
.C_ERROR_INJECTION_TYPE_WRCH(0),
|
|
||||||
.C_ERROR_INJECTION_TYPE_RACH(0),
|
|
||||||
.C_ERROR_INJECTION_TYPE_RDCH(0),
|
|
||||||
.C_ERROR_INJECTION_TYPE_AXIS(0),
|
|
||||||
.C_DIN_WIDTH_WACH(32),
|
|
||||||
.C_DIN_WIDTH_WDCH(64),
|
|
||||||
.C_DIN_WIDTH_WRCH(2),
|
|
||||||
.C_DIN_WIDTH_RACH(32),
|
|
||||||
.C_DIN_WIDTH_RDCH(64),
|
|
||||||
.C_DIN_WIDTH_AXIS(16),
|
|
||||||
.C_WR_DEPTH_WACH(16),
|
|
||||||
.C_WR_DEPTH_WDCH(1024),
|
|
||||||
.C_WR_DEPTH_WRCH(16),
|
|
||||||
.C_WR_DEPTH_RACH(16),
|
|
||||||
.C_WR_DEPTH_RDCH(1024),
|
|
||||||
.C_WR_DEPTH_AXIS(16),
|
|
||||||
.C_WR_PNTR_WIDTH_WACH(4),
|
|
||||||
.C_WR_PNTR_WIDTH_WDCH(10),
|
|
||||||
.C_WR_PNTR_WIDTH_WRCH(4),
|
|
||||||
.C_WR_PNTR_WIDTH_RACH(4),
|
|
||||||
.C_WR_PNTR_WIDTH_RDCH(10),
|
|
||||||
.C_WR_PNTR_WIDTH_AXIS(4),
|
|
||||||
.C_HAS_DATA_COUNTS_WACH(0),
|
|
||||||
.C_HAS_DATA_COUNTS_WDCH(0),
|
|
||||||
.C_HAS_DATA_COUNTS_WRCH(0),
|
|
||||||
.C_HAS_DATA_COUNTS_RACH(0),
|
|
||||||
.C_HAS_DATA_COUNTS_RDCH(0),
|
|
||||||
.C_HAS_DATA_COUNTS_AXIS(0),
|
|
||||||
.C_HAS_PROG_FLAGS_WACH(0),
|
|
||||||
.C_HAS_PROG_FLAGS_WDCH(0),
|
|
||||||
.C_HAS_PROG_FLAGS_WRCH(0),
|
|
||||||
.C_HAS_PROG_FLAGS_RACH(0),
|
|
||||||
.C_HAS_PROG_FLAGS_RDCH(0),
|
|
||||||
.C_HAS_PROG_FLAGS_AXIS(0),
|
|
||||||
.C_PROG_FULL_TYPE_WACH(0),
|
|
||||||
.C_PROG_FULL_TYPE_WDCH(0),
|
|
||||||
.C_PROG_FULL_TYPE_WRCH(0),
|
|
||||||
.C_PROG_FULL_TYPE_RACH(0),
|
|
||||||
.C_PROG_FULL_TYPE_RDCH(0),
|
|
||||||
.C_PROG_FULL_TYPE_AXIS(0),
|
|
||||||
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(15),
|
|
||||||
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
|
|
||||||
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(15),
|
|
||||||
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(15),
|
|
||||||
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
|
|
||||||
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(15),
|
|
||||||
.C_PROG_EMPTY_TYPE_WACH(0),
|
|
||||||
.C_PROG_EMPTY_TYPE_WDCH(0),
|
|
||||||
.C_PROG_EMPTY_TYPE_WRCH(0),
|
|
||||||
.C_PROG_EMPTY_TYPE_RACH(0),
|
|
||||||
.C_PROG_EMPTY_TYPE_RDCH(0),
|
|
||||||
.C_PROG_EMPTY_TYPE_AXIS(0),
|
|
||||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(13),
|
|
||||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1021),
|
|
||||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(13),
|
|
||||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(13),
|
|
||||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1021),
|
|
||||||
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(13),
|
|
||||||
.C_REG_SLICE_MODE_WACH(0),
|
|
||||||
.C_REG_SLICE_MODE_WDCH(0),
|
|
||||||
.C_REG_SLICE_MODE_WRCH(0),
|
|
||||||
.C_REG_SLICE_MODE_RACH(0),
|
|
||||||
.C_REG_SLICE_MODE_RDCH(0),
|
|
||||||
.C_REG_SLICE_MODE_AXIS(0)
|
|
||||||
) inst (
|
|
||||||
.backup(1'D0),
|
|
||||||
.backup_marker(1'D0),
|
|
||||||
.clk(1'D0),
|
|
||||||
.rst(1'D0),
|
|
||||||
.srst(1'D0),
|
|
||||||
.wr_clk(1'D0),
|
|
||||||
.wr_rst(1'D0),
|
|
||||||
.rd_clk(1'D0),
|
|
||||||
.rd_rst(1'D0),
|
|
||||||
.din(18'B0),
|
|
||||||
.wr_en(1'D0),
|
|
||||||
.rd_en(1'D0),
|
|
||||||
.prog_empty_thresh(10'B0),
|
|
||||||
.prog_empty_thresh_assert(10'B0),
|
|
||||||
.prog_empty_thresh_negate(10'B0),
|
|
||||||
.prog_full_thresh(10'B0),
|
|
||||||
.prog_full_thresh_assert(10'B0),
|
|
||||||
.prog_full_thresh_negate(10'B0),
|
|
||||||
.int_clk(1'D0),
|
|
||||||
.injectdbiterr(1'D0),
|
|
||||||
.injectsbiterr(1'D0),
|
|
||||||
.sleep(1'D0),
|
|
||||||
.dout(),
|
|
||||||
.full(),
|
|
||||||
.almost_full(),
|
|
||||||
.wr_ack(),
|
|
||||||
.overflow(),
|
|
||||||
.empty(),
|
|
||||||
.almost_empty(),
|
|
||||||
.valid(),
|
|
||||||
.underflow(),
|
|
||||||
.data_count(),
|
|
||||||
.rd_data_count(),
|
|
||||||
.wr_data_count(),
|
|
||||||
.prog_full(),
|
|
||||||
.prog_empty(),
|
|
||||||
.sbiterr(),
|
|
||||||
.dbiterr(),
|
|
||||||
.wr_rst_busy(wr_rst_busy),
|
|
||||||
.rd_rst_busy(rd_rst_busy),
|
|
||||||
.m_aclk(m_aclk),
|
|
||||||
.s_aclk(s_aclk),
|
|
||||||
.s_aresetn(s_aresetn),
|
|
||||||
.m_aclk_en(1'D0),
|
|
||||||
.s_aclk_en(1'D0),
|
|
||||||
.s_axi_awid(1'B0),
|
|
||||||
.s_axi_awaddr(32'B0),
|
|
||||||
.s_axi_awlen(8'B0),
|
|
||||||
.s_axi_awsize(3'B0),
|
|
||||||
.s_axi_awburst(2'B0),
|
|
||||||
.s_axi_awlock(1'B0),
|
|
||||||
.s_axi_awcache(4'B0),
|
|
||||||
.s_axi_awprot(3'B0),
|
|
||||||
.s_axi_awqos(4'B0),
|
|
||||||
.s_axi_awregion(4'B0),
|
|
||||||
.s_axi_awuser(1'B0),
|
|
||||||
.s_axi_awvalid(1'D0),
|
|
||||||
.s_axi_awready(),
|
|
||||||
.s_axi_wid(1'B0),
|
|
||||||
.s_axi_wdata(64'B0),
|
|
||||||
.s_axi_wstrb(8'B0),
|
|
||||||
.s_axi_wlast(1'D0),
|
|
||||||
.s_axi_wuser(1'B0),
|
|
||||||
.s_axi_wvalid(1'D0),
|
|
||||||
.s_axi_wready(),
|
|
||||||
.s_axi_bid(),
|
|
||||||
.s_axi_bresp(),
|
|
||||||
.s_axi_buser(),
|
|
||||||
.s_axi_bvalid(),
|
|
||||||
.s_axi_bready(1'D0),
|
|
||||||
.m_axi_awid(),
|
|
||||||
.m_axi_awaddr(),
|
|
||||||
.m_axi_awlen(),
|
|
||||||
.m_axi_awsize(),
|
|
||||||
.m_axi_awburst(),
|
|
||||||
.m_axi_awlock(),
|
|
||||||
.m_axi_awcache(),
|
|
||||||
.m_axi_awprot(),
|
|
||||||
.m_axi_awqos(),
|
|
||||||
.m_axi_awregion(),
|
|
||||||
.m_axi_awuser(),
|
|
||||||
.m_axi_awvalid(),
|
|
||||||
.m_axi_awready(1'D0),
|
|
||||||
.m_axi_wid(),
|
|
||||||
.m_axi_wdata(),
|
|
||||||
.m_axi_wstrb(),
|
|
||||||
.m_axi_wlast(),
|
|
||||||
.m_axi_wuser(),
|
|
||||||
.m_axi_wvalid(),
|
|
||||||
.m_axi_wready(1'D0),
|
|
||||||
.m_axi_bid(1'B0),
|
|
||||||
.m_axi_bresp(2'B0),
|
|
||||||
.m_axi_buser(1'B0),
|
|
||||||
.m_axi_bvalid(1'D0),
|
|
||||||
.m_axi_bready(),
|
|
||||||
.s_axi_arid(1'B0),
|
|
||||||
.s_axi_araddr(32'B0),
|
|
||||||
.s_axi_arlen(8'B0),
|
|
||||||
.s_axi_arsize(3'B0),
|
|
||||||
.s_axi_arburst(2'B0),
|
|
||||||
.s_axi_arlock(1'B0),
|
|
||||||
.s_axi_arcache(4'B0),
|
|
||||||
.s_axi_arprot(3'B0),
|
|
||||||
.s_axi_arqos(4'B0),
|
|
||||||
.s_axi_arregion(4'B0),
|
|
||||||
.s_axi_aruser(1'B0),
|
|
||||||
.s_axi_arvalid(1'D0),
|
|
||||||
.s_axi_arready(),
|
|
||||||
.s_axi_rid(),
|
|
||||||
.s_axi_rdata(),
|
|
||||||
.s_axi_rresp(),
|
|
||||||
.s_axi_rlast(),
|
|
||||||
.s_axi_ruser(),
|
|
||||||
.s_axi_rvalid(),
|
|
||||||
.s_axi_rready(1'D0),
|
|
||||||
.m_axi_arid(),
|
|
||||||
.m_axi_araddr(),
|
|
||||||
.m_axi_arlen(),
|
|
||||||
.m_axi_arsize(),
|
|
||||||
.m_axi_arburst(),
|
|
||||||
.m_axi_arlock(),
|
|
||||||
.m_axi_arcache(),
|
|
||||||
.m_axi_arprot(),
|
|
||||||
.m_axi_arqos(),
|
|
||||||
.m_axi_arregion(),
|
|
||||||
.m_axi_aruser(),
|
|
||||||
.m_axi_arvalid(),
|
|
||||||
.m_axi_arready(1'D0),
|
|
||||||
.m_axi_rid(1'B0),
|
|
||||||
.m_axi_rdata(64'B0),
|
|
||||||
.m_axi_rresp(2'B0),
|
|
||||||
.m_axi_rlast(1'D0),
|
|
||||||
.m_axi_ruser(1'B0),
|
|
||||||
.m_axi_rvalid(1'D0),
|
|
||||||
.m_axi_rready(),
|
|
||||||
.s_axis_tvalid(s_axis_tvalid),
|
|
||||||
.s_axis_tready(s_axis_tready),
|
|
||||||
.s_axis_tdata(s_axis_tdata),
|
|
||||||
.s_axis_tstrb(2'B0),
|
|
||||||
.s_axis_tkeep(2'B0),
|
|
||||||
.s_axis_tlast(1'D0),
|
|
||||||
.s_axis_tid(1'B0),
|
|
||||||
.s_axis_tdest(1'B0),
|
|
||||||
.s_axis_tuser(1'B0),
|
|
||||||
.m_axis_tvalid(m_axis_tvalid),
|
|
||||||
.m_axis_tready(m_axis_tready),
|
|
||||||
.m_axis_tdata(m_axis_tdata),
|
|
||||||
.m_axis_tstrb(),
|
|
||||||
.m_axis_tkeep(),
|
|
||||||
.m_axis_tlast(),
|
|
||||||
.m_axis_tid(),
|
|
||||||
.m_axis_tdest(),
|
|
||||||
.m_axis_tuser(),
|
|
||||||
.axi_aw_injectsbiterr(1'D0),
|
|
||||||
.axi_aw_injectdbiterr(1'D0),
|
|
||||||
.axi_aw_prog_full_thresh(4'B0),
|
|
||||||
.axi_aw_prog_empty_thresh(4'B0),
|
|
||||||
.axi_aw_data_count(),
|
|
||||||
.axi_aw_wr_data_count(),
|
|
||||||
.axi_aw_rd_data_count(),
|
|
||||||
.axi_aw_sbiterr(),
|
|
||||||
.axi_aw_dbiterr(),
|
|
||||||
.axi_aw_overflow(),
|
|
||||||
.axi_aw_underflow(),
|
|
||||||
.axi_aw_prog_full(),
|
|
||||||
.axi_aw_prog_empty(),
|
|
||||||
.axi_w_injectsbiterr(1'D0),
|
|
||||||
.axi_w_injectdbiterr(1'D0),
|
|
||||||
.axi_w_prog_full_thresh(10'B0),
|
|
||||||
.axi_w_prog_empty_thresh(10'B0),
|
|
||||||
.axi_w_data_count(),
|
|
||||||
.axi_w_wr_data_count(),
|
|
||||||
.axi_w_rd_data_count(),
|
|
||||||
.axi_w_sbiterr(),
|
|
||||||
.axi_w_dbiterr(),
|
|
||||||
.axi_w_overflow(),
|
|
||||||
.axi_w_underflow(),
|
|
||||||
.axi_w_prog_full(),
|
|
||||||
.axi_w_prog_empty(),
|
|
||||||
.axi_b_injectsbiterr(1'D0),
|
|
||||||
.axi_b_injectdbiterr(1'D0),
|
|
||||||
.axi_b_prog_full_thresh(4'B0),
|
|
||||||
.axi_b_prog_empty_thresh(4'B0),
|
|
||||||
.axi_b_data_count(),
|
|
||||||
.axi_b_wr_data_count(),
|
|
||||||
.axi_b_rd_data_count(),
|
|
||||||
.axi_b_sbiterr(),
|
|
||||||
.axi_b_dbiterr(),
|
|
||||||
.axi_b_overflow(),
|
|
||||||
.axi_b_underflow(),
|
|
||||||
.axi_b_prog_full(),
|
|
||||||
.axi_b_prog_empty(),
|
|
||||||
.axi_ar_injectsbiterr(1'D0),
|
|
||||||
.axi_ar_injectdbiterr(1'D0),
|
|
||||||
.axi_ar_prog_full_thresh(4'B0),
|
|
||||||
.axi_ar_prog_empty_thresh(4'B0),
|
|
||||||
.axi_ar_data_count(),
|
|
||||||
.axi_ar_wr_data_count(),
|
|
||||||
.axi_ar_rd_data_count(),
|
|
||||||
.axi_ar_sbiterr(),
|
|
||||||
.axi_ar_dbiterr(),
|
|
||||||
.axi_ar_overflow(),
|
|
||||||
.axi_ar_underflow(),
|
|
||||||
.axi_ar_prog_full(),
|
|
||||||
.axi_ar_prog_empty(),
|
|
||||||
.axi_r_injectsbiterr(1'D0),
|
|
||||||
.axi_r_injectdbiterr(1'D0),
|
|
||||||
.axi_r_prog_full_thresh(10'B0),
|
|
||||||
.axi_r_prog_empty_thresh(10'B0),
|
|
||||||
.axi_r_data_count(),
|
|
||||||
.axi_r_wr_data_count(),
|
|
||||||
.axi_r_rd_data_count(),
|
|
||||||
.axi_r_sbiterr(),
|
|
||||||
.axi_r_dbiterr(),
|
|
||||||
.axi_r_overflow(),
|
|
||||||
.axi_r_underflow(),
|
|
||||||
.axi_r_prog_full(),
|
|
||||||
.axi_r_prog_empty(),
|
|
||||||
.axis_injectsbiterr(1'D0),
|
|
||||||
.axis_injectdbiterr(1'D0),
|
|
||||||
.axis_prog_full_thresh(4'B0),
|
|
||||||
.axis_prog_empty_thresh(4'B0),
|
|
||||||
.axis_data_count(),
|
|
||||||
.axis_wr_data_count(),
|
|
||||||
.axis_rd_data_count(),
|
|
||||||
.axis_sbiterr(),
|
|
||||||
.axis_dbiterr(),
|
|
||||||
.axis_overflow(),
|
|
||||||
.axis_underflow(),
|
|
||||||
.axis_prog_full(),
|
|
||||||
.axis_prog_empty()
|
|
||||||
);
|
|
||||||
endmodule
|
|
||||||
BIN
Binary file not shown.
BIN
Binary file not shown.
+5
-5
@@ -54,14 +54,14 @@
|
|||||||
// (in parentheses) to your own signal names.
|
// (in parentheses) to your own signal names.
|
||||||
|
|
||||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||||
rom_hop_data your_instance_name (
|
rom_freq_word your_instance_name (
|
||||||
.clka(clka), // input wire clka
|
.clka(clka), // input wire clka
|
||||||
.addra(addra), // input wire [13 : 0] addra
|
.addra(addra), // input wire [6 : 0] addra
|
||||||
.douta(douta) // output wire [95 : 0] douta
|
.douta(douta) // output wire [10 : 0] douta
|
||||||
);
|
);
|
||||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||||
|
|
||||||
// You must compile the wrapper file rom_hop_data.v when simulating
|
// You must compile the wrapper file rom_freq_word.v when simulating
|
||||||
// the core, rom_hop_data. When compiling the wrapper file, be sure to
|
// the core, rom_freq_word. When compiling the wrapper file, be sure to
|
||||||
// reference the Verilog simulation library.
|
// reference the Verilog simulation library.
|
||||||
|
|
||||||
+6
-6
@@ -52,11 +52,11 @@
|
|||||||
-- The following code must appear in the VHDL architecture header.
|
-- The following code must appear in the VHDL architecture header.
|
||||||
|
|
||||||
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||||
COMPONENT rom_hop_data
|
COMPONENT rom_freq_word
|
||||||
PORT (
|
PORT (
|
||||||
clka : IN STD_LOGIC;
|
clka : IN STD_LOGIC;
|
||||||
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
|
addra : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
|
||||||
douta : OUT STD_LOGIC_VECTOR(95 DOWNTO 0)
|
douta : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
|
||||||
);
|
);
|
||||||
END COMPONENT;
|
END COMPONENT;
|
||||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||||
@@ -65,7 +65,7 @@ END COMPONENT;
|
|||||||
-- body. Substitute your own instance name and net names.
|
-- body. Substitute your own instance name and net names.
|
||||||
|
|
||||||
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||||
your_instance_name : rom_hop_data
|
your_instance_name : rom_freq_word
|
||||||
PORT MAP (
|
PORT MAP (
|
||||||
clka => clka,
|
clka => clka,
|
||||||
addra => addra,
|
addra => addra,
|
||||||
@@ -73,7 +73,7 @@ your_instance_name : rom_hop_data
|
|||||||
);
|
);
|
||||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||||
|
|
||||||
-- You must compile the wrapper file rom_hop_data.vhd when simulating
|
-- You must compile the wrapper file rom_freq_word.vhd when simulating
|
||||||
-- the core, rom_hop_data. When compiling the wrapper file, be sure to
|
-- the core, rom_freq_word. When compiling the wrapper file, be sure to
|
||||||
-- reference the VHDL simulation library.
|
-- reference the VHDL simulation library.
|
||||||
|
|
||||||
BIN
Binary file not shown.
BIN
Binary file not shown.
@@ -0,0 +1,22 @@
|
|||||||
|
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||||
|
// Date : Mon May 8 18:56:10 2023
|
||||||
|
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||||
|
// Command : write_verilog -force -mode synth_stub
|
||||||
|
// /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v
|
||||||
|
// Design : rom_freq_word
|
||||||
|
// Purpose : Stub declaration of top-level module interface
|
||||||
|
// Device : xc7z100ffg900-2
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||||
|
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||||
|
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||||
|
(* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *)
|
||||||
|
module rom_freq_word(clka, addra, douta)
|
||||||
|
/* synthesis syn_black_box black_box_pad_pin="clka,addra[6:0],douta[10:0]" */;
|
||||||
|
input clka;
|
||||||
|
input [6:0]addra;
|
||||||
|
output [10:0]douta;
|
||||||
|
endmodule
|
||||||
+32
@@ -0,0 +1,32 @@
|
|||||||
|
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
-- --------------------------------------------------------------------------------
|
||||||
|
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||||
|
-- Date : Mon May 8 18:56:10 2023
|
||||||
|
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||||
|
-- Command : write_vhdl -force -mode synth_stub
|
||||||
|
-- /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl
|
||||||
|
-- Design : rom_freq_word
|
||||||
|
-- Purpose : Stub declaration of top-level module interface
|
||||||
|
-- Device : xc7z100ffg900-2
|
||||||
|
-- --------------------------------------------------------------------------------
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
|
||||||
|
entity rom_freq_word is
|
||||||
|
Port (
|
||||||
|
clka : in STD_LOGIC;
|
||||||
|
addra : in STD_LOGIC_VECTOR ( 6 downto 0 );
|
||||||
|
douta : out STD_LOGIC_VECTOR ( 10 downto 0 )
|
||||||
|
);
|
||||||
|
|
||||||
|
end rom_freq_word;
|
||||||
|
|
||||||
|
architecture stub of rom_freq_word is
|
||||||
|
attribute syn_black_box : boolean;
|
||||||
|
attribute black_box_pad_pin : string;
|
||||||
|
attribute syn_black_box of stub : architecture is true;
|
||||||
|
attribute black_box_pad_pin of stub : architecture is "clka,addra[6:0],douta[10:0]";
|
||||||
|
attribute x_core_info : string;
|
||||||
|
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3";
|
||||||
|
begin
|
||||||
|
end;
|
||||||
@@ -0,0 +1,211 @@
|
|||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
|
||||||
|
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
|
||||||
|
// IP Revision: 3
|
||||||
|
|
||||||
|
`timescale 1ns/1ps
|
||||||
|
|
||||||
|
(* DowngradeIPIdentifiedWarnings = "yes" *)
|
||||||
|
module rom_freq_word (
|
||||||
|
clka,
|
||||||
|
addra,
|
||||||
|
douta
|
||||||
|
);
|
||||||
|
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
|
||||||
|
input wire clka;
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
|
||||||
|
input wire [6 : 0] addra;
|
||||||
|
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *)
|
||||||
|
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
|
||||||
|
output wire [10 : 0] douta;
|
||||||
|
|
||||||
|
blk_mem_gen_v8_4_3 #(
|
||||||
|
.C_FAMILY("zynq"),
|
||||||
|
.C_XDEVICEFAMILY("zynq"),
|
||||||
|
.C_ELABORATION_DIR("./"),
|
||||||
|
.C_INTERFACE_TYPE(0),
|
||||||
|
.C_AXI_TYPE(1),
|
||||||
|
.C_AXI_SLAVE_TYPE(0),
|
||||||
|
.C_USE_BRAM_BLOCK(0),
|
||||||
|
.C_ENABLE_32BIT_ADDRESS(0),
|
||||||
|
.C_CTRL_ECC_ALGO("NONE"),
|
||||||
|
.C_HAS_AXI_ID(0),
|
||||||
|
.C_AXI_ID_WIDTH(4),
|
||||||
|
.C_MEM_TYPE(3),
|
||||||
|
.C_BYTE_SIZE(9),
|
||||||
|
.C_ALGORITHM(1),
|
||||||
|
.C_PRIM_TYPE(1),
|
||||||
|
.C_LOAD_INIT_FILE(1),
|
||||||
|
.C_INIT_FILE_NAME("rom_freq_word.mif"),
|
||||||
|
.C_INIT_FILE("rom_freq_word.mem"),
|
||||||
|
.C_USE_DEFAULT_DATA(0),
|
||||||
|
.C_DEFAULT_DATA("0"),
|
||||||
|
.C_HAS_RSTA(0),
|
||||||
|
.C_RST_PRIORITY_A("CE"),
|
||||||
|
.C_RSTRAM_A(0),
|
||||||
|
.C_INITA_VAL("0"),
|
||||||
|
.C_HAS_ENA(0),
|
||||||
|
.C_HAS_REGCEA(0),
|
||||||
|
.C_USE_BYTE_WEA(0),
|
||||||
|
.C_WEA_WIDTH(1),
|
||||||
|
.C_WRITE_MODE_A("WRITE_FIRST"),
|
||||||
|
.C_WRITE_WIDTH_A(11),
|
||||||
|
.C_READ_WIDTH_A(11),
|
||||||
|
.C_WRITE_DEPTH_A(81),
|
||||||
|
.C_READ_DEPTH_A(81),
|
||||||
|
.C_ADDRA_WIDTH(7),
|
||||||
|
.C_HAS_RSTB(0),
|
||||||
|
.C_RST_PRIORITY_B("CE"),
|
||||||
|
.C_RSTRAM_B(0),
|
||||||
|
.C_INITB_VAL("0"),
|
||||||
|
.C_HAS_ENB(0),
|
||||||
|
.C_HAS_REGCEB(0),
|
||||||
|
.C_USE_BYTE_WEB(0),
|
||||||
|
.C_WEB_WIDTH(1),
|
||||||
|
.C_WRITE_MODE_B("WRITE_FIRST"),
|
||||||
|
.C_WRITE_WIDTH_B(11),
|
||||||
|
.C_READ_WIDTH_B(11),
|
||||||
|
.C_WRITE_DEPTH_B(81),
|
||||||
|
.C_READ_DEPTH_B(81),
|
||||||
|
.C_ADDRB_WIDTH(7),
|
||||||
|
.C_HAS_MEM_OUTPUT_REGS_A(1),
|
||||||
|
.C_HAS_MEM_OUTPUT_REGS_B(0),
|
||||||
|
.C_HAS_MUX_OUTPUT_REGS_A(0),
|
||||||
|
.C_HAS_MUX_OUTPUT_REGS_B(0),
|
||||||
|
.C_MUX_PIPELINE_STAGES(0),
|
||||||
|
.C_HAS_SOFTECC_INPUT_REGS_A(0),
|
||||||
|
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
|
||||||
|
.C_USE_SOFTECC(0),
|
||||||
|
.C_USE_ECC(0),
|
||||||
|
.C_EN_ECC_PIPE(0),
|
||||||
|
.C_READ_LATENCY_A(1),
|
||||||
|
.C_READ_LATENCY_B(1),
|
||||||
|
.C_HAS_INJECTERR(0),
|
||||||
|
.C_SIM_COLLISION_CHECK("ALL"),
|
||||||
|
.C_COMMON_CLK(0),
|
||||||
|
.C_DISABLE_WARN_BHV_COLL(0),
|
||||||
|
.C_EN_SLEEP_PIN(0),
|
||||||
|
.C_USE_URAM(0),
|
||||||
|
.C_EN_RDADDRA_CHG(0),
|
||||||
|
.C_EN_RDADDRB_CHG(0),
|
||||||
|
.C_EN_DEEPSLEEP_PIN(0),
|
||||||
|
.C_EN_SHUTDOWN_PIN(0),
|
||||||
|
.C_EN_SAFETY_CKT(0),
|
||||||
|
.C_DISABLE_WARN_BHV_RANGE(0),
|
||||||
|
.C_COUNT_36K_BRAM("0"),
|
||||||
|
.C_COUNT_18K_BRAM("1"),
|
||||||
|
.C_EST_POWER_SUMMARY("Estimated Power for IP : 2.5016 mW")
|
||||||
|
) inst (
|
||||||
|
.clka(clka),
|
||||||
|
.rsta(1'D0),
|
||||||
|
.ena(1'D0),
|
||||||
|
.regcea(1'D0),
|
||||||
|
.wea(1'B0),
|
||||||
|
.addra(addra),
|
||||||
|
.dina(11'B0),
|
||||||
|
.douta(douta),
|
||||||
|
.clkb(1'D0),
|
||||||
|
.rstb(1'D0),
|
||||||
|
.enb(1'D0),
|
||||||
|
.regceb(1'D0),
|
||||||
|
.web(1'B0),
|
||||||
|
.addrb(7'B0),
|
||||||
|
.dinb(11'B0),
|
||||||
|
.doutb(),
|
||||||
|
.injectsbiterr(1'D0),
|
||||||
|
.injectdbiterr(1'D0),
|
||||||
|
.eccpipece(1'D0),
|
||||||
|
.sbiterr(),
|
||||||
|
.dbiterr(),
|
||||||
|
.rdaddrecc(),
|
||||||
|
.sleep(1'D0),
|
||||||
|
.deepsleep(1'D0),
|
||||||
|
.shutdown(1'D0),
|
||||||
|
.rsta_busy(),
|
||||||
|
.rstb_busy(),
|
||||||
|
.s_aclk(1'H0),
|
||||||
|
.s_aresetn(1'D0),
|
||||||
|
.s_axi_awid(4'B0),
|
||||||
|
.s_axi_awaddr(32'B0),
|
||||||
|
.s_axi_awlen(8'B0),
|
||||||
|
.s_axi_awsize(3'B0),
|
||||||
|
.s_axi_awburst(2'B0),
|
||||||
|
.s_axi_awvalid(1'D0),
|
||||||
|
.s_axi_awready(),
|
||||||
|
.s_axi_wdata(11'B0),
|
||||||
|
.s_axi_wstrb(1'B0),
|
||||||
|
.s_axi_wlast(1'D0),
|
||||||
|
.s_axi_wvalid(1'D0),
|
||||||
|
.s_axi_wready(),
|
||||||
|
.s_axi_bid(),
|
||||||
|
.s_axi_bresp(),
|
||||||
|
.s_axi_bvalid(),
|
||||||
|
.s_axi_bready(1'D0),
|
||||||
|
.s_axi_arid(4'B0),
|
||||||
|
.s_axi_araddr(32'B0),
|
||||||
|
.s_axi_arlen(8'B0),
|
||||||
|
.s_axi_arsize(3'B0),
|
||||||
|
.s_axi_arburst(2'B0),
|
||||||
|
.s_axi_arvalid(1'D0),
|
||||||
|
.s_axi_arready(),
|
||||||
|
.s_axi_rid(),
|
||||||
|
.s_axi_rdata(),
|
||||||
|
.s_axi_rresp(),
|
||||||
|
.s_axi_rlast(),
|
||||||
|
.s_axi_rvalid(),
|
||||||
|
.s_axi_rready(1'D0),
|
||||||
|
.s_axi_injectsbiterr(1'D0),
|
||||||
|
.s_axi_injectdbiterr(1'D0),
|
||||||
|
.s_axi_sbiterr(),
|
||||||
|
.s_axi_dbiterr(),
|
||||||
|
.s_axi_rdaddrecc()
|
||||||
|
);
|
||||||
|
endmodule
|
||||||
@@ -1,92 +0,0 @@
|
|||||||
|
|
||||||
// file: sig_clk_gen.v
|
|
||||||
//
|
|
||||||
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
|
||||||
//
|
|
||||||
// This file contains confidential and proprietary information
|
|
||||||
// of Xilinx, Inc. and is protected under U.S. and
|
|
||||||
// international copyright and other intellectual property
|
|
||||||
// laws.
|
|
||||||
//
|
|
||||||
// DISCLAIMER
|
|
||||||
// This disclaimer is not a license and does not grant any
|
|
||||||
// rights to the materials distributed herewith. Except as
|
|
||||||
// otherwise provided in a valid license issued to you by
|
|
||||||
// Xilinx, and to the maximum extent permitted by applicable
|
|
||||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
|
||||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
|
||||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
|
||||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
|
||||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
|
||||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
|
||||||
// including negligence, or under any other theory of
|
|
||||||
// liability) for any loss or damage of any kind or nature
|
|
||||||
// related to, arising under or in connection with these
|
|
||||||
// materials, including for any direct, or any indirect,
|
|
||||||
// special, incidental, or consequential loss or damage
|
|
||||||
// (including loss of data, profits, goodwill, or any type of
|
|
||||||
// loss or damage suffered as a result of any action brought
|
|
||||||
// by a third party) even if such damage or loss was
|
|
||||||
// reasonably foreseeable or Xilinx had been advised of the
|
|
||||||
// possibility of the same.
|
|
||||||
//
|
|
||||||
// CRITICAL APPLICATIONS
|
|
||||||
// Xilinx products are not designed or intended to be fail-
|
|
||||||
// safe, or for use in any application requiring fail-safe
|
|
||||||
// performance, such as life-support or safety devices or
|
|
||||||
// systems, Class III medical devices, nuclear facilities,
|
|
||||||
// applications related to the deployment of airbags, or any
|
|
||||||
// other applications that could lead to death, personal
|
|
||||||
// injury, or severe property or environmental damage
|
|
||||||
// (individually and collectively, "Critical
|
|
||||||
// Applications"). Customer assumes the sole risk and
|
|
||||||
// liability of any use of Xilinx products in Critical
|
|
||||||
// Applications, subject only to applicable laws and
|
|
||||||
// regulations governing limitations on product liability.
|
|
||||||
//
|
|
||||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
|
||||||
// PART OF THIS FILE AT ALL TIMES.
|
|
||||||
//
|
|
||||||
//----------------------------------------------------------------------------
|
|
||||||
// User entered comments
|
|
||||||
//----------------------------------------------------------------------------
|
|
||||||
// None
|
|
||||||
//
|
|
||||||
//----------------------------------------------------------------------------
|
|
||||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
|
||||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
|
||||||
//----------------------------------------------------------------------------
|
|
||||||
// clk_out1____48.000______0.000______50.0______172.739____111.288
|
|
||||||
//
|
|
||||||
//----------------------------------------------------------------------------
|
|
||||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
|
||||||
//----------------------------------------------------------------------------
|
|
||||||
// __primary__________122.88____________0.010
|
|
||||||
|
|
||||||
`timescale 1ps/1ps
|
|
||||||
|
|
||||||
(* CORE_GENERATION_INFO = "sig_clk_gen,clk_wiz_v6_0_3_0_0,{component_name=sig_clk_gen,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=8.138,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
|
|
||||||
|
|
||||||
module sig_clk_gen
|
|
||||||
(
|
|
||||||
// Clock out ports
|
|
||||||
output clk_out1,
|
|
||||||
// Status and control signals
|
|
||||||
input reset,
|
|
||||||
output locked,
|
|
||||||
// Clock in ports
|
|
||||||
input clk_in1
|
|
||||||
);
|
|
||||||
|
|
||||||
sig_clk_gen_clk_wiz inst
|
|
||||||
(
|
|
||||||
// Clock out ports
|
|
||||||
.clk_out1(clk_out1),
|
|
||||||
// Status and control signals
|
|
||||||
.reset(reset),
|
|
||||||
.locked(locked),
|
|
||||||
// Clock in ports
|
|
||||||
.clk_in1(clk_in1)
|
|
||||||
);
|
|
||||||
|
|
||||||
endmodule
|
|
||||||
@@ -1,204 +0,0 @@
|
|||||||
|
|
||||||
// file: sig_clk_gen.v
|
|
||||||
//
|
|
||||||
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
|
|
||||||
//
|
|
||||||
// This file contains confidential and proprietary information
|
|
||||||
// of Xilinx, Inc. and is protected under U.S. and
|
|
||||||
// international copyright and other intellectual property
|
|
||||||
// laws.
|
|
||||||
//
|
|
||||||
// DISCLAIMER
|
|
||||||
// This disclaimer is not a license and does not grant any
|
|
||||||
// rights to the materials distributed herewith. Except as
|
|
||||||
// otherwise provided in a valid license issued to you by
|
|
||||||
// Xilinx, and to the maximum extent permitted by applicable
|
|
||||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
|
||||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
|
||||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
|
||||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
|
||||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
|
||||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
|
||||||
// including negligence, or under any other theory of
|
|
||||||
// liability) for any loss or damage of any kind or nature
|
|
||||||
// related to, arising under or in connection with these
|
|
||||||
// materials, including for any direct, or any indirect,
|
|
||||||
// special, incidental, or consequential loss or damage
|
|
||||||
// (including loss of data, profits, goodwill, or any type of
|
|
||||||
// loss or damage suffered as a result of any action brought
|
|
||||||
// by a third party) even if such damage or loss was
|
|
||||||
// reasonably foreseeable or Xilinx had been advised of the
|
|
||||||
// possibility of the same.
|
|
||||||
//
|
|
||||||
// CRITICAL APPLICATIONS
|
|
||||||
// Xilinx products are not designed or intended to be fail-
|
|
||||||
// safe, or for use in any application requiring fail-safe
|
|
||||||
// performance, such as life-support or safety devices or
|
|
||||||
// systems, Class III medical devices, nuclear facilities,
|
|
||||||
// applications related to the deployment of airbags, or any
|
|
||||||
// other applications that could lead to death, personal
|
|
||||||
// injury, or severe property or environmental damage
|
|
||||||
// (individually and collectively, "Critical
|
|
||||||
// Applications"). Customer assumes the sole risk and
|
|
||||||
// liability of any use of Xilinx products in Critical
|
|
||||||
// Applications, subject only to applicable laws and
|
|
||||||
// regulations governing limitations on product liability.
|
|
||||||
//
|
|
||||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
|
||||||
// PART OF THIS FILE AT ALL TIMES.
|
|
||||||
//
|
|
||||||
//----------------------------------------------------------------------------
|
|
||||||
// User entered comments
|
|
||||||
//----------------------------------------------------------------------------
|
|
||||||
// None
|
|
||||||
//
|
|
||||||
//----------------------------------------------------------------------------
|
|
||||||
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
|
||||||
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
|
||||||
//----------------------------------------------------------------------------
|
|
||||||
// clk_out1____48.000______0.000______50.0______172.739____111.288
|
|
||||||
//
|
|
||||||
//----------------------------------------------------------------------------
|
|
||||||
// Input Clock Freq (MHz) Input Jitter (UI)
|
|
||||||
//----------------------------------------------------------------------------
|
|
||||||
// __primary__________122.88____________0.010
|
|
||||||
|
|
||||||
`timescale 1ps/1ps
|
|
||||||
|
|
||||||
module sig_clk_gen_clk_wiz
|
|
||||||
|
|
||||||
(// Clock in ports
|
|
||||||
// Clock out ports
|
|
||||||
output clk_out1,
|
|
||||||
// Status and control signals
|
|
||||||
input reset,
|
|
||||||
output locked,
|
|
||||||
input clk_in1
|
|
||||||
);
|
|
||||||
// Input buffering
|
|
||||||
//------------------------------------
|
|
||||||
wire clk_in1_sig_clk_gen;
|
|
||||||
wire clk_in2_sig_clk_gen;
|
|
||||||
BUFG clkin1_bufg
|
|
||||||
(.O (clk_in1_sig_clk_gen),
|
|
||||||
.I (clk_in1));
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
// Clocking PRIMITIVE
|
|
||||||
//------------------------------------
|
|
||||||
|
|
||||||
// Instantiation of the MMCM PRIMITIVE
|
|
||||||
// * Unused inputs are tied off
|
|
||||||
// * Unused outputs are labeled unused
|
|
||||||
|
|
||||||
wire clk_out1_sig_clk_gen;
|
|
||||||
wire clk_out2_sig_clk_gen;
|
|
||||||
wire clk_out3_sig_clk_gen;
|
|
||||||
wire clk_out4_sig_clk_gen;
|
|
||||||
wire clk_out5_sig_clk_gen;
|
|
||||||
wire clk_out6_sig_clk_gen;
|
|
||||||
wire clk_out7_sig_clk_gen;
|
|
||||||
|
|
||||||
wire [15:0] do_unused;
|
|
||||||
wire drdy_unused;
|
|
||||||
wire psdone_unused;
|
|
||||||
wire locked_int;
|
|
||||||
wire clkfbout_sig_clk_gen;
|
|
||||||
wire clkfbout_buf_sig_clk_gen;
|
|
||||||
wire clkfboutb_unused;
|
|
||||||
wire clkout0b_unused;
|
|
||||||
wire clkout1_unused;
|
|
||||||
wire clkout1b_unused;
|
|
||||||
wire clkout2_unused;
|
|
||||||
wire clkout2b_unused;
|
|
||||||
wire clkout3_unused;
|
|
||||||
wire clkout3b_unused;
|
|
||||||
wire clkout4_unused;
|
|
||||||
wire clkout5_unused;
|
|
||||||
wire clkout6_unused;
|
|
||||||
wire clkfbstopped_unused;
|
|
||||||
wire clkinstopped_unused;
|
|
||||||
wire reset_high;
|
|
||||||
|
|
||||||
MMCME2_ADV
|
|
||||||
#(.BANDWIDTH ("OPTIMIZED"),
|
|
||||||
.CLKOUT4_CASCADE ("FALSE"),
|
|
||||||
.COMPENSATION ("ZHOLD"),
|
|
||||||
.STARTUP_WAIT ("FALSE"),
|
|
||||||
.DIVCLK_DIVIDE (2),
|
|
||||||
.CLKFBOUT_MULT_F (15.625),
|
|
||||||
.CLKFBOUT_PHASE (0.000),
|
|
||||||
.CLKFBOUT_USE_FINE_PS ("FALSE"),
|
|
||||||
.CLKOUT0_DIVIDE_F (20.000),
|
|
||||||
.CLKOUT0_PHASE (0.000),
|
|
||||||
.CLKOUT0_DUTY_CYCLE (0.500),
|
|
||||||
.CLKOUT0_USE_FINE_PS ("FALSE"),
|
|
||||||
.CLKIN1_PERIOD (8.138))
|
|
||||||
mmcm_adv_inst
|
|
||||||
// Output clocks
|
|
||||||
(
|
|
||||||
.CLKFBOUT (clkfbout_sig_clk_gen),
|
|
||||||
.CLKFBOUTB (clkfboutb_unused),
|
|
||||||
.CLKOUT0 (clk_out1_sig_clk_gen),
|
|
||||||
.CLKOUT0B (clkout0b_unused),
|
|
||||||
.CLKOUT1 (clkout1_unused),
|
|
||||||
.CLKOUT1B (clkout1b_unused),
|
|
||||||
.CLKOUT2 (clkout2_unused),
|
|
||||||
.CLKOUT2B (clkout2b_unused),
|
|
||||||
.CLKOUT3 (clkout3_unused),
|
|
||||||
.CLKOUT3B (clkout3b_unused),
|
|
||||||
.CLKOUT4 (clkout4_unused),
|
|
||||||
.CLKOUT5 (clkout5_unused),
|
|
||||||
.CLKOUT6 (clkout6_unused),
|
|
||||||
// Input clock control
|
|
||||||
.CLKFBIN (clkfbout_buf_sig_clk_gen),
|
|
||||||
.CLKIN1 (clk_in1_sig_clk_gen),
|
|
||||||
.CLKIN2 (1'b0),
|
|
||||||
// Tied to always select the primary input clock
|
|
||||||
.CLKINSEL (1'b1),
|
|
||||||
// Ports for dynamic reconfiguration
|
|
||||||
.DADDR (7'h0),
|
|
||||||
.DCLK (1'b0),
|
|
||||||
.DEN (1'b0),
|
|
||||||
.DI (16'h0),
|
|
||||||
.DO (do_unused),
|
|
||||||
.DRDY (drdy_unused),
|
|
||||||
.DWE (1'b0),
|
|
||||||
// Ports for dynamic phase shift
|
|
||||||
.PSCLK (1'b0),
|
|
||||||
.PSEN (1'b0),
|
|
||||||
.PSINCDEC (1'b0),
|
|
||||||
.PSDONE (psdone_unused),
|
|
||||||
// Other control and status signals
|
|
||||||
.LOCKED (locked_int),
|
|
||||||
.CLKINSTOPPED (clkinstopped_unused),
|
|
||||||
.CLKFBSTOPPED (clkfbstopped_unused),
|
|
||||||
.PWRDWN (1'b0),
|
|
||||||
.RST (reset_high));
|
|
||||||
assign reset_high = reset;
|
|
||||||
|
|
||||||
assign locked = locked_int;
|
|
||||||
// Clock Monitor clock assigning
|
|
||||||
//--------------------------------------
|
|
||||||
// Output buffering
|
|
||||||
//-----------------------------------
|
|
||||||
|
|
||||||
BUFG clkf_buf
|
|
||||||
(.O (clkfbout_buf_sig_clk_gen),
|
|
||||||
.I (clkfbout_sig_clk_gen));
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
BUFG clkout1_buf
|
|
||||||
(.O (clk_out1),
|
|
||||||
.I (clk_out1_sig_clk_gen));
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
endmodule
|
|
||||||
BIN
Binary file not shown.
+68
@@ -0,0 +1,68 @@
|
|||||||
|
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
`timescale 1ns / 1ps
|
||||||
|
module vio_manual_ctrl (
|
||||||
|
clk,
|
||||||
|
|
||||||
|
probe_out0,
|
||||||
|
probe_out1,
|
||||||
|
probe_out2,
|
||||||
|
probe_out3,
|
||||||
|
probe_out4
|
||||||
|
);
|
||||||
|
|
||||||
|
input clk;
|
||||||
|
|
||||||
|
output reg [2 : 0] probe_out0 = 'h4 ;
|
||||||
|
output reg [0 : 0] probe_out1 = 'h0 ;
|
||||||
|
output reg [31 : 0] probe_out2 = 'h00000000 ;
|
||||||
|
output reg [1 : 0] probe_out3 = 'h3 ;
|
||||||
|
output reg [3 : 0] probe_out4 = 'h0 ;
|
||||||
|
|
||||||
|
|
||||||
|
endmodule
|
||||||
+70
@@ -0,0 +1,70 @@
|
|||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
// IP VLNV: xilinx.com:ip:vio:3.0
|
||||||
|
// IP Revision: 20
|
||||||
|
|
||||||
|
// The following must be inserted into your Verilog file for this
|
||||||
|
// core to be instantiated. Change the instance name and port connections
|
||||||
|
// (in parentheses) to your own signal names.
|
||||||
|
|
||||||
|
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||||
|
vio_manual_ctrl your_instance_name (
|
||||||
|
.clk(clk), // input wire clk
|
||||||
|
.probe_out0(probe_out0), // output wire [2 : 0] probe_out0
|
||||||
|
.probe_out1(probe_out1), // output wire [0 : 0] probe_out1
|
||||||
|
.probe_out2(probe_out2), // output wire [31 : 0] probe_out2
|
||||||
|
.probe_out3(probe_out3), // output wire [1 : 0] probe_out3
|
||||||
|
.probe_out4(probe_out4) // output wire [3 : 0] probe_out4
|
||||||
|
);
|
||||||
|
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||||
|
|
||||||
|
// You must compile the wrapper file vio_manual_ctrl.v when simulating
|
||||||
|
// the core, vio_manual_ctrl. When compiling the wrapper file, be sure to
|
||||||
|
// reference the Verilog simulation library.
|
||||||
|
|
||||||
+85
@@ -0,0 +1,85 @@
|
|||||||
|
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
--
|
||||||
|
-- This file contains confidential and proprietary information
|
||||||
|
-- of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
-- international copyright and other intellectual property
|
||||||
|
-- laws.
|
||||||
|
--
|
||||||
|
-- DISCLAIMER
|
||||||
|
-- This disclaimer is not a license and does not grant any
|
||||||
|
-- rights to the materials distributed herewith. Except as
|
||||||
|
-- otherwise provided in a valid license issued to you by
|
||||||
|
-- Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
-- including negligence, or under any other theory of
|
||||||
|
-- liability) for any loss or damage of any kind or nature
|
||||||
|
-- related to, arising under or in connection with these
|
||||||
|
-- materials, including for any direct, or any indirect,
|
||||||
|
-- special, incidental, or consequential loss or damage
|
||||||
|
-- (including loss of data, profits, goodwill, or any type of
|
||||||
|
-- loss or damage suffered as a result of any action brought
|
||||||
|
-- by a third party) even if such damage or loss was
|
||||||
|
-- reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
-- possibility of the same.
|
||||||
|
--
|
||||||
|
-- CRITICAL APPLICATIONS
|
||||||
|
-- Xilinx products are not designed or intended to be fail-
|
||||||
|
-- safe, or for use in any application requiring fail-safe
|
||||||
|
-- performance, such as life-support or safety devices or
|
||||||
|
-- systems, Class III medical devices, nuclear facilities,
|
||||||
|
-- applications related to the deployment of airbags, or any
|
||||||
|
-- other applications that could lead to death, personal
|
||||||
|
-- injury, or severe property or environmental damage
|
||||||
|
-- (individually and collectively, "Critical
|
||||||
|
-- Applications"). Customer assumes the sole risk and
|
||||||
|
-- liability of any use of Xilinx products in Critical
|
||||||
|
-- Applications, subject only to applicable laws and
|
||||||
|
-- regulations governing limitations on product liability.
|
||||||
|
--
|
||||||
|
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
-- PART OF THIS FILE AT ALL TIMES.
|
||||||
|
--
|
||||||
|
-- DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
-- IP VLNV: xilinx.com:ip:vio:3.0
|
||||||
|
-- IP Revision: 20
|
||||||
|
|
||||||
|
-- The following code must appear in the VHDL architecture header.
|
||||||
|
|
||||||
|
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||||
|
COMPONENT vio_manual_ctrl
|
||||||
|
PORT (
|
||||||
|
clk : IN STD_LOGIC;
|
||||||
|
probe_out0 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||||
|
probe_out1 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
probe_out2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||||
|
probe_out3 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||||
|
probe_out4 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||||
|
|
||||||
|
-- The following code must appear in the VHDL architecture
|
||||||
|
-- body. Substitute your own instance name and net names.
|
||||||
|
|
||||||
|
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||||
|
your_instance_name : vio_manual_ctrl
|
||||||
|
PORT MAP (
|
||||||
|
clk => clk,
|
||||||
|
probe_out0 => probe_out0,
|
||||||
|
probe_out1 => probe_out1,
|
||||||
|
probe_out2 => probe_out2,
|
||||||
|
probe_out3 => probe_out3,
|
||||||
|
probe_out4 => probe_out4
|
||||||
|
);
|
||||||
|
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||||
|
|
||||||
|
-- You must compile the wrapper file vio_manual_ctrl.vhd when simulating
|
||||||
|
-- the core, vio_manual_ctrl. When compiling the wrapper file, be sure to
|
||||||
|
-- reference the VHDL simulation library.
|
||||||
|
|
||||||
LFS
BIN
Binary file not shown.
LFS
BIN
Binary file not shown.
+26
@@ -0,0 +1,26 @@
|
|||||||
|
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||||
|
// Date : Mon May 8 17:56:01 2023
|
||||||
|
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||||
|
// Command : write_verilog -force -mode synth_stub
|
||||||
|
// /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v
|
||||||
|
// Design : vio_manual_ctrl
|
||||||
|
// Purpose : Stub declaration of top-level module interface
|
||||||
|
// Device : xc7z100ffg900-2
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||||
|
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||||
|
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||||
|
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
|
||||||
|
module vio_manual_ctrl(clk, probe_out0, probe_out1, probe_out2,
|
||||||
|
probe_out3, probe_out4)
|
||||||
|
/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[2:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]" */;
|
||||||
|
input clk;
|
||||||
|
output [2:0]probe_out0;
|
||||||
|
output [0:0]probe_out1;
|
||||||
|
output [31:0]probe_out2;
|
||||||
|
output [1:0]probe_out3;
|
||||||
|
output [3:0]probe_out4;
|
||||||
|
endmodule
|
||||||
+13
-10
@@ -1,31 +1,34 @@
|
|||||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
-- --------------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------------
|
||||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||||
-- Date : Wed Apr 19 12:04:19 2023
|
-- Date : Mon May 8 17:56:01 2023
|
||||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||||
-- Command : write_vhdl -force -mode synth_stub
|
-- Command : write_vhdl -force -mode synth_stub
|
||||||
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_stub.vhdl
|
-- /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl
|
||||||
-- Design : vio_hop
|
-- Design : vio_manual_ctrl
|
||||||
-- Purpose : Stub declaration of top-level module interface
|
-- Purpose : Stub declaration of top-level module interface
|
||||||
-- Device : xc7k410tffg900-2
|
-- Device : xc7z100ffg900-2
|
||||||
-- --------------------------------------------------------------------------------
|
-- --------------------------------------------------------------------------------
|
||||||
library IEEE;
|
library IEEE;
|
||||||
use IEEE.STD_LOGIC_1164.ALL;
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
|
||||||
entity vio_hop is
|
entity vio_manual_ctrl is
|
||||||
Port (
|
Port (
|
||||||
clk : in STD_LOGIC;
|
clk : in STD_LOGIC;
|
||||||
probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
probe_out0 : out STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||||
probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 )
|
probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||||
|
probe_out3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||||
|
probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 )
|
||||||
);
|
);
|
||||||
|
|
||||||
end vio_hop;
|
end vio_manual_ctrl;
|
||||||
|
|
||||||
architecture stub of vio_hop is
|
architecture stub of vio_manual_ctrl is
|
||||||
attribute syn_black_box : boolean;
|
attribute syn_black_box : boolean;
|
||||||
attribute black_box_pad_pin : string;
|
attribute black_box_pad_pin : string;
|
||||||
attribute syn_black_box of stub : architecture is true;
|
attribute syn_black_box of stub : architecture is true;
|
||||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[0:0],probe_out1[0:0]";
|
attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[2:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]";
|
||||||
attribute X_CORE_INFO : string;
|
attribute X_CORE_INFO : string;
|
||||||
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
|
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
|
||||||
begin
|
begin
|
||||||
+87
@@ -0,0 +1,87 @@
|
|||||||
|
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
`timescale 1ns / 1ps
|
||||||
|
module vio_rf_control (
|
||||||
|
clk,
|
||||||
|
probe_in0,
|
||||||
|
probe_out0,
|
||||||
|
probe_out1,
|
||||||
|
probe_out2,
|
||||||
|
probe_out3,
|
||||||
|
probe_out4,
|
||||||
|
probe_out5,
|
||||||
|
probe_out6,
|
||||||
|
probe_out7,
|
||||||
|
probe_out8,
|
||||||
|
probe_out9,
|
||||||
|
probe_out10,
|
||||||
|
probe_out11,
|
||||||
|
probe_out12,
|
||||||
|
probe_out13
|
||||||
|
);
|
||||||
|
|
||||||
|
input clk;
|
||||||
|
input [10 : 0] probe_in0;
|
||||||
|
|
||||||
|
output reg [0 : 0] probe_out0 = 'h0 ;
|
||||||
|
output reg [1 : 0] probe_out1 = 'h0 ;
|
||||||
|
output reg [0 : 0] probe_out2 = 'h0 ;
|
||||||
|
output reg [5 : 0] probe_out3 = 'h08 ;
|
||||||
|
output reg [5 : 0] probe_out4 = 'h38 ;
|
||||||
|
output reg [10 : 0] probe_out5 = 'h3E8 ;
|
||||||
|
output reg [0 : 0] probe_out6 = 'h0 ;
|
||||||
|
output reg [0 : 0] probe_out7 = 'h0 ;
|
||||||
|
output reg [0 : 0] probe_out8 = 'h0 ;
|
||||||
|
output reg [0 : 0] probe_out9 = 'h0 ;
|
||||||
|
output reg [0 : 0] probe_out10 = 'h0 ;
|
||||||
|
output reg [0 : 0] probe_out11 = 'h0 ;
|
||||||
|
output reg [0 : 0] probe_out12 = 'h0 ;
|
||||||
|
output reg [15 : 0] probe_out13 = 'h0000 ;
|
||||||
|
|
||||||
|
|
||||||
|
endmodule
|
||||||
@@ -0,0 +1,80 @@
|
|||||||
|
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
// international copyright and other intellectual property
|
||||||
|
// laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// Xilinx products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of Xilinx products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//
|
||||||
|
// DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
// IP VLNV: xilinx.com:ip:vio:3.0
|
||||||
|
// IP Revision: 20
|
||||||
|
|
||||||
|
// The following must be inserted into your Verilog file for this
|
||||||
|
// core to be instantiated. Change the instance name and port connections
|
||||||
|
// (in parentheses) to your own signal names.
|
||||||
|
|
||||||
|
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||||
|
vio_rf_control your_instance_name (
|
||||||
|
.clk(clk), // input wire clk
|
||||||
|
.probe_in0(probe_in0), // input wire [10 : 0] probe_in0
|
||||||
|
.probe_out0(probe_out0), // output wire [0 : 0] probe_out0
|
||||||
|
.probe_out1(probe_out1), // output wire [1 : 0] probe_out1
|
||||||
|
.probe_out2(probe_out2), // output wire [0 : 0] probe_out2
|
||||||
|
.probe_out3(probe_out3), // output wire [5 : 0] probe_out3
|
||||||
|
.probe_out4(probe_out4), // output wire [5 : 0] probe_out4
|
||||||
|
.probe_out5(probe_out5), // output wire [10 : 0] probe_out5
|
||||||
|
.probe_out6(probe_out6), // output wire [0 : 0] probe_out6
|
||||||
|
.probe_out7(probe_out7), // output wire [0 : 0] probe_out7
|
||||||
|
.probe_out8(probe_out8), // output wire [0 : 0] probe_out8
|
||||||
|
.probe_out9(probe_out9), // output wire [0 : 0] probe_out9
|
||||||
|
.probe_out10(probe_out10), // output wire [0 : 0] probe_out10
|
||||||
|
.probe_out11(probe_out11), // output wire [0 : 0] probe_out11
|
||||||
|
.probe_out12(probe_out12), // output wire [0 : 0] probe_out12
|
||||||
|
.probe_out13(probe_out13) // output wire [15 : 0] probe_out13
|
||||||
|
);
|
||||||
|
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||||
|
|
||||||
|
// You must compile the wrapper file vio_rf_control.v when simulating
|
||||||
|
// the core, vio_rf_control. When compiling the wrapper file, be sure to
|
||||||
|
// reference the Verilog simulation library.
|
||||||
|
|
||||||
@@ -0,0 +1,105 @@
|
|||||||
|
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||||
|
--
|
||||||
|
-- This file contains confidential and proprietary information
|
||||||
|
-- of Xilinx, Inc. and is protected under U.S. and
|
||||||
|
-- international copyright and other intellectual property
|
||||||
|
-- laws.
|
||||||
|
--
|
||||||
|
-- DISCLAIMER
|
||||||
|
-- This disclaimer is not a license and does not grant any
|
||||||
|
-- rights to the materials distributed herewith. Except as
|
||||||
|
-- otherwise provided in a valid license issued to you by
|
||||||
|
-- Xilinx, and to the maximum extent permitted by applicable
|
||||||
|
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||||
|
-- including negligence, or under any other theory of
|
||||||
|
-- liability) for any loss or damage of any kind or nature
|
||||||
|
-- related to, arising under or in connection with these
|
||||||
|
-- materials, including for any direct, or any indirect,
|
||||||
|
-- special, incidental, or consequential loss or damage
|
||||||
|
-- (including loss of data, profits, goodwill, or any type of
|
||||||
|
-- loss or damage suffered as a result of any action brought
|
||||||
|
-- by a third party) even if such damage or loss was
|
||||||
|
-- reasonably foreseeable or Xilinx had been advised of the
|
||||||
|
-- possibility of the same.
|
||||||
|
--
|
||||||
|
-- CRITICAL APPLICATIONS
|
||||||
|
-- Xilinx products are not designed or intended to be fail-
|
||||||
|
-- safe, or for use in any application requiring fail-safe
|
||||||
|
-- performance, such as life-support or safety devices or
|
||||||
|
-- systems, Class III medical devices, nuclear facilities,
|
||||||
|
-- applications related to the deployment of airbags, or any
|
||||||
|
-- other applications that could lead to death, personal
|
||||||
|
-- injury, or severe property or environmental damage
|
||||||
|
-- (individually and collectively, "Critical
|
||||||
|
-- Applications"). Customer assumes the sole risk and
|
||||||
|
-- liability of any use of Xilinx products in Critical
|
||||||
|
-- Applications, subject only to applicable laws and
|
||||||
|
-- regulations governing limitations on product liability.
|
||||||
|
--
|
||||||
|
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
-- PART OF THIS FILE AT ALL TIMES.
|
||||||
|
--
|
||||||
|
-- DO NOT MODIFY THIS FILE.
|
||||||
|
|
||||||
|
-- IP VLNV: xilinx.com:ip:vio:3.0
|
||||||
|
-- IP Revision: 20
|
||||||
|
|
||||||
|
-- The following code must appear in the VHDL architecture header.
|
||||||
|
|
||||||
|
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
|
||||||
|
COMPONENT vio_rf_control
|
||||||
|
PORT (
|
||||||
|
clk : IN STD_LOGIC;
|
||||||
|
probe_in0 : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
|
||||||
|
probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
probe_out1 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||||
|
probe_out2 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
probe_out3 : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
|
||||||
|
probe_out4 : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
|
||||||
|
probe_out5 : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
|
||||||
|
probe_out6 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
probe_out7 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
probe_out8 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
probe_out9 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
probe_out10 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
probe_out11 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
probe_out12 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||||
|
probe_out13 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
|
||||||
|
);
|
||||||
|
END COMPONENT;
|
||||||
|
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||||
|
|
||||||
|
-- The following code must appear in the VHDL architecture
|
||||||
|
-- body. Substitute your own instance name and net names.
|
||||||
|
|
||||||
|
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
|
||||||
|
your_instance_name : vio_rf_control
|
||||||
|
PORT MAP (
|
||||||
|
clk => clk,
|
||||||
|
probe_in0 => probe_in0,
|
||||||
|
probe_out0 => probe_out0,
|
||||||
|
probe_out1 => probe_out1,
|
||||||
|
probe_out2 => probe_out2,
|
||||||
|
probe_out3 => probe_out3,
|
||||||
|
probe_out4 => probe_out4,
|
||||||
|
probe_out5 => probe_out5,
|
||||||
|
probe_out6 => probe_out6,
|
||||||
|
probe_out7 => probe_out7,
|
||||||
|
probe_out8 => probe_out8,
|
||||||
|
probe_out9 => probe_out9,
|
||||||
|
probe_out10 => probe_out10,
|
||||||
|
probe_out11 => probe_out11,
|
||||||
|
probe_out12 => probe_out12,
|
||||||
|
probe_out13 => probe_out13
|
||||||
|
);
|
||||||
|
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||||
|
|
||||||
|
-- You must compile the wrapper file vio_rf_control.vhd when simulating
|
||||||
|
-- the core, vio_rf_control. When compiling the wrapper file, be sure to
|
||||||
|
-- reference the VHDL simulation library.
|
||||||
|
|
||||||
BIN
Binary file not shown.
LFS
BIN
Binary file not shown.
+37
@@ -0,0 +1,37 @@
|
|||||||
|
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||||
|
// Date : Sun May 7 19:30:43 2023
|
||||||
|
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||||
|
// Command : write_verilog -force -mode synth_stub
|
||||||
|
// /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.v
|
||||||
|
// Design : vio_rf_control
|
||||||
|
// Purpose : Stub declaration of top-level module interface
|
||||||
|
// Device : xc7z100ffg900-2
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||||
|
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||||
|
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||||
|
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
|
||||||
|
module vio_rf_control(clk, probe_in0, probe_out0, probe_out1,
|
||||||
|
probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9,
|
||||||
|
probe_out10, probe_out11, probe_out12, probe_out13)
|
||||||
|
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[10:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[5:0],probe_out4[5:0],probe_out5[10:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[15:0]" */;
|
||||||
|
input clk;
|
||||||
|
input [10:0]probe_in0;
|
||||||
|
output [0:0]probe_out0;
|
||||||
|
output [1:0]probe_out1;
|
||||||
|
output [0:0]probe_out2;
|
||||||
|
output [5:0]probe_out3;
|
||||||
|
output [5:0]probe_out4;
|
||||||
|
output [10:0]probe_out5;
|
||||||
|
output [0:0]probe_out6;
|
||||||
|
output [0:0]probe_out7;
|
||||||
|
output [0:0]probe_out8;
|
||||||
|
output [0:0]probe_out9;
|
||||||
|
output [0:0]probe_out10;
|
||||||
|
output [0:0]probe_out11;
|
||||||
|
output [0:0]probe_out12;
|
||||||
|
output [15:0]probe_out13;
|
||||||
|
endmodule
|
||||||
+45
@@ -0,0 +1,45 @@
|
|||||||
|
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
-- --------------------------------------------------------------------------------
|
||||||
|
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||||
|
-- Date : Sun May 7 19:30:43 2023
|
||||||
|
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||||
|
-- Command : write_vhdl -force -mode synth_stub
|
||||||
|
-- /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.vhdl
|
||||||
|
-- Design : vio_rf_control
|
||||||
|
-- Purpose : Stub declaration of top-level module interface
|
||||||
|
-- Device : xc7z100ffg900-2
|
||||||
|
-- --------------------------------------------------------------------------------
|
||||||
|
library IEEE;
|
||||||
|
use IEEE.STD_LOGIC_1164.ALL;
|
||||||
|
|
||||||
|
entity vio_rf_control is
|
||||||
|
Port (
|
||||||
|
clk : in STD_LOGIC;
|
||||||
|
probe_in0 : in STD_LOGIC_VECTOR ( 10 downto 0 );
|
||||||
|
probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
probe_out1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||||
|
probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
probe_out3 : out STD_LOGIC_VECTOR ( 5 downto 0 );
|
||||||
|
probe_out4 : out STD_LOGIC_VECTOR ( 5 downto 0 );
|
||||||
|
probe_out5 : out STD_LOGIC_VECTOR ( 10 downto 0 );
|
||||||
|
probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
probe_out9 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
probe_out10 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
probe_out11 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
probe_out12 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||||
|
probe_out13 : out STD_LOGIC_VECTOR ( 15 downto 0 )
|
||||||
|
);
|
||||||
|
|
||||||
|
end vio_rf_control;
|
||||||
|
|
||||||
|
architecture stub of vio_rf_control is
|
||||||
|
attribute syn_black_box : boolean;
|
||||||
|
attribute black_box_pad_pin : string;
|
||||||
|
attribute syn_black_box of stub : architecture is true;
|
||||||
|
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[10:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[5:0],probe_out4[5:0],probe_out5[10:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[15:0]";
|
||||||
|
attribute X_CORE_INFO : string;
|
||||||
|
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
|
||||||
|
begin
|
||||||
|
end;
|
||||||
+4522
File diff suppressed because it is too large
Load Diff
+83
@@ -0,0 +1,83 @@
|
|||||||
|
MEMORY_INITIALIZATION_RADIX = 10;
|
||||||
|
MEMORY_INITIALIZATION_VECTOR =
|
||||||
|
1624,
|
||||||
|
1611,
|
||||||
|
1598,
|
||||||
|
1585,
|
||||||
|
1572,
|
||||||
|
1559,
|
||||||
|
1546,
|
||||||
|
1533,
|
||||||
|
1520,
|
||||||
|
1507,
|
||||||
|
1494,
|
||||||
|
1481,
|
||||||
|
1468,
|
||||||
|
1455,
|
||||||
|
1442,
|
||||||
|
1429,
|
||||||
|
1416,
|
||||||
|
1403,
|
||||||
|
1390,
|
||||||
|
1377,
|
||||||
|
1364,
|
||||||
|
1351,
|
||||||
|
1338,
|
||||||
|
1325,
|
||||||
|
1312,
|
||||||
|
1299,
|
||||||
|
1286,
|
||||||
|
1273,
|
||||||
|
1260,
|
||||||
|
1247,
|
||||||
|
1234,
|
||||||
|
1221,
|
||||||
|
1208,
|
||||||
|
1195,
|
||||||
|
1182,
|
||||||
|
1169,
|
||||||
|
1156,
|
||||||
|
1143,
|
||||||
|
1130,
|
||||||
|
1117,
|
||||||
|
1104,
|
||||||
|
1091,
|
||||||
|
1078,
|
||||||
|
1065,
|
||||||
|
1052,
|
||||||
|
1039,
|
||||||
|
1026,
|
||||||
|
1013,
|
||||||
|
1000,
|
||||||
|
987,
|
||||||
|
974,
|
||||||
|
961,
|
||||||
|
948,
|
||||||
|
935,
|
||||||
|
922,
|
||||||
|
909,
|
||||||
|
896,
|
||||||
|
883,
|
||||||
|
870,
|
||||||
|
857,
|
||||||
|
844,
|
||||||
|
831,
|
||||||
|
818,
|
||||||
|
805,
|
||||||
|
792,
|
||||||
|
779,
|
||||||
|
766,
|
||||||
|
753,
|
||||||
|
740,
|
||||||
|
727,
|
||||||
|
714,
|
||||||
|
701,
|
||||||
|
688,
|
||||||
|
675,
|
||||||
|
662,
|
||||||
|
649,
|
||||||
|
636,
|
||||||
|
623,
|
||||||
|
610,
|
||||||
|
597,
|
||||||
|
584,
|
||||||
@@ -0,0 +1,81 @@
|
|||||||
|
11001011000
|
||||||
|
11001001011
|
||||||
|
11000111110
|
||||||
|
11000110001
|
||||||
|
11000100100
|
||||||
|
11000010111
|
||||||
|
11000001010
|
||||||
|
10111111101
|
||||||
|
10111110000
|
||||||
|
10111100011
|
||||||
|
10111010110
|
||||||
|
10111001001
|
||||||
|
10110111100
|
||||||
|
10110101111
|
||||||
|
10110100010
|
||||||
|
10110010101
|
||||||
|
10110001000
|
||||||
|
10101111011
|
||||||
|
10101101110
|
||||||
|
10101100001
|
||||||
|
10101010100
|
||||||
|
10101000111
|
||||||
|
10100111010
|
||||||
|
10100101101
|
||||||
|
10100100000
|
||||||
|
10100010011
|
||||||
|
10100000110
|
||||||
|
10011111001
|
||||||
|
10011101100
|
||||||
|
10011011111
|
||||||
|
10011010010
|
||||||
|
10011000101
|
||||||
|
10010111000
|
||||||
|
10010101011
|
||||||
|
10010011110
|
||||||
|
10010010001
|
||||||
|
10010000100
|
||||||
|
10001110111
|
||||||
|
10001101010
|
||||||
|
10001011101
|
||||||
|
10001010000
|
||||||
|
10001000011
|
||||||
|
10000110110
|
||||||
|
10000101001
|
||||||
|
10000011100
|
||||||
|
10000001111
|
||||||
|
10000000010
|
||||||
|
01111110101
|
||||||
|
01111101000
|
||||||
|
01111011011
|
||||||
|
01111001110
|
||||||
|
01111000001
|
||||||
|
01110110100
|
||||||
|
01110100111
|
||||||
|
01110011010
|
||||||
|
01110001101
|
||||||
|
01110000000
|
||||||
|
01101110011
|
||||||
|
01101100110
|
||||||
|
01101011001
|
||||||
|
01101001100
|
||||||
|
01100111111
|
||||||
|
01100110010
|
||||||
|
01100100101
|
||||||
|
01100011000
|
||||||
|
01100001011
|
||||||
|
01011111110
|
||||||
|
01011110001
|
||||||
|
01011100100
|
||||||
|
01011010111
|
||||||
|
01011001010
|
||||||
|
01010111101
|
||||||
|
01010110000
|
||||||
|
01010100011
|
||||||
|
01010010110
|
||||||
|
01010001001
|
||||||
|
01001111100
|
||||||
|
01001101111
|
||||||
|
01001100010
|
||||||
|
01001010101
|
||||||
|
01001001000
|
||||||
+49
@@ -0,0 +1,49 @@
|
|||||||
|
################################################################################
|
||||||
|
# Vivado (TM) v2019.1.3 (64-bit)
|
||||||
|
#
|
||||||
|
# README.txt: Please read the sections below to understand the steps required to
|
||||||
|
# run the exported script and information about the source files.
|
||||||
|
#
|
||||||
|
# Generated by export_simulation on Mon May 08 18:55:24 CST 2023
|
||||||
|
#
|
||||||
|
################################################################################
|
||||||
|
|
||||||
|
1. How to run the generated simulation script:-
|
||||||
|
|
||||||
|
From the shell prompt in the current directory, issue the following command:-
|
||||||
|
|
||||||
|
./rom_freq_word.sh
|
||||||
|
|
||||||
|
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||||
|
implemented in the script file for the 3-step flow. These functions are called
|
||||||
|
from the main 'run' function in the script file.
|
||||||
|
|
||||||
|
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||||
|
create simulator specific setup files, create design library mappings and library
|
||||||
|
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||||
|
current directory.
|
||||||
|
|
||||||
|
The 'setup' function is also used for removing the simulator generated data in
|
||||||
|
order to reset the current directory to the original state when export_simulation
|
||||||
|
was launched from Vivado. This generated data can be removed by specifying the
|
||||||
|
'-reset_run' switch to the './rom_freq_word.sh' script.
|
||||||
|
|
||||||
|
./rom_freq_word.sh -reset_run
|
||||||
|
|
||||||
|
To keep the generated data from the previous run but regenerate the setup files and
|
||||||
|
library directories, use the '-noclean_files' switch.
|
||||||
|
|
||||||
|
./rom_freq_word.sh -noclean_files
|
||||||
|
|
||||||
|
For more information on the script, please type './rom_freq_word.sh -help'.
|
||||||
|
|
||||||
|
2. Additional design information files:-
|
||||||
|
|
||||||
|
export_simulation generates following additional file that can be used for fetching
|
||||||
|
the design files information or for integrating with external custom scripts.
|
||||||
|
|
||||||
|
Name : file_info.txt
|
||||||
|
Purpose: This file contains detail design file information based on the compile order
|
||||||
|
when export_simulation was executed from Vivado. The file contains information
|
||||||
|
about the file type, name, whether it is part of the IP, associated library
|
||||||
|
and the file path information.
|
||||||
+1
-1
@@ -20,7 +20,7 @@ vlog -work blk_mem_gen_v8_4_3 -v2k5 \
|
|||||||
"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
|
"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
|
||||||
|
|
||||||
vlog -work xil_defaultlib -v2k5 \
|
vlog -work xil_defaultlib -v2k5 \
|
||||||
"../../../ip/rom_hop_data/sim/rom_hop_data.v" \
|
"../../../ip/rom_freq_word/sim/rom_freq_word.v" \
|
||||||
|
|
||||||
vlog -work xil_defaultlib \
|
vlog -work xil_defaultlib \
|
||||||
"glbl.v"
|
"glbl.v"
|
||||||
+1
-1
@@ -2,5 +2,5 @@ xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tool
|
|||||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||||
blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
|
blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
|
||||||
rom_hop_data.v,verilog,xil_defaultlib,../../../ip/rom_hop_data/sim/rom_hop_data.v,
|
rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v,
|
||||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||||
Executable
+83
@@ -0,0 +1,83 @@
|
|||||||
|
MEMORY_INITIALIZATION_RADIX = 10;
|
||||||
|
MEMORY_INITIALIZATION_VECTOR =
|
||||||
|
1624,
|
||||||
|
1611,
|
||||||
|
1598,
|
||||||
|
1585,
|
||||||
|
1572,
|
||||||
|
1559,
|
||||||
|
1546,
|
||||||
|
1533,
|
||||||
|
1520,
|
||||||
|
1507,
|
||||||
|
1494,
|
||||||
|
1481,
|
||||||
|
1468,
|
||||||
|
1455,
|
||||||
|
1442,
|
||||||
|
1429,
|
||||||
|
1416,
|
||||||
|
1403,
|
||||||
|
1390,
|
||||||
|
1377,
|
||||||
|
1364,
|
||||||
|
1351,
|
||||||
|
1338,
|
||||||
|
1325,
|
||||||
|
1312,
|
||||||
|
1299,
|
||||||
|
1286,
|
||||||
|
1273,
|
||||||
|
1260,
|
||||||
|
1247,
|
||||||
|
1234,
|
||||||
|
1221,
|
||||||
|
1208,
|
||||||
|
1195,
|
||||||
|
1182,
|
||||||
|
1169,
|
||||||
|
1156,
|
||||||
|
1143,
|
||||||
|
1130,
|
||||||
|
1117,
|
||||||
|
1104,
|
||||||
|
1091,
|
||||||
|
1078,
|
||||||
|
1065,
|
||||||
|
1052,
|
||||||
|
1039,
|
||||||
|
1026,
|
||||||
|
1013,
|
||||||
|
1000,
|
||||||
|
987,
|
||||||
|
974,
|
||||||
|
961,
|
||||||
|
948,
|
||||||
|
935,
|
||||||
|
922,
|
||||||
|
909,
|
||||||
|
896,
|
||||||
|
883,
|
||||||
|
870,
|
||||||
|
857,
|
||||||
|
844,
|
||||||
|
831,
|
||||||
|
818,
|
||||||
|
805,
|
||||||
|
792,
|
||||||
|
779,
|
||||||
|
766,
|
||||||
|
753,
|
||||||
|
740,
|
||||||
|
727,
|
||||||
|
714,
|
||||||
|
701,
|
||||||
|
688,
|
||||||
|
675,
|
||||||
|
662,
|
||||||
|
649,
|
||||||
|
636,
|
||||||
|
623,
|
||||||
|
610,
|
||||||
|
597,
|
||||||
|
584,
|
||||||
+81
@@ -0,0 +1,81 @@
|
|||||||
|
11001011000
|
||||||
|
11001001011
|
||||||
|
11000111110
|
||||||
|
11000110001
|
||||||
|
11000100100
|
||||||
|
11000010111
|
||||||
|
11000001010
|
||||||
|
10111111101
|
||||||
|
10111110000
|
||||||
|
10111100011
|
||||||
|
10111010110
|
||||||
|
10111001001
|
||||||
|
10110111100
|
||||||
|
10110101111
|
||||||
|
10110100010
|
||||||
|
10110010101
|
||||||
|
10110001000
|
||||||
|
10101111011
|
||||||
|
10101101110
|
||||||
|
10101100001
|
||||||
|
10101010100
|
||||||
|
10101000111
|
||||||
|
10100111010
|
||||||
|
10100101101
|
||||||
|
10100100000
|
||||||
|
10100010011
|
||||||
|
10100000110
|
||||||
|
10011111001
|
||||||
|
10011101100
|
||||||
|
10011011111
|
||||||
|
10011010010
|
||||||
|
10011000101
|
||||||
|
10010111000
|
||||||
|
10010101011
|
||||||
|
10010011110
|
||||||
|
10010010001
|
||||||
|
10010000100
|
||||||
|
10001110111
|
||||||
|
10001101010
|
||||||
|
10001011101
|
||||||
|
10001010000
|
||||||
|
10001000011
|
||||||
|
10000110110
|
||||||
|
10000101001
|
||||||
|
10000011100
|
||||||
|
10000001111
|
||||||
|
10000000010
|
||||||
|
01111110101
|
||||||
|
01111101000
|
||||||
|
01111011011
|
||||||
|
01111001110
|
||||||
|
01111000001
|
||||||
|
01110110100
|
||||||
|
01110100111
|
||||||
|
01110011010
|
||||||
|
01110001101
|
||||||
|
01110000000
|
||||||
|
01101110011
|
||||||
|
01101100110
|
||||||
|
01101011001
|
||||||
|
01101001100
|
||||||
|
01100111111
|
||||||
|
01100110010
|
||||||
|
01100100101
|
||||||
|
01100011000
|
||||||
|
01100001011
|
||||||
|
01011111110
|
||||||
|
01011110001
|
||||||
|
01011100100
|
||||||
|
01011010111
|
||||||
|
01011001010
|
||||||
|
01010111101
|
||||||
|
01010110000
|
||||||
|
01010100011
|
||||||
|
01010010110
|
||||||
|
01010001001
|
||||||
|
01001111100
|
||||||
|
01001101111
|
||||||
|
01001100010
|
||||||
|
01001010101
|
||||||
|
01001001000
|
||||||
projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.sh
Executable
+152
@@ -0,0 +1,152 @@
|
|||||||
|
#!/bin/bash -f
|
||||||
|
#*********************************************************************************************************
|
||||||
|
# Vivado (TM) v2019.1.3 (64-bit)
|
||||||
|
#
|
||||||
|
# Filename : rom_freq_word.sh
|
||||||
|
# Simulator : Aldec Active-HDL Simulator
|
||||||
|
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
||||||
|
# The script will automatically create the design libraries sub-directories in the run
|
||||||
|
# directory, add the library logical mappings in the simulator setup file, create default
|
||||||
|
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||||
|
#
|
||||||
|
# Generated by Vivado on Mon May 08 18:55:24 CST 2023
|
||||||
|
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||||
|
#
|
||||||
|
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
#
|
||||||
|
# usage: rom_freq_word.sh [-help]
|
||||||
|
# usage: rom_freq_word.sh [-lib_map_path]
|
||||||
|
# usage: rom_freq_word.sh [-noclean_files]
|
||||||
|
# usage: rom_freq_word.sh [-reset_run]
|
||||||
|
#
|
||||||
|
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
|
||||||
|
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
|
||||||
|
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
|
||||||
|
# that points to these libraries and rerun export_simulation. For more information about this switch please
|
||||||
|
# type 'export_simulation -help' in the Tcl shell.
|
||||||
|
#
|
||||||
|
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
|
||||||
|
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
|
||||||
|
# executing this script. Please type 'rom_freq_word.sh -help' for more information.
|
||||||
|
#
|
||||||
|
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
|
||||||
|
#
|
||||||
|
#*********************************************************************************************************
|
||||||
|
|
||||||
|
|
||||||
|
# Script info
|
||||||
|
echo -e "rom_freq_word.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
|
||||||
|
|
||||||
|
# Main steps
|
||||||
|
run()
|
||||||
|
{
|
||||||
|
check_args $# $1
|
||||||
|
setup $1 $2
|
||||||
|
compile
|
||||||
|
simulate
|
||||||
|
}
|
||||||
|
|
||||||
|
# RUN_STEP: <compile>
|
||||||
|
compile()
|
||||||
|
{
|
||||||
|
# Compile design files
|
||||||
|
source compile.do 2>&1 | tee -a compile.log
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
# RUN_STEP: <simulate>
|
||||||
|
simulate()
|
||||||
|
{
|
||||||
|
runvsimsa -l simulate.log -do "do {simulate.do}"
|
||||||
|
}
|
||||||
|
|
||||||
|
# STEP: setup
|
||||||
|
setup()
|
||||||
|
{
|
||||||
|
case $1 in
|
||||||
|
"-lib_map_path" )
|
||||||
|
if [[ ($2 == "") ]]; then
|
||||||
|
echo -e "ERROR: Simulation library directory path not specified (type \"./rom_freq_word.sh -help\" for more information)\n"
|
||||||
|
exit 1
|
||||||
|
fi
|
||||||
|
map_setup_file $2
|
||||||
|
;;
|
||||||
|
"-reset_run" )
|
||||||
|
reset_run
|
||||||
|
echo -e "INFO: Simulation run files deleted.\n"
|
||||||
|
exit 0
|
||||||
|
;;
|
||||||
|
"-noclean_files" )
|
||||||
|
# do not remove previous data
|
||||||
|
;;
|
||||||
|
* )
|
||||||
|
map_setup_file $2
|
||||||
|
esac
|
||||||
|
|
||||||
|
# Add any setup/initialization commands here:-
|
||||||
|
|
||||||
|
# <user specific commands>
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
# Map library.cfg file
|
||||||
|
map_setup_file()
|
||||||
|
{
|
||||||
|
file="library.cfg"
|
||||||
|
lib_map_path=""
|
||||||
|
if [[ ($1 != "") ]]; then
|
||||||
|
lib_map_path="$1"
|
||||||
|
fi
|
||||||
|
if [[ ($lib_map_path != "") ]]; then
|
||||||
|
src_file="$lib_map_path/$file"
|
||||||
|
if [[ -e $src_file ]]; then
|
||||||
|
vmap -link $lib_map_path
|
||||||
|
fi
|
||||||
|
fi
|
||||||
|
}
|
||||||
|
|
||||||
|
# Delete generated data from the previous run
|
||||||
|
reset_run()
|
||||||
|
{
|
||||||
|
files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
|
||||||
|
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||||
|
file="${files_to_remove[i]}"
|
||||||
|
if [[ -e $file ]]; then
|
||||||
|
rm -rf $file
|
||||||
|
fi
|
||||||
|
done
|
||||||
|
}
|
||||||
|
|
||||||
|
# Check command line arguments
|
||||||
|
check_args()
|
||||||
|
{
|
||||||
|
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
||||||
|
echo -e "ERROR: Unknown option specified '$2' (type \"./rom_freq_word.sh -help\" for more information)\n"
|
||||||
|
exit 1
|
||||||
|
fi
|
||||||
|
|
||||||
|
if [[ ($2 == "-help" || $2 == "-h") ]]; then
|
||||||
|
usage
|
||||||
|
fi
|
||||||
|
}
|
||||||
|
|
||||||
|
# Script usage
|
||||||
|
usage()
|
||||||
|
{
|
||||||
|
msg="Usage: rom_freq_word.sh [-help]\n\
|
||||||
|
Usage: rom_freq_word.sh [-lib_map_path]\n\
|
||||||
|
Usage: rom_freq_word.sh [-reset_run]\n\
|
||||||
|
Usage: rom_freq_word.sh [-noclean_files]\n\n\
|
||||||
|
[-help] -- Print help information for this script\n\n\
|
||||||
|
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||||
|
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||||
|
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
|
||||||
|
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
|
||||||
|
-noclean_files switch.\n\n\
|
||||||
|
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
|
||||||
|
echo -e $msg
|
||||||
|
exit 1
|
||||||
|
}
|
||||||
|
|
||||||
|
# Launch script
|
||||||
|
run $1 $2
|
||||||
+17
@@ -0,0 +1,17 @@
|
|||||||
|
onbreak {quit -force}
|
||||||
|
onerror {quit -force}
|
||||||
|
|
||||||
|
asim -t 1ps +access +r +m+rom_freq_word -L xil_defaultlib -L xpm -L blk_mem_gen_v8_4_3 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.rom_freq_word xil_defaultlib.glbl
|
||||||
|
|
||||||
|
do {wave.do}
|
||||||
|
|
||||||
|
view wave
|
||||||
|
view structure
|
||||||
|
|
||||||
|
do {rom_freq_word.udo}
|
||||||
|
|
||||||
|
run -all
|
||||||
|
|
||||||
|
endsim
|
||||||
|
|
||||||
|
quit -force
|
||||||
+48
@@ -0,0 +1,48 @@
|
|||||||
|
################################################################################
|
||||||
|
# Vivado (TM) v2019.1.3 (64-bit)
|
||||||
|
#
|
||||||
|
# README.txt: Please read the sections below to understand the steps required to
|
||||||
|
# run the exported script and information about the source files.
|
||||||
|
#
|
||||||
|
# Generated by export_simulation on Mon May 08 18:55:24 CST 2023
|
||||||
|
#
|
||||||
|
################################################################################
|
||||||
|
|
||||||
|
1. How to run the generated simulation script:-
|
||||||
|
|
||||||
|
From the shell prompt in the current directory, issue the following command:-
|
||||||
|
|
||||||
|
./rom_freq_word.sh
|
||||||
|
|
||||||
|
This command will launch the 'execute' function for the single-step flow. This
|
||||||
|
function is called from the main 'run' function in the script file.
|
||||||
|
|
||||||
|
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||||
|
create simulator specific setup files, create design library mappings and library
|
||||||
|
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||||
|
current directory.
|
||||||
|
|
||||||
|
The 'setup' function is also used for removing the simulator generated data in
|
||||||
|
order to reset the current directory to the original state when export_simulation
|
||||||
|
was launched from Vivado. This generated data can be removed by specifying the
|
||||||
|
'-reset_run' switch to the './rom_freq_word.sh' script.
|
||||||
|
|
||||||
|
./rom_freq_word.sh -reset_run
|
||||||
|
|
||||||
|
To keep the generated data from the previous run but regenerate the setup files and
|
||||||
|
library directories, use the '-noclean_files' switch.
|
||||||
|
|
||||||
|
./rom_freq_word.sh -noclean_files
|
||||||
|
|
||||||
|
For more information on the script, please type './rom_freq_word.sh -help'.
|
||||||
|
|
||||||
|
2. Additional design information files:-
|
||||||
|
|
||||||
|
export_simulation generates following additional file that can be used for fetching
|
||||||
|
the design files information or for integrating with external custom scripts.
|
||||||
|
|
||||||
|
Name : file_info.txt
|
||||||
|
Purpose: This file contains detail design file information based on the compile order
|
||||||
|
when export_simulation was executed from Vivado. The file contains information
|
||||||
|
about the file type, name, whether it is part of the IP, associated library
|
||||||
|
and the file path information.
|
||||||
+1
-1
@@ -2,5 +2,5 @@ xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tool
|
|||||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||||
blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
|
blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
|
||||||
rom_hop_data.v,verilog,xil_defaultlib,../../../ip/rom_hop_data/sim/rom_hop_data.v,
|
rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v,
|
||||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||||
Executable
+83
@@ -0,0 +1,83 @@
|
|||||||
|
MEMORY_INITIALIZATION_RADIX = 10;
|
||||||
|
MEMORY_INITIALIZATION_VECTOR =
|
||||||
|
1624,
|
||||||
|
1611,
|
||||||
|
1598,
|
||||||
|
1585,
|
||||||
|
1572,
|
||||||
|
1559,
|
||||||
|
1546,
|
||||||
|
1533,
|
||||||
|
1520,
|
||||||
|
1507,
|
||||||
|
1494,
|
||||||
|
1481,
|
||||||
|
1468,
|
||||||
|
1455,
|
||||||
|
1442,
|
||||||
|
1429,
|
||||||
|
1416,
|
||||||
|
1403,
|
||||||
|
1390,
|
||||||
|
1377,
|
||||||
|
1364,
|
||||||
|
1351,
|
||||||
|
1338,
|
||||||
|
1325,
|
||||||
|
1312,
|
||||||
|
1299,
|
||||||
|
1286,
|
||||||
|
1273,
|
||||||
|
1260,
|
||||||
|
1247,
|
||||||
|
1234,
|
||||||
|
1221,
|
||||||
|
1208,
|
||||||
|
1195,
|
||||||
|
1182,
|
||||||
|
1169,
|
||||||
|
1156,
|
||||||
|
1143,
|
||||||
|
1130,
|
||||||
|
1117,
|
||||||
|
1104,
|
||||||
|
1091,
|
||||||
|
1078,
|
||||||
|
1065,
|
||||||
|
1052,
|
||||||
|
1039,
|
||||||
|
1026,
|
||||||
|
1013,
|
||||||
|
1000,
|
||||||
|
987,
|
||||||
|
974,
|
||||||
|
961,
|
||||||
|
948,
|
||||||
|
935,
|
||||||
|
922,
|
||||||
|
909,
|
||||||
|
896,
|
||||||
|
883,
|
||||||
|
870,
|
||||||
|
857,
|
||||||
|
844,
|
||||||
|
831,
|
||||||
|
818,
|
||||||
|
805,
|
||||||
|
792,
|
||||||
|
779,
|
||||||
|
766,
|
||||||
|
753,
|
||||||
|
740,
|
||||||
|
727,
|
||||||
|
714,
|
||||||
|
701,
|
||||||
|
688,
|
||||||
|
675,
|
||||||
|
662,
|
||||||
|
649,
|
||||||
|
636,
|
||||||
|
623,
|
||||||
|
610,
|
||||||
|
597,
|
||||||
|
584,
|
||||||
+81
@@ -0,0 +1,81 @@
|
|||||||
|
11001011000
|
||||||
|
11001001011
|
||||||
|
11000111110
|
||||||
|
11000110001
|
||||||
|
11000100100
|
||||||
|
11000010111
|
||||||
|
11000001010
|
||||||
|
10111111101
|
||||||
|
10111110000
|
||||||
|
10111100011
|
||||||
|
10111010110
|
||||||
|
10111001001
|
||||||
|
10110111100
|
||||||
|
10110101111
|
||||||
|
10110100010
|
||||||
|
10110010101
|
||||||
|
10110001000
|
||||||
|
10101111011
|
||||||
|
10101101110
|
||||||
|
10101100001
|
||||||
|
10101010100
|
||||||
|
10101000111
|
||||||
|
10100111010
|
||||||
|
10100101101
|
||||||
|
10100100000
|
||||||
|
10100010011
|
||||||
|
10100000110
|
||||||
|
10011111001
|
||||||
|
10011101100
|
||||||
|
10011011111
|
||||||
|
10011010010
|
||||||
|
10011000101
|
||||||
|
10010111000
|
||||||
|
10010101011
|
||||||
|
10010011110
|
||||||
|
10010010001
|
||||||
|
10010000100
|
||||||
|
10001110111
|
||||||
|
10001101010
|
||||||
|
10001011101
|
||||||
|
10001010000
|
||||||
|
10001000011
|
||||||
|
10000110110
|
||||||
|
10000101001
|
||||||
|
10000011100
|
||||||
|
10000001111
|
||||||
|
10000000010
|
||||||
|
01111110101
|
||||||
|
01111101000
|
||||||
|
01111011011
|
||||||
|
01111001110
|
||||||
|
01111000001
|
||||||
|
01110110100
|
||||||
|
01110100111
|
||||||
|
01110011010
|
||||||
|
01110001101
|
||||||
|
01110000000
|
||||||
|
01101110011
|
||||||
|
01101100110
|
||||||
|
01101011001
|
||||||
|
01101001100
|
||||||
|
01100111111
|
||||||
|
01100110010
|
||||||
|
01100100101
|
||||||
|
01100011000
|
||||||
|
01100001011
|
||||||
|
01011111110
|
||||||
|
01011110001
|
||||||
|
01011100100
|
||||||
|
01011010111
|
||||||
|
01011001010
|
||||||
|
01010111101
|
||||||
|
01010110000
|
||||||
|
01010100011
|
||||||
|
01010010110
|
||||||
|
01010001001
|
||||||
|
01001111100
|
||||||
|
01001101111
|
||||||
|
01001100010
|
||||||
|
01001010101
|
||||||
|
01001001000
|
||||||
+15
-15
@@ -2,22 +2,22 @@
|
|||||||
#*********************************************************************************************************
|
#*********************************************************************************************************
|
||||||
# Vivado (TM) v2019.1.3 (64-bit)
|
# Vivado (TM) v2019.1.3 (64-bit)
|
||||||
#
|
#
|
||||||
# Filename : rom_hop_data.sh
|
# Filename : rom_freq_word.sh
|
||||||
# Simulator : Cadence Incisive Enterprise Simulator
|
# Simulator : Cadence Incisive Enterprise Simulator
|
||||||
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
||||||
# The script will automatically create the design libraries sub-directories in the run
|
# The script will automatically create the design libraries sub-directories in the run
|
||||||
# directory, add the library logical mappings in the simulator setup file, create default
|
# directory, add the library logical mappings in the simulator setup file, create default
|
||||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||||
#
|
#
|
||||||
# Generated by Vivado on Mon Apr 17 13:38:36 CST 2023
|
# Generated by Vivado on Mon May 08 18:55:24 CST 2023
|
||||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||||
#
|
#
|
||||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
#
|
#
|
||||||
# usage: rom_hop_data.sh [-help]
|
# usage: rom_freq_word.sh [-help]
|
||||||
# usage: rom_hop_data.sh [-lib_map_path]
|
# usage: rom_freq_word.sh [-lib_map_path]
|
||||||
# usage: rom_hop_data.sh [-noclean_files]
|
# usage: rom_freq_word.sh [-noclean_files]
|
||||||
# usage: rom_hop_data.sh [-reset_run]
|
# usage: rom_freq_word.sh [-reset_run]
|
||||||
#
|
#
|
||||||
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
|
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
|
||||||
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
|
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
|
||||||
@@ -27,7 +27,7 @@
|
|||||||
#
|
#
|
||||||
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
|
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
|
||||||
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
|
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
|
||||||
# executing this script. Please type 'rom_hop_data.sh -help' for more information.
|
# executing this script. Please type 'rom_freq_word.sh -help' for more information.
|
||||||
#
|
#
|
||||||
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
|
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
|
||||||
#
|
#
|
||||||
@@ -54,7 +54,7 @@ design_libs=(xil_defaultlib xpm blk_mem_gen_v8_4_3)
|
|||||||
sim_lib_dir="ies_lib"
|
sim_lib_dir="ies_lib"
|
||||||
|
|
||||||
# Script info
|
# Script info
|
||||||
echo -e "rom_hop_data.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
|
echo -e "rom_freq_word.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
|
||||||
|
|
||||||
# Main steps
|
# Main steps
|
||||||
run()
|
run()
|
||||||
@@ -73,7 +73,7 @@ execute()
|
|||||||
-reflib "$ref_lib_dir/secureip:secureip" \
|
-reflib "$ref_lib_dir/secureip:secureip" \
|
||||||
-reflib "$ref_lib_dir/unimacro:unimacro" \
|
-reflib "$ref_lib_dir/unimacro:unimacro" \
|
||||||
-reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
|
-reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
|
||||||
-top xil_defaultlib.rom_hop_data \
|
-top xil_defaultlib.rom_freq_word \
|
||||||
-f run.f \
|
-f run.f \
|
||||||
-top glbl \
|
-top glbl \
|
||||||
glbl.v
|
glbl.v
|
||||||
@@ -85,7 +85,7 @@ setup()
|
|||||||
case $1 in
|
case $1 in
|
||||||
"-lib_map_path" )
|
"-lib_map_path" )
|
||||||
if [[ ($2 == "") ]]; then
|
if [[ ($2 == "") ]]; then
|
||||||
echo -e "ERROR: Simulation library directory path not specified (type \"./rom_hop_data.sh -help\" for more information)\n"
|
echo -e "ERROR: Simulation library directory path not specified (type \"./rom_freq_word.sh -help\" for more information)\n"
|
||||||
exit 1
|
exit 1
|
||||||
else
|
else
|
||||||
ref_lib_dir=$2
|
ref_lib_dir=$2
|
||||||
@@ -144,7 +144,7 @@ reset_run()
|
|||||||
check_args()
|
check_args()
|
||||||
{
|
{
|
||||||
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
||||||
echo -e "ERROR: Unknown option specified '$2' (type \"./rom_hop_data.sh -help\" for more information)\n"
|
echo -e "ERROR: Unknown option specified '$2' (type \"./rom_freq_word.sh -help\" for more information)\n"
|
||||||
exit 1
|
exit 1
|
||||||
fi
|
fi
|
||||||
|
|
||||||
@@ -156,10 +156,10 @@ check_args()
|
|||||||
# Script usage
|
# Script usage
|
||||||
usage()
|
usage()
|
||||||
{
|
{
|
||||||
msg="Usage: rom_hop_data.sh [-help]\n\
|
msg="Usage: rom_freq_word.sh [-help]\n\
|
||||||
Usage: rom_hop_data.sh [-lib_map_path]\n\
|
Usage: rom_freq_word.sh [-lib_map_path]\n\
|
||||||
Usage: rom_hop_data.sh [-reset_run]\n\
|
Usage: rom_freq_word.sh [-reset_run]\n\
|
||||||
Usage: rom_hop_data.sh [-noclean_files]\n\n\
|
Usage: rom_freq_word.sh [-noclean_files]\n\n\
|
||||||
[-help] -- Print help information for this script\n\n\
|
[-help] -- Print help information for this script\n\n\
|
||||||
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||||
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||||
+1
-1
@@ -9,7 +9,7 @@
|
|||||||
"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
|
"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
|
||||||
-endlib
|
-endlib
|
||||||
-makelib ies_lib/xil_defaultlib \
|
-makelib ies_lib/xil_defaultlib \
|
||||||
"../../../ip/rom_hop_data/sim/rom_hop_data.v" \
|
"../../../ip/rom_freq_word/sim/rom_freq_word.v" \
|
||||||
-endlib
|
-endlib
|
||||||
-makelib ies_lib/xil_defaultlib \
|
-makelib ies_lib/xil_defaultlib \
|
||||||
glbl.v
|
glbl.v
|
||||||
+49
@@ -0,0 +1,49 @@
|
|||||||
|
################################################################################
|
||||||
|
# Vivado (TM) v2019.1.3 (64-bit)
|
||||||
|
#
|
||||||
|
# README.txt: Please read the sections below to understand the steps required to
|
||||||
|
# run the exported script and information about the source files.
|
||||||
|
#
|
||||||
|
# Generated by export_simulation on Mon May 08 18:55:24 CST 2023
|
||||||
|
#
|
||||||
|
################################################################################
|
||||||
|
|
||||||
|
1. How to run the generated simulation script:-
|
||||||
|
|
||||||
|
From the shell prompt in the current directory, issue the following command:-
|
||||||
|
|
||||||
|
./rom_freq_word.sh
|
||||||
|
|
||||||
|
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||||
|
implemented in the script file for the 3-step flow. These functions are called
|
||||||
|
from the main 'run' function in the script file.
|
||||||
|
|
||||||
|
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||||
|
create simulator specific setup files, create design library mappings and library
|
||||||
|
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||||
|
current directory.
|
||||||
|
|
||||||
|
The 'setup' function is also used for removing the simulator generated data in
|
||||||
|
order to reset the current directory to the original state when export_simulation
|
||||||
|
was launched from Vivado. This generated data can be removed by specifying the
|
||||||
|
'-reset_run' switch to the './rom_freq_word.sh' script.
|
||||||
|
|
||||||
|
./rom_freq_word.sh -reset_run
|
||||||
|
|
||||||
|
To keep the generated data from the previous run but regenerate the setup files and
|
||||||
|
library directories, use the '-noclean_files' switch.
|
||||||
|
|
||||||
|
./rom_freq_word.sh -noclean_files
|
||||||
|
|
||||||
|
For more information on the script, please type './rom_freq_word.sh -help'.
|
||||||
|
|
||||||
|
2. Additional design information files:-
|
||||||
|
|
||||||
|
export_simulation generates following additional file that can be used for fetching
|
||||||
|
the design files information or for integrating with external custom scripts.
|
||||||
|
|
||||||
|
Name : file_info.txt
|
||||||
|
Purpose: This file contains detail design file information based on the compile order
|
||||||
|
when export_simulation was executed from Vivado. The file contains information
|
||||||
|
about the file type, name, whether it is part of the IP, associated library
|
||||||
|
and the file path information.
|
||||||
+1
-1
@@ -6,7 +6,7 @@ vlib modelsim_lib/msim/xil_defaultlib
|
|||||||
vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
|
vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
|
||||||
|
|
||||||
vlog -work xil_defaultlib -64 -incr \
|
vlog -work xil_defaultlib -64 -incr \
|
||||||
"../../../ip/rom_hop_data/sim/rom_hop_data.v" \
|
"../../../ip/rom_freq_word/sim/rom_freq_word.v" \
|
||||||
|
|
||||||
|
|
||||||
vlog -work xil_defaultlib \
|
vlog -work xil_defaultlib \
|
||||||
+2
@@ -0,0 +1,2 @@
|
|||||||
|
rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v,
|
||||||
|
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||||
Executable
+83
@@ -0,0 +1,83 @@
|
|||||||
|
MEMORY_INITIALIZATION_RADIX = 10;
|
||||||
|
MEMORY_INITIALIZATION_VECTOR =
|
||||||
|
1624,
|
||||||
|
1611,
|
||||||
|
1598,
|
||||||
|
1585,
|
||||||
|
1572,
|
||||||
|
1559,
|
||||||
|
1546,
|
||||||
|
1533,
|
||||||
|
1520,
|
||||||
|
1507,
|
||||||
|
1494,
|
||||||
|
1481,
|
||||||
|
1468,
|
||||||
|
1455,
|
||||||
|
1442,
|
||||||
|
1429,
|
||||||
|
1416,
|
||||||
|
1403,
|
||||||
|
1390,
|
||||||
|
1377,
|
||||||
|
1364,
|
||||||
|
1351,
|
||||||
|
1338,
|
||||||
|
1325,
|
||||||
|
1312,
|
||||||
|
1299,
|
||||||
|
1286,
|
||||||
|
1273,
|
||||||
|
1260,
|
||||||
|
1247,
|
||||||
|
1234,
|
||||||
|
1221,
|
||||||
|
1208,
|
||||||
|
1195,
|
||||||
|
1182,
|
||||||
|
1169,
|
||||||
|
1156,
|
||||||
|
1143,
|
||||||
|
1130,
|
||||||
|
1117,
|
||||||
|
1104,
|
||||||
|
1091,
|
||||||
|
1078,
|
||||||
|
1065,
|
||||||
|
1052,
|
||||||
|
1039,
|
||||||
|
1026,
|
||||||
|
1013,
|
||||||
|
1000,
|
||||||
|
987,
|
||||||
|
974,
|
||||||
|
961,
|
||||||
|
948,
|
||||||
|
935,
|
||||||
|
922,
|
||||||
|
909,
|
||||||
|
896,
|
||||||
|
883,
|
||||||
|
870,
|
||||||
|
857,
|
||||||
|
844,
|
||||||
|
831,
|
||||||
|
818,
|
||||||
|
805,
|
||||||
|
792,
|
||||||
|
779,
|
||||||
|
766,
|
||||||
|
753,
|
||||||
|
740,
|
||||||
|
727,
|
||||||
|
714,
|
||||||
|
701,
|
||||||
|
688,
|
||||||
|
675,
|
||||||
|
662,
|
||||||
|
649,
|
||||||
|
636,
|
||||||
|
623,
|
||||||
|
610,
|
||||||
|
597,
|
||||||
|
584,
|
||||||
+81
@@ -0,0 +1,81 @@
|
|||||||
|
11001011000
|
||||||
|
11001001011
|
||||||
|
11000111110
|
||||||
|
11000110001
|
||||||
|
11000100100
|
||||||
|
11000010111
|
||||||
|
11000001010
|
||||||
|
10111111101
|
||||||
|
10111110000
|
||||||
|
10111100011
|
||||||
|
10111010110
|
||||||
|
10111001001
|
||||||
|
10110111100
|
||||||
|
10110101111
|
||||||
|
10110100010
|
||||||
|
10110010101
|
||||||
|
10110001000
|
||||||
|
10101111011
|
||||||
|
10101101110
|
||||||
|
10101100001
|
||||||
|
10101010100
|
||||||
|
10101000111
|
||||||
|
10100111010
|
||||||
|
10100101101
|
||||||
|
10100100000
|
||||||
|
10100010011
|
||||||
|
10100000110
|
||||||
|
10011111001
|
||||||
|
10011101100
|
||||||
|
10011011111
|
||||||
|
10011010010
|
||||||
|
10011000101
|
||||||
|
10010111000
|
||||||
|
10010101011
|
||||||
|
10010011110
|
||||||
|
10010010001
|
||||||
|
10010000100
|
||||||
|
10001110111
|
||||||
|
10001101010
|
||||||
|
10001011101
|
||||||
|
10001010000
|
||||||
|
10001000011
|
||||||
|
10000110110
|
||||||
|
10000101001
|
||||||
|
10000011100
|
||||||
|
10000001111
|
||||||
|
10000000010
|
||||||
|
01111110101
|
||||||
|
01111101000
|
||||||
|
01111011011
|
||||||
|
01111001110
|
||||||
|
01111000001
|
||||||
|
01110110100
|
||||||
|
01110100111
|
||||||
|
01110011010
|
||||||
|
01110001101
|
||||||
|
01110000000
|
||||||
|
01101110011
|
||||||
|
01101100110
|
||||||
|
01101011001
|
||||||
|
01101001100
|
||||||
|
01100111111
|
||||||
|
01100110010
|
||||||
|
01100100101
|
||||||
|
01100011000
|
||||||
|
01100001011
|
||||||
|
01011111110
|
||||||
|
01011110001
|
||||||
|
01011100100
|
||||||
|
01011010111
|
||||||
|
01011001010
|
||||||
|
01010111101
|
||||||
|
01010110000
|
||||||
|
01010100011
|
||||||
|
01010010110
|
||||||
|
01010001001
|
||||||
|
01001111100
|
||||||
|
01001101111
|
||||||
|
01001100010
|
||||||
|
01001010101
|
||||||
|
01001001000
|
||||||
Executable
+167
@@ -0,0 +1,167 @@
|
|||||||
|
#!/bin/bash -f
|
||||||
|
#*********************************************************************************************************
|
||||||
|
# Vivado (TM) v2019.1.3 (64-bit)
|
||||||
|
#
|
||||||
|
# Filename : rom_freq_word.sh
|
||||||
|
# Simulator : Mentor Graphics ModelSim Simulator
|
||||||
|
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
||||||
|
# The script will automatically create the design libraries sub-directories in the run
|
||||||
|
# directory, add the library logical mappings in the simulator setup file, create default
|
||||||
|
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||||
|
#
|
||||||
|
# Generated by Vivado on Mon May 08 18:55:24 CST 2023
|
||||||
|
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||||
|
#
|
||||||
|
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
#
|
||||||
|
# usage: rom_freq_word.sh [-help]
|
||||||
|
# usage: rom_freq_word.sh [-lib_map_path]
|
||||||
|
# usage: rom_freq_word.sh [-noclean_files]
|
||||||
|
# usage: rom_freq_word.sh [-reset_run]
|
||||||
|
#
|
||||||
|
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
|
||||||
|
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
|
||||||
|
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
|
||||||
|
# that points to these libraries and rerun export_simulation. For more information about this switch please
|
||||||
|
# type 'export_simulation -help' in the Tcl shell.
|
||||||
|
#
|
||||||
|
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
|
||||||
|
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
|
||||||
|
# executing this script. Please type 'rom_freq_word.sh -help' for more information.
|
||||||
|
#
|
||||||
|
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
|
||||||
|
#
|
||||||
|
#*********************************************************************************************************
|
||||||
|
|
||||||
|
|
||||||
|
# Script info
|
||||||
|
echo -e "rom_freq_word.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
|
||||||
|
|
||||||
|
# Main steps
|
||||||
|
run()
|
||||||
|
{
|
||||||
|
check_args $# $1
|
||||||
|
setup $1 $2
|
||||||
|
compile
|
||||||
|
simulate
|
||||||
|
}
|
||||||
|
|
||||||
|
# RUN_STEP: <compile>
|
||||||
|
compile()
|
||||||
|
{
|
||||||
|
# Compile design files
|
||||||
|
source compile.do 2>&1 | tee -a compile.log
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
# RUN_STEP: <simulate>
|
||||||
|
simulate()
|
||||||
|
{
|
||||||
|
vsim -64 -c -do "do {simulate.do}" -l simulate.log
|
||||||
|
}
|
||||||
|
|
||||||
|
# STEP: setup
|
||||||
|
setup()
|
||||||
|
{
|
||||||
|
case $1 in
|
||||||
|
"-lib_map_path" )
|
||||||
|
if [[ ($2 == "") ]]; then
|
||||||
|
echo -e "ERROR: Simulation library directory path not specified (type \"./rom_freq_word.sh -help\" for more information)\n"
|
||||||
|
exit 1
|
||||||
|
fi
|
||||||
|
copy_setup_file $2
|
||||||
|
;;
|
||||||
|
"-reset_run" )
|
||||||
|
reset_run
|
||||||
|
echo -e "INFO: Simulation run files deleted.\n"
|
||||||
|
exit 0
|
||||||
|
;;
|
||||||
|
"-noclean_files" )
|
||||||
|
# do not remove previous data
|
||||||
|
;;
|
||||||
|
* )
|
||||||
|
copy_setup_file $2
|
||||||
|
esac
|
||||||
|
|
||||||
|
create_lib_dir
|
||||||
|
|
||||||
|
# Add any setup/initialization commands here:-
|
||||||
|
|
||||||
|
# <user specific commands>
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
# Copy modelsim.ini file
|
||||||
|
copy_setup_file()
|
||||||
|
{
|
||||||
|
file="modelsim.ini"
|
||||||
|
if [[ ($1 != "") ]]; then
|
||||||
|
lib_map_path="$1"
|
||||||
|
else
|
||||||
|
lib_map_path="/home/josh/Software/Xilinx/CompLib/Model/2019.1"
|
||||||
|
fi
|
||||||
|
if [[ ($lib_map_path != "") ]]; then
|
||||||
|
src_file="$lib_map_path/$file"
|
||||||
|
cp $src_file .
|
||||||
|
fi
|
||||||
|
}
|
||||||
|
|
||||||
|
# Create design library directory
|
||||||
|
create_lib_dir()
|
||||||
|
{
|
||||||
|
lib_dir="modelsim_lib"
|
||||||
|
if [[ -e $lib_dir ]]; then
|
||||||
|
rm -rf $lib_dir
|
||||||
|
fi
|
||||||
|
|
||||||
|
mkdir $lib_dir
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
# Delete generated data from the previous run
|
||||||
|
reset_run()
|
||||||
|
{
|
||||||
|
files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib)
|
||||||
|
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||||
|
file="${files_to_remove[i]}"
|
||||||
|
if [[ -e $file ]]; then
|
||||||
|
rm -rf $file
|
||||||
|
fi
|
||||||
|
done
|
||||||
|
|
||||||
|
create_lib_dir
|
||||||
|
}
|
||||||
|
|
||||||
|
# Check command line arguments
|
||||||
|
check_args()
|
||||||
|
{
|
||||||
|
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
||||||
|
echo -e "ERROR: Unknown option specified '$2' (type \"./rom_freq_word.sh -help\" for more information)\n"
|
||||||
|
exit 1
|
||||||
|
fi
|
||||||
|
|
||||||
|
if [[ ($2 == "-help" || $2 == "-h") ]]; then
|
||||||
|
usage
|
||||||
|
fi
|
||||||
|
}
|
||||||
|
|
||||||
|
# Script usage
|
||||||
|
usage()
|
||||||
|
{
|
||||||
|
msg="Usage: rom_freq_word.sh [-help]\n\
|
||||||
|
Usage: rom_freq_word.sh [-lib_map_path]\n\
|
||||||
|
Usage: rom_freq_word.sh [-reset_run]\n\
|
||||||
|
Usage: rom_freq_word.sh [-noclean_files]\n\n\
|
||||||
|
[-help] -- Print help information for this script\n\n\
|
||||||
|
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||||
|
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||||
|
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
|
||||||
|
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
|
||||||
|
-noclean_files switch.\n\n\
|
||||||
|
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
|
||||||
|
echo -e $msg
|
||||||
|
exit 1
|
||||||
|
}
|
||||||
|
|
||||||
|
# Launch script
|
||||||
|
run $1 $2
|
||||||
+2
-2
@@ -1,7 +1,7 @@
|
|||||||
onbreak {quit -f}
|
onbreak {quit -f}
|
||||||
onerror {quit -f}
|
onerror {quit -f}
|
||||||
|
|
||||||
vsim -voptargs="+acc" -t 1ps -L blk_mem_gen_v8_4_3 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.rom_hop_data xil_defaultlib.glbl
|
vsim -voptargs="+acc" -t 1ps -L blk_mem_gen_v8_4_3 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.rom_freq_word xil_defaultlib.glbl
|
||||||
|
|
||||||
do {wave.do}
|
do {wave.do}
|
||||||
|
|
||||||
@@ -9,7 +9,7 @@ view wave
|
|||||||
view structure
|
view structure
|
||||||
view signals
|
view signals
|
||||||
|
|
||||||
do {rom_hop_data.udo}
|
do {rom_freq_word.udo}
|
||||||
|
|
||||||
run -all
|
run -all
|
||||||
|
|
||||||
+49
@@ -0,0 +1,49 @@
|
|||||||
|
################################################################################
|
||||||
|
# Vivado (TM) v2019.1.3 (64-bit)
|
||||||
|
#
|
||||||
|
# README.txt: Please read the sections below to understand the steps required to
|
||||||
|
# run the exported script and information about the source files.
|
||||||
|
#
|
||||||
|
# Generated by export_simulation on Mon May 08 18:55:24 CST 2023
|
||||||
|
#
|
||||||
|
################################################################################
|
||||||
|
|
||||||
|
1. How to run the generated simulation script:-
|
||||||
|
|
||||||
|
From the shell prompt in the current directory, issue the following command:-
|
||||||
|
|
||||||
|
./rom_freq_word.sh
|
||||||
|
|
||||||
|
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||||
|
implemented in the script file for the 3-step flow. These functions are called
|
||||||
|
from the main 'run' function in the script file.
|
||||||
|
|
||||||
|
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||||
|
create simulator specific setup files, create design library mappings and library
|
||||||
|
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||||
|
current directory.
|
||||||
|
|
||||||
|
The 'setup' function is also used for removing the simulator generated data in
|
||||||
|
order to reset the current directory to the original state when export_simulation
|
||||||
|
was launched from Vivado. This generated data can be removed by specifying the
|
||||||
|
'-reset_run' switch to the './rom_freq_word.sh' script.
|
||||||
|
|
||||||
|
./rom_freq_word.sh -reset_run
|
||||||
|
|
||||||
|
To keep the generated data from the previous run but regenerate the setup files and
|
||||||
|
library directories, use the '-noclean_files' switch.
|
||||||
|
|
||||||
|
./rom_freq_word.sh -noclean_files
|
||||||
|
|
||||||
|
For more information on the script, please type './rom_freq_word.sh -help'.
|
||||||
|
|
||||||
|
2. Additional design information files:-
|
||||||
|
|
||||||
|
export_simulation generates following additional file that can be used for fetching
|
||||||
|
the design files information or for integrating with external custom scripts.
|
||||||
|
|
||||||
|
Name : file_info.txt
|
||||||
|
Purpose: This file contains detail design file information based on the compile order
|
||||||
|
when export_simulation was executed from Vivado. The file contains information
|
||||||
|
about the file type, name, whether it is part of the IP, associated library
|
||||||
|
and the file path information.
|
||||||
+1
-1
@@ -20,7 +20,7 @@ vlog -work blk_mem_gen_v8_4_3 -64 \
|
|||||||
"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
|
"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
|
||||||
|
|
||||||
vlog -work xil_defaultlib -64 \
|
vlog -work xil_defaultlib -64 \
|
||||||
"../../../ip/rom_hop_data/sim/rom_hop_data.v" \
|
"../../../ip/rom_freq_word/sim/rom_freq_word.v" \
|
||||||
|
|
||||||
vlog -work xil_defaultlib \
|
vlog -work xil_defaultlib \
|
||||||
"glbl.v"
|
"glbl.v"
|
||||||
+1
-1
@@ -1 +1 @@
|
|||||||
vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L blk_mem_gen_v8_4_3 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.rom_hop_data xil_defaultlib.glbl -o rom_hop_data_opt
|
vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L blk_mem_gen_v8_4_3 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.rom_freq_word xil_defaultlib.glbl -o rom_freq_word_opt
|
||||||
+1
-1
@@ -2,5 +2,5 @@ xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tool
|
|||||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||||
blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
|
blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
|
||||||
rom_hop_data.v,verilog,xil_defaultlib,../../../ip/rom_hop_data/sim/rom_hop_data.v,
|
rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v,
|
||||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||||
Executable
+83
@@ -0,0 +1,83 @@
|
|||||||
|
MEMORY_INITIALIZATION_RADIX = 10;
|
||||||
|
MEMORY_INITIALIZATION_VECTOR =
|
||||||
|
1624,
|
||||||
|
1611,
|
||||||
|
1598,
|
||||||
|
1585,
|
||||||
|
1572,
|
||||||
|
1559,
|
||||||
|
1546,
|
||||||
|
1533,
|
||||||
|
1520,
|
||||||
|
1507,
|
||||||
|
1494,
|
||||||
|
1481,
|
||||||
|
1468,
|
||||||
|
1455,
|
||||||
|
1442,
|
||||||
|
1429,
|
||||||
|
1416,
|
||||||
|
1403,
|
||||||
|
1390,
|
||||||
|
1377,
|
||||||
|
1364,
|
||||||
|
1351,
|
||||||
|
1338,
|
||||||
|
1325,
|
||||||
|
1312,
|
||||||
|
1299,
|
||||||
|
1286,
|
||||||
|
1273,
|
||||||
|
1260,
|
||||||
|
1247,
|
||||||
|
1234,
|
||||||
|
1221,
|
||||||
|
1208,
|
||||||
|
1195,
|
||||||
|
1182,
|
||||||
|
1169,
|
||||||
|
1156,
|
||||||
|
1143,
|
||||||
|
1130,
|
||||||
|
1117,
|
||||||
|
1104,
|
||||||
|
1091,
|
||||||
|
1078,
|
||||||
|
1065,
|
||||||
|
1052,
|
||||||
|
1039,
|
||||||
|
1026,
|
||||||
|
1013,
|
||||||
|
1000,
|
||||||
|
987,
|
||||||
|
974,
|
||||||
|
961,
|
||||||
|
948,
|
||||||
|
935,
|
||||||
|
922,
|
||||||
|
909,
|
||||||
|
896,
|
||||||
|
883,
|
||||||
|
870,
|
||||||
|
857,
|
||||||
|
844,
|
||||||
|
831,
|
||||||
|
818,
|
||||||
|
805,
|
||||||
|
792,
|
||||||
|
779,
|
||||||
|
766,
|
||||||
|
753,
|
||||||
|
740,
|
||||||
|
727,
|
||||||
|
714,
|
||||||
|
701,
|
||||||
|
688,
|
||||||
|
675,
|
||||||
|
662,
|
||||||
|
649,
|
||||||
|
636,
|
||||||
|
623,
|
||||||
|
610,
|
||||||
|
597,
|
||||||
|
584,
|
||||||
+81
@@ -0,0 +1,81 @@
|
|||||||
|
11001011000
|
||||||
|
11001001011
|
||||||
|
11000111110
|
||||||
|
11000110001
|
||||||
|
11000100100
|
||||||
|
11000010111
|
||||||
|
11000001010
|
||||||
|
10111111101
|
||||||
|
10111110000
|
||||||
|
10111100011
|
||||||
|
10111010110
|
||||||
|
10111001001
|
||||||
|
10110111100
|
||||||
|
10110101111
|
||||||
|
10110100010
|
||||||
|
10110010101
|
||||||
|
10110001000
|
||||||
|
10101111011
|
||||||
|
10101101110
|
||||||
|
10101100001
|
||||||
|
10101010100
|
||||||
|
10101000111
|
||||||
|
10100111010
|
||||||
|
10100101101
|
||||||
|
10100100000
|
||||||
|
10100010011
|
||||||
|
10100000110
|
||||||
|
10011111001
|
||||||
|
10011101100
|
||||||
|
10011011111
|
||||||
|
10011010010
|
||||||
|
10011000101
|
||||||
|
10010111000
|
||||||
|
10010101011
|
||||||
|
10010011110
|
||||||
|
10010010001
|
||||||
|
10010000100
|
||||||
|
10001110111
|
||||||
|
10001101010
|
||||||
|
10001011101
|
||||||
|
10001010000
|
||||||
|
10001000011
|
||||||
|
10000110110
|
||||||
|
10000101001
|
||||||
|
10000011100
|
||||||
|
10000001111
|
||||||
|
10000000010
|
||||||
|
01111110101
|
||||||
|
01111101000
|
||||||
|
01111011011
|
||||||
|
01111001110
|
||||||
|
01111000001
|
||||||
|
01110110100
|
||||||
|
01110100111
|
||||||
|
01110011010
|
||||||
|
01110001101
|
||||||
|
01110000000
|
||||||
|
01101110011
|
||||||
|
01101100110
|
||||||
|
01101011001
|
||||||
|
01101001100
|
||||||
|
01100111111
|
||||||
|
01100110010
|
||||||
|
01100100101
|
||||||
|
01100011000
|
||||||
|
01100001011
|
||||||
|
01011111110
|
||||||
|
01011110001
|
||||||
|
01011100100
|
||||||
|
01011010111
|
||||||
|
01011001010
|
||||||
|
01010111101
|
||||||
|
01010110000
|
||||||
|
01010100011
|
||||||
|
01010010110
|
||||||
|
01010001001
|
||||||
|
01001111100
|
||||||
|
01001101111
|
||||||
|
01001100010
|
||||||
|
01001010101
|
||||||
|
01001001000
|
||||||
Executable
+174
@@ -0,0 +1,174 @@
|
|||||||
|
#!/bin/bash -f
|
||||||
|
#*********************************************************************************************************
|
||||||
|
# Vivado (TM) v2019.1.3 (64-bit)
|
||||||
|
#
|
||||||
|
# Filename : rom_freq_word.sh
|
||||||
|
# Simulator : Mentor Graphics Questa Advanced Simulator
|
||||||
|
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
||||||
|
# The script will automatically create the design libraries sub-directories in the run
|
||||||
|
# directory, add the library logical mappings in the simulator setup file, create default
|
||||||
|
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||||
|
#
|
||||||
|
# Generated by Vivado on Mon May 08 18:55:24 CST 2023
|
||||||
|
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||||
|
#
|
||||||
|
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
#
|
||||||
|
# usage: rom_freq_word.sh [-help]
|
||||||
|
# usage: rom_freq_word.sh [-lib_map_path]
|
||||||
|
# usage: rom_freq_word.sh [-noclean_files]
|
||||||
|
# usage: rom_freq_word.sh [-reset_run]
|
||||||
|
#
|
||||||
|
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
|
||||||
|
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
|
||||||
|
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
|
||||||
|
# that points to these libraries and rerun export_simulation. For more information about this switch please
|
||||||
|
# type 'export_simulation -help' in the Tcl shell.
|
||||||
|
#
|
||||||
|
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
|
||||||
|
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
|
||||||
|
# executing this script. Please type 'rom_freq_word.sh -help' for more information.
|
||||||
|
#
|
||||||
|
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
|
||||||
|
#
|
||||||
|
#*********************************************************************************************************
|
||||||
|
|
||||||
|
|
||||||
|
# Script info
|
||||||
|
echo -e "rom_freq_word.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
|
||||||
|
|
||||||
|
# Main steps
|
||||||
|
run()
|
||||||
|
{
|
||||||
|
check_args $# $1
|
||||||
|
setup $1 $2
|
||||||
|
compile
|
||||||
|
elaborate
|
||||||
|
simulate
|
||||||
|
}
|
||||||
|
|
||||||
|
# RUN_STEP: <compile>
|
||||||
|
compile()
|
||||||
|
{
|
||||||
|
# Compile design files
|
||||||
|
source compile.do 2>&1 | tee -a compile.log
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
# RUN_STEP: <elaborate>
|
||||||
|
elaborate()
|
||||||
|
{
|
||||||
|
source elaborate.do 2>&1 | tee -a elaborate.log
|
||||||
|
}
|
||||||
|
|
||||||
|
# RUN_STEP: <simulate>
|
||||||
|
simulate()
|
||||||
|
{
|
||||||
|
vsim -64 -c -do "do {simulate.do}" -l simulate.log
|
||||||
|
}
|
||||||
|
|
||||||
|
# STEP: setup
|
||||||
|
setup()
|
||||||
|
{
|
||||||
|
case $1 in
|
||||||
|
"-lib_map_path" )
|
||||||
|
if [[ ($2 == "") ]]; then
|
||||||
|
echo -e "ERROR: Simulation library directory path not specified (type \"./rom_freq_word.sh -help\" for more information)\n"
|
||||||
|
exit 1
|
||||||
|
fi
|
||||||
|
copy_setup_file $2
|
||||||
|
;;
|
||||||
|
"-reset_run" )
|
||||||
|
reset_run
|
||||||
|
echo -e "INFO: Simulation run files deleted.\n"
|
||||||
|
exit 0
|
||||||
|
;;
|
||||||
|
"-noclean_files" )
|
||||||
|
# do not remove previous data
|
||||||
|
;;
|
||||||
|
* )
|
||||||
|
copy_setup_file $2
|
||||||
|
esac
|
||||||
|
|
||||||
|
create_lib_dir
|
||||||
|
|
||||||
|
# Add any setup/initialization commands here:-
|
||||||
|
|
||||||
|
# <user specific commands>
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
# Copy modelsim.ini file
|
||||||
|
copy_setup_file()
|
||||||
|
{
|
||||||
|
file="modelsim.ini"
|
||||||
|
if [[ ($1 != "") ]]; then
|
||||||
|
lib_map_path="$1"
|
||||||
|
else
|
||||||
|
lib_map_path="/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa"
|
||||||
|
fi
|
||||||
|
if [[ ($lib_map_path != "") ]]; then
|
||||||
|
src_file="$lib_map_path/$file"
|
||||||
|
cp $src_file .
|
||||||
|
fi
|
||||||
|
}
|
||||||
|
|
||||||
|
# Create design library directory
|
||||||
|
create_lib_dir()
|
||||||
|
{
|
||||||
|
lib_dir="questa_lib"
|
||||||
|
if [[ -e $lib_dir ]]; then
|
||||||
|
rm -rf $lib_dir
|
||||||
|
fi
|
||||||
|
|
||||||
|
mkdir $lib_dir
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
# Delete generated data from the previous run
|
||||||
|
reset_run()
|
||||||
|
{
|
||||||
|
files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib)
|
||||||
|
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||||
|
file="${files_to_remove[i]}"
|
||||||
|
if [[ -e $file ]]; then
|
||||||
|
rm -rf $file
|
||||||
|
fi
|
||||||
|
done
|
||||||
|
|
||||||
|
create_lib_dir
|
||||||
|
}
|
||||||
|
|
||||||
|
# Check command line arguments
|
||||||
|
check_args()
|
||||||
|
{
|
||||||
|
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
||||||
|
echo -e "ERROR: Unknown option specified '$2' (type \"./rom_freq_word.sh -help\" for more information)\n"
|
||||||
|
exit 1
|
||||||
|
fi
|
||||||
|
|
||||||
|
if [[ ($2 == "-help" || $2 == "-h") ]]; then
|
||||||
|
usage
|
||||||
|
fi
|
||||||
|
}
|
||||||
|
|
||||||
|
# Script usage
|
||||||
|
usage()
|
||||||
|
{
|
||||||
|
msg="Usage: rom_freq_word.sh [-help]\n\
|
||||||
|
Usage: rom_freq_word.sh [-lib_map_path]\n\
|
||||||
|
Usage: rom_freq_word.sh [-reset_run]\n\
|
||||||
|
Usage: rom_freq_word.sh [-noclean_files]\n\n\
|
||||||
|
[-help] -- Print help information for this script\n\n\
|
||||||
|
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||||
|
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||||
|
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
|
||||||
|
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
|
||||||
|
-noclean_files switch.\n\n\
|
||||||
|
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
|
||||||
|
echo -e $msg
|
||||||
|
exit 1
|
||||||
|
}
|
||||||
|
|
||||||
|
# Launch script
|
||||||
|
run $1 $2
|
||||||
+2
-2
@@ -1,7 +1,7 @@
|
|||||||
onbreak {quit -f}
|
onbreak {quit -f}
|
||||||
onerror {quit -f}
|
onerror {quit -f}
|
||||||
|
|
||||||
vsim -t 1ps -lib xil_defaultlib vio_null_phase_opt
|
vsim -t 1ps -lib xil_defaultlib rom_freq_word_opt
|
||||||
|
|
||||||
do {wave.do}
|
do {wave.do}
|
||||||
|
|
||||||
@@ -9,7 +9,7 @@ view wave
|
|||||||
view structure
|
view structure
|
||||||
view signals
|
view signals
|
||||||
|
|
||||||
do {vio_null_phase.udo}
|
do {rom_freq_word.udo}
|
||||||
|
|
||||||
run -all
|
run -all
|
||||||
|
|
||||||
+49
@@ -0,0 +1,49 @@
|
|||||||
|
################################################################################
|
||||||
|
# Vivado (TM) v2019.1.3 (64-bit)
|
||||||
|
#
|
||||||
|
# README.txt: Please read the sections below to understand the steps required to
|
||||||
|
# run the exported script and information about the source files.
|
||||||
|
#
|
||||||
|
# Generated by export_simulation on Mon May 08 18:55:24 CST 2023
|
||||||
|
#
|
||||||
|
################################################################################
|
||||||
|
|
||||||
|
1. How to run the generated simulation script:-
|
||||||
|
|
||||||
|
From the shell prompt in the current directory, issue the following command:-
|
||||||
|
|
||||||
|
./rom_freq_word.sh
|
||||||
|
|
||||||
|
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||||
|
implemented in the script file for the 3-step flow. These functions are called
|
||||||
|
from the main 'run' function in the script file.
|
||||||
|
|
||||||
|
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||||
|
create simulator specific setup files, create design library mappings and library
|
||||||
|
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||||
|
current directory.
|
||||||
|
|
||||||
|
The 'setup' function is also used for removing the simulator generated data in
|
||||||
|
order to reset the current directory to the original state when export_simulation
|
||||||
|
was launched from Vivado. This generated data can be removed by specifying the
|
||||||
|
'-reset_run' switch to the './rom_freq_word.sh' script.
|
||||||
|
|
||||||
|
./rom_freq_word.sh -reset_run
|
||||||
|
|
||||||
|
To keep the generated data from the previous run but regenerate the setup files and
|
||||||
|
library directories, use the '-noclean_files' switch.
|
||||||
|
|
||||||
|
./rom_freq_word.sh -noclean_files
|
||||||
|
|
||||||
|
For more information on the script, please type './rom_freq_word.sh -help'.
|
||||||
|
|
||||||
|
2. Additional design information files:-
|
||||||
|
|
||||||
|
export_simulation generates following additional file that can be used for fetching
|
||||||
|
the design files information or for integrating with external custom scripts.
|
||||||
|
|
||||||
|
Name : file_info.txt
|
||||||
|
Purpose: This file contains detail design file information based on the compile order
|
||||||
|
when export_simulation was executed from Vivado. The file contains information
|
||||||
|
about the file type, name, whether it is part of the IP, associated library
|
||||||
|
and the file path information.
|
||||||
+1
-1
@@ -20,7 +20,7 @@ vlog -work blk_mem_gen_v8_4_3 -v2k5 \
|
|||||||
"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
|
"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
|
||||||
|
|
||||||
vlog -work xil_defaultlib -v2k5 \
|
vlog -work xil_defaultlib -v2k5 \
|
||||||
"../../../ip/rom_hop_data/sim/rom_hop_data.v" \
|
"../../../ip/rom_freq_word/sim/rom_freq_word.v" \
|
||||||
|
|
||||||
vlog -work xil_defaultlib \
|
vlog -work xil_defaultlib \
|
||||||
"glbl.v"
|
"glbl.v"
|
||||||
+1
-1
@@ -2,5 +2,5 @@ xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tool
|
|||||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||||
blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
|
blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
|
||||||
rom_hop_data.v,verilog,xil_defaultlib,../../../ip/rom_hop_data/sim/rom_hop_data.v,
|
rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v,
|
||||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||||
Executable
+83
@@ -0,0 +1,83 @@
|
|||||||
|
MEMORY_INITIALIZATION_RADIX = 10;
|
||||||
|
MEMORY_INITIALIZATION_VECTOR =
|
||||||
|
1624,
|
||||||
|
1611,
|
||||||
|
1598,
|
||||||
|
1585,
|
||||||
|
1572,
|
||||||
|
1559,
|
||||||
|
1546,
|
||||||
|
1533,
|
||||||
|
1520,
|
||||||
|
1507,
|
||||||
|
1494,
|
||||||
|
1481,
|
||||||
|
1468,
|
||||||
|
1455,
|
||||||
|
1442,
|
||||||
|
1429,
|
||||||
|
1416,
|
||||||
|
1403,
|
||||||
|
1390,
|
||||||
|
1377,
|
||||||
|
1364,
|
||||||
|
1351,
|
||||||
|
1338,
|
||||||
|
1325,
|
||||||
|
1312,
|
||||||
|
1299,
|
||||||
|
1286,
|
||||||
|
1273,
|
||||||
|
1260,
|
||||||
|
1247,
|
||||||
|
1234,
|
||||||
|
1221,
|
||||||
|
1208,
|
||||||
|
1195,
|
||||||
|
1182,
|
||||||
|
1169,
|
||||||
|
1156,
|
||||||
|
1143,
|
||||||
|
1130,
|
||||||
|
1117,
|
||||||
|
1104,
|
||||||
|
1091,
|
||||||
|
1078,
|
||||||
|
1065,
|
||||||
|
1052,
|
||||||
|
1039,
|
||||||
|
1026,
|
||||||
|
1013,
|
||||||
|
1000,
|
||||||
|
987,
|
||||||
|
974,
|
||||||
|
961,
|
||||||
|
948,
|
||||||
|
935,
|
||||||
|
922,
|
||||||
|
909,
|
||||||
|
896,
|
||||||
|
883,
|
||||||
|
870,
|
||||||
|
857,
|
||||||
|
844,
|
||||||
|
831,
|
||||||
|
818,
|
||||||
|
805,
|
||||||
|
792,
|
||||||
|
779,
|
||||||
|
766,
|
||||||
|
753,
|
||||||
|
740,
|
||||||
|
727,
|
||||||
|
714,
|
||||||
|
701,
|
||||||
|
688,
|
||||||
|
675,
|
||||||
|
662,
|
||||||
|
649,
|
||||||
|
636,
|
||||||
|
623,
|
||||||
|
610,
|
||||||
|
597,
|
||||||
|
584,
|
||||||
+81
@@ -0,0 +1,81 @@
|
|||||||
|
11001011000
|
||||||
|
11001001011
|
||||||
|
11000111110
|
||||||
|
11000110001
|
||||||
|
11000100100
|
||||||
|
11000010111
|
||||||
|
11000001010
|
||||||
|
10111111101
|
||||||
|
10111110000
|
||||||
|
10111100011
|
||||||
|
10111010110
|
||||||
|
10111001001
|
||||||
|
10110111100
|
||||||
|
10110101111
|
||||||
|
10110100010
|
||||||
|
10110010101
|
||||||
|
10110001000
|
||||||
|
10101111011
|
||||||
|
10101101110
|
||||||
|
10101100001
|
||||||
|
10101010100
|
||||||
|
10101000111
|
||||||
|
10100111010
|
||||||
|
10100101101
|
||||||
|
10100100000
|
||||||
|
10100010011
|
||||||
|
10100000110
|
||||||
|
10011111001
|
||||||
|
10011101100
|
||||||
|
10011011111
|
||||||
|
10011010010
|
||||||
|
10011000101
|
||||||
|
10010111000
|
||||||
|
10010101011
|
||||||
|
10010011110
|
||||||
|
10010010001
|
||||||
|
10010000100
|
||||||
|
10001110111
|
||||||
|
10001101010
|
||||||
|
10001011101
|
||||||
|
10001010000
|
||||||
|
10001000011
|
||||||
|
10000110110
|
||||||
|
10000101001
|
||||||
|
10000011100
|
||||||
|
10000001111
|
||||||
|
10000000010
|
||||||
|
01111110101
|
||||||
|
01111101000
|
||||||
|
01111011011
|
||||||
|
01111001110
|
||||||
|
01111000001
|
||||||
|
01110110100
|
||||||
|
01110100111
|
||||||
|
01110011010
|
||||||
|
01110001101
|
||||||
|
01110000000
|
||||||
|
01101110011
|
||||||
|
01101100110
|
||||||
|
01101011001
|
||||||
|
01101001100
|
||||||
|
01100111111
|
||||||
|
01100110010
|
||||||
|
01100100101
|
||||||
|
01100011000
|
||||||
|
01100001011
|
||||||
|
01011111110
|
||||||
|
01011110001
|
||||||
|
01011100100
|
||||||
|
01011010111
|
||||||
|
01011001010
|
||||||
|
01010111101
|
||||||
|
01010110000
|
||||||
|
01010100011
|
||||||
|
01010010110
|
||||||
|
01010001001
|
||||||
|
01001111100
|
||||||
|
01001101111
|
||||||
|
01001100010
|
||||||
|
01001010101
|
||||||
|
01001001000
|
||||||
Executable
+153
@@ -0,0 +1,153 @@
|
|||||||
|
#!/bin/bash -f
|
||||||
|
#*********************************************************************************************************
|
||||||
|
# Vivado (TM) v2019.1.3 (64-bit)
|
||||||
|
#
|
||||||
|
# Filename : rom_freq_word.sh
|
||||||
|
# Simulator : Aldec Riviera-PRO Simulator
|
||||||
|
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
||||||
|
# The script will automatically create the design libraries sub-directories in the run
|
||||||
|
# directory, add the library logical mappings in the simulator setup file, create default
|
||||||
|
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||||
|
#
|
||||||
|
# Generated by Vivado on Mon May 08 18:55:24 CST 2023
|
||||||
|
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||||
|
#
|
||||||
|
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
|
#
|
||||||
|
# usage: rom_freq_word.sh [-help]
|
||||||
|
# usage: rom_freq_word.sh [-lib_map_path]
|
||||||
|
# usage: rom_freq_word.sh [-noclean_files]
|
||||||
|
# usage: rom_freq_word.sh [-reset_run]
|
||||||
|
#
|
||||||
|
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
|
||||||
|
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
|
||||||
|
# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
|
||||||
|
# that points to these libraries and rerun export_simulation. For more information about this switch please
|
||||||
|
# type 'export_simulation -help' in the Tcl shell.
|
||||||
|
#
|
||||||
|
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
|
||||||
|
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
|
||||||
|
# executing this script. Please type 'rom_freq_word.sh -help' for more information.
|
||||||
|
#
|
||||||
|
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
|
||||||
|
#
|
||||||
|
#*********************************************************************************************************
|
||||||
|
|
||||||
|
|
||||||
|
# Script info
|
||||||
|
echo -e "rom_freq_word.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
|
||||||
|
|
||||||
|
# Main steps
|
||||||
|
run()
|
||||||
|
{
|
||||||
|
check_args $# $1
|
||||||
|
setup $1 $2
|
||||||
|
compile
|
||||||
|
simulate
|
||||||
|
}
|
||||||
|
|
||||||
|
# RUN_STEP: <compile>
|
||||||
|
compile()
|
||||||
|
{
|
||||||
|
# Compile design files
|
||||||
|
source compile.do 2>&1 | tee -a compile.log
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
# RUN_STEP: <simulate>
|
||||||
|
simulate()
|
||||||
|
{
|
||||||
|
runvsimsa -l simulate.log -do "do {simulate.do}"
|
||||||
|
}
|
||||||
|
|
||||||
|
# STEP: setup
|
||||||
|
setup()
|
||||||
|
{
|
||||||
|
case $1 in
|
||||||
|
"-lib_map_path" )
|
||||||
|
if [[ ($2 == "") ]]; then
|
||||||
|
echo -e "ERROR: Simulation library directory path not specified (type \"./rom_freq_word.sh -help\" for more information)\n"
|
||||||
|
exit 1
|
||||||
|
fi
|
||||||
|
map_setup_file $2
|
||||||
|
;;
|
||||||
|
"-reset_run" )
|
||||||
|
reset_run
|
||||||
|
echo -e "INFO: Simulation run files deleted.\n"
|
||||||
|
exit 0
|
||||||
|
;;
|
||||||
|
"-noclean_files" )
|
||||||
|
# do not remove previous data
|
||||||
|
;;
|
||||||
|
* )
|
||||||
|
map_setup_file $2
|
||||||
|
esac
|
||||||
|
|
||||||
|
# Add any setup/initialization commands here:-
|
||||||
|
|
||||||
|
# <user specific commands>
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
# Map library.cfg file
|
||||||
|
map_setup_file()
|
||||||
|
{
|
||||||
|
file="library.cfg"
|
||||||
|
if [[ ($1 != "") ]]; then
|
||||||
|
lib_map_path="$1"
|
||||||
|
else
|
||||||
|
lib_map_path="/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera"
|
||||||
|
fi
|
||||||
|
if [[ ($lib_map_path != "") ]]; then
|
||||||
|
src_file="$lib_map_path/$file"
|
||||||
|
if [[ -e $src_file ]]; then
|
||||||
|
vmap -link $lib_map_path
|
||||||
|
fi
|
||||||
|
fi
|
||||||
|
}
|
||||||
|
|
||||||
|
# Delete generated data from the previous run
|
||||||
|
reset_run()
|
||||||
|
{
|
||||||
|
files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera)
|
||||||
|
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||||
|
file="${files_to_remove[i]}"
|
||||||
|
if [[ -e $file ]]; then
|
||||||
|
rm -rf $file
|
||||||
|
fi
|
||||||
|
done
|
||||||
|
}
|
||||||
|
|
||||||
|
# Check command line arguments
|
||||||
|
check_args()
|
||||||
|
{
|
||||||
|
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
||||||
|
echo -e "ERROR: Unknown option specified '$2' (type \"./rom_freq_word.sh -help\" for more information)\n"
|
||||||
|
exit 1
|
||||||
|
fi
|
||||||
|
|
||||||
|
if [[ ($2 == "-help" || $2 == "-h") ]]; then
|
||||||
|
usage
|
||||||
|
fi
|
||||||
|
}
|
||||||
|
|
||||||
|
# Script usage
|
||||||
|
usage()
|
||||||
|
{
|
||||||
|
msg="Usage: rom_freq_word.sh [-help]\n\
|
||||||
|
Usage: rom_freq_word.sh [-lib_map_path]\n\
|
||||||
|
Usage: rom_freq_word.sh [-reset_run]\n\
|
||||||
|
Usage: rom_freq_word.sh [-noclean_files]\n\n\
|
||||||
|
[-help] -- Print help information for this script\n\n\
|
||||||
|
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||||
|
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||||
|
[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
|
||||||
|
from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
|
||||||
|
-noclean_files switch.\n\n\
|
||||||
|
[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
|
||||||
|
echo -e $msg
|
||||||
|
exit 1
|
||||||
|
}
|
||||||
|
|
||||||
|
# Launch script
|
||||||
|
run $1 $2
|
||||||
+17
@@ -0,0 +1,17 @@
|
|||||||
|
onbreak {quit -force}
|
||||||
|
onerror {quit -force}
|
||||||
|
|
||||||
|
asim -t 1ps +access +r +m+rom_freq_word -L xil_defaultlib -L xpm -L blk_mem_gen_v8_4_3 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.rom_freq_word xil_defaultlib.glbl
|
||||||
|
|
||||||
|
do {wave.do}
|
||||||
|
|
||||||
|
view wave
|
||||||
|
view structure
|
||||||
|
|
||||||
|
do {rom_freq_word.udo}
|
||||||
|
|
||||||
|
run -all
|
||||||
|
|
||||||
|
endsim
|
||||||
|
|
||||||
|
quit -force
|
||||||
+49
@@ -0,0 +1,49 @@
|
|||||||
|
################################################################################
|
||||||
|
# Vivado (TM) v2019.1.3 (64-bit)
|
||||||
|
#
|
||||||
|
# README.txt: Please read the sections below to understand the steps required to
|
||||||
|
# run the exported script and information about the source files.
|
||||||
|
#
|
||||||
|
# Generated by export_simulation on Mon May 08 18:55:24 CST 2023
|
||||||
|
#
|
||||||
|
################################################################################
|
||||||
|
|
||||||
|
1. How to run the generated simulation script:-
|
||||||
|
|
||||||
|
From the shell prompt in the current directory, issue the following command:-
|
||||||
|
|
||||||
|
./rom_freq_word.sh
|
||||||
|
|
||||||
|
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||||
|
implemented in the script file for the 3-step flow. These functions are called
|
||||||
|
from the main 'run' function in the script file.
|
||||||
|
|
||||||
|
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||||
|
create simulator specific setup files, create design library mappings and library
|
||||||
|
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||||
|
current directory.
|
||||||
|
|
||||||
|
The 'setup' function is also used for removing the simulator generated data in
|
||||||
|
order to reset the current directory to the original state when export_simulation
|
||||||
|
was launched from Vivado. This generated data can be removed by specifying the
|
||||||
|
'-reset_run' switch to the './rom_freq_word.sh' script.
|
||||||
|
|
||||||
|
./rom_freq_word.sh -reset_run
|
||||||
|
|
||||||
|
To keep the generated data from the previous run but regenerate the setup files and
|
||||||
|
library directories, use the '-noclean_files' switch.
|
||||||
|
|
||||||
|
./rom_freq_word.sh -noclean_files
|
||||||
|
|
||||||
|
For more information on the script, please type './rom_freq_word.sh -help'.
|
||||||
|
|
||||||
|
2. Additional design information files:-
|
||||||
|
|
||||||
|
export_simulation generates following additional file that can be used for fetching
|
||||||
|
the design files information or for integrating with external custom scripts.
|
||||||
|
|
||||||
|
Name : file_info.txt
|
||||||
|
Purpose: This file contains detail design file information based on the compile order
|
||||||
|
when export_simulation was executed from Vivado. The file contains information
|
||||||
|
about the file type, name, whether it is part of the IP, associated library
|
||||||
|
and the file path information.
|
||||||
+2
@@ -0,0 +1,2 @@
|
|||||||
|
rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v,
|
||||||
|
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||||
Executable
+83
@@ -0,0 +1,83 @@
|
|||||||
|
MEMORY_INITIALIZATION_RADIX = 10;
|
||||||
|
MEMORY_INITIALIZATION_VECTOR =
|
||||||
|
1624,
|
||||||
|
1611,
|
||||||
|
1598,
|
||||||
|
1585,
|
||||||
|
1572,
|
||||||
|
1559,
|
||||||
|
1546,
|
||||||
|
1533,
|
||||||
|
1520,
|
||||||
|
1507,
|
||||||
|
1494,
|
||||||
|
1481,
|
||||||
|
1468,
|
||||||
|
1455,
|
||||||
|
1442,
|
||||||
|
1429,
|
||||||
|
1416,
|
||||||
|
1403,
|
||||||
|
1390,
|
||||||
|
1377,
|
||||||
|
1364,
|
||||||
|
1351,
|
||||||
|
1338,
|
||||||
|
1325,
|
||||||
|
1312,
|
||||||
|
1299,
|
||||||
|
1286,
|
||||||
|
1273,
|
||||||
|
1260,
|
||||||
|
1247,
|
||||||
|
1234,
|
||||||
|
1221,
|
||||||
|
1208,
|
||||||
|
1195,
|
||||||
|
1182,
|
||||||
|
1169,
|
||||||
|
1156,
|
||||||
|
1143,
|
||||||
|
1130,
|
||||||
|
1117,
|
||||||
|
1104,
|
||||||
|
1091,
|
||||||
|
1078,
|
||||||
|
1065,
|
||||||
|
1052,
|
||||||
|
1039,
|
||||||
|
1026,
|
||||||
|
1013,
|
||||||
|
1000,
|
||||||
|
987,
|
||||||
|
974,
|
||||||
|
961,
|
||||||
|
948,
|
||||||
|
935,
|
||||||
|
922,
|
||||||
|
909,
|
||||||
|
896,
|
||||||
|
883,
|
||||||
|
870,
|
||||||
|
857,
|
||||||
|
844,
|
||||||
|
831,
|
||||||
|
818,
|
||||||
|
805,
|
||||||
|
792,
|
||||||
|
779,
|
||||||
|
766,
|
||||||
|
753,
|
||||||
|
740,
|
||||||
|
727,
|
||||||
|
714,
|
||||||
|
701,
|
||||||
|
688,
|
||||||
|
675,
|
||||||
|
662,
|
||||||
|
649,
|
||||||
|
636,
|
||||||
|
623,
|
||||||
|
610,
|
||||||
|
597,
|
||||||
|
584,
|
||||||
+81
@@ -0,0 +1,81 @@
|
|||||||
|
11001011000
|
||||||
|
11001001011
|
||||||
|
11000111110
|
||||||
|
11000110001
|
||||||
|
11000100100
|
||||||
|
11000010111
|
||||||
|
11000001010
|
||||||
|
10111111101
|
||||||
|
10111110000
|
||||||
|
10111100011
|
||||||
|
10111010110
|
||||||
|
10111001001
|
||||||
|
10110111100
|
||||||
|
10110101111
|
||||||
|
10110100010
|
||||||
|
10110010101
|
||||||
|
10110001000
|
||||||
|
10101111011
|
||||||
|
10101101110
|
||||||
|
10101100001
|
||||||
|
10101010100
|
||||||
|
10101000111
|
||||||
|
10100111010
|
||||||
|
10100101101
|
||||||
|
10100100000
|
||||||
|
10100010011
|
||||||
|
10100000110
|
||||||
|
10011111001
|
||||||
|
10011101100
|
||||||
|
10011011111
|
||||||
|
10011010010
|
||||||
|
10011000101
|
||||||
|
10010111000
|
||||||
|
10010101011
|
||||||
|
10010011110
|
||||||
|
10010010001
|
||||||
|
10010000100
|
||||||
|
10001110111
|
||||||
|
10001101010
|
||||||
|
10001011101
|
||||||
|
10001010000
|
||||||
|
10001000011
|
||||||
|
10000110110
|
||||||
|
10000101001
|
||||||
|
10000011100
|
||||||
|
10000001111
|
||||||
|
10000000010
|
||||||
|
01111110101
|
||||||
|
01111101000
|
||||||
|
01111011011
|
||||||
|
01111001110
|
||||||
|
01111000001
|
||||||
|
01110110100
|
||||||
|
01110100111
|
||||||
|
01110011010
|
||||||
|
01110001101
|
||||||
|
01110000000
|
||||||
|
01101110011
|
||||||
|
01101100110
|
||||||
|
01101011001
|
||||||
|
01101001100
|
||||||
|
01100111111
|
||||||
|
01100110010
|
||||||
|
01100100101
|
||||||
|
01100011000
|
||||||
|
01100001011
|
||||||
|
01011111110
|
||||||
|
01011110001
|
||||||
|
01011100100
|
||||||
|
01011010111
|
||||||
|
01011001010
|
||||||
|
01010111101
|
||||||
|
01010110000
|
||||||
|
01010100011
|
||||||
|
01010010110
|
||||||
|
01010001001
|
||||||
|
01001111100
|
||||||
|
01001101111
|
||||||
|
01001100010
|
||||||
|
01001010101
|
||||||
|
01001001000
|
||||||
+18
-18
@@ -2,22 +2,22 @@
|
|||||||
#*********************************************************************************************************
|
#*********************************************************************************************************
|
||||||
# Vivado (TM) v2019.1.3 (64-bit)
|
# Vivado (TM) v2019.1.3 (64-bit)
|
||||||
#
|
#
|
||||||
# Filename : rom_hop_data.sh
|
# Filename : rom_freq_word.sh
|
||||||
# Simulator : Synopsys Verilog Compiler Simulator
|
# Simulator : Synopsys Verilog Compiler Simulator
|
||||||
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
||||||
# The script will automatically create the design libraries sub-directories in the run
|
# The script will automatically create the design libraries sub-directories in the run
|
||||||
# directory, add the library logical mappings in the simulator setup file, create default
|
# directory, add the library logical mappings in the simulator setup file, create default
|
||||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||||
#
|
#
|
||||||
# Generated by Vivado on Mon Apr 17 13:38:36 CST 2023
|
# Generated by Vivado on Mon May 08 18:55:24 CST 2023
|
||||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||||
#
|
#
|
||||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
#
|
#
|
||||||
# usage: rom_hop_data.sh [-help]
|
# usage: rom_freq_word.sh [-help]
|
||||||
# usage: rom_hop_data.sh [-lib_map_path]
|
# usage: rom_freq_word.sh [-lib_map_path]
|
||||||
# usage: rom_hop_data.sh [-noclean_files]
|
# usage: rom_freq_word.sh [-noclean_files]
|
||||||
# usage: rom_hop_data.sh [-reset_run]
|
# usage: rom_freq_word.sh [-reset_run]
|
||||||
#
|
#
|
||||||
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
|
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
|
||||||
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
|
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
|
||||||
@@ -27,7 +27,7 @@
|
|||||||
#
|
#
|
||||||
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
|
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
|
||||||
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
|
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
|
||||||
# executing this script. Please type 'rom_hop_data.sh -help' for more information.
|
# executing this script. Please type 'rom_freq_word.sh -help' for more information.
|
||||||
#
|
#
|
||||||
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
|
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
|
||||||
#
|
#
|
||||||
@@ -54,7 +54,7 @@ design_libs=(xil_defaultlib)
|
|||||||
sim_lib_dir="vcs_lib"
|
sim_lib_dir="vcs_lib"
|
||||||
|
|
||||||
# Script info
|
# Script info
|
||||||
echo -e "rom_hop_data.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
|
echo -e "rom_freq_word.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
|
||||||
|
|
||||||
# Main steps
|
# Main steps
|
||||||
run()
|
run()
|
||||||
@@ -71,7 +71,7 @@ compile()
|
|||||||
{
|
{
|
||||||
# Compile design files
|
# Compile design files
|
||||||
vlogan -work xil_defaultlib $vlogan_opts +v2k \
|
vlogan -work xil_defaultlib $vlogan_opts +v2k \
|
||||||
"$ref_dir/../../../ip/rom_hop_data/sim/rom_hop_data.v" \
|
"$ref_dir/../../../ip/rom_freq_word/sim/rom_freq_word.v" \
|
||||||
2>&1 | tee -a vlogan.log
|
2>&1 | tee -a vlogan.log
|
||||||
|
|
||||||
|
|
||||||
@@ -84,13 +84,13 @@ compile()
|
|||||||
# RUN_STEP: <elaborate>
|
# RUN_STEP: <elaborate>
|
||||||
elaborate()
|
elaborate()
|
||||||
{
|
{
|
||||||
vcs $vcs_elab_opts xil_defaultlib.rom_hop_data xil_defaultlib.glbl -o rom_hop_data_simv
|
vcs $vcs_elab_opts xil_defaultlib.rom_freq_word xil_defaultlib.glbl -o rom_freq_word_simv
|
||||||
}
|
}
|
||||||
|
|
||||||
# RUN_STEP: <simulate>
|
# RUN_STEP: <simulate>
|
||||||
simulate()
|
simulate()
|
||||||
{
|
{
|
||||||
./rom_hop_data_simv $vcs_sim_opts -do simulate.do
|
./rom_freq_word_simv $vcs_sim_opts -do simulate.do
|
||||||
}
|
}
|
||||||
|
|
||||||
# STEP: setup
|
# STEP: setup
|
||||||
@@ -99,7 +99,7 @@ setup()
|
|||||||
case $1 in
|
case $1 in
|
||||||
"-lib_map_path" )
|
"-lib_map_path" )
|
||||||
if [[ ($2 == "") ]]; then
|
if [[ ($2 == "") ]]; then
|
||||||
echo -e "ERROR: Simulation library directory path not specified (type \"./rom_hop_data.sh -help\" for more information)\n"
|
echo -e "ERROR: Simulation library directory path not specified (type \"./rom_freq_word.sh -help\" for more information)\n"
|
||||||
exit 1
|
exit 1
|
||||||
fi
|
fi
|
||||||
create_lib_mappings $2
|
create_lib_mappings $2
|
||||||
@@ -175,7 +175,7 @@ create_lib_dir()
|
|||||||
# Delete generated data from the previous run
|
# Delete generated data from the previous run
|
||||||
reset_run()
|
reset_run()
|
||||||
{
|
{
|
||||||
files_to_remove=(ucli.key rom_hop_data_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc rom_hop_data_simv.daidir)
|
files_to_remove=(ucli.key rom_freq_word_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc rom_freq_word_simv.daidir)
|
||||||
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
for (( i=0; i<${#files_to_remove[*]}; i++ )); do
|
||||||
file="${files_to_remove[i]}"
|
file="${files_to_remove[i]}"
|
||||||
if [[ -e $file ]]; then
|
if [[ -e $file ]]; then
|
||||||
@@ -190,7 +190,7 @@ reset_run()
|
|||||||
check_args()
|
check_args()
|
||||||
{
|
{
|
||||||
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
||||||
echo -e "ERROR: Unknown option specified '$2' (type \"./rom_hop_data.sh -help\" for more information)\n"
|
echo -e "ERROR: Unknown option specified '$2' (type \"./rom_freq_word.sh -help\" for more information)\n"
|
||||||
exit 1
|
exit 1
|
||||||
fi
|
fi
|
||||||
|
|
||||||
@@ -202,10 +202,10 @@ check_args()
|
|||||||
# Script usage
|
# Script usage
|
||||||
usage()
|
usage()
|
||||||
{
|
{
|
||||||
msg="Usage: rom_hop_data.sh [-help]\n\
|
msg="Usage: rom_freq_word.sh [-help]\n\
|
||||||
Usage: rom_hop_data.sh [-lib_map_path]\n\
|
Usage: rom_freq_word.sh [-lib_map_path]\n\
|
||||||
Usage: rom_hop_data.sh [-reset_run]\n\
|
Usage: rom_freq_word.sh [-reset_run]\n\
|
||||||
Usage: rom_hop_data.sh [-noclean_files]\n\n\
|
Usage: rom_freq_word.sh [-noclean_files]\n\n\
|
||||||
[-help] -- Print help information for this script\n\n\
|
[-help] -- Print help information for this script\n\n\
|
||||||
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||||
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||||
+48
@@ -0,0 +1,48 @@
|
|||||||
|
################################################################################
|
||||||
|
# Vivado (TM) v2019.1.3 (64-bit)
|
||||||
|
#
|
||||||
|
# README.txt: Please read the sections below to understand the steps required to
|
||||||
|
# run the exported script and information about the source files.
|
||||||
|
#
|
||||||
|
# Generated by export_simulation on Mon May 08 18:55:24 CST 2023
|
||||||
|
#
|
||||||
|
################################################################################
|
||||||
|
|
||||||
|
1. How to run the generated simulation script:-
|
||||||
|
|
||||||
|
From the shell prompt in the current directory, issue the following command:-
|
||||||
|
|
||||||
|
./rom_freq_word.sh
|
||||||
|
|
||||||
|
This command will launch the 'execute' function for the single-step flow. This
|
||||||
|
function is called from the main 'run' function in the script file.
|
||||||
|
|
||||||
|
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||||
|
create simulator specific setup files, create design library mappings and library
|
||||||
|
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||||
|
current directory.
|
||||||
|
|
||||||
|
The 'setup' function is also used for removing the simulator generated data in
|
||||||
|
order to reset the current directory to the original state when export_simulation
|
||||||
|
was launched from Vivado. This generated data can be removed by specifying the
|
||||||
|
'-reset_run' switch to the './rom_freq_word.sh' script.
|
||||||
|
|
||||||
|
./rom_freq_word.sh -reset_run
|
||||||
|
|
||||||
|
To keep the generated data from the previous run but regenerate the setup files and
|
||||||
|
library directories, use the '-noclean_files' switch.
|
||||||
|
|
||||||
|
./rom_freq_word.sh -noclean_files
|
||||||
|
|
||||||
|
For more information on the script, please type './rom_freq_word.sh -help'.
|
||||||
|
|
||||||
|
2. Additional design information files:-
|
||||||
|
|
||||||
|
export_simulation generates following additional file that can be used for fetching
|
||||||
|
the design files information or for integrating with external custom scripts.
|
||||||
|
|
||||||
|
Name : file_info.txt
|
||||||
|
Purpose: This file contains detail design file information based on the compile order
|
||||||
|
when export_simulation was executed from Vivado. The file contains information
|
||||||
|
about the file type, name, whether it is part of the IP, associated library
|
||||||
|
and the file path information.
|
||||||
+6
@@ -0,0 +1,6 @@
|
|||||||
|
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||||
|
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||||
|
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||||
|
blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
|
||||||
|
rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v,
|
||||||
|
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||||
Executable
+83
@@ -0,0 +1,83 @@
|
|||||||
|
MEMORY_INITIALIZATION_RADIX = 10;
|
||||||
|
MEMORY_INITIALIZATION_VECTOR =
|
||||||
|
1624,
|
||||||
|
1611,
|
||||||
|
1598,
|
||||||
|
1585,
|
||||||
|
1572,
|
||||||
|
1559,
|
||||||
|
1546,
|
||||||
|
1533,
|
||||||
|
1520,
|
||||||
|
1507,
|
||||||
|
1494,
|
||||||
|
1481,
|
||||||
|
1468,
|
||||||
|
1455,
|
||||||
|
1442,
|
||||||
|
1429,
|
||||||
|
1416,
|
||||||
|
1403,
|
||||||
|
1390,
|
||||||
|
1377,
|
||||||
|
1364,
|
||||||
|
1351,
|
||||||
|
1338,
|
||||||
|
1325,
|
||||||
|
1312,
|
||||||
|
1299,
|
||||||
|
1286,
|
||||||
|
1273,
|
||||||
|
1260,
|
||||||
|
1247,
|
||||||
|
1234,
|
||||||
|
1221,
|
||||||
|
1208,
|
||||||
|
1195,
|
||||||
|
1182,
|
||||||
|
1169,
|
||||||
|
1156,
|
||||||
|
1143,
|
||||||
|
1130,
|
||||||
|
1117,
|
||||||
|
1104,
|
||||||
|
1091,
|
||||||
|
1078,
|
||||||
|
1065,
|
||||||
|
1052,
|
||||||
|
1039,
|
||||||
|
1026,
|
||||||
|
1013,
|
||||||
|
1000,
|
||||||
|
987,
|
||||||
|
974,
|
||||||
|
961,
|
||||||
|
948,
|
||||||
|
935,
|
||||||
|
922,
|
||||||
|
909,
|
||||||
|
896,
|
||||||
|
883,
|
||||||
|
870,
|
||||||
|
857,
|
||||||
|
844,
|
||||||
|
831,
|
||||||
|
818,
|
||||||
|
805,
|
||||||
|
792,
|
||||||
|
779,
|
||||||
|
766,
|
||||||
|
753,
|
||||||
|
740,
|
||||||
|
727,
|
||||||
|
714,
|
||||||
|
701,
|
||||||
|
688,
|
||||||
|
675,
|
||||||
|
662,
|
||||||
|
649,
|
||||||
|
636,
|
||||||
|
623,
|
||||||
|
610,
|
||||||
|
597,
|
||||||
|
584,
|
||||||
+81
@@ -0,0 +1,81 @@
|
|||||||
|
11001011000
|
||||||
|
11001001011
|
||||||
|
11000111110
|
||||||
|
11000110001
|
||||||
|
11000100100
|
||||||
|
11000010111
|
||||||
|
11000001010
|
||||||
|
10111111101
|
||||||
|
10111110000
|
||||||
|
10111100011
|
||||||
|
10111010110
|
||||||
|
10111001001
|
||||||
|
10110111100
|
||||||
|
10110101111
|
||||||
|
10110100010
|
||||||
|
10110010101
|
||||||
|
10110001000
|
||||||
|
10101111011
|
||||||
|
10101101110
|
||||||
|
10101100001
|
||||||
|
10101010100
|
||||||
|
10101000111
|
||||||
|
10100111010
|
||||||
|
10100101101
|
||||||
|
10100100000
|
||||||
|
10100010011
|
||||||
|
10100000110
|
||||||
|
10011111001
|
||||||
|
10011101100
|
||||||
|
10011011111
|
||||||
|
10011010010
|
||||||
|
10011000101
|
||||||
|
10010111000
|
||||||
|
10010101011
|
||||||
|
10010011110
|
||||||
|
10010010001
|
||||||
|
10010000100
|
||||||
|
10001110111
|
||||||
|
10001101010
|
||||||
|
10001011101
|
||||||
|
10001010000
|
||||||
|
10001000011
|
||||||
|
10000110110
|
||||||
|
10000101001
|
||||||
|
10000011100
|
||||||
|
10000001111
|
||||||
|
10000000010
|
||||||
|
01111110101
|
||||||
|
01111101000
|
||||||
|
01111011011
|
||||||
|
01111001110
|
||||||
|
01111000001
|
||||||
|
01110110100
|
||||||
|
01110100111
|
||||||
|
01110011010
|
||||||
|
01110001101
|
||||||
|
01110000000
|
||||||
|
01101110011
|
||||||
|
01101100110
|
||||||
|
01101011001
|
||||||
|
01101001100
|
||||||
|
01100111111
|
||||||
|
01100110010
|
||||||
|
01100100101
|
||||||
|
01100011000
|
||||||
|
01100001011
|
||||||
|
01011111110
|
||||||
|
01011110001
|
||||||
|
01011100100
|
||||||
|
01011010111
|
||||||
|
01011001010
|
||||||
|
01010111101
|
||||||
|
01010110000
|
||||||
|
01010100011
|
||||||
|
01010010110
|
||||||
|
01010001001
|
||||||
|
01001111100
|
||||||
|
01001101111
|
||||||
|
01001100010
|
||||||
|
01001010101
|
||||||
|
01001001000
|
||||||
+15
-15
@@ -2,22 +2,22 @@
|
|||||||
#*********************************************************************************************************
|
#*********************************************************************************************************
|
||||||
# Vivado (TM) v2019.1.3 (64-bit)
|
# Vivado (TM) v2019.1.3 (64-bit)
|
||||||
#
|
#
|
||||||
# Filename : rom_hop_data.sh
|
# Filename : rom_freq_word.sh
|
||||||
# Simulator : Cadence Xcelium Parallel Simulator
|
# Simulator : Cadence Xcelium Parallel Simulator
|
||||||
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
# Description : Simulation script for compiling, elaborating and verifying the project source files.
|
||||||
# The script will automatically create the design libraries sub-directories in the run
|
# The script will automatically create the design libraries sub-directories in the run
|
||||||
# directory, add the library logical mappings in the simulator setup file, create default
|
# directory, add the library logical mappings in the simulator setup file, create default
|
||||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||||
#
|
#
|
||||||
# Generated by Vivado on Mon Apr 17 13:38:36 CST 2023
|
# Generated by Vivado on Mon May 08 18:55:24 CST 2023
|
||||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||||
#
|
#
|
||||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||||
#
|
#
|
||||||
# usage: rom_hop_data.sh [-help]
|
# usage: rom_freq_word.sh [-help]
|
||||||
# usage: rom_hop_data.sh [-lib_map_path]
|
# usage: rom_freq_word.sh [-lib_map_path]
|
||||||
# usage: rom_hop_data.sh [-noclean_files]
|
# usage: rom_freq_word.sh [-noclean_files]
|
||||||
# usage: rom_hop_data.sh [-reset_run]
|
# usage: rom_freq_word.sh [-reset_run]
|
||||||
#
|
#
|
||||||
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
|
# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
|
||||||
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
|
# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
|
||||||
@@ -27,7 +27,7 @@
|
|||||||
#
|
#
|
||||||
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
|
# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
|
||||||
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
|
# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
|
||||||
# executing this script. Please type 'rom_hop_data.sh -help' for more information.
|
# executing this script. Please type 'rom_freq_word.sh -help' for more information.
|
||||||
#
|
#
|
||||||
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
|
# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
|
||||||
#
|
#
|
||||||
@@ -54,7 +54,7 @@ design_libs=(xil_defaultlib xpm blk_mem_gen_v8_4_3)
|
|||||||
sim_lib_dir="xcelium_lib"
|
sim_lib_dir="xcelium_lib"
|
||||||
|
|
||||||
# Script info
|
# Script info
|
||||||
echo -e "rom_hop_data.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
|
echo -e "rom_freq_word.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
|
||||||
|
|
||||||
# Main steps
|
# Main steps
|
||||||
run()
|
run()
|
||||||
@@ -73,7 +73,7 @@ execute()
|
|||||||
-reflib "$ref_lib_dir/secureip:secureip" \
|
-reflib "$ref_lib_dir/secureip:secureip" \
|
||||||
-reflib "$ref_lib_dir/unimacro:unimacro" \
|
-reflib "$ref_lib_dir/unimacro:unimacro" \
|
||||||
-reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
|
-reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
|
||||||
-top xil_defaultlib.rom_hop_data \
|
-top xil_defaultlib.rom_freq_word \
|
||||||
-f run.f \
|
-f run.f \
|
||||||
-top glbl \
|
-top glbl \
|
||||||
glbl.v
|
glbl.v
|
||||||
@@ -85,7 +85,7 @@ setup()
|
|||||||
case $1 in
|
case $1 in
|
||||||
"-lib_map_path" )
|
"-lib_map_path" )
|
||||||
if [[ ($2 == "") ]]; then
|
if [[ ($2 == "") ]]; then
|
||||||
echo -e "ERROR: Simulation library directory path not specified (type \"./rom_hop_data.sh -help\" for more information)\n"
|
echo -e "ERROR: Simulation library directory path not specified (type \"./rom_freq_word.sh -help\" for more information)\n"
|
||||||
exit 1
|
exit 1
|
||||||
else
|
else
|
||||||
ref_lib_dir=$2
|
ref_lib_dir=$2
|
||||||
@@ -144,7 +144,7 @@ reset_run()
|
|||||||
check_args()
|
check_args()
|
||||||
{
|
{
|
||||||
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
|
||||||
echo -e "ERROR: Unknown option specified '$2' (type \"./rom_hop_data.sh -help\" for more information)\n"
|
echo -e "ERROR: Unknown option specified '$2' (type \"./rom_freq_word.sh -help\" for more information)\n"
|
||||||
exit 1
|
exit 1
|
||||||
fi
|
fi
|
||||||
|
|
||||||
@@ -156,10 +156,10 @@ check_args()
|
|||||||
# Script usage
|
# Script usage
|
||||||
usage()
|
usage()
|
||||||
{
|
{
|
||||||
msg="Usage: rom_hop_data.sh [-help]\n\
|
msg="Usage: rom_freq_word.sh [-help]\n\
|
||||||
Usage: rom_hop_data.sh [-lib_map_path]\n\
|
Usage: rom_freq_word.sh [-lib_map_path]\n\
|
||||||
Usage: rom_hop_data.sh [-reset_run]\n\
|
Usage: rom_freq_word.sh [-reset_run]\n\
|
||||||
Usage: rom_hop_data.sh [-noclean_files]\n\n\
|
Usage: rom_freq_word.sh [-noclean_files]\n\n\
|
||||||
[-help] -- Print help information for this script\n\n\
|
[-help] -- Print help information for this script\n\n\
|
||||||
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
|
||||||
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
|
||||||
+1
-1
@@ -9,7 +9,7 @@
|
|||||||
"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
|
"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
|
||||||
-endlib
|
-endlib
|
||||||
-makelib xcelium_lib/xil_defaultlib \
|
-makelib xcelium_lib/xil_defaultlib \
|
||||||
"../../../ip/rom_hop_data/sim/rom_hop_data.v" \
|
"../../../ip/rom_freq_word/sim/rom_freq_word.v" \
|
||||||
-endlib
|
-endlib
|
||||||
-makelib xcelium_lib/xil_defaultlib \
|
-makelib xcelium_lib/xil_defaultlib \
|
||||||
glbl.v
|
glbl.v
|
||||||
+49
@@ -0,0 +1,49 @@
|
|||||||
|
################################################################################
|
||||||
|
# Vivado (TM) v2019.1.3 (64-bit)
|
||||||
|
#
|
||||||
|
# README.txt: Please read the sections below to understand the steps required to
|
||||||
|
# run the exported script and information about the source files.
|
||||||
|
#
|
||||||
|
# Generated by export_simulation on Mon May 08 18:55:24 CST 2023
|
||||||
|
#
|
||||||
|
################################################################################
|
||||||
|
|
||||||
|
1. How to run the generated simulation script:-
|
||||||
|
|
||||||
|
From the shell prompt in the current directory, issue the following command:-
|
||||||
|
|
||||||
|
./rom_freq_word.sh
|
||||||
|
|
||||||
|
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||||
|
implemented in the script file for the 3-step flow. These functions are called
|
||||||
|
from the main 'run' function in the script file.
|
||||||
|
|
||||||
|
The 'run' function first executes the 'setup' function, the purpose of which is to
|
||||||
|
create simulator specific setup files, create design library mappings and library
|
||||||
|
directories and copy 'glbl.v' from the Vivado software install location into the
|
||||||
|
current directory.
|
||||||
|
|
||||||
|
The 'setup' function is also used for removing the simulator generated data in
|
||||||
|
order to reset the current directory to the original state when export_simulation
|
||||||
|
was launched from Vivado. This generated data can be removed by specifying the
|
||||||
|
'-reset_run' switch to the './rom_freq_word.sh' script.
|
||||||
|
|
||||||
|
./rom_freq_word.sh -reset_run
|
||||||
|
|
||||||
|
To keep the generated data from the previous run but regenerate the setup files and
|
||||||
|
library directories, use the '-noclean_files' switch.
|
||||||
|
|
||||||
|
./rom_freq_word.sh -noclean_files
|
||||||
|
|
||||||
|
For more information on the script, please type './rom_freq_word.sh -help'.
|
||||||
|
|
||||||
|
2. Additional design information files:-
|
||||||
|
|
||||||
|
export_simulation generates following additional file that can be used for fetching
|
||||||
|
the design files information or for integrating with external custom scripts.
|
||||||
|
|
||||||
|
Name : file_info.txt
|
||||||
|
Purpose: This file contains detail design file information based on the compile order
|
||||||
|
when export_simulation was executed from Vivado. The file contains information
|
||||||
|
about the file type, name, whether it is part of the IP, associated library
|
||||||
|
and the file path information.
|
||||||
+2
@@ -0,0 +1,2 @@
|
|||||||
|
rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v,
|
||||||
|
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||||
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Reference in New Issue
Block a user