Archived
major update to lcmv, to fit hop control
1. 调零算法部分增加调零控制模块,用于各模块互联和状态控制以及数据存储,增加LCMV和DAS选通; 2. Cordic 旋转输入改为保留两个符号位,避免溢出; 3. LCMV快拍数修改为2048; 4. 修改功率计算模块,适配较小数据位宽; 5. 修改在线捕获校准程序自动校准部分VIO初值; 6. 地检新射频发端增加自动频点切换
This commit is contained in:
+18
-12
@@ -48,7 +48,7 @@
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`timescale 1ns / 1ps
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module vio_phase_comp (
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clk,
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probe_in0,probe_in1,
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probe_in0,probe_in1,probe_in2,probe_in3,probe_in4,probe_in5,
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probe_out0,
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probe_out1,
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probe_out2,
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@@ -56,21 +56,27 @@ probe_out3,
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probe_out4,
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probe_out5,
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probe_out6,
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probe_out7
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probe_out7,
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probe_out8
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);
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input clk;
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input [31 : 0] probe_in0;
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input [0 : 0] probe_in1;
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input [0 : 0] probe_in0;
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input [31 : 0] probe_in1;
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input [31 : 0] probe_in2;
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input [31 : 0] probe_in3;
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input [31 : 0] probe_in4;
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input [31 : 0] probe_in5;
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output reg [0 : 0] probe_out0 = 'h0 ;
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output reg [0 : 0] probe_out1 = 'h0 ;
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output reg [0 : 0] probe_out2 = 'h1 ;
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output reg [0 : 0] probe_out3 = 'h0 ;
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output reg [15 : 0] probe_out4 = 'h0000 ;
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output reg [15 : 0] probe_out5 = 'h0000 ;
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output reg [15 : 0] probe_out6 = 'h0000 ;
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output reg [15 : 0] probe_out7 = 'h0000 ;
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output reg [15 : 0] probe_out0 = 'h0000 ;
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output reg [15 : 0] probe_out1 = 'h0000 ;
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output reg [15 : 0] probe_out2 = 'h0000 ;
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output reg [15 : 0] probe_out3 = 'h0000 ;
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output reg [0 : 0] probe_out4 = 'h0 ;
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output reg [0 : 0] probe_out5 = 'h1 ;
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output reg [0 : 0] probe_out6 = 'h0 ;
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output reg [0 : 0] probe_out7 = 'h0 ;
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output reg [0 : 0] probe_out8 = 'h0 ;
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endmodule
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+15
-10
@@ -56,16 +56,21 @@
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//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
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vio_phase_comp your_instance_name (
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.clk(clk), // input wire clk
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.probe_in0(probe_in0), // input wire [31 : 0] probe_in0
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.probe_in1(probe_in1), // input wire [0 : 0] probe_in1
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.probe_out0(probe_out0), // output wire [0 : 0] probe_out0
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.probe_out1(probe_out1), // output wire [0 : 0] probe_out1
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.probe_out2(probe_out2), // output wire [0 : 0] probe_out2
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.probe_out3(probe_out3), // output wire [0 : 0] probe_out3
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.probe_out4(probe_out4), // output wire [15 : 0] probe_out4
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.probe_out5(probe_out5), // output wire [15 : 0] probe_out5
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.probe_out6(probe_out6), // output wire [15 : 0] probe_out6
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.probe_out7(probe_out7) // output wire [15 : 0] probe_out7
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.probe_in0(probe_in0), // input wire [0 : 0] probe_in0
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.probe_in1(probe_in1), // input wire [31 : 0] probe_in1
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.probe_in2(probe_in2), // input wire [31 : 0] probe_in2
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.probe_in3(probe_in3), // input wire [31 : 0] probe_in3
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.probe_in4(probe_in4), // input wire [31 : 0] probe_in4
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.probe_in5(probe_in5), // input wire [31 : 0] probe_in5
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.probe_out0(probe_out0), // output wire [15 : 0] probe_out0
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.probe_out1(probe_out1), // output wire [15 : 0] probe_out1
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.probe_out2(probe_out2), // output wire [15 : 0] probe_out2
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.probe_out3(probe_out3), // output wire [15 : 0] probe_out3
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.probe_out4(probe_out4), // output wire [0 : 0] probe_out4
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.probe_out5(probe_out5), // output wire [0 : 0] probe_out5
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.probe_out6(probe_out6), // output wire [0 : 0] probe_out6
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.probe_out7(probe_out7), // output wire [0 : 0] probe_out7
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.probe_out8(probe_out8) // output wire [0 : 0] probe_out8
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);
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// INST_TAG_END ------ End INSTANTIATION Template ---------
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+21
-11
@@ -55,16 +55,21 @@
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COMPONENT vio_phase_comp
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PORT (
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clk : IN STD_LOGIC;
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probe_in0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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probe_in1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe_out1 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe_out2 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe_out3 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe_out4 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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probe_out5 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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probe_out6 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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probe_out7 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
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probe_in0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe_in1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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probe_in2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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probe_in3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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probe_in4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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probe_in5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
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probe_out0 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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probe_out1 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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probe_out2 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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probe_out3 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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probe_out4 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe_out5 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe_out6 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe_out7 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
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probe_out8 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
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);
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END COMPONENT;
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-- COMP_TAG_END ------ End COMPONENT Declaration ------------
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@@ -78,6 +83,10 @@ your_instance_name : vio_phase_comp
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clk => clk,
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probe_in0 => probe_in0,
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probe_in1 => probe_in1,
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probe_in2 => probe_in2,
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probe_in3 => probe_in3,
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probe_in4 => probe_in4,
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probe_in5 => probe_in5,
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probe_out0 => probe_out0,
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probe_out1 => probe_out1,
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probe_out2 => probe_out2,
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@@ -85,7 +94,8 @@ your_instance_name : vio_phase_comp
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probe_out4 => probe_out4,
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probe_out5 => probe_out5,
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probe_out6 => probe_out6,
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probe_out7 => probe_out7
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probe_out7 => probe_out7,
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probe_out8 => probe_out8
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);
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-- INST_TAG_END ------ End INSTANTIATION Template ---------
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BIN
Binary file not shown.
BIN
Binary file not shown.
+20
-14
@@ -1,7 +1,7 @@
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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// --------------------------------------------------------------------------------
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// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
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// Date : Thu Jun 15 10:54:16 2023
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// Date : Thu Jul 27 10:38:10 2023
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// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
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// Command : write_verilog -force -mode synth_stub
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// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.v
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@@ -14,18 +14,24 @@
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// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
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// Please paste the declaration into a Verilog source file or add the file as an additional source.
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(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
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module vio_phase_comp(clk, probe_in0, probe_in1, probe_out0,
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probe_out1, probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7)
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/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[31:0],probe_in1[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[0:0],probe_out3[0:0],probe_out4[15:0],probe_out5[15:0],probe_out6[15:0],probe_out7[15:0]" */;
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module vio_phase_comp(clk, probe_in0, probe_in1, probe_in2, probe_in3,
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probe_in4, probe_in5, probe_out0, probe_out1, probe_out2, probe_out3, probe_out4, probe_out5,
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probe_out6, probe_out7, probe_out8)
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/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_in1[31:0],probe_in2[31:0],probe_in3[31:0],probe_in4[31:0],probe_in5[31:0],probe_out0[15:0],probe_out1[15:0],probe_out2[15:0],probe_out3[15:0],probe_out4[0:0],probe_out5[0:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0]" */;
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input clk;
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input [31:0]probe_in0;
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input [0:0]probe_in1;
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output [0:0]probe_out0;
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output [0:0]probe_out1;
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output [0:0]probe_out2;
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output [0:0]probe_out3;
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output [15:0]probe_out4;
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output [15:0]probe_out5;
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output [15:0]probe_out6;
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output [15:0]probe_out7;
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input [0:0]probe_in0;
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input [31:0]probe_in1;
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input [31:0]probe_in2;
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input [31:0]probe_in3;
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input [31:0]probe_in4;
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input [31:0]probe_in5;
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output [15:0]probe_out0;
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output [15:0]probe_out1;
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output [15:0]probe_out2;
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output [15:0]probe_out3;
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output [0:0]probe_out4;
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output [0:0]probe_out5;
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output [0:0]probe_out6;
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output [0:0]probe_out7;
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output [0:0]probe_out8;
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endmodule
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+17
-12
@@ -1,7 +1,7 @@
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-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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-- --------------------------------------------------------------------------------
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-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
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-- Date : Thu Jun 15 10:54:16 2023
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-- Date : Thu Jul 27 10:38:10 2023
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-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
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-- Command : write_vhdl -force -mode synth_stub
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-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.vhdl
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@@ -15,16 +15,21 @@ use IEEE.STD_LOGIC_1164.ALL;
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entity vio_phase_comp is
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Port (
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clk : in STD_LOGIC;
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probe_in0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
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probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 );
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probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
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probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 );
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probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 );
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probe_out3 : out STD_LOGIC_VECTOR ( 0 to 0 );
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probe_out4 : out STD_LOGIC_VECTOR ( 15 downto 0 );
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probe_out5 : out STD_LOGIC_VECTOR ( 15 downto 0 );
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probe_out6 : out STD_LOGIC_VECTOR ( 15 downto 0 );
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probe_out7 : out STD_LOGIC_VECTOR ( 15 downto 0 )
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probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
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probe_in1 : in STD_LOGIC_VECTOR ( 31 downto 0 );
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probe_in2 : in STD_LOGIC_VECTOR ( 31 downto 0 );
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probe_in3 : in STD_LOGIC_VECTOR ( 31 downto 0 );
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probe_in4 : in STD_LOGIC_VECTOR ( 31 downto 0 );
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probe_in5 : in STD_LOGIC_VECTOR ( 31 downto 0 );
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probe_out0 : out STD_LOGIC_VECTOR ( 15 downto 0 );
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probe_out1 : out STD_LOGIC_VECTOR ( 15 downto 0 );
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probe_out2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
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probe_out3 : out STD_LOGIC_VECTOR ( 15 downto 0 );
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probe_out4 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
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probe_out5 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
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probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
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probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
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end vio_phase_comp;
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@@ -33,7 +38,7 @@ architecture stub of vio_phase_comp is
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||||
attribute syn_black_box : boolean;
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||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[31:0],probe_in1[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[0:0],probe_out3[0:0],probe_out4[15:0],probe_out5[15:0],probe_out6[15:0],probe_out7[15:0]";
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[0:0],probe_in1[31:0],probe_in2[31:0],probe_in3[31:0],probe_in4[31:0],probe_in5[31:0],probe_out0[15:0],probe_out1[15:0],probe_out2[15:0],probe_out3[15:0],probe_out4[0:0],probe_out5[0:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0]";
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||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
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begin
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||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
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||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
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||||
#
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# Generated by export_simulation on Thu Jun 15 10:53:59 CST 2023
|
||||
# Generated by export_simulation on Thu Jul 27 10:37:51 CST 2023
|
||||
#
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################################################################################
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+1
-1
@@ -9,7 +9,7 @@
|
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# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Thu Jun 15 10:53:59 CST 2023
|
||||
# Generated by Vivado on Thu Jul 27 10:37:51 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Thu Jun 15 10:53:59 CST 2023
|
||||
# Generated by export_simulation on Thu Jul 27 10:37:51 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Thu Jun 15 10:53:59 CST 2023
|
||||
# Generated by Vivado on Thu Jul 27 10:37:51 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Thu Jun 15 10:53:59 CST 2023
|
||||
# Generated by export_simulation on Thu Jul 27 10:37:51 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Thu Jun 15 10:53:59 CST 2023
|
||||
# Generated by Vivado on Thu Jul 27 10:37:51 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Thu Jun 15 10:53:59 CST 2023
|
||||
# Generated by export_simulation on Thu Jul 27 10:37:51 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Thu Jun 15 10:53:59 CST 2023
|
||||
# Generated by Vivado on Thu Jul 27 10:37:51 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Thu Jun 15 10:53:59 CST 2023
|
||||
# Generated by export_simulation on Thu Jul 27 10:37:51 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Thu Jun 15 10:53:59 CST 2023
|
||||
# Generated by Vivado on Thu Jul 27 10:37:51 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Thu Jun 15 10:53:59 CST 2023
|
||||
# Generated by export_simulation on Thu Jul 27 10:37:51 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Thu Jun 15 10:53:59 CST 2023
|
||||
# Generated by Vivado on Thu Jul 27 10:37:51 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Thu Jun 15 10:53:59 CST 2023
|
||||
# Generated by export_simulation on Thu Jul 27 10:37:51 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Thu Jun 15 10:53:59 CST 2023
|
||||
# Generated by Vivado on Thu Jul 27 10:37:51 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Thu Jun 15 10:53:59 CST 2023
|
||||
# Generated by export_simulation on Thu Jul 27 10:37:51 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Thu Jun 15 10:53:59 CST 2023
|
||||
# Generated by Vivado on Thu Jul 27 10:37:51 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+810
@@ -0,0 +1,810 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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||||
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||||
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BIN
Binary file not shown.
BIN
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BIN
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+37
@@ -0,0 +1,37 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Thu Jul 27 10:38:09 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_phase_comp_stub.v
|
||||
// Design : vio_phase_comp
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_in0, probe_in1, probe_in2, probe_in3,
|
||||
probe_in4, probe_in5, probe_out0, probe_out1, probe_out2, probe_out3, probe_out4, probe_out5,
|
||||
probe_out6, probe_out7, probe_out8)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_in1[31:0],probe_in2[31:0],probe_in3[31:0],probe_in4[31:0],probe_in5[31:0],probe_out0[15:0],probe_out1[15:0],probe_out2[15:0],probe_out3[15:0],probe_out4[0:0],probe_out5[0:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0]" */;
|
||||
input clk;
|
||||
input [0:0]probe_in0;
|
||||
input [31:0]probe_in1;
|
||||
input [31:0]probe_in2;
|
||||
input [31:0]probe_in3;
|
||||
input [31:0]probe_in4;
|
||||
input [31:0]probe_in5;
|
||||
output [15:0]probe_out0;
|
||||
output [15:0]probe_out1;
|
||||
output [15:0]probe_out2;
|
||||
output [15:0]probe_out3;
|
||||
output [0:0]probe_out4;
|
||||
output [0:0]probe_out5;
|
||||
output [0:0]probe_out6;
|
||||
output [0:0]probe_out7;
|
||||
output [0:0]probe_out8;
|
||||
endmodule
|
||||
+45
@@ -0,0 +1,45 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Thu Jul 27 10:38:09 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_phase_comp_stub.vhdl
|
||||
-- Design : vio_phase_comp
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_in1 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_in2 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_in3 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_in4 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_in5 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_out0 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out1 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out3 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out4 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out5 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[0:0],probe_in1[31:0],probe_in2[31:0],probe_in3[31:0],probe_in4[31:0],probe_in5[31:0],probe_out0[15:0],probe_out1[15:0],probe_out2[15:0],probe_out3[15:0],probe_out4[0:0],probe_out5[0:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+810
@@ -0,0 +1,810 @@
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||||
<?xml version="1.0" encoding="UTF-8"?>
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<spirit:vendor>xilinx.com</spirit:vendor>
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BIN
Binary file not shown.
BIN
Binary file not shown.
BIN
Binary file not shown.
+36
@@ -0,0 +1,36 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Thu Jul 27 10:36:54 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_phase_comp_stub.v
|
||||
// Design : vio_phase_comp
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_in0, probe_in1, probe_in2, probe_in3,
|
||||
probe_in4, probe_in5, probe_out0, probe_out1, probe_out2, probe_out3, probe_out4, probe_out5,
|
||||
probe_out6, probe_out7)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_in1[31:0],probe_in2[31:0],probe_in3[31:0],probe_in4[31:0],probe_in5[31:0],probe_out0[15:0],probe_out1[15:0],probe_out2[15:0],probe_out3[15:0],probe_out4[0:0],probe_out5[0:0],probe_out6[0:0],probe_out7[0:0]" */;
|
||||
input clk;
|
||||
input [0:0]probe_in0;
|
||||
input [31:0]probe_in1;
|
||||
input [31:0]probe_in2;
|
||||
input [31:0]probe_in3;
|
||||
input [31:0]probe_in4;
|
||||
input [31:0]probe_in5;
|
||||
output [15:0]probe_out0;
|
||||
output [15:0]probe_out1;
|
||||
output [15:0]probe_out2;
|
||||
output [15:0]probe_out3;
|
||||
output [0:0]probe_out4;
|
||||
output [0:0]probe_out5;
|
||||
output [0:0]probe_out6;
|
||||
output [0:0]probe_out7;
|
||||
endmodule
|
||||
+44
@@ -0,0 +1,44 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Thu Jul 27 10:36:54 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_phase_comp_stub.vhdl
|
||||
-- Design : vio_phase_comp
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_in1 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_in2 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_in3 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_in4 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_in5 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_out0 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out1 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out3 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out4 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out5 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[0:0],probe_in1[31:0],probe_in2[31:0],probe_in3[31:0],probe_in4[31:0],probe_in5[31:0],probe_out0[15:0],probe_out1[15:0],probe_out2[15:0],probe_out3[15:0],probe_out4[0:0],probe_out5[0:0],probe_out6[0:0],probe_out7[0:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+9
-9
@@ -1,29 +1,29 @@
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||||
version:1
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eof:2845626422
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||||
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+4
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
|
||||
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|
||||
version:1
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||||
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||||
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|
||||
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|
||||
|
||||
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-4
@@ -33,7 +33,7 @@ version:1
|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
eof:3042245255
|
||||
|
||||
+14
-14
@@ -3,7 +3,7 @@
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pa" timeStamp="Thu Jun 15 10:58:41 2023">
|
||||
<application name="pa" timeStamp="Thu Jul 27 11:20:12 2023">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="ce818763e31a4de8ac7850431f15fb5a" type="ProjectID"/>
|
||||
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
|
||||
@@ -18,49 +18,49 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
</item>
|
||||
<item name="Java Command Handlers">
|
||||
<property name="AddExistingIPHandler" value="5" type="JavaHandler"/>
|
||||
<property name="CloseProject" value="9" type="JavaHandler"/>
|
||||
<property name="CloseProject" value="10" type="JavaHandler"/>
|
||||
<property name="CopyIPHandler" value="3" type="JavaHandler"/>
|
||||
<property name="CustomizeCore" value="3" type="JavaHandler"/>
|
||||
<property name="EditDelete" value="8" type="JavaHandler"/>
|
||||
<property name="ManageCompositeTargets" value="3" type="JavaHandler"/>
|
||||
<property name="NewIPLocationHandler" value="1" type="JavaHandler"/>
|
||||
<property name="OpenIPLocationHandler" value="7" type="JavaHandler"/>
|
||||
<property name="OpenPreviousIPHandler" value="11" type="JavaHandler"/>
|
||||
<property name="RecustomizeCore" value="30" type="JavaHandler"/>
|
||||
<property name="OpenPreviousIPHandler" value="12" type="JavaHandler"/>
|
||||
<property name="RecustomizeCore" value="33" type="JavaHandler"/>
|
||||
</item>
|
||||
<item name="Gui Handlers">
|
||||
<property name="BaseDialog_CANCEL" value="17" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_OK" value="42" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_CANCEL" value="18" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_OK" value="45" type="GuiHandlerData"/>
|
||||
<property name="CopyIPHandler_DESTINATION_IP_NAME" value="3" type="GuiHandlerData"/>
|
||||
<property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="10" type="GuiHandlerData"/>
|
||||
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="10" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="147" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="157" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_MANAGE_IP" value="8" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_START_USING_VIVADO_WITH_IP_CATALOG" value="1" type="GuiHandlerData"/>
|
||||
<property name="HACGCCoeFileWidget_BROWSE" value="1" type="GuiHandlerData"/>
|
||||
<property name="HJFileChooserHelpers_JUMP_TO_RECENT_PROJECT_DIRECTORY" value="1" type="GuiHandlerData"/>
|
||||
<property name="IPCoreView_TABBED_PANE" value="2" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_EDIT" value="2" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_FILE" value="20" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_FILE" value="22" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_OPEN_RECENT_PROJECT" value="2" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_PROJECT" value="10" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_PROJECT" value="11" type="GuiHandlerData"/>
|
||||
<property name="NewIPProjectWizard_IP_LOCATION" value="1" type="GuiHandlerData"/>
|
||||
<property name="NewIPProjectWizard_PART" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_ADD_EXISTING_IP" value="5" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_CLOSE_PROJECT" value="9" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_CLOSE_PROJECT" value="10" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_COPY_IP" value="3" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_GENERATE_COMPOSITE_FILE" value="3" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_OPEN_IP_LOCATION" value="7" type="GuiHandlerData"/>
|
||||
<property name="RemoveSourcesDialog_ALSO_DELETE" value="8" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="22" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="24" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_ADD_CONFIGURABLE_IP_FILES" value="5" type="GuiHandlerData"/>
|
||||
<property name="SrcMenu_IP_DOCUMENTATION" value="5" type="GuiHandlerData"/>
|
||||
<property name="SyntheticaGettingStartedView_RECENT_IP_LOCATIONS" value="11" type="GuiHandlerData"/>
|
||||
<property name="SyntheticaGettingStartedView_RECENT_IP_LOCATIONS" value="12" type="GuiHandlerData"/>
|
||||
</item>
|
||||
<item name="Other">
|
||||
<property name="GuiMode" value="14" type="GuiMode"/>
|
||||
<property name="GuiMode" value="34" type="GuiMode"/>
|
||||
<property name="BatchMode" value="0" type="BatchMode"/>
|
||||
<property name="TclMode" value="8" type="TclMode"/>
|
||||
<property name="TclMode" value="19" type="TclMode"/>
|
||||
</item>
|
||||
</section>
|
||||
</application>
|
||||
|
||||
+8
@@ -0,0 +1,8 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="vio_phase_comp_synth_1" LaunchDir="/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
+8
@@ -0,0 +1,8 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="vio_phase_comp_synth_1" LaunchDir="/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="rom_hop_data_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681709915">
|
||||
<File Type="RDS-UTIL-PB" Name="rom_hop_data_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="rom_hop_data_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="rom_hop_data_utilization_synth.pb"/>
|
||||
<File Type="RDS-RDS" Name="rom_hop_data.vds"/>
|
||||
<File Type="RDS-DCP" Name="rom_hop_data.dcp"/>
|
||||
<File Type="PA-TCL" Name="rom_hop_data.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="vio_manual_ctrl_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1682237933">
|
||||
<File Type="PA-TCL" Name="vio_manual_ctrl.tcl"/>
|
||||
<File Type="RDS-DCP" Name="vio_manual_ctrl.dcp"/>
|
||||
<File Type="PA-TCL" Name="vio_manual_ctrl.tcl"/>
|
||||
<File Type="REPORTS-TCL" Name="vio_manual_ctrl_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="vio_manual_ctrl.vds"/>
|
||||
<File Type="RDS-UTIL-PB" Name="vio_manual_ctrl_utilization_synth.pb"/>
|
||||
|
||||
+1
-1
@@ -1,5 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado" Owner="josh" Host="JOSH-ASUS-Z690" Pid="658812" HostCore="20" HostMemory="65588996">
|
||||
<Process Command="vivado" Owner="josh" Host="JOSH-ASUS-Z690" Pid="203890" HostCore="20" HostMemory="65576700">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
|
||||
+1
-1
@@ -1,5 +1,5 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="vio_phase_comp_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1686797638">
|
||||
<GenRun Id="vio_phase_comp_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1690425471">
|
||||
<File Type="VDS-TIMING-PB" Name="vio_phase_comp_timing_summary_synth.pb"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="vio_phase_comp_timing_summary_synth.rpt"/>
|
||||
<File Type="RDS-DCP" Name="vio_phase_comp.dcp"/>
|
||||
|
||||
+8
-8
@@ -24,12 +24,12 @@ version:1
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3236:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3236:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3236:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3236:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3236:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3236:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3236:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3238:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3238:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3238:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3238:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3238:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3238:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3238:00:00
|
||||
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3966393835363732626435303431393139633038356339623061353561633562:506172656e742050412070726f6a656374204944:00
|
||||
eof:2018463593
|
||||
eof:296298308
|
||||
|
||||
BIN
Binary file not shown.
+2
@@ -17,6 +17,8 @@ proc create_report { reportName command } {
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
set_param simulator.modelsimInstallPath /home/josh/Software/Mentor/modeltech/bin
|
||||
set_param simulator.vcsmxInstallPath /home/josh/Software/Synopsys/vcs/T-2022.06/bin
|
||||
set_param project.vivado.isBlockSynthRun true
|
||||
set_msg_config -msgmgr_mode ooc_run
|
||||
create_project -in_memory -part xc7k410tffg900-2
|
||||
|
||||
+213
-163
@@ -2,8 +2,8 @@
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Thu Jun 15 10:53:59 2023
|
||||
# Process ID: 658851
|
||||
# Start of session at: Thu Jul 27 10:37:52 2023
|
||||
# Process ID: 203930
|
||||
# Current directory: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1
|
||||
# Command line: vivado -log vio_phase_comp.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_phase_comp.tcl
|
||||
# Log file: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.vds
|
||||
@@ -16,34 +16,13 @@ Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t'
|
||||
INFO: [Device 21-403] Loading part xc7k410tffg900-2
|
||||
INFO: Launching helper process for spawning children vivado processes
|
||||
INFO: Helper process launched with PID 658962
|
||||
INFO: Helper process launched with PID 204191
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1829.910 ; gain = 149.719 ; free physical = 1052 ; free virtual = 31239
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1830.883 ; gain = 153.719 ; free physical = 2320 ; free virtual = 33631
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-6157] synthesizing module 'vio_phase_comp' [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/rx_pre_process/vio_phase_comp/synth/vio_phase_comp.v:59]
|
||||
WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_phase_comp does not have driver. [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/rx_pre_process/vio_phase_comp/synth/vio_phase_comp.v:87]
|
||||
WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_phase_comp does not have driver. [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/rx_pre_process/vio_phase_comp/synth/vio_phase_comp.v:93]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'vio_phase_comp' (8#1) [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/rx_pre_process/vio_phase_comp/synth/vio_phase_comp.v:59]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Read
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Internal_cnt_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Read
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[15]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[14]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[13]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[12]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[11]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[10]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[9]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[8]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[7]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[6]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[5]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[4]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[3]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[2]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[1]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Internal_cnt_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Read
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[15]
|
||||
@@ -62,10 +41,27 @@ WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unc
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[2]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[1]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Internal_cnt_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in2[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in3[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in4[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in5[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Read
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[15]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[14]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[13]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[12]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[11]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[10]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[9]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[8]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[7]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[6]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[5]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[4]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[3]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[2]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[1]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Internal_cnt_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Read
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Internal_cnt_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in6[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in7[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in8[0]
|
||||
@@ -123,9 +119,13 @@ WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in59[0
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in60[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in61[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in62[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in63[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in64[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in65[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in66[0]
|
||||
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1891.629 ; gain = 211.438 ; free physical = 1310 ; free virtual = 31095
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1891.602 ; gain = 214.438 ; free physical = 2307 ; free virtual = 33620
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
@@ -138,10 +138,10 @@ Report Check Netlist:
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1894.598 ; gain = 214.406 ; free physical = 1267 ; free virtual = 31042
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1903.477 ; gain = 226.312 ; free physical = 2314 ; free virtual = 33628
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1894.598 ; gain = 214.406 ; free physical = 1267 ; free virtual = 31042
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1903.477 ; gain = 226.312 ; free physical = 2314 ; free virtual = 33628
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
|
||||
@@ -153,29 +153,29 @@ Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal
|
||||
Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/rx_pre_process/vio_phase_comp/vio_phase_comp.xdc]
|
||||
Completed Processing XDC Constraints
|
||||
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2077.254 ; gain = 0.000 ; free physical = 1178 ; free virtual = 30970
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2087.102 ; gain = 0.000 ; free physical = 2211 ; free virtual = 33525
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2083.191 ; gain = 5.938 ; free physical = 1178 ; free virtual = 30970
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2093.039 ; gain = 5.938 ; free physical = 2211 ; free virtual = 33525
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1269 ; free virtual = 31062
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2093.039 ; gain = 415.875 ; free physical = 2306 ; free virtual = 33621
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7k410tffg900-2
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1269 ; free virtual = 31062
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2093.039 ; gain = 415.875 ; free physical = 2306 ; free virtual = 33621
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying 'set_property' XDC Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1271 ; free virtual = 31064
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2093.039 ; gain = 415.875 ; free physical = 2303 ; free virtual = 33617
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1265 ; free virtual = 31058
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2093.039 ; gain = 415.875 ; free physical = 2280 ; free virtual = 33596
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
@@ -188,22 +188,27 @@ Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
2 Input 4 Bit Adders := 1
|
||||
2 Input 6 Bit Adders := 1
|
||||
2 Input 3 Bit Adders := 1
|
||||
2 Input 2 Bit Adders := 1
|
||||
+---Registers :
|
||||
161 Bit Registers := 3
|
||||
128 Bit Registers := 1
|
||||
33 Bit Registers := 5
|
||||
16 Bit Registers := 19
|
||||
16 Bit Registers := 20
|
||||
13 Bit Registers := 1
|
||||
12 Bit Registers := 1
|
||||
7 Bit Registers := 1
|
||||
6 Bit Registers := 1
|
||||
5 Bit Registers := 1
|
||||
4 Bit Registers := 1
|
||||
3 Bit Registers := 3
|
||||
2 Bit Registers := 1
|
||||
1 Bit Registers := 26
|
||||
1 Bit Registers := 28
|
||||
+---Muxes :
|
||||
2 Input 16 Bit Muxes := 2
|
||||
2 Input 1 Bit Muxes := 10
|
||||
3 Input 13 Bit Muxes := 1
|
||||
5 Input 12 Bit Muxes := 1
|
||||
2 Input 1 Bit Muxes := 11
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
@@ -214,19 +219,25 @@ Hierarchical RTL Component report
|
||||
Module vio_v3_0_20_probe_in_one
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
2 Input 4 Bit Adders := 1
|
||||
2 Input 6 Bit Adders := 1
|
||||
+---Registers :
|
||||
33 Bit Registers := 5
|
||||
161 Bit Registers := 3
|
||||
16 Bit Registers := 1
|
||||
4 Bit Registers := 1
|
||||
6 Bit Registers := 1
|
||||
1 Bit Registers := 2
|
||||
Module vio_v3_0_20_probe_width
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
2 Input 2 Bit Adders := 1
|
||||
+---Registers :
|
||||
13 Bit Registers := 1
|
||||
2 Bit Registers := 1
|
||||
+---Muxes :
|
||||
3 Input 13 Bit Muxes := 1
|
||||
Module vio_v3_0_20_probe_out_one
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
16 Bit Registers := 1
|
||||
1 Bit Registers := 1
|
||||
+---Muxes :
|
||||
2 Input 1 Bit Muxes := 1
|
||||
16 Bit Registers := 2
|
||||
Module vio_v3_0_20_probe_out_one__parameterized0
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
@@ -237,22 +248,27 @@ Detailed RTL Component Info :
|
||||
Module vio_v3_0_20_probe_out_one__parameterized1
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
16 Bit Registers := 2
|
||||
16 Bit Registers := 1
|
||||
1 Bit Registers := 1
|
||||
+---Muxes :
|
||||
2 Input 1 Bit Muxes := 1
|
||||
Module vio_v3_0_20_probe_out_all
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
16 Bit Registers := 1
|
||||
3 Bit Registers := 1
|
||||
1 Bit Registers := 10
|
||||
4 Bit Registers := 1
|
||||
1 Bit Registers := 11
|
||||
+---Muxes :
|
||||
2 Input 1 Bit Muxes := 2
|
||||
Module vio_v3_0_20_probe_width
|
||||
Module vio_v3_0_20_probe_width__parameterized0
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
2 Input 2 Bit Adders := 1
|
||||
2 Input 3 Bit Adders := 1
|
||||
+---Registers :
|
||||
12 Bit Registers := 1
|
||||
2 Bit Registers := 1
|
||||
3 Bit Registers := 1
|
||||
+---Muxes :
|
||||
5 Input 12 Bit Muxes := 1
|
||||
Module xsdbs_v1_0_2_xsdbs
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
@@ -293,79 +309,108 @@ Finished Part Resource Summary
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
Warning: Parallel synthesis criteria is not met
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[2]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[2]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[2]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[2]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[4]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[4]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[4]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[5]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[5]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[5]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[5]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[6]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[6]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[6]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[6]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[8]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[8]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[8]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[8]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[9]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[9]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[9]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[9]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[10]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[10]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[10]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[10]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[11]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[11]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[11]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[11]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[12]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[12]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[12]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[12]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[13]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[13]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[13]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[13]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[14]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[14]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[14]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[14]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[15]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[15]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[15]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[15]'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[15] )
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[15] )
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[15] )
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[15] )
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[2]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[2]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[2]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[2]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[2]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[4]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[4]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[4]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[4]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[4]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[5]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[5]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[5]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[5]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[5]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[6]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[6]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[6]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[6]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[6]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[8]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[8]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[8]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[8]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[8]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[9]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[9]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[9]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[9]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[9]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[10]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[10]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[10]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[10]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[10]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[11]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[11]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[11]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[11]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[11]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[12]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[12]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[12]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[12]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[12]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[13]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[13]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[13]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[13]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[13]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[14]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[14]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[14]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[14]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[14]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[15]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[15]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[15]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[15]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[15]'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[15] )
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[15] )
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[15] )
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[15] )
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[15] )
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/addr_p1_reg[0]' (FD) to 'inst/DECODER_INST/xsdb_addr_2_0_p1_reg[0]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/addr_p1_reg[1]' (FD) to 'inst/DECODER_INST/xsdb_addr_2_0_p1_reg[1]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/addr_p1_reg[2]' (FD) to 'inst/DECODER_INST/xsdb_addr_2_0_p1_reg[2]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[0]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[1]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[0]' (FD) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[1]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[1]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[2]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[1]' (FD) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[2]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[2]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[2]' (FD) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[3]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[8]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[3]' (FD) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[4]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[4]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[5]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[5]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[6]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[7]'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_WIDTH_INST/probe_width_int_reg[7] )
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[6]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[7]' (FD) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[7]'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_IN_WIDTH_INST/probe_width_int_reg[7] )
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[8]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[9]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[8]' (FD) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[9]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[9]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[10]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[9]' (FD) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[10]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[10]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[11]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[10]' (FD) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[11]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[11]' (FD) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[12]'
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1250 ; free virtual = 31049
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 2093.039 ; gain = 415.875 ; free physical = 2277 ; free virtual = 33605
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
@@ -377,13 +422,13 @@ Report RTL Partitions:
|
||||
Start Applying XDC Timing Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1187 ; free virtual = 30983
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2093.039 ; gain = 415.875 ; free physical = 2120 ; free virtual = 33434
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1187 ; free virtual = 30983
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2093.039 ; gain = 415.875 ; free physical = 2119 ; free virtual = 33433
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
@@ -395,7 +440,7 @@ Report RTL Partitions:
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1206 ; free virtual = 30981
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2093.039 ; gain = 415.875 ; free physical = 2138 ; free virtual = 33428
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
@@ -415,6 +460,9 @@ Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-4618] Found max_fanout attribute set to 100 on net \PROBE_IN_INST/addr_count [0]. Fanout reduced from 135 to 68 by creating 1 replicas.
|
||||
INFO: [Synth 8-4618] Found max_fanout attribute set to 100 on net \PROBE_IN_INST/addr_count [1]. Fanout reduced from 134 to 67 by creating 1 replicas.
|
||||
INFO: [Synth 8-4618] Found max_fanout attribute set to 200 on net \PROBE_IN_INST/read_done . Fanout reduced from 322 to 161 by creating 1 replicas.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
@@ -456,7 +504,7 @@ WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[2] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[1] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1206 ; free virtual = 30980
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2093.039 ; gain = 415.875 ; free physical = 2150 ; free virtual = 33410
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
@@ -469,7 +517,7 @@ Report Check Netlist:
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1206 ; free virtual = 30980
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2093.039 ; gain = 415.875 ; free physical = 2148 ; free virtual = 33409
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
@@ -481,25 +529,25 @@ Report RTL Partitions:
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1206 ; free virtual = 30980
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2093.039 ; gain = 415.875 ; free physical = 2148 ; free virtual = 33409
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1206 ; free virtual = 30980
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2093.039 ; gain = 415.875 ; free physical = 2148 ; free virtual = 33409
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1206 ; free virtual = 30980
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2093.039 ; gain = 415.875 ; free physical = 2148 ; free virtual = 33409
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1206 ; free virtual = 30980
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2093.039 ; gain = 415.875 ; free physical = 2148 ; free virtual = 33409
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
@@ -515,14 +563,14 @@ Report Cell Usage:
|
||||
+------+------+------+
|
||||
| |Cell |Count |
|
||||
+------+------+------+
|
||||
|1 |LUT1 | 3|
|
||||
|2 |LUT2 | 12|
|
||||
|3 |LUT3 | 30|
|
||||
|4 |LUT4 | 82|
|
||||
|5 |LUT5 | 24|
|
||||
|6 |LUT6 | 122|
|
||||
|7 |MUXF7 | 1|
|
||||
|8 |FDRE | 577|
|
||||
|1 |LUT1 | 2|
|
||||
|2 |LUT2 | 27|
|
||||
|3 |LUT3 | 363|
|
||||
|4 |LUT4 | 11|
|
||||
|5 |LUT5 | 28|
|
||||
|6 |LUT6 | 237|
|
||||
|7 |MUXF7 | 51|
|
||||
|8 |FDRE | 1232|
|
||||
|9 |FDSE | 2|
|
||||
+------+------+------+
|
||||
|
||||
@@ -530,51 +578,53 @@ Report Instance Areas:
|
||||
+------+---------------------------------------+--------------------------------------------+------+
|
||||
| |Instance |Module |Cells |
|
||||
+------+---------------------------------------+--------------------------------------------+------+
|
||||
|1 |top | | 853|
|
||||
|2 | inst |vio_v3_0_20_vio | 853|
|
||||
|1 |top | | 1953|
|
||||
|2 | inst |vio_v3_0_20_vio | 1953|
|
||||
|3 | U_XSDB_SLAVE |xsdbs_v1_0_2_xsdbs | 248|
|
||||
|4 | DECODER_INST |vio_v3_0_20_decoder | 90|
|
||||
|5 | PROBE_IN_INST |vio_v3_0_20_probe_in_one | 296|
|
||||
|6 | PROBE_OUT_ALL_INST |vio_v3_0_20_probe_out_all | 198|
|
||||
|7 | \G_PROBE_OUT[0].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one | 3|
|
||||
|8 | \G_PROBE_OUT[1].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_0 | 3|
|
||||
|9 | \G_PROBE_OUT[2].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0 | 3|
|
||||
|10 | \G_PROBE_OUT[3].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_1 | 3|
|
||||
|11 | \G_PROBE_OUT[4].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1 | 32|
|
||||
|12 | \G_PROBE_OUT[5].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1_2 | 32|
|
||||
|13 | \G_PROBE_OUT[6].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1_3 | 32|
|
||||
|14 | \G_PROBE_OUT[7].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1_4 | 32|
|
||||
|15 | PROBE_OUT_WIDTH_INST |vio_v3_0_20_probe_width | 5|
|
||||
|4 | DECODER_INST |vio_v3_0_20_decoder | 95|
|
||||
|5 | PROBE_IN_INST |vio_v3_0_20_probe_in_one | 1360|
|
||||
|6 | PROBE_IN_WIDTH_INST |vio_v3_0_20_probe_width | 8|
|
||||
|7 | PROBE_OUT_ALL_INST |vio_v3_0_20_probe_out_all | 218|
|
||||
|8 | \G_PROBE_OUT[0].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one | 32|
|
||||
|9 | \G_PROBE_OUT[1].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_0 | 32|
|
||||
|10 | \G_PROBE_OUT[2].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_1 | 32|
|
||||
|11 | \G_PROBE_OUT[3].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_2 | 47|
|
||||
|12 | \G_PROBE_OUT[4].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0 | 3|
|
||||
|13 | \G_PROBE_OUT[5].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1 | 3|
|
||||
|14 | \G_PROBE_OUT[6].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0_3 | 3|
|
||||
|15 | \G_PROBE_OUT[7].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0_4 | 3|
|
||||
|16 | \G_PROBE_OUT[8].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0_5 | 3|
|
||||
|17 | PROBE_OUT_WIDTH_INST |vio_v3_0_20_probe_width__parameterized0 | 8|
|
||||
+------+---------------------------------------+--------------------------------------------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1206 ; free virtual = 30980
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2093.039 ; gain = 415.875 ; free physical = 2148 ; free virtual = 33409
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 291 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2083.191 ; gain = 214.406 ; free physical = 1262 ; free virtual = 31037
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2083.191 ; gain = 403.000 ; free physical = 1276 ; free virtual = 31050
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 289 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2093.039 ; gain = 226.312 ; free physical = 2200 ; free virtual = 33461
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2093.039 ; gain = 415.875 ; free physical = 2214 ; free virtual = 33474
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
|
||||
INFO: [Netlist 29-17] Analyzing 51 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2083.191 ; gain = 0.000 ; free physical = 1192 ; free virtual = 30968
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2093.039 ; gain = 0.000 ; free physical = 2137 ; free virtual = 33397
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
85 Infos, 138 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
117 Infos, 138 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2083.191 ; gain = 684.277 ; free physical = 1284 ; free virtual = 31060
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2083.191 ; gain = 0.000 ; free physical = 1283 ; free virtual = 31059
|
||||
synth_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2093.039 ; gain = 676.738 ; free physical = 2226 ; free virtual = 33486
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2093.039 ; gain = 0.000 ; free physical = 2226 ; free virtual = 33486
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.dcp' has been generated.
|
||||
WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
|
||||
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_phase_comp, cache-ID = 0ddc3e874811cad5
|
||||
INFO: [Coretcl 2-1174] Renamed 14 cell refs.
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2107.203 ; gain = 0.000 ; free physical = 1286 ; free virtual = 31064
|
||||
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_phase_comp, cache-ID = 115dfcf85af89900
|
||||
INFO: [Coretcl 2-1174] Renamed 16 cell refs.
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2117.051 ; gain = 0.000 ; free physical = 2170 ; free virtual = 33426
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file vio_phase_comp_utilization_synth.rpt -pb vio_phase_comp_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Thu Jun 15 10:54:16 2023...
|
||||
INFO: [Common 17-206] Exiting Vivado at Thu Jul 27 10:38:10 2023...
|
||||
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
+20
-14
@@ -1,7 +1,7 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Thu Jun 15 10:54:16 2023
|
||||
// Date : Thu Jul 27 10:38:10 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.v
|
||||
@@ -14,18 +14,24 @@
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
|
||||
module vio_phase_comp(clk, probe_in0, probe_in1, probe_out0,
|
||||
probe_out1, probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[31:0],probe_in1[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[0:0],probe_out3[0:0],probe_out4[15:0],probe_out5[15:0],probe_out6[15:0],probe_out7[15:0]" */;
|
||||
module vio_phase_comp(clk, probe_in0, probe_in1, probe_in2, probe_in3,
|
||||
probe_in4, probe_in5, probe_out0, probe_out1, probe_out2, probe_out3, probe_out4, probe_out5,
|
||||
probe_out6, probe_out7, probe_out8)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_in1[31:0],probe_in2[31:0],probe_in3[31:0],probe_in4[31:0],probe_in5[31:0],probe_out0[15:0],probe_out1[15:0],probe_out2[15:0],probe_out3[15:0],probe_out4[0:0],probe_out5[0:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0]" */;
|
||||
input clk;
|
||||
input [31:0]probe_in0;
|
||||
input [0:0]probe_in1;
|
||||
output [0:0]probe_out0;
|
||||
output [0:0]probe_out1;
|
||||
output [0:0]probe_out2;
|
||||
output [0:0]probe_out3;
|
||||
output [15:0]probe_out4;
|
||||
output [15:0]probe_out5;
|
||||
output [15:0]probe_out6;
|
||||
output [15:0]probe_out7;
|
||||
input [0:0]probe_in0;
|
||||
input [31:0]probe_in1;
|
||||
input [31:0]probe_in2;
|
||||
input [31:0]probe_in3;
|
||||
input [31:0]probe_in4;
|
||||
input [31:0]probe_in5;
|
||||
output [15:0]probe_out0;
|
||||
output [15:0]probe_out1;
|
||||
output [15:0]probe_out2;
|
||||
output [15:0]probe_out3;
|
||||
output [0:0]probe_out4;
|
||||
output [0:0]probe_out5;
|
||||
output [0:0]probe_out6;
|
||||
output [0:0]probe_out7;
|
||||
output [0:0]probe_out8;
|
||||
endmodule
|
||||
|
||||
+17
-12
@@ -1,7 +1,7 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Thu Jun 15 10:54:16 2023
|
||||
-- Date : Thu Jul 27 10:38:10 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.vhdl
|
||||
@@ -15,16 +15,21 @@ use IEEE.STD_LOGIC_1164.ALL;
|
||||
entity vio_phase_comp is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe_in0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out3 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out4 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out5 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out6 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out7 : out STD_LOGIC_VECTOR ( 15 downto 0 )
|
||||
probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_in1 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_in2 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_in3 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_in4 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_in5 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_out0 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out1 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out3 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out4 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out5 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
|
||||
end vio_phase_comp;
|
||||
@@ -33,7 +38,7 @@ architecture stub of vio_phase_comp is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[31:0],probe_in1[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[0:0],probe_out3[0:0],probe_out4[15:0],probe_out5[15:0],probe_out6[15:0],probe_out7[15:0]";
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[0:0],probe_in1[31:0],probe_in2[31:0],probe_in3[31:0],probe_in4[31:0],probe_in5[31:0],probe_out0[15:0],probe_out1[15:0],probe_out2[15:0],probe_out3[15:0],probe_out4[0:0],probe_out5[0:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
|
||||
begin
|
||||
|
||||
BIN
Binary file not shown.
+15
-15
@@ -1,7 +1,7 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-----------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
| Date : Thu Jun 15 10:54:16 2023
|
||||
| Date : Thu Jul 27 10:38:10 2023
|
||||
| Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
| Command : report_utilization -file vio_phase_comp_utilization_synth.rpt -pb vio_phase_comp_utilization_synth.pb
|
||||
| Design : vio_phase_comp
|
||||
@@ -30,13 +30,13 @@ Table of Contents
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Slice LUTs* | 250 | 0 | 254200 | 0.10 |
|
||||
| LUT as Logic | 250 | 0 | 254200 | 0.10 |
|
||||
| Slice LUTs* | 637 | 0 | 254200 | 0.25 |
|
||||
| LUT as Logic | 637 | 0 | 254200 | 0.25 |
|
||||
| LUT as Memory | 0 | 0 | 90600 | 0.00 |
|
||||
| Slice Registers | 579 | 0 | 508400 | 0.11 |
|
||||
| Register as Flip Flop | 579 | 0 | 508400 | 0.11 |
|
||||
| Slice Registers | 1234 | 0 | 508400 | 0.24 |
|
||||
| Register as Flip Flop | 1234 | 0 | 508400 | 0.24 |
|
||||
| Register as Latch | 0 | 0 | 508400 | 0.00 |
|
||||
| F7 Muxes | 1 | 0 | 127100 | <0.01 |
|
||||
| F7 Muxes | 51 | 0 | 127100 | 0.04 |
|
||||
| F8 Muxes | 0 | 0 | 63550 | 0.00 |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
|
||||
@@ -57,7 +57,7 @@ Table of Contents
|
||||
| 0 | Yes | - | Set |
|
||||
| 0 | Yes | - | Reset |
|
||||
| 2 | Yes | Set | - |
|
||||
| 577 | Yes | Reset | - |
|
||||
| 1232 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
@@ -151,15 +151,15 @@ Table of Contents
|
||||
+----------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+------+---------------------+
|
||||
| FDRE | 577 | Flop & Latch |
|
||||
| LUT6 | 122 | LUT |
|
||||
| LUT4 | 82 | LUT |
|
||||
| LUT3 | 30 | LUT |
|
||||
| LUT5 | 24 | LUT |
|
||||
| LUT2 | 12 | LUT |
|
||||
| LUT1 | 3 | LUT |
|
||||
| FDRE | 1232 | Flop & Latch |
|
||||
| LUT3 | 363 | LUT |
|
||||
| LUT6 | 237 | LUT |
|
||||
| MUXF7 | 51 | MuxFx |
|
||||
| LUT5 | 28 | LUT |
|
||||
| LUT2 | 27 | LUT |
|
||||
| LUT4 | 11 | LUT |
|
||||
| LUT1 | 2 | LUT |
|
||||
| FDSE | 2 | Flop & Latch |
|
||||
| MUXF7 | 1 | MuxFx |
|
||||
+----------+------+---------------------+
|
||||
|
||||
|
||||
|
||||
BIN
Binary file not shown.
@@ -39,13 +39,13 @@
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="27"/>
|
||||
<Option Name="WTModelSimExportSim" Val="27"/>
|
||||
<Option Name="WTQuestaExportSim" Val="27"/>
|
||||
<Option Name="WTIesExportSim" Val="27"/>
|
||||
<Option Name="WTVcsExportSim" Val="27"/>
|
||||
<Option Name="WTRivieraExportSim" Val="27"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="27"/>
|
||||
<Option Name="WTXSimExportSim" Val="29"/>
|
||||
<Option Name="WTModelSimExportSim" Val="29"/>
|
||||
<Option Name="WTQuestaExportSim" Val="29"/>
|
||||
<Option Name="WTIesExportSim" Val="29"/>
|
||||
<Option Name="WTVcsExportSim" Val="29"/>
|
||||
<Option Name="WTRivieraExportSim" Val="29"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="29"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
|
||||
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Reference in New Issue
Block a user