josh/vivado-202401
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major update to lcmv, to fit hop control

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1. 调零算法部分增加调零控制模块,用于各模块互联和状态控制以及数据存储,增加LCMV和DAS选通; 2. Cordic 旋转输入改为保留两个符号位,避免溢出; 3. LCMV快拍数修改为2048; 4. 修改功率计算模块,适配较小数据位宽; 5. 修改在线捕获校准程序自动校准部分VIO初值; 6. 地检新射频发端增加自动频点切换
This commit is contained in:
josh
2023-07-31 10:31:21 +08:00
parent a877802bdf
commit 365a132831
418 changed files with 14603 additions and 3824 deletions
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projects/dl814_k7/dl814_k7_cal_coarse/project.tcl
+19 -23
View File
@@ -3,7 +3,7 @@
#
# project.tcl: Tcl script for re-creating project 'project'
#
# Generated by Vivado on Sun Jul 09 14:58:03 CST 2023
# Generated by Vivado on Sun Jul 30 21:21:34 CST 2023
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
@@ -42,11 +42,10 @@
# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/var_cal/ip/cmpy_18x18_mult/cmpy_18x18_mult.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/rx_pre_process/rom_hop_data/rom_hop_data.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/cmpy_16x12/cmpy_16x12.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/ram_hop_data/ram_hop_data.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/fifo_accor_cdc/fifo_accor_cdc.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/add_s24_s32_s32/add_s24_s32_s32.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/cmpy_12x12/cmpy_12x12.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/ram_hop_data/ram_hop_data.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/rotate_16b/rotate_16b.xci"
# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xci"
# "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8.xci"
@@ -85,6 +84,7 @@
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/Sisyif_src/fre_caliatt.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/Sisyif_src/mgc_ctrl.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/Sisyif_src/mod2_rom.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/rx_pre_process/null_ctrl.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/rx_pre_process/phase_comp.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/rx_pre_process/rx_pre_process.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/rx_pre_process/rx_pre_test.v"
@@ -111,9 +111,12 @@
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/basic_driver/vio_clk_ld_rd/vio_clk_ld_rd.xci"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/constraints/k7401t_ad9516_2ad9361_physical.xdc"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/constraints/k7410t_ad9516_2ad9361_timing.xdc"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/testbenches/tb_rx_pre_test.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/testbenches/tb_rx_test.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/testbenches/tb_rx_pre.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/testbenches/tb_rx_pre_test.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/testbenches/tb_null_ctrl.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/testbenches/tb_accum.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/testbenches/tb_acorr.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/testbenches/tb_rx_test.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/testbenches/tb_tx_pre_process.v"
# "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/testbenches/tb_xpm_cdc_pulse.v"
#
@@ -229,7 +232,7 @@ set_property -name "webtalk.modelsim_launch_sim" -value "2" -objects $obj
set_property -name "webtalk.questa_export_sim" -value "92" -objects $obj
set_property -name "webtalk.riviera_export_sim" -value "92" -objects $obj
set_property -name "webtalk.vcs_export_sim" -value "92" -objects $obj
set_property -name "webtalk.vcs_launch_sim" -value "77" -objects $obj
set_property -name "webtalk.vcs_launch_sim" -value "148" -objects $obj
set_property -name "webtalk.xsim_export_sim" -value "92" -objects $obj
set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj
@@ -263,11 +266,10 @@ set files [list \
[file normalize "${origin_dir}/../../../modules/xc7k410tffg900-2/var_cal/ip/cmpy_18x18_mult/cmpy_18x18_mult.xci"] \
[file normalize "${origin_dir}/ip/rx_pre_process/rom_hop_data/rom_hop_data.xci"] \
[file normalize "${origin_dir}/../common_ip/rx_pre_process/cmpy_16x12/cmpy_16x12.xci"] \
[file normalize "${origin_dir}/../common_ip/rx_pre_process/ram_hop_data/ram_hop_data.xci"] \
[file normalize "${origin_dir}/../common_ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc.xci"] \
[file normalize "${origin_dir}/../common_ip/rx_pre_process/fifo_accor_cdc/fifo_accor_cdc.xci"] \
[file normalize "${origin_dir}/../common_ip/rx_pre_process/add_s24_s32_s32/add_s24_s32_s32.xci"] \
[file normalize "${origin_dir}/../common_ip/rx_pre_process/cmpy_12x12/cmpy_12x12.xci"] \
[file normalize "${origin_dir}/../common_ip/rx_pre_process/ram_hop_data/ram_hop_data.xci"] \
[file normalize "${origin_dir}/../common_ip/rx_pre_process/rotate_16b/rotate_16b.xci"] \
[file normalize "${origin_dir}/../../../modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xci"] \
[file normalize "${origin_dir}/../../../modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8.xci"] \
@@ -306,6 +308,7 @@ set files [list \
[file normalize "${origin_dir}/rtl/Sisyif_src/fre_caliatt.v"] \
[file normalize "${origin_dir}/rtl/Sisyif_src/mgc_ctrl.v"] \
[file normalize "${origin_dir}/rtl/Sisyif_src/mod2_rom.v"] \
[file normalize "${origin_dir}/rtl/rx_pre_process/null_ctrl.v"] \
[file normalize "${origin_dir}/rtl/rx_pre_process/phase_comp.v"] \
[file normalize "${origin_dir}/rtl/rx_pre_process/rx_pre_process.v"] \
[file normalize "${origin_dir}/rtl/rx_pre_process/rx_pre_test.v"] \
@@ -469,15 +472,6 @@ if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
set file "$origin_dir/../common_ip/rx_pre_process/ram_hop_data/ram_hop_data.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
set_property -name "registered_with_manager" -value "1" -objects $file_obj
if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
set file "$origin_dir/../common_ip/rx_pre_process/fifo_weight_cdc/fifo_weight_cdc.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
@@ -496,7 +490,7 @@ if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
set file "$origin_dir/../common_ip/rx_pre_process/add_s24_s32_s32/add_s24_s32_s32.xci"
set file "$origin_dir/../common_ip/rx_pre_process/cmpy_12x12/cmpy_12x12.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
@@ -505,7 +499,7 @@ if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
set file "$origin_dir/../common_ip/rx_pre_process/cmpy_12x12/cmpy_12x12.xci"
set file "$origin_dir/../common_ip/rx_pre_process/ram_hop_data/ram_hop_data.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
@@ -690,9 +684,12 @@ if {[string equal [get_filesets -quiet sim_1] ""]} {
# Set 'sim_1' fileset object
set obj [get_filesets sim_1]
set files [list \
[file normalize "${origin_dir}/testbenches/tb_rx_pre_test.v"] \
[file normalize "${origin_dir}/testbenches/tb_rx_test.v"] \
[file normalize "${origin_dir}/testbenches/tb_rx_pre.v"] \
[file normalize "${origin_dir}/testbenches/tb_rx_pre_test.v"] \
[file normalize "${origin_dir}/testbenches/tb_null_ctrl.v"] \
[file normalize "${origin_dir}/testbenches/tb_accum.v"] \
[file normalize "${origin_dir}/testbenches/tb_acorr.v"] \
[file normalize "${origin_dir}/testbenches/tb_rx_test.v"] \
[file normalize "${origin_dir}/testbenches/tb_tx_pre_process.v"] \
[file normalize "${origin_dir}/testbenches/tb_xpm_cdc_pulse.v"] \
]
@@ -706,8 +703,7 @@ add_files -norecurse -fileset $obj $files
# Set 'sim_1' fileset properties
set obj [get_filesets sim_1]
set_property -name "sim_mode" -value "post-implementation" -objects $obj
set_property -name "top" -value "tb_rx_pre_test" -objects $obj
set_property -name "top" -value "tb_rx_pre" -objects $obj
set_property -name "top_auto_set" -value "0" -objects $obj
set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
set_property -name "vcs.compile.vlogan.more_options" -value "-v2005 -kdb" -objects $obj