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major update to lcmv, to fit hop control

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1. 调零算法部分增加调零控制模块,用于各模块互联和状态控制以及数据存储,增加LCMV和DAS选通; 2. Cordic 旋转输入改为保留两个符号位,避免溢出; 3. LCMV快拍数修改为2048; 4. 修改功率计算模块,适配较小数据位宽; 5. 修改在线捕获校准程序自动校准部分VIO初值; 6. 地检新射频发端增加自动频点切换
This commit is contained in:
josh
2023-07-31 10:31:21 +08:00
parent a877802bdf
commit 365a132831
418 changed files with 14603 additions and 3824 deletions
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projects/dl814_k7/dl814_k7_cal_coarse/testbenches/tb_accum.v
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@@ -0,0 +1,160 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
// _ _ ____
// | | ___ ___| |__ / ___| __ _ ___
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
// \___/ \___/|___/_| |_| \____|\__,_|\___/
//
// Create Date: 2022/10/30 20:46:26
// Last Simulate Data: 2023/07/17 15:51
// Design Name:
// Module Name: tb_accum
// Project Name:
// Target Devices:
// Tool Versions:
// Description: Testbench for [accum_cmplx_mat]
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// -------------------------------
// MATLAB Code for data generation
// -------------------------------
// COLUMN_NUM = 4;
// DATA_I_WIDTH = 12;
// ACC_NUM = 10;
// rng(0);
// data = rand(4,2)*2-1;
// d_12b = round(data.*(2^(DATA_I_WIDTH-1)-1));
// d_12b_cmplx = d_12b(:,1) + 1i*d_12b(:,2);
// d_12b_cmplx = d_12b_cmplx(end:-1:1,:);
// d_12b_acorr = d_12b_cmplx*d_12b_cmplx';
// d_12b_acorr_real_sim = reshape(flip(reshape(real(d_12b_acorr)',1,16)),4,4);
// d_12b_acorr_imag_sim = reshape(flip(reshape(imag(d_12b_acorr)',1,16)),4,4);
// d_12b_acorr_real_sim_sum = ACC_NUM*d_12b_acorr_real_sim;
// d_12b_acorr_imag_sim_sum = ACC_NUM*d_12b_acorr_imag_sim;
module tb_accum;
localparam DATA_I_WIDTH = 24;
localparam DATA_O_WIDTH = 32;
localparam ROW_NUM = 4;
localparam COL_NUM = 4;
localparam ACC_NUM = 2048;
reg acc_rst = 1'b0;
reg clk = 1'b1;
reg rst = 1'b1;
reg din_valid = 'b0;
// reg [ROW_NUM*COL_NUM*DATA_I_WIDTH-1:0] din_real = {
// 24'd1952708, 24'd1246152, -24'd2458370, 24'd2283360,
// 24'd1246152, 24'd5474825, -24'd1041611, 24'd2493996,
// -24'd2458370, -24'd1041611, 24'd3154378, -24'd2757828,
// 24'd2283360, 24'd2493996, -24'd2757828, 24'd2899728
// };
// reg [ROW_NUM*COL_NUM*DATA_I_WIDTH-1:0] din_real = {
// 24'd0, -24'd3022886, -24'd340582, -24'd669768,
// 24'd3022886, 24'd0, -24'd4023023, 24'd3107328,
// 24'd340582, 24'd4023023, 24'd0, 24'd1241460,
// 24'd669768, -24'd3107328, -24'd1241460, 24'd0
// };
reg [ROW_NUM*COL_NUM*DATA_I_WIDTH-1:0] din_real = {
24'd1952708, 24'd1246152, -24'd2458370, 24'd2283360,
24'd1246152, 24'd5474825, -24'd1041611, 24'd2493996,
-24'd2458370, -24'd1041611, 24'd3154378, 24'h7F_FFFF,
24'd2283360, 24'd2493996, -24'd2757828, 24'h80_0000
};
reg [ROW_NUM*COL_NUM*DATA_I_WIDTH-1:0] din_imag = {
24'd0, -24'd3022886, -24'd340582, -24'd669768,
24'd3022886, 24'd0, -24'd4023023, 24'd3107328,
24'd340582, 24'd4023023, 24'd0, 24'd1241460,
24'd669768, -24'd3107328, -24'd1241460, 24'd0
};
wire dout_valid;
wire [ROW_NUM*COL_NUM*DATA_O_WIDTH-1:0] dout_real, dout_imag;
accum_cmplx_mat #(
.ROW_NUM (ROW_NUM),
.COL_NUM (COL_NUM),
.DATA_I_WIDTH (DATA_I_WIDTH),
.DATA_O_WIDTH (DATA_O_WIDTH),
.ACC_NUM (ACC_NUM)
) u_accum_cmplx_mat
(
// clock & reset
.clk (clk ),
.rst (rst ),
.acc_rst (acc_rst ), // [acc_rst] should assert before accumulation starts
// input data
.din_valid (din_valid ),
.din_real (din_real ),
.din_imag (din_imag ),
// output data
.dout_valid (dout_valid ),
.dout_real (dout_real ),
.dout_imag (dout_imag )
);
initial begin
#102
rst = 1'b0;
// reset
#222
acc_rst = 1'b1;
#20
acc_rst = 1'b0;
// input data valid lasts [ACC_NUM] clock cycles
#222
@(posedge clk)
#1
din_valid = 1'b1;
#(20*ACC_NUM)
din_valid = 1'b0;
// reset
#222
acc_rst = 1'b1;
#20
acc_rst = 1'b0;
// input data valid lasts [ACC_NUM] clock cycles
#222
@(posedge clk)
#1
din_valid = 1'b1;
#(20*ACC_NUM)
din_valid = 1'b0;
#222
$stop;
end
always #10 clk = ~clk;
endmodule
projects/dl814_k7/dl814_k7_cal_coarse/testbenches/tb_acorr.v
+105
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@@ -0,0 +1,105 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
// _ _ ____
// | | ___ ___| |__ / ___| __ _ ___
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
// \___/ \___/|___/_| |_| \____|\__,_|\___/
//
// Create Date: 2022/10/30 20:46:26
// Design Name:
// Module Name: acorr_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description: Testbench for [acorr_cmplx_col_vec]
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_acorr;
localparam ROW_NUM = 1;
localparam COL_NUM = 4;
localparam DATA_I_WIDTH = 12;
localparam DATA_O_WIDTH = 23;
reg acc_rst = 1'b0;
reg clk = 1'b1;
reg rst = 1'b1;
reg din_valid = 'b0;
reg [COL_NUM*DATA_I_WIDTH-1:0] din_real = 'b0, din_imag = 'b0;
wire dout_valid;
wire [COL_NUM*COL_NUM*DATA_O_WIDTH-1:0] dout_real, dout_imag;
acorr_cmplx_col_vec #(
.COL_NUM (COL_NUM),
.DATA_I_WIDTH (DATA_I_WIDTH),
.DATA_O_WIDTH (DATA_O_WIDTH)
) u_acorr_cmplx_col_vec
(
// clock & reset
.clk (clk ),
.rst (rst ),
// input data
.din_valid (din_valid ),
.din_real (din_real ),
.din_imag (din_imag ),
// output data
.dout_valid (dout_valid ),
.dout_real (dout_real ),
.dout_imag (dout_imag )
);
initial begin
#102 rst = 1'b0;
#222;
@(posedge clk)
din_valid = 1'b1;
din_real = {
12'd1351,
-12'd1219,
12'd1326,
12'd1029};
din_imag = {
12'd1538,
-12'd1119,
12'd1519,
12'd1495};
@(posedge clk)
din_valid = 1'b0;
@(posedge clk)
din_valid = 1'b1;
din_real = {
12'd153 ,
-12'd724 ,
-12'd1315,
12'd433 };
din_imag = {
-12'd1170,
12'd981 ,
-12'd48 ,
12'd1494};
end
always #10 clk = ~clk;
endmodule
projects/dl814_k7/dl814_k7_cal_coarse/testbenches/tb_null_ctrl.v
+80
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@@ -0,0 +1,80 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 07/18/2023 11:22:10 AM
// Design Name:
// Module Name: tb_null_ctrl
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_null_ctrl;
localparam HOP_CNT_192 = 192*200;
reg clk = 1'b1;
reg clk_2x = 1'b1;
reg clk_4x = 1'b1;
reg rst = 1'b1;
reg hop_flag_in = 1'b0;
reg sync_flag_phy = 1'b0;
reg sync_null_en_phy = 1'b1;
wire hop_flag_out_phy;
null_ctrl u_null_ctrl
(
.clk (clk ),
.clk_phy (clk_4x ),
.rst (rst ),
.hop_flag_in_phy (hop_flag_in ),
.sync_flag_phy (sync_flag_phy ),
.sync_null_en_phy (sync_null_en_phy ),
.hop_flag_out_phy (hop_flag_out_phy ),
.adc_din_valid (1'b1 )
);
// clock & reset
initial begin
#102
rst = 1'b0;
end
always #5 clk_4x = ~clk_4x;
always @(posedge clk_4x) begin
clk_2x = ~clk_2x;
end
always @(posedge clk_2x) begin
clk = ~clk;
end
// hop control
reg [$clog2(HOP_CNT_192)-1 : 0] hop_cnt = 'b0;
always @(posedge clk_4x) begin
if (rst) begin
hop_cnt <= 'b0;
hop_flag_in <= 'b0;
end
else begin
hop_cnt <= (hop_cnt == HOP_CNT_192-1) ? 'b0 : hop_cnt + 1'b1;
hop_flag_in <= (hop_cnt == 120) ? 1'b1 : 'b0;
end
end
endmodule
projects/dl814_k7/dl814_k7_cal_coarse/testbenches/tb_rx_pre.v
+23 -10
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@@ -32,7 +32,7 @@ localparam COL_NUM = 4;
localparam PS_PL_WIDTH = 32;
localparam OUTPUT_DATA_WIDTH = 30;
localparam FRAME_HEAD = 32'b10110011100011110000111000110010;
localparam FRAME_HEAD = 32'h7E7E7E7E;
localparam FRAME_BITS = (2+COL_NUM*2)*PS_PL_WIDTH;
reg [FRAME_BITS-1 : 0] weight_stream_buf =
@@ -69,6 +69,7 @@ wire [11:0] rx_ch4_i;
wire [11:0] rx_ch4_q;
reg hop_start_flag = 1'b0;
wire hop_flag_out;
wire accor_stream_valid;
wire accor_stream_data;
wire weight_stream_data;
@@ -76,12 +77,13 @@ wire rx_data_valid;
wire [OUTPUT_DATA_WIDTH-1:0] rx_data_i, rx_data_q;
rx_pre_process #(
.OUTPUT_DATA_WIDTH (OUTPUT_DATA_WIDTH )
.OUTPUT_WIDTH (OUTPUT_DATA_WIDTH ),
.SYNC_HOP_INTVL (48*200 )
) u_rx_pre_process
(
// clock & reset
.sys_clk (sys_clk ), // input sys_clk
.sys_clk_4x (sys_clk_4x ), // input sys_clk_4x
.sys_clk_phy (sys_clk_4x ), // input sys_clk_4x
.sys_rst (sys_rst ), // input sys_rst
.clk_96m (clk_96m ), // input clk_96m
.ant_rst (ant_rst ), // input ant_rst
@@ -94,6 +96,11 @@ rx_pre_process #(
.rx_ch3_q (rx_ch3_q ), // input [11:0] rx_ch3_q
.rx_ch4_i (-rx_ch4_i ), // input [11:0] rx_ch4_i
.rx_ch4_q (-rx_ch4_q ), // input [11:0] rx_ch4_q
// input channel phase
.phase_ch1 ('b0 ),
.phase_ch2 ('b0 ),
.phase_ch3 ('b0 ),
.phase_ch4 ('b0 ),
// ad9361 calibration interface
.ad9361_1_cal_start (ad9361_1_cal_start ), // input ad9361_1_cal_start
.ad9361_1_cal_done (ad9361_1_cal_done ), // output ad9361_1_cal_done
@@ -103,7 +110,11 @@ rx_pre_process #(
.ad9361_cal_valid (ad9361_cal_valid ), // output ad9361_cal_valid
.ad9361_recal (ad9361_recal ), // input ad9361_recal
// nulling algotithm interface
.hop_start_flag (hop_start_flag ), // input hop_start_flag
.hop_flag_in_phy (hop_start_flag ), // input hop_start_flag
.sync_flag_phy (1'b0 ),
.lcmv_en_phy (1'b1 ),
.hop_flag_out (hop_flag_out ),
.accor_stream_valid (accor_stream_valid ), // output accor_stream_valid
.accor_stream_data (accor_stream_data ), // output accor_stream_data
.weight_stream_data (weight_stream_data ), // input weight_stream_data
@@ -219,8 +230,8 @@ always @(posedge sys_clk_4x) begin
hop_start_flag <= 1'b0;
end
else if (ad9361_cal_valid) begin
hop_cnt <= (hop_cnt == 38399) ? 'b0 : hop_cnt + 1'b1;
hop_start_flag <= (hop_cnt == 1'b1) ? 1'b1 : 1'b0;
hop_cnt <= (hop_cnt == 200*48*4-1) ? 'b0 : hop_cnt + 1'b1;
hop_start_flag <= (hop_cnt == 127) ? 1'b1 : 1'b0;
end
else begin
hop_cnt <= hop_cnt;
@@ -232,10 +243,12 @@ end
reg weight_stream_valid = 'b0;
always @(negedge accor_stream_valid) begin
#((48*50)*40+18); // 50us of 48M clock
weight_stream_valid = 'b1;
#(FRAME_BITS*20);
weight_stream_valid = 'b0;
if (~sys_rst) begin
#((48*50)*40+18); // 50us of 48M clock
weight_stream_valid = 'b1;
#(FRAME_BITS*20);
weight_stream_valid = 'b0;
end
end
reg [$clog2(FRAME_BITS)-1 : 0] weight_stream_cnt;
projects/dl814_k7/dl814_k7_cal_coarse/testbenches/tb_rx_pre_test.v
+18 -13
View File
@@ -78,6 +78,7 @@ reg [11:0] rx_ch4_i_cal = -12'd2047;
reg [11:0] rx_ch4_q_cal = -12'd2047;
wire hop_start_flag;
wire hop_flag_out;
wire accor_stream_valid;
wire accor_stream_data;
wire weight_stream_data;
@@ -204,13 +205,13 @@ assign weight_stream_data = weight_stream_buf[FRAME_BITS-1-weight_stream_cnt];
////////////////////////////////////////////////////////////////////////////////
rx_pre_process #(
.OUTPUT_DATA_WIDTH (30 ),
.SNAPSHOT_NUM (256 )
.OUTPUT_DATA_WIDTH (30 ),
.SYNC_HOP_INTVL (48*200 )
) u_rx_pre_process
(
// clock & reset
.sys_clk (sys_clk ), // sync to adc data
.sys_clk_4x (sys_clk_4x ), // sync to physical layer
.sys_clk_phy (sys_clk_3x ), // sync to physical layer
.sys_rst (sys_rst ), // sync to [sys_clk]
.clk_96m (clk_96m ), // sync to c2c data
.ant_rst (ant_rst ), // sync to [clk_96m]
@@ -237,22 +238,26 @@ rx_pre_process #(
.ad9361_cal_valid (ad9361_cal_valid ),
.ad9361_recal (ad9361_recal ),
// nulling algotithm interface
.hop_start_flag (hop_start_flag ), // sync to [sys_clk_4x]
.accor_stream_valid (accor_stream_valid ), // sync to [clk_96m]
.accor_stream_data (accor_stream_data ), // sync to [clk_96m]
.weight_stream_data (weight_stream_data ), // sync to [clk_96m]
.rx_data_valid (rx_data_valid ), // sync to [sys_clk]
.rx_data_i (rx_data_i ), // sync to [sys_clk]
.rx_data_q (rx_data_q ) // sync to [sys_clk]
.hop_flag_in_phy (hop_start_flag ), // input hop_start_flag
.sync_flag_phy (1'b0 ),
.lcmv_en_phy (1'b1 ),
.hop_flag_out (hop_flag_out ),
.accor_stream_valid (accor_stream_valid ), // output accor_stream_valid
.accor_stream_data (accor_stream_data ), // output accor_stream_data
.weight_stream_data (weight_stream_data ), // input weight_stream_data
.rx_data_valid (rx_data_valid ),
.rx_data_i (rx_data_i ),
.rx_data_q (rx_data_q )
);
// temporary test cases
rx_pre_test u_rx_pre_test
(
// clock & reset
.sys_clk (sys_clk ),
.sys_rst (sys_rst ),
.sys_clk_4x (sys_clk_4x ),
.clk (sys_clk ),
.rst (sys_rst ),
.clk_phy (sys_clk_3x ),
.hop_trigger (hop_trigger ),
.hop_trigger_en (1'b1 ),
// calc result
projects/dl814_k7/dl814_k7_cal_coarse/testbenches/tb_rx_test.m
-2
View File
@@ -113,5 +113,3 @@ for i = 1:9600
end
xs1_12b_bin_join(i) = [xs1_real_12b_bin_join_tmp,xs1_imag_12b_bin_join_tmp];
end
coe