Archived
major update to lcmv, to fit hop control
1. 调零算法部分增加调零控制模块,用于各模块互联和状态控制以及数据存储,增加LCMV和DAS选通; 2. Cordic 旋转输入改为保留两个符号位,避免溢出; 3. LCMV快拍数修改为2048; 4. 修改功率计算模块,适配较小数据位宽; 5. 修改在线捕获校准程序自动校准部分VIO初值; 6. 地检新射频发端增加自动频点切换
This commit is contained in:
LFS
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+3
-3
@@ -1,10 +1,10 @@
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Fri May 12 16:06:19 2023
|
||||
// Date : Fri May 12 16:06:18 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top rom_freq_word -prefix
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||||
// rom_freq_word_ rom_freq_word_stub.v
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||||
// Design : rom_freq_word
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||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
|
||||
+3
-3
@@ -1,10 +1,10 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Fri May 12 16:06:19 2023
|
||||
-- Date : Fri May 12 16:06:18 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top rom_freq_word -prefix
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||||
-- rom_freq_word_ rom_freq_word_stub.vhdl
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||||
-- Design : rom_freq_word
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||||
-- Purpose : Stub declaration of top-level module interface
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||||
-- Device : xc7k410tffg900-2
|
||||
|
||||
+4
-4
@@ -93,10 +93,10 @@ output reg [0 : 0] probe_out13 = 'h0 ;
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output reg [0 : 0] probe_out14 = 'h0 ;
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output reg [0 : 0] probe_out15 = 'h0 ;
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output reg [0 : 0] probe_out16 = 'h0 ;
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output reg [31 : 0] probe_out17 = 'h00000000 ;
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output reg [31 : 0] probe_out18 = 'h00000000 ;
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output reg [31 : 0] probe_out19 = 'h00000000 ;
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output reg [31 : 0] probe_out20 = 'h00000000 ;
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output reg [31 : 0] probe_out17 = 'h00075300 ;
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output reg [31 : 0] probe_out18 = 'h00075300 ;
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output reg [31 : 0] probe_out19 = 'h00075300 ;
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output reg [31 : 0] probe_out20 = 'h00057E40 ;
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||||
|
||||
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||||
endmodule
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LFS
BIN
Binary file not shown.
projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_rfcontrl/vio_rfcontrl_sim_netlist.vhdl
LFS
BIN
Binary file not shown.
+1
-1
@@ -1,7 +1,7 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Fri May 12 15:59:09 2023
|
||||
// Date : Sun Jul 30 19:29:54 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.v
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Fri May 12 15:59:09 2023
|
||||
-- Date : Sun Jul 30 19:29:54 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/vio_rfcontrl_stub.vhdl
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Fri May 12 16:05:33 CST 2023
|
||||
# Generated by export_simulation on Sun Jul 30 19:13:03 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+3
-3
@@ -10,11 +10,11 @@ vmap xpm activehdl/xpm
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||||
vmap blk_mem_gen_v8_4_3 activehdl/blk_mem_gen_v8_4_3
|
||||
|
||||
vlog -work xil_defaultlib -sv2k12 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -93 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vlog -work blk_mem_gen_v8_4_3 -v2k5 \
|
||||
"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
|
||||
|
||||
+3
-3
@@ -1,6 +1,6 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
|
||||
rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v,
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Fri May 12 16:05:33 CST 2023
|
||||
# Generated by Vivado on Sun Jul 30 19:13:03 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Fri May 12 16:05:33 CST 2023
|
||||
# Generated by export_simulation on Sun Jul 30 19:13:03 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+3
-3
@@ -1,6 +1,6 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
|
||||
rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v,
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Fri May 12 16:05:33 CST 2023
|
||||
# Generated by Vivado on Sun Jul 30 19:13:03 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+3
-3
@@ -1,9 +1,9 @@
|
||||
-makelib ies_lib/xil_defaultlib -sv \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
-endlib
|
||||
-makelib ies_lib/xpm \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
-endlib
|
||||
-makelib ies_lib/blk_mem_gen_v8_4_3 \
|
||||
"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Fri May 12 16:05:33 CST 2023
|
||||
# Generated by export_simulation on Sun Jul 30 19:13:03 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Fri May 12 16:05:33 CST 2023
|
||||
# Generated by Vivado on Sun Jul 30 19:13:03 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Fri May 12 16:05:33 CST 2023
|
||||
# Generated by export_simulation on Sun Jul 30 19:13:03 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+3
-3
@@ -10,11 +10,11 @@ vmap xpm questa_lib/msim/xpm
|
||||
vmap blk_mem_gen_v8_4_3 questa_lib/msim/blk_mem_gen_v8_4_3
|
||||
|
||||
vlog -work xil_defaultlib -64 -sv \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -64 -93 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vlog -work blk_mem_gen_v8_4_3 -64 \
|
||||
"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
|
||||
|
||||
+3
-3
@@ -1,6 +1,6 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
|
||||
rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v,
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Fri May 12 16:05:33 CST 2023
|
||||
# Generated by Vivado on Sun Jul 30 19:13:03 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Fri May 12 16:05:33 CST 2023
|
||||
# Generated by export_simulation on Sun Jul 30 19:13:03 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+3
-3
@@ -10,11 +10,11 @@ vmap xpm riviera/xpm
|
||||
vmap blk_mem_gen_v8_4_3 riviera/blk_mem_gen_v8_4_3
|
||||
|
||||
vlog -work xil_defaultlib -sv2k12 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -93 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vlog -work blk_mem_gen_v8_4_3 -v2k5 \
|
||||
"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
|
||||
|
||||
+3
-3
@@ -1,6 +1,6 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
|
||||
rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v,
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Fri May 12 16:05:33 CST 2023
|
||||
# Generated by Vivado on Sun Jul 30 19:13:03 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Fri May 12 16:05:33 CST 2023
|
||||
# Generated by export_simulation on Sun Jul 30 19:13:03 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Fri May 12 16:05:33 CST 2023
|
||||
# Generated by Vivado on Sun Jul 30 19:13:03 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Fri May 12 16:05:33 CST 2023
|
||||
# Generated by export_simulation on Sun Jul 30 19:13:03 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+3
-3
@@ -1,6 +1,6 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v,
|
||||
rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v,
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Fri May 12 16:05:33 CST 2023
|
||||
# Generated by Vivado on Sun Jul 30 19:13:03 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+3
-3
@@ -1,9 +1,9 @@
|
||||
-makelib xcelium_lib/xil_defaultlib -sv \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
-endlib
|
||||
-makelib xcelium_lib/xpm \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
-endlib
|
||||
-makelib xcelium_lib/blk_mem_gen_v8_4_3 \
|
||||
"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Fri May 12 16:05:33 CST 2023
|
||||
# Generated by export_simulation on Sun Jul 30 19:13:03 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+3
-3
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Fri May 12 16:05:33 CST 2023
|
||||
# Generated by Vivado on Sun Jul 30 19:13:03 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
@@ -22,7 +22,7 @@
|
||||
#*********************************************************************************************************
|
||||
|
||||
# Command line options
|
||||
xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0
|
||||
xv_boost_lib_path=/home/josh/Software/Xilinx/Vivado/2019.1/tps/boost_1_64_0
|
||||
xvlog_opts="--relax"
|
||||
|
||||
|
||||
@@ -92,7 +92,7 @@ setup()
|
||||
copy_setup_file()
|
||||
{
|
||||
file="xsim.ini"
|
||||
lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim"
|
||||
lib_map_path="/home/josh/Software/Xilinx/Vivado/2019.1/data/xsim"
|
||||
if [[ ($1 != "") ]]; then
|
||||
lib_map_path="$1"
|
||||
fi
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Fri May 12 15:58:50 CST 2023
|
||||
# Generated by export_simulation on Sun Jul 30 19:29:34 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+3
-3
@@ -8,11 +8,11 @@ vmap xil_defaultlib activehdl/xil_defaultlib
|
||||
vmap xpm activehdl/xpm
|
||||
|
||||
vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/vio_rfcontrl/hdl/verilog" "+incdir+../../../ip/vio_rfcontrl/hdl" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -93 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/vio_rfcontrl/hdl/verilog" "+incdir+../../../ip/vio_rfcontrl/hdl" \
|
||||
"../../../ip/vio_rfcontrl/sim/vio_rfcontrl.v" \
|
||||
|
||||
+3
-3
@@ -1,5 +1,5 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl"
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl"
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl"
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl"
|
||||
vio_rfcontrl.v,verilog,xil_defaultlib,../../../ip/vio_rfcontrl/sim/vio_rfcontrl.v,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl"
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Fri May 12 15:58:50 CST 2023
|
||||
# Generated by Vivado on Sun Jul 30 19:29:34 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Fri May 12 15:58:50 CST 2023
|
||||
# Generated by export_simulation on Sun Jul 30 19:29:34 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+3
-3
@@ -1,5 +1,5 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl"
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl"
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl"
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl"
|
||||
vio_rfcontrl.v,verilog,xil_defaultlib,../../../ip/vio_rfcontrl/sim/vio_rfcontrl.v,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl"
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
|
||||
+3
-3
@@ -1,9 +1,9 @@
|
||||
-makelib ies_lib/xil_defaultlib -sv \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
-endlib
|
||||
-makelib ies_lib/xpm \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
-endlib
|
||||
-makelib ies_lib/xil_defaultlib \
|
||||
"../../../ip/vio_rfcontrl/sim/vio_rfcontrl.v" \
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Fri May 12 15:58:50 CST 2023
|
||||
# Generated by Vivado on Sun Jul 30 19:29:34 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Fri May 12 15:58:50 CST 2023
|
||||
# Generated by export_simulation on Sun Jul 30 19:29:34 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Fri May 12 15:58:50 CST 2023
|
||||
# Generated by Vivado on Sun Jul 30 19:29:34 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Fri May 12 15:58:50 CST 2023
|
||||
# Generated by export_simulation on Sun Jul 30 19:29:34 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+3
-3
@@ -8,11 +8,11 @@ vmap xil_defaultlib questa_lib/msim/xil_defaultlib
|
||||
vmap xpm questa_lib/msim/xpm
|
||||
|
||||
vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/vio_rfcontrl/hdl/verilog" "+incdir+../../../ip/vio_rfcontrl/hdl" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -64 -93 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vlog -work xil_defaultlib -64 "+incdir+../../../ip/vio_rfcontrl/hdl/verilog" "+incdir+../../../ip/vio_rfcontrl/hdl" \
|
||||
"../../../ip/vio_rfcontrl/sim/vio_rfcontrl.v" \
|
||||
|
||||
+3
-3
@@ -1,5 +1,5 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl"
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl"
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl"
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl"
|
||||
vio_rfcontrl.v,verilog,xil_defaultlib,../../../ip/vio_rfcontrl/sim/vio_rfcontrl.v,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl"
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Fri May 12 15:58:50 CST 2023
|
||||
# Generated by Vivado on Sun Jul 30 19:29:34 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Fri May 12 15:58:50 CST 2023
|
||||
# Generated by export_simulation on Sun Jul 30 19:29:34 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+3
-3
@@ -8,11 +8,11 @@ vmap xil_defaultlib riviera/xil_defaultlib
|
||||
vmap xpm riviera/xpm
|
||||
|
||||
vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/vio_rfcontrl/hdl/verilog" "+incdir+../../../ip/vio_rfcontrl/hdl" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -93 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/vio_rfcontrl/hdl/verilog" "+incdir+../../../ip/vio_rfcontrl/hdl" \
|
||||
"../../../ip/vio_rfcontrl/sim/vio_rfcontrl.v" \
|
||||
|
||||
+3
-3
@@ -1,5 +1,5 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl"
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl"
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl"
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl"
|
||||
vio_rfcontrl.v,verilog,xil_defaultlib,../../../ip/vio_rfcontrl/sim/vio_rfcontrl.v,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl"
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Fri May 12 15:58:50 CST 2023
|
||||
# Generated by Vivado on Sun Jul 30 19:29:34 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Fri May 12 15:58:50 CST 2023
|
||||
# Generated by export_simulation on Sun Jul 30 19:29:34 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Fri May 12 15:58:50 CST 2023
|
||||
# Generated by Vivado on Sun Jul 30 19:29:34 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Fri May 12 15:58:50 CST 2023
|
||||
# Generated by export_simulation on Sun Jul 30 19:29:34 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+3
-3
@@ -1,5 +1,5 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl"
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl"
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl"
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl"
|
||||
vio_rfcontrl.v,verilog,xil_defaultlib,../../../ip/vio_rfcontrl/sim/vio_rfcontrl.v,incdir="../../../ip/vio_rfcontrl/hdl/verilog"incdir="../../../ip/vio_rfcontrl/hdl"
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
|
||||
+3
-3
@@ -1,9 +1,9 @@
|
||||
-makelib xcelium_lib/xil_defaultlib -sv \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
-endlib
|
||||
-makelib xcelium_lib/xpm \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
-endlib
|
||||
-makelib xcelium_lib/xil_defaultlib \
|
||||
"../../../ip/vio_rfcontrl/sim/vio_rfcontrl.v" \
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Fri May 12 15:58:50 CST 2023
|
||||
# Generated by Vivado on Sun Jul 30 19:29:34 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Fri May 12 15:58:50 CST 2023
|
||||
# Generated by export_simulation on Sun Jul 30 19:29:34 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+3
-3
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Fri May 12 15:58:50 CST 2023
|
||||
# Generated by Vivado on Sun Jul 30 19:29:34 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
@@ -22,7 +22,7 @@
|
||||
#*********************************************************************************************************
|
||||
|
||||
# Command line options
|
||||
xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0
|
||||
xv_boost_lib_path=/home/josh/Software/Xilinx/Vivado/2019.1/tps/boost_1_64_0
|
||||
xvlog_opts="--relax"
|
||||
|
||||
|
||||
@@ -92,7 +92,7 @@ setup()
|
||||
copy_setup_file()
|
||||
{
|
||||
file="xsim.ini"
|
||||
lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim"
|
||||
lib_map_path="/home/josh/Software/Xilinx/Vivado/2019.1/data/xsim"
|
||||
if [[ ($1 != "") ]]; then
|
||||
lib_map_path="$1"
|
||||
fi
|
||||
|
||||
+2
@@ -0,0 +1,2 @@
|
||||
NumberHits:1
|
||||
Timestamp: Sun Jul 30 11:13:01 UTC 2023
|
||||
+810
@@ -0,0 +1,810 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
|
||||
<spirit:name>a299833a56443345</spirit:name>
|
||||
<spirit:version>0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>vio_rfcontrl</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="vio" spirit:version="3.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EN_PROBE_IN_ACTIVITY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EN_SYNCHRONIZATION">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PROBE_IN">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PROBE_OUT">21</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN0_WIDTH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN100_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN101_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN102_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN103_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN104_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN105_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN106_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN107_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN108_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN109_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN10_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN110_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN111_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN112_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN113_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN114_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN115_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN116_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN117_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN118_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN119_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN11_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN120_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN121_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN122_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN123_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN124_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN125_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN126_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN127_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN128_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN129_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN12_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN130_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN131_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN132_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN133_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN134_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN135_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN136_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN137_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN138_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN139_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN13_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN140_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN141_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN142_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN143_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN144_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN145_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN146_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN147_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN148_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN149_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN14_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN150_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN151_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN152_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN153_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN154_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN155_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN156_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN157_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN158_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN159_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN15_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN160_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN161_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN162_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN163_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN164_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN165_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN166_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN167_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN168_WIDTH">1</spirit:configurableElementValue>
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BIN
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BIN
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BIN
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+46
@@ -0,0 +1,46 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Sun Jul 30 19:29:53 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rfcontrl_stub.v
|
||||
// Design : vio_rfcontrl
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_in0, probe_in1, probe_out0,
|
||||
probe_out1, probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8,
|
||||
probe_out9, probe_out10, probe_out11, probe_out12, probe_out13, probe_out14, probe_out15,
|
||||
probe_out16, probe_out17, probe_out18, probe_out19, probe_out20)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[15:0],probe_in1[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[31:0],probe_out18[31:0],probe_out19[31:0],probe_out20[31:0]" */;
|
||||
input clk;
|
||||
input [15:0]probe_in0;
|
||||
input [0:0]probe_in1;
|
||||
output [0:0]probe_out0;
|
||||
output [0:0]probe_out1;
|
||||
output [15:0]probe_out2;
|
||||
output [7:0]probe_out3;
|
||||
output [3:0]probe_out4;
|
||||
output [3:0]probe_out5;
|
||||
output [3:0]probe_out6;
|
||||
output [3:0]probe_out7;
|
||||
output [7:0]probe_out8;
|
||||
output [7:0]probe_out9;
|
||||
output [15:0]probe_out10;
|
||||
output [15:0]probe_out11;
|
||||
output [15:0]probe_out12;
|
||||
output [0:0]probe_out13;
|
||||
output [0:0]probe_out14;
|
||||
output [0:0]probe_out15;
|
||||
output [0:0]probe_out16;
|
||||
output [31:0]probe_out17;
|
||||
output [31:0]probe_out18;
|
||||
output [31:0]probe_out19;
|
||||
output [31:0]probe_out20;
|
||||
endmodule
|
||||
+53
@@ -0,0 +1,53 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Sun Jul 30 19:29:53 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rfcontrl_stub.vhdl
|
||||
-- Design : vio_rfcontrl
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe_in0 : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out3 : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe_out5 : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe_out6 : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe_out7 : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe_out8 : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe_out9 : out STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
probe_out10 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out11 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out12 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out13 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out15 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out16 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out17 : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_out18 : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_out19 : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_out20 : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[15:0],probe_in1[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[15:0],probe_out3[7:0],probe_out4[3:0],probe_out5[3:0],probe_out6[3:0],probe_out7[3:0],probe_out8[7:0],probe_out9[7:0],probe_out10[15:0],probe_out11[15:0],probe_out12[15:0],probe_out13[0:0],probe_out14[0:0],probe_out15[0:0],probe_out16[0:0],probe_out17[31:0],probe_out18[31:0],probe_out19[31:0],probe_out20[31:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+16
-14
@@ -1,41 +1,43 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:3431:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:313130:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:3433:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:313133:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:36:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f6d6d616e6473696e7075745f747970655f74636c5f636f6d6d616e645f68657265:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f7079697068616e646c65725f64657374696e6174696f6e5f69705f6e616d65:3130:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f7265747265657461626c6570616e656c5f636f72655f747265655f7461626c65:3634:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:65787072756e7472656570616e656c5f6578705f72756e5f747265655f7461626c65:3530:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:343436:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6d616e6167655f6970:36:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:65787072756e7472656570616e656c5f6578705f72756e5f747265655f7461626c65:3536:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:343535:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6d616e6167655f6970:38:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6f70656e5f70726f6a656374:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f73746172745f7573696e675f76697661646f5f776974685f69705f636174616c6f67:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6861636763636f6566696c657769646765745f62726f777365:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:686163676374616262656470616e655f7461626265645f70616e65:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:686a66696c6563686f6f73657268656c706572735f6a756d705f746f5f726563656e745f70726f6a6563745f6469726563746f7279:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68666f6c64657263686f6f73657268656c706572735f6a756d705f746f5f726563656e745f70726f6a6563745f6469726563746f7279:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:686a66696c6563686f6f73657268656c706572735f6a756d705f746f5f726563656e745f70726f6a6563745f6469726563746f7279:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6970636f7265766965775f7461626265645f70616e65:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f6578706f7274:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:3334:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:3338:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f6970:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f6f70656e5f726563656e745f70726f6a656374:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f70726f6a656374:3138:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f70726f6a656374:3230:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f746578745f656469746f72:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d7367766965775f636c6561725f6d657373616765735f726573756c74696e675f66726f6d5f757365725f6578656375746564:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6e6577697070726f6a65637477697a6172645f69705f6c6f636174696f6e:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6e6577697070726f6a65637477697a6172645f70617274:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6164645f6578697374696e675f6970:3135:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f636c6f73655f70726f6a656374:3137:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f636c6f73655f70726f6a656374:3139:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f636f70795f6970:3130:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f67656e65726174655f636f6d706f736974655f66696c65:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6f70656e5f69705f6c6f636174696f6e:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f67656e65726174655f636f6d706f736974655f66696c65:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6f70656e5f69705f6c6f636174696f6e:36:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f67726573736469616c6f675f63616e63656c:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72656d6f7665736f75726365736469616c6f675f616c736f5f64656c657465:3138:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f636c6f73655f6469616c6f675f756e73617665645f6368616e6765735f77696c6c:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f67656e65726174655f6f75747075745f70726f64756374735f696d6d6564696174656c79:3630:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f67656e65726174655f6f75747075745f70726f64756374735f696d6d6564696174656c79:3632:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f636f6e666967757261626c655f69705f66696c6573:3132:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f646f63756d656e746174696f6e:37:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f646f63756d656e746174696f6e:38:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f69705f6c6f636174696f6e73:3238:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7870675f636f6566696c65776964676465745f62726f777365:36:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7870675f636f6566696c65776964676465745f65646974:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7870675f697073796d626f6c5f73686f775f64697361626c65645f706f727473:32:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7870675f74616262656470616e655f7461626265645f70616e65:3132:00:00
|
||||
eof:705714440
|
||||
eof:2456062258
|
||||
|
||||
+6
-5
@@ -1,12 +1,13 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6164646578697374696e67697068616e646c6572:3135:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:3137:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:3139:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636f7079697068616e646c6572:3130:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:637573746f6d697a65636f7265:3230:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:3232:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6d616e616765636f6d706f7369746574617267657473:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6d616e616765636f6d706f7369746574617267657473:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657769706c6f636174696f6e68616e646c6572:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e69706c6f636174696f6e68616e646c6572:34:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e69706c6f636174696f6e68616e646c6572:36:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726576696f7573697068616e646c6572:3235:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265637573746f6d697a65636f7265:3930:00:00
|
||||
eof:3167550
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265637573746f6d697a65636f7265:3933:00:00
|
||||
eof:2833290637
|
||||
|
||||
+1
-1
@@ -1,3 +1,3 @@
|
||||
version:1
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:29
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:31
|
||||
eof:
|
||||
|
||||
+5
-5
@@ -1,7 +1,7 @@
|
||||
version:1
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863376b343130746666673930302d32:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:76696f5f70686173655f636f6d70:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:76696f5f7266636f6e74726c:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
@@ -33,7 +33,7 @@ version:1
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313073:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323037342e3635324d42:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3637312e3737304d42:00:00
|
||||
eof:1160710185
|
||||
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313173:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323038332e3133334d42:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3638302e3234364d42:00:00
|
||||
eof:3983104666
|
||||
|
||||
+23
-20
@@ -3,7 +3,7 @@
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pa" timeStamp="Tue May 23 08:24:22 2023">
|
||||
<application name="pa" timeStamp="Sun Jul 30 19:30:00 2023">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="ce818763e31a4de8ac7850431f15fb5a" type="ProjectID"/>
|
||||
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
|
||||
@@ -18,51 +18,54 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
</item>
|
||||
<item name="Java Command Handlers">
|
||||
<property name="AddExistingIPHandler" value="15" type="JavaHandler"/>
|
||||
<property name="CloseProject" value="17" type="JavaHandler"/>
|
||||
<property name="CloseProject" value="19" type="JavaHandler"/>
|
||||
<property name="CopyIPHandler" value="10" type="JavaHandler"/>
|
||||
<property name="CustomizeCore" value="20" type="JavaHandler"/>
|
||||
<property name="EditDelete" value="22" type="JavaHandler"/>
|
||||
<property name="ManageCompositeTargets" value="4" type="JavaHandler"/>
|
||||
<property name="ManageCompositeTargets" value="5" type="JavaHandler"/>
|
||||
<property name="NewIPLocationHandler" value="1" type="JavaHandler"/>
|
||||
<property name="OpenIPLocationHandler" value="4" type="JavaHandler"/>
|
||||
<property name="OpenIPLocationHandler" value="6" type="JavaHandler"/>
|
||||
<property name="OpenPreviousIPHandler" value="25" type="JavaHandler"/>
|
||||
<property name="RecustomizeCore" value="90" type="JavaHandler"/>
|
||||
<property name="OpenProject" value="1" type="JavaHandler"/>
|
||||
<property name="RecustomizeCore" value="93" type="JavaHandler"/>
|
||||
</item>
|
||||
<item name="Gui Handlers">
|
||||
<property name="BaseDialog_CANCEL" value="41" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_OK" value="110" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_CANCEL" value="43" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_OK" value="113" type="GuiHandlerData"/>
|
||||
<property name="CmdMsgDialog_OK" value="6" type="GuiHandlerData"/>
|
||||
<property name="CommandsInput_TYPE_TCL_COMMAND_HERE" value="2" type="GuiHandlerData"/>
|
||||
<property name="CopyIPHandler_DESTINATION_IP_NAME" value="10" type="GuiHandlerData"/>
|
||||
<property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="64" type="GuiHandlerData"/>
|
||||
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="50" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="446" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_MANAGE_IP" value="6" type="GuiHandlerData"/>
|
||||
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="56" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="455" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_MANAGE_IP" value="8" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_OPEN_PROJECT" value="1" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_START_USING_VIVADO_WITH_IP_CATALOG" value="1" type="GuiHandlerData"/>
|
||||
<property name="HACGCCoeFileWidget_BROWSE" value="3" type="GuiHandlerData"/>
|
||||
<property name="HACGCTabbedPane_TABBED_PANE" value="1" type="GuiHandlerData"/>
|
||||
<property name="HJFileChooserHelpers_JUMP_TO_RECENT_PROJECT_DIRECTORY" value="2" type="GuiHandlerData"/>
|
||||
<property name="HFolderChooserHelpers_JUMP_TO_RECENT_PROJECT_DIRECTORY" value="2" type="GuiHandlerData"/>
|
||||
<property name="HJFileChooserHelpers_JUMP_TO_RECENT_PROJECT_DIRECTORY" value="3" type="GuiHandlerData"/>
|
||||
<property name="IPCoreView_TABBED_PANE" value="2" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_EXPORT" value="1" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_FILE" value="34" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_FILE" value="38" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_IP" value="2" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_OPEN_RECENT_PROJECT" value="2" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_PROJECT" value="18" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_PROJECT" value="20" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_TEXT_EDITOR" value="2" type="GuiHandlerData"/>
|
||||
<property name="MsgView_CLEAR_MESSAGES_RESULTING_FROM_USER_EXECUTED" value="1" type="GuiHandlerData"/>
|
||||
<property name="NewIPProjectWizard_IP_LOCATION" value="1" type="GuiHandlerData"/>
|
||||
<property name="NewIPProjectWizard_PART" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_ADD_EXISTING_IP" value="15" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_CLOSE_PROJECT" value="17" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_CLOSE_PROJECT" value="19" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_COPY_IP" value="10" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_GENERATE_COMPOSITE_FILE" value="4" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_OPEN_IP_LOCATION" value="4" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_GENERATE_COMPOSITE_FILE" value="5" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_OPEN_IP_LOCATION" value="6" type="GuiHandlerData"/>
|
||||
<property name="ProgressDialog_CANCEL" value="1" type="GuiHandlerData"/>
|
||||
<property name="RemoveSourcesDialog_ALSO_DELETE" value="18" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_CLOSE_DIALOG_UNSAVED_CHANGES_WILL" value="1" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="60" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="62" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_ADD_CONFIGURABLE_IP_FILES" value="12" type="GuiHandlerData"/>
|
||||
<property name="SrcMenu_IP_DOCUMENTATION" value="7" type="GuiHandlerData"/>
|
||||
<property name="SrcMenu_IP_DOCUMENTATION" value="8" type="GuiHandlerData"/>
|
||||
<property name="SyntheticaGettingStartedView_RECENT_IP_LOCATIONS" value="28" type="GuiHandlerData"/>
|
||||
<property name="XPG_CoeFileWidgdet_BROWSE" value="6" type="GuiHandlerData"/>
|
||||
<property name="XPG_CoeFileWidgdet_EDIT" value="1" type="GuiHandlerData"/>
|
||||
@@ -70,9 +73,9 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="XPG_TabbedPane_TABBED_PANE" value="12" type="GuiHandlerData"/>
|
||||
</item>
|
||||
<item name="Other">
|
||||
<property name="GuiMode" value="144" type="GuiMode"/>
|
||||
<property name="GuiMode" value="40" type="GuiMode"/>
|
||||
<property name="BatchMode" value="0" type="BatchMode"/>
|
||||
<property name="TclMode" value="101" type="TclMode"/>
|
||||
<property name="TclMode" value="20" type="TclMode"/>
|
||||
</item>
|
||||
</section>
|
||||
</application>
|
||||
|
||||
+8
@@ -0,0 +1,8 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="vio_rfcontrl_synth_1" LaunchDir="/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
-5
@@ -1,5 +0,0 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado" Owner="josh" Host="JOSH-ASUS-Z690" Pid="1476074" HostCore="20" HostMemory="65588992">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
-270
@@ -1,270 +0,0 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
// GLOBAL VARIABLES
|
||||
var ISEShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var ISERunDir = "";
|
||||
var ISELogFile = "runme.log";
|
||||
var ISELogFileStr = null;
|
||||
var ISELogEcho = true;
|
||||
var ISEOldVersionWSH = false;
|
||||
|
||||
|
||||
|
||||
// BOOTSTRAP
|
||||
ISEInit();
|
||||
|
||||
|
||||
|
||||
//
|
||||
// ISE FUNCTIONS
|
||||
//
|
||||
function ISEInit() {
|
||||
|
||||
// 1. RUN DIR setup
|
||||
var ISEScrFP = WScript.ScriptFullName;
|
||||
var ISEScrN = WScript.ScriptName;
|
||||
ISERunDir =
|
||||
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
|
||||
|
||||
// 2. LOG file setup
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
// 3. LOG echo?
|
||||
var ISEScriptArgs = WScript.Arguments;
|
||||
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
|
||||
if ( ISEScriptArgs(loopi) == "-quiet" ) {
|
||||
ISELogEcho = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// 4. WSH version check
|
||||
var ISEOptimalVersionWSH = 5.6;
|
||||
var ISECurrentVersionWSH = WScript.Version;
|
||||
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
|
||||
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
|
||||
ISEOptimalVersionWSH + " or higher. Downloads" );
|
||||
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
|
||||
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
|
||||
ISEStdErr( "" );
|
||||
|
||||
ISEOldVersionWSH = true;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEStep( ISEProg, ISEArgs ) {
|
||||
|
||||
// CHECK for a STOP FILE
|
||||
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "*** Halting run - EA reset detected ***" );
|
||||
ISEStdErr( "" );
|
||||
WScript.Quit( 1 );
|
||||
}
|
||||
|
||||
// WRITE STEP HEADER to LOG
|
||||
ISEStdOut( "" );
|
||||
ISEStdOut( "*** Running " + ISEProg );
|
||||
ISEStdOut( " with args " + ISEArgs );
|
||||
ISEStdOut( "" );
|
||||
|
||||
// LAUNCH!
|
||||
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
|
||||
if ( ISEExitCode != 0 ) {
|
||||
WScript.Quit( ISEExitCode );
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEExec( ISEProg, ISEArgs ) {
|
||||
|
||||
var ISEStep = ISEProg;
|
||||
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
|
||||
ISEProg += ".bat";
|
||||
}
|
||||
|
||||
var ISECmdLine = ISEProg + " " + ISEArgs;
|
||||
var ISEExitCode = 1;
|
||||
|
||||
if ( ISEOldVersionWSH ) { // WSH 5.1
|
||||
|
||||
// BEGIN file creation
|
||||
ISETouchFile( ISEStep, "begin" );
|
||||
|
||||
// LAUNCH!
|
||||
ISELogFileStr.Close();
|
||||
ISECmdLine =
|
||||
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
|
||||
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
} else { // WSH 5.6
|
||||
|
||||
// LAUNCH!
|
||||
ISEShell.CurrentDirectory = ISERunDir;
|
||||
|
||||
// Redirect STDERR to STDOUT
|
||||
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
|
||||
var ISEProcess = ISEShell.Exec( ISECmdLine );
|
||||
|
||||
// BEGIN file creation
|
||||
var wbemFlagReturnImmediately = 0x10;
|
||||
var wbemFlagForwardOnly = 0x20;
|
||||
var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
|
||||
var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var NOC = 0;
|
||||
var NOLP = 0;
|
||||
var TPM = 0;
|
||||
|
||||
var cpuInfos = new Enumerator(processor);
|
||||
for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
|
||||
var cpuInfo = cpuInfos.item();
|
||||
NOC += cpuInfo.NumberOfCores;
|
||||
NOLP += cpuInfo.NumberOfLogicalProcessors;
|
||||
}
|
||||
var csInfos = new Enumerator(computerSystem);
|
||||
for(;!csInfos.atEnd(); csInfos.moveNext()) {
|
||||
var csInfo = csInfos.item();
|
||||
TPM += csInfo.TotalPhysicalMemory;
|
||||
}
|
||||
|
||||
var ISEHOSTCORE = NOLP
|
||||
var ISEMEMTOTAL = TPM
|
||||
|
||||
var ISENetwork = WScript.CreateObject( "WScript.Network" );
|
||||
var ISEHost = ISENetwork.ComputerName;
|
||||
var ISEUser = ISENetwork.UserName;
|
||||
var ISEPid = ISEProcess.ProcessID;
|
||||
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
|
||||
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
|
||||
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
|
||||
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
|
||||
"\" Owner=\"" + ISEUser +
|
||||
"\" Host=\"" + ISEHost +
|
||||
"\" Pid=\"" + ISEPid +
|
||||
"\" HostCore=\"" + ISEHOSTCORE +
|
||||
"\" HostMemory=\"" + ISEMEMTOTAL +
|
||||
"\">" );
|
||||
ISEBeginFile.WriteLine( " </Process>" );
|
||||
ISEBeginFile.WriteLine( "</ProcessHandle>" );
|
||||
ISEBeginFile.Close();
|
||||
|
||||
var ISEOutStr = ISEProcess.StdOut;
|
||||
var ISEErrStr = ISEProcess.StdErr;
|
||||
|
||||
// WAIT for ISEStep to finish
|
||||
while ( ISEProcess.Status == 0 ) {
|
||||
|
||||
// dump stdout then stderr - feels a little arbitrary
|
||||
while ( !ISEOutStr.AtEndOfStream ) {
|
||||
ISEStdOut( ISEOutStr.ReadLine() );
|
||||
}
|
||||
|
||||
WScript.Sleep( 100 );
|
||||
}
|
||||
|
||||
ISEExitCode = ISEProcess.ExitCode;
|
||||
}
|
||||
|
||||
ISELogFileStr.Close();
|
||||
|
||||
// END/ERROR file creation
|
||||
if ( ISEExitCode != 0 ) {
|
||||
ISETouchFile( ISEStep, "error" );
|
||||
|
||||
} else {
|
||||
ISETouchFile( ISEStep, "end" );
|
||||
}
|
||||
|
||||
return ISEExitCode;
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// UTILITIES
|
||||
//
|
||||
function ISEStdOut( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdOut.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISEStdErr( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdErr.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISETouchFile( ISERoot, ISEStatus ) {
|
||||
|
||||
var ISETFile =
|
||||
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
|
||||
ISETFile.Close();
|
||||
}
|
||||
|
||||
function ISEOpenFile( ISEFilename ) {
|
||||
|
||||
// This function has been updated to deal with a problem seen in CR #870871.
|
||||
// In that case the user runs a script that runs impl_1, and then turns around
|
||||
// and runs impl_1 -to_step write_bitstream. That second run takes place in
|
||||
// the same directory, which means we may hit some of the same files, and in
|
||||
// particular, we will open the runme.log file. Even though this script closes
|
||||
// the file (now), we see cases where a subsequent attempt to open the file
|
||||
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
|
||||
// play? In any case, we try to work around this by first waiting if the file
|
||||
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
|
||||
// and try to open the file 10 times with a one second delay after each attempt.
|
||||
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
|
||||
// If there is an unrecognized exception when trying to open the file, we output
|
||||
// an error message and write details to an exception.log file.
|
||||
var ISEFullPath = ISERunDir + "/" + ISEFilename;
|
||||
if (ISEFileSys.FileExists(ISEFullPath)) {
|
||||
// File is already there. This could be a problem. Wait in case it is still in use.
|
||||
WScript.Sleep(5000);
|
||||
}
|
||||
var i;
|
||||
for (i = 0; i < 10; ++i) {
|
||||
try {
|
||||
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
|
||||
} catch (exception) {
|
||||
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
|
||||
if (error_code == 52) { // 52 is bad file name or number.
|
||||
// Wait a second and try again.
|
||||
WScript.Sleep(1000);
|
||||
continue;
|
||||
} else {
|
||||
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
var exceptionFilePath = ISERunDir + "/exception.log";
|
||||
if (!ISEFileSys.FileExists(exceptionFilePath)) {
|
||||
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
|
||||
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
|
||||
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
exceptionFile.WriteLine("\tException name: " + exception.name);
|
||||
exceptionFile.WriteLine("\tException error code: " + error_code);
|
||||
exceptionFile.WriteLine("\tException message: " + exception.message);
|
||||
exceptionFile.Close();
|
||||
}
|
||||
throw exception;
|
||||
}
|
||||
}
|
||||
}
|
||||
// If we reached this point, we failed to open the file after 10 attempts.
|
||||
// We need to error out.
|
||||
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
|
||||
WScript.Quit(1);
|
||||
}
|
||||
-67
@@ -1,67 +0,0 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# ISEWrap.sh: Vivado Runs Script for UNIX
|
||||
# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
HD_LOG=$1
|
||||
shift
|
||||
|
||||
# CHECK for a STOP FILE
|
||||
if [ -f .stop.rst ]
|
||||
then
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
exit 1
|
||||
fi
|
||||
|
||||
ISE_STEP=$1
|
||||
shift
|
||||
|
||||
# WRITE STEP HEADER to LOG
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Running $ISE_STEP" >> $HD_LOG
|
||||
echo " with args $@" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
|
||||
# LAUNCH!
|
||||
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
|
||||
|
||||
# BEGIN file creation
|
||||
ISE_PID=$!
|
||||
if [ X != X$HOSTNAME ]
|
||||
then
|
||||
ISE_HOST=$HOSTNAME #bash
|
||||
else
|
||||
ISE_HOST=$HOST #csh
|
||||
fi
|
||||
ISE_USER=$USER
|
||||
|
||||
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
|
||||
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
|
||||
|
||||
ISE_BEGINFILE=.$ISE_STEP.begin.rst
|
||||
/bin/touch $ISE_BEGINFILE
|
||||
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
|
||||
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
|
||||
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
|
||||
echo " </Process>" >> $ISE_BEGINFILE
|
||||
echo "</ProcessHandle>" >> $ISE_BEGINFILE
|
||||
|
||||
# WAIT for ISEStep to finish
|
||||
wait $ISE_PID
|
||||
|
||||
# END/ERROR file creation
|
||||
RETVAL=$?
|
||||
if [ $RETVAL -eq 0 ]
|
||||
then
|
||||
/bin/touch .$ISE_STEP.end.rst
|
||||
else
|
||||
/bin/touch .$ISE_STEP.error.rst
|
||||
fi
|
||||
|
||||
exit $RETVAL
|
||||
|
||||
-16
@@ -1,16 +0,0 @@
|
||||
# This file is automatically generated.
|
||||
# It contains project source information necessary for synthesis and implementation.
|
||||
|
||||
# IP: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/rom_freq_word/rom_freq_word.xci
|
||||
# IP: The module: 'rom_freq_word' is the root of the design. Do not add the DONT_TOUCH constraint.
|
||||
|
||||
# XDC: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/rom_freq_word/rom_freq_word_ooc.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'rom_freq_word'. Do not add the DONT_TOUCH constraint.
|
||||
set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet
|
||||
|
||||
# IP: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/rom_freq_word/rom_freq_word.xci
|
||||
# IP: The module: 'rom_freq_word' is the root of the design. Do not add the DONT_TOUCH constraint.
|
||||
|
||||
# XDC: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/rom_freq_word/rom_freq_word_ooc.xdc
|
||||
# XDC: The top module name and the constraint reference have the same name: 'rom_freq_word'. Do not add the DONT_TOUCH constraint.
|
||||
#dup# set_property DONT_TOUCH TRUE [get_cells U0 -quiet] -quiet
|
||||
-59
@@ -1,59 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="rom_freq_word_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1683878733">
|
||||
<File Type="RDS-DCP" Name="rom_freq_word.dcp"/>
|
||||
<File Type="PA-TCL" Name="rom_freq_word.tcl"/>
|
||||
<File Type="REPORTS-TCL" Name="rom_freq_word_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="rom_freq_word.vds"/>
|
||||
<File Type="RDS-UTIL-PB" Name="rom_freq_word_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="rom_freq_word_utilization_synth.rpt"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/rom_freq_word">
|
||||
<File Path="$PPRDIR/../rom_freq_word.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../rom_freq_word/rom_freq_word.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="rom_freq_word"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="BlockSrcs" RelSrcDir="$PSRCDIR/rom_freq_word">
|
||||
<File Path="$PPRDIR/../rom_freq_word.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../rom_freq_word/rom_freq_word.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="rom_freq_word"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
-9
@@ -1,9 +0,0 @@
|
||||
#
|
||||
# Vivado(TM)
|
||||
# htr.txt: a Vivado-generated description of how-to-repeat the
|
||||
# the basic steps of a run. Note that runme.bat/sh needs
|
||||
# to be invoked for Vivado to track run status.
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
vivado -log rom_freq_word.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source rom_freq_word.tcl
|
||||
-43
@@ -1,43 +0,0 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:3132:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:3132:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c636d70795f76365f305f31375c636d70795f31327838:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c6464735f636f6d70696c65725f76365f305f31385c6464735f3332625f38625f636f6d70:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c6669725f636f6d70696c65725f76375f325f31325c6669725f7072627331305f696e766572745f72657032:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c6669725f636f6d70696c65725f76375f325f31325c6669725f70726273375f696e766572745f72657034:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f667265715f636f6d70:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f72665f6175746f5f636f6e74726f6c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f72785f646174615f636e74:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c6d756c745f67656e5f7631325f305f31355c6d756c745f3138783138:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c626c6b5f6d656d5f67656e5f76385f345f335c726f6d5f667265715f776f7264:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f667265715f636f6d70:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f6d616e75616c5f6374726c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f7266636f6e74726c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3631:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3631:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3631:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3631:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3631:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3631:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3631:00:00
|
||||
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3966393835363732626435303431393139633038356339623061353561633562:506172656e742050412070726f6a656374204944:00
|
||||
eof:2136661241
|
||||
BIN
Binary file not shown.
-156
@@ -1,156 +0,0 @@
|
||||
#
|
||||
# Synthesis run script generated by Vivado
|
||||
#
|
||||
|
||||
set TIME_start [clock seconds]
|
||||
proc create_report { reportName command } {
|
||||
set status "."
|
||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
|
||||
set fp [open $status w]
|
||||
close $fp
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
set_param simulator.modelsimInstallPath /home/josh/Software/Mentor/modeltech/bin
|
||||
set_param simulator.vcsmxInstallPath /usr/synopsys/vcs/T-2022.06/bin
|
||||
set_param project.vivado.isBlockSynthRun true
|
||||
set_msg_config -msgmgr_mode ooc_run
|
||||
create_project -in_memory -part xc7k410tffg900-2
|
||||
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
set_param project.compositeFile.enableAutoGeneration 0
|
||||
set_param synth.vivado.isSynthRun true
|
||||
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
|
||||
set_property webtalk.parent_dir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/wt [current_project]
|
||||
set_property parent.project_path /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.xpr [current_project]
|
||||
set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project]
|
||||
set_property default_lib xil_defaultlib [current_project]
|
||||
set_property target_language Verilog [current_project]
|
||||
set_property ip_output_repo /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
read_ip -quiet /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/rom_freq_word/rom_freq_word.xci
|
||||
set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/rom_freq_word/rom_freq_word_ooc.xdc]
|
||||
|
||||
# Mark all dcp files as not used in implementation to prevent them from being
|
||||
# stitched into the results of this synthesis run. Any black boxes in the
|
||||
# design are intentionally left as such for best results. Dcp files will be
|
||||
# stitched into the design at a later time, either when this synthesis run is
|
||||
# opened, or when it is stitched into a dependent implementation run.
|
||||
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||
set_property used_in_implementation false $dcp
|
||||
}
|
||||
read_xdc dont_touch.xdc
|
||||
set_property used_in_implementation false [get_files dont_touch.xdc]
|
||||
set_param ips.enableIPCacheLiteLoad 1
|
||||
|
||||
set cached_ip [config_ip_cache -export -no_bom -dir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1 -new_name rom_freq_word -ip [get_ips rom_freq_word]]
|
||||
|
||||
if { $cached_ip eq {} } {
|
||||
close [open __synthesis_is_running__ w]
|
||||
|
||||
synth_design -top rom_freq_word -part xc7k410tffg900-2 -mode out_of_context
|
||||
|
||||
#---------------------------------------------------------
|
||||
# Generate Checkpoint/Stub/Simulation Files For IP Cache
|
||||
#---------------------------------------------------------
|
||||
# disable binary constraint mode for IPCache checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
|
||||
catch {
|
||||
write_checkpoint -force -noxdef -rename_prefix rom_freq_word_ rom_freq_word.dcp
|
||||
|
||||
set ipCachedFiles {}
|
||||
write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rom_freq_word_stub.v
|
||||
lappend ipCachedFiles rom_freq_word_stub.v
|
||||
|
||||
write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rom_freq_word_stub.vhdl
|
||||
lappend ipCachedFiles rom_freq_word_stub.vhdl
|
||||
|
||||
write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rom_freq_word_sim_netlist.v
|
||||
lappend ipCachedFiles rom_freq_word_sim_netlist.v
|
||||
|
||||
write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rom_freq_word_sim_netlist.vhdl
|
||||
lappend ipCachedFiles rom_freq_word_sim_netlist.vhdl
|
||||
set TIME_taken [expr [clock seconds] - $TIME_start]
|
||||
|
||||
config_ip_cache -add -dcp rom_freq_word.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips rom_freq_word]
|
||||
}
|
||||
|
||||
rename_ref -prefix_all rom_freq_word_
|
||||
|
||||
# disable binary constraint mode for synth run checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
write_checkpoint -force -noxdef rom_freq_word.dcp
|
||||
create_report "rom_freq_word_synth_1_synth_report_utilization_0" "report_utilization -file rom_freq_word_utilization_synth.rpt -pb rom_freq_word_utilization_synth.pb"
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
|
||||
} else {
|
||||
|
||||
|
||||
}; # end if cached_ip
|
||||
|
||||
add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/rom_freq_word/rom_freq_word.xci]
|
||||
|
||||
add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/rom_freq_word/rom_freq_word.xci]
|
||||
|
||||
add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/rom_freq_word/rom_freq_word.xci]
|
||||
|
||||
add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/rom_freq_word/rom_freq_word.xci]
|
||||
|
||||
add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.dcp -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/rom_freq_word/rom_freq_word.xci]
|
||||
|
||||
if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_freq_word]} {
|
||||
catch {
|
||||
file copy -force /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.v /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_freq_word
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_freq_word]} {
|
||||
catch {
|
||||
file copy -force /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_sim_netlist.vhdl /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_freq_word
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_freq_word]} {
|
||||
catch {
|
||||
file copy -force /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_freq_word
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_freq_word]} {
|
||||
catch {
|
||||
file copy -force /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_freq_word
|
||||
}
|
||||
}
|
||||
file delete __synthesis_is_running__
|
||||
close [open __synthesis_is_complete__ w]
|
||||
-451
@@ -1,451 +0,0 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Fri May 12 16:05:33 2023
|
||||
# Process ID: 1476113
|
||||
# Current directory: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1
|
||||
# Command line: vivado -log rom_freq_word.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source rom_freq_word.tcl
|
||||
# Log file: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.vds
|
||||
# Journal file: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source rom_freq_word.tcl -notrace
|
||||
Command: synth_design -top rom_freq_word -part xc7k410tffg900-2 -mode out_of_context
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t'
|
||||
INFO: [Device 21-403] Loading part xc7k410tffg900-2
|
||||
INFO: Launching helper process for spawning children vivado processes
|
||||
INFO: Helper process launched with PID 1476273
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 1824.465 ; gain = 150.719 ; free physical = 851 ; free virtual = 44252
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-638] synthesizing module 'rom_freq_word' [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/rom_freq_word/synth/rom_freq_word.vhd:67]
|
||||
Parameter C_FAMILY bound to: kintex7 - type: string
|
||||
Parameter C_XDEVICEFAMILY bound to: kintex7 - type: string
|
||||
Parameter C_ELABORATION_DIR bound to: ./ - type: string
|
||||
Parameter C_INTERFACE_TYPE bound to: 0 - type: integer
|
||||
Parameter C_AXI_TYPE bound to: 1 - type: integer
|
||||
Parameter C_AXI_SLAVE_TYPE bound to: 0 - type: integer
|
||||
Parameter C_USE_BRAM_BLOCK bound to: 0 - type: integer
|
||||
Parameter C_ENABLE_32BIT_ADDRESS bound to: 0 - type: integer
|
||||
Parameter C_CTRL_ECC_ALGO bound to: NONE - type: string
|
||||
Parameter C_HAS_AXI_ID bound to: 0 - type: integer
|
||||
Parameter C_AXI_ID_WIDTH bound to: 4 - type: integer
|
||||
Parameter C_MEM_TYPE bound to: 3 - type: integer
|
||||
Parameter C_BYTE_SIZE bound to: 9 - type: integer
|
||||
Parameter C_ALGORITHM bound to: 1 - type: integer
|
||||
Parameter C_PRIM_TYPE bound to: 1 - type: integer
|
||||
Parameter C_LOAD_INIT_FILE bound to: 1 - type: integer
|
||||
Parameter C_INIT_FILE_NAME bound to: rom_freq_word.mif - type: string
|
||||
Parameter C_INIT_FILE bound to: rom_freq_word.mem - type: string
|
||||
Parameter C_USE_DEFAULT_DATA bound to: 0 - type: integer
|
||||
Parameter C_DEFAULT_DATA bound to: 0 - type: string
|
||||
Parameter C_HAS_RSTA bound to: 0 - type: integer
|
||||
Parameter C_RST_PRIORITY_A bound to: CE - type: string
|
||||
Parameter C_RSTRAM_A bound to: 0 - type: integer
|
||||
Parameter C_INITA_VAL bound to: 0 - type: string
|
||||
Parameter C_HAS_ENA bound to: 0 - type: integer
|
||||
Parameter C_HAS_REGCEA bound to: 0 - type: integer
|
||||
Parameter C_USE_BYTE_WEA bound to: 0 - type: integer
|
||||
Parameter C_WEA_WIDTH bound to: 1 - type: integer
|
||||
Parameter C_WRITE_MODE_A bound to: WRITE_FIRST - type: string
|
||||
Parameter C_WRITE_WIDTH_A bound to: 16 - type: integer
|
||||
Parameter C_READ_WIDTH_A bound to: 16 - type: integer
|
||||
Parameter C_WRITE_DEPTH_A bound to: 81 - type: integer
|
||||
Parameter C_READ_DEPTH_A bound to: 81 - type: integer
|
||||
Parameter C_ADDRA_WIDTH bound to: 7 - type: integer
|
||||
Parameter C_HAS_RSTB bound to: 0 - type: integer
|
||||
Parameter C_RST_PRIORITY_B bound to: CE - type: string
|
||||
Parameter C_RSTRAM_B bound to: 0 - type: integer
|
||||
Parameter C_INITB_VAL bound to: 0 - type: string
|
||||
Parameter C_HAS_ENB bound to: 0 - type: integer
|
||||
Parameter C_HAS_REGCEB bound to: 0 - type: integer
|
||||
Parameter C_USE_BYTE_WEB bound to: 0 - type: integer
|
||||
Parameter C_WEB_WIDTH bound to: 1 - type: integer
|
||||
Parameter C_WRITE_MODE_B bound to: WRITE_FIRST - type: string
|
||||
Parameter C_WRITE_WIDTH_B bound to: 16 - type: integer
|
||||
Parameter C_READ_WIDTH_B bound to: 16 - type: integer
|
||||
Parameter C_WRITE_DEPTH_B bound to: 81 - type: integer
|
||||
Parameter C_READ_DEPTH_B bound to: 81 - type: integer
|
||||
Parameter C_ADDRB_WIDTH bound to: 7 - type: integer
|
||||
Parameter C_HAS_MEM_OUTPUT_REGS_A bound to: 1 - type: integer
|
||||
Parameter C_HAS_MEM_OUTPUT_REGS_B bound to: 0 - type: integer
|
||||
Parameter C_HAS_MUX_OUTPUT_REGS_A bound to: 0 - type: integer
|
||||
Parameter C_HAS_MUX_OUTPUT_REGS_B bound to: 0 - type: integer
|
||||
Parameter C_MUX_PIPELINE_STAGES bound to: 0 - type: integer
|
||||
Parameter C_HAS_SOFTECC_INPUT_REGS_A bound to: 0 - type: integer
|
||||
Parameter C_HAS_SOFTECC_OUTPUT_REGS_B bound to: 0 - type: integer
|
||||
Parameter C_USE_SOFTECC bound to: 0 - type: integer
|
||||
Parameter C_USE_ECC bound to: 0 - type: integer
|
||||
Parameter C_EN_ECC_PIPE bound to: 0 - type: integer
|
||||
Parameter C_READ_LATENCY_A bound to: 1 - type: integer
|
||||
Parameter C_READ_LATENCY_B bound to: 1 - type: integer
|
||||
Parameter C_HAS_INJECTERR bound to: 0 - type: integer
|
||||
Parameter C_SIM_COLLISION_CHECK bound to: ALL - type: string
|
||||
Parameter C_COMMON_CLK bound to: 0 - type: integer
|
||||
Parameter C_DISABLE_WARN_BHV_COLL bound to: 0 - type: integer
|
||||
Parameter C_EN_SLEEP_PIN bound to: 0 - type: integer
|
||||
Parameter C_USE_URAM bound to: 0 - type: integer
|
||||
Parameter C_EN_RDADDRA_CHG bound to: 0 - type: integer
|
||||
Parameter C_EN_RDADDRB_CHG bound to: 0 - type: integer
|
||||
Parameter C_EN_DEEPSLEEP_PIN bound to: 0 - type: integer
|
||||
Parameter C_EN_SHUTDOWN_PIN bound to: 0 - type: integer
|
||||
Parameter C_EN_SAFETY_CKT bound to: 0 - type: integer
|
||||
Parameter C_DISABLE_WARN_BHV_RANGE bound to: 0 - type: integer
|
||||
Parameter C_COUNT_36K_BRAM bound to: 0 - type: string
|
||||
Parameter C_COUNT_18K_BRAM bound to: 1 - type: string
|
||||
Parameter C_EST_POWER_SUMMARY bound to: Estimated Power for IP : 2.7096 mW - type: string
|
||||
INFO: [Synth 8-3491] module 'blk_mem_gen_v8_4_3' declared at '/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/rom_freq_word/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd:195321' bound to instance 'U0' of component 'blk_mem_gen_v8_4_3' [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/rom_freq_word/synth/rom_freq_word.vhd:230]
|
||||
INFO: [Synth 8-256] done synthesizing module 'rom_freq_word' (9#1) [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/rom_freq_word/synth/rom_freq_word.vhd:67]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port SSRA
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port CLKB
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port SSRB
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ENB
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port REGCEB
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port WEB[0]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[8]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[7]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[6]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[5]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[4]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[3]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[2]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[1]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ADDRB[0]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[35]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[34]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[33]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[32]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[31]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[30]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[29]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[28]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[27]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[26]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[25]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[24]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[23]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[22]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[21]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[20]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[19]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[18]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[17]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[16]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[15]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[14]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[13]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[12]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[11]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[10]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[9]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[8]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[7]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[6]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[5]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[4]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[3]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[2]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[1]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port DINB[0]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port SLEEP
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port INJECTSBITERR
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port INJECTDBITERR
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ECCPIPECE
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ram_rstram_b
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_prim_wrapper_init has unconnected port ram_rstreg_b
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port RSTA[0]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port WEA[1]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port REGCEB[0]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port WEB[1]
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port INJECTSBITERR
|
||||
WARNING: [Synth 8-3331] design blk_mem_gen_generic_cstr has unconnected port INJECTDBITERR
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port CLKB
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[15]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[14]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[13]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[12]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[11]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[10]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[9]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[8]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[7]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[6]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[5]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[4]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[3]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[2]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[1]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DOUTB_I[0]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port SBITERR_I
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port DBITERR_I
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[6]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[5]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[4]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[3]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[2]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[1]
|
||||
WARNING: [Synth 8-3331] design blk_mem_output_block has unconnected port RDADDRECC_I[0]
|
||||
WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port RSTA
|
||||
WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port ENA
|
||||
WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port REGCEA
|
||||
WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port WEA[0]
|
||||
WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[15]
|
||||
WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[14]
|
||||
WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[13]
|
||||
WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[12]
|
||||
WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[11]
|
||||
WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[10]
|
||||
WARNING: [Synth 8-3331] design blk_mem_input_block has unconnected port DINA[9]
|
||||
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2038.176 ; gain = 364.430 ; free physical = 1600 ; free virtual = 45063
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2050.051 ; gain = 376.305 ; free physical = 1621 ; free virtual = 45083
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:27 ; elapsed = 00:00:32 . Memory (MB): peak = 2050.051 ; gain = 376.305 ; free physical = 1621 ; free virtual = 45083
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
|
||||
Processing XDC Constraints
|
||||
Initializing timing engine
|
||||
Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/rom_freq_word/rom_freq_word_ooc.xdc] for cell 'U0'
|
||||
Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/rom_freq_word/rom_freq_word_ooc.xdc] for cell 'U0'
|
||||
Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/dont_touch.xdc]
|
||||
Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/dont_touch.xdc]
|
||||
Completed Processing XDC Constraints
|
||||
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2122.988 ; gain = 0.000 ; free physical = 1591 ; free virtual = 45056
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2122.988 ; gain = 0.000 ; free physical = 1590 ; free virtual = 45055
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1596 ; free virtual = 45061
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7k410tffg900-2
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1595 ; free virtual = 45060
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying 'set_property' XDC Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
Applied set_property DONT_TOUCH = true for U0. (constraint file /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/dont_touch.xdc, line 9).
|
||||
---------------------------------------------------------------------------------
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1594 ; free virtual = 45059
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1585 ; free virtual = 45050
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Detailed RTL Component Info :
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Hierarchical RTL Component report
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 1540 (col length:140)
|
||||
BRAMs: 1590 (col length: RAMB18 140 RAMB36 70)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
Warning: Parallel synthesis criteria is not met
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:30 ; elapsed = 00:00:35 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1607 ; free virtual = 45073
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying XDC Timing Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1508 ; free virtual = 44984
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1508 ; free virtual = 44984
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:32 ; elapsed = 00:00:38 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1507 ; free virtual = 44984
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1519 ; free virtual = 44996
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1519 ; free virtual = 44996
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1519 ; free virtual = 44996
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1519 ; free virtual = 44996
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1519 ; free virtual = 44996
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1519 ; free virtual = 44996
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+---------+------+
|
||||
| |Cell |Count |
|
||||
+------+---------+------+
|
||||
|1 |RAMB18E1 | 1|
|
||||
+------+---------+------+
|
||||
|
||||
Report Instance Areas:
|
||||
+------+---------------------------------------------+------------------------------+------+
|
||||
| |Instance |Module |Cells |
|
||||
+------+---------------------------------------------+------------------------------+------+
|
||||
|1 |top | | 1|
|
||||
|2 | U0 |blk_mem_gen_v8_4_3 | 1|
|
||||
|3 | inst_blk_mem_gen |blk_mem_gen_v8_4_3_synth | 1|
|
||||
|4 | \gnbram.gnativebmg.native_blk_mem_gen |blk_mem_gen_top | 1|
|
||||
|5 | \valid.cstr |blk_mem_gen_generic_cstr | 1|
|
||||
|6 | \ramloop[0].ram.r |blk_mem_gen_prim_width | 1|
|
||||
|7 | \prim_init.ram |blk_mem_gen_prim_wrapper_init | 1|
|
||||
+------+---------------------------------------------+------------------------------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1519 ; free virtual = 44996
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 179 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:31 ; elapsed = 00:00:37 . Memory (MB): peak = 2122.988 ; gain = 376.305 ; free physical = 1573 ; free virtual = 45050
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:33 ; elapsed = 00:00:38 . Memory (MB): peak = 2122.988 ; gain = 449.242 ; free physical = 1573 ; free virtual = 45050
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2122.988 ; gain = 0.000 ; free physical = 1516 ; free virtual = 44993
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
17 Infos, 100 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:40 . Memory (MB): peak = 2122.988 ; gain = 728.012 ; free physical = 1605 ; free virtual = 45082
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2122.988 ; gain = 0.000 ; free physical = 1605 ; free virtual = 45082
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.dcp' has been generated.
|
||||
WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
|
||||
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP rom_freq_word, cache-ID = 56186d833b788b44
|
||||
INFO: [Coretcl 2-1174] Renamed 6 cell refs.
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2122.988 ; gain = 0.000 ; free physical = 1595 ; free virtual = 45072
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file rom_freq_word_utilization_synth.rpt -pb rom_freq_word_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Fri May 12 16:06:19 2023...
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
-22
@@ -1,22 +0,0 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Fri May 12 16:06:19 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.v
|
||||
// Design : rom_freq_word
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *)
|
||||
module rom_freq_word(clka, addra, douta)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clka,addra[6:0],douta[15:0]" */;
|
||||
input clka;
|
||||
input [6:0]addra;
|
||||
output [15:0]douta;
|
||||
endmodule
|
||||
-32
@@ -1,32 +0,0 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Fri May 12 16:06:19 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1/rom_freq_word_stub.vhdl
|
||||
-- Design : rom_freq_word
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity rom_freq_word is
|
||||
Port (
|
||||
clka : in STD_LOGIC;
|
||||
addra : in STD_LOGIC_VECTOR ( 6 downto 0 );
|
||||
douta : out STD_LOGIC_VECTOR ( 15 downto 0 )
|
||||
);
|
||||
|
||||
end rom_freq_word;
|
||||
|
||||
architecture stub of rom_freq_word is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clka,addra[6:0],douta[15:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
BIN
Binary file not shown.
-174
@@ -1,174 +0,0 @@
|
||||
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
| Date : Fri May 12 16:06:18 2023
|
||||
| Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
| Command : report_utilization -file rom_freq_word_utilization_synth.rpt -pb rom_freq_word_utilization_synth.pb
|
||||
| Design : rom_freq_word
|
||||
| Device : 7k410tffg900-2
|
||||
| Design State : Synthesized
|
||||
---------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Slice Logic
|
||||
1.1 Summary of Registers by Type
|
||||
2. Memory
|
||||
3. DSP
|
||||
4. IO and GT Specific
|
||||
5. Clocking
|
||||
6. Specific Feature
|
||||
7. Primitives
|
||||
8. Black Boxes
|
||||
9. Instantiated Netlists
|
||||
|
||||
1. Slice Logic
|
||||
--------------
|
||||
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
| Slice LUTs* | 0 | 0 | 254200 | 0.00 |
|
||||
| LUT as Logic | 0 | 0 | 254200 | 0.00 |
|
||||
| LUT as Memory | 0 | 0 | 90600 | 0.00 |
|
||||
| Slice Registers | 0 | 0 | 508400 | 0.00 |
|
||||
| Register as Flip Flop | 0 | 0 | 508400 | 0.00 |
|
||||
| Register as Latch | 0 | 0 | 508400 | 0.00 |
|
||||
| F7 Muxes | 0 | 0 | 127100 | 0.00 |
|
||||
| F8 Muxes | 0 | 0 | 63550 | 0.00 |
|
||||
+-------------------------+------+-------+-----------+-------+
|
||||
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
|
||||
|
||||
|
||||
1.1 Summary of Registers by Type
|
||||
--------------------------------
|
||||
|
||||
+-------+--------------+-------------+--------------+
|
||||
| Total | Clock Enable | Synchronous | Asynchronous |
|
||||
+-------+--------------+-------------+--------------+
|
||||
| 0 | _ | - | - |
|
||||
| 0 | _ | - | Set |
|
||||
| 0 | _ | - | Reset |
|
||||
| 0 | _ | Set | - |
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 0 | Yes | - | Set |
|
||||
| 0 | Yes | - | Reset |
|
||||
| 0 | Yes | Set | - |
|
||||
| 0 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
2. Memory
|
||||
---------
|
||||
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
| Block RAM Tile | 0.5 | 0 | 795 | 0.06 |
|
||||
| RAMB36/FIFO* | 0 | 0 | 795 | 0.00 |
|
||||
| RAMB18 | 1 | 0 | 1590 | 0.06 |
|
||||
| RAMB18E1 only | 1 | | | |
|
||||
+-------------------+------+-------+-----------+-------+
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
|
||||
3. DSP
|
||||
------
|
||||
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
| DSPs | 0 | 0 | 1540 | 0.00 |
|
||||
+-----------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
4. IO and GT Specific
|
||||
---------------------
|
||||
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
| Bonded IOB | 0 | 0 | 500 | 0.00 |
|
||||
| Bonded IPADs | 0 | 0 | 50 | 0.00 |
|
||||
| Bonded OPADs | 0 | 0 | 32 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 10 | 0.00 |
|
||||
| PHASER_REF | 0 | 0 | 10 | 0.00 |
|
||||
| OUT_FIFO | 0 | 0 | 40 | 0.00 |
|
||||
| IN_FIFO | 0 | 0 | 40 | 0.00 |
|
||||
| IDELAYCTRL | 0 | 0 | 10 | 0.00 |
|
||||
| IBUFDS | 0 | 0 | 480 | 0.00 |
|
||||
| GTXE2_COMMON | 0 | 0 | 4 | 0.00 |
|
||||
| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 |
|
||||
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 40 | 0.00 |
|
||||
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 40 | 0.00 |
|
||||
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 500 | 0.00 |
|
||||
| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 |
|
||||
| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 |
|
||||
| ILOGIC | 0 | 0 | 500 | 0.00 |
|
||||
| OLOGIC | 0 | 0 | 500 | 0.00 |
|
||||
+-----------------------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
5. Clocking
|
||||
-----------
|
||||
|
||||
+------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+------------+------+-------+-----------+-------+
|
||||
| BUFGCTRL | 0 | 0 | 32 | 0.00 |
|
||||
| BUFIO | 0 | 0 | 40 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 10 | 0.00 |
|
||||
| PLLE2_ADV | 0 | 0 | 10 | 0.00 |
|
||||
| BUFMRCE | 0 | 0 | 20 | 0.00 |
|
||||
| BUFHCE | 0 | 0 | 168 | 0.00 |
|
||||
| BUFR | 0 | 0 | 40 | 0.00 |
|
||||
+------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
6. Specific Feature
|
||||
-------------------
|
||||
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Available | Util% |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
| BSCANE2 | 0 | 0 | 4 | 0.00 |
|
||||
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
|
||||
| DNA_PORT | 0 | 0 | 1 | 0.00 |
|
||||
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
|
||||
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
|
||||
| ICAPE2 | 0 | 0 | 2 | 0.00 |
|
||||
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
|
||||
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
|
||||
| XADC | 0 | 0 | 1 | 0.00 |
|
||||
+-------------+------+-------+-----------+-------+
|
||||
|
||||
|
||||
7. Primitives
|
||||
-------------
|
||||
|
||||
+----------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+------+---------------------+
|
||||
| RAMB18E1 | 1 | Block Memory |
|
||||
+----------+------+---------------------+
|
||||
|
||||
|
||||
8. Black Boxes
|
||||
--------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
9. Instantiated Netlists
|
||||
------------------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
-40
@@ -1,40 +0,0 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
echo "This script was generated under a different operating system."
|
||||
echo "Please update the PATH variable below, before executing this script"
|
||||
exit
|
||||
|
||||
var WshShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ProcEnv = WshShell.Environment( "Process" );
|
||||
var PathVal = ProcEnv("PATH");
|
||||
if ( PathVal.length == 0 ) {
|
||||
PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;";
|
||||
} else {
|
||||
PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;" + PathVal;
|
||||
}
|
||||
|
||||
ProcEnv("PATH") = PathVal;
|
||||
|
||||
var RDScrFP = WScript.ScriptFullName;
|
||||
var RDScrN = WScript.ScriptName;
|
||||
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
|
||||
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
|
||||
eval( EAInclude(ISEJScriptLib) );
|
||||
|
||||
|
||||
ISEStep( "vivado",
|
||||
"-log rom_freq_word.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source rom_freq_word.tcl" );
|
||||
|
||||
|
||||
|
||||
function EAInclude( EAInclFilename ) {
|
||||
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
|
||||
var EAIFContents = EAInclFile.ReadAll();
|
||||
EAInclFile.Close();
|
||||
return EAIFContents;
|
||||
}
|
||||
-11
@@ -1,11 +0,0 @@
|
||||
@echo off
|
||||
|
||||
rem Vivado (TM)
|
||||
rem runme.bat: a Vivado-generated Script
|
||||
rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
|
||||
set HD_SDIR=%~dp0
|
||||
cd /d "%HD_SDIR%"
|
||||
set PATH=%SYSTEMROOT%\system32;%PATH%
|
||||
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
|
||||
-39
@@ -1,39 +0,0 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# runme.sh: a Vivado-generated Runs Script for UNIX
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
if [ -z "$PATH" ]; then
|
||||
PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin
|
||||
else
|
||||
PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin:$PATH
|
||||
fi
|
||||
export PATH
|
||||
|
||||
if [ -z "$LD_LIBRARY_PATH" ]; then
|
||||
LD_LIBRARY_PATH=
|
||||
else
|
||||
LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
|
||||
fi
|
||||
export LD_LIBRARY_PATH
|
||||
|
||||
HD_PWD='/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/rom_freq_word_synth_1'
|
||||
cd "$HD_PWD"
|
||||
|
||||
HD_LOG=runme.log
|
||||
/bin/touch $HD_LOG
|
||||
|
||||
ISEStep="./ISEWrap.sh"
|
||||
EAStep()
|
||||
{
|
||||
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
|
||||
if [ $? -ne 0 ]
|
||||
then
|
||||
exit
|
||||
fi
|
||||
}
|
||||
|
||||
EAStep vivado -log rom_freq_word.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source rom_freq_word.tcl
|
||||
BIN
Binary file not shown.
+1
-1
@@ -1,5 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado" Owner="josh" Host="JOSH-ASUS-Z690" Pid="1470064" HostCore="20" HostMemory="65588992">
|
||||
<Process Command="vivado" Owner="josh" Host="JOSH-ASUS-Z690" Pid="1619476" HostCore="20" HostMemory="65576700">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
|
||||
+7
-4
@@ -1,11 +1,14 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="vio_rfcontrl_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1683878330">
|
||||
<GenRun Id="vio_rfcontrl_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1690716574">
|
||||
<File Type="VDS-TIMING-PB" Name="vio_rfcontrl_timing_summary_synth.pb"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="vio_rfcontrl_timing_summary_synth.rpt"/>
|
||||
<File Type="RDS-DCP" Name="vio_rfcontrl.dcp"/>
|
||||
<File Type="PA-TCL" Name="vio_rfcontrl.tcl"/>
|
||||
<File Type="REPORTS-TCL" Name="vio_rfcontrl_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="vio_rfcontrl.vds"/>
|
||||
<File Type="RDS-UTIL-PB" Name="vio_rfcontrl_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="vio_rfcontrl_utilization_synth.rpt"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="vio_rfcontrl_drc_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="vio_rfcontrl.vds"/>
|
||||
<File Type="REPORTS-TCL" Name="vio_rfcontrl_reports.tcl"/>
|
||||
<File Type="PA-TCL" Name="vio_rfcontrl.tcl"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_rfcontrl">
|
||||
<File Path="$PPRDIR/../vio_rfcontrl.xcix">
|
||||
<FileInfo>
|
||||
|
||||
+14
-13
@@ -1,23 +1,24 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:36:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:37:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:3130:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:3130:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c636d70795f76365f305f31375c636d70795f31327838:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c6464735f636f6d70696c65725f76365f305f31385c6464735f3332625f38625f636f6d70:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c6669666f5f67656e657261746f725f7631335f325f345c6669666f5f72785f64617461:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c6669725f636f6d70696c65725f76375f325f31325c6669725f7072627331305f696e766572745f72657032:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c6669725f636f6d70696c65725f76375f325f31325c6669725f70726273375f696e766572745f72657034:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f667265715f636f6d70:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f72665f6175746f5f636f6e74726f6c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f72785f646174615f636e74:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c6d756c745f67656e5f7631325f305f31355c6d756c745f3138783138:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c626c6b5f6d656d5f67656e5f76385f345f335c726f6d5f667265715f776f7264:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f667265715f636f6d70:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
@@ -30,12 +31,12 @@ version:1
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3534:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3534:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3534:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3534:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3534:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3534:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3534:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3730:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3730:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3730:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3730:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3730:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3730:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3730:00:00
|
||||
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3966393835363732626435303431393139633038356339623061353561633562:506172656e742050412070726f6a656374204944:00
|
||||
eof:3228103618
|
||||
eof:946412261
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user