Archived
add ant data; add null algorithm switch
to evaluate amp-phase consistency of phased array at different frequency, tens of data set is sampled; in dl814_k7_cal_coarse, the switch of ad9361 data and test data is added, and the depth of rx data ila is enlarged to 131072
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 04/21/2023 11:37:14 AM
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// Design Name:
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// Module Name: truncate_manual
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module truncate_manual
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#(
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DATA_I_WIDTH = 30,
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DATA_O_WIDTH = 12
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)
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(
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input clk,
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input rst,
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input [DATA_I_WIDTH-1 : 0] data_in,
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input data_in_valid,
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input [$clog2(DATA_I_WIDTH)-1 : 0] trunc_pos,
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output [DATA_O_WIDTH-1 : 0] data_out,
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output data_out_valid
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);
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assign data_out = data_in[trunc_pos -: DATA_O_WIDTH];
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endmodule
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LFS
Executable → Regular
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end
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end
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weight_stream_data_ind
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weight_stream_data_index = 1;
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flag = 1;
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while (flag)
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weight_stream_data_str = num2str(weight_stream_data((1:32)+weight_stream_data_index-1)');
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tmp = bin2dec(erase(convertCharsToStrings(weight_stream_data_str)," "));
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if (tmp == hex2dec("7E7E7E7E"))
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flag = 0;
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else
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weight_stream_data_index = weight_stream_data_index + 1;
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end
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end
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+204
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%% File Header/文件说明
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%
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% Beamforming with phased array derives signal characteristics from phase
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% differences between sensors. Therefore the amplitude-phase consistence is
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% vital to phased systems.
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%
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% The script analyzes the amp-phase relations of ILA captured data, the format
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% of which is square-shaped pseudorandorm bit sequence. Each channel is
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% processed seperately with different frequency shifts and different optimum
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% sampling points. The estimation of amplitude and phase are based on
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% acculumated correlation peaks.
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%
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clc; clear;
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%% initial parameters/初始参数
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interp = 8; % interpolation factor
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channelNum = 4;
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dataLen = 8192;
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fs = 48e6;
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dataFile = [...
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"iladata_25.0G_1-1.csv",...
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"iladata_25.0G_1-2.csv",...
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"iladata_25.0G_1-3.csv",...
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"iladata_25.1G_1-1.csv",...
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"iladata_25.1G_1-2.csv",...
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"iladata_25.1G_1-3.csv",...
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"iladata_25.2G_1-1.csv",...
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"iladata_25.2G_1-2.csv",...
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"iladata_25.2G_1-3.csv",...
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"iladata_25.3G_1-1.csv",...
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"iladata_25.3G_1-2.csv",...
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"iladata_25.3G_1-3.csv",...
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"iladata_25.4G_1-1.csv",...
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"iladata_25.4G_1-2.csv",...
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"iladata_25.4G_1-3.csv",...
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"iladata_25.5G_1-1.csv",...
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"iladata_25.5G_1-2.csv",...
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"iladata_25.5G_1-3.csv",...
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"iladata_25.6G_1-1.csv",...
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"iladata_25.6G_1-2.csv",...
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"iladata_25.6G_1-3.csv",...
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"iladata_25.7G_1-1.csv",...
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"iladata_25.7G_1-2.csv",...
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"iladata_25.7G_1-3.csv",...
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"iladata_25.8G_1-1.csv",...
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"iladata_25.8G_1-2.csv",...
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"iladata_25.8G_1-3.csv",...
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"iladata_25.9G_1-1.csv",...
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"iladata_25.9G_1-2.csv",...
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"iladata_25.9G_1-3.csv",...
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"iladata_26.0G_1-1.csv",...
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"iladata_26.0G_1-2.csv",...
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"iladata_26.0G_1-3.csv",...
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"iladata_26.1G_1-1.csv",...
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"iladata_26.1G_1-2.csv",...
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"iladata_26.1G_1-3.csv",...
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"iladata_26.2G_1-1.csv",...
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"iladata_26.2G_1-2.csv",...
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"iladata_26.2G_1-3.csv",...
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"iladata_26.3G_1-1.csv",...
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"iladata_26.3G_1-2.csv",...
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"iladata_26.3G_1-3.csv",...
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"iladata_26.4G_1-1.csv",...
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"iladata_26.4G_1-2.csv",...
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"iladata_26.4G_1-3.csv",...
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"iladata_26.5G_1-1.csv",...
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"iladata_26.5G_1-2.csv",...
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"iladata_26.5G_1-3.csv",...
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"iladata_26.6G_1-1.csv",...
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"iladata_26.6G_1-2.csv",...
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"iladata_26.6G_1-3.csv",...
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"iladata_26.7G_1-1.csv",...
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"iladata_26.7G_1-2.csv",...
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"iladata_26.8G_1-1.csv",...
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"iladata_26.8G_1-2.csv",...
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"iladata_26.8G_1-3.csv",...
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"iladata_26.9G_1-1.csv",...
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"iladata_26.9G_1-2.csv",...
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"iladata_26.9G_1-3.csv",...
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"iladata_27.0G_1-1.csv",...
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"iladata_27.0G_1-2.csv",...
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"iladata_27.0G_1-3.csv",...
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];
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dataFileNum = length(dataFile);
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% standard pn sequence
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pnSequence = comm.PNSequence('Polynomial','x^7+x^6+1', ...
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'InitialConditions',[zeros(1,6),1],'SamplesPerFrame',2^7-1);
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PRBS7 = pnSequence();
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PRBS7_polar = 1-2*[PRBS7;0];
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chipLen = length(PRBS7_polar); % pn chip length
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symNum = dataLen/chipLen/interp; % total symbol number
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symNumPerAccum = 1; % symbol nbumber of each accumulation
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accNum = symNum/symNumPerAccum; % total accumulation numbers, i.e. peak numbers
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ampEstSymMax = zeros(dataFileNum,channelNum);
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ampEstSymMin = zeros(dataFileNum,channelNum);
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ampEstSymAvg = zeros(dataFileNum,channelNum);
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angleEstSymMax = zeros(dataFileNum,channelNum);
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angleEstSymMin = zeros(dataFileNum,channelNum);
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angleEstSymAvg = zeros(dataFileNum,channelNum);
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ampEstSymMaxList = strings(dataFileNum+1,channelNum+1);
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ampEstSymMinList = strings(dataFileNum+1,channelNum+1);
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ampEstSymAvgList = strings(dataFileNum+1,channelNum+1);
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angleEstSymMaxList = strings(dataFileNum+1,channelNum+1);
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angleEstSymMinList = strings(dataFileNum+1,channelNum+1);
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angleEstSymAvgList = strings(dataFileNum+1,channelNum+1);
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ampEstSymMaxList(1,:) = ["Amp Max Value", "ch1", "ch2", "ch3", "ch4"];
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ampEstSymMinList(1,:) = ["Amp Min Value", "ch1", "ch2", "ch3", "ch4"];
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ampEstSymAvgList(1,:) = ["Amp Avg Value", "ch1", "ch2", "ch3", "ch4"];
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angleEstSymMaxList(1,:) = ["Angle Max Value", "ch1", "ch2", "ch3", "ch4"];
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angleEstSymMinList(1,:) = ["Angle Min Value", "ch1", "ch2", "ch3", "ch4"];
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angleEstSymAvgList(1,:) = ["Angle Avg Value", "ch1", "ch2", "ch3", "ch4"];
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ampEstSymMaxList(2:end,1) = dataFile;
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ampEstSymMinList(2:end,1) = dataFile;
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ampEstSymAvgList(2:end,1) = dataFile;
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angleEstSymMaxList(2:end,1) = dataFile;
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angleEstSymMinList(2:end,1) = dataFile;
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angleEstSymAvgList(2:end,1) = dataFile;
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for dataFileIndex = 1:dataFileNum
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disp(dataFile(dataFileIndex));
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%% data analysis
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% read data, and swap ch1 and ch2, because loop data locate at ch2 and ch4
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rxdata = readmatrix(dataFile(dataFileIndex));
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seqRx(:,1) = (rxdata(:, 6) + 1i*rxdata(:, 7)).';
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seqRx(:,2) = (rxdata(:, 4) + 1i*rxdata(:, 5)).';
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seqRx(:,3) = (rxdata(:, 8) + 1i*rxdata(:, 9)).';
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seqRx(:,4) = (rxdata(:,10) + 1i*rxdata(:,11)).';
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% compensate frequecny deviation and downsample at optimum sample position based
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% on the varience of constellation
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[seqRxDown,fd,samplePos] = suqareShapeFreqEst(seqRx,interp,fs,-25000,-21000,5);
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% split [seqRxDown] into multiple groups, each group contains several symbols to
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% be correlated with PRBS7 and accumulated
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seqRxDownSplit = reshape(seqRxDown(1:dataLen/interp,:),chipLen*symNumPerAccum, ...
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accNum,channelNum);
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seqRxAcc = zeros(chipLen,accNum,channelNum);
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desiredPnt = zeros(accNum,channelNum);
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ampEstSym = zeros(accNum,channelNum);
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angleEstSym = zeros(accNum,channelNum);
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for i = 1:accNum
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for j = 1:channelNum
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% correlation & multi-symbol accumulation
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groupCorrAcc = sum(...
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reshape(...
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conv(...
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flip(seqRxDownSplit(:,i,j)),...
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PRBS7_polar,'same'),...
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chipLen,symNumPerAccum),...
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2)';
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seqRxAcc(:,i,j) = groupCorrAcc;
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% peak position
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desiredPnt(i,j) = groupCorrAcc(abs(groupCorrAcc)==max(abs(groupCorrAcc)));
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end
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end
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for i = 1:channelNum
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ampEstSym(:,i) = abs(desiredPnt(:,i))./abs(desiredPnt(:,1));
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angleEstSym(:,i) = mod((angle(desiredPnt(:,i))-angle(desiredPnt(:,1)))/pi*180,360);
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end
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ampEstSymMax(dataFileIndex,:) = max(ampEstSym);
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ampEstSymMin(dataFileIndex,:) = min(ampEstSym);
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ampEstSymAvg(dataFileIndex,:) = mean(ampEstSym);
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angleEstSymMax(dataFileIndex,:) = max(angleEstSym);
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angleEstSymMin(dataFileIndex,:) = min(angleEstSym);
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angleEstSymAvg(dataFileIndex,:) = mean(angleEstSym);
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ampEstSymMaxList(dataFileIndex+1,2:end) = string(ampEstSymMax(dataFileIndex,:));
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ampEstSymMinList(dataFileIndex+1,2:end) = string(ampEstSymMin(dataFileIndex,:));
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ampEstSymAvgList(dataFileIndex+1,2:end) = string(ampEstSymAvg(dataFileIndex,:));
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angleEstSymMaxList(dataFileIndex+1,2:end) = string(angleEstSymMax(dataFileIndex,:));
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angleEstSymMinList(dataFileIndex+1,2:end) = string(angleEstSymMin(dataFileIndex,:));
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angleEstSymAvgList(dataFileIndex+1,2:end) = string(angleEstSymAvg(dataFileIndex,:));
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end
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%% figures
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% figure(1);
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%
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% subplot(121);
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% plot(ampEstSym);
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% legend({"ch1","ch2","ch3","ch4"});
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% title("Amplitude Estimation");
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% ylim([min(ampEstSym,[],'all')-0.2,max(ampEstSym,[],'all')+0.2]);
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% grid on; grid minor;
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%
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% subplot(122);
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% plot(angleEstSym);
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% legend({"ch1","ch2","ch3","ch4"});
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% title("Angle Estimation");
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% ylim([-10,370]);
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% grid on; grid minor;
|
||||
+199
@@ -0,0 +1,199 @@
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%% File Header/文件说明
|
||||
%
|
||||
% Beamforming with phased array derives signal characteristics from phase
|
||||
% differences between sensors. Therefore the amplitude-phase consistence is
|
||||
% vital to phased systems.
|
||||
%
|
||||
% The script analyzes the amp-phase relations of ILA captured data, the format
|
||||
% of which is square-shaped pseudorandorm bit sequence. Each channel is
|
||||
% processed seperately with different frequency shifts and different optimum
|
||||
% sampling points. The estimation of amplitude and phase are based on
|
||||
% acculumated correlation peaks.
|
||||
%
|
||||
clc; clear;
|
||||
%% initial parameters/初始参数
|
||||
interp = 8; % interpolation factor
|
||||
channelNum = 4;
|
||||
dataLen = 8192;
|
||||
fs = 48e6;
|
||||
dataFile = [...
|
||||
"iladata_25.0G_1-1.csv",...
|
||||
"iladata_25.0G_1-2.csv",...
|
||||
"iladata_25.0G_1-3.csv",...
|
||||
"iladata_25.1G_1-1.csv",...
|
||||
"iladata_25.1G_1-2.csv",...
|
||||
"iladata_25.1G_1-3.csv",...
|
||||
"iladata_25.2G_1-1.csv",...
|
||||
"iladata_25.2G_1-2.csv",...
|
||||
"iladata_25.2G_1-3.csv",...
|
||||
"iladata_25.3G_1-1.csv",...
|
||||
"iladata_25.3G_1-2.csv",...
|
||||
"iladata_25.3G_1-3.csv",...
|
||||
"iladata_25.4G_1-1.csv",...
|
||||
"iladata_25.4G_1-2.csv",...
|
||||
"iladata_25.4G_1-3.csv",...
|
||||
"iladata_25.5G_1-1.csv",...
|
||||
"iladata_25.5G_1-2.csv",...
|
||||
"iladata_25.5G_1-3.csv",...
|
||||
"iladata_25.6G_1-1.csv",...
|
||||
"iladata_25.6G_1-2.csv",...
|
||||
"iladata_25.6G_1-3.csv",...
|
||||
"iladata_25.7G_1-1.csv",...
|
||||
"iladata_25.7G_1-2.csv",...
|
||||
"iladata_25.7G_1-3.csv",...
|
||||
"iladata_25.8G_1-1.csv",...
|
||||
"iladata_25.8G_1-2.csv",...
|
||||
"iladata_25.8G_1-3.csv",...
|
||||
"iladata_25.9G_1-1.csv",...
|
||||
"iladata_25.9G_1-2.csv",...
|
||||
"iladata_25.9G_1-3.csv",...
|
||||
"iladata_26.0G_1-1.csv",...
|
||||
"iladata_26.0G_1-2.csv",...
|
||||
"iladata_26.0G_1-3.csv",...
|
||||
"iladata_26.1G_1-1.csv",...
|
||||
"iladata_26.1G_1-2.csv",...
|
||||
"iladata_26.1G_1-3.csv",...
|
||||
"iladata_26.2G_1-1.csv",...
|
||||
"iladata_26.2G_1-2.csv",...
|
||||
"iladata_26.2G_1-3.csv",...
|
||||
"iladata_26.3G_1-1.csv",...
|
||||
"iladata_26.3G_1-2.csv",...
|
||||
"iladata_26.3G_1-3.csv",...
|
||||
"iladata_26.4G_1-1.csv",...
|
||||
"iladata_26.4G_1-2.csv",...
|
||||
"iladata_26.4G_1-3.csv",...
|
||||
"iladata_26.5G_1-1.csv",...
|
||||
"iladata_26.5G_1-2.csv",...
|
||||
"iladata_26.5G_1-3.csv",...
|
||||
"iladata_26.6G_1-1.csv",...
|
||||
"iladata_26.6G_1-2.csv",...
|
||||
"iladata_26.6G_1-3.csv",...
|
||||
"iladata_26.7G_1-1.csv",...
|
||||
"iladata_26.7G_1-2.csv",...
|
||||
"iladata_26.8G_1-1.csv",...
|
||||
"iladata_26.8G_1-2.csv",...
|
||||
"iladata_26.8G_1-3.csv",...
|
||||
"iladata_26.9G_1-1.csv",...
|
||||
"iladata_26.9G_1-2.csv",...
|
||||
"iladata_26.9G_1-3.csv",...
|
||||
"iladata_27.0G_1-1.csv",...
|
||||
"iladata_27.0G_1-2.csv",...
|
||||
"iladata_27.0G_1-3.csv",...
|
||||
];
|
||||
dataFileNum = length(dataFile);
|
||||
|
||||
% standard pn sequence
|
||||
pnSequence = comm.PNSequence('Polynomial','x^7+x^6+1', ...
|
||||
'InitialConditions',[zeros(1,6),1],'SamplesPerFrame',2^7-1);
|
||||
PRBS7 = pnSequence();
|
||||
PRBS7_polar = 1-2*[PRBS7;0];
|
||||
|
||||
chipLen = length(PRBS7_polar); % pn chip length
|
||||
symNum = dataLen/chipLen/interp; % total symbol number
|
||||
symNumPerAccum = 1; % symbol nbumber of each accumulation
|
||||
accNum = symNum/symNumPerAccum; % total accumulation numbers, i.e. peak numbers
|
||||
|
||||
ampEstSymMax = zeros(dataFileNum,channelNum);
|
||||
ampEstSymMin = zeros(dataFileNum,channelNum);
|
||||
ampEstSymAvg = zeros(dataFileNum,channelNum);
|
||||
angleEstSymMax = zeros(dataFileNum,channelNum);
|
||||
angleEstSymMin = zeros(dataFileNum,channelNum);
|
||||
angleEstSymAvg = zeros(dataFileNum,channelNum);
|
||||
|
||||
ampEstSymMaxList = strings(dataFileNum+1,channelNum+1);
|
||||
ampEstSymMinList = strings(dataFileNum+1,channelNum+1);
|
||||
ampEstSymAvgList = strings(dataFileNum+1,channelNum+1);
|
||||
angleEstSymMaxList = strings(dataFileNum+1,channelNum+1);
|
||||
angleEstSymMinList = strings(dataFileNum+1,channelNum+1);
|
||||
angleEstSymAvgList = strings(dataFileNum+1,channelNum+1);
|
||||
|
||||
ampEstSymMaxList(1,:) = ["Amp Max Value", "ch1", "ch2", "ch3", "ch4"];
|
||||
ampEstSymMinList(1,:) = ["Amp Min Value", "ch1", "ch2", "ch3", "ch4"];
|
||||
ampEstSymAvgList(1,:) = ["Amp Avg Value", "ch1", "ch2", "ch3", "ch4"];
|
||||
angleEstSymMaxList(1,:) = ["Angle Max Value", "ch1", "ch2", "ch3", "ch4"];
|
||||
angleEstSymMinList(1,:) = ["Angle Min Value", "ch1", "ch2", "ch3", "ch4"];
|
||||
angleEstSymAvgList(1,:) = ["Angle Avg Value", "ch1", "ch2", "ch3", "ch4"];
|
||||
|
||||
ampEstSymMaxList(2:end,1) = dataFile;
|
||||
ampEstSymMinList(2:end,1) = dataFile;
|
||||
ampEstSymAvgList(2:end,1) = dataFile;
|
||||
angleEstSymMaxList(2:end,1) = dataFile;
|
||||
angleEstSymMinList(2:end,1) = dataFile;
|
||||
angleEstSymAvgList(2:end,1) = dataFile;
|
||||
|
||||
for dataFileIndex = 1:dataFileNum
|
||||
disp(dataFile(dataFileIndex));
|
||||
|
||||
%% data analysis
|
||||
|
||||
% read data, and swap ch1 and ch2, because loop data locate at ch2 and ch4
|
||||
rxdata = readmatrix(dataFile(dataFileIndex));
|
||||
seqRx(:,1) = (rxdata(:, 6) + 1i*rxdata(:, 7)).';
|
||||
seqRx(:,2) = (rxdata(:, 4) + 1i*rxdata(:, 5)).';
|
||||
seqRx(:,3) = (rxdata(:, 8) + 1i*rxdata(:, 9)).';
|
||||
seqRx(:,4) = (rxdata(:,10) + 1i*rxdata(:,11)).';
|
||||
|
||||
% compensate frequecny deviation and downsample at optimum sample position based
|
||||
% on the varience of constellation
|
||||
[seqRxDown,fd,samplePos] = suqareShapeFreqEst(seqRx,interp,fs,-25000,-21000,5);
|
||||
|
||||
% split [seqRxDown] into multiple groups, each group contains several symbols to
|
||||
% be correlated with PRBS7 and accumulated
|
||||
seqRxDownSplit = reshape(seqRxDown(1:dataLen/interp,:),chipLen*symNumPerAccum, ...
|
||||
accNum,channelNum);
|
||||
|
||||
seqRxAcc = zeros(chipLen,accNum,channelNum);
|
||||
desiredPnt = zeros(accNum,channelNum);
|
||||
ampEstSym = zeros(accNum,channelNum);
|
||||
angleEstSym = zeros(accNum,channelNum);
|
||||
|
||||
for i = 1:accNum
|
||||
for j = 1:channelNum
|
||||
% correlation & multi-symbol accumulation
|
||||
groupCorrAcc = sum(reshape(conv(flip(seqRxDownSplit(:,i,j)), ...
|
||||
PRBS7_polar,'same'),chipLen,symNumPerAccum),2)';
|
||||
seqRxAcc(:,i,j) = groupCorrAcc;
|
||||
% peak position
|
||||
desiredPnt(i,j) = groupCorrAcc(abs(groupCorrAcc)==max(abs(groupCorrAcc)));
|
||||
end
|
||||
end
|
||||
|
||||
for i = 1:channelNum
|
||||
ampEstSym(:,i) = abs(desiredPnt(:,i))./abs(desiredPnt(:,1));
|
||||
angleEstSym(:,i) = mod((angle(desiredPnt(:,i))-angle(desiredPnt(:,1)))/pi*180,360);
|
||||
end
|
||||
|
||||
ampEstSymMax(dataFileIndex,:) = max(ampEstSym);
|
||||
ampEstSymMin(dataFileIndex,:) = min(ampEstSym);
|
||||
ampEstSymAvg(dataFileIndex,:) = mean(ampEstSym);
|
||||
angleEstSymMax(dataFileIndex,:) = max(angleEstSym);
|
||||
angleEstSymMin(dataFileIndex,:) = min(angleEstSym);
|
||||
angleEstSymAvg(dataFileIndex,:) = mean(angleEstSym);
|
||||
|
||||
ampEstSymMaxList(dataFileIndex+1,2:end) = string(ampEstSymMax(dataFileIndex,:));
|
||||
ampEstSymMinList(dataFileIndex+1,2:end) = string(ampEstSymMin(dataFileIndex,:));
|
||||
ampEstSymAvgList(dataFileIndex+1,2:end) = string(ampEstSymAvg(dataFileIndex,:));
|
||||
angleEstSymMaxList(dataFileIndex+1,2:end) = string(angleEstSymMax(dataFileIndex,:));
|
||||
angleEstSymMinList(dataFileIndex+1,2:end) = string(angleEstSymMin(dataFileIndex,:));
|
||||
angleEstSymAvgList(dataFileIndex+1,2:end) = string(angleEstSymAvg(dataFileIndex,:));
|
||||
|
||||
end
|
||||
|
||||
|
||||
|
||||
%% figures
|
||||
% figure(1);
|
||||
%
|
||||
% subplot(121);
|
||||
% plot(ampEstSym);
|
||||
% legend({"ch1","ch2","ch3","ch4"});
|
||||
% title("Amplitude Estimation");
|
||||
% ylim([min(ampEstSym,[],'all')-0.2,max(ampEstSym,[],'all')+0.2]);
|
||||
% grid on; grid minor;
|
||||
%
|
||||
% subplot(122);
|
||||
% plot(angleEstSym);
|
||||
% legend({"ch1","ch2","ch3","ch4"});
|
||||
% title("Angle Estimation");
|
||||
% ylim([-10,370]);
|
||||
% grid on; grid minor;
|
||||
@@ -0,0 +1,50 @@
|
||||
function [dataOut, fdTarget, samplePosTarget] = suqareShapeFreqEst(dataIn, interp, fs, fmin, fmax, fd)
|
||||
%suqareShapeFreqEst - 利用星座图的集中程度在一定频率范围内使用频率步进估计方波成形信号的频偏
|
||||
%
|
||||
% data - input complex data, row vector
|
||||
% dataLen - data length
|
||||
% interp - interpolation rate
|
||||
% fs - sampling rate, in Herts
|
||||
% fmin - minimum estimation frequency, in Herts
|
||||
% fmax - maximum estimation frequency, in Herts
|
||||
% fd - estimation frequency step, in Herts
|
||||
|
||||
% dimension
|
||||
[dataLen,channelNum] = size(dataIn);
|
||||
|
||||
freqList = fmin:fd:fmax;
|
||||
freqNum = length(freqList);
|
||||
varRecord = zeros(freqNum,interp);
|
||||
|
||||
dataOut = zeros(dataLen/interp,channelNum);
|
||||
fdTarget = zeros(channelNum,1);
|
||||
samplePosTarget = zeros(channelNum,1);
|
||||
|
||||
for channel = 1:channelNum
|
||||
|
||||
for freq = 1:freqNum
|
||||
|
||||
% carrier
|
||||
cxr = exp(-1i*2*pi*freqList(freq)/fs*(0:dataLen-1)');
|
||||
|
||||
% apply frequency shift onto input data
|
||||
seqRx = dataIn(:,channel).*cxr;
|
||||
|
||||
for samplePos = 0:interp-1
|
||||
seqRxDown = downsample(seqRx,interp,samplePos); % 下采样
|
||||
seqRxDownQuaterOne = abs(real(seqRxDown)) + 1i*abs(imag(seqRxDown)); % 集中到第一象限
|
||||
varRecord(freq,samplePos+1) = var(seqRxDownQuaterOne);
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
[fdIndex, samplePosIndex] = find(varRecord==min(min(varRecord)));
|
||||
fdTarget(channel) = freqList(fdIndex);
|
||||
samplePosTarget(channel) = samplePosIndex-1;
|
||||
|
||||
cxrTarget = exp(-1i*2*pi*fdTarget(channel)/fs*(0:dataLen-1)');
|
||||
seqRxTarget = dataIn(:,channel).*cxrTarget;
|
||||
dataOut(:,channel) = downsample(seqRxTarget,interp,samplePosTarget(channel));
|
||||
end
|
||||
|
||||
end
|
||||
@@ -0,0 +1,11 @@
|
||||
# 数据说明
|
||||
|
||||
1. iladata_ad9361_pure_noise.csv: 调零板 AD9361 单板噪声。
|
||||
|
||||
2. iladata_ad9361_ant_noise.csv: 调零板射频接收噪声。
|
||||
|
||||
3. iladata_ad9361_pure_noise_A-B.csv: 调零板 AD9361 单板噪声，第 A 次上电过程中第 B 次采集结果。
|
||||
|
||||
> 1~3 AD9361 配置均为 48Msps，BW 40MHz，外部本振，使用 AD9516-3 的 VCO 分频时钟。
|
||||
|
||||
4. iladata_814_1t2r_48msps_bwxxm_xxx_lo_A-B.csv：调零板 AD9361 单板噪声，48Msps，BW xxMHz，ext_lo 表示外部本振，int_lo 表示内部本振，第 A 次上电过程中第 B 次采集结果。
|
||||
+3
-1
@@ -53,7 +53,8 @@ probe_out0,
|
||||
probe_out1,
|
||||
probe_out2,
|
||||
probe_out3,
|
||||
probe_out4
|
||||
probe_out4,
|
||||
probe_out5
|
||||
);
|
||||
|
||||
input clk;
|
||||
@@ -63,6 +64,7 @@ output reg [0 : 0] probe_out1 = 'h0 ;
|
||||
output reg [31 : 0] probe_out2 = 'h00000000 ;
|
||||
output reg [1 : 0] probe_out3 = 'h3 ;
|
||||
output reg [3 : 0] probe_out4 = 'h0 ;
|
||||
output reg [0 : 0] probe_out5 = 'h0 ;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
+2
-1
@@ -60,7 +60,8 @@ vio_manual_ctrl your_instance_name (
|
||||
.probe_out1(probe_out1), // output wire [0 : 0] probe_out1
|
||||
.probe_out2(probe_out2), // output wire [31 : 0] probe_out2
|
||||
.probe_out3(probe_out3), // output wire [1 : 0] probe_out3
|
||||
.probe_out4(probe_out4) // output wire [3 : 0] probe_out4
|
||||
.probe_out4(probe_out4), // output wire [3 : 0] probe_out4
|
||||
.probe_out5(probe_out5) // output wire [0 : 0] probe_out5
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
|
||||
+4
-2
@@ -59,7 +59,8 @@ COMPONENT vio_manual_ctrl
|
||||
probe_out1 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe_out2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe_out3 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
probe_out4 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
|
||||
probe_out4 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
probe_out5 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
@@ -75,7 +76,8 @@ your_instance_name : vio_manual_ctrl
|
||||
probe_out1 => probe_out1,
|
||||
probe_out2 => probe_out2,
|
||||
probe_out3 => probe_out3,
|
||||
probe_out4 => probe_out4
|
||||
probe_out4 => probe_out4,
|
||||
probe_out5 => probe_out5
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
+4
-3
@@ -1,7 +1,7 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Wed Apr 19 12:03:53 2023
|
||||
// Date : Sun Apr 23 16:19:11 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v
|
||||
@@ -15,12 +15,13 @@
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
|
||||
module vio_manual_ctrl(clk, probe_out0, probe_out1, probe_out2,
|
||||
probe_out3, probe_out4)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]" */;
|
||||
probe_out3, probe_out4, probe_out5)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0],probe_out5[0:0]" */;
|
||||
input clk;
|
||||
output [1:0]probe_out0;
|
||||
output [0:0]probe_out1;
|
||||
output [31:0]probe_out2;
|
||||
output [1:0]probe_out3;
|
||||
output [3:0]probe_out4;
|
||||
output [0:0]probe_out5;
|
||||
endmodule
|
||||
|
||||
+4
-3
@@ -1,7 +1,7 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Wed Apr 19 12:03:53 2023
|
||||
-- Date : Sun Apr 23 16:19:11 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl
|
||||
@@ -19,7 +19,8 @@ entity vio_manual_ctrl is
|
||||
probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_out3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 )
|
||||
probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
probe_out5 : out STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
|
||||
end vio_manual_ctrl;
|
||||
@@ -28,7 +29,7 @@ architecture stub of vio_manual_ctrl is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]";
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[1:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0],probe_out5[0:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
|
||||
begin
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 19 12:03:35 CST 2023
|
||||
# Generated by export_simulation on Sun Apr 23 16:18:53 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-1
@@ -8,7 +8,6 @@ vmap xil_defaultlib activehdl/xil_defaultlib
|
||||
vmap xpm activehdl/xpm
|
||||
|
||||
vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/vio_manual_ctrl/hdl/verilog" "+incdir+../../../ip/vio_manual_ctrl/hdl" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -93 \
|
||||
@@ -17,6 +16,7 @@ vcom -work xpm -93 \
|
||||
vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/vio_manual_ctrl/hdl/verilog" "+incdir+../../../ip/vio_manual_ctrl/hdl" \
|
||||
"../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v" \
|
||||
|
||||
|
||||
vlog -work xil_defaultlib \
|
||||
"glbl.v"
|
||||
|
||||
|
||||
-1
@@ -1,4 +1,3 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
|
||||
vio_manual_ctrl.v,verilog,xil_defaultlib,../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Wed Apr 19 12:03:35 CST 2023
|
||||
# Generated by Vivado on Sun Apr 23 16:18:53 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 19 12:03:35 CST 2023
|
||||
# Generated by export_simulation on Sun Apr 23 16:18:53 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
-1
@@ -1,4 +1,3 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
|
||||
vio_manual_ctrl.v,verilog,xil_defaultlib,../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
|
||||
|
||||
-1
@@ -1,5 +1,4 @@
|
||||
-makelib ies_lib/xil_defaultlib -sv \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
-endlib
|
||||
-makelib ies_lib/xpm \
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Wed Apr 19 12:03:35 CST 2023
|
||||
# Generated by Vivado on Sun Apr 23 16:18:53 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 19 12:03:35 CST 2023
|
||||
# Generated by export_simulation on Sun Apr 23 16:18:53 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Wed Apr 19 12:03:35 CST 2023
|
||||
# Generated by Vivado on Sun Apr 23 16:18:53 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 19 12:03:35 CST 2023
|
||||
# Generated by export_simulation on Sun Apr 23 16:18:53 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-1
@@ -8,7 +8,6 @@ vmap xil_defaultlib questa_lib/msim/xil_defaultlib
|
||||
vmap xpm questa_lib/msim/xpm
|
||||
|
||||
vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/vio_manual_ctrl/hdl/verilog" "+incdir+../../../ip/vio_manual_ctrl/hdl" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -64 -93 \
|
||||
@@ -17,6 +16,7 @@ vcom -work xpm -64 -93 \
|
||||
vlog -work xil_defaultlib -64 "+incdir+../../../ip/vio_manual_ctrl/hdl/verilog" "+incdir+../../../ip/vio_manual_ctrl/hdl" \
|
||||
"../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v" \
|
||||
|
||||
|
||||
vlog -work xil_defaultlib \
|
||||
"glbl.v"
|
||||
|
||||
|
||||
-1
@@ -1,4 +1,3 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
|
||||
vio_manual_ctrl.v,verilog,xil_defaultlib,../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Wed Apr 19 12:03:35 CST 2023
|
||||
# Generated by Vivado on Sun Apr 23 16:18:53 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 19 12:03:35 CST 2023
|
||||
# Generated by export_simulation on Sun Apr 23 16:18:53 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-1
@@ -8,7 +8,6 @@ vmap xil_defaultlib riviera/xil_defaultlib
|
||||
vmap xpm riviera/xpm
|
||||
|
||||
vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/vio_manual_ctrl/hdl/verilog" "+incdir+../../../ip/vio_manual_ctrl/hdl" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -93 \
|
||||
@@ -17,6 +16,7 @@ vcom -work xpm -93 \
|
||||
vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/vio_manual_ctrl/hdl/verilog" "+incdir+../../../ip/vio_manual_ctrl/hdl" \
|
||||
"../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v" \
|
||||
|
||||
|
||||
vlog -work xil_defaultlib \
|
||||
"glbl.v"
|
||||
|
||||
|
||||
-1
@@ -1,4 +1,3 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
|
||||
vio_manual_ctrl.v,verilog,xil_defaultlib,../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl"
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Wed Apr 19 12:03:35 CST 2023
|
||||
# Generated by Vivado on Sun Apr 23 16:18:53 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 19 12:03:35 CST 2023
|
||||
# Generated by export_simulation on Sun Apr 23 16:18:53 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Wed Apr 19 12:03:35 CST 2023
|
||||
# Generated by Vivado on Sun Apr 23 16:18:53 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 19 12:03:35 CST 2023
|
||||
# Generated by export_simulation on Sun Apr 23 16:18:53 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user