add duifei_online_acq_par

完成对飞并行捕获程序的编写,仿真和测试,能够正常采集数据
2023-05-09 20:52:09 +08:00
parent 2d4650a3b6
commit 866b718eb3
1097 changed files with 236686 additions and 0 deletions
@@ -0,0 +1,93 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 05/06/2023 03:39:20 PM
+// Design Name:
+// Module Name: tb_freq_comp
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module tb_freq_comp;
+
+reg clk = 1'b1;
+reg rst = 1'b1;
+reg freq_comp_start = 'b0;
+wire freq_comp_busy;
+
+wire [11:0] tx_data_i, tx_data_q;
+wire [31:0] freq_target;
+wire freq_target_valid;
+
+initial begin
+    #102;
+    rst = 1'b0;
+    #1000;
+    freq_comp_start = ~freq_comp_start;
+    #1000;
+    wait (freq_comp_busy == 0);
+    #1000;
+    freq_comp_start = ~freq_comp_start;
+end
+
+always #10 clk = ~clk;
+
+tx_qpsk u_tx_qpsk
+(
+    .clk            (clk            ),
+    .rst            (rst            ),
+
+    .tx_data_i      (tx_data_i      ),
+    .tx_data_q      (tx_data_q      ),
+    // debug ports
+    .waveform_sel   (2'd1           ),
+    .sweep_on       (1'b0           ),
+    .freq_set       ('b0            ),
+    .iq_sel         (2'b11          ),
+    .bb_rshift      (4'd0           )
+);
+
+freq_comp #(
+    .FREQ_WORD_LOWER(-1024 ),
+    .FREQ_WORD_UPPER(1023  ),
+    .FREQ_WORD_STEP (1024  )
+)u_freq_comp
+(
+    .clk                (clk                ),
+    .rst                (rst                ),
+
+    .freq_comp_start    (freq_comp_start    ),
+    .freq_comp_busy     (freq_comp_busy     ),
+
+    .rx_data_valid      (~rst               ),
+    .rx_ch1_i           (tx_data_i          ),
+    .rx_ch1_q           (tx_data_q          ),
+    .rx_ch2_i           (tx_data_q          ),
+    .rx_ch2_q           (tx_data_i          ),
+    .rx_ch3_i           (tx_data_i          ),
+    .rx_ch3_q           (tx_data_i          ),
+    .rx_ch4_i           (tx_data_q          ),
+    .rx_ch4_q           (tx_data_q          ),
+
+    .dmf_num_per_ch     (2                  ),
+
+    .freq_manual        (327680             ),
+    .freq_manual_en     (1'b0               ),
+
+    .freq_target        (freq_target        ),
+    .freq_target_valid  (freq_target_valid  )
+);
+
+endmodule
@@ -0,0 +1,128 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 04/25/2023 06:48:44 PM
+// Design Name:
+// Module Name: tb_rx_dmf
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module tb_rx_dmf;
+
+// length of pseudorandom bit sequence, need to be a power of 2
+localparam PRBS_LEN        = 128;
+// interpolation of input signal, need to be a power of 2
+localparam INTERP_RATE     =   8;
+// signal processing interpolation, need to be a power of 2
+localparam PROCESS_INTERP  =   4;
+localparam PRBS_LEN_INTERP = PRBS_LEN*PROCESS_INTERP;
+// number of accumulated symbols, need to be a power of 2
+localparam ACC_SYM_NUM     =   4;
+
+localparam MAX_DMF_NUM     = 64;
+localparam DATA_I_WIDTH    = 12;
+localparam DATA_O_WIDTH    = 18;
+
+reg clk = 1'b1;
+reg rst = 1'b1;
+reg dmf_start = 'b0;
+wire dmf_busy;
+wire last_peak_valid;
+
+wire [11:0] tx_data_i, tx_data_q;
+
+reg [31:0] freq_set = 'b0;
+
+wire peak_valid                                 ;
+wire [DATA_O_WIDTH-1 : 0] peak_value_abs          ;
+wire [DATA_O_WIDTH-1 : 0] peak_value_i            ;
+wire [DATA_O_WIDTH-1 : 0] peak_value_q            ;
+wire [$clog2(PRBS_LEN_INTERP)-1 : 0] peak_index ;
+
+initial begin
+    #102;
+    rst = 1'b0;
+    #1000;
+    dmf_start = ~dmf_start;
+
+    wait (last_peak_valid == 1);
+    freq_set = -32'd2048;
+    #1000;
+    dmf_start = ~dmf_start;
+
+    wait (last_peak_valid == 1);
+    freq_set = 32'd1;
+    #1000;
+    dmf_start = ~dmf_start;
+
+    wait (last_peak_valid == 1);
+    freq_set = 32'd2048;
+    #1000;
+    dmf_start = ~dmf_start;
+
+    wait (last_peak_valid == 1);
+    freq_set = 32'd4096;
+    #1000;
+    dmf_start = ~dmf_start;
+
+    wait (last_peak_valid == 1);
+    freq_set = 32'd6144;
+    #1000;
+    dmf_start = ~dmf_start;
+end
+
+always #10 clk = ~clk;
+
+tx_qpsk u_tx_qpsk
+(
+    .clk            (clk            ),
+    .rst            (rst            ),
+
+    .tx_data_i      (tx_data_i      ),
+    .tx_data_q      (tx_data_q      ),
+    // debug ports
+    .waveform_sel   (2'd1           ),
+    .sweep_on       (1'b0           ),
+    .freq_set       (freq_set       ),
+    .iq_sel         (2'b11          ),
+    .bb_rshift      (4'd0           )
+);
+
+rx_dmf #(
+    .ACC_SYM_NUM    (ACC_SYM_NUM    )
+) u_rx_dmf
+(
+    .clk            (clk            ),
+    .rst            (rst            ),
+
+    .dmf_start      (dmf_start      ),
+    .dmf_busy       (dmf_busy       ),
+
+    .dmf_num        (2              ),
+
+    .din_valid      (~rst           ),
+    .din_real       (tx_data_i      ),
+    .din_imag       (tx_data_i      ),
+
+    .peak_valid     (peak_valid     ),
+    .last_peak_valid(last_peak_valid),
+    .peak_value_abs (peak_value_abs ),
+    .peak_value_i   (peak_value_i   ),
+    .peak_value_q   (peak_value_q   ),
+    .peak_index     (peak_index     )
+);
+
+endmodule