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remove lcmv from dl814_k7_online_acq; add phase comp to dl814_k7_cal_coarse

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josh
2023-05-21 17:15:49 +08:00
parent dcfe84872e
commit a476d6f42e
326 changed files with 1563 additions and 178251 deletions
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projects/dl814_k7/dl814_k7_cal_coarse/rtl/rx_pre_process/phase_comp.v
+134
View File
@@ -0,0 +1,134 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05/17/2023 03:30:04 PM
// Design Name:
// Module Name: phase_comp
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module phase_comp
#(
parameter DATA_WIDTH = 12,
parameter CORDIC_WIDTH = 16,
parameter CHANNEL_NUM = 4
)
(
// clock & reset
input rst ,
input clk ,
// input data
input din_valid ,
input [CHANNEL_NUM*CORDIC_WIDTH-1:0] phase ,
input [CHANNEL_NUM*DATA_WIDTH-1:0] din_real ,
input [CHANNEL_NUM*DATA_WIDTH-1:0] din_imag ,
// output data
output dout_valid ,
output [CHANNEL_NUM*DATA_WIDTH-1:0] dout_real ,
output [CHANNEL_NUM*DATA_WIDTH-1:0] dout_imag
);
genvar m;
localparam AXIS_CORDIC_WIDTH = 8*((CORDIC_WIDTH-1)/8+1);
// prepare cordic input data
wire [AXIS_CORDIC_WIDTH-1:0] din_real_array [0:CHANNEL_NUM-1];
wire [AXIS_CORDIC_WIDTH-1:0] din_imag_array [0:CHANNEL_NUM-1];
wire [AXIS_CORDIC_WIDTH-1:0] phase_array [0:CHANNEL_NUM-1];
generate
for(m = 0; m < CHANNEL_NUM; m = m + 1) begin: array_convert
if (CORDIC_WIDTH > DATA_WIDTH) begin
// append zeros to fit cordic input with, sign-bit extension to fit 8 bit axis format
assign din_real_array[m] = {{(AXIS_CORDIC_WIDTH-CORDIC_WIDTH){din_real[(m+1)*DATA_WIDTH-1]}},din_real[m*DATA_WIDTH +: DATA_WIDTH],{(CORDIC_WIDTH-DATA_WIDTH){1'b0}}};
assign din_imag_array[m] = {{(AXIS_CORDIC_WIDTH-CORDIC_WIDTH){din_imag[(m+1)*DATA_WIDTH-1]}},din_imag[m*DATA_WIDTH +: DATA_WIDTH],{(CORDIC_WIDTH-DATA_WIDTH){1'b0}}};
end
else begin
// truncate msb
assign din_real_array[m] = din_real[(m+1)*DATA_WIDTH-1 -: AXIS_CORDIC_WIDTH];
assign din_imag_array[m] = din_imag[(m+1)*DATA_WIDTH-1 -: AXIS_CORDIC_WIDTH];
end
if (AXIS_CORDIC_WIDTH > CORDIC_WIDTH) begin
// sign-bit extension to fit 8 bit axis format
assign phase_array[m] = {{(AXIS_CORDIC_WIDTH-CORDIC_WIDTH){phase[(m+1)*CORDIC_WIDTH-1]}},phase[m*CORDIC_WIDTH +: CORDIC_WIDTH]};
end
else begin
// truncate msb
assign phase_array[m] = phase[(m+1)*CORDIC_WIDTH-1 -: AXIS_CORDIC_WIDTH];
end
end
endgenerate
// output data & cordic interface
wire [AXIS_CORDIC_WIDTH-1:0] rotate_real_array [0:CHANNEL_NUM-1];
wire [AXIS_CORDIC_WIDTH-1:0] rotate_imag_array [0:CHANNEL_NUM-1];
wire [DATA_WIDTH-1:0] dout_real_array [0:CHANNEL_NUM-1];
wire [DATA_WIDTH-1:0] dout_imag_array [0:CHANNEL_NUM-1];
generate
for(m = 0; m < CHANNEL_NUM; m = m + 1) begin: cordic
wire rotate_phase_valid;
wire [15:0] rotate_phase_data ;
wire rotate_cart_valid ;
wire [31:0] rotate_cart_data ;
wire rotate_dout_valid ;
wire [31:0] rotate_dout_data ;
assign rotate_phase_valid = din_valid;
assign rotate_phase_data = phase_array[m];
assign rotate_cart_valid = din_valid;
assign rotate_cart_data = {din_imag_array[m],din_real_array[m]};
assign {rotate_imag_array[m],rotate_real_array[m]} = rotate_dout_data;
if (DATA_WIDTH > AXIS_CORDIC_WIDTH) begin
// append zeros
assign dout_real_array[m] = {rotate_real_array[m],{(DATA_WIDTH-AXIS_CORDIC_WIDTH){1'b0}}};
assign dout_imag_array[m] = {rotate_imag_array[m],{(DATA_WIDTH-AXIS_CORDIC_WIDTH){1'b0}}};
end
else begin
// truncate msb
assign dout_real_array[m] = rotate_real_array[m][AXIS_CORDIC_WIDTH-1 -: DATA_WIDTH];
assign dout_imag_array[m] = rotate_imag_array[m][AXIS_CORDIC_WIDTH-1 -: DATA_WIDTH];
end
assign dout_real[m*DATA_WIDTH +: DATA_WIDTH] = dout_real_array[m];
assign dout_imag[m*DATA_WIDTH +: DATA_WIDTH] = dout_imag_array[m];
rotate_16b u_rotate_16b
(
.aclk (clk ), // input wire aclk
.s_axis_phase_tvalid (rotate_phase_valid ), // input wire s_axis_phase_tvalid
.s_axis_phase_tdata (rotate_phase_data ), // input wire [15 : 0] s_axis_phase_tdata
.s_axis_cartesian_tvalid(rotate_cart_valid ), // input wire s_axis_cartesian_tvalid
.s_axis_cartesian_tdata (rotate_cart_data ), // input wire [31 : 0] s_axis_cartesian_tdata
.m_axis_dout_tvalid (rotate_dout_valid ), // output wire m_axis_dout_tvalid
.m_axis_dout_tdata (rotate_dout_data ) // output wire [31 : 0] m_axis_dout_tdata
);
end
endgenerate
assign dout_valid = cordic[0].rotate_dout_valid;
endmodule
projects/dl814_k7/dl814_k7_cal_coarse/rtl/rx_pre_process/rx_pre_process.v
+53 -5
View File
@@ -48,6 +48,7 @@ module rx_pre_process
parameter STABLE_CNT_MOD = 48 ,
parameter ADC_DATA_WIDTH = 12 ,
parameter CHANNEL_NUM = 4 ,
parameter PHASE_WIDTH = 16 ,
parameter SNAPSHOT_NUM = 256,
parameter PS_PL_WIDTH = 32 ,
parameter WEIGHT_TRUNC_WIDTH = 16 ,
@@ -73,6 +74,11 @@ module rx_pre_process
input [ADC_DATA_WIDTH-1:0] rx_ch3_q ,
input [ADC_DATA_WIDTH-1:0] rx_ch4_i ,
input [ADC_DATA_WIDTH-1:0] rx_ch4_q ,
// input channel phase
input [PHASE_WIDTH-1:0] phase_ch1 ,
input [PHASE_WIDTH-1:0] phase_ch2 ,
input [PHASE_WIDTH-1:0] phase_ch3 ,
input [PHASE_WIDTH-1:0] phase_ch4 ,
// ad9361 calibration interface
input ad9361_1_cal_start ,
@@ -142,6 +148,48 @@ ad9361_phase_cal_coarse u_ad9361_phase_cal
.rx_cal_ch4_q (rx_cal_ch4_q ) // output [ADC_DATA_WIDTH-1:0] rx_cal_ch4_q
);
////////////////////////////////////////////////////////////////////////////////
////////////////////////////// Phase Compensation //////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// input data
wire phase_comp_din_valid;
wire [CHANNEL_NUM*PHASE_WIDTH-1 : 0] phase_comp_phase;
wire [CHANNEL_NUM*ADC_DATA_WIDTH-1 : 0] phase_comp_din_real;
wire [CHANNEL_NUM*ADC_DATA_WIDTH-1 : 0] phase_comp_din_imag;
assign phase_comp_din_valid = ad9361_cal_valid;
assign phase_comp_phase = {phase_ch4, phase_ch3, phase_ch2, phase_ch1};
assign phase_comp_din_real = {rx_cal_ch4_i, rx_cal_ch3_i, rx_cal_ch2_i, rx_cal_ch1_i};
assign phase_comp_din_imag = {rx_cal_ch4_q, rx_cal_ch3_q, rx_cal_ch2_q, rx_cal_ch1_q};
// output data
wire phase_comp_dout_valid;
wire [CHANNEL_NUM*ADC_DATA_WIDTH-1:0] phase_comp_dout_real;
wire [CHANNEL_NUM*ADC_DATA_WIDTH-1:0] phase_comp_dout_imag;
phase_comp #(
.DATA_WIDTH (ADC_DATA_WIDTH ),
.CORDIC_WIDTH (PHASE_WIDTH ),
.CHANNEL_NUM (CHANNEL_NUM )
) u_phase_comp
(
// clock & reset
.rst (sys_clk ),
.clk (sys_rst ),
// input data
.din_valid (phase_comp_din_valid ),
.phase (phase_comp_phase ),
.din_real (phase_comp_din_real ),
.din_imag (phase_comp_din_imag ),
// output data
.dout_valid (phase_comp_dout_valid ),
.dout_real (phase_comp_dout_real ),
.dout_imag (phase_comp_dout_imag )
);
////////////////////////////////////////////////////////////////////////////////
//////////////////////// Autocorrelation State Machine /////////////////////////
////////////////////////////////////////////////////////////////////////////////
@@ -256,8 +304,8 @@ wire [CHANNEL_NUM*ADC_DATA_WIDTH-1 : 0] acorr_din_real;
wire [CHANNEL_NUM*ADC_DATA_WIDTH-1 : 0] acorr_din_imag;
assign acorr_din_valid = snapshot_valid;
assign acorr_din_real = {rx_cal_ch4_i, rx_cal_ch3_i, rx_cal_ch2_i, rx_cal_ch1_i};
assign acorr_din_imag = {rx_cal_ch4_q, rx_cal_ch3_q, rx_cal_ch2_q, rx_cal_ch1_q};
assign acorr_din_real = phase_comp_din_real;
assign acorr_din_imag = phase_comp_din_imag;
// output data
wire acorr_dout_valid;
@@ -435,9 +483,9 @@ wire filter_adc_valid;
wire [CHANNEL_NUM*ADC_DATA_WIDTH-1 : 0] filter_adc_real;
wire [CHANNEL_NUM*ADC_DATA_WIDTH-1 : 0] filter_adc_imag;
assign filter_adc_valid = ad9361_cal_valid;
assign filter_adc_real = {rx_cal_ch4_i, rx_cal_ch3_i, rx_cal_ch2_i, rx_cal_ch1_i};
assign filter_adc_imag = {rx_cal_ch4_q, rx_cal_ch3_q, rx_cal_ch2_q, rx_cal_ch1_q};
assign filter_adc_valid = phase_comp_dout_valid;
assign filter_adc_real = phase_comp_dout_real;
assign filter_adc_imag = phase_comp_dout_imag;
// output data
wire filter_dout_valid;
projects/dl814_k7/dl814_k7_cal_coarse/rtl/system_top.v
+49 -12
View File
@@ -566,7 +566,11 @@ wire [31:0] freq_set ;
wire [ 1:0] iq_sel ;
wire [ 3:0] bb_rshift ;
tx_qpsk u_tx_qpsk
tx_qpsk #(
.BIT_DATA (1024'b0000000100100010000011001001101000010010101000011110101110101101101100000000110000011011001100001010110101110001101111110001000111100111101101101000000010100001011010101000111110111100100101100000100110010001010001101101110000001111000111011111110010000110001011011101000011010101100111100101101100100000100010010011000000101100010100111011001110001011111101010001011101101011000011001101101010000011101001111010011010100100111000001111100111001101111010001010101101111100001001110100011101011111011010010000100001010010101100011100111111101100001000110100111001001111000011011101100011000111101111101001001010000001101000110010111010010110100010001011001101001010010001100001110110111100000101110010101110011101110111001100111010101110111101100101000100110110001000011100101111100101001100110010101010011111100110001101011110011010110100110001001011100001011110101010101111111101000001010100101111000101011110111010100110111001000111000111111111100000001110000111111011100010011111000110011111010110010110010010010000000001),
.BIT_DATA_LEN (1024),
.CLK_FREQ (48000000)
) u_tx_qpsk
(
.clk (sys_clk ), // input clk
.rst (sys_rst ), // input rst
@@ -598,6 +602,11 @@ wire [11:0] rx_ch2_i_test, rx_ch2_q_test;
wire [11:0] rx_ch3_i_test, rx_ch3_q_test;
wire [11:0] rx_ch4_i_test, rx_ch4_q_test;
wire [15:0] phase_ch1;
wire [15:0] phase_ch2;
wire [15:0] phase_ch3;
wire [15:0] phase_ch4;
wire rx_data_valid;
wire [29:0] rx_data_i, rx_data_q;
@@ -698,6 +707,11 @@ rx_pre_process #(
.rx_ch3_q (rx_ch3_q ),
.rx_ch4_i (rx_ch4_i ),
.rx_ch4_q (rx_ch4_q ),
// input channel phase
.phase_ch1 (phase_ch1 ),
.phase_ch2 (phase_ch2 ),
.phase_ch3 (phase_ch3 ),
.phase_ch4 (phase_ch4 ),
// ad9361 calibration interface
.ad9361_1_cal_start (ad9361_1_cal_start ),
.ad9361_1_cal_done (ad9361_1_cal_done ),
@@ -716,6 +730,21 @@ rx_pre_process #(
.rx_data_q (rx_data_q ) // sync to [sys_clk]
);
(*dont_touch = "true"*) wire [11:0] rx_rot_ch1_i, rx_rot_ch1_q;
(*dont_touch = "true"*) wire [11:0] rx_rot_ch2_i, rx_rot_ch2_q;
(*dont_touch = "true"*) wire [11:0] rx_rot_ch3_i, rx_rot_ch3_q;
(*dont_touch = "true"*) wire [11:0] rx_rot_ch4_i, rx_rot_ch4_q;
assign rx_rot_ch1_i = u_rx_pre_process.phase_comp_dout_real[11: 0];
assign rx_rot_ch2_i = u_rx_pre_process.phase_comp_dout_real[23:12];
assign rx_rot_ch3_i = u_rx_pre_process.phase_comp_dout_real[35:24];
assign rx_rot_ch4_i = u_rx_pre_process.phase_comp_dout_real[47:36];
assign rx_rot_ch1_q = u_rx_pre_process.phase_comp_dout_imag[11: 0];
assign rx_rot_ch2_q = u_rx_pre_process.phase_comp_dout_imag[23:12];
assign rx_rot_ch3_q = u_rx_pre_process.phase_comp_dout_imag[35:24];
assign rx_rot_ch4_q = u_rx_pre_process.phase_comp_dout_imag[47:36];
// temporary test cases
rx_pre_test u_rx_pre_test
(
@@ -888,17 +917,17 @@ ila_2x12x131072 u_ila_tx
ila_8x12_2x30_131072 u_ila_rx
(
.clk (sys_clk ), // input wire clk
.probe0 (u_rx_pre_process.rx_cal_ch1_i ), // input wire [11:0] probe0
.probe1 (u_rx_pre_process.rx_cal_ch1_q ), // input wire [11:0] probe1
.probe2 (u_rx_pre_process.rx_cal_ch2_i ), // input wire [11:0] probe2
.probe3 (u_rx_pre_process.rx_cal_ch2_q ), // input wire [11:0] probe3
.probe4 (u_rx_pre_process.rx_cal_ch3_i ), // input wire [11:0] probe4
.probe5 (u_rx_pre_process.rx_cal_ch3_q ), // input wire [11:0] probe5
.probe6 (u_rx_pre_process.rx_cal_ch4_i ), // input wire [11:0] probe6
.probe7 (u_rx_pre_process.rx_cal_ch4_q ), // input wire [11:0] probe7
.probe8 (rx_data_i ), // input wire [29:0] probe8
.probe9 (rx_data_q ) // input wire [29:0] probe9
.clk (sys_clk ), // input wire clk
.probe0 (rx_rot_ch1_i ), // input wire [11:0] probe0
.probe1 (rx_rot_ch1_q ), // input wire [11:0] probe1
.probe2 (rx_rot_ch2_i ), // input wire [11:0] probe2
.probe3 (rx_rot_ch2_q ), // input wire [11:0] probe3
.probe4 (rx_rot_ch3_i ), // input wire [11:0] probe4
.probe5 (rx_rot_ch3_q ), // input wire [11:0] probe5
.probe6 (rx_rot_ch4_i ), // input wire [11:0] probe6
.probe7 (rx_rot_ch4_q ), // input wire [11:0] probe7
.probe8 (rx_data_i ), // input wire [29:0] probe8
.probe9 (rx_data_q ) // input wire [29:0] probe9
);
ila_cal u_ila_cal
@@ -970,4 +999,12 @@ vio_hop u_vio_hop
.probe_out1 (hop_trigger_en ) // output wire [0 : 0] probe_out2
);
vio_phase_comp u_vio_phase_comp
(
.clk (sys_clk ), // input wire clk
.probe_out0 (phase_ch1 ), // output wire [15 : 0] probe_out0
.probe_out1 (phase_ch2 ), // output wire [15 : 0] probe_out1
.probe_out2 (phase_ch3 ), // output wire [15 : 0] probe_out2
.probe_out3 (phase_ch4 ) // output wire [15 : 0] probe_out3
);
endmodule