add new dl814 dj control

projects/dl814_dj/dl814_dj_new_48m/.gitignore

@@ -0,0 +1,131 @@
+################################################################################
+########################### Single Project Specific ############################
+################################################################################
+
+# ------------------------------------------------------------------------------
+# ------------------------------ Vivado Specific -------------------------------
+# ------------------------------------------------------------------------------
+
+# exclude everything in project directory
+project/**
+
+# include hardware manager projects and sources
+#   1. include `.hw` directory
+#   2. include everything in `.hw` directory
+!project/*.hw/
+!project/*.hw/**
+
+# include design run results
+#   1. include `*.runs` directory
+#   2. exclude everything in `.runs` directory
+#   3. include `.impl_*` directory
+#   4. include `*.bit` file in `.impl_*` directory
+#   5. include `*.ltx` file in `.impl_*` directory
+!/project/*.runs/
+/project/*.runs/**
+!/project/*.runs/impl_*/
+!/project/*.runs/impl_*/*.bit
+!/project/*.runs/impl_*/*.ltx
+
+# ------------------------------------------------------------------------------
+# -------------------------------- SDK Specific --------------------------------
+# ------------------------------------------------------------------------------
+
+# include sdk directory and everything in it
+!/project/*.sdk/
+!/project/*.sdk/**
+/project/*.sdk/**.log
+
+# exclude some obscure hidden SDK folders
+/project/*.sdk/.metadata/
+/project/*.sdk/.sdk/
+/project/*.sdk/RemoteSystemsTempFiles/
+/project/*.sdk/webtalk/
+
+# hw_platform: exclude the entire hw_platform folder, as everything can be
+# generated from the .hdf file. Make sure to include the bitstream in the .hdf
+# file when exporting from Vivado!
+/project/*.sdk/*_hw_platform_*/
+
+# BSP: only keep `.cproject`, `.project`, `.sdkproject`, `.system.mss` and
+# Makefile, ps lib files are regenerated automatically
+/project/*.sdk/*_bsp/*
+!/project/*.sdk/*_bsp/*.cproject
+!/project/*.sdk/*_bsp/*.project
+!/project/*.sdk/*_bsp/*.sdkproject
+!/project/*.sdk/*_bsp/system.mss
+!/project/*.sdk/*_bsp/Makefile
+
+# Application: ignored file patterns, exclude Debug & Release folders
+/project/*.sdk/**/*.o
+/project/*.sdk/**/*.d
+/project/*.sdk/**/*.a
+/project/*.sdk/*/Debug/
+/project/*.sdk/*/Release/
+
+
+################################################################################
+# ############################ Multi Project Specific ############################
+# ################################################################################
+
+# # ------------------------------------------------------------------------------
+# # ------------------------------ Vivado Specific -------------------------------
+# # ------------------------------------------------------------------------------
+
+# # exclude everything in project directory expect for top level directory
+# project/**
+# !/project/*/
+
+# # include hardware manager projects and sources
+# #   1. include `.hw` directory
+# #   2. include everything in `.hw` directory
+# !project/*/*.hw/
+# !project/*/*.hw/**
+
+# # include design run results
+# #   1. include `*.runs` directory
+# #   2. exclude everything in `.runs` directory
+# #   3. include `.impl_*` directory
+# #   4. include `*.bit` file in `.impl_*` directory
+# #   5. include `*.ltx` file in `.impl_*` directory
+# !/project/*/*.runs/
+# /project/*/*.runs/**
+# !/project/*/*.runs/impl_*/
+# !/project/*/*.runs/impl_*/*.bit
+# !/project/*/*.runs/impl_*/*.ltx
+
+# # ------------------------------------------------------------------------------
+# # -------------------------------- SDK Specific --------------------------------
+# # ------------------------------------------------------------------------------
+
+# # include sdk directory and everything in it
+# !/project/*/*.sdk/
+# !/project/*/*.sdk/**
+# /project/*/*.sdk/**.log
+
+# # exclude some obscure hidden SDK folders
+# /project/*/*.sdk/.metadata/
+# /project/*/*.sdk/.sdk/
+# /project/*/*.sdk/RemoteSystemsTempFiles/
+# /project/*/*.sdk/webtalk/
+
+# # hw_platform: exclude the entire hw_platform folder, as everything can be
+# # generated from the .hdf file. Make sure to include the bitstream in the .hdf
+# # file when exporting from Vivado!
+# /project/*/*.sdk/*_hw_platform_*/
+
+# # BSP: only keep `.cproject`, `.project`, `.sdkproject`, `.system.mss` and
+# # Makefile, ps lib files are regenerated automatically
+# /project/*/*.sdk/*_bsp/*
+# !/project/*/*.sdk/*_bsp/*.cproject
+# !/project/*/*.sdk/*_bsp/*.project
+# !/project/*/*.sdk/*_bsp/*.sdkproject
+# !/project/*/*.sdk/*_bsp/system.mss
+# !/project/*/*.sdk/*_bsp/Makefile
+
+# # Application: ignored file patterns, exclude Debug & Release folders
+# /project/*/*.sdk/**/*.o
+# /project/*/*.sdk/**/*.d
+# /project/*/*.sdk/**/*.a
+# /project/*/*.sdk/*/Debug/
+# /project/*/*.sdk/*/Release/

projects/dl814_dj/dl814_dj_new_48m/constraints/z7100_ad9528_ad9371.xdc

@@ -0,0 +1,64 @@
+# 2zynq0745_3ad9371 (xc7z100 version)
+
+## Timing Assertions Section
+create_clock -period 8.000 [get_ports refclk_p]
+create_clock -period 80.000 [get_ports clk_12M]
+
+## Physical Constraints Section
+
+# Clocks and Resets
+set_property  -dict  {PACKAGE_PIN AE22  IOSTANDARD LVDS_25 }  [get_ports sysclk_p               ] ;# FPGA_LOGIC_CLK_IN_1P
+set_property  -dict  {PACKAGE_PIN AD10                     }  [get_ports refclk_p               ] ;# FPGA_JESD204B_CLK_IN_1P
+set_property  -dict  {PACKAGE_PIN AJ20  IOSTANDARD LVDS_25 }  [get_ports sysref_p               ] ;# FPGA_SYSREF_IN_1P
+
+# AD9528 Interface
+set_property  -dict  {PACKAGE_PIN AE16  IOSTANDARD LVCMOS33}  [get_ports spi_csn_ad9528         ] ;# SPI_CS_9528
+set_property  -dict  {PACKAGE_PIN AE17  IOSTANDARD LVCMOS33}  [get_ports spi_clk_ad9528         ] ;# SPI_SCK_9528
+set_property  -dict  {PACKAGE_PIN AE18  IOSTANDARD LVCMOS33}  [get_ports spi_mosi_ad9528        ] ;# SPI_SDI_9528
+set_property  -dict  {PACKAGE_PIN AE15  IOSTANDARD LVCMOS33}  [get_ports spi_miso_ad9528        ] ;# SPI_SDO_9528
+set_property  -dict  {PACKAGE_PIN AH13  IOSTANDARD LVCMOS33}  [get_ports ad9528_reset_b         ] ;# AD9528_CLK_RESETB
+set_property  -dict  {PACKAGE_PIN AA17  IOSTANDARD LVCMOS33}  [get_ports ad9528_sysref_req      ] ;# AD9528_CLK_SYSREF_REQUEST
+
+# AD9371 Interface
+set_property  -dict  {PACKAGE_PIN AH23  IOSTANDARD LVDS_25 }  [get_ports rx_sync_p              ] ;# AD9371_1_SYNCINB0+
+set_property  -dict  {PACKAGE_PIN AJ25  IOSTANDARD LVDS_25 }  [get_ports tx_sync_p              ] ;# AD9371_1_SYNCOUTB0+
+set_property  -dict  {PACKAGE_PIN AH10                     }  [get_ports {rx_data_p[0]}         ] ;# AD9371_1_SERDOUT0+
+set_property  -dict  {PACKAGE_PIN AJ8                      }  [get_ports {rx_data_p[1]}         ] ;# AD9371_1_SERDOUT1+
+set_property  -dict  {PACKAGE_PIN AK10                     }  [get_ports {tx_data_p[0]}         ] ;# AD9371_1_SERDIN0+
+set_property  -dict  {PACKAGE_PIN AK6                      }  [get_ports {tx_data_p[1]}         ] ;# AD9371_1_SERDIN1+
+
+set_property  -dict  {PACKAGE_PIN AD24  IOSTANDARD LVCMOS25}  [get_ports spi_csn_ad9371         ] ;# AD9371_1_SPI_CS
+set_property  -dict  {PACKAGE_PIN AF23  IOSTANDARD LVCMOS25}  [get_ports spi_clk_ad9371         ] ;# AD9371_1_SPI_CLK
+set_property  -dict  {PACKAGE_PIN AG24  IOSTANDARD LVCMOS25}  [get_ports spi_mosi_ad9371        ] ;# AD9371_1_SPI_SDIN
+set_property  -dict  {PACKAGE_PIN AG25  IOSTANDARD LVCMOS25}  [get_ports spi_miso_ad9371        ] ;# AD9371_1_SPI_SDO
+
+set_property  -dict  {PACKAGE_PIN AK18  IOSTANDARD LVCMOS25}  [get_ports ad9371_test            ] ;# AD9371_1_TEST
+set_property  -dict  {PACKAGE_PIN AH19  IOSTANDARD LVCMOS25}  [get_ports ad9371_reset_b         ] ;# AD9371_1_RESETB
+set_property  -dict  {PACKAGE_PIN AK17  IOSTANDARD LVCMOS25}  [get_ports ad9371_gpint           ] ;# AD9371_1_GP_INTERRUPT
+
+# RF Control
+set_property  -dict  {PACKAGE_PIN V24   IOSTANDARD LVCMOS25}  [get_ports {freq_hop_words[0] }   ]
+set_property  -dict  {PACKAGE_PIN U24   IOSTANDARD LVCMOS25}  [get_ports {freq_hop_words[1] }   ]
+set_property  -dict  {PACKAGE_PIN V22   IOSTANDARD LVCMOS25}  [get_ports {freq_hop_words[2] }   ]
+set_property  -dict  {PACKAGE_PIN U22   IOSTANDARD LVCMOS25}  [get_ports {freq_hop_words[3] }   ]
+set_property  -dict  {PACKAGE_PIN R23   IOSTANDARD LVCMOS25}  [get_ports {freq_hop_words[4] }   ]
+set_property  -dict  {PACKAGE_PIN R22   IOSTANDARD LVCMOS25}  [get_ports {freq_hop_words[5] }   ]
+set_property  -dict  {PACKAGE_PIN T23   IOSTANDARD LVCMOS25}  [get_ports {freq_hop_words[6] }   ]
+set_property  -dict  {PACKAGE_PIN T22   IOSTANDARD LVCMOS25}  [get_ports {freq_hop_words[7] }   ]
+set_property  -dict  {PACKAGE_PIN W28   IOSTANDARD LVCMOS25}  [get_ports {freq_hop_words[8] }   ]
+set_property  -dict  {PACKAGE_PIN V27   IOSTANDARD LVCMOS25}  [get_ports {freq_hop_words[9] }   ]
+set_property  -dict  {PACKAGE_PIN W30   IOSTANDARD LVCMOS25}  [get_ports {freq_hop_words[10]}   ]
+set_property  -dict  {PACKAGE_PIN W29   IOSTANDARD LVCMOS25}  [get_ports {freq_hop_words[11]}   ]
+
+set_property  -dict  {PACKAGE_PIN AH21  IOSTANDARD LVCMOS25}  [get_ports tx_gain                ]
+set_property  -dict  {PACKAGE_PIN AG21  IOSTANDARD LVCMOS25}  [get_ports rx_gain                ]
+set_property  -dict  {PACKAGE_PIN V21   IOSTANDARD LVCMOS25}  [get_ports clk_12M                ]
+set_property  -dict  {PACKAGE_PIN AF20  IOSTANDARD LVCMOS25}  [get_ports CS_rf                  ]
+set_property  -dict  {PACKAGE_PIN V28   IOSTANDARD LVCMOS25}  [get_ports tx_gain_on             ]
+set_property  -dict  {PACKAGE_PIN V29   IOSTANDARD LVCMOS25}  [get_ports rx_gain_on             ]
+set_property  -dict  {PACKAGE_PIN V23   IOSTANDARD LVCMOS25}  [get_ports hop_words_valid        ]
+set_property  -dict  {PACKAGE_PIN W24   IOSTANDARD LVCMOS25}  [get_ports freq_hop_switch        ]
+
+# Sync Signal
+set_property  -dict  {PACKAGE_PIN AD19  IOSTANDARD LVCMOS25}  [get_ports sync_signal_out        ] ;# Bank9, not used before
+set_property  -dict  {PACKAGE_PIN AD18  IOSTANDARD LVCMOS25}  [get_ports sync_gnd               ] ;# Bank9, not used before

projects/dl814_dj/dl814_dj_new_48m/ip/coe/freq_word.coe

@@ -0,0 +1,83 @@
+MEMORY_INITIALIZATION_RADIX = 10;
+MEMORY_INITIALIZATION_VECTOR =
+1624,
+1611,
+1598,
+1585,
+1572,
+1559,
+1546,
+1533,
+1520,
+1507,
+1494,
+1481,
+1468,
+1455,
+1442,
+1429,
+1416,
+1403,
+1390,
+1377,
+1364,
+1351,
+1338,
+1325,
+1312,
+1299,
+1286,
+1273,
+1260,
+1247,
+1234,
+1221,
+1208,
+1195,
+1182,
+1169,
+1156,
+1143,
+1130,
+1117,
+1104,
+1091,
+1078,
+1065,
+1052,
+1039,
+1026,
+1013,
+1000,
+987,
+974,
+961,
+948,
+935,
+922,
+909,
+896,
+883,
+870,
+857,
+844,
+831,
+818,
+805,
+792,
+779,
+766,
+753,
+740,
+727,
+714,
+701,
+688,
+675,
+662,
+649,
+636,
+623,
+610,
+597,
+584,

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/README.txt

@@ -0,0 +1 @@
+The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/fifo_48m_to_122p88m/fifo_48m_to_122p88m.veo

@@ -0,0 +1,75 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+// IP VLNV: xilinx.com:ip:fifo_generator:13.2
+// IP Revision: 4
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+fifo_48m_to_122p88m your_instance_name (
+  .wr_rst_busy(wr_rst_busy),      // output wire wr_rst_busy
+  .rd_rst_busy(rd_rst_busy),      // output wire rd_rst_busy
+  .m_aclk(m_aclk),                // input wire m_aclk
+  .s_aclk(s_aclk),                // input wire s_aclk
+  .s_aresetn(s_aresetn),          // input wire s_aresetn
+  .s_axis_tvalid(s_axis_tvalid),  // input wire s_axis_tvalid
+  .s_axis_tready(s_axis_tready),  // output wire s_axis_tready
+  .s_axis_tdata(s_axis_tdata),    // input wire [15 : 0] s_axis_tdata
+  .m_axis_tvalid(m_axis_tvalid),  // output wire m_axis_tvalid
+  .m_axis_tready(m_axis_tready),  // input wire m_axis_tready
+  .m_axis_tdata(m_axis_tdata)    // output wire [15 : 0] m_axis_tdata
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file fifo_48m_to_122p88m.v when simulating
+// the core, fifo_48m_to_122p88m. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/fifo_48m_to_122p88m/fifo_48m_to_122p88m.vho

@@ -0,0 +1,95 @@
+-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:fifo_generator:13.2
+-- IP Revision: 4
+
+-- The following code must appear in the VHDL architecture header.
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT fifo_48m_to_122p88m
+  PORT (
+    wr_rst_busy : OUT STD_LOGIC;
+    rd_rst_busy : OUT STD_LOGIC;
+    m_aclk : IN STD_LOGIC;
+    s_aclk : IN STD_LOGIC;
+    s_aresetn : IN STD_LOGIC;
+    s_axis_tvalid : IN STD_LOGIC;
+    s_axis_tready : OUT STD_LOGIC;
+    s_axis_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+    m_axis_tvalid : OUT STD_LOGIC;
+    m_axis_tready : IN STD_LOGIC;
+    m_axis_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+  );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : fifo_48m_to_122p88m
+  PORT MAP (
+    wr_rst_busy => wr_rst_busy,
+    rd_rst_busy => rd_rst_busy,
+    m_aclk => m_aclk,
+    s_aclk => s_aclk,
+    s_aresetn => s_aresetn,
+    s_axis_tvalid => s_axis_tvalid,
+    s_axis_tready => s_axis_tready,
+    s_axis_tdata => s_axis_tdata,
+    m_axis_tvalid => m_axis_tvalid,
+    m_axis_tready => m_axis_tready,
+    m_axis_tdata => m_axis_tdata
+  );
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+-- You must compile the wrapper file fifo_48m_to_122p88m.vhd when simulating
+-- the core, fifo_48m_to_122p88m. When compiling the wrapper file, be sure to
+-- reference the VHDL simulation library.
+

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/fifo_48m_to_122p88m/fifo_48m_to_122p88m_stub.v

@@ -0,0 +1,32 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
+// Date        : Tue Mar 21 16:19:06 2023
+// Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top fifo_48m_to_122p88m -prefix
+//               fifo_48m_to_122p88m_ fifo_48m_to_122p88m_stub.v
+// Design      : fifo_48m_to_122p88m
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z100ffg900-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "fifo_generator_v13_2_4,Vivado 2019.1.3" *)
+module fifo_48m_to_122p88m(wr_rst_busy, rd_rst_busy, m_aclk, s_aclk, 
+  s_aresetn, s_axis_tvalid, s_axis_tready, s_axis_tdata, m_axis_tvalid, m_axis_tready, 
+  m_axis_tdata)
+/* synthesis syn_black_box black_box_pad_pin="wr_rst_busy,rd_rst_busy,m_aclk,s_aclk,s_aresetn,s_axis_tvalid,s_axis_tready,s_axis_tdata[15:0],m_axis_tvalid,m_axis_tready,m_axis_tdata[15:0]" */;
+  output wr_rst_busy;
+  output rd_rst_busy;
+  input m_aclk;
+  input s_aclk;
+  input s_aresetn;
+  input s_axis_tvalid;
+  output s_axis_tready;
+  input [15:0]s_axis_tdata;
+  output m_axis_tvalid;
+  input m_axis_tready;
+  output [15:0]m_axis_tdata;
+endmodule

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/fifo_48m_to_122p88m/fifo_48m_to_122p88m_stub.vhdl

@@ -0,0 +1,40 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
+-- Date        : Tue Mar 21 16:19:06 2023
+-- Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+-- Command     : write_vhdl -force -mode synth_stub -rename_top fifo_48m_to_122p88m -prefix
+--               fifo_48m_to_122p88m_ fifo_48m_to_122p88m_stub.vhdl
+-- Design      : fifo_48m_to_122p88m
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7z100ffg900-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity fifo_48m_to_122p88m is
+  Port ( 
+    wr_rst_busy : out STD_LOGIC;
+    rd_rst_busy : out STD_LOGIC;
+    m_aclk : in STD_LOGIC;
+    s_aclk : in STD_LOGIC;
+    s_aresetn : in STD_LOGIC;
+    s_axis_tvalid : in STD_LOGIC;
+    s_axis_tready : out STD_LOGIC;
+    s_axis_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    m_axis_tvalid : out STD_LOGIC;
+    m_axis_tready : in STD_LOGIC;
+    m_axis_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 )
+  );
+
+end fifo_48m_to_122p88m;
+
+architecture stub of fifo_48m_to_122p88m is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "wr_rst_busy,rd_rst_busy,m_aclk,s_aclk,s_aresetn,s_axis_tvalid,s_axis_tready,s_axis_tdata[15:0],m_axis_tvalid,m_axis_tready,m_axis_tdata[15:0]";
+attribute x_core_info : string;
+attribute x_core_info of stub : architecture is "fifo_generator_v13_2_4,Vivado 2019.1.3";
+begin
+end;

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/ila_rf_test.veo

@@ -0,0 +1,78 @@
+// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+// DO NOT MODIFY THIS FILE.
+
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+
+ila_rf_test your_instance_name (
+	.clk(clk), // input wire clk
+
+
+	.probe0(probe0), // input wire [11:0]  probe0  
+	.probe1(probe1), // input wire [0:0]  probe1 
+	.probe2(probe2), // input wire [0:0]  probe2 
+	.probe3(probe3), // input wire [0:0]  probe3 
+	.probe4(probe4), // input wire [0:0]  probe4 
+	.probe5(probe5), // input wire [0:0]  probe5 
+	.probe6(probe6), // input wire [0:0]  probe6 
+	.probe7(probe7), // input wire [0:0]  probe7 
+	.probe8(probe8), // input wire [0:0]  probe8 
+	.probe9(probe9) // input wire [11:0]  probe9
+);
+
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file ila_rf_test when simulating
+// the core, ila_rf_test. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+
+

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/ila_rf_test_stub.v

@@ -0,0 +1,31 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+// Date        : Thu May 18 12:55:28 2023
+// Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
+// Command     : write_verilog -force -mode synth_stub
+//               /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_stub.v
+// Design      : ila_rf_test
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z100ffg900-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* X_CORE_INFO = "ila,Vivado 2019.1.3" *)
+module ila_rf_test(clk, probe0, probe1, probe2, probe3, probe4, probe5, 
+  probe6, probe7, probe8, probe9)
+/* synthesis syn_black_box black_box_pad_pin="clk,probe0[11:0],probe1[0:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[0:0],probe8[0:0],probe9[11:0]" */;
+  input clk;
+  input [11:0]probe0;
+  input [0:0]probe1;
+  input [0:0]probe2;
+  input [0:0]probe3;
+  input [0:0]probe4;
+  input [0:0]probe5;
+  input [0:0]probe6;
+  input [0:0]probe7;
+  input [0:0]probe8;
+  input [11:0]probe9;
+endmodule

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/ila_rf_test_stub.vhdl

@@ -0,0 +1,40 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+-- Date        : Thu May 18 12:55:28 2023
+-- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
+-- Command     : write_vhdl -force -mode synth_stub
+--               /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_stub.vhdl
+-- Design      : ila_rf_test
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7z100ffg900-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity ila_rf_test is
+  Port ( 
+    clk : in STD_LOGIC;
+    probe0 : in STD_LOGIC_VECTOR ( 11 downto 0 );
+    probe1 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe3 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe4 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe5 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe6 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe7 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe8 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe9 : in STD_LOGIC_VECTOR ( 11 downto 0 )
+  );
+
+end ila_rf_test;
+
+architecture stub of ila_rf_test is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[0:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[0:0],probe8[0:0],probe9[11:0]";
+attribute X_CORE_INFO : string;
+attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3";
+begin
+end;

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/sim/ila_rf_test.v

@@ -0,0 +1,80 @@
+// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+// DO NOT MODIFY THIS FILE.
+`timescale 1ns / 1ps
+module ila_rf_test (
+clk,
+
+
+probe0,
+probe1,
+probe2,
+probe3,
+probe4,
+probe5,
+probe6,
+probe7,
+probe8,
+probe9
+);
+
+input clk;
+
+
+input [11 : 0] probe0;
+input [0 : 0] probe1;
+input [0 : 0] probe2;
+input [0 : 0] probe3;
+input [0 : 0] probe4;
+input [0 : 0] probe5;
+input [0 : 0] probe6;
+input [0 : 0] probe7;
+input [0 : 0] probe8;
+input [11 : 0] probe9;
+
+
+endmodule

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/lpf_125k/lpf_125k.veo

@@ -0,0 +1,70 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+// IP VLNV: xilinx.com:ip:fir_compiler:7.2
+// IP Revision: 12
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+lpf_125k your_instance_name (
+  .aclk(aclk),                              // input wire aclk
+  .s_axis_data_tvalid(s_axis_data_tvalid),  // input wire s_axis_data_tvalid
+  .s_axis_data_tready(s_axis_data_tready),  // output wire s_axis_data_tready
+  .s_axis_data_tdata(s_axis_data_tdata),    // input wire [15 : 0] s_axis_data_tdata
+  .m_axis_data_tvalid(m_axis_data_tvalid),  // output wire m_axis_data_tvalid
+  .m_axis_data_tdata(m_axis_data_tdata)    // output wire [39 : 0] m_axis_data_tdata
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file lpf_125k.v when simulating
+// the core, lpf_125k. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/lpf_125k/lpf_125k.vho

@@ -0,0 +1,85 @@
+-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
+-- IP Revision: 12
+
+-- The following code must appear in the VHDL architecture header.
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT lpf_125k
+  PORT (
+    aclk : IN STD_LOGIC;
+    s_axis_data_tvalid : IN STD_LOGIC;
+    s_axis_data_tready : OUT STD_LOGIC;
+    s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+    m_axis_data_tvalid : OUT STD_LOGIC;
+    m_axis_data_tdata : OUT STD_LOGIC_VECTOR(39 DOWNTO 0)
+  );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : lpf_125k
+  PORT MAP (
+    aclk => aclk,
+    s_axis_data_tvalid => s_axis_data_tvalid,
+    s_axis_data_tready => s_axis_data_tready,
+    s_axis_data_tdata => s_axis_data_tdata,
+    m_axis_data_tvalid => m_axis_data_tvalid,
+    m_axis_data_tdata => m_axis_data_tdata
+  );
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+-- You must compile the wrapper file lpf_125k.vhd when simulating
+-- the core, lpf_125k. When compiling the wrapper file, be sure to
+-- reference the VHDL simulation library.
+

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/lpf_125k/lpf_125k_stub.v

@@ -0,0 +1,26 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
+// Date        : Tue Mar 21 16:04:38 2023
+// Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top lpf_125k -prefix
+//               lpf_125k_ lpf_125k_stub.v
+// Design      : lpf_125k
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z100ffg900-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "fir_compiler_v7_2_12,Vivado 2019.1.3" *)
+module lpf_125k(aclk, s_axis_data_tvalid, s_axis_data_tready, 
+  s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata)
+/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[15:0],m_axis_data_tvalid,m_axis_data_tdata[39:0]" */;
+  input aclk;
+  input s_axis_data_tvalid;
+  output s_axis_data_tready;
+  input [15:0]s_axis_data_tdata;
+  output m_axis_data_tvalid;
+  output [39:0]m_axis_data_tdata;
+endmodule

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/lpf_125k/lpf_125k_stub.vhdl

@@ -0,0 +1,35 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
+-- Date        : Tue Mar 21 16:04:38 2023
+-- Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+-- Command     : write_vhdl -force -mode synth_stub -rename_top lpf_125k -prefix
+--               lpf_125k_ lpf_125k_stub.vhdl
+-- Design      : lpf_125k
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7z100ffg900-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity lpf_125k is
+  Port ( 
+    aclk : in STD_LOGIC;
+    s_axis_data_tvalid : in STD_LOGIC;
+    s_axis_data_tready : out STD_LOGIC;
+    s_axis_data_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    m_axis_data_tvalid : out STD_LOGIC;
+    m_axis_data_tdata : out STD_LOGIC_VECTOR ( 39 downto 0 )
+  );
+
+end lpf_125k;
+
+architecture stub of lpf_125k is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[15:0],m_axis_data_tvalid,m_axis_data_tdata[39:0]";
+attribute x_core_info : string;
+attribute x_core_info of stub : architecture is "fir_compiler_v7_2_12,Vivado 2019.1.3";
+begin
+end;

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word.veo

@@ -0,0 +1,67 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
+// IP Revision: 3
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+rom_freq_word your_instance_name (
+  .clka(clka),    // input wire clka
+  .addra(addra),  // input wire [6 : 0] addra
+  .douta(douta)  // output wire [10 : 0] douta
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file rom_freq_word.v when simulating
+// the core, rom_freq_word. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word.vho

@@ -0,0 +1,79 @@
+-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
+-- IP Revision: 3
+
+-- The following code must appear in the VHDL architecture header.
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT rom_freq_word
+  PORT (
+    clka : IN STD_LOGIC;
+    addra : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
+    douta : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
+  );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : rom_freq_word
+  PORT MAP (
+    clka => clka,
+    addra => addra,
+    douta => douta
+  );
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+-- You must compile the wrapper file rom_freq_word.vhd when simulating
+-- the core, rom_freq_word. When compiling the wrapper file, be sure to
+-- reference the VHDL simulation library.
+

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_stub.v

@@ -0,0 +1,22 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+// Date        : Mon May  8 18:56:10 2023
+// Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
+// Command     : write_verilog -force -mode synth_stub -rename_top rom_freq_word -prefix
+//               rom_freq_word_ rom_freq_word_stub.v
+// Design      : rom_freq_word
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z100ffg900-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *)
+module rom_freq_word(clka, addra, douta)
+/* synthesis syn_black_box black_box_pad_pin="clka,addra[6:0],douta[10:0]" */;
+  input clka;
+  input [6:0]addra;
+  output [10:0]douta;
+endmodule

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_stub.vhdl

@@ -0,0 +1,32 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+-- Date        : Mon May  8 18:56:10 2023
+-- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
+-- Command     : write_vhdl -force -mode synth_stub -rename_top rom_freq_word -prefix
+--               rom_freq_word_ rom_freq_word_stub.vhdl
+-- Design      : rom_freq_word
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7z100ffg900-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity rom_freq_word is
+  Port ( 
+    clka : in STD_LOGIC;
+    addra : in STD_LOGIC_VECTOR ( 6 downto 0 );
+    douta : out STD_LOGIC_VECTOR ( 10 downto 0 )
+  );
+
+end rom_freq_word;
+
+architecture stub of rom_freq_word is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "clka,addra[6:0],douta[10:0]";
+attribute x_core_info : string;
+attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3";
+begin
+end;

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/sim/rom_freq_word.v

@@ -0,0 +1,211 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
+// IP Revision: 3
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module rom_freq_word (
+  clka,
+  addra,
+  douta
+);
+
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
+input wire clka;
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
+input wire [6 : 0] addra;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *)
+(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
+output wire [10 : 0] douta;
+
+  blk_mem_gen_v8_4_3 #(
+    .C_FAMILY("zynq"),
+    .C_XDEVICEFAMILY("zynq"),
+    .C_ELABORATION_DIR("./"),
+    .C_INTERFACE_TYPE(0),
+    .C_AXI_TYPE(1),
+    .C_AXI_SLAVE_TYPE(0),
+    .C_USE_BRAM_BLOCK(0),
+    .C_ENABLE_32BIT_ADDRESS(0),
+    .C_CTRL_ECC_ALGO("NONE"),
+    .C_HAS_AXI_ID(0),
+    .C_AXI_ID_WIDTH(4),
+    .C_MEM_TYPE(3),
+    .C_BYTE_SIZE(9),
+    .C_ALGORITHM(1),
+    .C_PRIM_TYPE(1),
+    .C_LOAD_INIT_FILE(1),
+    .C_INIT_FILE_NAME("rom_freq_word.mif"),
+    .C_INIT_FILE("rom_freq_word.mem"),
+    .C_USE_DEFAULT_DATA(0),
+    .C_DEFAULT_DATA("0"),
+    .C_HAS_RSTA(0),
+    .C_RST_PRIORITY_A("CE"),
+    .C_RSTRAM_A(0),
+    .C_INITA_VAL("0"),
+    .C_HAS_ENA(0),
+    .C_HAS_REGCEA(0),
+    .C_USE_BYTE_WEA(0),
+    .C_WEA_WIDTH(1),
+    .C_WRITE_MODE_A("WRITE_FIRST"),
+    .C_WRITE_WIDTH_A(11),
+    .C_READ_WIDTH_A(11),
+    .C_WRITE_DEPTH_A(81),
+    .C_READ_DEPTH_A(81),
+    .C_ADDRA_WIDTH(7),
+    .C_HAS_RSTB(0),
+    .C_RST_PRIORITY_B("CE"),
+    .C_RSTRAM_B(0),
+    .C_INITB_VAL("0"),
+    .C_HAS_ENB(0),
+    .C_HAS_REGCEB(0),
+    .C_USE_BYTE_WEB(0),
+    .C_WEB_WIDTH(1),
+    .C_WRITE_MODE_B("WRITE_FIRST"),
+    .C_WRITE_WIDTH_B(11),
+    .C_READ_WIDTH_B(11),
+    .C_WRITE_DEPTH_B(81),
+    .C_READ_DEPTH_B(81),
+    .C_ADDRB_WIDTH(7),
+    .C_HAS_MEM_OUTPUT_REGS_A(1),
+    .C_HAS_MEM_OUTPUT_REGS_B(0),
+    .C_HAS_MUX_OUTPUT_REGS_A(0),
+    .C_HAS_MUX_OUTPUT_REGS_B(0),
+    .C_MUX_PIPELINE_STAGES(0),
+    .C_HAS_SOFTECC_INPUT_REGS_A(0),
+    .C_HAS_SOFTECC_OUTPUT_REGS_B(0),
+    .C_USE_SOFTECC(0),
+    .C_USE_ECC(0),
+    .C_EN_ECC_PIPE(0),
+    .C_READ_LATENCY_A(1),
+    .C_READ_LATENCY_B(1),
+    .C_HAS_INJECTERR(0),
+    .C_SIM_COLLISION_CHECK("ALL"),
+    .C_COMMON_CLK(0),
+    .C_DISABLE_WARN_BHV_COLL(0),
+    .C_EN_SLEEP_PIN(0),
+    .C_USE_URAM(0),
+    .C_EN_RDADDRA_CHG(0),
+    .C_EN_RDADDRB_CHG(0),
+    .C_EN_DEEPSLEEP_PIN(0),
+    .C_EN_SHUTDOWN_PIN(0),
+    .C_EN_SAFETY_CKT(0),
+    .C_DISABLE_WARN_BHV_RANGE(0),
+    .C_COUNT_36K_BRAM("0"),
+    .C_COUNT_18K_BRAM("1"),
+    .C_EST_POWER_SUMMARY("Estimated Power for IP     :     2.5016 mW")
+  ) inst (
+    .clka(clka),
+    .rsta(1'D0),
+    .ena(1'D0),
+    .regcea(1'D0),
+    .wea(1'B0),
+    .addra(addra),
+    .dina(11'B0),
+    .douta(douta),
+    .clkb(1'D0),
+    .rstb(1'D0),
+    .enb(1'D0),
+    .regceb(1'D0),
+    .web(1'B0),
+    .addrb(7'B0),
+    .dinb(11'B0),
+    .doutb(),
+    .injectsbiterr(1'D0),
+    .injectdbiterr(1'D0),
+    .eccpipece(1'D0),
+    .sbiterr(),
+    .dbiterr(),
+    .rdaddrecc(),
+    .sleep(1'D0),
+    .deepsleep(1'D0),
+    .shutdown(1'D0),
+    .rsta_busy(),
+    .rstb_busy(),
+    .s_aclk(1'H0),
+    .s_aresetn(1'D0),
+    .s_axi_awid(4'B0),
+    .s_axi_awaddr(32'B0),
+    .s_axi_awlen(8'B0),
+    .s_axi_awsize(3'B0),
+    .s_axi_awburst(2'B0),
+    .s_axi_awvalid(1'D0),
+    .s_axi_awready(),
+    .s_axi_wdata(11'B0),
+    .s_axi_wstrb(1'B0),
+    .s_axi_wlast(1'D0),
+    .s_axi_wvalid(1'D0),
+    .s_axi_wready(),
+    .s_axi_bid(),
+    .s_axi_bresp(),
+    .s_axi_bvalid(),
+    .s_axi_bready(1'D0),
+    .s_axi_arid(4'B0),
+    .s_axi_araddr(32'B0),
+    .s_axi_arlen(8'B0),
+    .s_axi_arsize(3'B0),
+    .s_axi_arburst(2'B0),
+    .s_axi_arvalid(1'D0),
+    .s_axi_arready(),
+    .s_axi_rid(),
+    .s_axi_rdata(),
+    .s_axi_rresp(),
+    .s_axi_rlast(),
+    .s_axi_rvalid(),
+    .s_axi_rready(1'D0),
+    .s_axi_injectsbiterr(1'D0),
+    .s_axi_injectdbiterr(1'D0),
+    .s_axi_sbiterr(),
+    .s_axi_dbiterr(),
+    .s_axi_rdaddrecc()
+  );
+endmodule

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/sig_clk_gen/sig_clk_gen.veo

@@ -0,0 +1,80 @@
+
+// 
+// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+//----------------------------------------------------------------------------
+// User entered comments
+//----------------------------------------------------------------------------
+// None
+//
+//----------------------------------------------------------------------------
+//  Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
+//   Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
+//----------------------------------------------------------------------------
+// clk_out1____48.000______0.000______50.0______172.739____111.288
+//
+//----------------------------------------------------------------------------
+// Input Clock   Freq (MHz)    Input Jitter (UI)
+//----------------------------------------------------------------------------
+// __primary__________122.88____________0.010
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+
+  sig_clk_gen instance_name
+   (
+    // Clock out ports
+    .clk_out1(clk_out1),     // output clk_out1
+    // Status and control signals
+    .reset(reset), // input reset
+    .locked(locked),       // output locked
+   // Clock in ports
+    .clk_in1(clk_in1));      // input clk_in1
+// INST_TAG_END ------ End INSTANTIATION Template ---------

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/sig_clk_gen/sig_clk_gen_stub.v

@@ -0,0 +1,22 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
+// Date        : Tue Mar 21 14:52:21 2023
+// Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub -rename_top sig_clk_gen -prefix
+//               sig_clk_gen_ sig_clk_gen_stub.v
+// Design      : sig_clk_gen
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z100ffg900-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+module sig_clk_gen(clk_out1, reset, locked, clk_in1)
+/* synthesis syn_black_box black_box_pad_pin="clk_out1,reset,locked,clk_in1" */;
+  output clk_out1;
+  input reset;
+  output locked;
+  input clk_in1;
+endmodule

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/sig_clk_gen/sig_clk_gen_stub.vhdl

@@ -0,0 +1,31 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep  4 09:45:24 MDT 2019
+-- Date        : Tue Mar 21 14:52:21 2023
+-- Host        : JOSH-ASUS-Z690 running 64-bit major release  (build 9200)
+-- Command     : write_vhdl -force -mode synth_stub -rename_top sig_clk_gen -prefix
+--               sig_clk_gen_ sig_clk_gen_stub.vhdl
+-- Design      : sig_clk_gen
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7z100ffg900-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity sig_clk_gen is
+  Port ( 
+    clk_out1 : out STD_LOGIC;
+    reset : in STD_LOGIC;
+    locked : out STD_LOGIC;
+    clk_in1 : in STD_LOGIC
+  );
+
+end sig_clk_gen;
+
+architecture stub of sig_clk_gen is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "clk_out1,reset,locked,clk_in1";
+begin
+end;

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_manual_ctrl/sim/vio_manual_ctrl.v

@@ -0,0 +1,68 @@
+// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+// DO NOT MODIFY THIS FILE.
+`timescale 1ns / 1ps
+module vio_manual_ctrl (
+clk,
+
+probe_out0,
+probe_out1,
+probe_out2,
+probe_out3,
+probe_out4
+);
+
+input clk;
+
+output reg [2 : 0] probe_out0 = 'h4 ;
+output reg [0 : 0] probe_out1 = 'h0 ;
+output reg [31 : 0] probe_out2 = 'h00000000 ;
+output reg [1 : 0] probe_out3 = 'h3 ;
+output reg [3 : 0] probe_out4 = 'h0 ;
+
+
+endmodule

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl.veo

@@ -0,0 +1,70 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+// IP VLNV: xilinx.com:ip:vio:3.0
+// IP Revision: 20
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+vio_manual_ctrl your_instance_name (
+  .clk(clk),                // input wire clk
+  .probe_out0(probe_out0),  // output wire [2 : 0] probe_out0
+  .probe_out1(probe_out1),  // output wire [0 : 0] probe_out1
+  .probe_out2(probe_out2),  // output wire [31 : 0] probe_out2
+  .probe_out3(probe_out3),  // output wire [1 : 0] probe_out3
+  .probe_out4(probe_out4)  // output wire [3 : 0] probe_out4
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file vio_manual_ctrl.v when simulating
+// the core, vio_manual_ctrl. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl.vho

@@ -0,0 +1,85 @@
+-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:vio:3.0
+-- IP Revision: 20
+
+-- The following code must appear in the VHDL architecture header.
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT vio_manual_ctrl
+  PORT (
+    clk : IN STD_LOGIC;
+    probe_out0 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+    probe_out1 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    probe_out2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    probe_out3 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    probe_out4 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+  );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : vio_manual_ctrl
+  PORT MAP (
+    clk => clk,
+    probe_out0 => probe_out0,
+    probe_out1 => probe_out1,
+    probe_out2 => probe_out2,
+    probe_out3 => probe_out3,
+    probe_out4 => probe_out4
+  );
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+-- You must compile the wrapper file vio_manual_ctrl.vhd when simulating
+-- the core, vio_manual_ctrl. When compiling the wrapper file, be sure to
+-- reference the VHDL simulation library.
+

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_stub.v

@@ -0,0 +1,26 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+// Date        : Mon May  8 17:56:01 2023
+// Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
+// Command     : write_verilog -force -mode synth_stub
+//               /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v
+// Design      : vio_manual_ctrl
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z100ffg900-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
+module vio_manual_ctrl(clk, probe_out0, probe_out1, probe_out2, 
+  probe_out3, probe_out4)
+/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[2:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]" */;
+  input clk;
+  output [2:0]probe_out0;
+  output [0:0]probe_out1;
+  output [31:0]probe_out2;
+  output [1:0]probe_out3;
+  output [3:0]probe_out4;
+endmodule

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_stub.vhdl

@@ -0,0 +1,35 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+-- Date        : Mon May  8 17:56:01 2023
+-- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
+-- Command     : write_vhdl -force -mode synth_stub
+--               /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl
+-- Design      : vio_manual_ctrl
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7z100ffg900-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity vio_manual_ctrl is
+  Port ( 
+    clk : in STD_LOGIC;
+    probe_out0 : out STD_LOGIC_VECTOR ( 2 downto 0 );
+    probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 );
+    probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    probe_out3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 )
+  );
+
+end vio_manual_ctrl;
+
+architecture stub of vio_manual_ctrl is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[2:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]";
+attribute X_CORE_INFO : string;
+attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
+begin
+end;

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/sim/vio_rf_control.v

@@ -0,0 +1,91 @@
+// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+// DO NOT MODIFY THIS FILE.
+`timescale 1ns / 1ps
+module vio_rf_control (
+clk,
+probe_in0,
+probe_out0,
+probe_out1,
+probe_out2,
+probe_out3,
+probe_out4,
+probe_out5,
+probe_out6,
+probe_out7,
+probe_out8,
+probe_out9,
+probe_out10,
+probe_out11,
+probe_out12,
+probe_out13,
+probe_out14,
+probe_out15
+);
+
+input clk;
+input [10 : 0] probe_in0;
+
+output reg [0 : 0] probe_out0 = 'h0 ;
+output reg [1 : 0] probe_out1 = 'h0 ;
+output reg [0 : 0] probe_out2 = 'h0 ;
+output reg [5 : 0] probe_out3 = 'h08 ;
+output reg [5 : 0] probe_out4 = 'h38 ;
+output reg [11 : 0] probe_out5 = 'h3E8 ;
+output reg [0 : 0] probe_out6 = 'h0 ;
+output reg [0 : 0] probe_out7 = 'h0 ;
+output reg [0 : 0] probe_out8 = 'h0 ;
+output reg [0 : 0] probe_out9 = 'h0 ;
+output reg [0 : 0] probe_out10 = 'h0 ;
+output reg [0 : 0] probe_out11 = 'h0 ;
+output reg [0 : 0] probe_out12 = 'h0 ;
+output reg [31 : 0] probe_out13 = 'h00000000 ;
+output reg [0 : 0] probe_out14 = 'h0 ;
+output reg [31 : 0] probe_out15 = 'h00000000 ;
+
+
+endmodule

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control.veo

@@ -0,0 +1,82 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+// IP VLNV: xilinx.com:ip:vio:3.0
+// IP Revision: 20
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+vio_rf_control your_instance_name (
+  .clk(clk),                  // input wire clk
+  .probe_in0(probe_in0),      // input wire [10 : 0] probe_in0
+  .probe_out0(probe_out0),    // output wire [0 : 0] probe_out0
+  .probe_out1(probe_out1),    // output wire [1 : 0] probe_out1
+  .probe_out2(probe_out2),    // output wire [0 : 0] probe_out2
+  .probe_out3(probe_out3),    // output wire [5 : 0] probe_out3
+  .probe_out4(probe_out4),    // output wire [5 : 0] probe_out4
+  .probe_out5(probe_out5),    // output wire [11 : 0] probe_out5
+  .probe_out6(probe_out6),    // output wire [0 : 0] probe_out6
+  .probe_out7(probe_out7),    // output wire [0 : 0] probe_out7
+  .probe_out8(probe_out8),    // output wire [0 : 0] probe_out8
+  .probe_out9(probe_out9),    // output wire [0 : 0] probe_out9
+  .probe_out10(probe_out10),  // output wire [0 : 0] probe_out10
+  .probe_out11(probe_out11),  // output wire [0 : 0] probe_out11
+  .probe_out12(probe_out12),  // output wire [0 : 0] probe_out12
+  .probe_out13(probe_out13),  // output wire [31 : 0] probe_out13
+  .probe_out14(probe_out14),  // output wire [0 : 0] probe_out14
+  .probe_out15(probe_out15)  // output wire [31 : 0] probe_out15
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file vio_rf_control.v when simulating
+// the core, vio_rf_control. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control.vho

@@ -0,0 +1,109 @@
+-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:vio:3.0
+-- IP Revision: 20
+
+-- The following code must appear in the VHDL architecture header.
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT vio_rf_control
+  PORT (
+    clk : IN STD_LOGIC;
+    probe_in0 : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
+    probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    probe_out1 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+    probe_out2 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    probe_out3 : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+    probe_out4 : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+    probe_out5 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
+    probe_out6 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    probe_out7 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    probe_out8 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    probe_out9 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    probe_out10 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    probe_out11 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    probe_out12 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    probe_out13 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    probe_out14 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    probe_out15 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+  );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : vio_rf_control
+  PORT MAP (
+    clk => clk,
+    probe_in0 => probe_in0,
+    probe_out0 => probe_out0,
+    probe_out1 => probe_out1,
+    probe_out2 => probe_out2,
+    probe_out3 => probe_out3,
+    probe_out4 => probe_out4,
+    probe_out5 => probe_out5,
+    probe_out6 => probe_out6,
+    probe_out7 => probe_out7,
+    probe_out8 => probe_out8,
+    probe_out9 => probe_out9,
+    probe_out10 => probe_out10,
+    probe_out11 => probe_out11,
+    probe_out12 => probe_out12,
+    probe_out13 => probe_out13,
+    probe_out14 => probe_out14,
+    probe_out15 => probe_out15
+  );
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+-- You must compile the wrapper file vio_rf_control.vhd when simulating
+-- the core, vio_rf_control. When compiling the wrapper file, be sure to
+-- reference the VHDL simulation library.
+

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_stub.v

@@ -0,0 +1,39 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+// Date        : Thu May 18 11:36:40 2023
+// Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
+// Command     : write_verilog -force -mode synth_stub
+//               /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.v
+// Design      : vio_rf_control
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z100ffg900-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
+module vio_rf_control(clk, probe_in0, probe_out0, probe_out1, 
+  probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9, 
+  probe_out10, probe_out11, probe_out12, probe_out13, probe_out14, probe_out15)
+/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[10:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[5:0],probe_out4[5:0],probe_out5[11:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[31:0],probe_out14[0:0],probe_out15[31:0]" */;
+  input clk;
+  input [10:0]probe_in0;
+  output [0:0]probe_out0;
+  output [1:0]probe_out1;
+  output [0:0]probe_out2;
+  output [5:0]probe_out3;
+  output [5:0]probe_out4;
+  output [11:0]probe_out5;
+  output [0:0]probe_out6;
+  output [0:0]probe_out7;
+  output [0:0]probe_out8;
+  output [0:0]probe_out9;
+  output [0:0]probe_out10;
+  output [0:0]probe_out11;
+  output [0:0]probe_out12;
+  output [31:0]probe_out13;
+  output [0:0]probe_out14;
+  output [31:0]probe_out15;
+endmodule

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_stub.vhdl

@@ -0,0 +1,47 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+-- Date        : Thu May 18 11:36:40 2023
+-- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
+-- Command     : write_vhdl -force -mode synth_stub
+--               /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.vhdl
+-- Design      : vio_rf_control
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7z100ffg900-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity vio_rf_control is
+  Port ( 
+    clk : in STD_LOGIC;
+    probe_in0 : in STD_LOGIC_VECTOR ( 10 downto 0 );
+    probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
+    probe_out1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
+    probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 );
+    probe_out3 : out STD_LOGIC_VECTOR ( 5 downto 0 );
+    probe_out4 : out STD_LOGIC_VECTOR ( 5 downto 0 );
+    probe_out5 : out STD_LOGIC_VECTOR ( 11 downto 0 );
+    probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 );
+    probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 );
+    probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 );
+    probe_out9 : out STD_LOGIC_VECTOR ( 0 to 0 );
+    probe_out10 : out STD_LOGIC_VECTOR ( 0 to 0 );
+    probe_out11 : out STD_LOGIC_VECTOR ( 0 to 0 );
+    probe_out12 : out STD_LOGIC_VECTOR ( 0 to 0 );
+    probe_out13 : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 );
+    probe_out15 : out STD_LOGIC_VECTOR ( 31 downto 0 )
+  );
+
+end vio_rf_control;
+
+architecture stub of vio_rf_control is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[10:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[5:0],probe_out4[5:0],probe_out5[11:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[31:0],probe_out14[0:0],probe_out15[31:0]";
+attribute X_CORE_INFO : string;
+attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
+begin
+end;

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/hdl/vio_v3_0_20_vio_include.v

@@ -0,0 +1,283 @@
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "XILINX"
+`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1"
+`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
+`pragma protect key_block
+GbQWy7xyRnDVKNEgu/syxcQSo3KIIWjSBPIwi/pSAYCe9sIQf1xA0ykhHf7s3r7GRWRS+sel+0Xx
+XWe4lBDDrw==
+
+`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
+`pragma protect key_block
+rLh670IEMVEjBamdsB+LhhoxrK6I5H9wfmPCOFqaLelJt08QWbH7WNvjIhNNz7hnkT7w+wDWT6AH
+9ZJgOGPSJmj9pWoXHAojkkRBTIXpFT11+IDyFQ4FgN2TPXWILoYGY+uZG1GlGN7dsEIm5HUCUy2c
+eVhT3XSIJDvufMyiJUc=
+
+`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
+KgKxjU+tI9TXRZLkaaosEf4JcTfzGtF82aOinFlVe78eUyHdMvwHHcKsxUKAjkhYW491bZ0jTKit
+pNc3Ov7QvW8kjTq3JHFuCf7SmCYRrmElQv0XobTk6mnMb4khaXw9wTP8YMS0XAqk3Bksal+aKfvX
+LL/afyM4UwBfiIb04ZgvhdOlp/dkCqWqZyDL2qVScyGrZcDCW3CCZTVQO29hqMLZP5S82keXpBv3
+5J7nHHbQ3n4dxsRykYtJtwg7JDyqGHiwhj1HDtjhG+LX9ry1wy5YgvxrzSfKoouAeHCKXcG7TY0a
+sz4nRUsC3Yg3/CybYyPjvVJDirIzWRzSD6l1DQ==
+
+`pragma protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
+ItrqCM44kZl0WwWeSAjetSYD0fPwYZdVjFp5cRl5XZyoYOMWKCVEXncinM06x/MDVlkYiXgz2Xqn
+6ui7jR7RwOKALvqoqdehIoXZUA/5yPMntFpxPcFIY1DonBI4CuMjhqCuB2RkxKNIco5Z7/QxCk49
+MCUlvIFRd2MXM+zvhCRdja7e9blnwJEUETukq+EKuAwuR3+VN3uzCXsNtgBqMZa2CyM6Z60fStuc
+v1eiDP/hxOimuSfsS7evakl5WMjgZuj4Jld1+y5hTOuPvw4+s3KIb2ejIH2r/I7ui7sWUZTah36a
+4QexKWP16Ghv319FCz4KExZ6lY+7HuoO55lf4A==
+
+`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
+FGUAaXx6dK7W5dgDUXY6j9xLpCHdbPvbaH+O+ozu9kcNjL5BJcGWnTdooAxaZdBsOZBvrVuXUU4v
+ev5owQI9+5/+8aoXfeX2zZHp++ESqotCFj5ykw8BPjwCOCZz+tiV1Q8ISqf/NCuDNU2KJyvQUsFX
+cOXAwCPvrI5SwQ04u9sVTaHwAuTuRw3j6nkt6BHWrjKpq9pUfNH4L04ag/tUGVpnlcSBGewN0ieC
+xkzVV1mPCyCu/thxu0k0yda5pS/u3MFeC1N8rTrSsLEZMUiPYg/BwwWGT7D/s9FCMbbM2kyoUXpa
+draqn+K8c06CQxLI+ieilCd38M25buwOc3ANjg==
+
+`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
+`pragma protect key_block
+ucIv1ZvudBg6K9ubpyCObknzSo2JKwxETiac5kbTyw0xwj34bo+xJ/DnUCoAdEVHZcAwDc9Fhbhv
+j5a7MwnHY+TpzDjhwdN75A97jOZ4V65wcuFErbH19OSacDchGykcwXCiaA5haDJK2hF1qPxu7TtO
+R19uHYIhWP+7IpmjTiQ=
+
+`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
+AI09c0Va0j6swrG6tMKXPaWcjMpXDnvuIze3bAe9Cj0tCXFumugM/pZL81X53kMwmKPvRCpTi8DM
+kLLATubglrp6DudyaIY943skTmlH+as6fKaHODrTcy4CDIP4kKrok/7y1rBI6+YAfN3ZIW+45MiV
+cHuhXHXxxXblzCT6obAZK5QUCP2qZKgO0jjI1RD7ZEJuS/mX5wkIAvOe8L1HBkyUsRq6Cu30W6u9
+7VI3LOy7TZqb6Nix6Ok85ylO82KP12tdXY2IRivakKu4fdWQ6vc3ARiefSR0+RDmE/eZzhzQbt26
+mf7t4ZoEITJYnmd5zcenAnw+6AO3fUwtTLT81Q==
+
+`pragma protect data_method = "AES128-CBC"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12464)
+`pragma protect data_block
+vLDJJUgjrlRfGtI6e1+Byt5lDBB9Oezy8FH9Uy/Lem9icZpnVjts8rEqPHcw31BJ5u3y4ePWkCUm
+QQfQ8vh3WaO2dCX+QhbDMTmPaIe/t8nHJKefrbW5OY3eRKkptlVSIFCFITpJlzyfpSe0CsF+dWLc
+F4J0aJzlQEKkTcCFk2ey1erWcvHgIf6eCwkGouO/COjRPomcaMzJt3ty3PwhKodmumGUICNXKjG/
+lH5VI4pSkr0hpeNp/WZhHstrrYJB7GSwMCqfL0IH36wCF3R29Yjp7ouoogJ4+imS5vnMJpU2Czmi
+PFyY3LiBeZ4VP5b8Iv0AK4XoJtM3XG9iTBAC/oslCJUtBhINFPia8EueAVn178qtq+htmZXlEAbM
+O43w6xZ55fggub8NiHe8M4qAhDC0nwv3LBVndn8xEKF+13iwSiqhLjU1Cya8z+0j0TUExIeVQyri
+OXh0d9oxCJ2lfPtNjHZ3LkjbMLvzdJG8pBuDtx5952IJrwkJIaT76aOEs7XK8O+cfrtfhh1fPpY1
+XTzoMx95+Qp7Ay2J8NObIZHBuUKX2ORE3b7zSBW5FPRjaxTibHQ2blQzoAbo5y5f30hxOHsi0+Xe
+D4bwHKzoBpsdKAyvlKom17BBx5Q5KccIElz3z9ulgthM6zwAWmMVPzQnJAhmz3Hl3t0m7+YNA4Ia
+cg/H8tiXcV6CEnRuaFRr8dvkZAlT16o4u+tEwi85XgpkoApFQ7EytG673+LigwZbb2C7khwEoIiw
+1LN4Eh9i2WsLPaEipn3q58x1rH4/MEzwsGw7loWE4BkCf+n5QAWYc/nk4xfSwFTBvxs6sPejsrRX
+qbtO8ZOnKuVTT2ZLwEtvGrf+Ii1Xymt1JsQt7Z0QBWTykLt0ZhWTrPnMg/zcRxyRCDNYWVJx8JKC
+Fjg1XzSDYIYff4HaLPjmiu5sPEXaKTQJvaZa52Dq87oKwWI0A3g0ymKK7UVXrmX/odtLOlHIxuhy
+JnruUntWueD34KJMT2lBO7AP0g/OmHDI6v72Q/2Tk66QaWfnnDJl6qRN2WDuGyNuwSflbEGQiK02
+vyM4a6K9KN70ev9aLX4d2m7Uo9n4GFbdvjakrlHDS/K+TRs6XmOa+y8ErWxn9Pfy9UyRrFg1TdQb
+Zk69XUdoQZ6CNWoKazZHaJ5p5+6nk/G0nm8LR039U2sqH+B1hJMuvFvsx4NzEoYpE1jNsiy4B9Ta
+ArVNSpGuZCA4Juifia1UC8m+mMYsLBACf9YX/Uua3EeOfU2CEi5koPuBzR/QKb/1oRa3x2oux2Cf
++p+HcJdQfSOpF6AkpWZLChsoTMd2F24Ztmjz3/vNIapPf4rcObfDEJwayu7hSrsslcCIcoXdojo4
+VXLn2QFVUYMgSq3pYGFywvmQTA5x/JAfOcWO8IBKdixvS3F6xSTwH8JaKocC0735inh65PwNjS9F
+2KIwvgHQvLpCxNny+0NvSQ7ETTouC6xXj+EUv4bGpml7J3HNjixHtTPfYXf7cl0mqQmUDJu0wLkp
+WuvXFDvCxpwSZ5qw+1H5MPeue3MeB1Z6Ibu51Fs1EwnAe/g9C0Mo1XDCD6LfVjvpZYE62HzlzF/K
+IJoLfeJT0O0VhjqhC3+M3TGXHNYm6chuUtfNR31cC7WgG/QiHYOVySvp3zljDZWrxsgHO+JwhbQC
+n8ALL+g50X6+uS5w/HkFBsxwCIocmViJb0ojg1j2ncsUjwwEqkDBprVPYFh6Zimk5SJ9f3RO6pQj
+saDd3hitIgpMf1ha8rpCYBkwqBTogxXfwijLMplBdGWVGSSSnnp6jTnWb0sV2VPA1l2X6Iq+pomM
+jilYYfQ2dBuXFEMpQpwDC3/8N4YxpDZWX3gtyK2XV+2BcRONvrl/naflTsXxuXAhSxOBqggJw7pL
+HvsOGKk0ng6uKC5yQPc6Q0SbWwwT54D9vLM4U1OiRKPpL9S1YXak+W8ZCXqdHkQNlUlm21ssL4dl
+Et7q9IF5Vil/wnUjm0nJxVZ4QJU/uN7icrtnrvAf1gVLwK3fpC0ed6ku9s7Lq1KvNb7NEPDrOu3Q
+hg+xhyl9MJTquidnbUsYlHdTvVzxIkI4q/1kx5mkbEjiIWG0R+haIwSqhTCdxpxxTgm+LGAtWJ4W
+lEuCQ2VEu3cyamx3PWNKPt+CE1VayIkgGqEBXIaGpwkymL0y6hkgrA+q+2msQq245iR7XC83U26E
+yb3da4UnYxL7g5WjJCSfCdNVOkKS1Yl9VZ6XSW5RFwWIdURQyewZxfPKaJWsDAGfpRftpZ2mOfIl
+DP1TwLOJrgsh3QI82hOYlUbHmcPIFMH3Pqp4OpbOBRcPcZhabwMA3pidOtbloqo5pRGblsO79JSJ
+OdbTH0XVln2LAlQ0bOmaMt9/rOwfexnMgActW5gvaaxAXuYDKRM1UMECbAxeXCwqzS0dc0V8ypcG
+fteDGHXMo0F/XAmGvVeyXJ9wCk8OaNq3QfJv7J98GeFlsisK3g+DzyHnma8+DPiQz5fXZYlWQATB
+TYmRqvJl1KzKtTAluhm7MMLb3F8xL2NDeGuxLbfrf6E9zY45m5mPjZ9RgD7Lp/aRq3yRGIHZT/Hj
+UOW9tPIFXsnd71c0SWPBukdkw6Iu4mmRap139EPPn1NbxII0Kx4bXAFSaRSVv/XzPy5uqO62NQBW
+NGvw4f1JGumSY/O23vkXjZaGvN+S0bz8EKrqST2JR7xwKXiyc1EiBTO4wNbd6azULsK4LQc7wEe9
+fLtkLqeh1/tDw12z4e/cGuujh09rf8Olns7hcq6KvzDyM4MT1hSizKeViDqgTaWsim2icOPXIWGf
+sFNi0Bc38qKoDMEnsp36riwZe+y4DdFzqzq0Yrr9+0B5ByNMyLSvi4M65KZswrHoq1MwgubuGmRu
+bnAcGsxnoNMIlXHHBxS1+kIY2Dh9+Op3PVTHiBM/kexi6XMyY9pwe8I7Fd+L4PTexmvNKi2x2UOL
+UB7l3OgfCdwQ1+9QgliX4xN46NNnISm8EFE0zpn4SAV7B38UDLL5XBcO4aOW2/+q4crLHtw/9GsO
+Y/Cx5SaOa3cx/2UTFnVpxTvDICQyosM7R93SgxQmmXswXIdh8L2v/X/bojwYGYza/K+ZJ0+GVEmn
+nCagAUyAPO9aMwlnCcidIDOIx639+B7IWa8jTYsObePK4Ghp0//E3pFZ5vIkTWsQXfAYwjvWp2BP
+uzZRqK+C5GbLkw7SZrUlFK5w4BI7ABx4bYqP78Tc95Ps8aGL0SCwiBy9wMXqlvcjOpsy2CWJcBBL
+No8TvQKlYRdWealaPFJO9gB0RF3LDIjFwXgnEoKX0BxHOftGEX13le2Gj+dqsFGgktTXoPqVXMnL
+PadND3iSF8Mff8/7uoQGaAyV9g5DOJqmQLnj0eF2QyoBvRGXBL/bKGoIll//kBqaNk12RuOHWHbT
+U3iLXaTrhf6yOmDHZS38ocYG3lcoaDi9EBU0SpzR2m/JSjAWViDRbV14QeUf5lflN3TECF/z/MKo
+gEjxx6dUwsjIVt7BIZZgOL80YeU3xkS37nzrv3xyl2G0JIC9mpKwrIQHkyP7JC87DWrMHJOYHtjt
+PEi+zZL25OwIqRTZP4gg6kmeS8iRsBEL+Wk7s2gqpe8V4NTQSt2HTXZp5AmCgTmS8a0DR/A75FTA
+oqGCUEQmrmej2XJT/KbkzAsUiZnJmY1k7SGAZTnNXaPuj9i/AAUayAg/URaLLS0rwvoFuiQ+er1J
+ybk7ldZcUYpebiVjfe0oBAa2KcW2qf5kI099lfylsrU1uO6XEmh1+VbtTRbuUrmEwJVG4p9UoubF
+AJ5DHGvb54gwpkLa3TRT+DjjpI8s0l7qUFB7R0tizSDuDX64GDdpM1pVSkFBUHll+6mks5or2/VB
+Hln3g/I8AdHS0Ee5lAgRL5Vgy+KWSBTLnjmXLh2PLn57BNiULh7VPy829wKrZJzgBOYcGlMu5kVN
+i+q/xu2QYwfcgRXDwljWcFOQvoqkcg/ohyPA25kU5XTO426LkqCkp2B0LjwS6Ru0LFCAT9VD7Xfs
+gC577whnyCFKF02by8lumThgKPi3e+MFtFtUUP4NqrLVuoSbDZsRwrNLyTJF5CT1Wl+aOJGzBGLb
+aL2kFLF94YfyykQ0o02bH63Eq/QsrvKdm76fU02BuG8sPH+GK1L5aPAurh/ab5w1JeJBFY5pOKJT
+4fTwDyIeEAJz40vvDBQETJqKAhx9slR77zV2TVAcxQmhXXAIqZXXBO4UNgOILVyLPm8NKFZWdS12
+5rxQdEE0s8y1Rlg7X+kk8gHu6a/p0FivgMMDJuguKcf9ny0SGFHsgKO10TL3rr9swBrfjeJFqAHl
+8W0pH40VE7s+aSVwYDpLrNXaIj1huF7Nq8R6N7mAzihrKyJtqe2DPGthc3b84plrtQYyABnDsPcV
+XbMi+Hx7t/RKzR8L4kpXW5iFnOd7LF1uNCDdhIKWpoUxHnK6vKemXGK9h0pRsFZVohQ5sopKQOyf
+tJ1isqkEpBP6oxCvnVnRbFV98aHA/yOywevf5nDEJAphXQxOPUg1wSrYQYyqMfwqvWNmTDuqN1go
+rW1nqIaOkZREKe0NScx7qC3I+8/ez+12dTJjqyv77G91cucF7CB+uApoocTDq4tPa8LQlR3qLjzq
+AxZ8CVJ3uVUgYv9lp/EI5Gb0GrZC3APt8tbR5WZC1E54EoOkj5prTRaon3PVL45oSNcPWZAcx/Gh
+sXORdqYB6CW8+sC1kSQfKQJifA+ZAyRCvvQihld8XSpwx1zUa+LM6lPLA7wlphZ49dGLYr2CkQY2
+tXqToNQ3zSltn097FYtScosgXjCeZGa/4TktbJTpJgvxNpDtJqmRtfQE1ADqwSLMbBavYK7FGTw8
+XgWElR1F/Qub/wupGjRfM9hciZyVh2psk5atHuL8/U/OeXSZaiirana5yKNG9ML4neG+c3Ffrvrw
+dgdUbozDo1QV/0Cg87j8rLVdFRgM4BRWPCmhg1tVdr8IMCd/UzggMBXmb7mbXAYbnVAu1Vqxb8/i
+EbdzYB08pVdUn7jlTr6MeLNinFYRTq0d2j8xKP0hCTHVXHNbqU39kREEe68c6FOF3SiJXOX8qtnL
+D8YZlKOOiqCzd43er0Ysy61SsfAstKPe+dg9vZmsoE8/xcD/3/4sALY7BlWJz68btYgaBASDCU//
+6gqk28sSeHQARhFY18vCNuLAf+dRD7Zze1Ya6kt22/nstLou1lRgGmDjNm2O3iXExXIPG/C6YYIm
++ZMypy+ZdUCkzpEzpaGk/3BrdaFKH2s1N5sE3fWaA/BIIFxLNPVf897o7Ij03t+Bf71s+JBR3BUV
+9y7JJhslPI2/daCPSJ3oktvJIGYwLLp3qfznlcZuqdPdzlhN1T5TWVZZbXFFaL9FGo+rPo0dKrbM
+Wo6hmW310X/qVlc3ctYz0lvVkYns67UDHVrVP/SBQPIYETmt2hsWlzJU1CRCby4uBBsIZXwe+j2b
+9PW9ETn2gyplsyBWewR0f5/xsB1q6Qn9zG0usHhxK9SGLeohwJlDS5YOLB3+gn57VvtBcOCMY8Rr
+UEG+pgmDhvBxacswIQ8EI05LKINgsIRhfgBpZW0mz5m2q8kIOz2BAJCvpJgP0FPevu5Aqp8mIQPP
+XbnfppOC204x9UzilksaVjLDZ//txnmXZ8uhv62NP6MTQLNvbL15Pu8l31x1sbOV1qYZx3PAsTXJ
+vllgzGP9ABfPyx7JUpV2evLblwFrNERmZ2+zXXJpqrC1Y+Ov+y8h2uwKsK4lKHdlBbHwThPq2cTq
+KTkMYt6RebsvxZFGgJ6yCPdBhTx2ChLIQcmCPTj/Cm7ObdneYwd95jdv9iHg/d9pfG86QOUU2C5G
+xLGBVWEFe99YFTQQ6P56UzhgKPwJw+xgM/aTnoym0USW+WRbpF8pO5vXSa0UfxGAGTv9q7JqkHKr
+4iTBPPXJtWBhNl5rzUh8OJSTjMKQTLIv+btrrmsLhWk8Nfwa1GcpBoLBrZOxrwP2f7flQSnVnpz+
+4xasi+5di7/V6xOZemXcfgKGWI4wjehafy0oCnRFIPOfEiWVQid2K5nodgxJK4q89nYXd9OoqRTD
+AdyqlFa/Jluk0IikDwurqAU+Xup9pJI3C67dOMX7naeOYGZujxknSJUCO7Kua3mygTXk3bUyk40U
+doNI6/wljhhP3iWlzB+n/kaUg4HNcwZmZ74uX9jpIunTr5tASrGmrQO/VC9CHD6+Em9UYj8cNhKF
+7CqnnxKng0r5zt4/aG9G/y722aeAk16U+4hze9jyqG2axwKnNxd/UVmw+GbZLsCDlXr7zSZoxW4x
+sM64LaY1oGJobMVrrqdby+Y5r+5hKeMT/44jo/aNf+6eMxDYoYTH3epAwlH7bOCmeamTo1huxBZT
+XThu+Q07lQaDFZqLTAblck8J0qkr2HpxzQgqYJrlacxkUALRTyrw+jH+IZA8N/FT6RuQf0+PbN78
+VIRBJSqCQl02jGtP5rsSn/HycL5Ox04HkdfIH8QYThUzR5+udvtklkxOZtOHBUdzBW8Opljffh/5
+k3+es50uiyKTgL5O+iYOSDkjVhojw4mQAEH/PJAlPXfy8VPE8QqCTWW7Ed2huLNU2naH5iS1T/Le
+ShJB+/lO4hv7daACsQUBy3CvVJ2+ruK9QJnWshHcq/0FuZ1LJF76ux4HdJ9RoVyOwBD6tIUP+XZK
+cr2VOw4e5FYEpZpZjXVEx1/ENgiBeGAcr/UKTpt4voXTk6ea5eBtmIgEcPeWZU2cKBgG/QaO1SXa
+xSWK6eU+7InXUItxijDl/lnWPx9CVPV1BCfUOkcz3EQ/HL0UeaAXmhzyJvka0zEnjPrrQkztRCge
+t4yP57MciI/K3OUQ45ZORC+vL/6bD9juHR12kKn93LtWileJJ15bGSrOtGJIoaTR7F29WCDSEB5z
+yjzl5n/WSWcSDiqAR+S/ZC9uWpkQXhSD1oPCwsQSU9eEce9nvDm2E+f4apRAzWlwpci6r6gdbGTL
+h4dTrEIgEqJVmEP9Svu+2xHIVYTcbd8Abkz8JYgHyGH5tifzu6UWSu2G9pIY0r8dBelnxZdNheLp
+iiyUBgnPMv2M7VCFZLpbbJzBF1MFN/7jEPHiW5dA/nwvL5v46yg/fYSA9zV8Tz+aYVAMxd55bFTz
+Ws/PjjIQrtifnNGtyR63clFuegIt+ftcNC34dPtQqTqgoXwcXUG29idHgfvU76Fhm87ldyWopnsk
+aFdduRQA3+ZPnXMIEmNvEf3iiW3DWFaUbP1d8kCgrwRBfE8+v7HHMI1QJP8mTgPv4Iy7l1elI0y/
+Ax6MbQaR7bAvQlBb2iu/LJF++LJQsWnfHNyTBe9h85NaH6zRuZjpc29RX9JjnCO4nBRYDSyuSDSe
+fsX4pIWp7xhlkhE8Vq6kJQPd+LoekUz7mOchfv4TirPuh3HquJBF8XAGmgdE9tDWE3CiXJIgkQVp
+dbrFhqkwem4OlipJUY7yZKEzOmtHtwi8BeN3RaiOX+rUpuAa4knsAG0XF8OAGljke9T0nkX+bQ6Q
+kMLmcx1ZLotyx+dwituzYg3n3/2rLoNaDCrxdv7eGSiwEwAQaGTE91GfsK/bW3LilAlBF4slbiHO
+Gr5i3euR71fgubMoEbFNK/CTI56XnhBZKGNsezvyNZhTIctMPxggNQ/BgJe71lsPcLznK44PV4aj
+7Q4qiQ8dRtlJTgS3IAQvtTAqvLDcUSPnq7AWHavmljjJT5QX+rDJsNvJXfrcy4RGQudCauFNIxqe
+GWq40gIpsl5qdSLuOy9j1vP3uBz2ioorlCf0AE/TCs+XZBX0M4iQo97CSqrRVsVb/ycyRjzqFKDk
+ff9/m6kuAdIqU/8DWoq9bmb9RKRZqwG0jGteggwkv3Qu7OwYzYczHpW8QHqMxSg5VQuP2bRXb9J8
+WGm80TYiii+TWVBifZUrikX1sIO6gpBP2xRZDybWn67xaxQ4aUoMVR9F3tLo+pH3M06QuwRc8UVw
+NJnDRG3sgmR6i53cvdLTfYzi8WNesxlcL99IRwZ+8XrSPr8bDyibEJVtCkpNthFHvQ+BGtQlt7M1
+BWgz4VlLW5XG9g31idaWDyM1TJPGgZjePDguHn3s+cowoTgl8RjcwaO8fXqNIDNc7Nqw7DhCJXxf
+OOErW0Bj+5za1YjEQ+MHEgLWJm7vOeWxPzNwQFslWXWeypM02ONdpqRj20w95++SlZ2zKvh6dopw
+3uNDXuMirFALSIbwUDMYypbRHPbGhRoyUYQ1gyRo55xdGUgMTNmbWWDE6UMCp1mW80oGpR6OWmdO
+VwFKsuzeGs1ALnTweVm36FPemaFSzk3pc7rPiZmdhs1v7+dw9FYjBttfkwcf/Iy7nk0Ev8oSFRZ/
+ex1zi6BXYS3bILREFMpWuRTw7HtE6I3RpaA/k3OzHdMzZFml4Xkn7f2j7gkhPHzXToR52p6f/P2G
+oPD3blyogU6TUQ3LKFTqNiqQZenz1x3XdwqscEp/4i5w4fux9cjWwrVI1Dx6mPJ1tCNCi1kEIAZQ
+zOdUeZKKPJ+gu3/PfZBDdCZTZsGI2XIoYJ0Vk64K48gnuUCK08d1pNCABh8YBXF2zT5pPp9A99on
+j4mRR/u91Cel2mHReNJEynTJHMuZzf4BmXj76H/01YrVKaWyLJs5zSdAykxhA2h/LGnYEaiNBPWb
+39te0WIrUs+IG2dO91DB0USld72iU4jEwSVZzvyPNPL33uNtNSZYayM+g2cYg7U4bPcmdzW5YUJR
+alsYJPrDv+KlKSqyj3EulKAAql50npg0tCM85ZMPE/zz6d0uC4cGWi2AkUGX/9dSBE1/0xgfQveU
+0+OtofanGvTY66DLwOtQegffJlegmLvWyBa12w7NxGVhm8RfpdDvLyVdc4sBxzM6zKVpwcuSZy/k
+seYqXFSq6WE9rb/d4VC8Ta6QLg716zEh+OklBSyeF/tbD/neWeVcJkZMzQ6w1VjihYLGqOnDBNlD
+UB3KNJuEqvyyTK1zMVBmluGZhspXj1yq8ZV2xfkxiEMLL7NpdSSItMlZTamNo9nGYpLMFzxKMAxR
+teItxoLs9ZKVWd8fW/P1iTMKayoh+aTg2lxH0ZCcdyp2NOEjCmkTAAXr18ZRN+WOhhzMw3uqwzNd
+6HBsbnlER/M8VsNgP+VBgmuvRNBlUMuJT+usv/p4Q9Bh7yFI6XhArqBq1teX6H2scn8Tn2WNKBeb
+9u/30RygW02pSX1vxKKLkx+ytrAnPVpiMinMiRLu32R4tOaI5jj0l0kZabn2uIArfZv4P85wG5FT
+LK5kniV1MkMOL+x3zk2BUaDB14bStOfLzZSbrj4wKri0MFKlqzWzTUG83q18kJTF5Gtm2NuaZZ6U
+W2WilwcqBSs+I4Tg0npMEzVxjngyw8DHp+eYEmrELjH1sGAaF4zTqFcc0K3Sd090sJPnl8P/Zab4
+CILx8N+ma0flJZWl9A9ONOokCHPJopFlVzikH/EO+/v6KJN3fkOnxGOCqp0F/UjxA1dAU09O3saX
+DupicKgsOh56WdrVad7VIggWzKI+HlYW4BWhFFtoZQTMdGg5OHzYiaCi9Bui1Zsqp/wPy8T1KD0e
+jBQPyxGZ/sq+ul19GWt6clKGKbMWgewsWBqAR/jgfIAIMkTkvG0CCdUkVCYBqtC/7M8fPAihKZ9p
+Xpqo3FDK7g9NjRYqnH+db+SOrt8GTSZabN5cgWW+D/LOOOAEhDCNwyDKGJXLKLTyjTd0gwfXrcfQ
+PnW526o0e2U4sP2hYSNWZ9fIJMlSKDfn45b/LgMj+uLkcnSu07pbcJIC9tad9d9vd4JMVPZj7W4d
+xz4JQjCqZyZOrXaceYrYee5H/BbJSTiHq6/gr9tNJscIybuvKAHDTl2plPuESjfVlczmANiPcQEF
+Evn0dqw7zpblg3aExbLNpjLLX8IcEpjfXD/Qz/hfk/UPE41U6UviUwzkSHE0c9xHVqb7nHfSfo9S
+7pkoZKV6Cj6RmsmKPnjf7/WLgoDeGBEm4Mde9fhovbwmrlpI2QcYsuO0dg6vo2Q+DeC7SO9wzGOe
+TmmxM3WXjhDy2uiDyls8ZUwruC7Bh0T+zHljR47iWDw4A9RnLWU4GzBzuS2TR1LWbP0Khrz6DwFs
+nHD+b8yGBFdI8rUA9r+LJNBy46oo6pg4bwkhPrZGGvJdpZkXFQ9itfGlsN/TZ/Jo64v0Z5ocEEkN
+Of0nVQpDnBsPhDDgj96Tx+f8sX0au2/KIPzZzV1hivOmWnIqgl44ZWLxVoy0ns/w3kF5NoKo0LQU
+s14F/NE32TD/u23zSOJiDe1LnTKJgO/0T6ulhs1iw5upeq6rCMEEdFOIxQcLbCsY2A73mJRnPHmR
+lHN9yNCDpuhxCFiDeL5/Shm+lxStfHBLHmUb2f/jVXorCS5SQFFgpOGYef6qyQPSBNXciZf9Sbdr
+Qnu10CkltDgf/0saImmVuvpWrho3booiXFEVOSPDxOBZezF43Y+zyuFNrvkDoo0z0vAn7pRctJ+M
+en5InchEyM7kTpQo816yPYhq932YEWpT/BL/XthZxXuC6cRq3rxmyHES/t5XlqEKFyok9/OqyJns
+l0KYVQijY1toOhWysECQ//wIdzHJAKPd/LnAq1VQd7p73mbHc8zvFaG+hPNeG5PCmEv0NbxWIkSk
+EyHj2QblPQi+vdwOA8/lLZJTLn9k5HEB0LK2i1qn6SbzyamgTMgrK4+Yz0oLi8XRq5x0Ebx7e7Mg
+m4HXSRNragMZA12zvzHaepmX2YTHdmaLXmAq1lbh2wxbo/KXmFBLJ8E1RxubY6ZNznO/We3bqSE3
+xyaKhdt0VzCU6ZwJNsK0N5xOqFn43zajLltRs1zmPrZ+BGj3fBfNBtu2ZPJBkiraJG76VhuBa3HN
+AwljiAVWWeXuVTOQC+SoPDceebdL21D+TUSDg3hEAM0RjIyYv19Han2s7BbaaXpsrYqsLHv4+VbA
+qOwJVIli+TaoCNYkfLwTLQVuD1wv01kV4qq5wZrjOBv9eq5vywskXrvNi7vr4x21UjQqYTFmkEPs
+Sy9tiL0DgA3pRch8vk3D2xaf4Z9sK5zR8YqugMVsAQ8sTn6hN25znEucHWxIZA6OTbAqe3SjSEPo
+yscvFEtiZGMpSaO1BeWc70tM1JSv3Mq74tWLOjnUxdAMXr2eXwf83R8C+r/C2VHXpKZlbNuSptyQ
+r+TC6oJKmjBTiViyKAtMUkNX/puBz/fkHDAPPQe+eNb4MFxvkJvl1zb+Jyb57d8mCYyhz19+TZ0s
+EOB7MpKqqQjz/AlDHzIYSltJ8wnIVsd2Neqy8y6OOYoyYTN27vPyWk7G+h0Mgg4EtmAWY/h55Pyl
+5YlNP4Ll39xGxdlk1xq5Bt2kD4b4e3laUAvM1h2hoLD0ouVwkcmdPTAL1bcbfQlQ7F8QWd1WrDfw
+L3a1w1cqgUVYKSmnsg6NJ+oLOlJQGy8wY7yUvXmZfFDySiY+avUR/t2i4XWwX+lRh08bQ6ec/tt3
+SVbDklDfgVoRVmrbxv4sQad5EVH9Nn511AAa9lWrJLYdIRC0/LoNczEgM0uaMYb46hxrrwJ5fGef
+uolQ4Gs77vx9keudHpiqRJO62BdHgDCaYDUltxrknlVzb6j0VRqRd3YD8a/N8KX8njOn2UMU+tsz
+EfJoQeB/SamZ5cjNe3DOHG9fptHNhpH3AgupdeHZhOa6s3Qh+1QJsFn04Uy9otihMXyHUfD14HHn
+TTGHg6eEuDH9RjVLpJ9OMP0BhvkFRRVwT9blnY+V8/LU8a0guNCUwAfEKEQx99yUC2mWSa5/bJxy
+Z+Nfl3wmXF9gLlhmCEIlqHFCPTaL6g6tVjtT6KwqxKfFdeQ842GhWblC1+gT7NwiLjntx6UxXdHP
+jWyovNmstdoZGvlaiC0UPxdHXmC53mEE7xslGTy3x/GfvwD9Wdb0QyB0pn0wFU4dYg+HuuJ2tZk9
+e5N/9xEIk7/etVr6+gwmhLy6HVukFRqCEk8+2plhAjmVF94UUrLRm0eTWKmgu/mi8ertCPhxhmoX
+ByW+bhc+mQ1X0Q4zeO3YljMM51iXstIO/2gR0Re7khCmgQ5g9AdkHaPvBxRxZXaPoCw70Ir0PXLE
+dE7UDCznrXz/BitxSJgNJcmaJHoBVskzEOegQhAhAkyAV6SZ22S4AKMxb4Mb8BpkZkKNz4j3wDbl
+CRUy3zK6Tjc4Nqy8jfhYaRynMhBQvSCPclmmSen4vNnqXI6aQhYXR7Z2AgOP+Ap56ss4IbTy9KKi
+OPkun2RaUDAGa2Lwjc+PzMvdbSEnnlvTleo/uFqy09UJ5OyrjkIJNBxDxfHJ7IyNGdoaW3IefWAX
+rKaL7xvop3b5BPqWMvXXRSqysOzyGN/s0f8fiCrtHI6ym2xolwawx6zQZqKKv3Be+wKvTgRT2sh6
+xDJfQ3A00hem1RnQoVtPumBwow1QQbuVd8TNu7arV8oM5rKM6NMVecmND12ayeEVgKK0N/3IdsYO
+F4MLdAOd4MebirS+NMRdcxb2hdfFbA9dMw9Rce7q10x4IiVU3DT7Vo7IKHnwPOso4A2+hWaTt5Hs
+gNH6nqK1WaFHx8HIBktEg9tGl9ifBfYSuisgMUHs+1/e8ZwMmn78iBvMaUkXR/1m1SAK13gDrPOV
+2KRk1f8MuUONuZtRHbsSsoRzeEEj2MblEFIUkXKPGSnGtpyaIqcLKu7qSNqEWbd3Mi6iqZyAF9ur
+S6PrT631ucYj4KsgxamK3CkcPnro6JRXoW0bhfZ+FXdUMudyp9ciMAmR0Xm2CUwwoLb8BERVr9fi
+VraW1mYpdUtEgGUyYF8wK/m9DtCWErSUVF7KTwXcQ1v7cC9UYluD4y3/NQoOAkmLp3q4iMvI6Kr9
+wXPu3xTOgClz/Ske9d5zj9FHXX17ahUlM6L4CEP5hQa6NsPaBp1uykxeRkQ7/DTbuP2TeFNFCSNB
+c0MrXeXL8l3KuVjnQPG3zoxDIZcDyRavpLLamqDLergVscng6L68Yawbsp/7V39jWYmit6uTXmp2
+f2ncjHWTjL0XwQzypjcAELV1+oztimMwLbjSVD0phFRes9iBRK72DYxyumFEUz71wn48hrTVPyiv
+OwqNkS3IVQ89yHXEHjlbn5mG1QvvTrFhVsa8HMvSsvRw3YKji+5g6VSsKfWFwD9+L2uVb28OKpTJ
+cKL7M17lzF20jyOi3otlBI58p9xkdw3EStQRCVsBu0Ndv03deh078hmZ0HxBYx2WihCnp7pqf5ok
+H2b3GMbtmM8HuFKmstioDyd3wGfzUisb9394+do1aViRsEnfX1JytHtrbZHtBkDBMDeu1xemX4RH
+SdEqzvwXjLHrXR0y9WJvAzoedZz31pBbDzvZXkzRmKdAeszVYf0oVkXChUa0Iv/fPpw86N6/8+P2
+VPHGAVW7HHD5O5/fILc/OnzuPP7FNctlbjeoXoOpkoPgnSE25bSDEIpWkNwEdV/jnkHnsJYphp6k
+GbnBCj/5xIP7oYaDOoWLK+nDtwjEUMItMNNxVXBECuBo4DxxKp6DbWP3yF2tpzAg9w9j9AnlQB7J
+eNz3s1yPJ3QJSu0WFonPDcE9fepllJZXjtlCVe9M5BMOBowY+hjvgQhE7FNblFZvEithQ82dDAqa
+s/GpNPeczJVmzSB5su0G35o8nGfK4ZoWmOHqqsPhmE4r8lRR6fceHsT0/uNOI0wER6O7UFOOe33j
+VZkt3M8yIRuUIxBlBHOaSgluYveHryPMo6BXQKlRL9sauqc7TpLDMGby2i2Vs6oGBK846hXuVC7t
+V2dYDayv1u0Ge1HTHsN5qkXY+d5Om9Gbv+o1P4aeDW/Hq5FEGeM+M21cI5zWdkxenxRa83hUEj26
+v2Zlt80v4XT2YrJXwrSv9/s4r13D1nQxa+OLtCkswaew9xoNRGKjcvpq4UQCp6tbkxD0vb8CkoNM
+cdPJFZZywgON5pFzzafo6o6alG9UEROYK564Ukp+wv4Xt/7IQpzGf9dbB6yFYp2L1URdlebTvLx5
+hM1L2n1ND+QZU0JGytXefsrxRaxRx4C6HUnkYDc7xb6GgHZIMN1h5iClg9Cd3dAMkE9UAp3DM3/x
+ISJz9CaphM74pPa5dKbqvkS5pJO4kbGJkHEJVLr1l8GcOQyUxnghqEZ1zyCNaapf8lZxkfpfgq6x
+DGgZqwf5LUAsp48H/3MZd95X8QsJUy7DRXHRmkfxf+186QNCmLzbhEhQHSyA9c/odoKhHfbzDrzz
+/IkHBHBTn0eLBJLKJaa76hdRhBNJ7sQHHAH0fbKOeN2RJKXMXcw/XYRjOTQmsFCpT3NBHmOQiJgh
+3CdDOALtnNy4biZgOYL35bnbtFd1xUqTqC+RUgy7s3hy2qYtRkmVym6UV30Gj5TIhX2yyeiLDr3/
+jh8oFVLi0vc0q9Cc8e/OgV2APtbhFKtmd0nf+qDwJNcP//aElllnka5RtY8szPGbEOnaoDRJh56V
+hQh7aYlaHiSTBUYkTqZAtZmddvPDoR5MYP6eHmspahZP3r5gPnGg9dEPZYniwa9R4AyIBG6CLzl7
+VAb4Up6hlQbSbazZAxSnm+D37Vepi02N1mUN+kZLkuXoE+8bSkCLkoUHAggz6A1FFZrVFBOZJFF3
+yanmQKRKVeV/RYWvCiCWK+NMHrKLjqwXE7BuzG4+kwJz4yptIZG7+QQ9/y++9K2qfGzpFAKOvYVA
+QoivjQTdF68auy5ncT6ZGGsg1KSWqiU6r5yQQE7+0086p9DpxCfeFinvElNbr/k1SeAAgX0mCiNN
+dXHULePP/Gipl82oGh1JJCdAQ9LDpey65p0KEjYXXANeTZwhPYOga4BHA0oN4pwOdnTeCb5A4iZ/
+heS3mgFhvHAhevmsEhIK2h2zSF3Akf5BwgPCbpnCYkYb+ME0TdvNEiJCphU9jUE4p5X9A9dSGDJj
+khYzrG0vqQ5aTHUtA/ettxOdp4eUS7ysX0thI24EuES+7VvT4f8wgeSqBHZFzQ/CElgrRx4ExPs7
+D0v5Ej5wagiorCgqq7nJ+WVo4jzSjwP1YPz0OorE1bZuBq7lGr3Rbp63T09vP9TTzlMsJSWxGHqT
+JeKFlv86ZJ1h39w2Zj+8gJ4U4AZbOygG4bLImMVZigruDqvkaOxNreC1k+1vLgOPtZ/kWzXOwH+O
+/KlC0MjIWmtLxc4WQHgphsph364TvIk2pNXhw0kVpwDtyTQQTZ0uelX9+IewGOhxjBSp71WJ3KS6
+vd6oUylWNSjtHxK7eVyclTxCvy8AwzP5K+8lwRzhDkWw2j7nriqzZ6sBQ8sc55H3/PkQ1nhDvP3S
+Y4mETg95nQKorrqSDgb6WO6YmD7apM6gCf2H5/4poh7YLqjOw7ajEzyPcoHqdJRC+6dswNNb8pdu
+Eynk1RGGG3fnXVSGn5SSGA2S8xxJpeOPXqhwWm47l709TR53pdlNgeNlLSat/LE3Yr6f3dzCO3+M
+mLQSSv4FDwGW+hU2bHZPiUhUUQSmaa9T19pbpa6s8ZJ0xLEbS3z1xEajwM0bFGEGE+lodnN0Ziu+
+StlkG0O7ozjg6V6hRnz8KkJqNDirqESfbjE6WMHtc599lGztc/77jnBfdHd3VIuf4IgUcezITMqj
+5MGygT2/VAEb4BZAbcRxPGqKcLfYnJZ63t3QEqbgblMA1vFo4VgSV1ajLUyoDGBGLV28ExlwTut1
+HzIaED7RvsGxFpR26+1akJ1/8bReaeZFhca9QQVHRvj1X698r4C/XUsrSc+05XtjMx6HM5q1yZwu
+pU7X3s5l0gEMjqTKe4cxHPW2hjvKhiEEb66pzjN7HK0y5nrjMJxzwtfqbNV7b76TcDtX27W08c9U
+hsEprM3gDA7yAWiwAy3nxW57jdofbM5LfU0HVc1mK3FN0pfA/Fg0HWk0RX6K1vbYorZ2YFYwkpIK
+Spx8l1Y/4Kpd/0yvO9c4f8OcsEc6LfaQSV83l2H8v6NalHbhaZ2gKxmDZi/k03xDyL8v6GCn18bp
+dB5LUUJUKbnsl6q5E9b8DkJqSnAaHRLJDnEvMp6EfGlpc52On3lCg0wI5XERerziamjcMH44VZfd
+j8z1WUyHlyOSmkvZdJ66PfYWu5BxCG7hfdtSGROPtIxs36iLmesyYm4yHKwwbWgNIrLgra92DF2L
+R6e0RM1WWkcJHei4v89Nmwym4k0dKMTX1HkfTogoprrdIyDYj4qMmeTqfl0U8pRehVs6/zy4x8HS
+0V2+smFFQ/BZxLQ4eV8NHKeszc4kI6jJ3OCncsP57tfkE6TmVTtWKiimERISYB4KhUpblsbN6zyX
+Bni5ezNwl9XdaBq9c90k+QQmaMGeyQbczdGy9ufcC269vB1FU5+a67Ew8h0jPAPeYHvsw4kGsTSh
+xnhGNUHRuPoNmQYBjI2LztvnbGuoucUVntUi5quKpKAK1fOZerZTh+kr5PjaW0YlozpL5CtElvS3
+eqqkVT8a5mdW+sWTxJxTjqronag0QACsSwbA9qurCW9IdcOO+0D7nzfIJIFrWKx+D71JhKNvOmUa
+NmCy9l+wzdpcLs1zvS3o3zwEgUWOOHzITgzOxtDhIuBcJkg9lS+o5b+W+U9fplCbVFjYd5ZDa2sX
+90/8XCJA0a9VcsSrh1LoO0V3YX80VWdNPY79OUOlqftl3rNXVXE=
+`pragma protect end_protected

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/sim/vio_rf_test.v

@@ -0,0 +1,82 @@
+// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+// DO NOT MODIFY THIS FILE.
+`timescale 1ns / 1ps
+module vio_rf_test (
+clk,
+
+probe_out0,
+probe_out1,
+probe_out2,
+probe_out3,
+probe_out4,
+probe_out5,
+probe_out6,
+probe_out7,
+probe_out8,
+probe_out9,
+probe_out10,
+probe_out11
+);
+
+input clk;
+
+output reg [0 : 0] probe_out0 = 'h0 ;
+output reg [7 : 0] probe_out1 = 'h1f ;
+output reg [7 : 0] probe_out2 = 'h1f ;
+output reg [31 : 0] probe_out3 = 'h003A9800 ;
+output reg [0 : 0] probe_out4 = 'h0 ;
+output reg [11 : 0] probe_out5 = 'h3E8 ;
+output reg [11 : 0] probe_out6 = 'h5DC ;
+output reg [31 : 0] probe_out7 = 'h00004800 ;
+output reg [31 : 0] probe_out8 = 'h000000C0 ;
+output reg [63 : 0] probe_out9 = 'h0000000000009600 ;
+output reg [4 : 0] probe_out10 = 'h10 ;
+output reg [0 : 0] probe_out11 = 'h0 ;
+
+
+endmodule

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/vio_rf_test.veo

@@ -0,0 +1,77 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+// IP VLNV: xilinx.com:ip:vio:3.0
+// IP Revision: 20
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+vio_rf_test your_instance_name (
+  .clk(clk),                  // input wire clk
+  .probe_out0(probe_out0),    // output wire [0 : 0] probe_out0
+  .probe_out1(probe_out1),    // output wire [7 : 0] probe_out1
+  .probe_out2(probe_out2),    // output wire [7 : 0] probe_out2
+  .probe_out3(probe_out3),    // output wire [31 : 0] probe_out3
+  .probe_out4(probe_out4),    // output wire [0 : 0] probe_out4
+  .probe_out5(probe_out5),    // output wire [11 : 0] probe_out5
+  .probe_out6(probe_out6),    // output wire [11 : 0] probe_out6
+  .probe_out7(probe_out7),    // output wire [31 : 0] probe_out7
+  .probe_out8(probe_out8),    // output wire [31 : 0] probe_out8
+  .probe_out9(probe_out9),    // output wire [63 : 0] probe_out9
+  .probe_out10(probe_out10),  // output wire [4 : 0] probe_out10
+  .probe_out11(probe_out11)  // output wire [0 : 0] probe_out11
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file vio_rf_test.v when simulating
+// the core, vio_rf_test. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/vio_rf_test.vho

@@ -0,0 +1,99 @@
+-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:vio:3.0
+-- IP Revision: 20
+
+-- The following code must appear in the VHDL architecture header.
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT vio_rf_test
+  PORT (
+    clk : IN STD_LOGIC;
+    probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    probe_out1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+    probe_out2 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+    probe_out3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    probe_out4 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    probe_out5 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
+    probe_out6 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
+    probe_out7 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    probe_out8 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    probe_out9 : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
+    probe_out10 : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
+    probe_out11 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
+  );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : vio_rf_test
+  PORT MAP (
+    clk => clk,
+    probe_out0 => probe_out0,
+    probe_out1 => probe_out1,
+    probe_out2 => probe_out2,
+    probe_out3 => probe_out3,
+    probe_out4 => probe_out4,
+    probe_out5 => probe_out5,
+    probe_out6 => probe_out6,
+    probe_out7 => probe_out7,
+    probe_out8 => probe_out8,
+    probe_out9 => probe_out9,
+    probe_out10 => probe_out10,
+    probe_out11 => probe_out11
+  );
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+-- You must compile the wrapper file vio_rf_test.vhd when simulating
+-- the core, vio_rf_test. When compiling the wrapper file, be sure to
+-- reference the VHDL simulation library.
+

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/vio_rf_test_stub.v

@@ -0,0 +1,34 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+// Date        : Thu May 18 12:54:39 2023
+// Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
+// Command     : write_verilog -force -mode synth_stub
+//               /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_stub.v
+// Design      : vio_rf_test
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z100ffg900-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
+module vio_rf_test(clk, probe_out0, probe_out1, probe_out2, 
+  probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9, 
+  probe_out10, probe_out11)
+/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[0:0],probe_out1[7:0],probe_out2[7:0],probe_out3[31:0],probe_out4[0:0],probe_out5[11:0],probe_out6[11:0],probe_out7[31:0],probe_out8[31:0],probe_out9[63:0],probe_out10[4:0],probe_out11[0:0]" */;
+  input clk;
+  output [0:0]probe_out0;
+  output [7:0]probe_out1;
+  output [7:0]probe_out2;
+  output [31:0]probe_out3;
+  output [0:0]probe_out4;
+  output [11:0]probe_out5;
+  output [11:0]probe_out6;
+  output [31:0]probe_out7;
+  output [31:0]probe_out8;
+  output [63:0]probe_out9;
+  output [4:0]probe_out10;
+  output [0:0]probe_out11;
+endmodule

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/vio_rf_test_stub.vhdl

@@ -0,0 +1,42 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+-- Date        : Thu May 18 12:54:39 2023
+-- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
+-- Command     : write_vhdl -force -mode synth_stub
+--               /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_stub.vhdl
+-- Design      : vio_rf_test
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7z100ffg900-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity vio_rf_test is
+  Port ( 
+    clk : in STD_LOGIC;
+    probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
+    probe_out1 : out STD_LOGIC_VECTOR ( 7 downto 0 );
+    probe_out2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
+    probe_out3 : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    probe_out4 : out STD_LOGIC_VECTOR ( 0 to 0 );
+    probe_out5 : out STD_LOGIC_VECTOR ( 11 downto 0 );
+    probe_out6 : out STD_LOGIC_VECTOR ( 11 downto 0 );
+    probe_out7 : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    probe_out8 : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    probe_out9 : out STD_LOGIC_VECTOR ( 63 downto 0 );
+    probe_out10 : out STD_LOGIC_VECTOR ( 4 downto 0 );
+    probe_out11 : out STD_LOGIC_VECTOR ( 0 to 0 )
+  );
+
+end vio_rf_test;
+
+architecture stub of vio_rf_test is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[0:0],probe_out1[7:0],probe_out2[7:0],probe_out3[31:0],probe_out4[0:0],probe_out5[11:0],probe_out6[11:0],probe_out7[31:0],probe_out8[31:0],probe_out9[63:0],probe_out10[4:0],probe_out11[0:0]";
+attribute X_CORE_INFO : string;
+attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
+begin
+end;

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/mem_init_files/freq_word.coe

@@ -0,0 +1,83 @@
+MEMORY_INITIALIZATION_RADIX = 10;
+MEMORY_INITIALIZATION_VECTOR =
+1624,
+1611,
+1598,
+1585,
+1572,
+1559,
+1546,
+1533,
+1520,
+1507,
+1494,
+1481,
+1468,
+1455,
+1442,
+1429,
+1416,
+1403,
+1390,
+1377,
+1364,
+1351,
+1338,
+1325,
+1312,
+1299,
+1286,
+1273,
+1260,
+1247,
+1234,
+1221,
+1208,
+1195,
+1182,
+1169,
+1156,
+1143,
+1130,
+1117,
+1104,
+1091,
+1078,
+1065,
+1052,
+1039,
+1026,
+1013,
+1000,
+987,
+974,
+961,
+948,
+935,
+922,
+909,
+896,
+883,
+870,
+857,
+844,
+831,
+818,
+805,
+792,
+779,
+766,
+753,
+740,
+727,
+714,
+701,
+688,
+675,
+662,
+649,
+636,
+623,
+610,
+597,
+584,

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/mem_init_files/rom_freq_word.mif

@@ -0,0 +1,81 @@
+11001011000
+11001001011
+11000111110
+11000110001
+11000100100
+11000010111
+11000001010
+10111111101
+10111110000
+10111100011
+10111010110
+10111001001
+10110111100
+10110101111
+10110100010
+10110010101
+10110001000
+10101111011
+10101101110
+10101100001
+10101010100
+10101000111
+10100111010
+10100101101
+10100100000
+10100010011
+10100000110
+10011111001
+10011101100
+10011011111
+10011010010
+10011000101
+10010111000
+10010101011
+10010011110
+10010010001
+10010000100
+10001110111
+10001101010
+10001011101
+10001010000
+10001000011
+10000110110
+10000101001
+10000011100
+10000001111
+10000000010
+01111110101
+01111101000
+01111011011
+01111001110
+01111000001
+01110110100
+01110100111
+01110011010
+01110001101
+01110000000
+01101110011
+01101100110
+01101011001
+01101001100
+01100111111
+01100110010
+01100100101
+01100011000
+01100001011
+01011111110
+01011110001
+01011100100
+01011010111
+01011001010
+01010111101
+01010110000
+01010100011
+01010010110
+01010001001
+01001111100
+01001101111
+01001100010
+01001010101
+01001001000

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/README.txt

@@ -0,0 +1,83 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required
+#             to simulate the design for a simulator, the directory structure
+#             and the generated exported files.
+#
+################################################################################
+
+1. Simulate Design
+
+To simulate design, cd to the simulator directory and execute the script.
+
+For example:-
+
+% cd questa
+% ./top.sh
+
+The export simulation flow requires the Xilinx pre-compiled simulation library
+components for the target simulator. These components are referred using the
+'-lib_map_path' switch. If this switch is specified, then the export simulation
+will automatically set this library path in the generated script and update,
+copy the simulator setup file(s) in the exported directory.
+
+If '-lib_map_path' is not specified, then the pre-compiled simulation library
+information will not be included in the exported scripts and that may cause
+simulation errors when running this script. Alternatively, you can provide the
+library information using this switch while executing the generated script.
+
+For example:-
+
+% ./top.sh -lib_map_path /design/questa/clibs
+
+Please refer to the generated script header 'Prerequisite' section for more details.
+
+2. Directory Structure
+
+By default, if the -directory switch is not specified, export_simulation will
+create the following directory structure:-
+
+<current_working_directory>/export_sim/<simulator>
+
+For example, if the current working directory is /tmp/test, export_simulation
+will create the following directory path:-
+
+/tmp/test/export_sim/questa
+
+If -directory switch is specified, export_simulation will create a simulator
+sub-directory under the specified directory path.
+
+For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
+command will create the following directory:-
+
+/tmp/test/my_test_area/func_sim/questa
+
+By default, if -simulator is not specified, export_simulation will create a
+simulator sub-directory for each simulator and export the files for each simulator
+in this sub-directory respectively.
+
+IMPORTANT: Please note that the simulation library path must be specified manually
+in the generated script for the respective simulator. Please refer to the generated
+script header 'Prerequisite' section for more details.
+
+3. Exported script and files
+
+Export simulation will create the driver shell script, setup files and copy the
+design sources in the output directory path.
+
+By default, when the -script_name switch is not specified, export_simulation will
+create the following script name:-
+
+<simulation_top>.sh  (Unix)
+When exporting the files for an IP using the -of_objects switch, export_simulation
+will create the following script name:-
+
+<ip-name>.sh  (Unix)
+Export simulation will create the setup files for the target simulator specified
+with the -simulator switch.
+
+For example, if the target simulator is "ies", export_simulation will create the
+'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
+file.
+

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/activehdl/README.txt

@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Thu Apr 13 10:59:39 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./fifo_48m_to_122p88m.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './fifo_48m_to_122p88m.sh' script.
+
+./fifo_48m_to_122p88m.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./fifo_48m_to_122p88m.sh -noclean_files
+
+For more information on the script, please type './fifo_48m_to_122p88m.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/activehdl/compile.do

@@ -0,0 +1,33 @@
+vlib work
+vlib activehdl
+
+vlib activehdl/xil_defaultlib
+vlib activehdl/xpm
+vlib activehdl/fifo_generator_v13_2_4
+
+vmap xil_defaultlib activehdl/xil_defaultlib
+vmap xpm activehdl/xpm
+vmap fifo_generator_v13_2_4 activehdl/fifo_generator_v13_2_4
+
+vlog -work xil_defaultlib  -sv2k12 \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work fifo_generator_v13_2_4  -v2k5 \
+"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \
+
+vcom -work fifo_generator_v13_2_4 -93 \
+"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \
+
+vlog -work fifo_generator_v13_2_4  -v2k5 \
+"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \
+
+vlog -work xil_defaultlib  -v2k5 \
+"../../../ip/fifo_48m_to_122p88m/sim/fifo_48m_to_122p88m.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/activehdl/fifo_48m_to_122p88m.sh

@@ -0,0 +1,152 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : fifo_48m_to_122p88m.sh
+# Simulator   : Aldec Active-HDL Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Thu Apr 13 10:59:39 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: fifo_48m_to_122p88m.sh [-help]
+# usage: fifo_48m_to_122p88m.sh [-lib_map_path]
+# usage: fifo_48m_to_122p88m.sh [-noclean_files]
+# usage: fifo_48m_to_122p88m.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'fifo_48m_to_122p88m.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "fifo_48m_to_122p88m.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./fifo_48m_to_122p88m.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  lib_map_path=""
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./fifo_48m_to_122p88m.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: fifo_48m_to_122p88m.sh [-help]\n\
+Usage: fifo_48m_to_122p88m.sh [-lib_map_path]\n\
+Usage: fifo_48m_to_122p88m.sh [-reset_run]\n\
+Usage: fifo_48m_to_122p88m.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/activehdl/file_info.txt

@@ -0,0 +1,8 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/simulation/fifo_generator_vlog_beh.v,
+fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd,
+fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v,
+fifo_48m_to_122p88m.v,verilog,xil_defaultlib,../../../ip/fifo_48m_to_122p88m/sim/fifo_48m_to_122p88m.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/activehdl/glbl.v

@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/activehdl/simulate.do

@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim -t 1ps +access +r +m+fifo_48m_to_122p88m -L xil_defaultlib -L xpm -L fifo_generator_v13_2_4 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.fifo_48m_to_122p88m xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {fifo_48m_to_122p88m.udo}
+
+run -all
+
+endsim
+
+quit -force

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/activehdl/wave.do

@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/ies/README.txt

@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Thu Apr 13 10:59:39 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./fifo_48m_to_122p88m.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './fifo_48m_to_122p88m.sh' script.
+
+./fifo_48m_to_122p88m.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./fifo_48m_to_122p88m.sh -noclean_files
+
+For more information on the script, please type './fifo_48m_to_122p88m.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/ies/fifo_48m_to_122p88m.sh

@@ -0,0 +1,175 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : fifo_48m_to_122p88m.sh
+# Simulator   : Cadence Incisive Enterprise Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Thu Apr 13 10:59:39 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: fifo_48m_to_122p88m.sh [-help]
+# usage: fifo_48m_to_122p88m.sh [-lib_map_path]
+# usage: fifo_48m_to_122p88m.sh [-noclean_files]
+# usage: fifo_48m_to_122p88m.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'fifo_48m_to_122p88m.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xil_defaultlib xpm fifo_generator_v13_2_4)
+
+# Simulation root library directory
+sim_lib_dir="ies_lib"
+
+# Script info
+echo -e "fifo_48m_to_122p88m.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  irun $irun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.fifo_48m_to_122p88m \
+       -f run.f \
+       -top glbl \
+       glbl.v
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./fifo_48m_to_122p88m.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./fifo_48m_to_122p88m.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: fifo_48m_to_122p88m.sh [-help]\n\
+Usage: fifo_48m_to_122p88m.sh [-lib_map_path]\n\
+Usage: fifo_48m_to_122p88m.sh [-reset_run]\n\
+Usage: fifo_48m_to_122p88m.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/ies/file_info.txt

@@ -0,0 +1,8 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/simulation/fifo_generator_vlog_beh.v,
+fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd,
+fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v,
+fifo_48m_to_122p88m.v,verilog,xil_defaultlib,../../../ip/fifo_48m_to_122p88m/sim/fifo_48m_to_122p88m.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/ies/glbl.v

@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/ies/run.f

@@ -0,0 +1,23 @@
+-makelib ies_lib/xil_defaultlib -sv \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+-endlib
+-makelib ies_lib/xpm \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib ies_lib/fifo_generator_v13_2_4 \
+  "../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \
+-endlib
+-makelib ies_lib/fifo_generator_v13_2_4 \
+  "../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \
+-endlib
+-makelib ies_lib/fifo_generator_v13_2_4 \
+  "../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../ip/fifo_48m_to_122p88m/sim/fifo_48m_to_122p88m.v" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  glbl.v
+-endlib
+

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/modelsim/README.txt

@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Thu Apr 13 10:59:39 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./fifo_48m_to_122p88m.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './fifo_48m_to_122p88m.sh' script.
+
+./fifo_48m_to_122p88m.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./fifo_48m_to_122p88m.sh -noclean_files
+
+For more information on the script, please type './fifo_48m_to_122p88m.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/modelsim/compile.do

@@ -0,0 +1,33 @@
+vlib modelsim_lib/work
+vlib modelsim_lib/msim
+
+vlib modelsim_lib/msim/xil_defaultlib
+vlib modelsim_lib/msim/xpm
+vlib modelsim_lib/msim/fifo_generator_v13_2_4
+
+vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
+vmap xpm modelsim_lib/msim/xpm
+vmap fifo_generator_v13_2_4 modelsim_lib/msim/fifo_generator_v13_2_4
+
+vlog -work xil_defaultlib -64 -incr -sv \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -64 -93 \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work fifo_generator_v13_2_4 -64 -incr \
+"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \
+
+vcom -work fifo_generator_v13_2_4 -64 -93 \
+"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \
+
+vlog -work fifo_generator_v13_2_4 -64 -incr \
+"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \
+
+vlog -work xil_defaultlib -64 -incr \
+"../../../ip/fifo_48m_to_122p88m/sim/fifo_48m_to_122p88m.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/modelsim/fifo_48m_to_122p88m.sh

@@ -0,0 +1,168 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : fifo_48m_to_122p88m.sh
+# Simulator   : Mentor Graphics ModelSim Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Thu Apr 13 10:59:39 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: fifo_48m_to_122p88m.sh [-help]
+# usage: fifo_48m_to_122p88m.sh [-lib_map_path]
+# usage: fifo_48m_to_122p88m.sh [-noclean_files]
+# usage: fifo_48m_to_122p88m.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'fifo_48m_to_122p88m.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "fifo_48m_to_122p88m.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./fifo_48m_to_122p88m.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
+  if [[ ($1 != "" && -e $1) ]]; then
+    lib_map_path="$1"
+  else
+    echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="modelsim_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./fifo_48m_to_122p88m.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: fifo_48m_to_122p88m.sh [-help]\n\
+Usage: fifo_48m_to_122p88m.sh [-lib_map_path]\n\
+Usage: fifo_48m_to_122p88m.sh [-reset_run]\n\
+Usage: fifo_48m_to_122p88m.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/modelsim/file_info.txt

@@ -0,0 +1,8 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/simulation/fifo_generator_vlog_beh.v,
+fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd,
+fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v,
+fifo_48m_to_122p88m.v,verilog,xil_defaultlib,../../../ip/fifo_48m_to_122p88m/sim/fifo_48m_to_122p88m.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/modelsim/glbl.v

@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/modelsim/simulate.do

@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L xpm -L fifo_generator_v13_2_4 -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.fifo_48m_to_122p88m xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {fifo_48m_to_122p88m.udo}
+
+run -all
+
+quit -force

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/modelsim/wave.do

@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/questa/README.txt

@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Thu Apr 13 10:59:39 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./fifo_48m_to_122p88m.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './fifo_48m_to_122p88m.sh' script.
+
+./fifo_48m_to_122p88m.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./fifo_48m_to_122p88m.sh -noclean_files
+
+For more information on the script, please type './fifo_48m_to_122p88m.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/questa/compile.do

@@ -0,0 +1,33 @@
+vlib questa_lib/work
+vlib questa_lib/msim
+
+vlib questa_lib/msim/xil_defaultlib
+vlib questa_lib/msim/xpm
+vlib questa_lib/msim/fifo_generator_v13_2_4
+
+vmap xil_defaultlib questa_lib/msim/xil_defaultlib
+vmap xpm questa_lib/msim/xpm
+vmap fifo_generator_v13_2_4 questa_lib/msim/fifo_generator_v13_2_4
+
+vlog -work xil_defaultlib -64 -sv \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -64 -93 \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work fifo_generator_v13_2_4 -64 \
+"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \
+
+vcom -work fifo_generator_v13_2_4 -64 -93 \
+"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \
+
+vlog -work fifo_generator_v13_2_4 -64 \
+"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \
+
+vlog -work xil_defaultlib -64 \
+"../../../ip/fifo_48m_to_122p88m/sim/fifo_48m_to_122p88m.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/questa/elaborate.do

@@ -0,0 +1 @@
+vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L fifo_generator_v13_2_4 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.fifo_48m_to_122p88m xil_defaultlib.glbl -o fifo_48m_to_122p88m_opt

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/questa/fifo_48m_to_122p88m.sh

@@ -0,0 +1,173 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : fifo_48m_to_122p88m.sh
+# Simulator   : Mentor Graphics Questa Advanced Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Thu Apr 13 10:59:39 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: fifo_48m_to_122p88m.sh [-help]
+# usage: fifo_48m_to_122p88m.sh [-lib_map_path]
+# usage: fifo_48m_to_122p88m.sh [-noclean_files]
+# usage: fifo_48m_to_122p88m.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'fifo_48m_to_122p88m.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "fifo_48m_to_122p88m.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  source elaborate.do 2>&1 | tee -a elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./fifo_48m_to_122p88m.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  lib_map_path=""
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="questa_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./fifo_48m_to_122p88m.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: fifo_48m_to_122p88m.sh [-help]\n\
+Usage: fifo_48m_to_122p88m.sh [-lib_map_path]\n\
+Usage: fifo_48m_to_122p88m.sh [-reset_run]\n\
+Usage: fifo_48m_to_122p88m.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/questa/file_info.txt

@@ -0,0 +1,8 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/simulation/fifo_generator_vlog_beh.v,
+fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd,
+fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v,
+fifo_48m_to_122p88m.v,verilog,xil_defaultlib,../../../ip/fifo_48m_to_122p88m/sim/fifo_48m_to_122p88m.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/questa/glbl.v

@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/questa/simulate.do

@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -t 1ps -lib xil_defaultlib fifo_48m_to_122p88m_opt
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {fifo_48m_to_122p88m.udo}
+
+run -all
+
+quit -force

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/questa/wave.do

@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/riviera/README.txt

@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Thu Apr 13 10:59:39 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./fifo_48m_to_122p88m.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './fifo_48m_to_122p88m.sh' script.
+
+./fifo_48m_to_122p88m.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./fifo_48m_to_122p88m.sh -noclean_files
+
+For more information on the script, please type './fifo_48m_to_122p88m.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/riviera/compile.do

@@ -0,0 +1,33 @@
+vlib work
+vlib riviera
+
+vlib riviera/xil_defaultlib
+vlib riviera/xpm
+vlib riviera/fifo_generator_v13_2_4
+
+vmap xil_defaultlib riviera/xil_defaultlib
+vmap xpm riviera/xpm
+vmap fifo_generator_v13_2_4 riviera/fifo_generator_v13_2_4
+
+vlog -work xil_defaultlib  -sv2k12 \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work fifo_generator_v13_2_4  -v2k5 \
+"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \
+
+vcom -work fifo_generator_v13_2_4 -93 \
+"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \
+
+vlog -work fifo_generator_v13_2_4  -v2k5 \
+"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \
+
+vlog -work xil_defaultlib  -v2k5 \
+"../../../ip/fifo_48m_to_122p88m/sim/fifo_48m_to_122p88m.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/riviera/fifo_48m_to_122p88m.sh

@@ -0,0 +1,152 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : fifo_48m_to_122p88m.sh
+# Simulator   : Aldec Riviera-PRO Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Thu Apr 13 10:59:39 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: fifo_48m_to_122p88m.sh [-help]
+# usage: fifo_48m_to_122p88m.sh [-lib_map_path]
+# usage: fifo_48m_to_122p88m.sh [-noclean_files]
+# usage: fifo_48m_to_122p88m.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'fifo_48m_to_122p88m.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "fifo_48m_to_122p88m.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./fifo_48m_to_122p88m.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  lib_map_path=""
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./fifo_48m_to_122p88m.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: fifo_48m_to_122p88m.sh [-help]\n\
+Usage: fifo_48m_to_122p88m.sh [-lib_map_path]\n\
+Usage: fifo_48m_to_122p88m.sh [-reset_run]\n\
+Usage: fifo_48m_to_122p88m.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/riviera/file_info.txt

@@ -0,0 +1,8 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/simulation/fifo_generator_vlog_beh.v,
+fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd,
+fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v,
+fifo_48m_to_122p88m.v,verilog,xil_defaultlib,../../../ip/fifo_48m_to_122p88m/sim/fifo_48m_to_122p88m.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v