remove lcmv from dl814_k7_online_acq; add phase comp to dl814_k7_cal_coarse

projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Wed May 17 22:20:39 CST 2023
+# Generated by export_simulation on Sun May 21 16:31:40 CST 2023
 #
 ################################################################################
 

projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/compile.do

@@ -8,7 +8,6 @@ vmap xil_defaultlib activehdl/xil_defaultlib
 vmap xpm activehdl/xpm
 
 vlog -work xil_defaultlib  -sv2k12 "+incdir+../../../ip/vio_phase_comp/hdl/verilog" "+incdir+../../../ip/vio_phase_comp/hdl" \
-"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
 "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
 
 vcom -work xpm -93 \
@@ -17,6 +16,7 @@ vcom -work xpm -93 \
 vlog -work xil_defaultlib  -v2k5 "+incdir+../../../ip/vio_phase_comp/hdl/verilog" "+incdir+../../../ip/vio_phase_comp/hdl" \
 "../../../ip/vio_phase_comp/sim/vio_phase_comp.v" \
 
+
 vlog -work xil_defaultlib \
 "glbl.v"
 

projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/file_info.txt

@@ -1,4 +1,3 @@
-xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
 xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
 xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
 vio_phase_comp.v,verilog,xil_defaultlib,../../../ip/vio_phase_comp/sim/vio_phase_comp.v,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"

projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/vio_phase_comp.sh

@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Wed May 17 22:20:39 CST 2023
+# Generated by Vivado on Sun May 21 16:31:40 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 

projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/ies/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Wed May 17 22:20:39 CST 2023
+# Generated by export_simulation on Sun May 21 16:31:40 CST 2023
 #
 ################################################################################
 

projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/ies/file_info.txt

@@ -1,4 +1,3 @@
-xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
 xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
 xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
 vio_phase_comp.v,verilog,xil_defaultlib,../../../ip/vio_phase_comp/sim/vio_phase_comp.v,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"

projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/ies/run.f

@@ -1,5 +1,4 @@
 -makelib ies_lib/xil_defaultlib -sv \
-  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
   "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
 -endlib
 -makelib ies_lib/xpm \

projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/ies/vio_phase_comp.sh

@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Wed May 17 22:20:39 CST 2023
+# Generated by Vivado on Sun May 21 16:31:40 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 

projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Wed May 17 22:20:39 CST 2023
+# Generated by export_simulation on Sun May 21 16:31:40 CST 2023
 #
 ################################################################################
 

projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/compile.do

@@ -7,15 +7,15 @@ vlib modelsim_lib/msim/xpm
 vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
 vmap xpm modelsim_lib/msim/xpm
 
-vlog -work xil_defaultlib -64 -incr -sv "+incdir+../../../ip/vio_hop/hdl/verilog" "+incdir+../../../ip/vio_hop/hdl" \
+vlog -work xil_defaultlib -64 -incr -sv "+incdir+../../../ip/vio_phase_comp/hdl/verilog" "+incdir+../../../ip/vio_phase_comp/hdl" \
-"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
 "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
 
 vcom -work xpm -64 -93 \
 "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
 
-vlog -work xil_defaultlib -64 -incr "+incdir+../../../ip/vio_hop/hdl/verilog" "+incdir+../../../ip/vio_hop/hdl" \
+vlog -work xil_defaultlib -64 -incr "+incdir+../../../ip/vio_phase_comp/hdl/verilog" "+incdir+../../../ip/vio_phase_comp/hdl" \
-"../../../ip/vio_hop/sim/vio_hop.v" \
+"../../../ip/vio_phase_comp/sim/vio_phase_comp.v" \
+
 
 vlog -work xil_defaultlib \
 "glbl.v"

projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/file_info.txt

@@ -1,4 +1,3 @@
-xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
 xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
 xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
 vio_phase_comp.v,verilog,xil_defaultlib,../../../ip/vio_phase_comp/sim/vio_phase_comp.v,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"

projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/simulate.do

@@ -1,7 +1,7 @@
 onbreak {quit -f}
 onerror {quit -f}
 
-vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.vio_hop xil_defaultlib.glbl
+vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.vio_phase_comp xil_defaultlib.glbl
 
 do {wave.do}
 
@@ -9,7 +9,7 @@ view wave
 view structure
 view signals
 
-do {vio_hop.udo}
+do {vio_phase_comp.udo}
 
 run -all
 

projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/vio_phase_comp.sh

@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Wed May 17 22:20:39 CST 2023
+# Generated by Vivado on Sun May 21 16:31:40 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
@@ -95,10 +95,11 @@ setup()
 copy_setup_file()
 {
   file="modelsim.ini"
-  if [[ ($1 != "") ]]; then
+  lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
+  if [[ ($1 != "" && -e $1) ]]; then
     lib_map_path="$1"
   else
-    lib_map_path="/home/josh/Software/Xilinx/CompLib/Model/2019.1"
+    echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
   fi
   if [[ ($lib_map_path != "") ]]; then
     src_file="$lib_map_path/$file"

projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Wed May 17 22:20:39 CST 2023
+# Generated by export_simulation on Sun May 21 16:31:40 CST 2023
 #
 ################################################################################
 

projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/compile.do

@@ -8,7 +8,6 @@ vmap xil_defaultlib questa_lib/msim/xil_defaultlib
 vmap xpm questa_lib/msim/xpm
 
 vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/vio_phase_comp/hdl/verilog" "+incdir+../../../ip/vio_phase_comp/hdl" \
-"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
 "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
 
 vcom -work xpm -64 -93 \
@@ -17,6 +16,7 @@ vcom -work xpm -64 -93 \
 vlog -work xil_defaultlib -64 "+incdir+../../../ip/vio_phase_comp/hdl/verilog" "+incdir+../../../ip/vio_phase_comp/hdl" \
 "../../../ip/vio_phase_comp/sim/vio_phase_comp.v" \
 
+
 vlog -work xil_defaultlib \
 "glbl.v"
 

projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/file_info.txt

@@ -1,4 +1,3 @@
-xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
 xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
 xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
 vio_phase_comp.v,verilog,xil_defaultlib,../../../ip/vio_phase_comp/sim/vio_phase_comp.v,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"

projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/vio_phase_comp.sh

@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Wed May 17 22:20:39 CST 2023
+# Generated by Vivado on Sun May 21 16:31:40 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
@@ -102,10 +102,9 @@ setup()
 copy_setup_file()
 {
   file="modelsim.ini"
+  lib_map_path=""
   if [[ ($1 != "") ]]; then
     lib_map_path="$1"
-  else
-    lib_map_path="/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa"
   fi
   if [[ ($lib_map_path != "") ]]; then
     src_file="$lib_map_path/$file"

projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Wed May 17 22:20:39 CST 2023
+# Generated by export_simulation on Sun May 21 16:31:40 CST 2023
 #
 ################################################################################
 

projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/compile.do

@@ -8,7 +8,6 @@ vmap xil_defaultlib riviera/xil_defaultlib
 vmap xpm riviera/xpm
 
 vlog -work xil_defaultlib  -sv2k12 "+incdir+../../../ip/vio_phase_comp/hdl/verilog" "+incdir+../../../ip/vio_phase_comp/hdl" \
-"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
 "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
 
 vcom -work xpm -93 \
@@ -17,6 +16,7 @@ vcom -work xpm -93 \
 vlog -work xil_defaultlib  -v2k5 "+incdir+../../../ip/vio_phase_comp/hdl/verilog" "+incdir+../../../ip/vio_phase_comp/hdl" \
 "../../../ip/vio_phase_comp/sim/vio_phase_comp.v" \
 
+
 vlog -work xil_defaultlib \
 "glbl.v"
 

projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/file_info.txt

@@ -0,0 +1,4 @@
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
+xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
+vio_phase_comp.v,verilog,xil_defaultlib,../../../ip/vio_phase_comp/sim/vio_phase_comp.v,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
+glbl.v,Verilog,xil_defaultlib,glbl.v

projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/vio_phase_comp.sh

@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Wed May 17 22:20:39 CST 2023
+# Generated by Vivado on Sun May 21 16:31:40 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
@@ -93,10 +93,9 @@ setup()
 map_setup_file()
 {
   file="library.cfg"
+  lib_map_path=""
   if [[ ($1 != "") ]]; then
     lib_map_path="$1"
-  else
-    lib_map_path="/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera"
   fi
   if [[ ($lib_map_path != "") ]]; then
     src_file="$lib_map_path/$file"

projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/vcs/README.txt

@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Sun May 21 16:31:40 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./vio_phase_comp.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './vio_phase_comp.sh' script.
+
+./vio_phase_comp.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./vio_phase_comp.sh -noclean_files
+
+For more information on the script, please type './vio_phase_comp.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/vcs/file_info.txt

@@ -0,0 +1,4 @@
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
+xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
+vio_phase_comp.v,verilog,xil_defaultlib,../../../ip/vio_phase_comp/sim/vio_phase_comp.v,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
+glbl.v,Verilog,xil_defaultlib,glbl.v

projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/vcs/vio_phase_comp.sh

@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Wed May 17 22:20:39 CST 2023
+# Generated by Vivado on Sun May 21 16:31:40 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
@@ -48,7 +48,7 @@ vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log"
 vcs_sim_opts="-ucli -licqueue -l simulate.log"
 
 # Design libraries
-design_libs=(xil_defaultlib)
+design_libs=(xil_defaultlib xpm)
 
 # Simulation root library directory
 sim_lib_dir="vcs_lib"
@@ -70,6 +70,14 @@ run()
 compile()
 {
   # Compile design files
+  vlogan -work xil_defaultlib $vlogan_opts -sverilog +incdir+"$ref_dir/../../../ip/vio_phase_comp/hdl/verilog" +incdir+"$ref_dir/../../../ip/vio_phase_comp/hdl" \
+    "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+  2>&1 | tee -a vlogan.log
+
+  vhdlan -work xpm $vhdlan_opts \
+    "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+  2>&1 | tee -a vhdlan.log
+
   vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ip/vio_phase_comp/hdl/verilog" +incdir+"$ref_dir/../../../ip/vio_phase_comp/hdl" \
     "$ref_dir/../../../ip/vio_phase_comp/sim/vio_phase_comp.v" \
   2>&1 | tee -a vlogan.log
@@ -138,10 +146,9 @@ create_lib_mappings()
 
   touch $file
 
+  lib_map_path=""
   if [[ ($1 != "") ]]; then
     lib_map_path="$1"
-  else
-    lib_map_path="/home/josh/Software/Xilinx/CompLib/VCS/2019.1"
   fi
 
   for (( i=0; i<${#design_libs[*]}; i++ )); do

projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xcelium/README.txt

@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Wed May 17 22:20:39 CST 2023
+# Generated by export_simulation on Sun May 21 16:31:40 CST 2023
 #
 ################################################################################
 

projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xcelium/file_info.txt

@@ -0,0 +1,4 @@
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
+xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
+vio_phase_comp.v,verilog,xil_defaultlib,../../../ip/vio_phase_comp/sim/vio_phase_comp.v,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
+glbl.v,Verilog,xil_defaultlib,glbl.v

projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xcelium/run.f

@@ -1,5 +1,4 @@
 -makelib xcelium_lib/xil_defaultlib -sv \
-  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
   "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
 -endlib
 -makelib xcelium_lib/xpm \

projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xcelium/vio_phase_comp.sh

@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Wed May 17 22:20:39 CST 2023
+# Generated by Vivado on Sun May 21 16:31:40 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 

projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xsim/README.txt

@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Sun May 21 16:31:40 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./vio_phase_comp.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './vio_phase_comp.sh' script.
+
+./vio_phase_comp.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./vio_phase_comp.sh -noclean_files
+
+For more information on the script, please type './vio_phase_comp.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xsim/vio_phase_comp.sh

@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Wed May 17 22:20:39 CST 2023
+# Generated by Vivado on Sun May 21 16:31:40 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 

projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf

@@ -1,28 +1,28 @@
 version:1
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projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf

@@ -1,12 +1,12 @@
 version:1
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-eof:78398358
+eof:2577552565

projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc

@@ -1,3 +1,3 @@
 version:1
-6d6f64655f636f756e7465727c4755494d6f6465:11
+6d6f64655f636f756e7465727c4755494d6f6465:12
 eof:

projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml

@@ -3,7 +3,7 @@
 <!--The data in this file is primarily intended for consumption by Xilinx tools.
 The structure and the elements are likely to change over the next few releases.
 This means code written to parse this file will need to be revisited each subsequent release.-->
-<application name="pa" timeStamp="Wed May 17 15:21:38 2023">
+<application name="pa" timeStamp="Sun May 21 16:32:31 2023">
 <section name="Project Information" visible="false">
 <property name="ProjectID" value="ce818763e31a4de8ac7850431f15fb5a" type="ProjectID"/>
 <property name="ProjectIteration" value="1" type="ProjectIteration"/>
@@ -17,49 +17,49 @@ This means code written to parse this file will need to be revisited each subseq
 <property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
 </item>
 <item name="Java Command Handlers">
-<property name="AddExistingIPHandler" value="3" type="JavaHandler"/>
+<property name="AddExistingIPHandler" value="4" type="JavaHandler"/>
-<property name="CloseProject" value="4" type="JavaHandler"/>
+<property name="CloseProject" value="5" type="JavaHandler"/>
 <property name="CopyIPHandler" value="3" type="JavaHandler"/>
 <property name="CustomizeCore" value="1" type="JavaHandler"/>
 <property name="EditDelete" value="6" type="JavaHandler"/>
-<property name="ManageCompositeTargets" value="2" type="JavaHandler"/>
+<property name="ManageCompositeTargets" value="3" type="JavaHandler"/>
 <property name="NewIPLocationHandler" value="1" type="JavaHandler"/>
-<property name="OpenIPLocationHandler" value="2" type="JavaHandler"/>
+<property name="OpenIPLocationHandler" value="3" type="JavaHandler"/>
 <property name="OpenPreviousIPHandler" value="9" type="JavaHandler"/>
 <property name="RecustomizeCore" value="20" type="JavaHandler"/>
 </item>
 <item name="Gui Handlers">
 <property name="BaseDialog_CANCEL" value="10" type="GuiHandlerData"/>
-<property name="BaseDialog_OK" value="28" type="GuiHandlerData"/>
+<property name="BaseDialog_OK" value="30" type="GuiHandlerData"/>
 <property name="CopyIPHandler_DESTINATION_IP_NAME" value="3" type="GuiHandlerData"/>
 <property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="4" type="GuiHandlerData"/>
 <property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="10" type="GuiHandlerData"/>
-<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="102" type="GuiHandlerData"/>
+<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="104" type="GuiHandlerData"/>
-<property name="GettingStartedView_MANAGE_IP" value="3" type="GuiHandlerData"/>
+<property name="GettingStartedView_MANAGE_IP" value="4" type="GuiHandlerData"/>
 <property name="GettingStartedView_START_USING_VIVADO_WITH_IP_CATALOG" value="1" type="GuiHandlerData"/>
 <property name="HACGCCoeFileWidget_BROWSE" value="1" type="GuiHandlerData"/>
 <property name="HJFileChooserHelpers_JUMP_TO_RECENT_PROJECT_DIRECTORY" value="1" type="GuiHandlerData"/>
 <property name="IPCoreView_TABBED_PANE" value="2" type="GuiHandlerData"/>
-<property name="MainMenuMgr_FILE" value="8" type="GuiHandlerData"/>
+<property name="MainMenuMgr_FILE" value="10" type="GuiHandlerData"/>
 <property name="MainMenuMgr_OPEN_RECENT_PROJECT" value="2" type="GuiHandlerData"/>
-<property name="MainMenuMgr_PROJECT" value="5" type="GuiHandlerData"/>
+<property name="MainMenuMgr_PROJECT" value="6" type="GuiHandlerData"/>
 <property name="NewIPProjectWizard_IP_LOCATION" value="1" type="GuiHandlerData"/>
 <property name="NewIPProjectWizard_PART" value="1" type="GuiHandlerData"/>
-<property name="PACommandNames_ADD_EXISTING_IP" value="3" type="GuiHandlerData"/>
+<property name="PACommandNames_ADD_EXISTING_IP" value="4" type="GuiHandlerData"/>
-<property name="PACommandNames_CLOSE_PROJECT" value="4" type="GuiHandlerData"/>
+<property name="PACommandNames_CLOSE_PROJECT" value="5" type="GuiHandlerData"/>
 <property name="PACommandNames_COPY_IP" value="3" type="GuiHandlerData"/>
-<property name="PACommandNames_GENERATE_COMPOSITE_FILE" value="2" type="GuiHandlerData"/>
+<property name="PACommandNames_GENERATE_COMPOSITE_FILE" value="3" type="GuiHandlerData"/>
-<property name="PACommandNames_OPEN_IP_LOCATION" value="2" type="GuiHandlerData"/>
+<property name="PACommandNames_OPEN_IP_LOCATION" value="3" type="GuiHandlerData"/>
 <property name="RemoveSourcesDialog_ALSO_DELETE" value="6" type="GuiHandlerData"/>
-<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="14" type="GuiHandlerData"/>
+<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="15" type="GuiHandlerData"/>
-<property name="SrcChooserPanel_ADD_CONFIGURABLE_IP_FILES" value="4" type="GuiHandlerData"/>
+<property name="SrcChooserPanel_ADD_CONFIGURABLE_IP_FILES" value="5" type="GuiHandlerData"/>
-<property name="SrcMenu_IP_DOCUMENTATION" value="4" type="GuiHandlerData"/>
+<property name="SrcMenu_IP_DOCUMENTATION" value="5" type="GuiHandlerData"/>
 <property name="SyntheticaGettingStartedView_RECENT_IP_LOCATIONS" value="9" type="GuiHandlerData"/>
 </item>
 <item name="Other">
-<property name="GuiMode" value="136" type="GuiMode"/>
+<property name="GuiMode" value="144" type="GuiMode"/>
 <property name="BatchMode" value="0" type="BatchMode"/>
-<property name="TclMode" value="96" type="TclMode"/>
+<property name="TclMode" value="101" type="TclMode"/>
 </item>
 </section>
 </application>

projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/gen_run.xml

@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="rom_hop_data_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681709915">
-  <File Type="RDS-UTIL" Name="rom_hop_data_utilization_synth.rpt"/>
   <File Type="RDS-UTIL-PB" Name="rom_hop_data_utilization_synth.pb"/>
+  <File Type="RDS-UTIL" Name="rom_hop_data_utilization_synth.rpt"/>
   <File Type="RDS-RDS" Name="rom_hop_data.vds"/>
   <File Type="RDS-DCP" Name="rom_hop_data.dcp"/>
   <File Type="PA-TCL" Name="rom_hop_data.tcl"/>

projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/gen_run.xml

@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="vio_hop_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681877041">
-  <File Type="RDS-UTIL-PB" Name="vio_hop_utilization_synth.pb"/>
   <File Type="RDS-UTIL" Name="vio_hop_utilization_synth.rpt"/>
+  <File Type="RDS-UTIL-PB" Name="vio_hop_utilization_synth.pb"/>
   <File Type="RDS-RDS" Name="vio_hop.vds"/>
   <File Type="RDS-DCP" Name="vio_hop.dcp"/>
   <File Type="PA-TCL" Name="vio_hop.tcl"/>

projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/gen_run.xml

@@ -1,14 +1,11 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <GenRun Id="vio_manual_ctrl_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1682237933">
-  <File Type="VDS-TIMING-PB" Name="vio_manual_ctrl_timing_summary_synth.pb"/>
+  <File Type="PA-TCL" Name="vio_manual_ctrl.tcl"/>
-  <File Type="VDS-TIMINGSUMMARY" Name="vio_manual_ctrl_timing_summary_synth.rpt"/>
+  <File Type="REPORTS-TCL" Name="vio_manual_ctrl_reports.tcl"/>
+  <File Type="RDS-RDS" Name="vio_manual_ctrl.vds"/>
   <File Type="RDS-DCP" Name="vio_manual_ctrl.dcp"/>
   <File Type="RDS-UTIL-PB" Name="vio_manual_ctrl_utilization_synth.pb"/>
   <File Type="RDS-UTIL" Name="vio_manual_ctrl_utilization_synth.rpt"/>
-  <File Type="RDS-PROPCONSTRS" Name="vio_manual_ctrl_drc_synth.rpt"/>
-  <File Type="RDS-RDS" Name="vio_manual_ctrl.vds"/>
-  <File Type="REPORTS-TCL" Name="vio_manual_ctrl_reports.tcl"/>
-  <File Type="PA-TCL" Name="vio_manual_ctrl.tcl"/>
   <FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_manual_ctrl">
     <File Path="$PPRDIR/../vio_manual_ctrl.xcix">
       <FileInfo>

projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.xpr

@@ -39,13 +39,13 @@
     <Option Name="WTVcsLaunchSim" Val="0"/>
     <Option Name="WTRivieraLaunchSim" Val="0"/>
     <Option Name="WTActivehdlLaunchSim" Val="0"/>
-    <Option Name="WTXSimExportSim" Val="19"/>
+    <Option Name="WTXSimExportSim" Val="20"/>
-    <Option Name="WTModelSimExportSim" Val="19"/>
+    <Option Name="WTModelSimExportSim" Val="20"/>
-    <Option Name="WTQuestaExportSim" Val="19"/>
+    <Option Name="WTQuestaExportSim" Val="20"/>
-    <Option Name="WTIesExportSim" Val="19"/>
+    <Option Name="WTIesExportSim" Val="20"/>
-    <Option Name="WTVcsExportSim" Val="19"/>
+    <Option Name="WTVcsExportSim" Val="20"/>
-    <Option Name="WTRivieraExportSim" Val="19"/>
+    <Option Name="WTRivieraExportSim" Val="20"/>
-    <Option Name="WTActivehdlExportSim" Val="19"/>
+    <Option Name="WTActivehdlExportSim" Val="20"/>
     <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
     <Option Name="XSimRadix" Val="hex"/>
     <Option Name="XSimTimeUnit" Val="ns"/>
@@ -80,6 +80,20 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PPRDIR/../rx_pre_process/vio_phase_comp.xcix">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../rx_pre_process/vio_phase_comp/vio_phase_comp.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
         <Option Name="TopAutoSet" Val="TRUE"/>

projects/dl814_k7/dl814_k7_cal_coarse/project.tcl

@@ -3,7 +3,7 @@
 #
 # project.tcl: Tcl script for re-creating project 'project'
 #
-# Generated by Vivado on Mon Apr 24 11:12:47 CST 2023
+# Generated by Vivado on Sun May 21 17:14:02 CST 2023
 # IP Build 2633630 on Wed Sep  4 12:30:14 MDT 2019
 #
 # This file contains the Vivado Tcl commands for re-creating the project to the state*
@@ -27,6 +27,7 @@
 #
 # 3. The following remote source files that were added to the original project:-
 #
+#    "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/rx_pre_process/vio_phase_comp/vio_phase_comp.xci"
 #    "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/vio_hop/vio_hop.xci"
 #    "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/vio_manual_ctrl/vio_manual_ctrl.xci"
 #    "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/ila_rx_pre_ant/ila_rx_pre_ant.xci"
@@ -46,6 +47,7 @@
 #    "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/fifo_accor_cdc/fifo_accor_cdc.xci"
 #    "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/add_s24_s32_s32/add_s24_s32_s32.xci"
 #    "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/cmpy_12x12/cmpy_12x12.xci"
+#    "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/rotate_16b/rotate_16b.xci"
 #    "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xci"
 #    "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8.xci"
 #    "/home/josh/Workspace/vivado-git/modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci"
@@ -83,6 +85,7 @@
 #    "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/Sisyif_src/fre_caliatt.v"
 #    "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/Sisyif_src/mgc_ctrl.v"
 #    "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/Sisyif_src/mod2_rom.v"
+#    "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/rx_pre_process/phase_comp.v"
 #    "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/rx_pre_process/rx_pre_process.v"
 #    "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/rx_pre_process/rx_pre_test.v"
 #    "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/rtl/rx_pre_process/spatial_filter.v"
@@ -102,7 +105,6 @@
 #    "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/rx_pre_process/coe/one_hop_data.coe"
 #    "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/ant_rf_interface/vio_ant_rd/vio_ant_rd.xci"
 #    "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/atan2_16b/atan2_16b.xci"
-#    "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/rotate_16b/rotate_16b.xci"
 #    "/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/basic_driver/vio_clk_ld_rd/vio_clk_ld_rd.xci"
 #    "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/constraints/k7401t_ad9516_2ad9361_physical.xdc"
 #    "/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/constraints/k7410t_ad9516_2ad9361_timing.xdc"
@@ -217,15 +219,15 @@ set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_use
 set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
 set_property -name "simulator_language" -value "Mixed" -objects $obj
 set_property -name "target_simulator" -value "VCS" -objects $obj
-set_property -name "webtalk.activehdl_export_sim" -value "89" -objects $obj
+set_property -name "webtalk.activehdl_export_sim" -value "90" -objects $obj
-set_property -name "webtalk.ies_export_sim" -value "89" -objects $obj
+set_property -name "webtalk.ies_export_sim" -value "90" -objects $obj
-set_property -name "webtalk.modelsim_export_sim" -value "89" -objects $obj
+set_property -name "webtalk.modelsim_export_sim" -value "90" -objects $obj
 set_property -name "webtalk.modelsim_launch_sim" -value "2" -objects $obj
-set_property -name "webtalk.questa_export_sim" -value "89" -objects $obj
+set_property -name "webtalk.questa_export_sim" -value "90" -objects $obj
-set_property -name "webtalk.riviera_export_sim" -value "89" -objects $obj
+set_property -name "webtalk.riviera_export_sim" -value "90" -objects $obj
-set_property -name "webtalk.vcs_export_sim" -value "89" -objects $obj
+set_property -name "webtalk.vcs_export_sim" -value "90" -objects $obj
 set_property -name "webtalk.vcs_launch_sim" -value "69" -objects $obj
-set_property -name "webtalk.xsim_export_sim" -value "89" -objects $obj
+set_property -name "webtalk.xsim_export_sim" -value "90" -objects $obj
 set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj
 
 # Create 'sources_1' fileset (if not found)
@@ -243,6 +245,7 @@ update_ip_catalog -rebuild
 # Set 'sources_1' fileset object
 set obj [get_filesets sources_1]
 set files [list \
+ [file normalize "${origin_dir}/ip/rx_pre_process/vio_phase_comp/vio_phase_comp.xci"] \
  [file normalize "${origin_dir}/ip/vio_hop/vio_hop.xci"] \
  [file normalize "${origin_dir}/ip/vio_manual_ctrl/vio_manual_ctrl.xci"] \
  [file normalize "${origin_dir}/../common_ip/rx_pre_process/ila_rx_pre_ant/ila_rx_pre_ant.xci"] \
@@ -262,6 +265,7 @@ set files [list \
  [file normalize "${origin_dir}/../common_ip/rx_pre_process/fifo_accor_cdc/fifo_accor_cdc.xci"] \
  [file normalize "${origin_dir}/../common_ip/rx_pre_process/add_s24_s32_s32/add_s24_s32_s32.xci"] \
  [file normalize "${origin_dir}/../common_ip/rx_pre_process/cmpy_12x12/cmpy_12x12.xci"] \
+ [file normalize "${origin_dir}/../common_ip/rx_pre_process/rotate_16b/rotate_16b.xci"] \
  [file normalize "${origin_dir}/../../../modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xci"] \
  [file normalize "${origin_dir}/../../../modules/xc7k410tffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8.xci"] \
  [file normalize "${origin_dir}/../../../modules/xc7k410tffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci"] \
@@ -299,6 +303,7 @@ set files [list \
  [file normalize "${origin_dir}/rtl/Sisyif_src/fre_caliatt.v"] \
  [file normalize "${origin_dir}/rtl/Sisyif_src/mgc_ctrl.v"] \
  [file normalize "${origin_dir}/rtl/Sisyif_src/mod2_rom.v"] \
+ [file normalize "${origin_dir}/rtl/rx_pre_process/phase_comp.v"] \
  [file normalize "${origin_dir}/rtl/rx_pre_process/rx_pre_process.v"] \
  [file normalize "${origin_dir}/rtl/rx_pre_process/rx_pre_test.v"] \
  [file normalize "${origin_dir}/rtl/rx_pre_process/spatial_filter.v"] \
@@ -318,12 +323,20 @@ set files [list \
  [file normalize "${origin_dir}/ip/rx_pre_process/coe/one_hop_data.coe"] \
  [file normalize "${origin_dir}/../common_ip/ant_rf_interface/vio_ant_rd/vio_ant_rd.xci"] \
  [file normalize "${origin_dir}/../common_ip/rx_pre_process/atan2_16b/atan2_16b.xci"] \
- [file normalize "${origin_dir}/../common_ip/rx_pre_process/rotate_16b/rotate_16b.xci"] \
  [file normalize "${origin_dir}/../common_ip/basic_driver/vio_clk_ld_rd/vio_clk_ld_rd.xci"] \
 ]
 add_files -norecurse -fileset $obj $files
 
 # Set 'sources_1' fileset file properties for remote files
+set file "$origin_dir/ip/rx_pre_process/vio_phase_comp/vio_phase_comp.xci"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
 set file "$origin_dir/ip/vio_hop/vio_hop.xci"
 set file [file normalize $file]
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
@@ -495,6 +508,15 @@ if { ![get_property "is_locked" $file_obj] } {
   set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
 }
 
+set file "$origin_dir/../common_ip/rx_pre_process/rotate_16b/rotate_16b.xci"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
 set file "$origin_dir/../../../modules/xc7k410tffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xci"
 set file [file normalize $file]
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
@@ -608,15 +630,6 @@ if { ![get_property "is_locked" $file_obj] } {
   set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
 }
 
-set file "$origin_dir/../common_ip/rx_pre_process/rotate_16b/rotate_16b.xci"
-set file [file normalize $file]
-set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
-set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
-set_property -name "registered_with_manager" -value "1" -objects $file_obj
-if { ![get_property "is_locked" $file_obj] } {
-  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
-}
-
 set file "$origin_dir/../common_ip/basic_driver/vio_clk_ld_rd/vio_clk_ld_rd.xci"
 set file [file normalize $file]
 set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]

projects/dl814_k7/dl814_k7_cal_coarse/rtl/rx_pre_process/rx_pre_process.v

@@ -48,6 +48,7 @@ module rx_pre_process
     parameter STABLE_CNT_MOD     = 48 ,
     parameter ADC_DATA_WIDTH     = 12 ,
     parameter CHANNEL_NUM        = 4  ,
+    parameter PHASE_WIDTH        = 16 ,
     parameter SNAPSHOT_NUM       = 256,
     parameter PS_PL_WIDTH        = 32 ,
     parameter WEIGHT_TRUNC_WIDTH = 16 ,
@@ -73,6 +74,11 @@ module rx_pre_process
     input [ADC_DATA_WIDTH-1:0] rx_ch3_q     ,
     input [ADC_DATA_WIDTH-1:0] rx_ch4_i     ,
     input [ADC_DATA_WIDTH-1:0] rx_ch4_q     ,
+    // input channel phase
+    input [PHASE_WIDTH-1:0] phase_ch1       ,
+    input [PHASE_WIDTH-1:0] phase_ch2       ,
+    input [PHASE_WIDTH-1:0] phase_ch3       ,
+    input [PHASE_WIDTH-1:0] phase_ch4       ,
 
     // ad9361 calibration interface
     input           ad9361_1_cal_start      ,
@@ -142,6 +148,48 @@ ad9361_phase_cal_coarse u_ad9361_phase_cal
     .rx_cal_ch4_q       (rx_cal_ch4_q       )  // output [ADC_DATA_WIDTH-1:0] rx_cal_ch4_q
 );
 
+
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////// Phase Compensation //////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+// input data
+wire phase_comp_din_valid;
+wire [CHANNEL_NUM*PHASE_WIDTH-1 : 0] phase_comp_phase;
+wire [CHANNEL_NUM*ADC_DATA_WIDTH-1 : 0] phase_comp_din_real;
+wire [CHANNEL_NUM*ADC_DATA_WIDTH-1 : 0] phase_comp_din_imag;
+
+assign phase_comp_din_valid = ad9361_cal_valid;
+assign phase_comp_phase = {phase_ch4, phase_ch3, phase_ch2, phase_ch1};
+assign phase_comp_din_real = {rx_cal_ch4_i, rx_cal_ch3_i, rx_cal_ch2_i, rx_cal_ch1_i};
+assign phase_comp_din_imag = {rx_cal_ch4_q, rx_cal_ch3_q, rx_cal_ch2_q, rx_cal_ch1_q};
+
+// output data
+wire phase_comp_dout_valid;
+wire [CHANNEL_NUM*ADC_DATA_WIDTH-1:0] phase_comp_dout_real;
+wire [CHANNEL_NUM*ADC_DATA_WIDTH-1:0] phase_comp_dout_imag;
+
+phase_comp #(
+    .DATA_WIDTH     (ADC_DATA_WIDTH     ),
+    .CORDIC_WIDTH   (PHASE_WIDTH        ),
+    .CHANNEL_NUM    (CHANNEL_NUM        )
+) u_phase_comp
+(
+    // clock & reset
+    .rst        (sys_clk                ),
+    .clk        (sys_rst                ),
+
+    // input data
+    .din_valid  (phase_comp_din_valid   ),
+    .phase      (phase_comp_phase       ),
+    .din_real   (phase_comp_din_real    ),
+    .din_imag   (phase_comp_din_imag    ),
+
+    // output data
+    .dout_valid (phase_comp_dout_valid  ),
+    .dout_real  (phase_comp_dout_real   ),
+    .dout_imag  (phase_comp_dout_imag   )
+);
+
 ////////////////////////////////////////////////////////////////////////////////
 //////////////////////// Autocorrelation State Machine /////////////////////////
 ////////////////////////////////////////////////////////////////////////////////
@@ -256,8 +304,8 @@ wire [CHANNEL_NUM*ADC_DATA_WIDTH-1 : 0] acorr_din_real;
 wire [CHANNEL_NUM*ADC_DATA_WIDTH-1 : 0] acorr_din_imag;
 
 assign acorr_din_valid = snapshot_valid;
-assign acorr_din_real = {rx_cal_ch4_i, rx_cal_ch3_i, rx_cal_ch2_i, rx_cal_ch1_i};
+assign acorr_din_real = phase_comp_din_real;
-assign acorr_din_imag = {rx_cal_ch4_q, rx_cal_ch3_q, rx_cal_ch2_q, rx_cal_ch1_q};
+assign acorr_din_imag = phase_comp_din_imag;
 
 // output data
 wire acorr_dout_valid;
@@ -435,9 +483,9 @@ wire filter_adc_valid;
 wire [CHANNEL_NUM*ADC_DATA_WIDTH-1 : 0] filter_adc_real;
 wire [CHANNEL_NUM*ADC_DATA_WIDTH-1 : 0] filter_adc_imag;
 
-assign filter_adc_valid = ad9361_cal_valid;
+assign filter_adc_valid = phase_comp_dout_valid;
-assign filter_adc_real = {rx_cal_ch4_i, rx_cal_ch3_i, rx_cal_ch2_i, rx_cal_ch1_i};
+assign filter_adc_real = phase_comp_dout_real;
-assign filter_adc_imag = {rx_cal_ch4_q, rx_cal_ch3_q, rx_cal_ch2_q, rx_cal_ch1_q};
+assign filter_adc_imag = phase_comp_dout_imag;
 
 // output data
 wire filter_dout_valid;

projects/dl814_k7/dl814_k7_cal_coarse/rtl/system_top.v

@@ -566,7 +566,11 @@ wire    [31:0]  freq_set    ;
 wire    [ 1:0]  iq_sel      ;
 wire    [ 3:0]  bb_rshift   ;
 
-tx_qpsk u_tx_qpsk
+tx_qpsk #(
+    .BIT_DATA       (1024'b0000000100100010000011001001101000010010101000011110101110101101101100000000110000011011001100001010110101110001101111110001000111100111101101101000000010100001011010101000111110111100100101100000100110010001010001101101110000001111000111011111110010000110001011011101000011010101100111100101101100100000100010010011000000101100010100111011001110001011111101010001011101101011000011001101101010000011101001111010011010100100111000001111100111001101111010001010101101111100001001110100011101011111011010010000100001010010101100011100111111101100001000110100111001001111000011011101100011000111101111101001001010000001101000110010111010010110100010001011001101001010010001100001110110111100000101110010101110011101110111001100111010101110111101100101000100110110001000011100101111100101001100110010101010011111100110001101011110011010110100110001001011100001011110101010101111111101000001010100101111000101011110111010100110111001000111000111111111100000001110000111111011100010011111000110011111010110010110010010010000000001),
+    .BIT_DATA_LEN   (1024),
+    .CLK_FREQ       (48000000)
+) u_tx_qpsk
 (
     .clk            (sys_clk            ), // input           clk
     .rst            (sys_rst            ), // input           rst
@@ -598,6 +602,11 @@ wire    [11:0]  rx_ch2_i_test, rx_ch2_q_test;
 wire    [11:0]  rx_ch3_i_test, rx_ch3_q_test;
 wire    [11:0]  rx_ch4_i_test, rx_ch4_q_test;
 
+wire    [15:0]  phase_ch1;
+wire    [15:0]  phase_ch2;
+wire    [15:0]  phase_ch3;
+wire    [15:0]  phase_ch4;
+
 wire            rx_data_valid;
 wire    [29:0]  rx_data_i, rx_data_q;
 
@@ -698,6 +707,11 @@ rx_pre_process #(
     .rx_ch3_q           (rx_ch3_q           ),
     .rx_ch4_i           (rx_ch4_i           ),
     .rx_ch4_q           (rx_ch4_q           ),
+    // input channel phase
+    .phase_ch1          (phase_ch1          ),
+    .phase_ch2          (phase_ch2          ),
+    .phase_ch3          (phase_ch3          ),
+    .phase_ch4          (phase_ch4          ),
     // ad9361 calibration interface
     .ad9361_1_cal_start (ad9361_1_cal_start ),
     .ad9361_1_cal_done  (ad9361_1_cal_done  ),
@@ -716,6 +730,21 @@ rx_pre_process #(
     .rx_data_q          (rx_data_q          )  // sync to [sys_clk]
 );
 
+(*dont_touch = "true"*) wire    [11:0]  rx_rot_ch1_i, rx_rot_ch1_q;
+(*dont_touch = "true"*) wire    [11:0]  rx_rot_ch2_i, rx_rot_ch2_q;
+(*dont_touch = "true"*) wire    [11:0]  rx_rot_ch3_i, rx_rot_ch3_q;
+(*dont_touch = "true"*) wire    [11:0]  rx_rot_ch4_i, rx_rot_ch4_q;
+
+assign rx_rot_ch1_i = u_rx_pre_process.phase_comp_dout_real[11: 0];
+assign rx_rot_ch2_i = u_rx_pre_process.phase_comp_dout_real[23:12];
+assign rx_rot_ch3_i = u_rx_pre_process.phase_comp_dout_real[35:24];
+assign rx_rot_ch4_i = u_rx_pre_process.phase_comp_dout_real[47:36];
+
+assign rx_rot_ch1_q = u_rx_pre_process.phase_comp_dout_imag[11: 0];
+assign rx_rot_ch2_q = u_rx_pre_process.phase_comp_dout_imag[23:12];
+assign rx_rot_ch3_q = u_rx_pre_process.phase_comp_dout_imag[35:24];
+assign rx_rot_ch4_q = u_rx_pre_process.phase_comp_dout_imag[47:36];
+
 // temporary test cases
 rx_pre_test u_rx_pre_test
 (
@@ -888,17 +917,17 @@ ila_2x12x131072 u_ila_tx
 
 ila_8x12_2x30_131072 u_ila_rx
 (
-    .clk    (sys_clk                        ), // input wire clk
+    .clk    (sys_clk        ), // input wire clk
-    .probe0 (u_rx_pre_process.rx_cal_ch1_i  ), // input wire [11:0]  probe0
+    .probe0 (rx_rot_ch1_i   ), // input wire [11:0]  probe0
-    .probe1 (u_rx_pre_process.rx_cal_ch1_q  ), // input wire [11:0]  probe1
+    .probe1 (rx_rot_ch1_q   ), // input wire [11:0]  probe1
-    .probe2 (u_rx_pre_process.rx_cal_ch2_i  ), // input wire [11:0]  probe2
+    .probe2 (rx_rot_ch2_i   ), // input wire [11:0]  probe2
-    .probe3 (u_rx_pre_process.rx_cal_ch2_q  ), // input wire [11:0]  probe3
+    .probe3 (rx_rot_ch2_q   ), // input wire [11:0]  probe3
-    .probe4 (u_rx_pre_process.rx_cal_ch3_i  ), // input wire [11:0]  probe4
+    .probe4 (rx_rot_ch3_i   ), // input wire [11:0]  probe4
-    .probe5 (u_rx_pre_process.rx_cal_ch3_q  ), // input wire [11:0]  probe5
+    .probe5 (rx_rot_ch3_q   ), // input wire [11:0]  probe5
-    .probe6 (u_rx_pre_process.rx_cal_ch4_i  ), // input wire [11:0]  probe6
+    .probe6 (rx_rot_ch4_i   ), // input wire [11:0]  probe6
-    .probe7 (u_rx_pre_process.rx_cal_ch4_q  ), // input wire [11:0]  probe7
+    .probe7 (rx_rot_ch4_q   ), // input wire [11:0]  probe7
-    .probe8 (rx_data_i                      ), // input wire [29:0]  probe8
+    .probe8 (rx_data_i      ), // input wire [29:0]  probe8
-    .probe9 (rx_data_q                      )  // input wire [29:0]  probe9
+    .probe9 (rx_data_q      )  // input wire [29:0]  probe9
 );
 
 ila_cal u_ila_cal
@@ -970,4 +999,12 @@ vio_hop u_vio_hop
     .probe_out1 (hop_trigger_en     )  // output wire [0 : 0] probe_out2
 );
 
+vio_phase_comp u_vio_phase_comp
+(
+    .clk        (sys_clk    ), // input wire clk
+    .probe_out0 (phase_ch1  ), // output wire [15 : 0] probe_out0
+    .probe_out1 (phase_ch2  ), // output wire [15 : 0] probe_out1
+    .probe_out2 (phase_ch3  ), // output wire [15 : 0] probe_out2
+    .probe_out3 (phase_ch4  )  // output wire [15 : 0] probe_out3
+);
 endmodule

projects/dl814_k7/dl814_k7_online_acq/constraints/k7410t_ad9516_2ad9361_timing.xdc

@@ -1,4 +1,4 @@
-set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[9]/C}] -to [get_pins u_rx_pre_process/u_ad9361_phase_cal/ad9361_2_cal_start_d1_reg/D]
+set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[9]/C}] -to [get_pins u_ad9361_phase_cal/ad9361_2_cal_start_d1_reg/D]
 set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[7]/C}] -to [get_pins u_tx_pre_process/ad9361_tx_switch_d1_reg/D]
-set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[10]/C}] -to [get_pins u_rx_pre_process/u_ad9361_phase_cal/ad9361_1_cal_start_d1_reg/D]
+set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[10]/C}] -to [get_pins u_ad9361_phase_cal/ad9361_1_cal_start_d1_reg/D]
-set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[8]/C}] -to [get_pins u_rx_pre_process/u_ad9361_phase_cal/ad9361_recal_d1_reg/D]
+set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[8]/C}] -to [get_pins u_ad9361_phase_cal/ad9361_recal_d1_reg/D]

projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_hop_data/rom_hop_data.veo

@@ -1,67 +0,0 @@
-// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
-// 
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-// 
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-// 
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-// 
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-// 
-// DO NOT MODIFY THIS FILE.
-
-// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
-// IP Revision: 3
-
-// The following must be inserted into your Verilog file for this
-// core to be instantiated. Change the instance name and port connections
-// (in parentheses) to your own signal names.
-
-//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
-rom_hop_data your_instance_name (
-  .clka(clka),    // input wire clka
-  .addra(addra),  // input wire [13 : 0] addra
-  .douta(douta)  // output wire [95 : 0] douta
-);
-// INST_TAG_END ------ End INSTANTIATION Template ---------
-
-// You must compile the wrapper file rom_hop_data.v when simulating
-// the core, rom_hop_data. When compiling the wrapper file, be sure to
-// reference the Verilog simulation library.
-

projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_hop_data/rom_hop_data.vho

@@ -1,79 +0,0 @@
--- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
--- 
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
--- 
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
--- 
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
--- 
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
--- 
--- DO NOT MODIFY THIS FILE.
-
--- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
--- IP Revision: 3
-
--- The following code must appear in the VHDL architecture header.
-
-------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
-COMPONENT rom_hop_data
-  PORT (
-    clka : IN STD_LOGIC;
-    addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
-    douta : OUT STD_LOGIC_VECTOR(95 DOWNTO 0)
-  );
-END COMPONENT;
--- COMP_TAG_END ------ End COMPONENT Declaration ------------
-
--- The following code must appear in the VHDL architecture
--- body. Substitute your own instance name and net names.
-
-------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
-your_instance_name : rom_hop_data
-  PORT MAP (
-    clka => clka,
-    addra => addra,
-    douta => douta
-  );
--- INST_TAG_END ------ End INSTANTIATION Template ---------
-
--- You must compile the wrapper file rom_hop_data.vhd when simulating
--- the core, rom_hop_data. When compiling the wrapper file, be sure to
--- reference the VHDL simulation library.
-

projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_hop_data/rom_hop_data_stub.v

@@ -1,22 +0,0 @@
-// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
-// Date        : Mon Apr 17 13:39:39 2023
-// Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
-// Command     : write_verilog -force -mode synth_stub
-//               /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/rom_hop_data_stub.v
-// Design      : rom_hop_data
-// Purpose     : Stub declaration of top-level module interface
-// Device      : xc7k410tffg900-2
-// --------------------------------------------------------------------------------
-
-// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
-// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
-// Please paste the declaration into a Verilog source file or add the file as an additional source.
-(* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *)
-module rom_hop_data(clka, addra, douta)
-/* synthesis syn_black_box black_box_pad_pin="clka,addra[13:0],douta[95:0]" */;
-  input clka;
-  input [13:0]addra;
-  output [95:0]douta;
-endmodule

projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_hop_data/rom_hop_data_stub.vhdl

@@ -1,32 +0,0 @@
--- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
--- --------------------------------------------------------------------------------
--- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
--- Date        : Mon Apr 17 13:39:39 2023
--- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
--- Command     : write_vhdl -force -mode synth_stub
---               /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/rom_hop_data_synth_1/rom_hop_data_stub.vhdl
--- Design      : rom_hop_data
--- Purpose     : Stub declaration of top-level module interface
--- Device      : xc7k410tffg900-2
--- --------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-entity rom_hop_data is
-  Port ( 
-    clka : in STD_LOGIC;
-    addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
-    douta : out STD_LOGIC_VECTOR ( 95 downto 0 )
-  );
-
-end rom_hop_data;
-
-architecture stub of rom_hop_data is
-attribute syn_black_box : boolean;
-attribute black_box_pad_pin : string;
-attribute syn_black_box of stub : architecture is true;
-attribute black_box_pad_pin of stub : architecture is "clka,addra[13:0],douta[95:0]";
-attribute x_core_info : string;
-attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3";
-begin
-end;

projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/rom_hop_data/sim/rom_hop_data.v

@@ -1,211 +0,0 @@
-// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
-// 
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-// 
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-// 
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-// 
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-// 
-// DO NOT MODIFY THIS FILE.
-
-
-// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
-// IP Revision: 3
-
-`timescale 1ns/1ps
-
-(* DowngradeIPIdentifiedWarnings = "yes" *)
-module rom_hop_data (
-  clka,
-  addra,
-  douta
-);
-
-(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
-input wire clka;
-(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
-input wire [13 : 0] addra;
-(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *)
-(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
-output wire [95 : 0] douta;
-
-  blk_mem_gen_v8_4_3 #(
-    .C_FAMILY("kintex7"),
-    .C_XDEVICEFAMILY("kintex7"),
-    .C_ELABORATION_DIR("./"),
-    .C_INTERFACE_TYPE(0),
-    .C_AXI_TYPE(1),
-    .C_AXI_SLAVE_TYPE(0),
-    .C_USE_BRAM_BLOCK(0),
-    .C_ENABLE_32BIT_ADDRESS(0),
-    .C_CTRL_ECC_ALGO("NONE"),
-    .C_HAS_AXI_ID(0),
-    .C_AXI_ID_WIDTH(4),
-    .C_MEM_TYPE(3),
-    .C_BYTE_SIZE(9),
-    .C_ALGORITHM(1),
-    .C_PRIM_TYPE(1),
-    .C_LOAD_INIT_FILE(1),
-    .C_INIT_FILE_NAME("rom_hop_data.mif"),
-    .C_INIT_FILE("rom_hop_data.mem"),
-    .C_USE_DEFAULT_DATA(0),
-    .C_DEFAULT_DATA("0"),
-    .C_HAS_RSTA(0),
-    .C_RST_PRIORITY_A("CE"),
-    .C_RSTRAM_A(0),
-    .C_INITA_VAL("0"),
-    .C_HAS_ENA(0),
-    .C_HAS_REGCEA(0),
-    .C_USE_BYTE_WEA(0),
-    .C_WEA_WIDTH(1),
-    .C_WRITE_MODE_A("WRITE_FIRST"),
-    .C_WRITE_WIDTH_A(96),
-    .C_READ_WIDTH_A(96),
-    .C_WRITE_DEPTH_A(9600),
-    .C_READ_DEPTH_A(9600),
-    .C_ADDRA_WIDTH(14),
-    .C_HAS_RSTB(0),
-    .C_RST_PRIORITY_B("CE"),
-    .C_RSTRAM_B(0),
-    .C_INITB_VAL("0"),
-    .C_HAS_ENB(0),
-    .C_HAS_REGCEB(0),
-    .C_USE_BYTE_WEB(0),
-    .C_WEB_WIDTH(1),
-    .C_WRITE_MODE_B("WRITE_FIRST"),
-    .C_WRITE_WIDTH_B(96),
-    .C_READ_WIDTH_B(96),
-    .C_WRITE_DEPTH_B(9600),
-    .C_READ_DEPTH_B(9600),
-    .C_ADDRB_WIDTH(14),
-    .C_HAS_MEM_OUTPUT_REGS_A(0),
-    .C_HAS_MEM_OUTPUT_REGS_B(0),
-    .C_HAS_MUX_OUTPUT_REGS_A(0),
-    .C_HAS_MUX_OUTPUT_REGS_B(0),
-    .C_MUX_PIPELINE_STAGES(0),
-    .C_HAS_SOFTECC_INPUT_REGS_A(0),
-    .C_HAS_SOFTECC_OUTPUT_REGS_B(0),
-    .C_USE_SOFTECC(0),
-    .C_USE_ECC(0),
-    .C_EN_ECC_PIPE(0),
-    .C_READ_LATENCY_A(1),
-    .C_READ_LATENCY_B(1),
-    .C_HAS_INJECTERR(0),
-    .C_SIM_COLLISION_CHECK("ALL"),
-    .C_COMMON_CLK(0),
-    .C_DISABLE_WARN_BHV_COLL(0),
-    .C_EN_SLEEP_PIN(0),
-    .C_USE_URAM(0),
-    .C_EN_RDADDRA_CHG(0),
-    .C_EN_RDADDRB_CHG(0),
-    .C_EN_DEEPSLEEP_PIN(0),
-    .C_EN_SHUTDOWN_PIN(0),
-    .C_EN_SAFETY_CKT(0),
-    .C_DISABLE_WARN_BHV_RANGE(0),
-    .C_COUNT_36K_BRAM("26"),
-    .C_COUNT_18K_BRAM("1"),
-    .C_EST_POWER_SUMMARY("Estimated Power for IP     :     23.399606 mW")
-  ) inst (
-    .clka(clka),
-    .rsta(1'D0),
-    .ena(1'D0),
-    .regcea(1'D0),
-    .wea(1'B0),
-    .addra(addra),
-    .dina(96'B0),
-    .douta(douta),
-    .clkb(1'D0),
-    .rstb(1'D0),
-    .enb(1'D0),
-    .regceb(1'D0),
-    .web(1'B0),
-    .addrb(14'B0),
-    .dinb(96'B0),
-    .doutb(),
-    .injectsbiterr(1'D0),
-    .injectdbiterr(1'D0),
-    .eccpipece(1'D0),
-    .sbiterr(),
-    .dbiterr(),
-    .rdaddrecc(),
-    .sleep(1'D0),
-    .deepsleep(1'D0),
-    .shutdown(1'D0),
-    .rsta_busy(),
-    .rstb_busy(),
-    .s_aclk(1'H0),
-    .s_aresetn(1'D0),
-    .s_axi_awid(4'B0),
-    .s_axi_awaddr(32'B0),
-    .s_axi_awlen(8'B0),
-    .s_axi_awsize(3'B0),
-    .s_axi_awburst(2'B0),
-    .s_axi_awvalid(1'D0),
-    .s_axi_awready(),
-    .s_axi_wdata(96'B0),
-    .s_axi_wstrb(1'B0),
-    .s_axi_wlast(1'D0),
-    .s_axi_wvalid(1'D0),
-    .s_axi_wready(),
-    .s_axi_bid(),
-    .s_axi_bresp(),
-    .s_axi_bvalid(),
-    .s_axi_bready(1'D0),
-    .s_axi_arid(4'B0),
-    .s_axi_araddr(32'B0),
-    .s_axi_arlen(8'B0),
-    .s_axi_arsize(3'B0),
-    .s_axi_arburst(2'B0),
-    .s_axi_arvalid(1'D0),
-    .s_axi_arready(),
-    .s_axi_rid(),
-    .s_axi_rdata(),
-    .s_axi_rresp(),
-    .s_axi_rlast(),
-    .s_axi_rvalid(),
-    .s_axi_rready(1'D0),
-    .s_axi_injectsbiterr(1'D0),
-    .s_axi_injectdbiterr(1'D0),
-    .s_axi_sbiterr(),
-    .s_axi_dbiterr(),
-    .s_axi_rdaddrecc()
-  );
-endmodule

projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_hop/sim/vio_hop.v

@@ -1,62 +0,0 @@
-// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
-//
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-//
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-//
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-//
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-//
-// DO NOT MODIFY THIS FILE.
-`timescale 1ns / 1ps
-module vio_hop (
-clk,
-
-probe_out0,
-probe_out1
-);
-
-input clk;
-
-output reg [0 : 0] probe_out0 = 'h0 ;
-output reg [0 : 0] probe_out1 = 'h0 ;
-
-
-endmodule

projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_hop/vio_hop.veo

@@ -1,67 +0,0 @@
-// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
-// 
-// This file contains confidential and proprietary information
-// of Xilinx, Inc. and is protected under U.S. and
-// international copyright and other intellectual property
-// laws.
-// 
-// DISCLAIMER
-// This disclaimer is not a license and does not grant any
-// rights to the materials distributed herewith. Except as
-// otherwise provided in a valid license issued to you by
-// Xilinx, and to the maximum extent permitted by applicable
-// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-// (2) Xilinx shall not be liable (whether in contract or tort,
-// including negligence, or under any other theory of
-// liability) for any loss or damage of any kind or nature
-// related to, arising under or in connection with these
-// materials, including for any direct, or any indirect,
-// special, incidental, or consequential loss or damage
-// (including loss of data, profits, goodwill, or any type of
-// loss or damage suffered as a result of any action brought
-// by a third party) even if such damage or loss was
-// reasonably foreseeable or Xilinx had been advised of the
-// possibility of the same.
-// 
-// CRITICAL APPLICATIONS
-// Xilinx products are not designed or intended to be fail-
-// safe, or for use in any application requiring fail-safe
-// performance, such as life-support or safety devices or
-// systems, Class III medical devices, nuclear facilities,
-// applications related to the deployment of airbags, or any
-// other applications that could lead to death, personal
-// injury, or severe property or environmental damage
-// (individually and collectively, "Critical
-// Applications"). Customer assumes the sole risk and
-// liability of any use of Xilinx products in Critical
-// Applications, subject only to applicable laws and
-// regulations governing limitations on product liability.
-// 
-// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-// PART OF THIS FILE AT ALL TIMES.
-// 
-// DO NOT MODIFY THIS FILE.
-
-// IP VLNV: xilinx.com:ip:vio:3.0
-// IP Revision: 20
-
-// The following must be inserted into your Verilog file for this
-// core to be instantiated. Change the instance name and port connections
-// (in parentheses) to your own signal names.
-
-//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
-vio_hop your_instance_name (
-  .clk(clk),                // input wire clk
-  .probe_out0(probe_out0),  // output wire [0 : 0] probe_out0
-  .probe_out1(probe_out1)  // output wire [0 : 0] probe_out1
-);
-// INST_TAG_END ------ End INSTANTIATION Template ---------
-
-// You must compile the wrapper file vio_hop.v when simulating
-// the core, vio_hop. When compiling the wrapper file, be sure to
-// reference the Verilog simulation library.
-

projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_hop/vio_hop.vho

@@ -1,79 +0,0 @@
--- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
--- 
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
--- 
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
--- 
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
--- 
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
--- 
--- DO NOT MODIFY THIS FILE.
-
--- IP VLNV: xilinx.com:ip:vio:3.0
--- IP Revision: 20
-
--- The following code must appear in the VHDL architecture header.
-
-------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
-COMPONENT vio_hop
-  PORT (
-    clk : IN STD_LOGIC;
-    probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
-    probe_out1 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
-  );
-END COMPONENT;
--- COMP_TAG_END ------ End COMPONENT Declaration ------------
-
--- The following code must appear in the VHDL architecture
--- body. Substitute your own instance name and net names.
-
-------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
-your_instance_name : vio_hop
-  PORT MAP (
-    clk => clk,
-    probe_out0 => probe_out0,
-    probe_out1 => probe_out1
-  );
--- INST_TAG_END ------ End INSTANTIATION Template ---------
-
--- You must compile the wrapper file vio_hop.vhd when simulating
--- the core, vio_hop. When compiling the wrapper file, be sure to
--- reference the VHDL simulation library.
-

projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_hop/vio_hop_stub.v

@@ -1,22 +0,0 @@
-// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-// --------------------------------------------------------------------------------
-// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
-// Date        : Wed Apr 19 12:04:19 2023
-// Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
-// Command     : write_verilog -force -mode synth_stub
-//               /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_stub.v
-// Design      : vio_hop
-// Purpose     : Stub declaration of top-level module interface
-// Device      : xc7k410tffg900-2
-// --------------------------------------------------------------------------------
-
-// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
-// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
-// Please paste the declaration into a Verilog source file or add the file as an additional source.
-(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
-module vio_hop(clk, probe_out0, probe_out1)
-/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[0:0],probe_out1[0:0]" */;
-  input clk;
-  output [0:0]probe_out0;
-  output [0:0]probe_out1;
-endmodule

projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_hop/vio_hop_stub.vhdl

@@ -1,32 +0,0 @@
--- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
--- --------------------------------------------------------------------------------
--- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
--- Date        : Wed Apr 19 12:04:19 2023
--- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
--- Command     : write_vhdl -force -mode synth_stub
---               /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_hop_synth_1/vio_hop_stub.vhdl
--- Design      : vio_hop
--- Purpose     : Stub declaration of top-level module interface
--- Device      : xc7k410tffg900-2
--- --------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-entity vio_hop is
-  Port ( 
-    clk : in STD_LOGIC;
-    probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
-    probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 )
-  );
-
-end vio_hop;
-
-architecture stub of vio_hop is
-attribute syn_black_box : boolean;
-attribute black_box_pad_pin : string;
-attribute syn_black_box of stub : architecture is true;
-attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[0:0],probe_out1[0:0]";
-attribute X_CORE_INFO : string;
-attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
-begin
-end;

projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_manual_ctrl/sim/vio_manual_ctrl.v

@@ -53,8 +53,7 @@ probe_out0,
 probe_out1,
 probe_out2,
 probe_out3,
-probe_out4,
+probe_out4
-probe_out5
 );
 
 input clk;
@@ -64,7 +63,6 @@ output reg [0 : 0] probe_out1 = 'h0 ;
 output reg [31 : 0] probe_out2 = 'h00000000 ;
 output reg [1 : 0] probe_out3 = 'h3 ;
 output reg [3 : 0] probe_out4 = 'h0 ;
-output reg [0 : 0] probe_out5 = 'h0 ;
 
 
 endmodule

projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl.veo

@@ -60,8 +60,7 @@ vio_manual_ctrl your_instance_name (
   .probe_out1(probe_out1),  // output wire [0 : 0] probe_out1
   .probe_out2(probe_out2),  // output wire [31 : 0] probe_out2
   .probe_out3(probe_out3),  // output wire [1 : 0] probe_out3
-  .probe_out4(probe_out4),  // output wire [3 : 0] probe_out4
+  .probe_out4(probe_out4)  // output wire [3 : 0] probe_out4
-  .probe_out5(probe_out5)  // output wire [0 : 0] probe_out5
 );
 // INST_TAG_END ------ End INSTANTIATION Template ---------
 

projects/dl814_k7/dl814_k7_online_acq/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl.vho

@@ -59,8 +59,7 @@ COMPONENT vio_manual_ctrl
     probe_out1 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
     probe_out2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
     probe_out3 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
-    probe_out4 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+    probe_out4 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
-    probe_out5 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
   );
 END COMPONENT;
 -- COMP_TAG_END ------ End COMPONENT Declaration ------------
@@ -76,8 +75,7 @@ your_instance_name : vio_manual_ctrl
     probe_out1 => probe_out1,
     probe_out2 => probe_out2,
     probe_out3 => probe_out3,
-    probe_out4 => probe_out4,
+    probe_out4 => probe_out4
-    probe_out5 => probe_out5
   );
 -- INST_TAG_END ------ End INSTANTIATION Template ---------