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prepare for major change in anti-jamming

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resimulated dl814_k7_cal_coarse with multiple trigger and phase compensation; 将校准信号发端移植到地检新射频发送程序上,但是未合并扫频自动校准程序
This commit is contained in:
josh
2023-07-09 15:08:00 +08:00
parent 0729aa40a3
commit a877802bdf
268 changed files with 1448 additions and 13324 deletions
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projects/dl814_dj/dl814_dj_new_48m/rtl/rf_control.v
+207 -414
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@@ -19,439 +19,232 @@
//
//////////////////////////////////////////////////////////////////////////////////
module rf_control(
input clk , //192Mclk
input rst ,
module rf_control
(
// clock & reset
input clk , // 192M clk
input rst ,
input [5:0] tx_gain_manual , //发射增益输入
input [5:0] rx_gain_manual , //接收增益输入
// net tx/rx control
input [ 1:0] rf_txrx_net , // 网络层控制收发，1发2收
input gain_on_vio , //vio设置参数or自动切换
input [1:0] rf_txrx_vio , //发射通道或者接收通道
input [1:0] rf_txrx_net , //受网络层控制
// net freq control
input [11:0] tx_freq_hop_words , // tx跳频频率控制字
input tx_hop_words_valid , // tx跳频频率控制字有效脉冲
input tx_freq_hop_switch , // tx频点切换脉冲
input rf_vio_set , //vio设置参数or自动切换
input [11:0] rx_freq_hop_words , // rx跳频频率控制字
input rx_hop_words_valid , // rx跳频频率控制字有效脉冲
input rx_freq_hop_switch , // rx频点切换脉冲
input [11:0] tx_freq_hop_words , //tx跳频频率控制字
input tx_hop_words_valid , //tx跳频频率控制字有效脉冲
input tx_freq_hop_switch , //tx频点切换脉冲
// vio tx/rx control
input [ 1:0] rf_txrx_vio , // vio控制收发，1发2收
input [11:0] rx_freq_hop_words , //rx跳频频率控制字
input rx_hop_words_valid , //rx跳频频率控制字有效脉冲
input rx_freq_hop_switch , //rx频点切换脉冲
// vio freq control
input [11:0] freq_hop_words_vio , // vio设置跳频频率控制字
input hop_words_valid_vio , // vio设置跳频频率控制字有效脉冲
input freq_hop_switch_vio , // vio设置频点切换脉冲
input [11:0] freq_hop_words_vio , //vio设置跳频频率控制字
input hop_words_valid_vio , //vio设置跳频频率控制字有效脉冲
input freq_hop_switch_vio , //vio设置频点切换脉冲
// manual configuration
input vio_set_trx , // 0: 网络层控制收发，1: vio控制收发
input vio_set_freq , // 0: 网络层控制频点，1: vio控制频点
input rf_config_valid , // 衰减切换脉冲
input [ 7:0] tx_gain , // 发射通道衰减，可调范围0~60dB，1dB步进
input [ 7:0] rx_gain , // 接收通道衰减，可调范围0~60dB，1dB步进
// 新增4个引脚
output reg clk_12M = 1'd0 , // 串行输入时钟
output reg CS_rf = 1'd1 , // 发送使能输入CS
output reg tx_gain = 1'd0 , //发射通道增益
input rx_gain ,
// rf attenuation spi interface
output reg spi_attn_clk = 1'd0 ,
output reg spi_attn_csn = 1'd1 ,
output reg spi_attn_mosi = 1'd0 ,
input spi_attn_miso ,
output reg tx_gain_on = 1'd0 , //发射通道开关
// output reg rx_gain = 1'd0 , //接收通道增益
output reg rx_gain_on = 1'd0 , //发射通道开关
// rf tx/rx control
output reg tx_gain_on = 1'd0 , // 发射通道开关
output reg rx_gain_on = 1'd0 , // 发射通道开关
output reg [11:0] freq_hop_words = 12'd0 , //跳频频率控制字
output reg hop_words_valid = 1'd0 , //跳频频率控制字有效脉冲
output reg freq_hop_switch = 1'd0 , //频点切换脉冲
output reg freq_hop_switch_out = 1'd0 ,
output reg [11:0] freq_hop_words_sweep = 12'd0
);
reg rst_D1_1 = 1'd0;
reg rst_D1_2 = 1'd0;
reg rst_D1_3 = 1'd0;
always @(posedge clk) begin
rst_D1_1 <= rst ;
rst_D1_2 <= rst ;
rst_D1_3 <= rst ;
end
//--------------------------------------------------------------------------------------------------
//发射通道增益、开关设置
always @(posedge clk) begin
if(rst_D1_1)
tx_gain_on <= 1'b0 ;
else if(gain_on_vio)
tx_gain_on <= (rf_txrx_vio[1:0] == 2'd1) ? 1'd1 :1'd0 ;
else
tx_gain_on <= (rf_txrx_net[1:0] == 2'd1) ? 1'd1 :1'd0 ;
end
//--------------------------------------------------------------------------------------------------
//接收通道增益、开关设置
reg [5:0] rx_gain_div2 = 5'd0;
always @(posedge clk) begin
if(rst_D1_2)
rx_gain_on <= 1'b0 ;
else if(gain_on_vio)
rx_gain_on <= (rf_txrx_vio[1:0] == 2'd2) ? 1'd1 :1'd0 ;
else
rx_gain_on <= (rf_txrx_net[1:0] == 2'd2) ? 1'd1 :1'd0 ;
end
//--------------------------------------------------------------------------------------------------
//跳频设置vio控制or网络层设置
reg [11:0] freq_hop_words_net = 12'd0 ;
reg hop_words_valid_net = 1'd0 ;
reg freq_hop_switch_net = 1'd0 ;
always @(posedge clk) begin
if(rst_D1_3)begin
freq_hop_words_net [11:0] <= 12'd0 ;
hop_words_valid_net <= 1'd0 ;
freq_hop_switch_net <= 1'd0 ;
end
else if(rf_txrx_net[1:0] == 2'd1)begin
freq_hop_words_net [11:0] <= tx_freq_hop_words[11:0] ;
hop_words_valid_net <= tx_hop_words_valid ;
freq_hop_switch_net <= tx_freq_hop_switch ;
end
else if(rf_txrx_net[1:0] == 2'd2)begin
freq_hop_words_net [11:0] <= rx_freq_hop_words[11:0] ;
hop_words_valid_net <= rx_hop_words_valid ;
freq_hop_switch_net <= rx_freq_hop_switch ;
end
else begin
freq_hop_words_net [11:0] <= freq_hop_words_net [11:0] ;
hop_words_valid_net <= 1'd0 ;
freq_hop_switch_net <= 1'd0 ;
end
end
// reg [11:0] freq_hop_words_sweep = 12'd0;
reg hop_words_valid_sweep = 1'd0;
reg freq_hop_switch_sweep = 1'd0;
reg hop_words_valid_manual = 1'd0;
reg freq_hop_switch_manual = 1'd0;
reg [11:0] freq_hop_words_manual = 12'd0 ;
wire freq_swicth_start;
always @(posedge clk) begin
if(rst_D1_3)begin
freq_hop_words [11:0] <= 12'd0 ;
hop_words_valid <= 1'd0 ;
freq_hop_switch <= 1'd0 ;
freq_hop_switch_out <= 1'd0 ;
end
else if(rf_vio_set)begin // rf_vio_set为1频率控制字控
freq_hop_words [11:0] <= freq_hop_words_vio[11:0] ;
hop_words_valid <= hop_words_valid_vio ;
freq_hop_switch <= freq_hop_switch_vio ;
freq_hop_switch_out <= freq_hop_switch_vio ;
end
else if(freq_swicth_start)begin
freq_hop_words [11:0] <= freq_hop_words_sweep[11:0] ;
hop_words_valid <= hop_words_valid_sweep ;
freq_hop_switch <= freq_hop_switch_sweep ;
freq_hop_switch_out <= freq_hop_switch_sweep ;
end
else begin
freq_hop_words [11:0] <= freq_hop_words_manual[11:0] ;
hop_words_valid <= hop_words_valid_manual ;
freq_hop_switch <= freq_hop_switch_manual ;
freq_hop_switch_out <= freq_hop_switch_manual ;
end
end
// 12M时钟生成
// reg clk_12M = 1'd0 ;
reg [2:0] cnt_8 = 3'd0 ;
reg clk_switch = 1'd0 ;
// 8位计数器
always@(posedge clk) begin
if(rst_D1_1) begin
cnt_8 <= 3'd0 ;
clk_switch <= 1'd0 ;
end
else if(cnt_8 == 3'd7)begin
cnt_8 <= 3'd0 ;
clk_switch <= 1'd1 ;
end
else begin
cnt_8 <= cnt_8 + 3'd1 ;
clk_switch <= 1'd0 ;
end
end
always@(posedge clk) begin // 产生12M时钟
if(clk_switch == 1'd1)begin
clk_12M <= ~clk_12M ;
end
else begin
clk_12M <= clk_12M ;
end
end
// 发送使能输入
// reg CS_rf = 1'd1;
wire CS_rf_flag;
reg CS_rf_flag_D1 = 1'd0;
wire [31:0] cnt_frechange_top ;
wire [31:0] switch_delay_time ;
wire freq_hop_change ;
wire [11:0] freq_hop_words_vio1 ;
wire [11:0] freq_hop_words_vio2 ;
wire [31:0] valid_delay_time_max ;
wire [63:0] slot_vio_time ;
wire [4:0] cnt_slot_max ;
wire [7:0] MOSI_tx_atte ;
wire [7:0] MOSI_rx_atte ;
// 发送使能输入vio_rftx_en
vio_rf_test vio_rf_test (
.clk(clk), // input wire clk
.probe_out0(CS_rf_flag), // output wire [0 : 0] probe_out0
.probe_out1(MOSI_tx_atte), // output wire [0 : 0] probe_out0
.probe_out2(MOSI_rx_atte), // output wire [0 : 0] probe_out0
.probe_out3(cnt_frechange_top),
.probe_out4(freq_hop_change), // 切换频率开始
.probe_out5(freq_hop_words_vio1[11:0]),
.probe_out6(freq_hop_words_vio2[11:0]),
.probe_out7(switch_delay_time[31:0]), // valid和switch之间的时间
.probe_out8(valid_delay_time_max[31:0]), // valid和switch的切换时间
.probe_out9(slot_vio_time[63:0]), // 一个频点的时间
.probe_out10(cnt_slot_max[4:0]),
.probe_out11(freq_swicth_start)
// rf freq control
output reg [11:0] freq_hop_words = 11'd0 , // 跳频频率控制字
output reg hop_words_valid = 1'd0 , // 跳频频率控制字有效脉冲
output reg freq_hop_switch = 1'd0 // 频点切换脉冲
);
always@(posedge clk_12M)begin
CS_rf_flag_D1 <= CS_rf_flag;
reg rst_D1_1 = 1'd0;
reg rst_D1_2 = 1'd0;
reg rst_D1_3 = 1'd0;
always @(posedge clk) begin
rst_D1_1 <= rst ;
rst_D1_2 <= rst ;
rst_D1_3 <= rst ;
end
// 中频-射频数据输出MOSI
reg MOSI = 1'd0 ;
wire [31:0] MOSI_data;
reg [7:0] MOSI_head = 8'h5A;
// wire [7:0] MOSI_tx_atte ;
// wire [7:0] MOSI_rx_atte ;
reg [7:0] MOSI_recv = 8'hA5;
//------------------------------------------------------------------------------
//发射通道增益、开关设置
assign MOSI_data = {MOSI_head,MOSI_tx_atte,MOSI_rx_atte,MOSI_recv};
always @(posedge clk) begin
if(rst_D1_1)
tx_gain_on <= 1'b0 ;
else if(vio_set_trx)
tx_gain_on <= (rf_txrx_vio[1:0] == 2'd1) ? 1'd1 :1'd0 ;
else
tx_gain_on <= (rf_txrx_net[1:0] == 2'd1) ? 1'd1 :1'd0 ;
end
//------------------------------------------------------------------------------
//接收通道增益、开关设置
always @(posedge clk) begin
if(rst_D1_2)
rx_gain_on <= 1'b0 ;
else if(vio_set_trx)
rx_gain_on <= (rf_txrx_vio[1:0] == 2'd2) ? 1'd1 :1'd0 ;
else
rx_gain_on <= (rf_txrx_net[1:0] == 2'd2) ? 1'd1 :1'd0 ;
end
//------------------------------------------------------------------------------
//跳频设置vio控制or网络层设置
reg [11:0] freq_hop_words_net = 'b0;
reg hop_words_valid_net = 'b0;
reg freq_hop_switch_net = 'b0;
always @(posedge clk) begin
if(rst_D1_3)begin
freq_hop_words_net[11:0] <= 'b0;
hop_words_valid_net <= 'b0;
freq_hop_switch_net <= 'b0;
end
else if(rf_txrx_net[1:0] == 2'd1)begin
freq_hop_words_net[11:0] <= tx_freq_hop_words[11:0];
hop_words_valid_net <= tx_hop_words_valid ;
freq_hop_switch_net <= tx_freq_hop_switch ;
end
else if(rf_txrx_net[1:0] == 2'd2)begin
freq_hop_words_net[11:0] <= rx_freq_hop_words[11:0];
hop_words_valid_net <= rx_hop_words_valid ;
freq_hop_switch_net <= rx_freq_hop_switch ;
end
else begin
freq_hop_words_net[11:0] <= freq_hop_words_net[11:0];
hop_words_valid_net <= 1'd0 ;
freq_hop_switch_net <= 1'd0 ;
end
end
always @(posedge clk) begin
if(rst_D1_3)begin
freq_hop_words[11:0] <= 'b0;
hop_words_valid <= 'b0;
freq_hop_switch <= 'b0;
end
else if(vio_set_freq)begin
freq_hop_words[11:0] <= freq_hop_words_vio[11:0];
hop_words_valid <= hop_words_valid_vio ;
freq_hop_switch <= freq_hop_switch_vio ;
end
else begin
freq_hop_words[11:0] <= freq_hop_words_net[11:0];
hop_words_valid <= hop_words_valid_net ;
freq_hop_switch <= freq_hop_switch_net ;
end
end
// 12M时钟生成
// reg spi_attn_clk = 1'd0;
reg [2:0] cnt_8 = 3'd0;
reg clk_switch = 1'd0;
// 8位计数器
always@(posedge clk) begin
if(rst_D1_1) begin
cnt_8 <= 3'd0;
clk_switch <= 1'd0;
end
else if(cnt_8 == 3'd7)begin
cnt_8 <= 3'd0;
clk_switch <= 1'd1;
end
else begin
cnt_8 <= cnt_8 + 3'd1;
clk_switch <= 1'd0 ;
end
end
always@(posedge clk) begin // 产生12M时钟
if (clk_switch == 1'd1)begin
spi_attn_clk <= ~spi_attn_clk;
end
else begin
spi_attn_clk <= spi_attn_clk;
end
end
// 发送使能输入
reg CS_rf_flag = 'b0;
reg CS_rf_flag_D1 = 'b0;
reg CS_rf_flag_D2 = 'b0;
reg CS_rf_flag_D3 = 'b0;
// 中频-射频数据输出MOSI
reg MOSI = 1'd0 ;
wire [31:0] MOSI_data ;
reg [ 7:0] MOSI_head = 8'h5A;
wire [ 7:0] MOSI_tx_attn ;
wire [ 7:0] MOSI_rx_attn ;
reg [ 7:0] MOSI_recv = 8'hA5;
assign MOSI_tx_attn = tx_gain;
assign MOSI_rx_attn = rx_gain;
always@(posedge spi_attn_clk)begin
CS_rf_flag_D1 <= rf_config_valid;
CS_rf_flag_D2 <= CS_rf_flag_D1;
CS_rf_flag_D3 <= CS_rf_flag_D2;
end
assign MOSI_data = {MOSI_head,MOSI_tx_attn,MOSI_rx_attn,MOSI_recv};
reg [3:0] state_MOSI = 4'd0;
reg [7:0] cnt_64 = 8'd0;
reg [7:0] cnt_64 = 8'd0;
always@(posedge clk_12M) begin
if(rst_D1_1) begin
state_MOSI <= 4'd0;
cnt_64 <= 8'd0;
end
else begin
case(state_MOSI)
4'd0:begin // 等待发送指令
if(CS_rf_flag && !CS_rf_flag_D1)begin
state_MOSI <= 4'd1;
end
else begin
state_MOSI <= 4'd0;
end
end
always@(posedge spi_attn_clk) begin
if(rst_D1_1) begin
state_MOSI <= 4'd0;
cnt_64 <= 8'd0;
end
else begin
case(state_MOSI)
4'd0:begin // 等待发送指令
if(CS_rf_flag_D2 && !CS_rf_flag_D3)begin
state_MOSI <= 4'd1;
end
else begin
state_MOSI <= 4'd0;
end
end
4'd1:begin // 发送数据
CS_rf <= 1'd0;
if(cnt_64 == 8'd31)begin
cnt_64 <= 8'd0;
tx_gain <= MOSI_data[0];
state_MOSI <= 4'd2;
end
else begin
cnt_64 <= cnt_64 + 8'd1;
tx_gain <= MOSI_data[31 - cnt_64];
state_MOSI <= 4'd1;
end
end
4'd1:begin // 发送数据
spi_attn_csn <= 1'd0;
if(cnt_64 == 8'd31)begin
cnt_64 <= 8'd0;
spi_attn_mosi <= MOSI_data[0];
state_MOSI <= 4'd2;
end
else begin
cnt_64 <= cnt_64 + 8'd1;
spi_attn_mosi <= MOSI_data[31 - cnt_64];
state_MOSI <= 4'd1;
end
end
4'd2:begin
CS_rf <= 1'd1;
state_MOSI <= 4'd0;
tx_gain <= 1'd0;
end
endcase
end
end
// 扫频信号
// 通过vio选择控制频点的方式
reg [31:0] cnt_frechange;
always@(posedge clk) begin
if(rst_D1_1)begin
cnt_frechange <= 32'd0;
end
else begin
if(cnt_frechange == cnt_frechange_top) begin
cnt_frechange <= 32'd0;
end
else begin
cnt_frechange <= cnt_frechange + 32'd1;
end
end
end
always@(posedge clk) begin
if(rst_D1_2)begin
freq_hop_words_sweep <= 12'd0;
hop_words_valid_sweep <= 1'd0;
freq_hop_switch_sweep <= 1'd0;
end
else if(cnt_frechange == cnt_frechange_top) begin
if(freq_hop_words_sweep == 12'd3500) begin
freq_hop_words_sweep <= 12'd0;
end
else begin
freq_hop_words_sweep <= freq_hop_words_sweep + 12'd1;
end
hop_words_valid_sweep <= 1'd0;
freq_hop_switch_sweep <= 1'd1;
end
else if(cnt_frechange == cnt_frechange_top - 32'd1920000) begin
freq_hop_words_sweep <= freq_hop_words_sweep;
hop_words_valid_sweep <= 1'd1;
freq_hop_switch_sweep <= 1'd0;
end
else begin
freq_hop_words_sweep <= freq_hop_words_sweep;
hop_words_valid_sweep <= 1'd0;
freq_hop_switch_sweep <= 1'd0;
end
end
// 控制时隙长短
reg [31:0] delay_time = 32'd0;
reg hop_words_valid_manual_long = 1'd0;
reg [31:0] valid_delay_time = 32'd0;
reg [31:0] freq_hop_switch_delay_time = 32'd0;
reg [63:0] slot_time_cnt = 64'd0;
reg [4:0] state_vio_time = 5'd0;
reg [4:0] cnt_slot = 5'd0;
reg freq_hop_change_D1 = 1'd0;
reg freq_hop_change_D2 = 1'd0;
reg freq_hop_change_D3 = 1'd0;
always@(posedge clk) begin
freq_hop_change_D1 <= freq_hop_change;
freq_hop_change_D2 <= freq_hop_change_D1;
freq_hop_change_D3 <= freq_hop_change_D2;
end
always@(posedge clk) begin
if(rst_D1_1) begin
state_vio_time <= 5'd0;
freq_hop_words_manual <= freq_hop_words_vio1;
end
else begin
case(state_vio_time)
5'd0:begin // 等待切换频率开始
if(!freq_hop_change_D1 && freq_hop_change)begin
state_vio_time <= 5'd1;
slot_time_cnt <= 64'd1 + slot_time_cnt;
if(freq_hop_words_manual == freq_hop_words_vio1) begin
freq_hop_words_manual <= freq_hop_words_vio2;
end
else if(freq_hop_words_manual == freq_hop_words_vio2) begin
freq_hop_words_manual <= freq_hop_words_vio1;
end
else begin
freq_hop_words_manual <= freq_hop_words_vio1;
end
end
else begin
state_vio_time <= 5'd0;
freq_hop_words_manual <= freq_hop_words_manual;
end
end
5'd1:begin // 等待valid信号拉高完毕
if(valid_delay_time == valid_delay_time_max) begin
hop_words_valid_manual <= 1'd0;
valid_delay_time <= 32'd0;
state_vio_time <= 5'd2;
end
else begin
hop_words_valid_manual <= 1'd1;
valid_delay_time <= valid_delay_time + 32'd1;
state_vio_time <= 5'd1;
end
slot_time_cnt <= 64'd1 + slot_time_cnt;
end
5'd2:begin // 等待switch信号
if(delay_time == switch_delay_time) begin
freq_hop_switch_manual <= 1'd1;
delay_time <= 32'd0;
state_vio_time <= 5'd3;
end
else begin
freq_hop_switch_manual <= 1'd0;
delay_time <= 32'd1 + delay_time;
state_vio_time <= 5'd2;
end
slot_time_cnt <= 64'd1 + slot_time_cnt;
end
5'd3:begin // 等待switch信号拉高完毕
if(freq_hop_switch_delay_time == valid_delay_time_max) begin
freq_hop_switch_manual <= 1'd0;
freq_hop_switch_delay_time <= 32'd0;
state_vio_time <= 5'd4;
end
else begin
freq_hop_switch_manual <= 1'd1;
freq_hop_switch_delay_time <= freq_hop_switch_delay_time + 32'd1;
state_vio_time <= 5'd3;
end
slot_time_cnt <= 64'd1 + slot_time_cnt;
end
5'd4:begin // 等待时隙结束
if(slot_time_cnt == slot_vio_time)begin
if(cnt_slot == cnt_slot_max - 5'd1) begin
cnt_slot <= 5'd0;
state_vio_time <= 5'd0;
slot_time_cnt <= 64'd0;
end
else begin
state_vio_time <= 5'd1;
slot_time_cnt <= 64'd0;
cnt_slot <= cnt_slot + 5'd1;
end
end
else begin
state_vio_time <= 5'd4;
slot_time_cnt <= 64'd1 + slot_time_cnt;
cnt_slot <= cnt_slot;
end
end
default:begin
if(!freq_hop_change_D1 && freq_hop_change)begin
state_vio_time <= 5'd1;
end
else begin
state_vio_time <= 5'd0;
end
end
endcase
end
4'd2:begin
spi_attn_csn <= 1'd1;
state_MOSI <= 4'd0;
spi_attn_mosi <= 1'd0;
end
endcase
end
end
endmodule
projects/dl814_dj/dl814_dj_new_48m/rtl/system_top.v
+80 -125
View File
@@ -71,10 +71,10 @@ module system_top
// *************************************************************************
// ****************************** RF Control *******************************
// *************************************************************************
output tx_gain ,
input rx_gain ,
output clk_12M ,
output CS_rf ,
output rf_spi_attn_clk ,
output rf_spi_attn_csn ,
output rf_spi_attn_mosi ,
input rf_spi_attn_miso ,
output tx_gain_on ,
output rx_gain_on ,
@@ -107,12 +107,7 @@ module system_top
inout [53:0] fixed_io_mio ,
inout fixed_io_ps_clk ,
inout fixed_io_ps_porb ,
inout fixed_io_ps_srstb ,
// *************************************************************************
// ************************* Sync Signal ***********************************
// *************************************************************************
output sync_signal_out ,
output reg sync_gnd = 1'b0
inout fixed_io_ps_srstb
);
@@ -125,7 +120,10 @@ wire sys_clk_2x ; // 245.76mhz
wire sys_rst ;
// optional siganl clock, can be changed to whatever frequency you want
wire sig_clk ; // 245.76mhz
wire sig_clk ; // 48MHz
wire sig_clk_2x ; // 96MHz
wire sig_clk_3x ; // 144MHz
wire sig_clk_4x ; // 192MHz
wire sig_clk_ld ;
wire sig_rst ;
@@ -135,6 +133,9 @@ sig_clk_gen u_sig_clk_gen
(
// Clock out ports
.clk_out1 (sig_clk ), // output clk_out1
.clk_out2 (sig_clk_2x ), // output clk_out2
.clk_out3 (sig_clk_3x ), // output clk_out3
.clk_out4 (sig_clk_4x ), // output clk_out4
// Status and control signals
.reset (sys_rst ), // input reset
.locked (sig_clk_ld ), // output locked
@@ -257,102 +258,65 @@ system_bd_wrapper u_system_bd
////////////////////////////////////////////////////////////////////////////////
//////////////////////////// RF Control Interface //////////////////////////////
////////////////////////////////////////////////////////////////////////////////
wire gain_on_vio ;
wire [1:0] rf_txrx_vio ;
wire rf_vio_set ;
wire vio_set_trx ;
wire vio_set_freq ;
wire rf_config_valid ;
wire [5:0] tx_gain_manual ;
wire [5:0] rx_gain_manual ;
wire [1:0] rf_txrx_vio ;
wire [7:0] tx_gain_manual ;
wire [7:0] rx_gain_manual ;
wire [11:0] freq_hop_words_vio ;
wire hop_words_valid_vio ;
wire freq_hop_switch_vio ;
wire freq_hop_switch_out ;
wire [11:0] freq_hop_words_sweep;
// rf auto switch frequency function
wire auto_test_enable_vio;
wire rf_auto_start_vio ;
wire rf_ctrl_mode_vio ;
wire switch_next_freq_vio;
wire switch_last_freq_vio;
wire [31:0] cnt_valid_to_switch_vio;
wire [31:0] test_slot_length_vio;
wire [11:0] freq_hop_words_auto ;
wire hop_words_valid_auto;
wire freq_hop_switch_auto;
rf_auto_switch_freq u_rf_auto_switch_freq
(
.clk (sys_clk ),
.rst (sys_rst ),
// vio control
.start (rf_auto_start_vio ), // rise-edge active, if start, change freq word to the first
.auto_test_enable (auto_test_enable_vio ), // rise-edge active
.rf_ctrl_mode (rf_ctrl_mode_vio ), // 1 : auto switch, 0 : manual switch
.switch_next_freq (switch_next_freq_vio ), // rise-edge active
.switch_last_freq (switch_last_freq_vio ), // rise-edge active
.cnt_valid_to_switch (cnt_valid_to_switch_vio ), // the clock number from valid to switch
.test_slot_length (test_slot_length_vio[31:0] ),
// input
.freq_hop_words_vio (freq_hop_words_vio[11:0] ),
.hop_words_valid_vio (hop_words_valid_vio ),
.freq_hop_switch_vio (freq_hop_switch_vio ),
// output
.freq_hop_words_auto (freq_hop_words_auto[11:0] ),
.hop_words_valid_auto (hop_words_valid_auto ),
.freq_hop_switch_auto (freq_hop_switch_auto ),
.sync_signal (sync_signal_out )
);
wire [11:0] freq_hop_words_vio ;
wire hop_words_valid_vio;
wire freq_hop_switch_vio;
rf_control u_rf_control
(
.clk (sys_clk ),
.rst (sys_rst ),
// clock & reset
.clk (sig_clk_4x ), // 192M clk
.rst (sig_rst ),
//input
.gain_on_vio (gain_on_vio ),
.rf_txrx_vio (rf_txrx_vio[1:0] ),
.rf_txrx_net (2'd0 ),
.tx_gain_manual (tx_gain_manual[5:0] ),
.rx_gain_manual (rx_gain_manual[5:0] ),
// net tx/rx control
.rf_txrx_net ('b0 ), // 网络层控制收发，1发2收
//0:net->control 1:vio->control
.rf_vio_set (rf_vio_set ),
// net freq control
.tx_freq_hop_words ('b0 ), // tx跳频频率控制字
.tx_hop_words_valid ('b0 ), // tx跳频频率控制字有效脉冲
.tx_freq_hop_switch ('b0 ), // tx频点切换脉冲
//vio hop control
.freq_hop_words_vio (freq_hop_words_auto[10:0] ),
.hop_words_valid_vio (hop_words_valid_auto ),
.freq_hop_switch_vio (freq_hop_switch_auto ),
.rx_freq_hop_words ('b0 ), // rx跳频频率控制字
.rx_hop_words_valid ('b0 ), // rx跳频频率控制字有效脉冲
.rx_freq_hop_switch ('b0 ), // rx频点切换脉冲
//tx hop control
.tx_freq_hop_words (11'b0 ),
.tx_hop_words_valid (1'b0 ),
.tx_freq_hop_switch (1'b0 ),
// vio tx/rx control
.rf_txrx_vio (rf_txrx_vio[1:0] ), // vio控制收发，1发2收
//rx hop control
.rx_freq_hop_words (11'b0 ),
.rx_hop_words_valid (1'b0 ),
.rx_freq_hop_switch (1'b0 ),
// vio freq control
.freq_hop_words_vio (freq_hop_words_vio[11:0] ), // vio设置跳频频率控制字
.hop_words_valid_vio (hop_words_valid_vio ), // vio设置跳频频率控制字有效脉冲
.freq_hop_switch_vio (freq_hop_switch_vio ), // vio设置频点切换脉冲
//output
.clk_12M (clk_12M ),
.CS_rf (CS_rf ),
.tx_gain (tx_gain ),
.tx_gain_on (tx_gain_on ),
.rx_gain (rx_gain ),
.rx_gain_on (rx_gain_on ),
// manual configuration
.vio_set_trx (vio_set_trx ), // 0: 网络层控制收发，1: vio控制收发
.vio_set_freq (vio_set_freq ), // 0: 网络层控制频点，1: vio控制频点
.rf_config_valid (rf_config_valid ), // 衰减切换脉冲
.tx_gain (tx_gain_manual[7:0] ), // 发射通道衰减，可调范围0~60dB，1dB步进
.rx_gain (rx_gain_manual[7:0] ), // 接收通道衰减，可调范围0~60dB，1dB步进
.freq_hop_words (freq_hop_words[11:0] ),
.hop_words_valid (hop_words_valid ),
.freq_hop_switch (freq_hop_switch ),
.freq_hop_switch_out (freq_hop_switch_out ),
.freq_hop_words_sweep (freq_hop_words_sweep )
// rf attenuation spi interface
.spi_attn_clk (rf_spi_attn_clk ),
.spi_attn_csn (rf_spi_attn_csn ),
.spi_attn_mosi (rf_spi_attn_mosi ),
.spi_attn_miso (rf_spi_attn_miso ),
// rf tx/rx control
.tx_gain_on (tx_gain_on ), // 发射通道开关
.rx_gain_on (rx_gain_on ), // 发射通道开关
// rf freq control
.freq_hop_words (freq_hop_words[11:0] ), // 跳频频率控制字
.hop_words_valid (hop_words_valid ), // 跳频频率控制字有效脉冲
.freq_hop_switch (freq_hop_switch ) // 频点切换脉冲
);
@@ -465,41 +429,32 @@ vio_manual_ctrl u_vio_manual_ctrl
.probe_out4 (bb_rshift ) // output wire [3 : 0] probe_out4
);
vio_rf_control u_vio_rf_control
vio_RF_control u_vio_rf_control
(
.clk (sys_clk ), // input wire clk
.probe_out0 (gain_on_vio ), // output wire [0 : 0] probe_out0
.probe_out1 (rf_txrx_vio[1:0] ), // output wire [1 : 0] probe_out1
.probe_out2 (rf_vio_set ), // output wire [0 : 0] probe_out2
.probe_out3 (tx_gain_manual[5:0] ), // output wire [5 : 0] probe_out3
.probe_out4 (rx_gain_manual[5:0] ), // output wire [5 : 0] probe_out4
.probe_out5 (freq_hop_words_vio[11:0] ), // output wire [10 : 0] probe_out5
.probe_out6 (hop_words_valid_vio ), // output wire [0 : 0] probe_out6
.probe_out7 (freq_hop_switch_vio ), // output wire [0 : 0] probe_out7
.probe_out8 (self_check_dout ), // output wire [0 : 0] probe_out8
.probe_out9 (rf_auto_start_vio ), // output wire [0 : 0] probe_out9
.probe_out10 (rf_ctrl_mode_vio ), // output wire [0 : 0] probe_out10
.probe_out11 (switch_next_freq_vio ), // output wire [0 : 0] probe_out11
.probe_out12 (switch_last_freq_vio ), // output wire [0 : 0] probe_out12
.probe_out13 (cnt_valid_to_switch_vio[31:0] ), // output wire [31: 0] probe_out13
.probe_out14 (auto_test_enable_vio ), // output wire [0 : 0] probe_out14
.probe_out15 (test_slot_length_vio[31:0] ), // output wire [31: 0] probe_out15
.probe_in0 (freq_hop_words_auto[10:0] ) // input wire [10: 0] probe_in0
.clk (sig_clk_4x ), // input wire clk
.probe_out0 (vio_set_trx ), // output wire [0 : 0] probe_out0
.probe_out1 (rf_txrx_vio[1:0] ), // output wire [1 : 0] probe_out1
.probe_out2 (vio_set_freq ), // output wire [0 : 0] probe_out2
.probe_out3 (tx_gain_manual[7:0] ), // output wire [5 : 0] probe_out3
.probe_out4 (rx_gain_manual[7:0] ), // output wire [5 : 0] probe_out4
.probe_out5 (freq_hop_words_vio[11:0] ), // output wire [10 : 0] probe_out5
.probe_out6 (hop_words_valid_vio ), // output wire [0 : 0] probe_out6
.probe_out7 (freq_hop_switch_vio ), // output wire [0 : 0] probe_out7
.probe_out8 (rf_config_valid ) // output wire [0 : 0] probe_out8
);
ila_rf_test ila_rf_test
ila_rf_test u_ila_rf_test
(
.clk (sys_clk ), // input wire clk
.clk (sig_clk_4x ), // input wire clk
.probe0 (freq_hop_words[11:0] ), // input wire [11:0] probe0
.probe1 (tx_gain_on ), // input wire [0:0] probe1
.probe2 (rx_gain ), // input wire [0:0] probe2
.probe3 (rx_gain_on ), // input wire [0:0] probe3
.probe4 (tx_gain ), // input wire [0:0] probe4
.probe5 (hop_words_valid ), // input wire [0:0] probe5
.probe6 (freq_hop_switch ), // input wire [0:0] probe6
.probe7 (clk_12M ), // input wire [0:0] probe7
.probe8 (CS_rf ), // input wire [0:0] probe8
.probe9 (freq_hop_words_sweep ) // input wire [11:0] probe9
.probe1 (rf_spi_attn_clk ), // input wire [0:0] probe1
.probe2 (rf_spi_attn_csn ), // input wire [0:0] probe2
.probe3 (rf_spi_attn_mosi ), // input wire [0:0] probe3
.probe4 (rf_spi_attn_miso ), // input wire [0:0] probe4
.probe5 (tx_gain_on ), // input wire [0:0] probe5
.probe6 (rx_gain_on ), // input wire [0:0] probe6
.probe7 (hop_words_valid ), // input wire [0:0] probe7
.probe8 (freq_hop_switch ) // input wire [0:0] probe8
);
endmodule