prepare for major change in anti-jamming

resimulated dl814_k7_cal_coarse with multiple trigger and phase compensation; 将校准信号发端移植到地检新射频发送程序上,但是未合并扫频自动校准程序
2023-07-09 15:08:00 +08:00
parent 0729aa40a3
commit a877802bdf
268 changed files with 1448 additions and 13324 deletions
@@ -49,15 +49,15 @@ set_property  -dict  {PACKAGE_PIN V27   IOSTANDARD LVCMOS25}  [get_ports {freq_h
 set_property  -dict  {PACKAGE_PIN W30   IOSTANDARD LVCMOS25}  [get_ports {freq_hop_words[10]}   ]
 set_property  -dict  {PACKAGE_PIN W29   IOSTANDARD LVCMOS25}  [get_ports {freq_hop_words[11]}   ]
-set_property  -dict  {PACKAGE_PIN AH21  IOSTANDARD LVCMOS25}  [get_ports tx_gain                ]
+set_property  -dict  {PACKAGE_PIN AH21  IOSTANDARD LVCMOS25}  [get_ports rf_spi_attn_mosi       ]
-set_property  -dict  {PACKAGE_PIN AG21  IOSTANDARD LVCMOS25}  [get_ports rx_gain                ]
+set_property  -dict  {PACKAGE_PIN AG21  IOSTANDARD LVCMOS25}  [get_ports rf_spi_attn_miso       ]
-set_property  -dict  {PACKAGE_PIN V21   IOSTANDARD LVCMOS25}  [get_ports clk_12M                ]
+set_property  -dict  {PACKAGE_PIN V21   IOSTANDARD LVCMOS25}  [get_ports rf_spi_attn_clk        ]
-set_property  -dict  {PACKAGE_PIN AF20  IOSTANDARD LVCMOS25}  [get_ports CS_rf                  ]
+set_property  -dict  {PACKAGE_PIN AF20  IOSTANDARD LVCMOS25}  [get_ports rf_spi_attn_csn        ]
 set_property  -dict  {PACKAGE_PIN V28   IOSTANDARD LVCMOS25}  [get_ports tx_gain_on             ]
 set_property  -dict  {PACKAGE_PIN V29   IOSTANDARD LVCMOS25}  [get_ports rx_gain_on             ]
 set_property  -dict  {PACKAGE_PIN V23   IOSTANDARD LVCMOS25}  [get_ports hop_words_valid        ]
 set_property  -dict  {PACKAGE_PIN W24   IOSTANDARD LVCMOS25}  [get_ports freq_hop_switch        ]
 # Sync Signal
-set_property  -dict  {PACKAGE_PIN AD19  IOSTANDARD LVCMOS25}  [get_ports sync_signal_out        ] ;# Bank9, not used before
+# set_property  -dict  {PACKAGE_PIN AD19  IOSTANDARD LVCMOS25}  [get_ports sync_signal_out        ] ;# Bank9, not used before
-set_property  -dict  {PACKAGE_PIN AD18  IOSTANDARD LVCMOS25}  [get_ports sync_gnd               ] ;# Bank9, not used before
+# set_property  -dict  {PACKAGE_PIN AD18  IOSTANDARD LVCMOS25}  [get_ports sync_gnd               ] ;# Bank9, not used before
@@ -65,8 +65,7 @@ ila_rf_test your_instance_name (
 	.probe5(probe5), // input wire [0:0]  probe5 
 	.probe6(probe6), // input wire [0:0]  probe6 
 	.probe7(probe7), // input wire [0:0]  probe7 
-	.probe8(probe8), // input wire [0:0]  probe8 
+	.probe8(probe8) // input wire [0:0]  probe8
 	.probe9(probe9) // input wire [11:0]  probe9
 );
 // INST_TAG_END ------ End INSTANTIATION Template ---------
@@ -1,10 +1,10 @@
 // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 // --------------------------------------------------------------------------------
 // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
-// Date        : Thu May 18 12:55:28 2023
+// Date        : Mon Jul  3 16:32:04 2023
 // Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
 // Command     : write_verilog -force -mode synth_stub
-//               /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_stub.v
+//               /home/josh/Workspace/datalink_814/phy/dl814_dj_phy_ber/dl814_dj_phy_ber.runs/ila_rf_test_synth_1/ila_rf_test_stub.v
 // Design      : ila_rf_test
 // Purpose     : Stub declaration of top-level module interface
 // Device      : xc7z100ffg900-2
@@ -15,8 +15,8 @@
 // Please paste the declaration into a Verilog source file or add the file as an additional source.
 (* X_CORE_INFO = "ila,Vivado 2019.1.3" *)
 module ila_rf_test(clk, probe0, probe1, probe2, probe3, probe4, probe5, 
-  probe6, probe7, probe8, probe9)
+  probe6, probe7, probe8)
-/* synthesis syn_black_box black_box_pad_pin="clk,probe0[11:0],probe1[0:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[0:0],probe8[0:0],probe9[11:0]" */;
+/* synthesis syn_black_box black_box_pad_pin="clk,probe0[11:0],probe1[0:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[0:0],probe8[0:0]" */;
  input clk;
  input [11:0]probe0;
  input [0:0]probe1;
@@ -27,5 +27,4 @@ module ila_rf_test(clk, probe0, probe1, probe2, probe3, probe4, probe5,
  input [0:0]probe6;
  input [0:0]probe7;
  input [0:0]probe8;
  input [11:0]probe9;
 endmodule
@@ -1,10 +1,10 @@
 -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 -- --------------------------------------------------------------------------------
 -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
-- Date        : Thu May 18 12:55:28 2023
+-- Date        : Mon Jul  3 16:32:04 2023
 -- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
 -- Command     : write_vhdl -force -mode synth_stub
--               /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_stub.vhdl
+--               /home/josh/Workspace/datalink_814/phy/dl814_dj_phy_ber/dl814_dj_phy_ber.runs/ila_rf_test_synth_1/ila_rf_test_stub.vhdl
 -- Design      : ila_rf_test
 -- Purpose     : Stub declaration of top-level module interface
 -- Device      : xc7z100ffg900-2
@@ -23,8 +23,7 @@ entity ila_rf_test is
    probe5 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe6 : in STD_LOGIC_VECTOR ( 0 to 0 );
    probe7 : in STD_LOGIC_VECTOR ( 0 to 0 );
-    probe8 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe8 : in STD_LOGIC_VECTOR ( 0 to 0 )
    probe9 : in STD_LOGIC_VECTOR ( 11 downto 0 )
  );
 end ila_rf_test;
@@ -33,7 +32,7 @@ architecture stub of ila_rf_test is
 attribute syn_black_box : boolean;
 attribute black_box_pad_pin : string;
 attribute syn_black_box of stub : architecture is true;
-attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[0:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[0:0],probe8[0:0],probe9[11:0]";
+attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[0:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[0:0],probe8[0:0]";
 attribute X_CORE_INFO : string;
 attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3";
 begin
@@ -58,8 +58,7 @@ probe4,
 probe5,
 probe6,
 probe7,
-probe8,
+probe8
 probe9
 );
 input clk;
@@ -74,7 +73,6 @@ input [0 : 0] probe5;
 input [0 : 0] probe6;
 input [0 : 0] probe7;
 input [0 : 0] probe8;
 input [11 : 0] probe9;
 endmodule
@@ -46,9 +46,9 @@
 //
 // DO NOT MODIFY THIS FILE.
 `timescale 1ns / 1ps
-module vio_rf_control (
+module vio_RF_control (
 clk,
-probe_in0,
+
 probe_out0,
 probe_out1,
 probe_out2,
@@ -57,35 +57,20 @@ probe_out4,
 probe_out5,
 probe_out6,
 probe_out7,
-probe_out8,
+probe_out8
 probe_out9,
 probe_out10,
 probe_out11,
 probe_out12,
 probe_out13,
 probe_out14,
 probe_out15
 );
 input clk;
 input [10 : 0] probe_in0;
 output reg [0 : 0] probe_out0 = 'h0 ;
 output reg [1 : 0] probe_out1 = 'h0 ;
 output reg [0 : 0] probe_out2 = 'h0 ;
-output reg [5 : 0] probe_out3 = 'h08 ;
+output reg [7 : 0] probe_out3 = 'h03 ;
-output reg [5 : 0] probe_out4 = 'h38 ;
+output reg [7 : 0] probe_out4 = 'h23 ;
 output reg [11 : 0] probe_out5 = 'h3E8 ;
 output reg [0 : 0] probe_out6 = 'h0 ;
 output reg [0 : 0] probe_out7 = 'h0 ;
 output reg [0 : 0] probe_out8 = 'h0 ;
 output reg [0 : 0] probe_out9 = 'h0 ;
 output reg [0 : 0] probe_out10 = 'h0 ;
 output reg [0 : 0] probe_out11 = 'h0 ;
 output reg [0 : 0] probe_out12 = 'h0 ;
 output reg [31 : 0] probe_out13 = 'h00000000 ;
 output reg [0 : 0] probe_out14 = 'h0 ;
 output reg [31 : 0] probe_out15 = 'h00000000 ;
 endmodule
@@ -54,24 +54,21 @@
 // (in parentheses) to your own signal names.
 //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
-vio_rf_test your_instance_name (
+vio_RF_control your_instance_name (
  .clk(clk),                // input wire clk
  .probe_out0(probe_out0),  // output wire [0 : 0] probe_out0
-  .probe_out1(probe_out1),    // output wire [7 : 0] probe_out1
+  .probe_out1(probe_out1),  // output wire [1 : 0] probe_out1
-  .probe_out2(probe_out2),    // output wire [7 : 0] probe_out2
+  .probe_out2(probe_out2),  // output wire [0 : 0] probe_out2
-  .probe_out3(probe_out3),    // output wire [31 : 0] probe_out3
+  .probe_out3(probe_out3),  // output wire [7 : 0] probe_out3
-  .probe_out4(probe_out4),    // output wire [0 : 0] probe_out4
+  .probe_out4(probe_out4),  // output wire [7 : 0] probe_out4
  .probe_out5(probe_out5),  // output wire [11 : 0] probe_out5
-  .probe_out6(probe_out6),    // output wire [11 : 0] probe_out6
+  .probe_out6(probe_out6),  // output wire [0 : 0] probe_out6
-  .probe_out7(probe_out7),    // output wire [31 : 0] probe_out7
+  .probe_out7(probe_out7),  // output wire [0 : 0] probe_out7
-  .probe_out8(probe_out8),    // output wire [31 : 0] probe_out8
+  .probe_out8(probe_out8)  // output wire [0 : 0] probe_out8
  .probe_out9(probe_out9),    // output wire [63 : 0] probe_out9
  .probe_out10(probe_out10),  // output wire [4 : 0] probe_out10
  .probe_out11(probe_out11)  // output wire [0 : 0] probe_out11
 );
 // INST_TAG_END ------ End INSTANTIATION Template ---------
-// You must compile the wrapper file vio_rf_test.v when simulating
+// You must compile the wrapper file vio_RF_control.v when simulating
-// the core, vio_rf_test. When compiling the wrapper file, be sure to
+// the core, vio_RF_control. When compiling the wrapper file, be sure to
 // reference the Verilog simulation library.
@@ -52,21 +52,18 @@
 -- The following code must appear in the VHDL architecture header.
 ------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
-COMPONENT vio_rf_test
+COMPONENT vio_RF_control
  PORT (
    clk : IN STD_LOGIC;
    probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
-    probe_out1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+    probe_out1 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
-    probe_out2 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+    probe_out2 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
-    probe_out3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    probe_out3 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-    probe_out4 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    probe_out4 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
    probe_out5 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
-    probe_out6 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
+    probe_out6 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
-    probe_out7 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    probe_out7 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
-    probe_out8 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    probe_out8 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
    probe_out9 : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
    probe_out10 : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
    probe_out11 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
  );
 END COMPONENT;
 -- COMP_TAG_END ------ End COMPONENT Declaration ------------
@@ -75,7 +72,7 @@ END COMPONENT;
 -- body. Substitute your own instance name and net names.
 ------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
-your_instance_name : vio_rf_test
+your_instance_name : vio_RF_control
  PORT MAP (
    clk => clk,
    probe_out0 => probe_out0,
@@ -86,14 +83,11 @@ your_instance_name : vio_rf_test
    probe_out5 => probe_out5,
    probe_out6 => probe_out6,
    probe_out7 => probe_out7,
-    probe_out8 => probe_out8,
+    probe_out8 => probe_out8
    probe_out9 => probe_out9,
    probe_out10 => probe_out10,
    probe_out11 => probe_out11
  );
 -- INST_TAG_END ------ End INSTANTIATION Template ---------
-- You must compile the wrapper file vio_rf_test.vhd when simulating
+-- You must compile the wrapper file vio_RF_control.vhd when simulating
-- the core, vio_rf_test. When compiling the wrapper file, be sure to
+-- the core, vio_RF_control. When compiling the wrapper file, be sure to
 -- reference the VHDL simulation library.
@@ -1,11 +1,11 @@
 // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 // --------------------------------------------------------------------------------
 // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
-// Date        : Thu May 18 12:54:39 2023
+// Date        : Tue Jun 27 16:05:58 2023
 // Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
 // Command     : write_verilog -force -mode synth_stub
-//               /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_stub.v
+//               /home/josh/Workspace/datalink_814/phy/dl814_dj_phy_ber/dl814_dj_phy_ber.runs/vio_RF_control_synth_1/vio_RF_control_stub.v
-// Design      : vio_rf_test
+// Design      : vio_RF_control
 // Purpose     : Stub declaration of top-level module interface
 // Device      : xc7z100ffg900-2
 // --------------------------------------------------------------------------------
@@ -14,21 +14,17 @@
 // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
 // Please paste the declaration into a Verilog source file or add the file as an additional source.
 (* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
-module vio_rf_test(clk, probe_out0, probe_out1, probe_out2, 
+module vio_RF_control(clk, probe_out0, probe_out1, probe_out2, 
-  probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9, 
+  probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8)
-  probe_out10, probe_out11)
+/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[7:0],probe_out4[7:0],probe_out5[11:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0]" */;
 /* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[0:0],probe_out1[7:0],probe_out2[7:0],probe_out3[31:0],probe_out4[0:0],probe_out5[11:0],probe_out6[11:0],probe_out7[31:0],probe_out8[31:0],probe_out9[63:0],probe_out10[4:0],probe_out11[0:0]" */;
  input clk;
  output [0:0]probe_out0;
-  output [7:0]probe_out1;
+  output [1:0]probe_out1;
-  output [7:0]probe_out2;
+  output [0:0]probe_out2;
-  output [31:0]probe_out3;
+  output [7:0]probe_out3;
-  output [0:0]probe_out4;
+  output [7:0]probe_out4;
  output [11:0]probe_out5;
-  output [11:0]probe_out6;
+  output [0:0]probe_out6;
-  output [31:0]probe_out7;
+  output [0:0]probe_out7;
-  output [31:0]probe_out8;
+  output [0:0]probe_out8;
  output [63:0]probe_out9;
  output [4:0]probe_out10;
  output [0:0]probe_out11;
 endmodule
@@ -1,46 +1,38 @@
 -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 -- --------------------------------------------------------------------------------
 -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
-- Date        : Thu May 18 11:36:40 2023
+-- Date        : Tue Jun 27 16:05:58 2023
 -- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
 -- Command     : write_vhdl -force -mode synth_stub
--               /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.vhdl
+--               /home/josh/Workspace/datalink_814/phy/dl814_dj_phy_ber/dl814_dj_phy_ber.runs/vio_RF_control_synth_1/vio_RF_control_stub.vhdl
-- Design      : vio_rf_control
+-- Design      : vio_RF_control
 -- Purpose     : Stub declaration of top-level module interface
 -- Device      : xc7z100ffg900-2
 -- --------------------------------------------------------------------------------
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
-entity vio_rf_control is
+entity vio_RF_control is
  Port ( 
    clk : in STD_LOGIC;
    probe_in0 : in STD_LOGIC_VECTOR ( 10 downto 0 );
    probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    probe_out1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 );
-    probe_out3 : out STD_LOGIC_VECTOR ( 5 downto 0 );
+    probe_out3 : out STD_LOGIC_VECTOR ( 7 downto 0 );
-    probe_out4 : out STD_LOGIC_VECTOR ( 5 downto 0 );
+    probe_out4 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    probe_out5 : out STD_LOGIC_VECTOR ( 11 downto 0 );
    probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 );
    probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 );
-    probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 );
+    probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 )
    probe_out9 : out STD_LOGIC_VECTOR ( 0 to 0 );
    probe_out10 : out STD_LOGIC_VECTOR ( 0 to 0 );
    probe_out11 : out STD_LOGIC_VECTOR ( 0 to 0 );
    probe_out12 : out STD_LOGIC_VECTOR ( 0 to 0 );
    probe_out13 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 );
    probe_out15 : out STD_LOGIC_VECTOR ( 31 downto 0 )
  );
-end vio_rf_control;
+end vio_RF_control;
-architecture stub of vio_rf_control is
+architecture stub of vio_RF_control is
 attribute syn_black_box : boolean;
 attribute black_box_pad_pin : string;
 attribute syn_black_box of stub : architecture is true;
-attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[10:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[5:0],probe_out4[5:0],probe_out5[11:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[31:0],probe_out14[0:0],probe_out15[31:0]";
+attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[7:0],probe_out4[7:0],probe_out5[11:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0]";
 attribute X_CORE_INFO : string;
 attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
 begin
@@ -1,82 +0,0 @@
 // (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
 // 
 // This file contains confidential and proprietary information
 // of Xilinx, Inc. and is protected under U.S. and
 // international copyright and other intellectual property
 // laws.
 // 
 // DISCLAIMER
 // This disclaimer is not a license and does not grant any
 // rights to the materials distributed herewith. Except as
 // otherwise provided in a valid license issued to you by
 // Xilinx, and to the maximum extent permitted by applicable
 // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
 // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
 // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
 // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
 // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
 // (2) Xilinx shall not be liable (whether in contract or tort,
 // including negligence, or under any other theory of
 // liability) for any loss or damage of any kind or nature
 // related to, arising under or in connection with these
 // materials, including for any direct, or any indirect,
 // special, incidental, or consequential loss or damage
 // (including loss of data, profits, goodwill, or any type of
 // loss or damage suffered as a result of any action brought
 // by a third party) even if such damage or loss was
 // reasonably foreseeable or Xilinx had been advised of the
 // possibility of the same.
 // 
 // CRITICAL APPLICATIONS
 // Xilinx products are not designed or intended to be fail-
 // safe, or for use in any application requiring fail-safe
 // performance, such as life-support or safety devices or
 // systems, Class III medical devices, nuclear facilities,
 // applications related to the deployment of airbags, or any
 // other applications that could lead to death, personal
 // injury, or severe property or environmental damage
 // (individually and collectively, "Critical
 // Applications"). Customer assumes the sole risk and
 // liability of any use of Xilinx products in Critical
 // Applications, subject only to applicable laws and
 // regulations governing limitations on product liability.
 // 
 // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
 // PART OF THIS FILE AT ALL TIMES.
 // 
 // DO NOT MODIFY THIS FILE.
 // IP VLNV: xilinx.com:ip:vio:3.0
 // IP Revision: 20
 // The following must be inserted into your Verilog file for this
 // core to be instantiated. Change the instance name and port connections
 // (in parentheses) to your own signal names.
 //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
 vio_rf_control your_instance_name (
  .clk(clk),                  // input wire clk
  .probe_in0(probe_in0),      // input wire [10 : 0] probe_in0
  .probe_out0(probe_out0),    // output wire [0 : 0] probe_out0
  .probe_out1(probe_out1),    // output wire [1 : 0] probe_out1
  .probe_out2(probe_out2),    // output wire [0 : 0] probe_out2
  .probe_out3(probe_out3),    // output wire [5 : 0] probe_out3
  .probe_out4(probe_out4),    // output wire [5 : 0] probe_out4
  .probe_out5(probe_out5),    // output wire [11 : 0] probe_out5
  .probe_out6(probe_out6),    // output wire [0 : 0] probe_out6
  .probe_out7(probe_out7),    // output wire [0 : 0] probe_out7
  .probe_out8(probe_out8),    // output wire [0 : 0] probe_out8
  .probe_out9(probe_out9),    // output wire [0 : 0] probe_out9
  .probe_out10(probe_out10),  // output wire [0 : 0] probe_out10
  .probe_out11(probe_out11),  // output wire [0 : 0] probe_out11
  .probe_out12(probe_out12),  // output wire [0 : 0] probe_out12
  .probe_out13(probe_out13),  // output wire [31 : 0] probe_out13
  .probe_out14(probe_out14),  // output wire [0 : 0] probe_out14
  .probe_out15(probe_out15)  // output wire [31 : 0] probe_out15
 );
 // INST_TAG_END ------ End INSTANTIATION Template ---------
 // You must compile the wrapper file vio_rf_control.v when simulating
 // the core, vio_rf_control. When compiling the wrapper file, be sure to
 // reference the Verilog simulation library.
@@ -1,109 +0,0 @@
 -- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
 -- 
 -- This file contains confidential and proprietary information
 -- of Xilinx, Inc. and is protected under U.S. and
 -- international copyright and other intellectual property
 -- laws.
 -- 
 -- DISCLAIMER
 -- This disclaimer is not a license and does not grant any
 -- rights to the materials distributed herewith. Except as
 -- otherwise provided in a valid license issued to you by
 -- Xilinx, and to the maximum extent permitted by applicable
 -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
 -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
 -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
 -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
 -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
 -- (2) Xilinx shall not be liable (whether in contract or tort,
 -- including negligence, or under any other theory of
 -- liability) for any loss or damage of any kind or nature
 -- related to, arising under or in connection with these
 -- materials, including for any direct, or any indirect,
 -- special, incidental, or consequential loss or damage
 -- (including loss of data, profits, goodwill, or any type of
 -- loss or damage suffered as a result of any action brought
 -- by a third party) even if such damage or loss was
 -- reasonably foreseeable or Xilinx had been advised of the
 -- possibility of the same.
 -- 
 -- CRITICAL APPLICATIONS
 -- Xilinx products are not designed or intended to be fail-
 -- safe, or for use in any application requiring fail-safe
 -- performance, such as life-support or safety devices or
 -- systems, Class III medical devices, nuclear facilities,
 -- applications related to the deployment of airbags, or any
 -- other applications that could lead to death, personal
 -- injury, or severe property or environmental damage
 -- (individually and collectively, "Critical
 -- Applications"). Customer assumes the sole risk and
 -- liability of any use of Xilinx products in Critical
 -- Applications, subject only to applicable laws and
 -- regulations governing limitations on product liability.
 -- 
 -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
 -- PART OF THIS FILE AT ALL TIMES.
 -- 
 -- DO NOT MODIFY THIS FILE.
 -- IP VLNV: xilinx.com:ip:vio:3.0
 -- IP Revision: 20
 -- The following code must appear in the VHDL architecture header.
 ------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
 COMPONENT vio_rf_control
  PORT (
    clk : IN STD_LOGIC;
    probe_in0 : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
    probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    probe_out1 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
    probe_out2 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    probe_out3 : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
    probe_out4 : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
    probe_out5 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
    probe_out6 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    probe_out7 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    probe_out8 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    probe_out9 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    probe_out10 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    probe_out11 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    probe_out12 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    probe_out13 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
    probe_out14 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    probe_out15 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
  );
 END COMPONENT;
 -- COMP_TAG_END ------ End COMPONENT Declaration ------------
 -- The following code must appear in the VHDL architecture
 -- body. Substitute your own instance name and net names.
 ------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
 your_instance_name : vio_rf_control
  PORT MAP (
    clk => clk,
    probe_in0 => probe_in0,
    probe_out0 => probe_out0,
    probe_out1 => probe_out1,
    probe_out2 => probe_out2,
    probe_out3 => probe_out3,
    probe_out4 => probe_out4,
    probe_out5 => probe_out5,
    probe_out6 => probe_out6,
    probe_out7 => probe_out7,
    probe_out8 => probe_out8,
    probe_out9 => probe_out9,
    probe_out10 => probe_out10,
    probe_out11 => probe_out11,
    probe_out12 => probe_out12,
    probe_out13 => probe_out13,
    probe_out14 => probe_out14,
    probe_out15 => probe_out15
  );
 -- INST_TAG_END ------ End INSTANTIATION Template ---------
 -- You must compile the wrapper file vio_rf_control.vhd when simulating
 -- the core, vio_rf_control. When compiling the wrapper file, be sure to
 -- reference the VHDL simulation library.
@@ -1,39 +0,0 @@
 // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 // --------------------------------------------------------------------------------
 // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
 // Date        : Thu May 18 11:36:40 2023
 // Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
 // Command     : write_verilog -force -mode synth_stub
 //               /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.v
 // Design      : vio_rf_control
 // Purpose     : Stub declaration of top-level module interface
 // Device      : xc7z100ffg900-2
 // --------------------------------------------------------------------------------
 // This empty module with port declaration file causes synthesis tools to infer a black box for IP.
 // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
 // Please paste the declaration into a Verilog source file or add the file as an additional source.
 (* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
 module vio_rf_control(clk, probe_in0, probe_out0, probe_out1, 
  probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9, 
  probe_out10, probe_out11, probe_out12, probe_out13, probe_out14, probe_out15)
 /* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[10:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[5:0],probe_out4[5:0],probe_out5[11:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[31:0],probe_out14[0:0],probe_out15[31:0]" */;
  input clk;
  input [10:0]probe_in0;
  output [0:0]probe_out0;
  output [1:0]probe_out1;
  output [0:0]probe_out2;
  output [5:0]probe_out3;
  output [5:0]probe_out4;
  output [11:0]probe_out5;
  output [0:0]probe_out6;
  output [0:0]probe_out7;
  output [0:0]probe_out8;
  output [0:0]probe_out9;
  output [0:0]probe_out10;
  output [0:0]probe_out11;
  output [0:0]probe_out12;
  output [31:0]probe_out13;
  output [0:0]probe_out14;
  output [31:0]probe_out15;
 endmodule
@@ -1,47 +0,0 @@
 -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 -- --------------------------------------------------------------------------------
 -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
 -- Date        : Thu May 18 11:36:40 2023
 -- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
 -- Command     : write_vhdl -force -mode synth_stub
 --               /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.vhdl
 -- Design      : vio_rf_control
 -- Purpose     : Stub declaration of top-level module interface
 -- Device      : xc7z100ffg900-2
 -- --------------------------------------------------------------------------------
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 entity vio_rf_control is
  Port ( 
    clk : in STD_LOGIC;
    probe_in0 : in STD_LOGIC_VECTOR ( 10 downto 0 );
    probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    probe_out1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 );
    probe_out3 : out STD_LOGIC_VECTOR ( 5 downto 0 );
    probe_out4 : out STD_LOGIC_VECTOR ( 5 downto 0 );
    probe_out5 : out STD_LOGIC_VECTOR ( 11 downto 0 );
    probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 );
    probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 );
    probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 );
    probe_out9 : out STD_LOGIC_VECTOR ( 0 to 0 );
    probe_out10 : out STD_LOGIC_VECTOR ( 0 to 0 );
    probe_out11 : out STD_LOGIC_VECTOR ( 0 to 0 );
    probe_out12 : out STD_LOGIC_VECTOR ( 0 to 0 );
    probe_out13 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 );
    probe_out15 : out STD_LOGIC_VECTOR ( 31 downto 0 )
  );
 end vio_rf_control;
 architecture stub of vio_rf_control is
 attribute syn_black_box : boolean;
 attribute black_box_pad_pin : string;
 attribute syn_black_box of stub : architecture is true;
 attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[10:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[5:0],probe_out4[5:0],probe_out5[11:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[31:0],probe_out14[0:0],probe_out15[31:0]";
 attribute X_CORE_INFO : string;
 attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
 begin
 end;
@@ -1,283 +0,0 @@
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 mLQSSv4FDwGW+hU2bHZPiUhUUQSmaa9T19pbpa6s8ZJ0xLEbS3z1xEajwM0bFGEGE+lodnN0Ziu+
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 pU7X3s5l0gEMjqTKe4cxHPW2hjvKhiEEb66pzjN7HK0y5nrjMJxzwtfqbNV7b76TcDtX27W08c9U
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 0V2+smFFQ/BZxLQ4eV8NHKeszc4kI6jJ3OCncsP57tfkE6TmVTtWKiimERISYB4KhUpblsbN6zyX
 Bni5ezNwl9XdaBq9c90k+QQmaMGeyQbczdGy9ufcC269vB1FU5+a67Ew8h0jPAPeYHvsw4kGsTSh
 xnhGNUHRuPoNmQYBjI2LztvnbGuoucUVntUi5quKpKAK1fOZerZTh+kr5PjaW0YlozpL5CtElvS3
 eqqkVT8a5mdW+sWTxJxTjqronag0QACsSwbA9qurCW9IdcOO+0D7nzfIJIFrWKx+D71JhKNvOmUa
 NmCy9l+wzdpcLs1zvS3o3zwEgUWOOHzITgzOxtDhIuBcJkg9lS+o5b+W+U9fplCbVFjYd5ZDa2sX
 90/8XCJA0a9VcsSrh1LoO0V3YX80VWdNPY79OUOlqftl3rNXVXE=
 `pragma protect end_protected
@@ -1,82 +0,0 @@
 // (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
 //
 // This file contains confidential and proprietary information
 // of Xilinx, Inc. and is protected under U.S. and
 // international copyright and other intellectual property
 // laws.
 //
 // DISCLAIMER
 // This disclaimer is not a license and does not grant any
 // rights to the materials distributed herewith. Except as
 // otherwise provided in a valid license issued to you by
 // Xilinx, and to the maximum extent permitted by applicable
 // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
 // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
 // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
 // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
 // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
 // (2) Xilinx shall not be liable (whether in contract or tort,
 // including negligence, or under any other theory of
 // liability) for any loss or damage of any kind or nature
 // related to, arising under or in connection with these
 // materials, including for any direct, or any indirect,
 // special, incidental, or consequential loss or damage
 // (including loss of data, profits, goodwill, or any type of
 // loss or damage suffered as a result of any action brought
 // by a third party) even if such damage or loss was
 // reasonably foreseeable or Xilinx had been advised of the
 // possibility of the same.
 //
 // CRITICAL APPLICATIONS
 // Xilinx products are not designed or intended to be fail-
 // safe, or for use in any application requiring fail-safe
 // performance, such as life-support or safety devices or
 // systems, Class III medical devices, nuclear facilities,
 // applications related to the deployment of airbags, or any
 // other applications that could lead to death, personal
 // injury, or severe property or environmental damage
 // (individually and collectively, "Critical
 // Applications"). Customer assumes the sole risk and
 // liability of any use of Xilinx products in Critical
 // Applications, subject only to applicable laws and
 // regulations governing limitations on product liability.
 //
 // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
 // PART OF THIS FILE AT ALL TIMES.
 //
 // DO NOT MODIFY THIS FILE.
 `timescale 1ns / 1ps
 module vio_rf_test (
 clk,
 probe_out0,
 probe_out1,
 probe_out2,
 probe_out3,
 probe_out4,
 probe_out5,
 probe_out6,
 probe_out7,
 probe_out8,
 probe_out9,
 probe_out10,
 probe_out11
 );
 input clk;
 output reg [0 : 0] probe_out0 = 'h0 ;
 output reg [7 : 0] probe_out1 = 'h1f ;
 output reg [7 : 0] probe_out2 = 'h1f ;
 output reg [31 : 0] probe_out3 = 'h003A9800 ;
 output reg [0 : 0] probe_out4 = 'h0 ;
 output reg [11 : 0] probe_out5 = 'h3E8 ;
 output reg [11 : 0] probe_out6 = 'h5DC ;
 output reg [31 : 0] probe_out7 = 'h00004800 ;
 output reg [31 : 0] probe_out8 = 'h000000C0 ;
 output reg [63 : 0] probe_out9 = 'h0000000000009600 ;
 output reg [4 : 0] probe_out10 = 'h10 ;
 output reg [0 : 0] probe_out11 = 'h0 ;
 endmodule
@@ -1,42 +0,0 @@
 -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 -- --------------------------------------------------------------------------------
 -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
 -- Date        : Thu May 18 12:54:39 2023
 -- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
 -- Command     : write_vhdl -force -mode synth_stub
 --               /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_stub.vhdl
 -- Design      : vio_rf_test
 -- Purpose     : Stub declaration of top-level module interface
 -- Device      : xc7z100ffg900-2
 -- --------------------------------------------------------------------------------
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 entity vio_rf_test is
  Port ( 
    clk : in STD_LOGIC;
    probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    probe_out1 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    probe_out2 : out STD_LOGIC_VECTOR ( 7 downto 0 );
    probe_out3 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    probe_out4 : out STD_LOGIC_VECTOR ( 0 to 0 );
    probe_out5 : out STD_LOGIC_VECTOR ( 11 downto 0 );
    probe_out6 : out STD_LOGIC_VECTOR ( 11 downto 0 );
    probe_out7 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    probe_out8 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    probe_out9 : out STD_LOGIC_VECTOR ( 63 downto 0 );
    probe_out10 : out STD_LOGIC_VECTOR ( 4 downto 0 );
    probe_out11 : out STD_LOGIC_VECTOR ( 0 to 0 )
  );
 end vio_rf_test;
 architecture stub of vio_rf_test is
 attribute syn_black_box : boolean;
 attribute black_box_pad_pin : string;
 attribute syn_black_box of stub : architecture is true;
 attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[0:0],probe_out1[7:0],probe_out2[7:0],probe_out3[31:0],probe_out4[0:0],probe_out5[11:0],probe_out6[11:0],probe_out7[31:0],probe_out8[31:0],probe_out9[63:0],probe_out10[4:0],probe_out11[0:0]";
 attribute X_CORE_INFO : string;
 attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
 begin
 end;
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Thu May 18 12:54:21 CST 2023
+# Generated by export_simulation on Mon Jul 03 19:45:33 CST 2023
 #
 ################################################################################
@@ -8,11 +8,11 @@ vmap xil_defaultlib activehdl/xil_defaultlib
 vmap xpm activehdl/xpm
 vlog -work xil_defaultlib  -sv2k12 "+incdir+../../../ip/ila_rf_test/hdl/verilog" \
-"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
-"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
 vcom -work xpm -93 \
-"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
 vlog -work xil_defaultlib  -v2k5 "+incdir+../../../ip/ila_rf_test/hdl/verilog" \
 "../../../ip/ila_rf_test/sim/ila_rf_test.v" \
@@ -1,5 +1,5 @@
-xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rf_test/hdl/verilog"
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rf_test/hdl/verilog"
-xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rf_test/hdl/verilog"
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rf_test/hdl/verilog"
-xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rf_test/hdl/verilog"
+xpm_VCOMP.vhd,vhdl,xpm,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rf_test/hdl/verilog"
 ila_rf_test.v,verilog,xil_defaultlib,../../../ip/ila_rf_test/sim/ila_rf_test.v,incdir="../../../ip/ila_rf_test/hdl/verilog"
 glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Thu May 18 12:54:21 CST 2023
+# Generated by Vivado on Mon Jul 03 19:45:33 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Thu May 18 12:54:21 CST 2023
+# Generated by export_simulation on Mon Jul 03 19:45:33 CST 2023
 #
 ################################################################################
@@ -1,5 +1,5 @@
-xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rf_test/hdl/verilog"
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rf_test/hdl/verilog"
-xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rf_test/hdl/verilog"
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rf_test/hdl/verilog"
-xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rf_test/hdl/verilog"
+xpm_VCOMP.vhd,vhdl,xpm,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rf_test/hdl/verilog"
 ila_rf_test.v,verilog,xil_defaultlib,../../../ip/ila_rf_test/sim/ila_rf_test.v,incdir="../../../ip/ila_rf_test/hdl/verilog"
 glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Thu May 18 12:54:21 CST 2023
+# Generated by Vivado on Mon Jul 03 19:45:33 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
@@ -1,9 +1,9 @@
 -makelib ies_lib/xil_defaultlib -sv \
-  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+  "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
-  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+  "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
 -endlib
 -makelib ies_lib/xpm \
-  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+  "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
 -endlib
 -makelib ies_lib/xil_defaultlib \
  "../../../ip/ila_rf_test/sim/ila_rf_test.v" \
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Thu May 18 12:54:21 CST 2023
+# Generated by export_simulation on Mon Jul 03 19:45:33 CST 2023
 #
 ################################################################################
@@ -2,13 +2,21 @@ vlib modelsim_lib/work
 vlib modelsim_lib/msim
 vlib modelsim_lib/msim/xil_defaultlib
 vlib modelsim_lib/msim/xpm
 vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
 vmap xpm modelsim_lib/msim/xpm
 vlog -work xil_defaultlib -64 -incr -sv "+incdir+../../../ip/ila_rf_test/hdl/verilog" \
 "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
 "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
 vcom -work xpm -64 -93 \
 "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
 vlog -work xil_defaultlib -64 -incr "+incdir+../../../ip/ila_rf_test/hdl/verilog" \
 "../../../ip/ila_rf_test/sim/ila_rf_test.v" \
 vlog -work xil_defaultlib \
 "glbl.v"
@@ -1,2 +1,5 @@
 xpm_cdc.sv,systemverilog,xil_defaultlib,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rf_test/hdl/verilog"
 xpm_memory.sv,systemverilog,xil_defaultlib,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rf_test/hdl/verilog"
 xpm_VCOMP.vhd,vhdl,xpm,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rf_test/hdl/verilog"
 ila_rf_test.v,verilog,xil_defaultlib,../../../ip/ila_rf_test/sim/ila_rf_test.v,incdir="../../../ip/ila_rf_test/hdl/verilog"
 glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Thu May 18 12:54:21 CST 2023
+# Generated by Vivado on Mon Jul 03 19:45:33 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
@@ -95,10 +95,11 @@ setup()
 copy_setup_file()
 {
  file="modelsim.ini"
-  if [[ ($1 != "") ]]; then
+  lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
  if [[ ($1 != "" && -e $1) ]]; then
    lib_map_path="$1"
  else
-    lib_map_path="/home/josh/Software/Xilinx/CompLib/Model/2019.1"
+    echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
  fi
  if [[ ($lib_map_path != "") ]]; then
    src_file="$lib_map_path/$file"
@@ -1,7 +1,7 @@
 onbreak {quit -f}
 onerror {quit -f}
-vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.ila_rf_test xil_defaultlib.glbl
+vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.ila_rf_test xil_defaultlib.glbl
 do {wave.do}
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Thu May 18 12:54:21 CST 2023
+# Generated by export_simulation on Mon Jul 03 19:45:33 CST 2023
 #
 ################################################################################
@@ -8,11 +8,11 @@ vmap xil_defaultlib questa_lib/msim/xil_defaultlib
 vmap xpm questa_lib/msim/xpm
 vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/ila_rf_test/hdl/verilog" \
-"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
-"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
 vcom -work xpm -64 -93 \
-"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
 vlog -work xil_defaultlib -64 "+incdir+../../../ip/ila_rf_test/hdl/verilog" \
 "../../../ip/ila_rf_test/sim/ila_rf_test.v" \
@@ -1,5 +1,5 @@
-xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rf_test/hdl/verilog"
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rf_test/hdl/verilog"
-xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rf_test/hdl/verilog"
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rf_test/hdl/verilog"
-xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rf_test/hdl/verilog"
+xpm_VCOMP.vhd,vhdl,xpm,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rf_test/hdl/verilog"
 ila_rf_test.v,verilog,xil_defaultlib,../../../ip/ila_rf_test/sim/ila_rf_test.v,incdir="../../../ip/ila_rf_test/hdl/verilog"
 glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Thu May 18 12:54:21 CST 2023
+# Generated by Vivado on Mon Jul 03 19:45:33 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
@@ -102,10 +102,9 @@ setup()
 copy_setup_file()
 {
  file="modelsim.ini"
  lib_map_path=""
  if [[ ($1 != "") ]]; then
    lib_map_path="$1"
  else
    lib_map_path="/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa"
  fi
  if [[ ($lib_map_path != "") ]]; then
    src_file="$lib_map_path/$file"
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Thu May 18 12:54:21 CST 2023
+# Generated by export_simulation on Mon Jul 03 19:45:33 CST 2023
 #
 ################################################################################
@@ -8,11 +8,11 @@ vmap xil_defaultlib riviera/xil_defaultlib
 vmap xpm riviera/xpm
 vlog -work xil_defaultlib  -sv2k12 "+incdir+../../../ip/ila_rf_test/hdl/verilog" \
-"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
-"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
 vcom -work xpm -93 \
-"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
 vlog -work xil_defaultlib  -v2k5 "+incdir+../../../ip/ila_rf_test/hdl/verilog" \
 "../../../ip/ila_rf_test/sim/ila_rf_test.v" \
@@ -1,5 +1,5 @@
-xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rf_test/hdl/verilog"
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rf_test/hdl/verilog"
-xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rf_test/hdl/verilog"
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rf_test/hdl/verilog"
-xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rf_test/hdl/verilog"
+xpm_VCOMP.vhd,vhdl,xpm,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rf_test/hdl/verilog"
 ila_rf_test.v,verilog,xil_defaultlib,../../../ip/ila_rf_test/sim/ila_rf_test.v,incdir="../../../ip/ila_rf_test/hdl/verilog"
 glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Thu May 18 12:54:21 CST 2023
+# Generated by Vivado on Mon Jul 03 19:45:33 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
@@ -93,10 +93,9 @@ setup()
 map_setup_file()
 {
  file="library.cfg"
  lib_map_path=""
  if [[ ($1 != "") ]]; then
    lib_map_path="$1"
  else
    lib_map_path="/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera"
  fi
  if [[ ($lib_map_path != "") ]]; then
    src_file="$lib_map_path/$file"
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Thu May 18 12:54:21 CST 2023
+# Generated by export_simulation on Mon Jul 03 19:45:33 CST 2023
 #
 ################################################################################
@@ -1,2 +1,5 @@
 xpm_cdc.sv,systemverilog,xil_defaultlib,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rf_test/hdl/verilog"
 xpm_memory.sv,systemverilog,xil_defaultlib,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rf_test/hdl/verilog"
 xpm_VCOMP.vhd,vhdl,xpm,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rf_test/hdl/verilog"
 ila_rf_test.v,verilog,xil_defaultlib,../../../ip/ila_rf_test/sim/ila_rf_test.v,incdir="../../../ip/ila_rf_test/hdl/verilog"
 glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Thu May 18 12:54:21 CST 2023
+# Generated by Vivado on Mon Jul 03 19:45:33 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
@@ -48,7 +48,7 @@ vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log"
 vcs_sim_opts="-ucli -licqueue -l simulate.log"
 # Design libraries
-design_libs=(xil_defaultlib)
+design_libs=(xil_defaultlib xpm)
 # Simulation root library directory
 sim_lib_dir="vcs_lib"
@@ -70,6 +70,15 @@ run()
 compile()
 {
  # Compile design files
  vlogan -work xil_defaultlib $vlogan_opts -sverilog +incdir+"$ref_dir/../../../ip/ila_rf_test/hdl/verilog" \
    "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
    "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
  2>&1 | tee -a vlogan.log
  vhdlan -work xpm $vhdlan_opts \
    "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
  2>&1 | tee -a vhdlan.log
  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ip/ila_rf_test/hdl/verilog" \
    "$ref_dir/../../../ip/ila_rf_test/sim/ila_rf_test.v" \
  2>&1 | tee -a vlogan.log
@@ -138,10 +147,9 @@ create_lib_mappings()
  touch $file
  lib_map_path=""
  if [[ ($1 != "") ]]; then
    lib_map_path="$1"
  else
    lib_map_path="/home/josh/Software/Xilinx/CompLib/VCS/2019.1"
  fi
  for (( i=0; i<${#design_libs[*]}; i++ )); do
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Thu May 18 12:54:21 CST 2023
+# Generated by export_simulation on Mon Jul 03 19:45:33 CST 2023
 #
 ################################################################################
@@ -1,5 +1,5 @@
-xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rf_test/hdl/verilog"
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rf_test/hdl/verilog"
-xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rf_test/hdl/verilog"
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rf_test/hdl/verilog"
-xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rf_test/hdl/verilog"
+xpm_VCOMP.vhd,vhdl,xpm,../../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rf_test/hdl/verilog"
 ila_rf_test.v,verilog,xil_defaultlib,../../../ip/ila_rf_test/sim/ila_rf_test.v,incdir="../../../ip/ila_rf_test/hdl/verilog"
 glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Thu May 18 12:54:21 CST 2023
+# Generated by Vivado on Mon Jul 03 19:45:33 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
@@ -1,9 +1,9 @@
 -makelib xcelium_lib/xil_defaultlib -sv \
-  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+  "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
-  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+  "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
 -endlib
 -makelib xcelium_lib/xpm \
-  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+  "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
 -endlib
 -makelib xcelium_lib/xil_defaultlib \
  "../../../ip/ila_rf_test/sim/ila_rf_test.v" \
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Thu May 18 12:54:21 CST 2023
+# Generated by export_simulation on Mon Jul 03 19:45:33 CST 2023
 #
 ################################################################################
@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Thu May 18 12:54:21 CST 2023
+# Generated by Vivado on Mon Jul 03 19:45:33 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
@@ -22,7 +22,7 @@
 #*********************************************************************************************************
 # Command line options
-xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0
+xv_boost_lib_path=/home/josh/Software/Xilinx/Vivado/2019.1/tps/boost_1_64_0
 xvlog_opts="--relax"
@@ -92,7 +92,7 @@ setup()
 copy_setup_file()
 {
  file="xsim.ini"
-  lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim"
+  lib_map_path="/home/josh/Software/Xilinx/Vivado/2019.1/data/xsim"
  if [[ ($1 != "") ]]; then
    lib_map_path="$1"
  fi
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Thu May 18 11:36:22 CST 2023
+# Generated by export_simulation on Mon Jul 03 19:45:40 CST 2023
 #
 ################################################################################
@@ -12,7 +12,7 @@
 From the shell prompt in the current directory, issue the following command:-
-./vio_rf_control.sh
+./vio_RF_control.sh
 This command will launch the 'compile', 'elaborate' and 'simulate' functions
 implemented in the script file for the 3-step flow. These functions are called
@@ -26,16 +26,16 @@ current directory.
 The 'setup' function is also used for removing the simulator generated data in
 order to reset the current directory to the original state when export_simulation
 was launched from Vivado. This generated data can be removed by specifying the
-'-reset_run' switch to the './vio_rf_control.sh' script.
+'-reset_run' switch to the './vio_RF_control.sh' script.
-./vio_rf_control.sh -reset_run
+./vio_RF_control.sh -reset_run
 To keep the generated data from the previous run but regenerate the setup files and
 library directories, use the '-noclean_files' switch.
-./vio_rf_control.sh -noclean_files
+./vio_RF_control.sh -noclean_files
-For more information on the script, please type './vio_rf_control.sh -help'.
+For more information on the script, please type './vio_RF_control.sh -help'.
 2. Additional design information files:-
@@ -0,0 +1,22 @@
 vlib work
 vlib activehdl
 vlib activehdl/xil_defaultlib
 vlib activehdl/xpm
 vmap xil_defaultlib activehdl/xil_defaultlib
 vmap xpm activehdl/xpm
 vlog -work xil_defaultlib  -sv2k12 "+incdir+../../../ip/vio_RF_control/hdl/verilog" "+incdir+../../../ip/vio_RF_control/hdl" \
 "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
 "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
 vcom -work xpm -93 \
 "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
 vlog -work xil_defaultlib  -v2k5 "+incdir+../../../ip/vio_RF_control/hdl/verilog" "+incdir+../../../ip/vio_RF_control/hdl" \
 "../../../ip/vio_RF_control/sim/vio_RF_control.v" \
 vlog -work xil_defaultlib \
 "glbl.v"
@@ -0,0 +1,5 @@
 xpm_cdc.sv,systemverilog,xil_defaultlib,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl"
 xpm_memory.sv,systemverilog,xil_defaultlib,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl"
 xpm_VCOMP.vhd,vhdl,xpm,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl"
 vio_RF_control.v,verilog,xil_defaultlib,../../../ip/vio_RF_control/sim/vio_RF_control.v,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl"
 glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -1,14 +1,14 @@
 onbreak {quit -force}
 onerror {quit -force}
-asim -t 1ps +access +r +m+vio_rf_control -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.vio_rf_control xil_defaultlib.glbl
+asim -t 1ps +access +r +m+vio_RF_control -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.vio_RF_control xil_defaultlib.glbl
 do {wave.do}
 view wave
 view structure
-do {vio_rf_control.udo}
+do {vio_RF_control.udo}
 run -all
@@ -2,22 +2,22 @@
 #*********************************************************************************************************
 # Vivado (TM) v2019.1.3 (64-bit)
 #
-# Filename    : vio_rf_control.sh
+# Filename    : vio_RF_control.sh
 # Simulator   : Aldec Active-HDL Simulator
 # Description : Simulation script for compiling, elaborating and verifying the project source files.
 #               The script will automatically create the design libraries sub-directories in the run
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Thu May 18 11:36:22 CST 2023
+# Generated by Vivado on Mon Jul 03 19:45:40 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
 #
-# usage: vio_rf_control.sh [-help]
+# usage: vio_RF_control.sh [-help]
-# usage: vio_rf_control.sh [-lib_map_path]
+# usage: vio_RF_control.sh [-lib_map_path]
-# usage: vio_rf_control.sh [-noclean_files]
+# usage: vio_RF_control.sh [-noclean_files]
-# usage: vio_rf_control.sh [-reset_run]
+# usage: vio_RF_control.sh [-reset_run]
 #
 # Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
 # 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
@@ -27,7 +27,7 @@
 #
 # You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
 # script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
-# executing this script. Please type 'vio_rf_control.sh -help' for more information.
+# executing this script. Please type 'vio_RF_control.sh -help' for more information.
 #
 # Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
 #
@@ -35,7 +35,7 @@
 # Script info
-echo -e "vio_rf_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+echo -e "vio_RF_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
 # Main steps
 run()
@@ -66,7 +66,7 @@ setup()
  case $1 in
    "-lib_map_path" )
      if [[ ($2 == "") ]]; then
-        echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_control.sh -help\" for more information)\n"
+        echo -e "ERROR: Simulation library directory path not specified (type \"./vio_RF_control.sh -help\" for more information)\n"
        exit 1
      fi
     map_setup_file $2
@@ -121,7 +121,7 @@ reset_run()
 check_args()
 {
  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
-    echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_control.sh -help\" for more information)\n"
+    echo -e "ERROR: Unknown option specified '$2' (type \"./vio_RF_control.sh -help\" for more information)\n"
    exit 1
  fi
@@ -133,10 +133,10 @@ check_args()
 # Script usage
 usage()
 {
-  msg="Usage: vio_rf_control.sh [-help]\n\
+  msg="Usage: vio_RF_control.sh [-help]\n\
-Usage: vio_rf_control.sh [-lib_map_path]\n\
+Usage: vio_RF_control.sh [-lib_map_path]\n\
-Usage: vio_rf_control.sh [-reset_run]\n\
+Usage: vio_RF_control.sh [-reset_run]\n\
-Usage: vio_rf_control.sh [-noclean_files]\n\n\
+Usage: vio_RF_control.sh [-noclean_files]\n\n\
 [-help] -- Print help information for this script\n\n\
 [-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
 using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Thu May 18 11:36:22 CST 2023
+# Generated by export_simulation on Mon Jul 03 19:45:40 CST 2023
 #
 ################################################################################
@@ -12,7 +12,7 @@
 From the shell prompt in the current directory, issue the following command:-
-./vio_rf_control.sh
+./vio_RF_control.sh
 This command will launch the 'execute' function for the single-step flow. This
 function is called from the main 'run' function in the script file.
@@ -25,16 +25,16 @@ current directory.
 The 'setup' function is also used for removing the simulator generated data in
 order to reset the current directory to the original state when export_simulation
 was launched from Vivado. This generated data can be removed by specifying the
-'-reset_run' switch to the './vio_rf_control.sh' script.
+'-reset_run' switch to the './vio_RF_control.sh' script.
-./vio_rf_control.sh -reset_run
+./vio_RF_control.sh -reset_run
 To keep the generated data from the previous run but regenerate the setup files and
 library directories, use the '-noclean_files' switch.
-./vio_rf_control.sh -noclean_files
+./vio_RF_control.sh -noclean_files
-For more information on the script, please type './vio_rf_control.sh -help'.
+For more information on the script, please type './vio_RF_control.sh -help'.
 2. Additional design information files:-
@@ -0,0 +1,5 @@
 xpm_cdc.sv,systemverilog,xil_defaultlib,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl"
 xpm_memory.sv,systemverilog,xil_defaultlib,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl"
 xpm_VCOMP.vhd,vhdl,xpm,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl"
 vio_RF_control.v,verilog,xil_defaultlib,../../../ip/vio_RF_control/sim/vio_RF_control.v,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl"
 glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -0,0 +1,14 @@
 -makelib ies_lib/xil_defaultlib -sv \
  "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
  "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
 -endlib
 -makelib ies_lib/xpm \
  "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
 -endlib
 -makelib ies_lib/xil_defaultlib \
  "../../../ip/vio_RF_control/sim/vio_RF_control.v" \
 -endlib
 -makelib ies_lib/xil_defaultlib \
  glbl.v
 -endlib
@@ -2,22 +2,22 @@
 #*********************************************************************************************************
 # Vivado (TM) v2019.1.3 (64-bit)
 #
-# Filename    : vio_rf_control.sh
+# Filename    : vio_RF_control.sh
 # Simulator   : Cadence Incisive Enterprise Simulator
 # Description : Simulation script for compiling, elaborating and verifying the project source files.
 #               The script will automatically create the design libraries sub-directories in the run
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Thu May 18 11:36:22 CST 2023
+# Generated by Vivado on Mon Jul 03 19:45:40 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
 #
-# usage: vio_rf_control.sh [-help]
+# usage: vio_RF_control.sh [-help]
-# usage: vio_rf_control.sh [-lib_map_path]
+# usage: vio_RF_control.sh [-lib_map_path]
-# usage: vio_rf_control.sh [-noclean_files]
+# usage: vio_RF_control.sh [-noclean_files]
-# usage: vio_rf_control.sh [-reset_run]
+# usage: vio_RF_control.sh [-reset_run]
 #
 # Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
 # 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
@@ -27,7 +27,7 @@
 #
 # You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
 # script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
-# executing this script. Please type 'vio_rf_control.sh -help' for more information.
+# executing this script. Please type 'vio_RF_control.sh -help' for more information.
 #
 # Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
 #
@@ -54,7 +54,7 @@ design_libs=(xil_defaultlib xpm)
 sim_lib_dir="ies_lib"
 # Script info
-echo -e "vio_rf_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+echo -e "vio_RF_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
 # Main steps
 run()
@@ -73,12 +73,12 @@ execute()
       -reflib "$ref_lib_dir/secureip:secureip" \
       -reflib "$ref_lib_dir/unimacro:unimacro" \
       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
-       -top xil_defaultlib.vio_rf_control \
+       -top xil_defaultlib.vio_RF_control \
       -f run.f \
       -top glbl \
       glbl.v \
-       +incdir+"../../../ip/vio_rf_control/hdl/verilog" \
+       +incdir+"../../../ip/vio_RF_control/hdl/verilog" \
-       +incdir+"../../../ip/vio_rf_control/hdl"
+       +incdir+"../../../ip/vio_RF_control/hdl"
 }
 # STEP: setup
@@ -87,7 +87,7 @@ setup()
  case $1 in
    "-lib_map_path" )
      if [[ ($2 == "") ]]; then
-        echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_control.sh -help\" for more information)\n"
+        echo -e "ERROR: Simulation library directory path not specified (type \"./vio_RF_control.sh -help\" for more information)\n"
        exit 1
      else
        ref_lib_dir=$2
@@ -146,7 +146,7 @@ reset_run()
 check_args()
 {
  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
-    echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_control.sh -help\" for more information)\n"
+    echo -e "ERROR: Unknown option specified '$2' (type \"./vio_RF_control.sh -help\" for more information)\n"
    exit 1
  fi
@@ -158,10 +158,10 @@ check_args()
 # Script usage
 usage()
 {
-  msg="Usage: vio_rf_control.sh [-help]\n\
+  msg="Usage: vio_RF_control.sh [-help]\n\
-Usage: vio_rf_control.sh [-lib_map_path]\n\
+Usage: vio_RF_control.sh [-lib_map_path]\n\
-Usage: vio_rf_control.sh [-reset_run]\n\
+Usage: vio_RF_control.sh [-reset_run]\n\
-Usage: vio_rf_control.sh [-noclean_files]\n\n\
+Usage: vio_RF_control.sh [-noclean_files]\n\n\
 [-help] -- Print help information for this script\n\n\
 [-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
 using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Thu May 18 11:36:22 CST 2023
+# Generated by export_simulation on Mon Jul 03 19:45:40 CST 2023
 #
 ################################################################################
@@ -12,7 +12,7 @@
 From the shell prompt in the current directory, issue the following command:-
-./vio_rf_control.sh
+./vio_RF_control.sh
 This command will launch the 'compile', 'elaborate' and 'simulate' functions
 implemented in the script file for the 3-step flow. These functions are called
@@ -26,16 +26,16 @@ current directory.
 The 'setup' function is also used for removing the simulator generated data in
 order to reset the current directory to the original state when export_simulation
 was launched from Vivado. This generated data can be removed by specifying the
-'-reset_run' switch to the './vio_rf_control.sh' script.
+'-reset_run' switch to the './vio_RF_control.sh' script.
-./vio_rf_control.sh -reset_run
+./vio_RF_control.sh -reset_run
 To keep the generated data from the previous run but regenerate the setup files and
 library directories, use the '-noclean_files' switch.
-./vio_rf_control.sh -noclean_files
+./vio_RF_control.sh -noclean_files
-For more information on the script, please type './vio_rf_control.sh -help'.
+For more information on the script, please type './vio_RF_control.sh -help'.
 2. Additional design information files:-
@@ -5,8 +5,8 @@ vlib modelsim_lib/msim/xil_defaultlib
 vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
-vlog -work xil_defaultlib -64 -incr "+incdir+../../../ip/vio_rf_test/hdl/verilog" "+incdir+../../../ip/vio_rf_test/hdl" \
+vlog -work xil_defaultlib -64 -incr "+incdir+../../../ip/vio_RF_control/hdl/verilog" "+incdir+../../../ip/vio_RF_control/hdl" \
-"../../../ip/vio_rf_test/sim/vio_rf_test.v" \
+"../../../ip/vio_RF_control/sim/vio_RF_control.v" \
 vlog -work xil_defaultlib \
@@ -0,0 +1,2 @@
 vio_RF_control.v,verilog,xil_defaultlib,../../../ip/vio_RF_control/sim/vio_RF_control.v,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl"
 glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -1,7 +1,7 @@
 onbreak {quit -f}
 onerror {quit -f}
-vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.vio_rf_test xil_defaultlib.glbl
+vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.vio_RF_control xil_defaultlib.glbl
 do {wave.do}
@@ -9,7 +9,7 @@ view wave
 view structure
 view signals
-do {vio_rf_test.udo}
+do {vio_RF_control.udo}
 run -all
@@ -2,22 +2,22 @@
 #*********************************************************************************************************
 # Vivado (TM) v2019.1.3 (64-bit)
 #
-# Filename    : vio_rf_control.sh
+# Filename    : vio_RF_control.sh
 # Simulator   : Mentor Graphics ModelSim Simulator
 # Description : Simulation script for compiling, elaborating and verifying the project source files.
 #               The script will automatically create the design libraries sub-directories in the run
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Thu May 18 11:36:22 CST 2023
+# Generated by Vivado on Mon Jul 03 19:45:40 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
 #
-# usage: vio_rf_control.sh [-help]
+# usage: vio_RF_control.sh [-help]
-# usage: vio_rf_control.sh [-lib_map_path]
+# usage: vio_RF_control.sh [-lib_map_path]
-# usage: vio_rf_control.sh [-noclean_files]
+# usage: vio_RF_control.sh [-noclean_files]
-# usage: vio_rf_control.sh [-reset_run]
+# usage: vio_RF_control.sh [-reset_run]
 #
 # Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
 # 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
@@ -27,7 +27,7 @@
 #
 # You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
 # script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
-# executing this script. Please type 'vio_rf_control.sh -help' for more information.
+# executing this script. Please type 'vio_RF_control.sh -help' for more information.
 #
 # Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
 #
@@ -35,7 +35,7 @@
 # Script info
-echo -e "vio_rf_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+echo -e "vio_RF_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
 # Main steps
 run()
@@ -66,7 +66,7 @@ setup()
  case $1 in
    "-lib_map_path" )
      if [[ ($2 == "") ]]; then
-        echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_control.sh -help\" for more information)\n"
+        echo -e "ERROR: Simulation library directory path not specified (type \"./vio_RF_control.sh -help\" for more information)\n"
        exit 1
      fi
     copy_setup_file $2
@@ -136,7 +136,7 @@ reset_run()
 check_args()
 {
  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
-    echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_control.sh -help\" for more information)\n"
+    echo -e "ERROR: Unknown option specified '$2' (type \"./vio_RF_control.sh -help\" for more information)\n"
    exit 1
  fi
@@ -148,10 +148,10 @@ check_args()
 # Script usage
 usage()
 {
-  msg="Usage: vio_rf_control.sh [-help]\n\
+  msg="Usage: vio_RF_control.sh [-help]\n\
-Usage: vio_rf_control.sh [-lib_map_path]\n\
+Usage: vio_RF_control.sh [-lib_map_path]\n\
-Usage: vio_rf_control.sh [-reset_run]\n\
+Usage: vio_RF_control.sh [-reset_run]\n\
-Usage: vio_rf_control.sh [-noclean_files]\n\n\
+Usage: vio_RF_control.sh [-noclean_files]\n\n\
 [-help] -- Print help information for this script\n\n\
 [-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
 using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Thu May 18 11:36:22 CST 2023
+# Generated by export_simulation on Mon Jul 03 19:45:40 CST 2023
 #
 ################################################################################
@@ -12,7 +12,7 @@
 From the shell prompt in the current directory, issue the following command:-
-./vio_rf_control.sh
+./vio_RF_control.sh
 This command will launch the 'compile', 'elaborate' and 'simulate' functions
 implemented in the script file for the 3-step flow. These functions are called
@@ -26,16 +26,16 @@ current directory.
 The 'setup' function is also used for removing the simulator generated data in
 order to reset the current directory to the original state when export_simulation
 was launched from Vivado. This generated data can be removed by specifying the
-'-reset_run' switch to the './vio_rf_control.sh' script.
+'-reset_run' switch to the './vio_RF_control.sh' script.
-./vio_rf_control.sh -reset_run
+./vio_RF_control.sh -reset_run
 To keep the generated data from the previous run but regenerate the setup files and
 library directories, use the '-noclean_files' switch.
-./vio_rf_control.sh -noclean_files
+./vio_RF_control.sh -noclean_files
-For more information on the script, please type './vio_rf_control.sh -help'.
+For more information on the script, please type './vio_RF_control.sh -help'.
 2. Additional design information files:-
@@ -0,0 +1,22 @@
 vlib questa_lib/work
 vlib questa_lib/msim
 vlib questa_lib/msim/xil_defaultlib
 vlib questa_lib/msim/xpm
 vmap xil_defaultlib questa_lib/msim/xil_defaultlib
 vmap xpm questa_lib/msim/xpm
 vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/vio_RF_control/hdl/verilog" "+incdir+../../../ip/vio_RF_control/hdl" \
 "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
 "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
 vcom -work xpm -64 -93 \
 "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
 vlog -work xil_defaultlib -64 "+incdir+../../../ip/vio_RF_control/hdl/verilog" "+incdir+../../../ip/vio_RF_control/hdl" \
 "../../../ip/vio_RF_control/sim/vio_RF_control.v" \
 vlog -work xil_defaultlib \
 "glbl.v"
@@ -1 +1 @@
-vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.vio_rf_control xil_defaultlib.glbl -o vio_rf_control_opt
+vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.vio_RF_control xil_defaultlib.glbl -o vio_RF_control_opt
@@ -0,0 +1,5 @@
 xpm_cdc.sv,systemverilog,xil_defaultlib,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl"
 xpm_memory.sv,systemverilog,xil_defaultlib,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl"
 xpm_VCOMP.vhd,vhdl,xpm,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl"
 vio_RF_control.v,verilog,xil_defaultlib,../../../ip/vio_RF_control/sim/vio_RF_control.v,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl"
 glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -1,7 +1,7 @@
 onbreak {quit -f}
 onerror {quit -f}
-vsim -t 1ps -lib xil_defaultlib vio_rf_test_opt
+vsim -t 1ps -lib xil_defaultlib vio_RF_control_opt
 do {wave.do}
@@ -9,7 +9,7 @@ view wave
 view structure
 view signals
-do {vio_rf_test.udo}
+do {vio_RF_control.udo}
 run -all
@@ -2,22 +2,22 @@
 #*********************************************************************************************************
 # Vivado (TM) v2019.1.3 (64-bit)
 #
-# Filename    : vio_rf_control.sh
+# Filename    : vio_RF_control.sh
 # Simulator   : Mentor Graphics Questa Advanced Simulator
 # Description : Simulation script for compiling, elaborating and verifying the project source files.
 #               The script will automatically create the design libraries sub-directories in the run
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Thu May 18 11:36:22 CST 2023
+# Generated by Vivado on Mon Jul 03 19:45:40 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
 #
-# usage: vio_rf_control.sh [-help]
+# usage: vio_RF_control.sh [-help]
-# usage: vio_rf_control.sh [-lib_map_path]
+# usage: vio_RF_control.sh [-lib_map_path]
-# usage: vio_rf_control.sh [-noclean_files]
+# usage: vio_RF_control.sh [-noclean_files]
-# usage: vio_rf_control.sh [-reset_run]
+# usage: vio_RF_control.sh [-reset_run]
 #
 # Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
 # 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
@@ -27,7 +27,7 @@
 #
 # You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
 # script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
-# executing this script. Please type 'vio_rf_control.sh -help' for more information.
+# executing this script. Please type 'vio_RF_control.sh -help' for more information.
 #
 # Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
 #
@@ -35,7 +35,7 @@
 # Script info
-echo -e "vio_rf_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+echo -e "vio_RF_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
 # Main steps
 run()
@@ -73,7 +73,7 @@ setup()
  case $1 in
    "-lib_map_path" )
      if [[ ($2 == "") ]]; then
-        echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_control.sh -help\" for more information)\n"
+        echo -e "ERROR: Simulation library directory path not specified (type \"./vio_RF_control.sh -help\" for more information)\n"
        exit 1
      fi
     copy_setup_file $2
@@ -143,7 +143,7 @@ reset_run()
 check_args()
 {
  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
-    echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_control.sh -help\" for more information)\n"
+    echo -e "ERROR: Unknown option specified '$2' (type \"./vio_RF_control.sh -help\" for more information)\n"
    exit 1
  fi
@@ -155,10 +155,10 @@ check_args()
 # Script usage
 usage()
 {
-  msg="Usage: vio_rf_control.sh [-help]\n\
+  msg="Usage: vio_RF_control.sh [-help]\n\
-Usage: vio_rf_control.sh [-lib_map_path]\n\
+Usage: vio_RF_control.sh [-lib_map_path]\n\
-Usage: vio_rf_control.sh [-reset_run]\n\
+Usage: vio_RF_control.sh [-reset_run]\n\
-Usage: vio_rf_control.sh [-noclean_files]\n\n\
+Usage: vio_RF_control.sh [-noclean_files]\n\n\
 [-help] -- Print help information for this script\n\n\
 [-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
 using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Thu May 18 11:36:22 CST 2023
+# Generated by export_simulation on Mon Jul 03 19:45:40 CST 2023
 #
 ################################################################################
@@ -12,7 +12,7 @@
 From the shell prompt in the current directory, issue the following command:-
-./vio_rf_control.sh
+./vio_RF_control.sh
 This command will launch the 'compile', 'elaborate' and 'simulate' functions
 implemented in the script file for the 3-step flow. These functions are called
@@ -26,16 +26,16 @@ current directory.
 The 'setup' function is also used for removing the simulator generated data in
 order to reset the current directory to the original state when export_simulation
 was launched from Vivado. This generated data can be removed by specifying the
-'-reset_run' switch to the './vio_rf_control.sh' script.
+'-reset_run' switch to the './vio_RF_control.sh' script.
-./vio_rf_control.sh -reset_run
+./vio_RF_control.sh -reset_run
 To keep the generated data from the previous run but regenerate the setup files and
 library directories, use the '-noclean_files' switch.
-./vio_rf_control.sh -noclean_files
+./vio_RF_control.sh -noclean_files
-For more information on the script, please type './vio_rf_control.sh -help'.
+For more information on the script, please type './vio_RF_control.sh -help'.
 2. Additional design information files:-
@@ -0,0 +1,22 @@
 vlib work
 vlib riviera
 vlib riviera/xil_defaultlib
 vlib riviera/xpm
 vmap xil_defaultlib riviera/xil_defaultlib
 vmap xpm riviera/xpm
 vlog -work xil_defaultlib  -sv2k12 "+incdir+../../../ip/vio_RF_control/hdl/verilog" "+incdir+../../../ip/vio_RF_control/hdl" \
 "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
 "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
 vcom -work xpm -93 \
 "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
 vlog -work xil_defaultlib  -v2k5 "+incdir+../../../ip/vio_RF_control/hdl/verilog" "+incdir+../../../ip/vio_RF_control/hdl" \
 "../../../ip/vio_RF_control/sim/vio_RF_control.v" \
 vlog -work xil_defaultlib \
 "glbl.v"
@@ -0,0 +1,5 @@
 xpm_cdc.sv,systemverilog,xil_defaultlib,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl"
 xpm_memory.sv,systemverilog,xil_defaultlib,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl"
 xpm_VCOMP.vhd,vhdl,xpm,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl"
 vio_RF_control.v,verilog,xil_defaultlib,../../../ip/vio_RF_control/sim/vio_RF_control.v,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl"
 glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -1,14 +1,14 @@
 onbreak {quit -force}
 onerror {quit -force}
-asim -t 1ps +access +r +m+vio_rf_control -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.vio_rf_control xil_defaultlib.glbl
+asim -t 1ps +access +r +m+vio_RF_control -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.vio_RF_control xil_defaultlib.glbl
 do {wave.do}
 view wave
 view structure
-do {vio_rf_control.udo}
+do {vio_RF_control.udo}
 run -all
@@ -2,22 +2,22 @@
 #*********************************************************************************************************
 # Vivado (TM) v2019.1.3 (64-bit)
 #
-# Filename    : vio_rf_control.sh
+# Filename    : vio_RF_control.sh
 # Simulator   : Aldec Riviera-PRO Simulator
 # Description : Simulation script for compiling, elaborating and verifying the project source files.
 #               The script will automatically create the design libraries sub-directories in the run
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Thu May 18 11:36:22 CST 2023
+# Generated by Vivado on Mon Jul 03 19:45:40 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
 #
-# usage: vio_rf_control.sh [-help]
+# usage: vio_RF_control.sh [-help]
-# usage: vio_rf_control.sh [-lib_map_path]
+# usage: vio_RF_control.sh [-lib_map_path]
-# usage: vio_rf_control.sh [-noclean_files]
+# usage: vio_RF_control.sh [-noclean_files]
-# usage: vio_rf_control.sh [-reset_run]
+# usage: vio_RF_control.sh [-reset_run]
 #
 # Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
 # 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
@@ -27,7 +27,7 @@
 #
 # You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
 # script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
-# executing this script. Please type 'vio_rf_control.sh -help' for more information.
+# executing this script. Please type 'vio_RF_control.sh -help' for more information.
 #
 # Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
 #
@@ -35,7 +35,7 @@
 # Script info
-echo -e "vio_rf_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+echo -e "vio_RF_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
 # Main steps
 run()
@@ -66,7 +66,7 @@ setup()
  case $1 in
    "-lib_map_path" )
      if [[ ($2 == "") ]]; then
-        echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_control.sh -help\" for more information)\n"
+        echo -e "ERROR: Simulation library directory path not specified (type \"./vio_RF_control.sh -help\" for more information)\n"
        exit 1
      fi
     map_setup_file $2
@@ -122,7 +122,7 @@ reset_run()
 check_args()
 {
  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
-    echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_control.sh -help\" for more information)\n"
+    echo -e "ERROR: Unknown option specified '$2' (type \"./vio_RF_control.sh -help\" for more information)\n"
    exit 1
  fi
@@ -134,10 +134,10 @@ check_args()
 # Script usage
 usage()
 {
-  msg="Usage: vio_rf_control.sh [-help]\n\
+  msg="Usage: vio_RF_control.sh [-help]\n\
-Usage: vio_rf_control.sh [-lib_map_path]\n\
+Usage: vio_RF_control.sh [-lib_map_path]\n\
-Usage: vio_rf_control.sh [-reset_run]\n\
+Usage: vio_RF_control.sh [-reset_run]\n\
-Usage: vio_rf_control.sh [-noclean_files]\n\n\
+Usage: vio_RF_control.sh [-noclean_files]\n\n\
 [-help] -- Print help information for this script\n\n\
 [-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
 using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
@@ -0,0 +1,49 @@
 ################################################################################
 # Vivado (TM) v2019.1.3 (64-bit)
 #
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
 # Generated by export_simulation on Mon Jul 03 19:45:40 CST 2023
 #
 ################################################################################
 1. How to run the generated simulation script:-
 From the shell prompt in the current directory, issue the following command:-
 ./vio_RF_control.sh
 This command will launch the 'compile', 'elaborate' and 'simulate' functions
 implemented in the script file for the 3-step flow. These functions are called
 from the main 'run' function in the script file.
 The 'run' function first executes the 'setup' function, the purpose of which is to
 create simulator specific setup files, create design library mappings and library
 directories and copy 'glbl.v' from the Vivado software install location into the
 current directory.
 The 'setup' function is also used for removing the simulator generated data in
 order to reset the current directory to the original state when export_simulation
 was launched from Vivado. This generated data can be removed by specifying the
 '-reset_run' switch to the './vio_RF_control.sh' script.
 ./vio_RF_control.sh -reset_run
 To keep the generated data from the previous run but regenerate the setup files and
 library directories, use the '-noclean_files' switch.
 ./vio_RF_control.sh -noclean_files
 For more information on the script, please type './vio_RF_control.sh -help'.
 2. Additional design information files:-
 export_simulation generates following additional file that can be used for fetching
 the design files information or for integrating with external custom scripts.
 Name   : file_info.txt
 Purpose: This file contains detail design file information based on the compile order
         when export_simulation was executed from Vivado. The file contains information
         about the file type, name, whether it is part of the IP, associated library
         and the file path information.
@@ -0,0 +1,2 @@
 vio_RF_control.v,verilog,xil_defaultlib,../../../ip/vio_RF_control/sim/vio_RF_control.v,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl"
 glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -2,22 +2,22 @@
 #*********************************************************************************************************
 # Vivado (TM) v2019.1.3 (64-bit)
 #
-# Filename    : vio_rf_control.sh
+# Filename    : vio_RF_control.sh
 # Simulator   : Synopsys Verilog Compiler Simulator
 # Description : Simulation script for compiling, elaborating and verifying the project source files.
 #               The script will automatically create the design libraries sub-directories in the run
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Thu May 18 11:36:22 CST 2023
+# Generated by Vivado on Mon Jul 03 19:45:40 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
 #
-# usage: vio_rf_control.sh [-help]
+# usage: vio_RF_control.sh [-help]
-# usage: vio_rf_control.sh [-lib_map_path]
+# usage: vio_RF_control.sh [-lib_map_path]
-# usage: vio_rf_control.sh [-noclean_files]
+# usage: vio_RF_control.sh [-noclean_files]
-# usage: vio_rf_control.sh [-reset_run]
+# usage: vio_RF_control.sh [-reset_run]
 #
 # Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
 # 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
@@ -27,7 +27,7 @@
 #
 # You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
 # script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
-# executing this script. Please type 'vio_rf_control.sh -help' for more information.
+# executing this script. Please type 'vio_RF_control.sh -help' for more information.
 #
 # Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
 #
@@ -54,7 +54,7 @@ design_libs=(xil_defaultlib)
 sim_lib_dir="vcs_lib"
 # Script info
-echo -e "vio_rf_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+echo -e "vio_RF_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
 # Main steps
 run()
@@ -70,8 +70,8 @@ run()
 compile()
 {
  # Compile design files
-  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ip/vio_rf_control/hdl/verilog" +incdir+"$ref_dir/../../../ip/vio_rf_control/hdl" \
+  vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ip/vio_RF_control/hdl/verilog" +incdir+"$ref_dir/../../../ip/vio_RF_control/hdl" \
-    "$ref_dir/../../../ip/vio_rf_control/sim/vio_rf_control.v" \
+    "$ref_dir/../../../ip/vio_RF_control/sim/vio_RF_control.v" \
  2>&1 | tee -a vlogan.log
@@ -84,13 +84,13 @@ compile()
 # RUN_STEP: <elaborate>
 elaborate()
 {
-  vcs $vcs_elab_opts xil_defaultlib.vio_rf_control xil_defaultlib.glbl -o vio_rf_control_simv
+  vcs $vcs_elab_opts xil_defaultlib.vio_RF_control xil_defaultlib.glbl -o vio_RF_control_simv
 }
 # RUN_STEP: <simulate>
 simulate()
 {
-  ./vio_rf_control_simv $vcs_sim_opts -do simulate.do
+  ./vio_RF_control_simv $vcs_sim_opts -do simulate.do
 }
 # STEP: setup
@@ -99,7 +99,7 @@ setup()
  case $1 in
    "-lib_map_path" )
      if [[ ($2 == "") ]]; then
-        echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_control.sh -help\" for more information)\n"
+        echo -e "ERROR: Simulation library directory path not specified (type \"./vio_RF_control.sh -help\" for more information)\n"
        exit 1
      fi
      create_lib_mappings $2
@@ -175,7 +175,7 @@ create_lib_dir()
 # Delete generated data from the previous run
 reset_run()
 {
-  files_to_remove=(ucli.key vio_rf_control_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc vio_rf_control_simv.daidir)
+  files_to_remove=(ucli.key vio_RF_control_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc vio_RF_control_simv.daidir)
  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
    file="${files_to_remove[i]}"
    if [[ -e $file ]]; then
@@ -190,7 +190,7 @@ reset_run()
 check_args()
 {
  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
-    echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_control.sh -help\" for more information)\n"
+    echo -e "ERROR: Unknown option specified '$2' (type \"./vio_RF_control.sh -help\" for more information)\n"
    exit 1
  fi
@@ -202,10 +202,10 @@ check_args()
 # Script usage
 usage()
 {
-  msg="Usage: vio_rf_control.sh [-help]\n\
+  msg="Usage: vio_RF_control.sh [-help]\n\
-Usage: vio_rf_control.sh [-lib_map_path]\n\
+Usage: vio_RF_control.sh [-lib_map_path]\n\
-Usage: vio_rf_control.sh [-reset_run]\n\
+Usage: vio_RF_control.sh [-reset_run]\n\
-Usage: vio_rf_control.sh [-noclean_files]\n\n\
+Usage: vio_RF_control.sh [-noclean_files]\n\n\
 [-help] -- Print help information for this script\n\n\
 [-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
 using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
--- a/Show More
+++ b/Show More
		`@@ -0,0 +1,2 @@`
							`vio_RF_control.v,verilog,xil_defaultlib,../../../ip/vio_RF_control/sim/vio_RF_control.v,incdir="../../../ip/vio_RF_control/hdl/verilog"incdir="../../../ip/vio_RF_control/hdl"`
							`glbl.v,Verilog,xil_defaultlib,glbl.v`
		`@@ -1 +1 @@`
			`vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.vio_rf_control xil_defaultlib.glbl -o vio_rf_control_opt`				`vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.vio_RF_control xil_defaultlib.glbl -o vio_RF_control_opt`