add phase compensate to duifei online acq

2023-05-16 20:44:17 +08:00
parent 986a2ea1e1
commit b2a6a62da0
249 changed files with 15824 additions and 2162 deletions
@@ -0,0 +1,258 @@
+RADIX = 10;
+COEFDATA = 
+1,
+1,
+1,
+1,
+1,
+1,
+1,
+1,
+1,
+1,
+1,
+1,
+-1,
+-1,
+-1,
+-1,
+1,
+1,
+1,
+1,
+1,
+1,
+1,
+1,
+-1,
+-1,
+1,
+1,
+-1,
+-1,
+1,
+1,
+1,
+1,
+1,
+1,
+-1,
+-1,
+-1,
+-1,
+-1,
+-1,
+-1,
+-1,
+1,
+1,
+1,
+1,
+-1,
+-1,
+1,
+1,
+1,
+1,
+1,
+1,
+-1,
+-1,
+1,
+1,
+-1,
+-1,
+-1,
+-1,
+1,
+1,
+1,
+1,
+-1,
+-1,
+-1,
+-1,
+-1,
+-1,
+1,
+1,
+-1,
+-1,
+1,
+1,
+-1,
+-1,
+1,
+1,
+1,
+1,
+-1,
+-1,
+-1,
+-1,
+-1,
+-1,
+-1,
+-1,
+-1,
+-1,
+1,
+1,
+-1,
+-1,
+1,
+1,
+1,
+1,
+1,
+1,
+1,
+1,
+-1,
+-1,
+-1,
+-1,
+-1,
+-1,
+1,
+1,
+1,
+1,
+1,
+1,
+-1,
+-1,
+1,
+1,
+1,
+1,
+-1,
+-1,
+1,
+1,
+1,
+1,
+-1,
+-1,
+-1,
+-1,
+1,
+1,
+-1,
+-1,
+-1,
+-1,
+1,
+1,
+-1,
+-1,
+1,
+1,
+-1,
+-1,
+-1,
+-1,
+1,
+1,
+-1,
+-1,
+-1,
+-1,
+-1,
+-1,
+-1,
+-1,
+1,
+1,
+-1,
+-1,
+-1,
+-1,
+1,
+1,
+1,
+1,
+1,
+1,
+-1,
+-1,
+-1,
+-1,
+1,
+1,
+-1,
+-1,
+1,
+1,
+1,
+1,
+-1,
+-1,
+1,
+1,
+-1,
+-1,
+-1,
+-1,
+-1,
+-1,
+1,
+1,
+-1,
+-1,
+-1,
+-1,
+-1,
+-1,
+1,
+1,
+1,
+1,
+-1,
+-1,
+-1,
+-1,
+1,
+1,
+1,
+1,
+-1,
+-1,
+1,
+1,
+-1,
+-1,
+1,
+1,
+-1,
+-1,
+1,
+1,
+-1,
+-1,
+-1,
+-1,
+-1,
+-1,
+-1,
+-1,
+-1,
+-1,
+-1,
+-1,
+-1,
+-1,
+1,
+1,
+1,
+1,
+1,
+1,
+1,
+1,
+1,
+1,
+1,
+1,
+-1,
+-1;
@@ -0,0 +1,71 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+// IP VLNV: xilinx.com:ip:cmpy:6.0
+// IP Revision: 17
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+cmpy_12_12 your_instance_name (
+  .aclk(aclk),                              // input wire aclk
+  .s_axis_a_tvalid(s_axis_a_tvalid),        // input wire s_axis_a_tvalid
+  .s_axis_a_tdata(s_axis_a_tdata),          // input wire [31 : 0] s_axis_a_tdata
+  .s_axis_b_tvalid(s_axis_b_tvalid),        // input wire s_axis_b_tvalid
+  .s_axis_b_tdata(s_axis_b_tdata),          // input wire [31 : 0] s_axis_b_tdata
+  .m_axis_dout_tvalid(m_axis_dout_tvalid),  // output wire m_axis_dout_tvalid
+  .m_axis_dout_tdata(m_axis_dout_tdata)    // output wire [63 : 0] m_axis_dout_tdata
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file cmpy_12_12.v when simulating
+// the core, cmpy_12_12. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+
@@ -0,0 +1,87 @@
+-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:cmpy:6.0
+-- IP Revision: 17
+
+-- The following code must appear in the VHDL architecture header.
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT cmpy_12_12
+  PORT (
+    aclk : IN STD_LOGIC;
+    s_axis_a_tvalid : IN STD_LOGIC;
+    s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axis_b_tvalid : IN STD_LOGIC;
+    s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    m_axis_dout_tvalid : OUT STD_LOGIC;
+    m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
+  );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : cmpy_12_12
+  PORT MAP (
+    aclk => aclk,
+    s_axis_a_tvalid => s_axis_a_tvalid,
+    s_axis_a_tdata => s_axis_a_tdata,
+    s_axis_b_tvalid => s_axis_b_tvalid,
+    s_axis_b_tdata => s_axis_b_tdata,
+    m_axis_dout_tvalid => m_axis_dout_tvalid,
+    m_axis_dout_tdata => m_axis_dout_tdata
+  );
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+-- You must compile the wrapper file cmpy_12_12.vhd when simulating
+-- the core, cmpy_12_12. When compiling the wrapper file, be sure to
+-- reference the VHDL simulation library.
+
@@ -0,0 +1,27 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
+// Date        : Tue May 16 02:16:23 2023
+// Host        : DESKTOP-3AAKI0I running 64-bit major release  (build 9200)
+// Command     : write_verilog -force -mode synth_stub
+//               E:/DF/df_datalink_v0/df_datalink_v0.runs/cmpy_12_12_synth_1/cmpy_12_12_stub.v
+// Design      : cmpy_12_12
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z100ffg900-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "cmpy_v6_0_17,Vivado 2019.1" *)
+module cmpy_12_12(aclk, s_axis_a_tvalid, s_axis_a_tdata, 
+  s_axis_b_tvalid, s_axis_b_tdata, m_axis_dout_tvalid, m_axis_dout_tdata)
+/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_a_tvalid,s_axis_a_tdata[31:0],s_axis_b_tvalid,s_axis_b_tdata[31:0],m_axis_dout_tvalid,m_axis_dout_tdata[63:0]" */;
+  input aclk;
+  input s_axis_a_tvalid;
+  input [31:0]s_axis_a_tdata;
+  input s_axis_b_tvalid;
+  input [31:0]s_axis_b_tdata;
+  output m_axis_dout_tvalid;
+  output [63:0]m_axis_dout_tdata;
+endmodule
@@ -0,0 +1,36 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
+-- Date        : Tue May 16 02:16:23 2023
+-- Host        : DESKTOP-3AAKI0I running 64-bit major release  (build 9200)
+-- Command     : write_vhdl -force -mode synth_stub
+--               E:/DF/df_datalink_v0/df_datalink_v0.runs/cmpy_12_12_synth_1/cmpy_12_12_stub.vhdl
+-- Design      : cmpy_12_12
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7z100ffg900-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity cmpy_12_12 is
+  Port ( 
+    aclk : in STD_LOGIC;
+    s_axis_a_tvalid : in STD_LOGIC;
+    s_axis_a_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    s_axis_b_tvalid : in STD_LOGIC;
+    s_axis_b_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    m_axis_dout_tvalid : out STD_LOGIC;
+    m_axis_dout_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 )
+  );
+
+end cmpy_12_12;
+
+architecture stub of cmpy_12_12 is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_a_tvalid,s_axis_a_tdata[31:0],s_axis_b_tvalid,s_axis_b_tdata[31:0],m_axis_dout_tvalid,m_axis_dout_tdata[63:0]";
+attribute x_core_info : string;
+attribute x_core_info of stub : architecture is "cmpy_v6_0_17,Vivado 2019.1";
+begin
+end;
@@ -0,0 +1,389 @@
+--------------------------------------------------------------------------------
+-- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--------------------------------------------------------------------------------
+-- Description:
+-- This is an example testbench for the Complex Multiplier IP core.
+-- The testbench has been generated by Vivado to accompany the IP core
+-- instance you have generated.
+--
+-- This testbench is for demonstration purposes only.  See note below for
+-- instructions on how to use it with your core.
+--
+-- See the Complex Multiplier product guide for further information
+-- about this core.
+--
+--------------------------------------------------------------------------------
+-- Using this testbench
+--
+-- This testbench instantiates your generated Complex Multiplier core
+-- instance named "cmpy_12_12".
+--
+-- Use Vivado's Run Simulation flow to run this testbench.  See the Vivado
+-- documentation for details.
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.math_real.all;
+
+entity tb_cmpy_12_12 is
+end tb_cmpy_12_12;
+
+architecture tb of tb_cmpy_12_12 is
+
+  -----------------------------------------------------------------------
+  -- Timing constants
+  -----------------------------------------------------------------------
+  constant CLOCK_PERIOD : time := 100 ns;
+  constant T_HOLD       : time := 10 ns;
+  constant T_STROBE     : time := CLOCK_PERIOD - (1 ns);
+  constant TEST_CYCLES  : integer := 3000;
+  constant PHASE_CYCLES : integer := 1000;
+
+  -----------------------------------------------------------------------
+  -- DUT input signals
+  -----------------------------------------------------------------------
+
+  -- General inputs
+  signal aclk               : std_logic := '0';  -- the master clock
+
+  -- Slave channel A inputs
+  signal s_axis_a_tvalid    : std_logic := '0';  -- TVALID for channel A
+  signal s_axis_a_tdata     : std_logic_vector(31 downto 0) := (others => '0');  -- TDATA for channel A
+
+  -- Slave channel B inputs
+  signal s_axis_b_tvalid    : std_logic := '0';  -- TVALID for channel B
+  signal s_axis_b_tdata     : std_logic_vector(31 downto 0) := (others => '0');  -- TDATA for channel B
+
+  -----------------------------------------------------------------------
+  -- DUT output signals
+  -----------------------------------------------------------------------
+
+  -- Master channel DOUT outputs
+  signal m_axis_dout_tvalid : std_logic := '0';  -- TVALID for channel DOUT
+  signal m_axis_dout_tdata  : std_logic_vector(63 downto 0) := (others => '0');  -- TDATA for channel DOUT
+
+  -----------------------------------------------------------------------
+  -- Aliases for AXI channel TDATA fields
+  -- These are a convenience for viewing data in a simulator waveform viewer.
+  -- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
+  -- to prevent the simulator optimizing away these signals.
+  -----------------------------------------------------------------------
+  signal s_axis_a_tdata_real     : std_logic_vector(11 downto 0) := (others => '0');
+  signal s_axis_a_tdata_imag     : std_logic_vector(11 downto 0) := (others => '0');
+  signal s_axis_b_tdata_real     : std_logic_vector(11 downto 0) := (others => '0');
+  signal s_axis_b_tdata_imag     : std_logic_vector(11 downto 0) := (others => '0');
+  signal m_axis_dout_tdata_real  : std_logic_vector(24 downto 0) := (others => '0');
+  signal m_axis_dout_tdata_imag  : std_logic_vector(24 downto 0) := (others => '0');
+
+  -----------------------------------------------------------------------
+  -- Testbench signals
+  -----------------------------------------------------------------------
+
+  signal cycles       : integer   := 0;    -- Clock cycle counter
+
+  -----------------------------------------------------------------------
+  -- Constants, types and functions to create input data
+  -- Treat the complex multiplier as a mixer that is combining two
+  -- sinusoids exp(+/-jwt) of different frequencies and amplitudes:
+  --   channel A: exp(+jwt), frequency = clock / 30, amplitude = fullscale >> 3
+  --   channel B: exp(-jwt), frequency = clock / 32, amplitude = fullscale
+  -- The output of the complex multiplier is a sinusoid with a frequency
+  -- equal to the difference between the input frequencies.
+  -----------------------------------------------------------------------
+
+  constant IP_A_DEPTH : integer := 30;
+  constant IP_A_WIDTH : integer := 12;
+  constant IP_A_SHIFT : integer := 3;  -- bit shift for amplitude
+  constant IP_B_DEPTH : integer := 32;
+  constant IP_B_WIDTH : integer := 12;
+  constant IP_B_SHIFT : integer := 0;  -- no bit shift, max amplitude
+  type T_IP_INT_ENTRY is record
+    re : integer;
+    im : integer;
+  end record;
+  type T_IP_A_ENTRY is record
+    re : std_logic_vector(IP_A_WIDTH-1 downto 0);
+    im : std_logic_vector(IP_A_WIDTH-1 downto 0);
+  end record;
+  type T_IP_B_ENTRY is record
+    re : std_logic_vector(IP_B_WIDTH-1 downto 0);
+    im : std_logic_vector(IP_B_WIDTH-1 downto 0);
+  end record;
+  type T_IP_A_TABLE is array (0 to IP_A_DEPTH-1) of T_IP_A_ENTRY;
+  type T_IP_B_TABLE is array (0 to IP_B_DEPTH-1) of T_IP_B_ENTRY;
+
+  -- Common function to calculate sine and cosine values
+  function create_ip_entry(index, depth, width : integer) return T_IP_INT_ENTRY is
+    variable result : T_IP_INT_ENTRY;
+    variable theta : real;
+    variable limited_width : integer := width - 2;
+  begin
+    if limited_width > 30 then
+      limited_width := 30;
+    end if;
+    theta := real(index) / real(depth) * 2.0 * MATH_PI;
+    result.re := integer(round(cos(theta) * real(2**limited_width-1)));
+    result.im := integer(round(sin(theta) * real(2**limited_width-1)));
+    return result;
+  end function create_ip_entry;
+
+  -- Use separate functions to calculate channel A and B sinusoids as they return different types
+  function create_ip_a_table return T_IP_A_TABLE is
+    variable result : T_IP_A_TABLE;
+    variable entry_int : T_IP_INT_ENTRY;
+  begin
+    for i in 0 to IP_A_DEPTH-1 loop
+      entry_int := create_ip_entry(i, IP_A_DEPTH, IP_A_WIDTH - IP_A_SHIFT);
+      result(i).re := std_logic_vector(to_signed(entry_int.re, IP_A_WIDTH));
+      result(i).im := std_logic_vector(to_signed(entry_int.im, IP_A_WIDTH));
+    end loop;
+    return result;
+  end function create_ip_a_table;
+
+  function create_ip_b_table return T_IP_B_TABLE is
+    variable result : T_IP_B_TABLE;
+    variable entry_int : T_IP_INT_ENTRY;
+  begin
+    for i in 0 to IP_B_DEPTH-1 loop
+      entry_int := create_ip_entry(IP_B_DEPTH-1-i, IP_B_DEPTH, IP_B_WIDTH - IP_B_SHIFT);  -- note rotation direction
+      result(i).re := std_logic_vector(to_signed(entry_int.re, IP_B_WIDTH));
+      result(i).im := std_logic_vector(to_signed(entry_int.im, IP_B_WIDTH));
+    end loop;
+    return result;
+  end function create_ip_b_table;
+
+  -- Call the functions to create the data
+  constant IP_A_DATA : T_IP_A_TABLE := create_ip_a_table;
+  constant IP_B_DATA : T_IP_B_TABLE := create_ip_b_table;
+
+
+begin
+
+  -----------------------------------------------------------------------
+  -- Instantiate the DUT
+  -----------------------------------------------------------------------
+
+  dut : entity work.cmpy_12_12
+    port map (
+      aclk                => aclk,
+      s_axis_a_tvalid     => s_axis_a_tvalid,
+      s_axis_a_tdata      => s_axis_a_tdata,
+      s_axis_b_tvalid     => s_axis_b_tvalid,
+      s_axis_b_tdata      => s_axis_b_tdata,
+      m_axis_dout_tvalid  => m_axis_dout_tvalid,
+      m_axis_dout_tdata   => m_axis_dout_tdata
+      );
+
+  -----------------------------------------------------------------------
+  -- Generate clock
+  -----------------------------------------------------------------------
+
+  clock_gen : process
+  begin
+    aclk <= '0';
+    wait for CLOCK_PERIOD;
+    loop
+      cycles <= cycles + 1;
+      aclk <= '0';
+      wait for CLOCK_PERIOD/2;
+      aclk <= '1';
+      wait for CLOCK_PERIOD/2;
+      if cycles >= TEST_CYCLES then
+        report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;
+        wait;
+      end if;
+    end loop;
+  end process clock_gen;
+
+  -----------------------------------------------------------------------
+  -- Generate inputs
+  -----------------------------------------------------------------------
+
+  stimuli : process
+    variable ip_a_index       : integer   := 0;
+    variable ip_b_index       : integer   := 0;
+    variable a_tvalid_nxt     : std_logic := '0';
+    variable b_tvalid_nxt     : std_logic := '0';
+    variable phase2_cycles : integer := 1;
+    variable phase2_count  : integer := 0;
+    constant PHASE2_LIMIT  : integer := 30;
+  begin
+
+    -- Test is stopped in clock_gen process, use endless loop here
+    loop
+
+      -- Drive inputs T_HOLD time after rising edge of clock
+      wait until rising_edge(aclk);
+      wait for T_HOLD;
+
+      -- Drive AXI TVALID signals to demonstrate different types of operation
+      case cycles is  -- do different types of operation at different phases of the test
+        when 0 to PHASE_CYCLES * 1 - 1 =>
+          -- Phase 1: inputs always valid, no missing input data
+          a_tvalid_nxt    := '1';
+          b_tvalid_nxt    := '1';
+        when PHASE_CYCLES * 1 to PHASE_CYCLES * 2 - 1 =>
+          -- Phase 2: deprive channel A of valid transactions at an increasing rate
+          b_tvalid_nxt    := '1';
+          if phase2_count < phase2_cycles then
+            a_tvalid_nxt := '0';
+          else
+            a_tvalid_nxt := '1';
+          end if;
+          phase2_count := phase2_count + 1;
+          if phase2_count >= PHASE2_LIMIT then
+            phase2_count  := 0;
+            phase2_cycles := phase2_cycles + 1;
+          end if;
+        when PHASE_CYCLES * 2 to PHASE_CYCLES * 3 - 1 =>
+          -- Phase 3: deprive channel A of 1 out of 2 transactions, and channel B of 1 out of 3 transactions
+          if cycles mod 2 = 0 then
+            a_tvalid_nxt := '0';
+          else
+            a_tvalid_nxt := '1';
+          end if;
+          if cycles mod 3 = 0 then
+            b_tvalid_nxt := '0';
+          else
+            b_tvalid_nxt := '1';
+          end if;
+        when others =>
+          -- Test will stop imminently - do nothing
+          null;
+      end case;
+
+      -- Drive handshake signals with local variable values
+      s_axis_a_tvalid <= a_tvalid_nxt;
+      s_axis_b_tvalid <= b_tvalid_nxt;
+
+      -- Drive AXI slave channel A payload
+      -- Drive '0's on payload signals when not valid
+      if a_tvalid_nxt /= '1' then
+        s_axis_a_tdata <= (others => '0');
+      else
+        -- TDATA: Real and imaginary components are each 12 bits wide and byte-aligned at their LSBs
+        s_axis_a_tdata(11 downto 0) <= IP_A_DATA(ip_a_index).re;
+        s_axis_a_tdata(15 downto 12) <= (others => IP_A_DATA(ip_a_index).re(11));  -- sign-extend;
+        s_axis_a_tdata(27 downto 16) <= IP_A_DATA(ip_a_index).im;
+        s_axis_a_tdata(31 downto 28) <= (others => IP_A_DATA(ip_a_index).im(11));  -- sign-extend;
+      end if;
+
+      -- Drive AXI slave channel B payload
+      -- Drive '0's on payload signals when not valid
+      if b_tvalid_nxt /= '1' then
+        s_axis_b_tdata <= (others => '0');
+      else
+        -- TDATA: Real and imaginary components are each 12 bits wide and byte-aligned at their LSBs
+        s_axis_b_tdata(11 downto 0) <= IP_B_DATA(ip_b_index).re;
+        s_axis_b_tdata(15 downto 12) <= (others => IP_B_DATA(ip_b_index).re(11));  -- sign-extend
+        s_axis_b_tdata(27 downto 16) <= IP_B_DATA(ip_b_index).im;
+        s_axis_b_tdata(31 downto 28) <= (others => IP_B_DATA(ip_b_index).im(11));  -- sign-extend
+      end if;
+
+      -- Increment input data indices
+      if a_tvalid_nxt = '1' then
+        ip_a_index := ip_a_index + 1;
+        if ip_a_index = IP_A_DEPTH then
+          ip_a_index := 0;
+        end if;
+      end if;
+      if b_tvalid_nxt = '1' then
+        ip_b_index := ip_b_index + 1;
+        if ip_b_index = IP_B_DEPTH then
+          ip_b_index := 0;
+        end if;
+      end if;
+
+    end loop;
+
+  end process stimuli;
+
+  -----------------------------------------------------------------------
+  -- Check outputs
+  -----------------------------------------------------------------------
+
+  check_outputs : process
+    variable check_ok : boolean := true;
+  begin
+
+    -- Check outputs T_STROBE time after rising edge of clock
+    wait until rising_edge(aclk);
+    wait for T_STROBE;
+
+    -- Do not check the output payload values, as this requires the behavioral model
+    -- which would make this demonstration testbench unwieldy.
+    -- Instead, check the protocol of the DOUT channel:
+    -- check that the payload is valid (not X) when TVALID is high
+
+    if m_axis_dout_tvalid = '1' then
+      if is_x(m_axis_dout_tdata) then
+        report "ERROR: m_axis_dout_tdata is invalid when m_axis_dout_tvalid is high" severity error;
+        check_ok := false;
+      end if;
+
+    end if;
+
+    assert check_ok
+      report "ERROR: terminating test with failures." severity failure;
+
+  end process check_outputs;
+
+  -----------------------------------------------------------------------
+  -- Assign TDATA fields to aliases, for easy simulator waveform viewing
+  -----------------------------------------------------------------------
+
+  s_axis_a_tdata_real     <= s_axis_a_tdata(11 downto 0);
+  s_axis_a_tdata_imag     <= s_axis_a_tdata(27 downto 16);
+  s_axis_b_tdata_real     <= s_axis_b_tdata(11 downto 0);
+  s_axis_b_tdata_imag     <= s_axis_b_tdata(27 downto 16);
+  m_axis_dout_tdata_real  <= m_axis_dout_tdata(24 downto 0);
+  m_axis_dout_tdata_imag  <= m_axis_dout_tdata(56 downto 32);
+
+end tb;
+
@@ -0,0 +1,202 @@
+-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:cmpy:6.0
+-- IP Revision: 17
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY cmpy_v6_0_17;
+USE cmpy_v6_0_17.cmpy_v6_0_17;
+
+ENTITY cmpy_12_12 IS
+  PORT (
+    aclk : IN STD_LOGIC;
+    s_axis_a_tvalid : IN STD_LOGIC;
+    s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    s_axis_b_tvalid : IN STD_LOGIC;
+    s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    m_axis_dout_tvalid : OUT STD_LOGIC;
+    m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
+  );
+END cmpy_12_12;
+
+ARCHITECTURE cmpy_12_12_arch OF cmpy_12_12 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF cmpy_12_12_arch: ARCHITECTURE IS "yes";
+  COMPONENT cmpy_v6_0_17 IS
+    GENERIC (
+      C_VERBOSITY : INTEGER;
+      C_XDEVICEFAMILY : STRING;
+      C_XDEVICE : STRING;
+      C_A_WIDTH : INTEGER;
+      C_B_WIDTH : INTEGER;
+      C_OUT_WIDTH : INTEGER;
+      C_LATENCY : INTEGER;
+      C_MULT_TYPE : INTEGER;
+      C_OPTIMIZE_GOAL : INTEGER;
+      HAS_NEGATE : INTEGER;
+      SINGLE_OUTPUT : INTEGER;
+      ROUND : INTEGER;
+      USE_DSP_CASCADES : INTEGER;
+      C_THROTTLE_SCHEME : INTEGER;
+      C_HAS_ACLKEN : INTEGER;
+      C_HAS_ARESETN : INTEGER;
+      C_HAS_S_AXIS_A_TUSER : INTEGER;
+      C_HAS_S_AXIS_A_TLAST : INTEGER;
+      C_HAS_S_AXIS_B_TUSER : INTEGER;
+      C_HAS_S_AXIS_B_TLAST : INTEGER;
+      C_HAS_S_AXIS_CTRL_TUSER : INTEGER;
+      C_HAS_S_AXIS_CTRL_TLAST : INTEGER;
+      C_TLAST_RESOLUTION : INTEGER;
+      C_S_AXIS_A_TDATA_WIDTH : INTEGER;
+      C_S_AXIS_A_TUSER_WIDTH : INTEGER;
+      C_S_AXIS_B_TDATA_WIDTH : INTEGER;
+      C_S_AXIS_B_TUSER_WIDTH : INTEGER;
+      C_S_AXIS_CTRL_TDATA_WIDTH : INTEGER;
+      C_S_AXIS_CTRL_TUSER_WIDTH : INTEGER;
+      C_M_AXIS_DOUT_TDATA_WIDTH : INTEGER;
+      C_M_AXIS_DOUT_TUSER_WIDTH : INTEGER
+    );
+    PORT (
+      aclk : IN STD_LOGIC;
+      aclken : IN STD_LOGIC;
+      aresetn : IN STD_LOGIC;
+      s_axis_a_tvalid : IN STD_LOGIC;
+      s_axis_a_tready : OUT STD_LOGIC;
+      s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      s_axis_a_tlast : IN STD_LOGIC;
+      s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axis_b_tvalid : IN STD_LOGIC;
+      s_axis_b_tready : OUT STD_LOGIC;
+      s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      s_axis_b_tlast : IN STD_LOGIC;
+      s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axis_ctrl_tvalid : IN STD_LOGIC;
+      s_axis_ctrl_tready : OUT STD_LOGIC;
+      s_axis_ctrl_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      s_axis_ctrl_tlast : IN STD_LOGIC;
+      s_axis_ctrl_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      m_axis_dout_tvalid : OUT STD_LOGIC;
+      m_axis_dout_tready : IN STD_LOGIC;
+      m_axis_dout_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      m_axis_dout_tlast : OUT STD_LOGIC;
+      m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
+    );
+  END COMPONENT cmpy_v6_0_17;
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TDATA";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_dout_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_DOUT, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_b_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_B, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_a_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_A, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_CTRL:S_AXIS_B:S_AXIS_A:M_AXIS_DOUT, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 10000000, PHASE 0.000, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
+BEGIN
+  U0 : cmpy_v6_0_17
+    GENERIC MAP (
+      C_VERBOSITY => 0,
+      C_XDEVICEFAMILY => "zynq",
+      C_XDEVICE => "xc7z100",
+      C_A_WIDTH => 12,
+      C_B_WIDTH => 12,
+      C_OUT_WIDTH => 25,
+      C_LATENCY => 6,
+      C_MULT_TYPE => 1,
+      C_OPTIMIZE_GOAL => 0,
+      HAS_NEGATE => 0,
+      SINGLE_OUTPUT => 0,
+      ROUND => 0,
+      USE_DSP_CASCADES => 1,
+      C_THROTTLE_SCHEME => 3,
+      C_HAS_ACLKEN => 0,
+      C_HAS_ARESETN => 0,
+      C_HAS_S_AXIS_A_TUSER => 0,
+      C_HAS_S_AXIS_A_TLAST => 0,
+      C_HAS_S_AXIS_B_TUSER => 0,
+      C_HAS_S_AXIS_B_TLAST => 0,
+      C_HAS_S_AXIS_CTRL_TUSER => 0,
+      C_HAS_S_AXIS_CTRL_TLAST => 0,
+      C_TLAST_RESOLUTION => 0,
+      C_S_AXIS_A_TDATA_WIDTH => 32,
+      C_S_AXIS_A_TUSER_WIDTH => 1,
+      C_S_AXIS_B_TDATA_WIDTH => 32,
+      C_S_AXIS_B_TUSER_WIDTH => 1,
+      C_S_AXIS_CTRL_TDATA_WIDTH => 8,
+      C_S_AXIS_CTRL_TUSER_WIDTH => 1,
+      C_M_AXIS_DOUT_TDATA_WIDTH => 64,
+      C_M_AXIS_DOUT_TUSER_WIDTH => 1
+    )
+    PORT MAP (
+      aclk => aclk,
+      aclken => '1',
+      aresetn => '1',
+      s_axis_a_tvalid => s_axis_a_tvalid,
+      s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      s_axis_a_tlast => '0',
+      s_axis_a_tdata => s_axis_a_tdata,
+      s_axis_b_tvalid => s_axis_b_tvalid,
+      s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      s_axis_b_tlast => '0',
+      s_axis_b_tdata => s_axis_b_tdata,
+      s_axis_ctrl_tvalid => '0',
+      s_axis_ctrl_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      s_axis_ctrl_tlast => '0',
+      s_axis_ctrl_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
+      m_axis_dout_tvalid => m_axis_dout_tvalid,
+      m_axis_dout_tready => '0',
+      m_axis_dout_tdata => m_axis_dout_tdata
+    );
+END cmpy_12_12_arch;
@@ -1,10 +1,10 @@
 // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 // --------------------------------------------------------------------------------
 // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
-// Date        : Mon May  8 19:43:16 2023
+// Date        : Mon May  8 19:43:15 2023
 // Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
-// Command     : write_verilog -force -mode synth_stub
-//               /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_stub.v
+// Command     : write_verilog -force -mode synth_stub -rename_top fir_prbs7_invert_rep2 -prefix
+//               fir_prbs7_invert_rep2_ fir_prbs7_invert_rep2_stub.v
 // Design      : fir_prbs7_invert_rep2
 // Purpose     : Stub declaration of top-level module interface
 // Device      : xc7z100ffg900-2
@@ -1,10 +1,10 @@
 -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 -- --------------------------------------------------------------------------------
 -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
-- Date        : Mon May  8 19:43:16 2023
+-- Date        : Mon May  8 19:43:15 2023
 -- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
-- Command     : write_vhdl -force -mode synth_stub
--               /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_stub.vhdl
+-- Command     : write_vhdl -force -mode synth_stub -rename_top fir_prbs7_invert_rep2 -prefix
+--               fir_prbs7_invert_rep2_ fir_prbs7_invert_rep2_stub.vhdl
 -- Design      : fir_prbs7_invert_rep2
 -- Purpose     : Stub declaration of top-level module interface
 -- Device      : xc7z100ffg900-2
@@ -66,7 +66,9 @@ ila_rx_data_cnt your_instance_name (
 	.probe6(probe6), // input wire [11:0]  probe6 
 	.probe7(probe7), // input wire [11:0]  probe7 
 	.probe8(probe8), // input wire [11:0]  probe8 
-	.probe9(probe9) // input wire [12:0]  probe9
+	.probe9(probe9), // input wire [12:0]  probe9 
+	.probe10(probe10), // input wire [15:0]  probe10 
+	.probe11(probe11) // input wire [15:0]  probe11
 );

 // INST_TAG_END ------ End INSTANTIATION Template ---------
@@ -1,7 +1,7 @@
 // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 // --------------------------------------------------------------------------------
 // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
-// Date        : Fri May 12 10:13:05 2023
+// Date        : Tue May 16 20:23:18 2023
 // Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
 // Command     : write_verilog -force -mode synth_stub
 //               /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.v
@@ -15,8 +15,8 @@
 // Please paste the declaration into a Verilog source file or add the file as an additional source.
 (* X_CORE_INFO = "ila,Vivado 2019.1.3" *)
 module ila_rx_data_cnt(clk, probe0, probe1, probe2, probe3, probe4, probe5, 
-  probe6, probe7, probe8, probe9)
-/* synthesis syn_black_box black_box_pad_pin="clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0],probe8[11:0],probe9[12:0]" */;
+  probe6, probe7, probe8, probe9, probe10, probe11)
+/* synthesis syn_black_box black_box_pad_pin="clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0],probe8[11:0],probe9[12:0],probe10[15:0],probe11[15:0]" */;
  input clk;
  input [11:0]probe0;
  input [11:0]probe1;
@@ -28,4 +28,6 @@ module ila_rx_data_cnt(clk, probe0, probe1, probe2, probe3, probe4, probe5,
  input [11:0]probe7;
  input [11:0]probe8;
  input [12:0]probe9;
+  input [15:0]probe10;
+  input [15:0]probe11;
 endmodule
@@ -1,7 +1,7 @@
 -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 -- --------------------------------------------------------------------------------
 -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
-- Date        : Fri May 12 10:13:05 2023
+-- Date        : Tue May 16 20:23:18 2023
 -- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
 -- Command     : write_vhdl -force -mode synth_stub
 --               /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.vhdl
@@ -24,7 +24,9 @@ entity ila_rx_data_cnt is
    probe6 : in STD_LOGIC_VECTOR ( 11 downto 0 );
    probe7 : in STD_LOGIC_VECTOR ( 11 downto 0 );
    probe8 : in STD_LOGIC_VECTOR ( 11 downto 0 );
-    probe9 : in STD_LOGIC_VECTOR ( 12 downto 0 )
+    probe9 : in STD_LOGIC_VECTOR ( 12 downto 0 );
+    probe10 : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    probe11 : in STD_LOGIC_VECTOR ( 15 downto 0 )
  );

 end ila_rx_data_cnt;
@@ -33,7 +35,7 @@ architecture stub of ila_rx_data_cnt is
 attribute syn_black_box : boolean;
 attribute black_box_pad_pin : string;
 attribute syn_black_box of stub : architecture is true;
-attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0],probe8[11:0],probe9[12:0]";
+attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0],probe8[11:0],probe9[12:0],probe10[15:0],probe11[15:0]";
 attribute X_CORE_INFO : string;
 attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3";
 begin
@@ -59,7 +59,9 @@ probe5,
 probe6,
 probe7,
 probe8,
-probe9
+probe9,
+probe10,
+probe11
 );

 input clk;
@@ -75,6 +77,8 @@ input [11 : 0] probe6;
 input [11 : 0] probe7;
 input [11 : 0] probe8;
 input [12 : 0] probe9;
+input [15 : 0] probe10;
+input [15 : 0] probe11;


 endmodule
@@ -0,0 +1,283 @@
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "XILINX"
+`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1"
+`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
+`pragma protect key_block
+GbQWy7xyRnDVKNEgu/syxcQSo3KIIWjSBPIwi/pSAYCe9sIQf1xA0ykhHf7s3r7GRWRS+sel+0Xx
+XWe4lBDDrw==
+
+`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
+`pragma protect key_block
+rLh670IEMVEjBamdsB+LhhoxrK6I5H9wfmPCOFqaLelJt08QWbH7WNvjIhNNz7hnkT7w+wDWT6AH
+9ZJgOGPSJmj9pWoXHAojkkRBTIXpFT11+IDyFQ4FgN2TPXWILoYGY+uZG1GlGN7dsEIm5HUCUy2c
+eVhT3XSIJDvufMyiJUc=
+
+`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
+KgKxjU+tI9TXRZLkaaosEf4JcTfzGtF82aOinFlVe78eUyHdMvwHHcKsxUKAjkhYW491bZ0jTKit
+pNc3Ov7QvW8kjTq3JHFuCf7SmCYRrmElQv0XobTk6mnMb4khaXw9wTP8YMS0XAqk3Bksal+aKfvX
+LL/afyM4UwBfiIb04ZgvhdOlp/dkCqWqZyDL2qVScyGrZcDCW3CCZTVQO29hqMLZP5S82keXpBv3
+5J7nHHbQ3n4dxsRykYtJtwg7JDyqGHiwhj1HDtjhG+LX9ry1wy5YgvxrzSfKoouAeHCKXcG7TY0a
+sz4nRUsC3Yg3/CybYyPjvVJDirIzWRzSD6l1DQ==
+
+`pragma protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
+ItrqCM44kZl0WwWeSAjetSYD0fPwYZdVjFp5cRl5XZyoYOMWKCVEXncinM06x/MDVlkYiXgz2Xqn
+6ui7jR7RwOKALvqoqdehIoXZUA/5yPMntFpxPcFIY1DonBI4CuMjhqCuB2RkxKNIco5Z7/QxCk49
+MCUlvIFRd2MXM+zvhCRdja7e9blnwJEUETukq+EKuAwuR3+VN3uzCXsNtgBqMZa2CyM6Z60fStuc
+v1eiDP/hxOimuSfsS7evakl5WMjgZuj4Jld1+y5hTOuPvw4+s3KIb2ejIH2r/I7ui7sWUZTah36a
+4QexKWP16Ghv319FCz4KExZ6lY+7HuoO55lf4A==
+
+`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
+FGUAaXx6dK7W5dgDUXY6j9xLpCHdbPvbaH+O+ozu9kcNjL5BJcGWnTdooAxaZdBsOZBvrVuXUU4v
+ev5owQI9+5/+8aoXfeX2zZHp++ESqotCFj5ykw8BPjwCOCZz+tiV1Q8ISqf/NCuDNU2KJyvQUsFX
+cOXAwCPvrI5SwQ04u9sVTaHwAuTuRw3j6nkt6BHWrjKpq9pUfNH4L04ag/tUGVpnlcSBGewN0ieC
+xkzVV1mPCyCu/thxu0k0yda5pS/u3MFeC1N8rTrSsLEZMUiPYg/BwwWGT7D/s9FCMbbM2kyoUXpa
+draqn+K8c06CQxLI+ieilCd38M25buwOc3ANjg==
+
+`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
+`pragma protect key_block
+ucIv1ZvudBg6K9ubpyCObknzSo2JKwxETiac5kbTyw0xwj34bo+xJ/DnUCoAdEVHZcAwDc9Fhbhv
+j5a7MwnHY+TpzDjhwdN75A97jOZ4V65wcuFErbH19OSacDchGykcwXCiaA5haDJK2hF1qPxu7TtO
+R19uHYIhWP+7IpmjTiQ=
+
+`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
+AI09c0Va0j6swrG6tMKXPaWcjMpXDnvuIze3bAe9Cj0tCXFumugM/pZL81X53kMwmKPvRCpTi8DM
+kLLATubglrp6DudyaIY943skTmlH+as6fKaHODrTcy4CDIP4kKrok/7y1rBI6+YAfN3ZIW+45MiV
+cHuhXHXxxXblzCT6obAZK5QUCP2qZKgO0jjI1RD7ZEJuS/mX5wkIAvOe8L1HBkyUsRq6Cu30W6u9
+7VI3LOy7TZqb6Nix6Ok85ylO82KP12tdXY2IRivakKu4fdWQ6vc3ARiefSR0+RDmE/eZzhzQbt26
+mf7t4ZoEITJYnmd5zcenAnw+6AO3fUwtTLT81Q==
+
+`pragma protect data_method = "AES128-CBC"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12464)
+`pragma protect data_block
+vLDJJUgjrlRfGtI6e1+Byt5lDBB9Oezy8FH9Uy/Lem9icZpnVjts8rEqPHcw31BJ5u3y4ePWkCUm
+QQfQ8vh3WaO2dCX+QhbDMTmPaIe/t8nHJKefrbW5OY3eRKkptlVSIFCFITpJlzyfpSe0CsF+dWLc
+F4J0aJzlQEKkTcCFk2ey1erWcvHgIf6eCwkGouO/COjRPomcaMzJt3ty3PwhKodmumGUICNXKjG/
+lH5VI4pSkr0hpeNp/WZhHstrrYJB7GSwMCqfL0IH36wCF3R29Yjp7ouoogJ4+imS5vnMJpU2Czmi
+PFyY3LiBeZ4VP5b8Iv0AK4XoJtM3XG9iTBAC/oslCJUtBhINFPia8EueAVn178qtq+htmZXlEAbM
+O43w6xZ55fggub8NiHe8M4qAhDC0nwv3LBVndn8xEKF+13iwSiqhLjU1Cya8z+0j0TUExIeVQyri
+OXh0d9oxCJ2lfPtNjHZ3LkjbMLvzdJG8pBuDtx5952IJrwkJIaT76aOEs7XK8O+cfrtfhh1fPpY1
+XTzoMx95+Qp7Ay2J8NObIZHBuUKX2ORE3b7zSBW5FPRjaxTibHQ2blQzoAbo5y5f30hxOHsi0+Xe
+D4bwHKzoBpsdKAyvlKom17BBx5Q5KccIElz3z9ulgthM6zwAWmMVPzQnJAhmz3Hl3t0m7+YNA4Ia
+cg/H8tiXcV6CEnRuaFRr8dvkZAlT16o4u+tEwi85XgpkoApFQ7EytG673+LigwZbb2C7khwEoIiw
+1LN4Eh9i2WsLPaEipn3q58x1rH4/MEzwsGw7loWE4BkCf+n5QAWYc/nk4xfSwFTBvxs6sPejsrRX
+qbtO8ZOnKuVTT2ZLwEtvGrf+Ii1Xymt1JsQt7Z0QBWTykLt0ZhWTrPnMg/zcRxyRCDNYWVJx8JKC
+Fjg1XzSDYIYff4HaLPjmiu5sPEXaKTQJvaZa52Dq87oKwWI0A3g0ymKK7UVXrmX/odtLOlHIxuhy
+JnruUntWueD34KJMT2lBO7AP0g/OmHDI6v72Q/2Tk66QaWfnnDJl6qRN2WDuGyNuwSflbEGQiK02
+vyM4a6K9KN70ev9aLX4d2m7Uo9n4GFbdvjakrlHDS/K+TRs6XmOa+y8ErWxn9Pfy9UyRrFg1TdQb
+Zk69XUdoQZ6CNWoKazZHaJ5p5+6nk/G0nm8LR039U2sqH+B1hJMuvFvsx4NzEoYpE1jNsiy4B9Ta
+ArVNSpGuZCA4Juifia1UC8m+mMYsLBACf9YX/Uua3EeOfU2CEi5koPuBzR/QKb/1oRa3x2oux2Cf
+p+HcJdQfSOpF6AkpWZLChsoTMd2F24Ztmjz3/vNIapPf4rcObfDEJwayu7hSrsslcCIcoXdojo4
+VXLn2QFVUYMgSq3pYGFywvmQTA5x/JAfOcWO8IBKdixvS3F6xSTwH8JaKocC0735inh65PwNjS9F
+2KIwvgHQvLpCxNny+0NvSQ7ETTouC6xXj+EUv4bGpml7J3HNjixHtTPfYXf7cl0mqQmUDJu0wLkp
+WuvXFDvCxpwSZ5qw+1H5MPeue3MeB1Z6Ibu51Fs1EwnAe/g9C0Mo1XDCD6LfVjvpZYE62HzlzF/K
+IJoLfeJT0O0VhjqhC3+M3TGXHNYm6chuUtfNR31cC7WgG/QiHYOVySvp3zljDZWrxsgHO+JwhbQC
+n8ALL+g50X6+uS5w/HkFBsxwCIocmViJb0ojg1j2ncsUjwwEqkDBprVPYFh6Zimk5SJ9f3RO6pQj
+saDd3hitIgpMf1ha8rpCYBkwqBTogxXfwijLMplBdGWVGSSSnnp6jTnWb0sV2VPA1l2X6Iq+pomM
+jilYYfQ2dBuXFEMpQpwDC3/8N4YxpDZWX3gtyK2XV+2BcRONvrl/naflTsXxuXAhSxOBqggJw7pL
+HvsOGKk0ng6uKC5yQPc6Q0SbWwwT54D9vLM4U1OiRKPpL9S1YXak+W8ZCXqdHkQNlUlm21ssL4dl
+Et7q9IF5Vil/wnUjm0nJxVZ4QJU/uN7icrtnrvAf1gVLwK3fpC0ed6ku9s7Lq1KvNb7NEPDrOu3Q
+hg+xhyl9MJTquidnbUsYlHdTvVzxIkI4q/1kx5mkbEjiIWG0R+haIwSqhTCdxpxxTgm+LGAtWJ4W
+lEuCQ2VEu3cyamx3PWNKPt+CE1VayIkgGqEBXIaGpwkymL0y6hkgrA+q+2msQq245iR7XC83U26E
+yb3da4UnYxL7g5WjJCSfCdNVOkKS1Yl9VZ6XSW5RFwWIdURQyewZxfPKaJWsDAGfpRftpZ2mOfIl
+DP1TwLOJrgsh3QI82hOYlUbHmcPIFMH3Pqp4OpbOBRcPcZhabwMA3pidOtbloqo5pRGblsO79JSJ
+OdbTH0XVln2LAlQ0bOmaMt9/rOwfexnMgActW5gvaaxAXuYDKRM1UMECbAxeXCwqzS0dc0V8ypcG
+fteDGHXMo0F/XAmGvVeyXJ9wCk8OaNq3QfJv7J98GeFlsisK3g+DzyHnma8+DPiQz5fXZYlWQATB
+TYmRqvJl1KzKtTAluhm7MMLb3F8xL2NDeGuxLbfrf6E9zY45m5mPjZ9RgD7Lp/aRq3yRGIHZT/Hj
+UOW9tPIFXsnd71c0SWPBukdkw6Iu4mmRap139EPPn1NbxII0Kx4bXAFSaRSVv/XzPy5uqO62NQBW
+NGvw4f1JGumSY/O23vkXjZaGvN+S0bz8EKrqST2JR7xwKXiyc1EiBTO4wNbd6azULsK4LQc7wEe9
+fLtkLqeh1/tDw12z4e/cGuujh09rf8Olns7hcq6KvzDyM4MT1hSizKeViDqgTaWsim2icOPXIWGf
+sFNi0Bc38qKoDMEnsp36riwZe+y4DdFzqzq0Yrr9+0B5ByNMyLSvi4M65KZswrHoq1MwgubuGmRu
+bnAcGsxnoNMIlXHHBxS1+kIY2Dh9+Op3PVTHiBM/kexi6XMyY9pwe8I7Fd+L4PTexmvNKi2x2UOL
+UB7l3OgfCdwQ1+9QgliX4xN46NNnISm8EFE0zpn4SAV7B38UDLL5XBcO4aOW2/+q4crLHtw/9GsO
+Y/Cx5SaOa3cx/2UTFnVpxTvDICQyosM7R93SgxQmmXswXIdh8L2v/X/bojwYGYza/K+ZJ0+GVEmn
+nCagAUyAPO9aMwlnCcidIDOIx639+B7IWa8jTYsObePK4Ghp0//E3pFZ5vIkTWsQXfAYwjvWp2BP
+uzZRqK+C5GbLkw7SZrUlFK5w4BI7ABx4bYqP78Tc95Ps8aGL0SCwiBy9wMXqlvcjOpsy2CWJcBBL
+No8TvQKlYRdWealaPFJO9gB0RF3LDIjFwXgnEoKX0BxHOftGEX13le2Gj+dqsFGgktTXoPqVXMnL
+PadND3iSF8Mff8/7uoQGaAyV9g5DOJqmQLnj0eF2QyoBvRGXBL/bKGoIll//kBqaNk12RuOHWHbT
+U3iLXaTrhf6yOmDHZS38ocYG3lcoaDi9EBU0SpzR2m/JSjAWViDRbV14QeUf5lflN3TECF/z/MKo
+gEjxx6dUwsjIVt7BIZZgOL80YeU3xkS37nzrv3xyl2G0JIC9mpKwrIQHkyP7JC87DWrMHJOYHtjt
+PEi+zZL25OwIqRTZP4gg6kmeS8iRsBEL+Wk7s2gqpe8V4NTQSt2HTXZp5AmCgTmS8a0DR/A75FTA
+oqGCUEQmrmej2XJT/KbkzAsUiZnJmY1k7SGAZTnNXaPuj9i/AAUayAg/URaLLS0rwvoFuiQ+er1J
+ybk7ldZcUYpebiVjfe0oBAa2KcW2qf5kI099lfylsrU1uO6XEmh1+VbtTRbuUrmEwJVG4p9UoubF
+AJ5DHGvb54gwpkLa3TRT+DjjpI8s0l7qUFB7R0tizSDuDX64GDdpM1pVSkFBUHll+6mks5or2/VB
+Hln3g/I8AdHS0Ee5lAgRL5Vgy+KWSBTLnjmXLh2PLn57BNiULh7VPy829wKrZJzgBOYcGlMu5kVN
+i+q/xu2QYwfcgRXDwljWcFOQvoqkcg/ohyPA25kU5XTO426LkqCkp2B0LjwS6Ru0LFCAT9VD7Xfs
+gC577whnyCFKF02by8lumThgKPi3e+MFtFtUUP4NqrLVuoSbDZsRwrNLyTJF5CT1Wl+aOJGzBGLb
+aL2kFLF94YfyykQ0o02bH63Eq/QsrvKdm76fU02BuG8sPH+GK1L5aPAurh/ab5w1JeJBFY5pOKJT
+4fTwDyIeEAJz40vvDBQETJqKAhx9slR77zV2TVAcxQmhXXAIqZXXBO4UNgOILVyLPm8NKFZWdS12
+5rxQdEE0s8y1Rlg7X+kk8gHu6a/p0FivgMMDJuguKcf9ny0SGFHsgKO10TL3rr9swBrfjeJFqAHl
+8W0pH40VE7s+aSVwYDpLrNXaIj1huF7Nq8R6N7mAzihrKyJtqe2DPGthc3b84plrtQYyABnDsPcV
+XbMi+Hx7t/RKzR8L4kpXW5iFnOd7LF1uNCDdhIKWpoUxHnK6vKemXGK9h0pRsFZVohQ5sopKQOyf
+tJ1isqkEpBP6oxCvnVnRbFV98aHA/yOywevf5nDEJAphXQxOPUg1wSrYQYyqMfwqvWNmTDuqN1go
+rW1nqIaOkZREKe0NScx7qC3I+8/ez+12dTJjqyv77G91cucF7CB+uApoocTDq4tPa8LQlR3qLjzq
+AxZ8CVJ3uVUgYv9lp/EI5Gb0GrZC3APt8tbR5WZC1E54EoOkj5prTRaon3PVL45oSNcPWZAcx/Gh
+sXORdqYB6CW8+sC1kSQfKQJifA+ZAyRCvvQihld8XSpwx1zUa+LM6lPLA7wlphZ49dGLYr2CkQY2
+tXqToNQ3zSltn097FYtScosgXjCeZGa/4TktbJTpJgvxNpDtJqmRtfQE1ADqwSLMbBavYK7FGTw8
+XgWElR1F/Qub/wupGjRfM9hciZyVh2psk5atHuL8/U/OeXSZaiirana5yKNG9ML4neG+c3Ffrvrw
+dgdUbozDo1QV/0Cg87j8rLVdFRgM4BRWPCmhg1tVdr8IMCd/UzggMBXmb7mbXAYbnVAu1Vqxb8/i
+EbdzYB08pVdUn7jlTr6MeLNinFYRTq0d2j8xKP0hCTHVXHNbqU39kREEe68c6FOF3SiJXOX8qtnL
+D8YZlKOOiqCzd43er0Ysy61SsfAstKPe+dg9vZmsoE8/xcD/3/4sALY7BlWJz68btYgaBASDCU//
+6gqk28sSeHQARhFY18vCNuLAf+dRD7Zze1Ya6kt22/nstLou1lRgGmDjNm2O3iXExXIPG/C6YYIm
+ZMypy+ZdUCkzpEzpaGk/3BrdaFKH2s1N5sE3fWaA/BIIFxLNPVf897o7Ij03t+Bf71s+JBR3BUV
+9y7JJhslPI2/daCPSJ3oktvJIGYwLLp3qfznlcZuqdPdzlhN1T5TWVZZbXFFaL9FGo+rPo0dKrbM
+Wo6hmW310X/qVlc3ctYz0lvVkYns67UDHVrVP/SBQPIYETmt2hsWlzJU1CRCby4uBBsIZXwe+j2b
+9PW9ETn2gyplsyBWewR0f5/xsB1q6Qn9zG0usHhxK9SGLeohwJlDS5YOLB3+gn57VvtBcOCMY8Rr
+UEG+pgmDhvBxacswIQ8EI05LKINgsIRhfgBpZW0mz5m2q8kIOz2BAJCvpJgP0FPevu5Aqp8mIQPP
+XbnfppOC204x9UzilksaVjLDZ//txnmXZ8uhv62NP6MTQLNvbL15Pu8l31x1sbOV1qYZx3PAsTXJ
+vllgzGP9ABfPyx7JUpV2evLblwFrNERmZ2+zXXJpqrC1Y+Ov+y8h2uwKsK4lKHdlBbHwThPq2cTq
+KTkMYt6RebsvxZFGgJ6yCPdBhTx2ChLIQcmCPTj/Cm7ObdneYwd95jdv9iHg/d9pfG86QOUU2C5G
+xLGBVWEFe99YFTQQ6P56UzhgKPwJw+xgM/aTnoym0USW+WRbpF8pO5vXSa0UfxGAGTv9q7JqkHKr
+4iTBPPXJtWBhNl5rzUh8OJSTjMKQTLIv+btrrmsLhWk8Nfwa1GcpBoLBrZOxrwP2f7flQSnVnpz+
+4xasi+5di7/V6xOZemXcfgKGWI4wjehafy0oCnRFIPOfEiWVQid2K5nodgxJK4q89nYXd9OoqRTD
+AdyqlFa/Jluk0IikDwurqAU+Xup9pJI3C67dOMX7naeOYGZujxknSJUCO7Kua3mygTXk3bUyk40U
+doNI6/wljhhP3iWlzB+n/kaUg4HNcwZmZ74uX9jpIunTr5tASrGmrQO/VC9CHD6+Em9UYj8cNhKF
+7CqnnxKng0r5zt4/aG9G/y722aeAk16U+4hze9jyqG2axwKnNxd/UVmw+GbZLsCDlXr7zSZoxW4x
+sM64LaY1oGJobMVrrqdby+Y5r+5hKeMT/44jo/aNf+6eMxDYoYTH3epAwlH7bOCmeamTo1huxBZT
+XThu+Q07lQaDFZqLTAblck8J0qkr2HpxzQgqYJrlacxkUALRTyrw+jH+IZA8N/FT6RuQf0+PbN78
+VIRBJSqCQl02jGtP5rsSn/HycL5Ox04HkdfIH8QYThUzR5+udvtklkxOZtOHBUdzBW8Opljffh/5
+k3+es50uiyKTgL5O+iYOSDkjVhojw4mQAEH/PJAlPXfy8VPE8QqCTWW7Ed2huLNU2naH5iS1T/Le
+ShJB+/lO4hv7daACsQUBy3CvVJ2+ruK9QJnWshHcq/0FuZ1LJF76ux4HdJ9RoVyOwBD6tIUP+XZK
+cr2VOw4e5FYEpZpZjXVEx1/ENgiBeGAcr/UKTpt4voXTk6ea5eBtmIgEcPeWZU2cKBgG/QaO1SXa
+xSWK6eU+7InXUItxijDl/lnWPx9CVPV1BCfUOkcz3EQ/HL0UeaAXmhzyJvka0zEnjPrrQkztRCge
+t4yP57MciI/K3OUQ45ZORC+vL/6bD9juHR12kKn93LtWileJJ15bGSrOtGJIoaTR7F29WCDSEB5z
+yjzl5n/WSWcSDiqAR+S/ZC9uWpkQXhSD1oPCwsQSU9eEce9nvDm2E+f4apRAzWlwpci6r6gdbGTL
+h4dTrEIgEqJVmEP9Svu+2xHIVYTcbd8Abkz8JYgHyGH5tifzu6UWSu2G9pIY0r8dBelnxZdNheLp
+iiyUBgnPMv2M7VCFZLpbbJzBF1MFN/7jEPHiW5dA/nwvL5v46yg/fYSA9zV8Tz+aYVAMxd55bFTz
+Ws/PjjIQrtifnNGtyR63clFuegIt+ftcNC34dPtQqTqgoXwcXUG29idHgfvU76Fhm87ldyWopnsk
+aFdduRQA3+ZPnXMIEmNvEf3iiW3DWFaUbP1d8kCgrwRBfE8+v7HHMI1QJP8mTgPv4Iy7l1elI0y/
+Ax6MbQaR7bAvQlBb2iu/LJF++LJQsWnfHNyTBe9h85NaH6zRuZjpc29RX9JjnCO4nBRYDSyuSDSe
+fsX4pIWp7xhlkhE8Vq6kJQPd+LoekUz7mOchfv4TirPuh3HquJBF8XAGmgdE9tDWE3CiXJIgkQVp
+dbrFhqkwem4OlipJUY7yZKEzOmtHtwi8BeN3RaiOX+rUpuAa4knsAG0XF8OAGljke9T0nkX+bQ6Q
+kMLmcx1ZLotyx+dwituzYg3n3/2rLoNaDCrxdv7eGSiwEwAQaGTE91GfsK/bW3LilAlBF4slbiHO
+Gr5i3euR71fgubMoEbFNK/CTI56XnhBZKGNsezvyNZhTIctMPxggNQ/BgJe71lsPcLznK44PV4aj
+7Q4qiQ8dRtlJTgS3IAQvtTAqvLDcUSPnq7AWHavmljjJT5QX+rDJsNvJXfrcy4RGQudCauFNIxqe
+GWq40gIpsl5qdSLuOy9j1vP3uBz2ioorlCf0AE/TCs+XZBX0M4iQo97CSqrRVsVb/ycyRjzqFKDk
+ff9/m6kuAdIqU/8DWoq9bmb9RKRZqwG0jGteggwkv3Qu7OwYzYczHpW8QHqMxSg5VQuP2bRXb9J8
+WGm80TYiii+TWVBifZUrikX1sIO6gpBP2xRZDybWn67xaxQ4aUoMVR9F3tLo+pH3M06QuwRc8UVw
+NJnDRG3sgmR6i53cvdLTfYzi8WNesxlcL99IRwZ+8XrSPr8bDyibEJVtCkpNthFHvQ+BGtQlt7M1
+BWgz4VlLW5XG9g31idaWDyM1TJPGgZjePDguHn3s+cowoTgl8RjcwaO8fXqNIDNc7Nqw7DhCJXxf
+OOErW0Bj+5za1YjEQ+MHEgLWJm7vOeWxPzNwQFslWXWeypM02ONdpqRj20w95++SlZ2zKvh6dopw
+3uNDXuMirFALSIbwUDMYypbRHPbGhRoyUYQ1gyRo55xdGUgMTNmbWWDE6UMCp1mW80oGpR6OWmdO
+VwFKsuzeGs1ALnTweVm36FPemaFSzk3pc7rPiZmdhs1v7+dw9FYjBttfkwcf/Iy7nk0Ev8oSFRZ/
+ex1zi6BXYS3bILREFMpWuRTw7HtE6I3RpaA/k3OzHdMzZFml4Xkn7f2j7gkhPHzXToR52p6f/P2G
+oPD3blyogU6TUQ3LKFTqNiqQZenz1x3XdwqscEp/4i5w4fux9cjWwrVI1Dx6mPJ1tCNCi1kEIAZQ
+zOdUeZKKPJ+gu3/PfZBDdCZTZsGI2XIoYJ0Vk64K48gnuUCK08d1pNCABh8YBXF2zT5pPp9A99on
+j4mRR/u91Cel2mHReNJEynTJHMuZzf4BmXj76H/01YrVKaWyLJs5zSdAykxhA2h/LGnYEaiNBPWb
+39te0WIrUs+IG2dO91DB0USld72iU4jEwSVZzvyPNPL33uNtNSZYayM+g2cYg7U4bPcmdzW5YUJR
+alsYJPrDv+KlKSqyj3EulKAAql50npg0tCM85ZMPE/zz6d0uC4cGWi2AkUGX/9dSBE1/0xgfQveU
+0+OtofanGvTY66DLwOtQegffJlegmLvWyBa12w7NxGVhm8RfpdDvLyVdc4sBxzM6zKVpwcuSZy/k
+seYqXFSq6WE9rb/d4VC8Ta6QLg716zEh+OklBSyeF/tbD/neWeVcJkZMzQ6w1VjihYLGqOnDBNlD
+UB3KNJuEqvyyTK1zMVBmluGZhspXj1yq8ZV2xfkxiEMLL7NpdSSItMlZTamNo9nGYpLMFzxKMAxR
+teItxoLs9ZKVWd8fW/P1iTMKayoh+aTg2lxH0ZCcdyp2NOEjCmkTAAXr18ZRN+WOhhzMw3uqwzNd
+6HBsbnlER/M8VsNgP+VBgmuvRNBlUMuJT+usv/p4Q9Bh7yFI6XhArqBq1teX6H2scn8Tn2WNKBeb
+9u/30RygW02pSX1vxKKLkx+ytrAnPVpiMinMiRLu32R4tOaI5jj0l0kZabn2uIArfZv4P85wG5FT
+LK5kniV1MkMOL+x3zk2BUaDB14bStOfLzZSbrj4wKri0MFKlqzWzTUG83q18kJTF5Gtm2NuaZZ6U
+W2WilwcqBSs+I4Tg0npMEzVxjngyw8DHp+eYEmrELjH1sGAaF4zTqFcc0K3Sd090sJPnl8P/Zab4
+CILx8N+ma0flJZWl9A9ONOokCHPJopFlVzikH/EO+/v6KJN3fkOnxGOCqp0F/UjxA1dAU09O3saX
+DupicKgsOh56WdrVad7VIggWzKI+HlYW4BWhFFtoZQTMdGg5OHzYiaCi9Bui1Zsqp/wPy8T1KD0e
+jBQPyxGZ/sq+ul19GWt6clKGKbMWgewsWBqAR/jgfIAIMkTkvG0CCdUkVCYBqtC/7M8fPAihKZ9p
+Xpqo3FDK7g9NjRYqnH+db+SOrt8GTSZabN5cgWW+D/LOOOAEhDCNwyDKGJXLKLTyjTd0gwfXrcfQ
+PnW526o0e2U4sP2hYSNWZ9fIJMlSKDfn45b/LgMj+uLkcnSu07pbcJIC9tad9d9vd4JMVPZj7W4d
+xz4JQjCqZyZOrXaceYrYee5H/BbJSTiHq6/gr9tNJscIybuvKAHDTl2plPuESjfVlczmANiPcQEF
+Evn0dqw7zpblg3aExbLNpjLLX8IcEpjfXD/Qz/hfk/UPE41U6UviUwzkSHE0c9xHVqb7nHfSfo9S
+7pkoZKV6Cj6RmsmKPnjf7/WLgoDeGBEm4Mde9fhovbwmrlpI2QcYsuO0dg6vo2Q+DeC7SO9wzGOe
+TmmxM3WXjhDy2uiDyls8ZUwruC7Bh0T+zHljR47iWDw4A9RnLWU4GzBzuS2TR1LWbP0Khrz6DwFs
+nHD+b8yGBFdI8rUA9r+LJNBy46oo6pg4bwkhPrZGGvJdpZkXFQ9itfGlsN/TZ/Jo64v0Z5ocEEkN
+Of0nVQpDnBsPhDDgj96Tx+f8sX0au2/KIPzZzV1hivOmWnIqgl44ZWLxVoy0ns/w3kF5NoKo0LQU
+s14F/NE32TD/u23zSOJiDe1LnTKJgO/0T6ulhs1iw5upeq6rCMEEdFOIxQcLbCsY2A73mJRnPHmR
+lHN9yNCDpuhxCFiDeL5/Shm+lxStfHBLHmUb2f/jVXorCS5SQFFgpOGYef6qyQPSBNXciZf9Sbdr
+Qnu10CkltDgf/0saImmVuvpWrho3booiXFEVOSPDxOBZezF43Y+zyuFNrvkDoo0z0vAn7pRctJ+M
+en5InchEyM7kTpQo816yPYhq932YEWpT/BL/XthZxXuC6cRq3rxmyHES/t5XlqEKFyok9/OqyJns
+l0KYVQijY1toOhWysECQ//wIdzHJAKPd/LnAq1VQd7p73mbHc8zvFaG+hPNeG5PCmEv0NbxWIkSk
+EyHj2QblPQi+vdwOA8/lLZJTLn9k5HEB0LK2i1qn6SbzyamgTMgrK4+Yz0oLi8XRq5x0Ebx7e7Mg
+m4HXSRNragMZA12zvzHaepmX2YTHdmaLXmAq1lbh2wxbo/KXmFBLJ8E1RxubY6ZNznO/We3bqSE3
+xyaKhdt0VzCU6ZwJNsK0N5xOqFn43zajLltRs1zmPrZ+BGj3fBfNBtu2ZPJBkiraJG76VhuBa3HN
+AwljiAVWWeXuVTOQC+SoPDceebdL21D+TUSDg3hEAM0RjIyYv19Han2s7BbaaXpsrYqsLHv4+VbA
+qOwJVIli+TaoCNYkfLwTLQVuD1wv01kV4qq5wZrjOBv9eq5vywskXrvNi7vr4x21UjQqYTFmkEPs
+Sy9tiL0DgA3pRch8vk3D2xaf4Z9sK5zR8YqugMVsAQ8sTn6hN25znEucHWxIZA6OTbAqe3SjSEPo
+yscvFEtiZGMpSaO1BeWc70tM1JSv3Mq74tWLOjnUxdAMXr2eXwf83R8C+r/C2VHXpKZlbNuSptyQ
+r+TC6oJKmjBTiViyKAtMUkNX/puBz/fkHDAPPQe+eNb4MFxvkJvl1zb+Jyb57d8mCYyhz19+TZ0s
+EOB7MpKqqQjz/AlDHzIYSltJ8wnIVsd2Neqy8y6OOYoyYTN27vPyWk7G+h0Mgg4EtmAWY/h55Pyl
+5YlNP4Ll39xGxdlk1xq5Bt2kD4b4e3laUAvM1h2hoLD0ouVwkcmdPTAL1bcbfQlQ7F8QWd1WrDfw
+L3a1w1cqgUVYKSmnsg6NJ+oLOlJQGy8wY7yUvXmZfFDySiY+avUR/t2i4XWwX+lRh08bQ6ec/tt3
+SVbDklDfgVoRVmrbxv4sQad5EVH9Nn511AAa9lWrJLYdIRC0/LoNczEgM0uaMYb46hxrrwJ5fGef
+uolQ4Gs77vx9keudHpiqRJO62BdHgDCaYDUltxrknlVzb6j0VRqRd3YD8a/N8KX8njOn2UMU+tsz
+EfJoQeB/SamZ5cjNe3DOHG9fptHNhpH3AgupdeHZhOa6s3Qh+1QJsFn04Uy9otihMXyHUfD14HHn
+TTGHg6eEuDH9RjVLpJ9OMP0BhvkFRRVwT9blnY+V8/LU8a0guNCUwAfEKEQx99yUC2mWSa5/bJxy
+Z+Nfl3wmXF9gLlhmCEIlqHFCPTaL6g6tVjtT6KwqxKfFdeQ842GhWblC1+gT7NwiLjntx6UxXdHP
+jWyovNmstdoZGvlaiC0UPxdHXmC53mEE7xslGTy3x/GfvwD9Wdb0QyB0pn0wFU4dYg+HuuJ2tZk9
+e5N/9xEIk7/etVr6+gwmhLy6HVukFRqCEk8+2plhAjmVF94UUrLRm0eTWKmgu/mi8ertCPhxhmoX
+ByW+bhc+mQ1X0Q4zeO3YljMM51iXstIO/2gR0Re7khCmgQ5g9AdkHaPvBxRxZXaPoCw70Ir0PXLE
+dE7UDCznrXz/BitxSJgNJcmaJHoBVskzEOegQhAhAkyAV6SZ22S4AKMxb4Mb8BpkZkKNz4j3wDbl
+CRUy3zK6Tjc4Nqy8jfhYaRynMhBQvSCPclmmSen4vNnqXI6aQhYXR7Z2AgOP+Ap56ss4IbTy9KKi
+OPkun2RaUDAGa2Lwjc+PzMvdbSEnnlvTleo/uFqy09UJ5OyrjkIJNBxDxfHJ7IyNGdoaW3IefWAX
+rKaL7xvop3b5BPqWMvXXRSqysOzyGN/s0f8fiCrtHI6ym2xolwawx6zQZqKKv3Be+wKvTgRT2sh6
+xDJfQ3A00hem1RnQoVtPumBwow1QQbuVd8TNu7arV8oM5rKM6NMVecmND12ayeEVgKK0N/3IdsYO
+F4MLdAOd4MebirS+NMRdcxb2hdfFbA9dMw9Rce7q10x4IiVU3DT7Vo7IKHnwPOso4A2+hWaTt5Hs
+gNH6nqK1WaFHx8HIBktEg9tGl9ifBfYSuisgMUHs+1/e8ZwMmn78iBvMaUkXR/1m1SAK13gDrPOV
+2KRk1f8MuUONuZtRHbsSsoRzeEEj2MblEFIUkXKPGSnGtpyaIqcLKu7qSNqEWbd3Mi6iqZyAF9ur
+S6PrT631ucYj4KsgxamK3CkcPnro6JRXoW0bhfZ+FXdUMudyp9ciMAmR0Xm2CUwwoLb8BERVr9fi
+VraW1mYpdUtEgGUyYF8wK/m9DtCWErSUVF7KTwXcQ1v7cC9UYluD4y3/NQoOAkmLp3q4iMvI6Kr9
+wXPu3xTOgClz/Ske9d5zj9FHXX17ahUlM6L4CEP5hQa6NsPaBp1uykxeRkQ7/DTbuP2TeFNFCSNB
+c0MrXeXL8l3KuVjnQPG3zoxDIZcDyRavpLLamqDLergVscng6L68Yawbsp/7V39jWYmit6uTXmp2
+f2ncjHWTjL0XwQzypjcAELV1+oztimMwLbjSVD0phFRes9iBRK72DYxyumFEUz71wn48hrTVPyiv
+OwqNkS3IVQ89yHXEHjlbn5mG1QvvTrFhVsa8HMvSsvRw3YKji+5g6VSsKfWFwD9+L2uVb28OKpTJ
+cKL7M17lzF20jyOi3otlBI58p9xkdw3EStQRCVsBu0Ndv03deh078hmZ0HxBYx2WihCnp7pqf5ok
+H2b3GMbtmM8HuFKmstioDyd3wGfzUisb9394+do1aViRsEnfX1JytHtrbZHtBkDBMDeu1xemX4RH
+SdEqzvwXjLHrXR0y9WJvAzoedZz31pBbDzvZXkzRmKdAeszVYf0oVkXChUa0Iv/fPpw86N6/8+P2
+VPHGAVW7HHD5O5/fILc/OnzuPP7FNctlbjeoXoOpkoPgnSE25bSDEIpWkNwEdV/jnkHnsJYphp6k
+GbnBCj/5xIP7oYaDOoWLK+nDtwjEUMItMNNxVXBECuBo4DxxKp6DbWP3yF2tpzAg9w9j9AnlQB7J
+eNz3s1yPJ3QJSu0WFonPDcE9fepllJZXjtlCVe9M5BMOBowY+hjvgQhE7FNblFZvEithQ82dDAqa
+s/GpNPeczJVmzSB5su0G35o8nGfK4ZoWmOHqqsPhmE4r8lRR6fceHsT0/uNOI0wER6O7UFOOe33j
+VZkt3M8yIRuUIxBlBHOaSgluYveHryPMo6BXQKlRL9sauqc7TpLDMGby2i2Vs6oGBK846hXuVC7t
+V2dYDayv1u0Ge1HTHsN5qkXY+d5Om9Gbv+o1P4aeDW/Hq5FEGeM+M21cI5zWdkxenxRa83hUEj26
+v2Zlt80v4XT2YrJXwrSv9/s4r13D1nQxa+OLtCkswaew9xoNRGKjcvpq4UQCp6tbkxD0vb8CkoNM
+cdPJFZZywgON5pFzzafo6o6alG9UEROYK564Ukp+wv4Xt/7IQpzGf9dbB6yFYp2L1URdlebTvLx5
+hM1L2n1ND+QZU0JGytXefsrxRaxRx4C6HUnkYDc7xb6GgHZIMN1h5iClg9Cd3dAMkE9UAp3DM3/x
+ISJz9CaphM74pPa5dKbqvkS5pJO4kbGJkHEJVLr1l8GcOQyUxnghqEZ1zyCNaapf8lZxkfpfgq6x
+DGgZqwf5LUAsp48H/3MZd95X8QsJUy7DRXHRmkfxf+186QNCmLzbhEhQHSyA9c/odoKhHfbzDrzz
+/IkHBHBTn0eLBJLKJaa76hdRhBNJ7sQHHAH0fbKOeN2RJKXMXcw/XYRjOTQmsFCpT3NBHmOQiJgh
+3CdDOALtnNy4biZgOYL35bnbtFd1xUqTqC+RUgy7s3hy2qYtRkmVym6UV30Gj5TIhX2yyeiLDr3/
+jh8oFVLi0vc0q9Cc8e/OgV2APtbhFKtmd0nf+qDwJNcP//aElllnka5RtY8szPGbEOnaoDRJh56V
+hQh7aYlaHiSTBUYkTqZAtZmddvPDoR5MYP6eHmspahZP3r5gPnGg9dEPZYniwa9R4AyIBG6CLzl7
+VAb4Up6hlQbSbazZAxSnm+D37Vepi02N1mUN+kZLkuXoE+8bSkCLkoUHAggz6A1FFZrVFBOZJFF3
+yanmQKRKVeV/RYWvCiCWK+NMHrKLjqwXE7BuzG4+kwJz4yptIZG7+QQ9/y++9K2qfGzpFAKOvYVA
+QoivjQTdF68auy5ncT6ZGGsg1KSWqiU6r5yQQE7+0086p9DpxCfeFinvElNbr/k1SeAAgX0mCiNN
+dXHULePP/Gipl82oGh1JJCdAQ9LDpey65p0KEjYXXANeTZwhPYOga4BHA0oN4pwOdnTeCb5A4iZ/
+heS3mgFhvHAhevmsEhIK2h2zSF3Akf5BwgPCbpnCYkYb+ME0TdvNEiJCphU9jUE4p5X9A9dSGDJj
+khYzrG0vqQ5aTHUtA/ettxOdp4eUS7ysX0thI24EuES+7VvT4f8wgeSqBHZFzQ/CElgrRx4ExPs7
+D0v5Ej5wagiorCgqq7nJ+WVo4jzSjwP1YPz0OorE1bZuBq7lGr3Rbp63T09vP9TTzlMsJSWxGHqT
+JeKFlv86ZJ1h39w2Zj+8gJ4U4AZbOygG4bLImMVZigruDqvkaOxNreC1k+1vLgOPtZ/kWzXOwH+O
+/KlC0MjIWmtLxc4WQHgphsph364TvIk2pNXhw0kVpwDtyTQQTZ0uelX9+IewGOhxjBSp71WJ3KS6
+vd6oUylWNSjtHxK7eVyclTxCvy8AwzP5K+8lwRzhDkWw2j7nriqzZ6sBQ8sc55H3/PkQ1nhDvP3S
+Y4mETg95nQKorrqSDgb6WO6YmD7apM6gCf2H5/4poh7YLqjOw7ajEzyPcoHqdJRC+6dswNNb8pdu
+Eynk1RGGG3fnXVSGn5SSGA2S8xxJpeOPXqhwWm47l709TR53pdlNgeNlLSat/LE3Yr6f3dzCO3+M
+mLQSSv4FDwGW+hU2bHZPiUhUUQSmaa9T19pbpa6s8ZJ0xLEbS3z1xEajwM0bFGEGE+lodnN0Ziu+
+StlkG0O7ozjg6V6hRnz8KkJqNDirqESfbjE6WMHtc599lGztc/77jnBfdHd3VIuf4IgUcezITMqj
+5MGygT2/VAEb4BZAbcRxPGqKcLfYnJZ63t3QEqbgblMA1vFo4VgSV1ajLUyoDGBGLV28ExlwTut1
+HzIaED7RvsGxFpR26+1akJ1/8bReaeZFhca9QQVHRvj1X698r4C/XUsrSc+05XtjMx6HM5q1yZwu
+pU7X3s5l0gEMjqTKe4cxHPW2hjvKhiEEb66pzjN7HK0y5nrjMJxzwtfqbNV7b76TcDtX27W08c9U
+hsEprM3gDA7yAWiwAy3nxW57jdofbM5LfU0HVc1mK3FN0pfA/Fg0HWk0RX6K1vbYorZ2YFYwkpIK
+Spx8l1Y/4Kpd/0yvO9c4f8OcsEc6LfaQSV83l2H8v6NalHbhaZ2gKxmDZi/k03xDyL8v6GCn18bp
+dB5LUUJUKbnsl6q5E9b8DkJqSnAaHRLJDnEvMp6EfGlpc52On3lCg0wI5XERerziamjcMH44VZfd
+j8z1WUyHlyOSmkvZdJ66PfYWu5BxCG7hfdtSGROPtIxs36iLmesyYm4yHKwwbWgNIrLgra92DF2L
+R6e0RM1WWkcJHei4v89Nmwym4k0dKMTX1HkfTogoprrdIyDYj4qMmeTqfl0U8pRehVs6/zy4x8HS
+0V2+smFFQ/BZxLQ4eV8NHKeszc4kI6jJ3OCncsP57tfkE6TmVTtWKiimERISYB4KhUpblsbN6zyX
+Bni5ezNwl9XdaBq9c90k+QQmaMGeyQbczdGy9ufcC269vB1FU5+a67Ew8h0jPAPeYHvsw4kGsTSh
+xnhGNUHRuPoNmQYBjI2LztvnbGuoucUVntUi5quKpKAK1fOZerZTh+kr5PjaW0YlozpL5CtElvS3
+eqqkVT8a5mdW+sWTxJxTjqronag0QACsSwbA9qurCW9IdcOO+0D7nzfIJIFrWKx+D71JhKNvOmUa
+NmCy9l+wzdpcLs1zvS3o3zwEgUWOOHzITgzOxtDhIuBcJkg9lS+o5b+W+U9fplCbVFjYd5ZDa2sX
+90/8XCJA0a9VcsSrh1LoO0V3YX80VWdNPY79OUOlqftl3rNXVXE=
+`pragma protect end_protected
@@ -0,0 +1,77 @@
+// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+// DO NOT MODIFY THIS FILE.
+`timescale 1ns / 1ps
+module vio_phase_comp (
+clk,
+probe_in0,
+probe_out0,
+probe_out1,
+probe_out2,
+probe_out3,
+probe_out4,
+probe_out5,
+probe_out6,
+probe_out7,
+probe_out8
+);
+
+input clk;
+input [0 : 0] probe_in0;
+
+output reg [11 : 0] probe_out0 = 'h000 ;
+output reg [11 : 0] probe_out1 = 'h000 ;
+output reg [11 : 0] probe_out2 = 'h000 ;
+output reg [11 : 0] probe_out3 = 'h000 ;
+output reg [11 : 0] probe_out4 = 'h000 ;
+output reg [11 : 0] probe_out5 = 'h000 ;
+output reg [11 : 0] probe_out6 = 'h000 ;
+output reg [11 : 0] probe_out7 = 'h000 ;
+output reg [4 : 0] probe_out8 = 'h00 ;
+
+
+endmodule
@@ -0,0 +1,75 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+// IP VLNV: xilinx.com:ip:vio:3.0
+// IP Revision: 20
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+vio_phase_comp your_instance_name (
+  .clk(clk),                // input wire clk
+  .probe_in0(probe_in0),    // input wire [0 : 0] probe_in0
+  .probe_out0(probe_out0),  // output wire [11 : 0] probe_out0
+  .probe_out1(probe_out1),  // output wire [11 : 0] probe_out1
+  .probe_out2(probe_out2),  // output wire [11 : 0] probe_out2
+  .probe_out3(probe_out3),  // output wire [11 : 0] probe_out3
+  .probe_out4(probe_out4),  // output wire [11 : 0] probe_out4
+  .probe_out5(probe_out5),  // output wire [11 : 0] probe_out5
+  .probe_out6(probe_out6),  // output wire [11 : 0] probe_out6
+  .probe_out7(probe_out7),  // output wire [11 : 0] probe_out7
+  .probe_out8(probe_out8)  // output wire [4 : 0] probe_out8
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file vio_phase_comp.v when simulating
+// the core, vio_phase_comp. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+
@@ -0,0 +1,95 @@
+-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:vio:3.0
+-- IP Revision: 20
+
+-- The following code must appear in the VHDL architecture header.
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT vio_phase_comp
+  PORT (
+    clk : IN STD_LOGIC;
+    probe_in0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    probe_out0 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
+    probe_out1 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
+    probe_out2 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
+    probe_out3 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
+    probe_out4 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
+    probe_out5 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
+    probe_out6 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
+    probe_out7 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
+    probe_out8 : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
+  );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : vio_phase_comp
+  PORT MAP (
+    clk => clk,
+    probe_in0 => probe_in0,
+    probe_out0 => probe_out0,
+    probe_out1 => probe_out1,
+    probe_out2 => probe_out2,
+    probe_out3 => probe_out3,
+    probe_out4 => probe_out4,
+    probe_out5 => probe_out5,
+    probe_out6 => probe_out6,
+    probe_out7 => probe_out7,
+    probe_out8 => probe_out8
+  );
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+-- You must compile the wrapper file vio_phase_comp.vhd when simulating
+-- the core, vio_phase_comp. When compiling the wrapper file, be sure to
+-- reference the VHDL simulation library.
+
@@ -1,11 +1,11 @@
 // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 // --------------------------------------------------------------------------------
 // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
-// Date        : Mon May  8 19:43:16 2023
+// Date        : Tue May 16 20:22:24 2023
 // Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
 // Command     : write_verilog -force -mode synth_stub
-//               /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs7_invert_rep2_synth_1/fir_prbs7_invert_rep2_stub.v
-// Design      : fir_prbs7_invert_rep2
+//               /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.v
+// Design      : vio_phase_comp
 // Purpose     : Stub declaration of top-level module interface
 // Device      : xc7z100ffg900-2
 // --------------------------------------------------------------------------------
@@ -13,15 +13,19 @@
 // This empty module with port declaration file causes synthesis tools to infer a black box for IP.
 // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
 // Please paste the declaration into a Verilog source file or add the file as an additional source.
-(* x_core_info = "fir_compiler_v7_2_12,Vivado 2019.1.3" *)
-module fir_prbs7_invert_rep2(aresetn, aclk, s_axis_data_tvalid, 
-  s_axis_data_tready, s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata)
-/* synthesis syn_black_box black_box_pad_pin="aresetn,aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[15:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]" */;
-  input aresetn;
-  input aclk;
-  input s_axis_data_tvalid;
-  output s_axis_data_tready;
-  input [15:0]s_axis_data_tdata;
-  output m_axis_data_tvalid;
-  output [23:0]m_axis_data_tdata;
+(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
+module vio_phase_comp(clk, probe_in0, probe_out0, probe_out1, 
+  probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8)
+/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_out0[11:0],probe_out1[11:0],probe_out2[11:0],probe_out3[11:0],probe_out4[11:0],probe_out5[11:0],probe_out6[11:0],probe_out7[11:0],probe_out8[4:0]" */;
+  input clk;
+  input [0:0]probe_in0;
+  output [11:0]probe_out0;
+  output [11:0]probe_out1;
+  output [11:0]probe_out2;
+  output [11:0]probe_out3;
+  output [11:0]probe_out4;
+  output [11:0]probe_out5;
+  output [11:0]probe_out6;
+  output [11:0]probe_out7;
+  output [4:0]probe_out8;
 endmodule
@@ -0,0 +1,40 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+-- Date        : Tue May 16 20:22:24 2023
+-- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
+-- Command     : write_vhdl -force -mode synth_stub
+--               /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.vhdl
+-- Design      : vio_phase_comp
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7z100ffg900-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity vio_phase_comp is
+  Port ( 
+    clk : in STD_LOGIC;
+    probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe_out0 : out STD_LOGIC_VECTOR ( 11 downto 0 );
+    probe_out1 : out STD_LOGIC_VECTOR ( 11 downto 0 );
+    probe_out2 : out STD_LOGIC_VECTOR ( 11 downto 0 );
+    probe_out3 : out STD_LOGIC_VECTOR ( 11 downto 0 );
+    probe_out4 : out STD_LOGIC_VECTOR ( 11 downto 0 );
+    probe_out5 : out STD_LOGIC_VECTOR ( 11 downto 0 );
+    probe_out6 : out STD_LOGIC_VECTOR ( 11 downto 0 );
+    probe_out7 : out STD_LOGIC_VECTOR ( 11 downto 0 );
+    probe_out8 : out STD_LOGIC_VECTOR ( 4 downto 0 )
+  );
+
+end vio_phase_comp;
+
+architecture stub of vio_phase_comp is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[0:0],probe_out0[11:0],probe_out1[11:0],probe_out2[11:0],probe_out3[11:0],probe_out4[11:0],probe_out5[11:0],probe_out6[11:0],probe_out7[11:0],probe_out8[4:0]";
+attribute X_CORE_INFO : string;
+attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
+begin
+end;
@@ -0,0 +1,83 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required
+#             to simulate the design for a simulator, the directory structure
+#             and the generated exported files.
+#
+################################################################################
+
+1. Simulate Design
+
+To simulate design, cd to the simulator directory and execute the script.
+
+For example:-
+
+% cd questa
+% ./top.sh
+
+The export simulation flow requires the Xilinx pre-compiled simulation library
+components for the target simulator. These components are referred using the
+'-lib_map_path' switch. If this switch is specified, then the export simulation
+will automatically set this library path in the generated script and update,
+copy the simulator setup file(s) in the exported directory.
+
+If '-lib_map_path' is not specified, then the pre-compiled simulation library
+information will not be included in the exported scripts and that may cause
+simulation errors when running this script. Alternatively, you can provide the
+library information using this switch while executing the generated script.
+
+For example:-
+
+% ./top.sh -lib_map_path /design/questa/clibs
+
+Please refer to the generated script header 'Prerequisite' section for more details.
+
+2. Directory Structure
+
+By default, if the -directory switch is not specified, export_simulation will
+create the following directory structure:-
+
+<current_working_directory>/export_sim/<simulator>
+
+For example, if the current working directory is /tmp/test, export_simulation
+will create the following directory path:-
+
+/tmp/test/export_sim/questa
+
+If -directory switch is specified, export_simulation will create a simulator
+sub-directory under the specified directory path.
+
+For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
+command will create the following directory:-
+
+/tmp/test/my_test_area/func_sim/questa
+
+By default, if -simulator is not specified, export_simulation will create a
+simulator sub-directory for each simulator and export the files for each simulator
+in this sub-directory respectively.
+
+IMPORTANT: Please note that the simulation library path must be specified manually
+in the generated script for the respective simulator. Please refer to the generated
+script header 'Prerequisite' section for more details.
+
+3. Exported script and files
+
+Export simulation will create the driver shell script, setup files and copy the
+design sources in the output directory path.
+
+By default, when the -script_name switch is not specified, export_simulation will
+create the following script name:-
+
+<simulation_top>.sh  (Unix)
+When exporting the files for an IP using the -of_objects switch, export_simulation
+will create the following script name:-
+
+<ip-name>.sh  (Unix)
+Export simulation will create the setup files for the target simulator specified
+with the -simulator switch.
+
+For example, if the target simulator is "ies", export_simulation will create the
+'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
+file.
+
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue May 16 20:15:18 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./cmpy_12_12.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './cmpy_12_12.sh' script.
+
+./cmpy_12_12.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./cmpy_12_12.sh -noclean_files
+
+For more information on the script, please type './cmpy_12_12.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
@@ -0,0 +1,152 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : cmpy_12_12.sh
+# Simulator   : Aldec Active-HDL Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue May 16 20:15:18 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: cmpy_12_12.sh [-help]
+# usage: cmpy_12_12.sh [-lib_map_path]
+# usage: cmpy_12_12.sh [-noclean_files]
+# usage: cmpy_12_12.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'cmpy_12_12.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "cmpy_12_12.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_12_12.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  lib_map_path=""
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_12_12.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: cmpy_12_12.sh [-help]\n\
+Usage: cmpy_12_12.sh [-lib_map_path]\n\
+Usage: cmpy_12_12.sh [-reset_run]\n\
+Usage: cmpy_12_12.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
@@ -0,0 +1,52 @@
+vlib work
+vlib activehdl
+
+vlib activehdl/xil_defaultlib
+vlib activehdl/xpm
+vlib activehdl/xbip_utils_v3_0_10
+vlib activehdl/axi_utils_v2_0_6
+vlib activehdl/xbip_pipe_v3_0_6
+vlib activehdl/xbip_bram18k_v3_0_6
+vlib activehdl/mult_gen_v12_0_15
+vlib activehdl/cmpy_v6_0_17
+
+vmap xil_defaultlib activehdl/xil_defaultlib
+vmap xpm activehdl/xpm
+vmap xbip_utils_v3_0_10 activehdl/xbip_utils_v3_0_10
+vmap axi_utils_v2_0_6 activehdl/axi_utils_v2_0_6
+vmap xbip_pipe_v3_0_6 activehdl/xbip_pipe_v3_0_6
+vmap xbip_bram18k_v3_0_6 activehdl/xbip_bram18k_v3_0_6
+vmap mult_gen_v12_0_15 activehdl/mult_gen_v12_0_15
+vmap cmpy_v6_0_17 activehdl/cmpy_v6_0_17
+
+vlog -work xil_defaultlib  -sv2k12 \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vcom -work xbip_utils_v3_0_10 -93 \
+"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
+
+vcom -work axi_utils_v2_0_6 -93 \
+"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \
+
+vcom -work xbip_pipe_v3_0_6 -93 \
+"../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \
+
+vcom -work xbip_bram18k_v3_0_6 -93 \
+"../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \
+
+vcom -work mult_gen_v12_0_15 -93 \
+"../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \
+
+vcom -work cmpy_v6_0_17 -93 \
+"../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../ip/cmpy_12_12/sim/cmpy_12_12.vhd" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
@@ -0,0 +1,11 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
+axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
+xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
+xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd,
+mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd,
+cmpy_v6_0_vh_rfs.vhd,vhdl,cmpy_v6_0_17,../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd,
+cmpy_12_12.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_12_12/sim/cmpy_12_12.vhd,
+glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif
@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim -t 1ps +access +r +m+cmpy_12_12 -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L cmpy_v6_0_17 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.cmpy_12_12 xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {cmpy_12_12.udo}
+
+run -all
+
+endsim
+
+quit -force
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue May 16 20:15:18 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./cmpy_12_12.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './cmpy_12_12.sh' script.
+
+./cmpy_12_12.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./cmpy_12_12.sh -noclean_files
+
+For more information on the script, please type './cmpy_12_12.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
@@ -0,0 +1,175 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : cmpy_12_12.sh
+# Simulator   : Cadence Incisive Enterprise Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue May 16 20:15:18 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: cmpy_12_12.sh [-help]
+# usage: cmpy_12_12.sh [-lib_map_path]
+# usage: cmpy_12_12.sh [-noclean_files]
+# usage: cmpy_12_12.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'cmpy_12_12.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xil_defaultlib xpm xbip_utils_v3_0_10 axi_utils_v2_0_6 xbip_pipe_v3_0_6 xbip_bram18k_v3_0_6 mult_gen_v12_0_15 cmpy_v6_0_17)
+
+# Simulation root library directory
+sim_lib_dir="ies_lib"
+
+# Script info
+echo -e "cmpy_12_12.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  irun $irun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.cmpy_12_12 \
+       -f run.f \
+       -top glbl \
+       glbl.v
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_12_12.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_12_12.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: cmpy_12_12.sh [-help]\n\
+Usage: cmpy_12_12.sh [-lib_map_path]\n\
+Usage: cmpy_12_12.sh [-reset_run]\n\
+Usage: cmpy_12_12.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
@@ -0,0 +1,11 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
+axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
+xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
+xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd,
+mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd,
+cmpy_v6_0_vh_rfs.vhd,vhdl,cmpy_v6_0_17,../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd,
+cmpy_12_12.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_12_12/sim/cmpy_12_12.vhd,
+glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif
@@ -0,0 +1,32 @@
+-makelib ies_lib/xil_defaultlib -sv \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+-endlib
+-makelib ies_lib/xpm \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib ies_lib/xbip_utils_v3_0_10 \
+  "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
+-endlib
+-makelib ies_lib/axi_utils_v2_0_6 \
+  "../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \
+-endlib
+-makelib ies_lib/xbip_pipe_v3_0_6 \
+  "../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \
+-endlib
+-makelib ies_lib/xbip_bram18k_v3_0_6 \
+  "../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \
+-endlib
+-makelib ies_lib/mult_gen_v12_0_15 \
+  "../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \
+-endlib
+-makelib ies_lib/cmpy_v6_0_17 \
+  "../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../ip/cmpy_12_12/sim/cmpy_12_12.vhd" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  glbl.v
+-endlib
+
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue May 16 20:15:18 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./cmpy_12_12.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './cmpy_12_12.sh' script.
+
+./cmpy_12_12.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./cmpy_12_12.sh -noclean_files
+
+For more information on the script, please type './cmpy_12_12.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
@@ -0,0 +1,168 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : cmpy_12_12.sh
+# Simulator   : Mentor Graphics ModelSim Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue May 16 20:15:18 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: cmpy_12_12.sh [-help]
+# usage: cmpy_12_12.sh [-lib_map_path]
+# usage: cmpy_12_12.sh [-noclean_files]
+# usage: cmpy_12_12.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'cmpy_12_12.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "cmpy_12_12.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_12_12.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
+  if [[ ($1 != "" && -e $1) ]]; then
+    lib_map_path="$1"
+  else
+    echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="modelsim_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_12_12.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: cmpy_12_12.sh [-help]\n\
+Usage: cmpy_12_12.sh [-lib_map_path]\n\
+Usage: cmpy_12_12.sh [-reset_run]\n\
+Usage: cmpy_12_12.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
@@ -0,0 +1,52 @@
+vlib modelsim_lib/work
+vlib modelsim_lib/msim
+
+vlib modelsim_lib/msim/xil_defaultlib
+vlib modelsim_lib/msim/xpm
+vlib modelsim_lib/msim/xbip_utils_v3_0_10
+vlib modelsim_lib/msim/axi_utils_v2_0_6
+vlib modelsim_lib/msim/xbip_pipe_v3_0_6
+vlib modelsim_lib/msim/xbip_bram18k_v3_0_6
+vlib modelsim_lib/msim/mult_gen_v12_0_15
+vlib modelsim_lib/msim/cmpy_v6_0_17
+
+vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
+vmap xpm modelsim_lib/msim/xpm
+vmap xbip_utils_v3_0_10 modelsim_lib/msim/xbip_utils_v3_0_10
+vmap axi_utils_v2_0_6 modelsim_lib/msim/axi_utils_v2_0_6
+vmap xbip_pipe_v3_0_6 modelsim_lib/msim/xbip_pipe_v3_0_6
+vmap xbip_bram18k_v3_0_6 modelsim_lib/msim/xbip_bram18k_v3_0_6
+vmap mult_gen_v12_0_15 modelsim_lib/msim/mult_gen_v12_0_15
+vmap cmpy_v6_0_17 modelsim_lib/msim/cmpy_v6_0_17
+
+vlog -work xil_defaultlib -64 -incr -sv \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -64 -93 \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vcom -work xbip_utils_v3_0_10 -64 -93 \
+"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
+
+vcom -work axi_utils_v2_0_6 -64 -93 \
+"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \
+
+vcom -work xbip_pipe_v3_0_6 -64 -93 \
+"../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \
+
+vcom -work xbip_bram18k_v3_0_6 -64 -93 \
+"../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \
+
+vcom -work mult_gen_v12_0_15 -64 -93 \
+"../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \
+
+vcom -work cmpy_v6_0_17 -64 -93 \
+"../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../ip/cmpy_12_12/sim/cmpy_12_12.vhd" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
@@ -0,0 +1,11 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
+axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
+xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
+xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd,
+mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd,
+cmpy_v6_0_vh_rfs.vhd,vhdl,cmpy_v6_0_17,../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd,
+cmpy_12_12.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_12_12/sim/cmpy_12_12.vhd,
+glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif
@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L cmpy_v6_0_17 -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.cmpy_12_12 xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {cmpy_12_12.udo}
+
+run -all
+
+quit -force
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue May 16 20:15:18 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./cmpy_12_12.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './cmpy_12_12.sh' script.
+
+./cmpy_12_12.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./cmpy_12_12.sh -noclean_files
+
+For more information on the script, please type './cmpy_12_12.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
@@ -0,0 +1,173 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : cmpy_12_12.sh
+# Simulator   : Mentor Graphics Questa Advanced Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue May 16 20:15:18 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: cmpy_12_12.sh [-help]
+# usage: cmpy_12_12.sh [-lib_map_path]
+# usage: cmpy_12_12.sh [-noclean_files]
+# usage: cmpy_12_12.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'cmpy_12_12.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "cmpy_12_12.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  source elaborate.do 2>&1 | tee -a elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_12_12.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  lib_map_path=""
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="questa_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_12_12.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: cmpy_12_12.sh [-help]\n\
+Usage: cmpy_12_12.sh [-lib_map_path]\n\
+Usage: cmpy_12_12.sh [-reset_run]\n\
+Usage: cmpy_12_12.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
@@ -0,0 +1,52 @@
+vlib questa_lib/work
+vlib questa_lib/msim
+
+vlib questa_lib/msim/xil_defaultlib
+vlib questa_lib/msim/xpm
+vlib questa_lib/msim/xbip_utils_v3_0_10
+vlib questa_lib/msim/axi_utils_v2_0_6
+vlib questa_lib/msim/xbip_pipe_v3_0_6
+vlib questa_lib/msim/xbip_bram18k_v3_0_6
+vlib questa_lib/msim/mult_gen_v12_0_15
+vlib questa_lib/msim/cmpy_v6_0_17
+
+vmap xil_defaultlib questa_lib/msim/xil_defaultlib
+vmap xpm questa_lib/msim/xpm
+vmap xbip_utils_v3_0_10 questa_lib/msim/xbip_utils_v3_0_10
+vmap axi_utils_v2_0_6 questa_lib/msim/axi_utils_v2_0_6
+vmap xbip_pipe_v3_0_6 questa_lib/msim/xbip_pipe_v3_0_6
+vmap xbip_bram18k_v3_0_6 questa_lib/msim/xbip_bram18k_v3_0_6
+vmap mult_gen_v12_0_15 questa_lib/msim/mult_gen_v12_0_15
+vmap cmpy_v6_0_17 questa_lib/msim/cmpy_v6_0_17
+
+vlog -work xil_defaultlib -64 -sv \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -64 -93 \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vcom -work xbip_utils_v3_0_10 -64 -93 \
+"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
+
+vcom -work axi_utils_v2_0_6 -64 -93 \
+"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \
+
+vcom -work xbip_pipe_v3_0_6 -64 -93 \
+"../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \
+
+vcom -work xbip_bram18k_v3_0_6 -64 -93 \
+"../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \
+
+vcom -work mult_gen_v12_0_15 -64 -93 \
+"../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \
+
+vcom -work cmpy_v6_0_17 -64 -93 \
+"../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../ip/cmpy_12_12/sim/cmpy_12_12.vhd" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
@@ -0,0 +1 @@
+vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L cmpy_v6_0_17 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.cmpy_12_12 xil_defaultlib.glbl -o cmpy_12_12_opt
@@ -0,0 +1,11 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
+axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
+xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
+xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd,
+mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd,
+cmpy_v6_0_vh_rfs.vhd,vhdl,cmpy_v6_0_17,../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd,
+cmpy_12_12.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_12_12/sim/cmpy_12_12.vhd,
+glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif
@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -t 1ps -lib xil_defaultlib cmpy_12_12_opt
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {cmpy_12_12.udo}
+
+run -all
+
+quit -force
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue May 16 20:15:18 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./cmpy_12_12.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './cmpy_12_12.sh' script.
+
+./cmpy_12_12.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./cmpy_12_12.sh -noclean_files
+
+For more information on the script, please type './cmpy_12_12.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
@@ -0,0 +1,152 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : cmpy_12_12.sh
+# Simulator   : Aldec Riviera-PRO Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue May 16 20:15:18 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: cmpy_12_12.sh [-help]
+# usage: cmpy_12_12.sh [-lib_map_path]
+# usage: cmpy_12_12.sh [-noclean_files]
+# usage: cmpy_12_12.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'cmpy_12_12.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "cmpy_12_12.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_12_12.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  lib_map_path=""
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_12_12.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: cmpy_12_12.sh [-help]\n\
+Usage: cmpy_12_12.sh [-lib_map_path]\n\
+Usage: cmpy_12_12.sh [-reset_run]\n\
+Usage: cmpy_12_12.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
@@ -0,0 +1,52 @@
+vlib work
+vlib riviera
+
+vlib riviera/xil_defaultlib
+vlib riviera/xpm
+vlib riviera/xbip_utils_v3_0_10
+vlib riviera/axi_utils_v2_0_6
+vlib riviera/xbip_pipe_v3_0_6
+vlib riviera/xbip_bram18k_v3_0_6
+vlib riviera/mult_gen_v12_0_15
+vlib riviera/cmpy_v6_0_17
+
+vmap xil_defaultlib riviera/xil_defaultlib
+vmap xpm riviera/xpm
+vmap xbip_utils_v3_0_10 riviera/xbip_utils_v3_0_10
+vmap axi_utils_v2_0_6 riviera/axi_utils_v2_0_6
+vmap xbip_pipe_v3_0_6 riviera/xbip_pipe_v3_0_6
+vmap xbip_bram18k_v3_0_6 riviera/xbip_bram18k_v3_0_6
+vmap mult_gen_v12_0_15 riviera/mult_gen_v12_0_15
+vmap cmpy_v6_0_17 riviera/cmpy_v6_0_17
+
+vlog -work xil_defaultlib  -sv2k12 \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vcom -work xbip_utils_v3_0_10 -93 \
+"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
+
+vcom -work axi_utils_v2_0_6 -93 \
+"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \
+
+vcom -work xbip_pipe_v3_0_6 -93 \
+"../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \
+
+vcom -work xbip_bram18k_v3_0_6 -93 \
+"../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \
+
+vcom -work mult_gen_v12_0_15 -93 \
+"../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \
+
+vcom -work cmpy_v6_0_17 -93 \
+"../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../ip/cmpy_12_12/sim/cmpy_12_12.vhd" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
@@ -0,0 +1,11 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
+axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
+xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
+xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd,
+mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd,
+cmpy_v6_0_vh_rfs.vhd,vhdl,cmpy_v6_0_17,../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd,
+cmpy_12_12.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_12_12/sim/cmpy_12_12.vhd,
+glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif
@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim -t 1ps +access +r +m+cmpy_12_12 -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L cmpy_v6_0_17 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.cmpy_12_12 xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {cmpy_12_12.udo}
+
+run -all
+
+endsim
+
+quit -force
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue May 16 20:15:18 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./cmpy_12_12.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './cmpy_12_12.sh' script.
+
+./cmpy_12_12.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./cmpy_12_12.sh -noclean_files
+
+For more information on the script, please type './cmpy_12_12.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
@@ -0,0 +1,253 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : cmpy_12_12.sh
+# Simulator   : Synopsys Verilog Compiler Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue May 16 20:15:18 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: cmpy_12_12.sh [-help]
+# usage: cmpy_12_12.sh [-lib_map_path]
+# usage: cmpy_12_12.sh [-noclean_files]
+# usage: cmpy_12_12.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'cmpy_12_12.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Command line options
+vlogan_opts="-full64"
+vhdlan_opts="-full64"
+vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log"
+vcs_sim_opts="-ucli -licqueue -l simulate.log"
+
+# Design libraries
+design_libs=(xil_defaultlib xpm xbip_utils_v3_0_10 axi_utils_v2_0_6 xbip_pipe_v3_0_6 xbip_bram18k_v3_0_6 mult_gen_v12_0_15 cmpy_v6_0_17)
+
+# Simulation root library directory
+sim_lib_dir="vcs_lib"
+
+# Script info
+echo -e "cmpy_12_12.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  vlogan -work xil_defaultlib $vlogan_opts -sverilog \
+    "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+    "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+  2>&1 | tee -a vlogan.log
+
+  vhdlan -work xpm $vhdlan_opts \
+    "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work xbip_utils_v3_0_10 $vhdlan_opts \
+    "$ref_dir/../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work axi_utils_v2_0_6 $vhdlan_opts \
+    "$ref_dir/../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work xbip_pipe_v3_0_6 $vhdlan_opts \
+    "$ref_dir/../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work xbip_bram18k_v3_0_6 $vhdlan_opts \
+    "$ref_dir/../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work mult_gen_v12_0_15 $vhdlan_opts \
+    "$ref_dir/../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work cmpy_v6_0_17 $vhdlan_opts \
+    "$ref_dir/../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+  vhdlan -work xil_defaultlib $vhdlan_opts \
+    "$ref_dir/../../../ip/cmpy_12_12/sim/cmpy_12_12.vhd" \
+  2>&1 | tee -a vhdlan.log
+
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k \
+    glbl.v \
+  2>&1 | tee -a vlogan.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  vcs $vcs_elab_opts xil_defaultlib.cmpy_12_12 xil_defaultlib.glbl -o cmpy_12_12_simv
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  ./cmpy_12_12_simv $vcs_sim_opts -do simulate.do
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_12_12.sh -help\" for more information)\n"
+        exit 1
+      fi
+      create_lib_mappings $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+      create_lib_mappings $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Define design library mappings
+create_lib_mappings()
+{
+  file="synopsys_sim.setup"
+  if [[ -e $file ]]; then
+    if [[ ($1 == "") ]]; then
+      return
+    else
+      rm -rf $file
+    fi
+  fi
+
+  touch $file
+
+  lib_map_path=""
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    mapping="$lib:$sim_lib_dir/$lib"
+    echo $mapping >> $file
+  done
+
+  if [[ ($lib_map_path != "") ]]; then
+    incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup"
+    echo $incl_ref >> $file
+  fi
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ucli.key cmpy_12_12_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc cmpy_12_12_simv.daidir)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_12_12.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: cmpy_12_12.sh [-help]\n\
+Usage: cmpy_12_12.sh [-lib_map_path]\n\
+Usage: cmpy_12_12.sh [-reset_run]\n\
+Usage: cmpy_12_12.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
@@ -0,0 +1,11 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
+axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
+xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
+xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd,
+mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd,
+cmpy_v6_0_vh_rfs.vhd,vhdl,cmpy_v6_0_17,../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd,
+cmpy_12_12.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_12_12/sim/cmpy_12_12.vhd,
+glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif
@@ -0,0 +1,2 @@
+run
+quit
@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue May 16 20:15:18 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./cmpy_12_12.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './cmpy_12_12.sh' script.
+
+./cmpy_12_12.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./cmpy_12_12.sh -noclean_files
+
+For more information on the script, please type './cmpy_12_12.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
@@ -0,0 +1,175 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : cmpy_12_12.sh
+# Simulator   : Cadence Xcelium Parallel Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue May 16 20:15:18 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: cmpy_12_12.sh [-help]
+# usage: cmpy_12_12.sh [-lib_map_path]
+# usage: cmpy_12_12.sh [-noclean_files]
+# usage: cmpy_12_12.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'cmpy_12_12.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xil_defaultlib xpm xbip_utils_v3_0_10 axi_utils_v2_0_6 xbip_pipe_v3_0_6 xbip_bram18k_v3_0_6 mult_gen_v12_0_15 cmpy_v6_0_17)
+
+# Simulation root library directory
+sim_lib_dir="xcelium_lib"
+
+# Script info
+echo -e "cmpy_12_12.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  xrun $xrun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.cmpy_12_12 \
+       -f run.f \
+       -top glbl \
+       glbl.v
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_12_12.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_12_12.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: cmpy_12_12.sh [-help]\n\
+Usage: cmpy_12_12.sh [-lib_map_path]\n\
+Usage: cmpy_12_12.sh [-reset_run]\n\
+Usage: cmpy_12_12.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
@@ -0,0 +1,11 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
+axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,
+xbip_pipe_v3_0_vh_rfs.vhd,vhdl,xbip_pipe_v3_0_6,../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd,
+xbip_bram18k_v3_0_vh_rfs.vhd,vhdl,xbip_bram18k_v3_0_6,../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd,
+mult_gen_v12_0_vh_rfs.vhd,vhdl,mult_gen_v12_0_15,../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd,
+cmpy_v6_0_vh_rfs.vhd,vhdl,cmpy_v6_0_17,../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd,
+cmpy_12_12.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_12_12/sim/cmpy_12_12.vhd,
+glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif
@@ -0,0 +1,32 @@
+-makelib xcelium_lib/xil_defaultlib -sv \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+-endlib
+-makelib xcelium_lib/xpm \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib xcelium_lib/xbip_utils_v3_0_10 \
+  "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
+-endlib
+-makelib xcelium_lib/axi_utils_v2_0_6 \
+  "../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \
+-endlib
+-makelib xcelium_lib/xbip_pipe_v3_0_6 \
+  "../../../ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd" \
+-endlib
+-makelib xcelium_lib/xbip_bram18k_v3_0_6 \
+  "../../../ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd" \
+-endlib
+-makelib xcelium_lib/mult_gen_v12_0_15 \
+  "../../../ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd" \
+-endlib
+-makelib xcelium_lib/cmpy_v6_0_17 \
+  "../../../ipstatic/hdl/cmpy_v6_0_vh_rfs.vhd" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../ip/cmpy_12_12/sim/cmpy_12_12.vhd" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  glbl.v
+-endlib
+
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Tue May 16 20:15:18 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./cmpy_12_12.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './cmpy_12_12.sh' script.
+
+./cmpy_12_12.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./cmpy_12_12.sh -noclean_files
+
+For more information on the script, please type './cmpy_12_12.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.
@@ -0,0 +1,12 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+  if { [llength [get_objects]] > 0} {
+    add_wave /
+    set_property needs_save false [current_wave_config]
+  } else {
+     send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+  }
+}
+
+run -all
+quit
@@ -0,0 +1,214 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : cmpy_12_12.sh
+# Simulator   : Xilinx Vivado Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Tue May 16 20:15:18 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: cmpy_12_12.sh [-help]
+# usage: cmpy_12_12.sh [-lib_map_path]
+# usage: cmpy_12_12.sh [-noclean_files]
+# usage: cmpy_12_12.sh [-reset_run]
+#
+#*********************************************************************************************************
+
+# Command line options
+xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0
+xvlog_opts="--relax"
+xvhdl_opts="--relax"
+
+
+# Script info
+echo -e "cmpy_12_12.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log
+  xvhdl $xvhdl_opts -prj vhdl.prj 2>&1 | tee compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  xelab --relax --debug typical --mt auto -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L cmpy_v6_0_17 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot cmpy_12_12 xil_defaultlib.cmpy_12_12 xil_defaultlib.glbl -log elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  xsim cmpy_12_12 -key {Behavioral:sim_1:Functional:cmpy_12_12} -tclbatch cmd.tcl -log simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./cmpy_12_12.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy xsim.ini file
+copy_setup_file()
+{
+  file="xsim.ini"
+  lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      cp $src_file .
+    fi
+
+    # Map local design libraries to xsim.ini
+    map_local_libs
+
+  fi
+}
+
+# Map local design libraries
+map_local_libs()
+{
+  updated_mappings=()
+  local_mappings=()
+
+  # Local design libraries
+  local_libs=()
+
+  if [[ 0 == ${#local_libs[@]} ]]; then
+    return
+  fi
+
+  file="xsim.ini"
+  file_backup="xsim.ini.bak"
+
+  if [[ -e $file ]]; then
+    rm -f $file_backup
+    # Create a backup copy of the xsim.ini file
+    cp $file $file_backup
+    # Read libraries from backup file and search in local library collection
+    while read -r line
+    do
+      IN=$line
+      # Split mapping entry with '=' delimiter to fetch library name and mapping
+      read lib_name mapping <<<$(IFS="="; echo $IN)
+      # If local library found, then construct the local mapping and add to local mapping collection
+      if `echo ${local_libs[@]} | grep -wq $lib_name` ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        local_mappings+=("$lib_name")
+      fi
+      # Add to updated library mapping collection
+      updated_mappings+=("$line")
+    done < "$file_backup"
+    # Append local libraries not found originally from xsim.ini
+    for (( i=0; i<${#local_libs[*]}; i++ )); do
+      lib_name="${local_libs[i]}"
+      if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        updated_mappings+=("$line")
+      fi
+    done
+    # Write updated mappings in xsim.ini
+    rm -f $file
+    for (( i=0; i<${#updated_mappings[*]}; i++ )); do
+      lib_name="${updated_mappings[i]}"
+      echo $lib_name >> $file
+    done
+  else
+    for (( i=0; i<${#local_libs[*]}; i++ )); do
+      lib_name="${local_libs[i]}"
+      mapping="$lib_name=xsim.dir/$lib_name"
+      echo $mapping >> $file
+    done
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb cmpy_12_12.wdb xsim.dir)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./cmpy_12_12.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: cmpy_12_12.sh [-help]\n\
+Usage: cmpy_12_12.sh [-lib_map_path]\n\
+Usage: cmpy_12_12.sh [-reset_run]\n\
+Usage: cmpy_12_12.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2
@@ -0,0 +1,2 @@
+cmpy_12_12.vhd,vhdl,xil_defaultlib,../../../ip/cmpy_12_12/sim/cmpy_12_12.vhd,
+glbl.v,Verilog,xil_defaultlib,glbl.v
@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif
@@ -0,0 +1,4 @@
+vhdl xil_defaultlib  \
+"../../../ip/cmpy_12_12/sim/cmpy_12_12.vhd" \
+
+nosort
@@ -0,0 +1,4 @@
+
+verilog xil_defaultlib "glbl.v"
+
+nosort
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Mon May 08 19:42:46 CST 2023
+# Generated by export_simulation on Tue May 16 20:24:34 CST 2023
 #
 ################################################################################

@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Mon May 08 19:42:46 CST 2023
+# Generated by Vivado on Tue May 16 20:24:34 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Mon May 08 19:42:46 CST 2023
+# Generated by export_simulation on Tue May 16 20:24:34 CST 2023
 #
 ################################################################################

@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Mon May 08 19:42:46 CST 2023
+# Generated by Vivado on Tue May 16 20:24:34 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Mon May 08 19:42:46 CST 2023
+# Generated by export_simulation on Tue May 16 20:24:34 CST 2023
 #
 ################################################################################

@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Mon May 08 19:42:46 CST 2023
+# Generated by Vivado on Tue May 16 20:24:34 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Mon May 08 19:42:46 CST 2023
+# Generated by export_simulation on Tue May 16 20:24:34 CST 2023
 #
 ################################################################################

@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Mon May 08 19:42:46 CST 2023
+# Generated by Vivado on Tue May 16 20:24:34 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Mon May 08 19:42:46 CST 2023
+# Generated by export_simulation on Tue May 16 20:24:34 CST 2023
 #
 ################################################################################

@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Mon May 08 19:42:46 CST 2023
+# Generated by Vivado on Tue May 16 20:24:34 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Mon May 08 19:42:46 CST 2023
+# Generated by export_simulation on Tue May 16 20:24:34 CST 2023
 #
 ################################################################################

@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Mon May 08 19:42:46 CST 2023
+# Generated by Vivado on Tue May 16 20:24:34 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
@@ -4,7 +4,7 @@
 # README.txt: Please read the sections below to understand the steps required to
 #             run the exported script and information about the source files.
 #
-# Generated by export_simulation on Mon May 08 19:42:46 CST 2023
+# Generated by export_simulation on Tue May 16 20:24:34 CST 2023
 #
 ################################################################################

@@ -9,7 +9,7 @@
 #               directory, add the library logical mappings in the simulator setup file, create default
 #               'do/prj' file, execute compilation, elaboration and simulation steps.
 #
-# Generated by Vivado on Mon May 08 19:42:46 CST 2023
+# Generated by Vivado on Tue May 16 20:24:34 CST 2023
 # SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
 #
 # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
--- a/Show More
+++ b/Show More
				`@@ -0,0 +1 @@`
				`vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L cmpy_v6_0_17 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.cmpy_12_12 xil_defaultlib.glbl -o cmpy_12_12_opt`