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add phase compensate to duifei online acq

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josh
2023-05-16 20:44:17 +08:00
parent 986a2ea1e1
commit b2a6a62da0
249 changed files with 15824 additions and 2162 deletions
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projects/duifei/duifei_online_acq_par/project.tcl
+35 -11
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@@ -3,7 +3,7 @@
#
# project.tcl: Tcl script for re-creating project 'project'
#
# Generated by Vivado on Fri May 12 10:07:34 CST 2023
# Generated by Vivado on Tue May 16 20:40:18 CST 2023
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
@@ -27,6 +27,7 @@
#
# 3. The following remote source files that were added to the original project:-
#
# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_phase_comp/vio_phase_comp.xci"
# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/ila_freq_comp/ila_freq_comp.xci"
# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/vio_freq_comp/vio_freq_comp.xci"
# "/home/josh/Workspace/vivado-git/projects/duifei/common_ip/basic_driver/vio_manual_ctrl/vio_manual_ctrl.xci"
@@ -44,6 +45,7 @@
# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/cmpy_12x8/cmpy_12x8.xci"
# "/home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci"
# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/fifo_rx_data/fifo_rx_data.xci"
# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/cmpy_12_12/cmpy_12_12.xci"
# "/home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xci"
# "/home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8.xci"
# "/home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/tx_qpsk/ip/hop_rom/hop_rom.xci"
@@ -78,12 +80,14 @@
# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/freq_comp.v"
# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/mgc_ctrl.v"
# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/mod2_rom.v"
# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/phase_compensate.v"
# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/rf_auto_switch_freq.v"
# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/rx_dmf.v"
# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/spi_master.v"
# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/spi_salve.v"
# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/Sisyif_src/spi_tx.v"
# "/home/josh/Workspace/vivado-git/projects/duifei/common_ipi-bd/basic_driver_bd/hdl/system_bd_wrapper.v"
# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/trunc_32bit_to_12bit.v"
# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/tx_pre_process.v"
# "/home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/tx_qpsk/rtl/tx_qpsk.v"
# "/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/rtl/system_top.v"
@@ -205,15 +209,15 @@ set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_use
set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
set_property -name "simulator_language" -value "Mixed" -objects $obj
set_property -name "target_simulator" -value "VCS" -objects $obj
set_property -name "webtalk.activehdl_export_sim" -value "55" -objects $obj
set_property -name "webtalk.ies_export_sim" -value "55" -objects $obj
set_property -name "webtalk.modelsim_export_sim" -value "55" -objects $obj
set_property -name "webtalk.questa_export_sim" -value "55" -objects $obj
set_property -name "webtalk.riviera_export_sim" -value "55" -objects $obj
set_property -name "webtalk.vcs_export_sim" -value "55" -objects $obj
set_property -name "webtalk.activehdl_export_sim" -value "57" -objects $obj
set_property -name "webtalk.ies_export_sim" -value "57" -objects $obj
set_property -name "webtalk.modelsim_export_sim" -value "57" -objects $obj
set_property -name "webtalk.questa_export_sim" -value "57" -objects $obj
set_property -name "webtalk.riviera_export_sim" -value "57" -objects $obj
set_property -name "webtalk.vcs_export_sim" -value "57" -objects $obj
set_property -name "webtalk.vcs_launch_sim" -value "59" -objects $obj
set_property -name "webtalk.xcelium_export_sim" -value "3" -objects $obj
set_property -name "webtalk.xsim_export_sim" -value "55" -objects $obj
set_property -name "webtalk.xcelium_export_sim" -value "2" -objects $obj
set_property -name "webtalk.xsim_export_sim" -value "57" -objects $obj
set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj
# Create 'sources_1' fileset (if not found)
@@ -231,6 +235,7 @@ update_ip_catalog -rebuild
# Set 'sources_1' fileset object
set obj [get_filesets sources_1]
set files [list \
[file normalize "${origin_dir}/ip/vio_phase_comp/vio_phase_comp.xci"] \
[file normalize "${origin_dir}/ip/ila_freq_comp/ila_freq_comp.xci"] \
[file normalize "${origin_dir}/ip/vio_freq_comp/vio_freq_comp.xci"] \
[file normalize "${origin_dir}/../common_ip/basic_driver/vio_manual_ctrl/vio_manual_ctrl.xci"] \
@@ -248,6 +253,7 @@ set files [list \
[file normalize "${origin_dir}/ip/cmpy_12x8/cmpy_12x8.xci"] \
[file normalize "${origin_dir}/../../../modules/xc7z100ffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci"] \
[file normalize "${origin_dir}/ip/fifo_rx_data/fifo_rx_data.xci"] \
[file normalize "${origin_dir}/ip/cmpy_12_12/cmpy_12_12.xci"] \
[file normalize "${origin_dir}/../../../modules/xc7z100ffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xci"] \
[file normalize "${origin_dir}/../../../modules/xc7z100ffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8.xci"] \
[file normalize "${origin_dir}/../../../modules/xc7z100ffg900-2/tx_qpsk/ip/hop_rom/hop_rom.xci"] \
@@ -282,12 +288,14 @@ set files [list \
[file normalize "${origin_dir}/rtl/freq_comp.v"] \
[file normalize "${origin_dir}/rtl/Sisyif_src/mgc_ctrl.v"] \
[file normalize "${origin_dir}/rtl/Sisyif_src/mod2_rom.v"] \
[file normalize "${origin_dir}/rtl/phase_compensate.v"] \
[file normalize "${origin_dir}/rtl/rf_auto_switch_freq.v"] \
[file normalize "${origin_dir}/rtl/rx_dmf.v"] \
[file normalize "${origin_dir}/rtl/Sisyif_src/spi_master.v"] \
[file normalize "${origin_dir}/rtl/Sisyif_src/spi_salve.v"] \
[file normalize "${origin_dir}/rtl/Sisyif_src/spi_tx.v"] \
[file normalize "${origin_dir}/../common_ipi-bd/basic_driver_bd/hdl/system_bd_wrapper.v"] \
[file normalize "${origin_dir}/rtl/trunc_32bit_to_12bit.v"] \
[file normalize "${origin_dir}/rtl/tx_pre_process.v"] \
[file normalize "${origin_dir}/../../../modules/xc7z100ffg900-2/tx_qpsk/rtl/tx_qpsk.v"] \
[file normalize "${origin_dir}/rtl/system_top.v"] \
@@ -303,6 +311,15 @@ set files [list \
add_files -norecurse -fileset $obj $files
# Set 'sources_1' fileset file properties for remote files
set file "$origin_dir/ip/vio_phase_comp/vio_phase_comp.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
set_property -name "registered_with_manager" -value "1" -objects $file_obj
if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
set file "$origin_dir/ip/ila_freq_comp/ila_freq_comp.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
@@ -456,6 +473,15 @@ if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
set file "$origin_dir/ip/cmpy_12_12/cmpy_12_12.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
set_property -name "registered_with_manager" -value "1" -objects $file_obj
if { ![get_property "is_locked" $file_obj] } {
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
}
set file "$origin_dir/../../../modules/xc7z100ffg900-2/ad9361_mapping/ip/ad9361_fifo/ad9361_fifo.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
@@ -630,8 +656,6 @@ set obj [get_filesets sim_1]
set_property -name "top" -value "tb_freq_comp" -objects $obj
set_property -name "top_auto_set" -value "0" -objects $obj
set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
set_property -name "vcs.compile.vlogan.more_options" -value "-kdb -v2005" -objects $obj
set_property -name "vcs.elaborate.vcs.more_options" -value "-debug_access+all" -objects $obj
# Set 'utils_1' fileset object
set obj [get_filesets utils_1]