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add phase compensate to duifei online acq

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josh
2023-05-16 20:44:17 +08:00
parent 986a2ea1e1
commit b2a6a62da0
249 changed files with 15824 additions and 2162 deletions
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projects/duifei/duifei_online_acq_par/rtl/phase_compensate.v
Executable
+196
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@@ -0,0 +1,196 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2023/05/16 02:00:43
// Design Name:
// Module Name: phase_compensate
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module phase_compensate(
input clk ,
input rst ,
input [11:0] vio_sin_0 ,
input [11:0] vio_sin_1 ,
input [11:0] vio_sin_2 ,
input [11:0] vio_sin_3 ,
input [11:0] vio_cos_0 ,
input [11:0] vio_cos_1 ,
input [11:0] vio_cos_2 ,
input [11:0] vio_cos_3 ,
input [11:0] din_i_0 ,
input [11:0] din_i_1 ,
input [11:0] din_i_2 ,
input [11:0] din_i_3 ,
input [11:0] din_q_0 ,
input [11:0] din_q_1 ,
input [11:0] din_q_2 ,
input [11:0] din_q_3 ,
input [4:0] vio_trunc ,
output [15:0] dout_i ,
output [15:0] dout_q ,
output trunc_overflow
);
wire [63:0] dout_comp_0;
wire [63:0] dout_comp_1;
wire [63:0] dout_comp_2;
wire [63:0] dout_comp_3;
cmpy_12_12 cmpy_12_12_0 (
.aclk(clk), // input wire aclk
.s_axis_a_tvalid(1'd1), // input wire s_axis_a_tvalid
.s_axis_a_tdata({{4{vio_sin_0[11]}},vio_sin_0[11:0],{4{vio_cos_0[11]}},vio_cos_0[11:0]}), // input wire [31 : 0] s_axis_a_tdata
.s_axis_b_tvalid(1'd1), // input wire s_axis_b_tvalid
.s_axis_b_tdata({{4{din_q_0[11]}},din_q_0[11:0],{4{din_i_0[11]}},din_i_0[11:0]}), // input wire [31 : 0] s_axis_b_tdata
.m_axis_dout_tvalid(), // output wire m_axis_dout_tvalid
.m_axis_dout_tdata(dout_comp_0) // output wire [63 : 0] m_axis_dout_tdata
);
cmpy_12_12 cmpy_12_12_1 (
.aclk(clk), // input wire aclk
.s_axis_a_tvalid(1'd1), // input wire s_axis_a_tvalid
.s_axis_a_tdata({{4{vio_sin_1[11]}},vio_sin_1[11:0],{4{vio_cos_1[11]}},vio_cos_1[11:0]}), // input wire [31 : 0] s_axis_a_tdata
.s_axis_b_tvalid(1'd1), // input wire s_axis_b_tvalid
.s_axis_b_tdata({{4{din_q_1[11]}},din_q_1[11:0],{4{din_i_1[11]}},din_i_1[11:0]}), // input wire [31 : 0] s_axis_b_tdata
.m_axis_dout_tvalid(), // output wire m_axis_dout_tvalid
.m_axis_dout_tdata(dout_comp_1) // output wire [63 : 0] m_axis_dout_tdata
);
cmpy_12_12 cmpy_12_12_2 (
.aclk(clk), // input wire aclk
.s_axis_a_tvalid(1'd1), // input wire s_axis_a_tvalid
.s_axis_a_tdata({{4{vio_sin_2[11]}},vio_sin_2[11:0],{4{vio_cos_2[11]}},vio_cos_2[11:0]}), // input wire [31 : 0] s_axis_a_tdata
.s_axis_b_tvalid(1'd1), // input wire s_axis_b_tvalid
.s_axis_b_tdata({{4{din_q_2[11]}},din_q_2[11:0],{4{din_i_2[11]}},din_i_2[11:0]}), // input wire [31 : 0] s_axis_b_tdata
.m_axis_dout_tvalid(), // output wire m_axis_dout_tvalid
.m_axis_dout_tdata(dout_comp_2) // output wire [63 : 0] m_axis_dout_tdata
);
cmpy_12_12 cmpy_12_12_3 (
.aclk(clk), // input wire aclk
.s_axis_a_tvalid(1'd1), // input wire s_axis_a_tvalid
.s_axis_a_tdata({{4{vio_sin_3[11]}},vio_sin_3[11:0],{4{vio_cos_3[11]}},vio_cos_3[11:0]}), // input wire [31 : 0] s_axis_a_tdata
.s_axis_b_tvalid(1'd1), // input wire s_axis_b_tvalid
.s_axis_b_tdata({{4{din_q_3[11]}},din_q_3[11:0],{4{din_i_3[11]}},din_i_3[11:0]}), // input wire [31 : 0] s_axis_b_tdata
.m_axis_dout_tvalid(), // output wire m_axis_dout_tvalid
.m_axis_dout_tdata(dout_comp_3) // output wire [63 : 0] m_axis_dout_tdata
);
wire [11:0] dout_trunc_0i, dout_trunc_0q;
wire [11:0] dout_trunc_1i, dout_trunc_1q;
wire [11:0] dout_trunc_2i, dout_trunc_2q;
wire [11:0] dout_trunc_3i, dout_trunc_3q;
wire [11:0] trunc_overflow_0i, trunc_overflow_0q;
wire [11:0] trunc_overflow_1i, trunc_overflow_1q;
wire [11:0] trunc_overflow_2i, trunc_overflow_2q;
wire [11:0] trunc_overflow_3i, trunc_overflow_3q;
trunc_32bit_to_12bit trunc_32bit_to_12bit_0i(
.clk(clk),
.rst(rst),
.trunc_32bit_in({{7{dout_comp_0[24]}},dout_comp_0[24:0]}),
.vio_trunc(vio_trunc),
.trunc_12bit_out(dout_trunc_0i),
.trunc_overflow(trunc_overflow_0i)
);
trunc_32bit_to_12bit trunc_32bit_to_12bit_0q(
.clk(clk),
.rst(rst),
.trunc_32bit_in({{7{dout_comp_0[56]}},dout_comp_0[56:32]}),
.vio_trunc(vio_trunc),
.trunc_12bit_out(dout_trunc_0q),
.trunc_overflow(trunc_overflow_0q)
);
trunc_32bit_to_12bit trunc_32bit_to_12bit_1i(
.clk(clk),
.rst(rst),
.trunc_32bit_in({{7{dout_comp_1[24]}},dout_comp_1[24:0]}),
.vio_trunc(vio_trunc),
.trunc_12bit_out(dout_trunc_1i),
.trunc_overflow(trunc_overflow_1i)
);
trunc_32bit_to_12bit trunc_32bit_to_12bit_1q(
.clk(clk),
.rst(rst),
.trunc_32bit_in({{7{dout_comp_1[56]}},dout_comp_1[56:32]}),
.vio_trunc(vio_trunc),
.trunc_12bit_out(dout_trunc_1q),
.trunc_overflow(trunc_overflow_1q)
);
trunc_32bit_to_12bit trunc_32bit_to_12bit_2i(
.clk(clk),
.rst(rst),
.trunc_32bit_in({{7{dout_comp_2[24]}},dout_comp_2[24:0]}),
.vio_trunc(vio_trunc),
.trunc_12bit_out(dout_trunc_2i),
.trunc_overflow(trunc_overflow_2i)
);
trunc_32bit_to_12bit trunc_32bit_to_12bit_2q(
.clk(clk),
.rst(rst),
.trunc_32bit_in({{7{dout_comp_2[56]}},dout_comp_2[56:32]}),
.vio_trunc(vio_trunc),
.trunc_12bit_out(dout_trunc_2q),
.trunc_overflow(trunc_overflow_2q)
);
trunc_32bit_to_12bit trunc_32bit_to_12bit_3i(
.clk(clk),
.rst(rst),
.trunc_32bit_in({{7{dout_comp_3[24]}},dout_comp_3[24:0]}),
.vio_trunc(vio_trunc),
.trunc_12bit_out(dout_trunc_3i),
.trunc_overflow(trunc_overflow_3i)
);
trunc_32bit_to_12bit trunc_32bit_to_12bit_3q(
.clk(clk),
.rst(rst),
.trunc_32bit_in({{7{dout_comp_3[56]}},dout_comp_3[56:32]}),
.vio_trunc(vio_trunc),
.trunc_12bit_out(dout_trunc_3q),
.trunc_overflow(trunc_overflow_3q)
);
reg [15:0] data_i_combine = 16'd0;
reg [15:0] data_q_combine = 16'd0;
always @ (posedge clk) begin
if(rst) begin
data_i_combine[15:0] <= 16'd0;
data_q_combine[15:0] <= 16'd0;
end
else begin
data_i_combine[15:0] <= {{4{dout_trunc_0i[11]}},dout_trunc_0i[11:0]} + {{4{dout_trunc_1i[11]}},dout_trunc_1i[11:0]} + {{4{dout_trunc_2i[11]}},dout_trunc_2i[11:0]} + {{4{dout_trunc_3i[11]}},dout_trunc_3i[11:0]};
data_q_combine[15:0] <= {{4{dout_trunc_0q[11]}},dout_trunc_0q[11:0]} + {{4{dout_trunc_1q[11]}},dout_trunc_1q[11:0]} + {{4{dout_trunc_2q[11]}},dout_trunc_2q[11:0]} + {{4{dout_trunc_3q[11]}},dout_trunc_3q[11:0]};
end
end
assign dout_i[15:0] = data_i_combine[15:0];
assign dout_q[15:0] = data_q_combine[15:0];
assign trunc_overflow = trunc_overflow_3q || trunc_overflow_2q || trunc_overflow_1q || trunc_overflow_0q || trunc_overflow_3i || trunc_overflow_2i || trunc_overflow_1i || trunc_overflow_0i;
endmodule
projects/duifei/duifei_online_acq_par/rtl/system_top.v
+62 -1
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@@ -676,6 +676,50 @@ ad9361_phase_cal_coarse u_ad9361_phase_cal
// <--------------------------------------------------------------------------->
// <----------------------- insert receiver logic below ----------------------->
// <--------------------------------------------------------------------------->
// weighted summation
wire [11:0] vio_sin_0;
wire [11:0] vio_sin_1;
wire [11:0] vio_sin_2;
wire [11:0] vio_sin_3;
wire [11:0] vio_cos_0;
wire [11:0] vio_cos_1;
wire [11:0] vio_cos_2;
wire [11:0] vio_cos_3;
wire [4:0] vio_trunc;
wire trunc_overflow;
wire [15:0] dout_i;
wire [15:0] dout_q;
phase_compensate u_phase_compensate
(
.clk (sys_clk ), // input clk
.rst (sys_rst ), // input rst
.vio_sin_0 (vio_sin_0 ), // input [11:0] vio_sin_0
.vio_sin_1 (vio_sin_1 ), // input [11:0] vio_sin_1
.vio_sin_2 (vio_sin_2 ), // input [11:0] vio_sin_2
.vio_sin_3 (vio_sin_3 ), // input [11:0] vio_sin_3
.vio_cos_0 (vio_cos_0 ), // input [11:0] vio_cos_0
.vio_cos_1 (vio_cos_1 ), // input [11:0] vio_cos_1
.vio_cos_2 (vio_cos_2 ), // input [11:0] vio_cos_2
.vio_cos_3 (vio_cos_3 ), // input [11:0] vio_cos_3
.din_i_0 (rx_cal_ch1_i ), // input [11:0] din_i_0
.din_i_1 (rx_cal_ch2_i ), // input [11:0] din_i_1
.din_i_2 (rx_cal_ch3_i ), // input [11:0] din_i_2
.din_i_3 (rx_cal_ch4_i ), // input [11:0] din_i_3
.din_q_0 (rx_cal_ch1_q ), // input [11:0] din_q_0
.din_q_1 (rx_cal_ch2_q ), // input [11:0] din_q_1
.din_q_2 (rx_cal_ch3_q ), // input [11:0] din_q_2
.din_q_3 (rx_cal_ch4_q ), // input [11:0] din_q_3
.vio_trunc (vio_trunc ), // input [4:0] vio_trunc
.dout_i (dout_i ), // output [15:0] dout_i
.dout_q (dout_q ), // output [15:0] dout_q
.trunc_overflow (trunc_overflow ) // output trunc_overflow
);
// online acquisition
wire freq_comp_start ;
wire freq_comp_auto_enable_vio;
wire freq_comp_start_vio;
@@ -952,7 +996,9 @@ ila_rx_data_cnt u_ila_rx
.probe6 (rx_cal_ch4_i ), // input wire [11:0] probe6
.probe7 (rx_cal_ch4_q ), // input wire [11:0] probe7
.probe8 (vio_frequency_auto[11:0] ), // input wire [11:0] probe8
.probe9 (chip_cnt ) // input wire [9:0] probe9
.probe9 (chip_cnt ), // input wire [9:0] probe9
.probe10(dout_i ), // input wire [15:0] probe10
.probe11(dout_q ) // input wire [15:0] probe11
);
ila_cal u_ila_cal
@@ -1023,4 +1069,19 @@ ila_freq_comp u_ila_freq_comp
.probe20(vio_frequency_auto[11:0] ) // input wire [11:0] probe20
);
vio_phase_comp u_vio_phase_comp
(
.clk (sys_clk ), // input wire clk
.probe_in0 (trunc_overflow ), // input wire [0 : 0] probe_in0
.probe_out0 (vio_sin_0 ), // output wire [11 : 0] probe_out0
.probe_out1 (vio_sin_1 ), // output wire [11 : 0] probe_out1
.probe_out2 (vio_sin_2 ), // output wire [11 : 0] probe_out2
.probe_out3 (vio_sin_3 ), // output wire [11 : 0] probe_out3
.probe_out4 (vio_cos_0 ), // output wire [11 : 0] probe_out4
.probe_out5 (vio_cos_1 ), // output wire [11 : 0] probe_out5
.probe_out6 (vio_cos_2 ), // output wire [11 : 0] probe_out6
.probe_out7 (vio_cos_3 ), // output wire [11 : 0] probe_out7
.probe_out8 (vio_trunc ) // output wire [4 : 0] probe_out8
);
endmodule
projects/duifei/duifei_online_acq_par/rtl/trunc_32bit_to_12bit.v
Executable
+515
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@@ -0,0 +1,515 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2023/03/01 10:44:50
// Design Name:
// Module Name: trunc_32bit_to_12bit
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module trunc_32bit_to_12bit(
input clk,
input rst,
input [31:0] trunc_32bit_in,
input [4:0] vio_trunc,
output reg [11:0] trunc_12bit_out = 12'd0,
output reg trunc_overflow = 1'd0
);
always @ (posedge clk) begin
if(rst) begin
trunc_12bit_out[11:0] <= 12'd0;
trunc_overflow <= 1'd0;
end else begin
case(vio_trunc[4:0])
5'd0:begin
if(trunc_32bit_in[31:31] == 1'd1 || trunc_32bit_in[31:31] == 1'd0) begin
if(trunc_32bit_in[31:31] == 1'd0 &&trunc_32bit_in[19] == 1'd1 && trunc_32bit_in[31:20] != 12'd2047) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[31:20] + 12'd1;
end
else begin
if(trunc_32bit_in[31:31] == 1'd1 && trunc_32bit_in[19:0] > 20'd524288) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[31:20] + 12'd1;
end
else begin
trunc_12bit_out[11:0] <= trunc_32bit_in[31:20];
end
end
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
5'd1:begin
if(trunc_32bit_in[31:30] == 2'd3 || trunc_32bit_in[31:30] == 2'd0) begin
if(trunc_32bit_in[31:30] == 2'd0 &&trunc_32bit_in[18] == 1'd1 && trunc_32bit_in[30:19] != 12'd2047) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[30:19] + 12'd1;
end
else begin
if(trunc_32bit_in[31:30] == 2'd3 && trunc_32bit_in[18:0] > 19'd262144) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[30:19] + 12'd1;
end
else begin
trunc_12bit_out[11:0] <= trunc_32bit_in[30:19];
end
end
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
5'd2:begin
if(trunc_32bit_in[31:29] == 3'd7 || trunc_32bit_in[31:29] == 3'd0) begin
if(trunc_32bit_in[31:29] == 3'd0 &&trunc_32bit_in[17] == 1'd1 && trunc_32bit_in[29:18] != 12'd2047) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[29:18] + 12'd1;
end
else begin
if(trunc_32bit_in[31:29] == 3'd7 && trunc_32bit_in[17:0] > 18'd131072) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[29:18] + 12'd1;
end
else begin
trunc_12bit_out[11:0] <= trunc_32bit_in[29:18];
end
end
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
5'd3:begin
if(trunc_32bit_in[31:28] == 4'd15 || trunc_32bit_in[31:28] == 4'd0) begin
if(trunc_32bit_in[31:28] == 4'd0 &&trunc_32bit_in[16] == 1'd1 && trunc_32bit_in[28:17] != 12'd2047) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[28:17] + 12'd1;
end
else begin
if(trunc_32bit_in[31:28] == 4'd15 && trunc_32bit_in[16:0] > 17'd65536) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[28:17] + 12'd1;
end
else begin
trunc_12bit_out[11:0] <= trunc_32bit_in[28:17];
end
end
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
5'd4:begin
if(trunc_32bit_in[31:27] == 5'd31 || trunc_32bit_in[31:27] == 5'd0) begin
if(trunc_32bit_in[31:27] == 5'd0 &&trunc_32bit_in[15] == 1'd1 && trunc_32bit_in[27:16] != 12'd2047) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[27:16] + 12'd1;
end
else begin
if(trunc_32bit_in[31:27] == 5'd31 && trunc_32bit_in[15:0] > 16'd32768) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[27:16] + 12'd1;
end
else begin
trunc_12bit_out[11:0] <= trunc_32bit_in[27:16];
end
end
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
5'd5:begin
if(trunc_32bit_in[31:26] == 6'd63 || trunc_32bit_in[31:26] == 6'd0) begin
if(trunc_32bit_in[31:26] == 6'd0 &&trunc_32bit_in[14] == 1'd1 && trunc_32bit_in[26:15] != 12'd2047) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[26:15] + 12'd1;
end
else begin
if(trunc_32bit_in[31:26] == 6'd63 && trunc_32bit_in[14:0] > 15'd16384) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[26:15] + 12'd1;
end
else begin
trunc_12bit_out[11:0] <= trunc_32bit_in[26:15];
end
end
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
5'd6:begin
if(trunc_32bit_in[31:25] == 7'd127 || trunc_32bit_in[31:25] == 7'd0) begin
if(trunc_32bit_in[31:25] == 7'd0 &&trunc_32bit_in[13] == 1'd1 && trunc_32bit_in[25:14] != 12'd2047) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[25:14] + 12'd1;
end
else begin
if(trunc_32bit_in[31:25] == 7'd127 && trunc_32bit_in[13:0] > 14'd8192) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[25:14] + 12'd1;
end
else begin
trunc_12bit_out[11:0] <= trunc_32bit_in[25:14];
end
end
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
5'd7:begin
if(trunc_32bit_in[31:24] == 8'd255 || trunc_32bit_in[31:24] == 8'd0) begin
if(trunc_32bit_in[31:24] == 8'd0 &&trunc_32bit_in[12] == 1'd1 && trunc_32bit_in[24:13] != 12'd2047) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[24:13] + 12'd1;
end
else begin
if(trunc_32bit_in[31:24] == 8'd255 && trunc_32bit_in[12:0] > 13'd4096) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[24:13] + 12'd1;
end
else begin
trunc_12bit_out[11:0] <= trunc_32bit_in[24:13];
end
end
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
5'd8:begin
if(trunc_32bit_in[31:23] == 9'd511 || trunc_32bit_in[31:23] == 9'd0) begin
if(trunc_32bit_in[31:23] == 9'd0 &&trunc_32bit_in[11] == 1'd1 && trunc_32bit_in[23:12] != 12'd2047) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[23:12] + 12'd1;
end
else begin
if(trunc_32bit_in[31:23] == 9'd511 && trunc_32bit_in[11:0] > 12'd2048) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[23:12] + 12'd1;
end
else begin
trunc_12bit_out[11:0] <= trunc_32bit_in[23:12];
end
end
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
5'd9:begin
if(trunc_32bit_in[31:22] == 10'd1023 || trunc_32bit_in[31:22] == 10'd0) begin
if(trunc_32bit_in[31:22] == 10'd0 &&trunc_32bit_in[10] == 1'd1 && trunc_32bit_in[22:11] != 12'd2047) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[22:11] + 12'd1;
end
else begin
if(trunc_32bit_in[31:22] == 10'd1023 && trunc_32bit_in[10:0] > 11'd1024) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[22:11] + 12'd1;
end
else begin
trunc_12bit_out[11:0] <= trunc_32bit_in[22:11];
end
end
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
5'd10:begin
if(trunc_32bit_in[31:21] == 11'd2047 || trunc_32bit_in[31:21] == 11'd0) begin
if(trunc_32bit_in[31:21] == 11'd0 &&trunc_32bit_in[9] == 1'd1 && trunc_32bit_in[21:10] != 12'd2047) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[21:10] + 12'd1;
end
else begin
if(trunc_32bit_in[31:21] == 11'd2047 && trunc_32bit_in[9:0] > 10'd512) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[21:10] + 12'd1;
end
else begin
trunc_12bit_out[11:0] <= trunc_32bit_in[21:10];
end
end
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
5'd11:begin
if(trunc_32bit_in[31:20] == 12'd4095 || trunc_32bit_in[31:20] == 12'd0) begin
if(trunc_32bit_in[31:20] == 12'd0 &&trunc_32bit_in[8] == 1'd1 && trunc_32bit_in[20:9] != 12'd2047) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[20:9] + 12'd1;
end
else begin
if(trunc_32bit_in[31:20] == 12'd4095 && trunc_32bit_in[8:0] > 9'd256) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[20:9] + 12'd1;
end
else begin
trunc_12bit_out[11:0] <= trunc_32bit_in[20:9];
end
end
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
5'd12:begin
if(trunc_32bit_in[31:19] == 13'd8191 || trunc_32bit_in[31:19] == 13'd0) begin
if(trunc_32bit_in[31:19] == 13'd0 &&trunc_32bit_in[7] == 1'd1 && trunc_32bit_in[19:8] != 12'd2047) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[19:8] + 12'd1;
end
else begin
if(trunc_32bit_in[31:19] == 13'd8191 && trunc_32bit_in[7:0] > 8'd128) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[19:8] + 12'd1;
end
else begin
trunc_12bit_out[11:0] <= trunc_32bit_in[19:8];
end
end
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
5'd13:begin
if(trunc_32bit_in[31:18] == 14'd16383 || trunc_32bit_in[31:18] == 14'd0) begin
if(trunc_32bit_in[31:18] == 14'd0 &&trunc_32bit_in[6] == 1'd1 && trunc_32bit_in[18:7] != 12'd2047) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[18:7] + 12'd1;
end
else begin
if(trunc_32bit_in[31:18] == 14'd16383 && trunc_32bit_in[6:0] > 7'd64) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[18:7] + 12'd1;
end
else begin
trunc_12bit_out[11:0] <= trunc_32bit_in[18:7];
end
end
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
5'd14:begin
if(trunc_32bit_in[31:17] == 15'd32767 || trunc_32bit_in[31:17] == 15'd0) begin
if(trunc_32bit_in[31:17] == 15'd0 &&trunc_32bit_in[5] == 1'd1 && trunc_32bit_in[17:6] != 12'd2047) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[17:6] + 12'd1;
end
else begin
if(trunc_32bit_in[31:17] == 15'd32767 && trunc_32bit_in[5:0] > 6'd32) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[17:6] + 12'd1;
end
else begin
trunc_12bit_out[11:0] <= trunc_32bit_in[17:6];
end
end
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
5'd15:begin
if(trunc_32bit_in[31:16] == 16'd65535 || trunc_32bit_in[31:16] == 16'd0) begin
if(trunc_32bit_in[31:16] == 16'd0 &&trunc_32bit_in[4] == 1'd1 && trunc_32bit_in[16:5] != 12'd2047) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[16:5] + 12'd1;
end
else begin
if(trunc_32bit_in[31:16] == 16'd65535 && trunc_32bit_in[4:0] > 5'd16) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[16:5] + 12'd1;
end
else begin
trunc_12bit_out[11:0] <= trunc_32bit_in[16:5];
end
end
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
5'd16:begin
if(trunc_32bit_in[31:15] == 17'd131071 || trunc_32bit_in[31:15] == 17'd0) begin
if(trunc_32bit_in[31:15] == 17'd0 &&trunc_32bit_in[3] == 1'd1 && trunc_32bit_in[15:4] != 12'd2047) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[15:4] + 12'd1;
end
else begin
if(trunc_32bit_in[31:15] == 17'd131071 && trunc_32bit_in[3:0] > 4'd8) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[15:4] + 12'd1;
end
else begin
trunc_12bit_out[11:0] <= trunc_32bit_in[15:4];
end
end
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
5'd17:begin
if(trunc_32bit_in[31:14] == 18'd262143 || trunc_32bit_in[31:14] == 18'd0) begin
if(trunc_32bit_in[31:14] == 18'd0 &&trunc_32bit_in[2] == 1'd1 && trunc_32bit_in[14:3] != 12'd2047) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[14:3] + 12'd1;
end
else begin
if(trunc_32bit_in[31:14] == 18'd262143 && trunc_32bit_in[2:0] > 3'd4) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[14:3] + 12'd1;
end
else begin
trunc_12bit_out[11:0] <= trunc_32bit_in[14:3];
end
end
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
5'd18:begin
if(trunc_32bit_in[31:13] == 19'd524287 || trunc_32bit_in[31:13] == 19'd0) begin
if(trunc_32bit_in[31:13] == 19'd0 &&trunc_32bit_in[1] == 1'd1 && trunc_32bit_in[13:2] != 12'd2047) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[13:2] + 12'd1;
end
else begin
if(trunc_32bit_in[31:13] == 19'd524287 && trunc_32bit_in[1:0] > 2'd2) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[13:2] + 12'd1;
end
else begin
trunc_12bit_out[11:0] <= trunc_32bit_in[13:2];
end
end
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
5'd19:begin
if(trunc_32bit_in[31:12] == 20'd1048575 || trunc_32bit_in[31:12] == 20'd0) begin
if(trunc_32bit_in[31:12] == 20'd0 &&trunc_32bit_in[0] == 1'd1 && trunc_32bit_in[12:1] != 12'd2047) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[12:1] + 12'd1;
end
else begin
if(trunc_32bit_in[31:12] == 20'd1048575 && trunc_32bit_in[0:0] > 1'd1) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[12:1] + 12'd1;
end
else begin
trunc_12bit_out[11:0] <= trunc_32bit_in[12:1];
end
end
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
default:begin
if(trunc_32bit_in[31:11] == 21'd2097151 || trunc_32bit_in[31:11] == 21'd0) begin
trunc_12bit_out[11:0] <= trunc_32bit_in[11:0];
trunc_overflow <= 1'd0;
end else begin
if(trunc_32bit_in[31] == 1'd1) begin
trunc_12bit_out[11:0] <= -12'd2048;
end else begin
trunc_12bit_out[11:0] <= 12'd2047;
end
trunc_overflow <= 1'd1;
end
end
endcase
end
end
endmodule