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change online acq pn code length, change 814 online acq to the same

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修改了在线捕获程序的PN码长和频偏搜索步进,修改了地检发送程序的PN码长,使用对飞相控阵进行了测试,得到正确结果;将程序移植到814平台,同样能够正常工作;对地检程序(20230512),对飞程序(20230512)和814程序(20230415)进行归档
This commit is contained in:
josh
2023-05-14 12:51:10 +08:00
parent 0f97436c8f
commit c32d684223
1071 changed files with 222689 additions and 31208 deletions
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projects/dl814_k7/dl814_k7_online_acq/rtl/freq_comp.v
+399 -385
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File diff suppressed because it is too large Load Diff
projects/dl814_k7/dl814_k7_online_acq/rtl/rf_auto_switch_freq.v
+109 -39
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@@ -1,44 +1,49 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Company:
// Engineer:
//
// Create Date: 2023/05/06 15:37:29
// Design Name:
// Design Name:
// Module Name: rf_auto_switch_freq
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
//////////////////////////////////////////////////////////////////////////////////
module rf_auto_switch_freq(
input clk ,
input rst ,
input clk ,
input rst ,
// vio control
input start , // rise-edge active, if start, change freq word to the first
input rf_ctrl_mode , // 1 : auto switch, 0 : manual switch
input switch_next_freq , // rise-edge active
input switch_last_freq , // rise-edge active
input [15:0] cnt_valid_to_switch , // clock number from valid to switch
input start , // rise-edge active, if start, change freq word to the first
input rf_ctrl_mode , // 1 : auto switch, 0 : manual switch
input switch_next_freq , // rise-edge active
input switch_last_freq , // rise-edge active
input [31:0] cnt_valid_to_switch , // clock number from valid to switch
input [31:0] cnt_switch_to_freq_start ,
input [31:0] cnt_sync_in ,
input [31:0] cnt_sync_in_high ,
// input
input [15:0] freq_hop_words_vio ,
input hop_words_valid_vio ,
input freq_hop_switch_vio ,
// output
output reg [15:0] freq_hop_words_auto = 11'd0 ,
output reg hop_words_valid_auto = 1'd0 ,
output reg freq_hop_switch_auto = 1'd0
input sync_in , // rise-edge or down-edge active
input [15:0] freq_hop_words_vio ,
input hop_words_valid_vio ,
input freq_hop_switch_vio ,
// output
output reg [15:0] freq_hop_words_auto = 11'd0,
output reg hop_words_valid_auto = 1'd0 ,
output reg freq_hop_switch_auto = 1'd0 ,
output reg freq_comp_start = 1'b0 // rise-edge or down-edge active
);
//************************* rise-edge detect ***********************************
reg start_d1 = 1'b0;
reg start_d2 = 1'b0;
@@ -73,6 +78,46 @@ always @ (posedge clk)
switch_last_freq_pulse[0] <= switch_last_freq_d1 & ~switch_last_freq_d2;
switch_last_freq_pulse[9:1] <= switch_last_freq_pulse[8:0];
end
//*********************** sync signal detect ***********************************
reg sync_in_reg = 1'b0;
reg [31:0] sync_in_cnt = 32'd0;
reg [31:0] sync_in_high_cnt = 32'd0;
reg sync_in_valid = 1'b0;
reg sync_in_valid_d1 = 1'b0;
always @ (posedge clk)
if(rst | start_pulse) begin
sync_in_cnt <= 32'd0;
sync_in_high_cnt <= 32'd0;
end else if(sync_in_cnt == cnt_sync_in) begin
sync_in_cnt <= 32'd0;
sync_in_high_cnt <= 32'd0;
end else if(sync_in == 1'b1) begin
sync_in_cnt <= sync_in_cnt + 1'b1;
sync_in_high_cnt <= sync_in_high_cnt + 1'b1;
end else begin
sync_in_cnt <= sync_in_cnt + 1'b1;
end
always @ (posedge clk)
if(rst | start_pulse)
sync_in_reg <= 1'b0;
else if(sync_in_cnt == cnt_sync_in && sync_in_high_cnt > cnt_sync_in_high)
sync_in_reg <= 1'b1;
else if(sync_in_cnt == cnt_sync_in)
sync_in_reg <= 1'b0;
always @ (posedge clk)
if(rst | start_pulse)
sync_in_valid <= 1'b0;
else if(sync_in_reg != sync_in_valid)
sync_in_valid <= ~sync_in_valid;
always @ (posedge clk)
if(rst | start_pulse)
sync_in_valid_d1 <= 1'b0;
else
sync_in_valid_d1 <= sync_in_valid;
//******************** local freq word control *********************************
reg [15:0] local_freq_word = 16'd0;
@@ -89,35 +134,40 @@ rom_freq_word rom_freq_word_inst(
always @ (posedge clk)
if(rst | start_pulse)
freq_word_cnt <= 8'd0;
freq_word_cnt <= 8'd80;
else if(freq_word_cnt == 8'd80 && switch_next_freq_pulse[0])
freq_word_cnt <= 8'd0;
else if(freq_word_cnt == 8'd80 && sync_in_valid != sync_in_valid_d1)
freq_word_cnt <= 8'd0;
else if(freq_word_cnt == 8'd0 && switch_last_freq_pulse[0])
freq_word_cnt <= 8'd80;
else if(switch_next_freq_pulse[0])
freq_word_cnt <= freq_word_cnt + 1'b1;
else if(sync_in_valid != sync_in_valid_d1)
freq_word_cnt <= freq_word_cnt + 1'b1;
else if(switch_last_freq_pulse[0])
freq_word_cnt <= freq_word_cnt - 1'b1;
else
freq_word_cnt <= freq_word_cnt;
reg [31:0] freq_word_valid_cnt = 32'd0;
always @ (posedge clk)
if(rst | start_pulse)
local_freq_word_valid <= 1'b0;
else if(switch_next_freq_pulse[4] | switch_last_freq_pulse[4])
else if(switch_next_freq_pulse[4] | switch_last_freq_pulse[4] | sync_in_valid != sync_in_valid_d1 | freq_word_valid_cnt == cnt_valid_to_switch<<1)
local_freq_word_valid <= 1'b1;
else
else
local_freq_word_valid <= 1'b0;
reg [15:0] freq_word_valid_cnt = 16'd0;
always @ (posedge clk)
if(rst | start_pulse)
freq_word_valid_cnt <= 16'd0;
else if(freq_word_valid_cnt == cnt_valid_to_switch)
freq_word_valid_cnt <= 16'd0;
freq_word_valid_cnt <= 32'd0;
else if(freq_word_valid_cnt == cnt_valid_to_switch<<2)
freq_word_valid_cnt <= 32'd0;
else if(local_freq_word_valid)
freq_word_valid_cnt <= freq_word_valid_cnt + 1'b1;
else if(freq_word_valid_cnt != 16'd0)
else if(freq_word_valid_cnt != 32'd0)
freq_word_valid_cnt <= freq_word_valid_cnt + 1'b1;
else
freq_word_valid_cnt <= freq_word_valid_cnt;
@@ -125,9 +175,9 @@ always @ (posedge clk)
always @ (posedge clk)
if(rst | start_pulse)
local_freq_word_switch <= 1'b0;
else if(freq_word_valid_cnt == cnt_valid_to_switch)
else if(freq_word_valid_cnt == cnt_valid_to_switch | freq_word_valid_cnt == (cnt_valid_to_switch+cnt_valid_to_switch<<1))
local_freq_word_switch <= ~local_freq_word_switch;
else
else
local_freq_word_switch <= local_freq_word_switch;
always @ (posedge clk)
@@ -154,7 +204,7 @@ always @ (posedge clk)
hop_words_valid_auto <= local_freq_word_valid;
else
hop_words_valid_auto <= hop_words_valid_vio;
// freq_hop_switch_auto
always @ (posedge clk)
if(rst | start_pulse)
@@ -163,5 +213,25 @@ always @ (posedge clk)
freq_hop_switch_auto <= local_freq_word_switch;
else
freq_hop_switch_auto <= freq_hop_switch_vio;
// freq_comp_start
reg [31:0] freq_comp_start_cnt = 32'd0;
always @ (posedge clk)
if(rst | start_pulse)
freq_comp_start_cnt <= 32'd0;
else if(freq_comp_start_cnt == cnt_switch_to_freq_start)
freq_comp_start_cnt <= 32'd0;
else if(freq_word_valid_cnt == cnt_valid_to_switch<<2)
freq_comp_start_cnt <= freq_comp_start_cnt + 1'b1;
else if(freq_comp_start_cnt != 32'd0)
freq_comp_start_cnt <= freq_comp_start_cnt + 1'b1;
else
freq_comp_start_cnt <= freq_comp_start_cnt;
always @ (posedge clk)
if(rst | start_pulse)
freq_comp_start <= 1'b0;
else if(freq_comp_start_cnt == cnt_switch_to_freq_start)
freq_comp_start <= ~freq_comp_start;
endmodule
projects/dl814_k7/dl814_k7_online_acq/rtl/rx_dmf.v
+78 -39
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@@ -28,16 +28,16 @@
module rx_dmf
#(
// length of pseudorandom bit sequence, need to be a power of 2
parameter PRBS_LEN = 128,
parameter PRBS_LEN = 1024,
// interpolation of input signal, need to be a power of 2
parameter INTERP_RATE = 8,
parameter INTERP_RATE = 32,
// signal processing interpolation, need to be a power of 2
parameter PROCESS_INTERP = 4,
parameter PROCESS_INTERP = 2,
// possible position of pn code
parameter PRBS_POS = 2*PRBS_LEN*PROCESS_INTERP,
parameter DATA_I_WIDTH = 12,
parameter DATA_O_WIDTH = 18
parameter PRBS_POS = PRBS_LEN*PROCESS_INTERP,
parameter MAX_DMF_NUM = 64,
parameter DATA_I_WIDTH = 12,
parameter DATA_O_WIDTH = 18
)
(
input clk ,
@@ -50,7 +50,11 @@ module rx_dmf
input [DATA_I_WIDTH-1 : 0] din_real ,
input [DATA_I_WIDTH-1 : 0] din_imag ,
input [$clog2(MAX_DMF_NUM+1)-1 : 0] dmf_num ,
input dmf_continuous ,
output peak_valid ,
output last_peak_valid ,
output [DATA_O_WIDTH-1 : 0] peak_value_abs ,
output [DATA_O_WIDTH-1 : 0] peak_value_i ,
output [DATA_O_WIDTH-1 : 0] peak_value_q ,
@@ -62,7 +66,7 @@ localparam APPROX_ABS_WIDTH = 29;
localparam ABS_WIDTH = 18;
localparam DMF_I_WIDTH = 12;
localparam DMF_O_WIDTH = DMF_I_WIDTH+$clog2(PRBS_POS/2);
localparam DMF_O_WIDTH = DMF_I_WIDTH+$clog2(PRBS_POS);
localparam AXIS_DMF_I_WIDTH = 8*((DMF_I_WIDTH-1)/8+1);
localparam AXIS_DMF_O_WIDTH = 8*((DMF_O_WIDTH-1)/8+1);
@@ -76,6 +80,9 @@ integer i;
reg dmf_busy_buf = 'b0;
reg dmf_start_d1 = 'b0;
reg dmf_start_d2 = 'b0;
reg [$clog2(MAX_DMF_NUM)-1 : 0] cnt_dmf_num = 'b0;
reg moduli_max_valid = 'b0;
assign dmf_busy = dmf_busy_buf;
@@ -84,15 +91,27 @@ always @(posedge clk) begin
dmf_start_d2 <= dmf_start_d1;
end
always @(posedge clk) begin
if (rst) begin
cnt_dmf_num <= 'b0;
end
else if (dmf_busy) begin
cnt_dmf_num <= (moduli_max_valid) ? cnt_dmf_num + 1'b1 : cnt_dmf_num;
end
else begin
cnt_dmf_num <= 'b0;
end
end
always @(posedge clk) begin
if (rst) begin
dmf_busy_buf <= 'b0;
end
else if (peak_valid == 1'b1) begin
else if (cnt_dmf_num == dmf_num+1 && ~dmf_continuous) begin
// clear when output is valid
dmf_busy_buf <= 'b0;
end
else if (din_valid && (dmf_start_d2 != dmf_start_d1)) begin
else if (din_valid && (dmf_start_d2 != dmf_start_d1) && (dmf_num != 'b0)) begin
// set when either edge is detected
dmf_busy_buf <= 1'b1;
end
@@ -182,7 +201,7 @@ assign dmf_axis_o_imag = m_axis_data_ttdata_imag;
assign dmf_o_valid = m_axis_data_tvalid_real;
// fir ip core instantiation
fir_prbs7_invert_rep4 u_dmf_real
fir_prbs10_invert_rep2 u_dmf_real
(
.aclk (clk ), // input wire aclk
.aresetn (dmf_busy ), // input aresetn
@@ -193,7 +212,7 @@ fir_prbs7_invert_rep4 u_dmf_real
.m_axis_data_tdata (m_axis_data_ttdata_real) // output wire [23 : 0] m_axis_data_tdata
);
fir_prbs7_invert_rep4 u_dmf_imag
fir_prbs10_invert_rep2 u_dmf_imag
(
.aclk (clk ), // input wire aclk
.aresetn (dmf_busy ), // input aresetn
@@ -208,10 +227,9 @@ fir_prbs7_invert_rep4 u_dmf_imag
///////////////////////////////// Chip Counter /////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
localparam PEAK_ABS_DELAY = 6; // 5 for multiplier, 1 for adder
localparam CHIP_CNT_DELAY = PEAK_ABS_DELAY + 2; // 1 for peak record, 1 for register output
reg [$clog2(PRBS_POS)-1 : 0] cnt_chip = 'b0;
reg [$clog2(PRBS_POS)-1 : 0] cnt_chip_delay [0 : CHIP_CNT_DELAY-1];
reg [$clog2(PRBS_POS)-1 : 0] cnt_chip_delay [0 : PEAK_ABS_DELAY-1];
always @(posedge clk) begin
if (rst) begin
@@ -227,7 +245,7 @@ end
always @(posedge clk) begin
for (i = 1; i < CHIP_CNT_DELAY; i = i + 1) begin
for (i = 1; i < PEAK_ABS_DELAY; i = i + 1) begin
cnt_chip_delay[i] <= cnt_chip_delay[i-1];
end
@@ -354,7 +372,6 @@ mult_18x18 u_mult_imag
// );
// peak record
reg moduli_max_valid = 'b0;
reg [DATA_O_WIDTH-1 : 0] moduli_max_abs = 'b0;
reg [DATA_O_WIDTH-1 : 0] moduli_max_real = 'b0;
reg [DATA_O_WIDTH-1 : 0] moduli_max_imag = 'b0;
@@ -369,15 +386,31 @@ always @(posedge clk) begin
moduli_max_index <= 'b0;
end
else if (dmf_busy) begin
if (moduli_abs_valid && (cnt_chip_delay[PEAK_ABS_DELAY-1][$clog2(PRBS_POS)-1] == 1)) begin
moduli_max_valid <= 1'b1;
moduli_max_abs <= (moduli_abs > moduli_max_abs) ? moduli_abs : moduli_max_abs ;
moduli_max_real <= (moduli_abs > moduli_max_abs) ? moduli_real_delay[PEAK_ABS_DELAY-1] : moduli_max_real ;
moduli_max_imag <= (moduli_abs > moduli_max_abs) ? moduli_imag_delay[PEAK_ABS_DELAY-1] : moduli_max_imag ;
moduli_max_index <= (moduli_abs > moduli_max_abs) ? cnt_chip_delay[CHIP_CNT_DELAY-2] : moduli_max_index;
if (moduli_abs_valid) begin
if ((cnt_chip_delay[PEAK_ABS_DELAY-1] == 0) || (moduli_abs > moduli_max_abs)) begin
// reset when chip counter reaches zero or record peak
moduli_max_abs <= moduli_abs ;
moduli_max_real <= moduli_real_delay[PEAK_ABS_DELAY-1];
moduli_max_imag <= moduli_imag_delay[PEAK_ABS_DELAY-1];
moduli_max_index <= cnt_chip_delay[PEAK_ABS_DELAY-1] ;
end
else begin
moduli_max_abs <= moduli_max_abs;
moduli_max_real <= moduli_max_real;
moduli_max_imag <= moduli_max_imag;
moduli_max_index <= moduli_max_index;
end
if (cnt_chip_delay[PEAK_ABS_DELAY-1] == PRBS_POS-1) begin
// peak record valid when chip counter reaches maximum value
moduli_max_valid <= 1'b1;
end
else begin
moduli_max_valid <= 'b0;
end
end
else begin
moduli_max_valid <= 1'b0;
moduli_max_valid <= 'b0;
moduli_max_abs <= moduli_max_abs;
moduli_max_real <= moduli_max_real;
moduli_max_imag <= moduli_max_imag;
@@ -395,38 +428,44 @@ end
// register output
reg peak_valid_buf = 1'b0;
reg last_peak_valid_buf = 1'b0;
reg [DATA_O_WIDTH-1 : 0] peak_value_abs_buf = 'b0;
reg [DATA_O_WIDTH-1 : 0] peak_value_i_buf = 'b0;
reg [DATA_O_WIDTH-1 : 0] peak_value_q_buf = 'b0;
reg [$clog2(PRBS_POS)-1 : 0] peak_index_buf = 'b0;
assign peak_valid = peak_valid_buf ;
assign peak_value_abs = peak_value_abs_buf;
assign peak_value_i = peak_value_i_buf ;
assign peak_value_q = peak_value_q_buf ;
assign peak_index = peak_index_buf ;
assign peak_valid = peak_valid_buf ;
assign last_peak_valid = last_peak_valid_buf;
assign peak_value_abs = peak_value_abs_buf ;
assign peak_value_i = peak_value_i_buf ;
assign peak_value_q = peak_value_q_buf ;
assign peak_index = peak_index_buf ;
always @(posedge clk) begin
if (rst) begin
peak_valid_buf <= 'b0;
peak_value_abs_buf <= 'b0;
peak_value_i_buf <= 'b0;
peak_value_q_buf <= 'b0;
peak_index_buf <= 'b0;
peak_valid_buf <= 'b0;
last_peak_valid_buf <= 'b0;
peak_value_abs_buf <= 'b0;
peak_value_i_buf <= 'b0;
peak_value_q_buf <= 'b0;
peak_index_buf <= 'b0;
end
else if (moduli_max_valid && (cnt_chip_delay[CHIP_CNT_DELAY-1] == PRBS_POS-1)) begin
else if (moduli_max_valid && (cnt_dmf_num != 'b0)) begin
peak_valid_buf <= 1'b1;
peak_value_abs_buf <= moduli_max_abs ;
peak_value_i_buf <= moduli_max_real ;
peak_value_q_buf <= moduli_max_imag ;
peak_index_buf <= moduli_max_index;
last_peak_valid_buf<= ((cnt_dmf_num == dmf_num) && ~dmf_continuous) ? 1'b1 : 'b0;
end
else begin
peak_valid_buf <= 1'b0;
peak_value_abs_buf <= peak_value_abs_buf;
peak_value_i_buf <= peak_value_i_buf ;
peak_value_q_buf <= peak_value_q_buf ;
peak_index_buf <= peak_index_buf ;
peak_valid_buf <= 1'b0;
last_peak_valid_buf <= 1'b0;
peak_value_abs_buf <= peak_value_abs_buf;
peak_value_i_buf <= peak_value_i_buf ;
peak_value_q_buf <= peak_value_q_buf ;
peak_index_buf <= peak_index_buf ;
end
end
projects/dl814_k7/dl814_k7_online_acq/rtl/system_top.v
+180 -147
View File
@@ -181,7 +181,7 @@ module system_top
input uart3_rxd ,
inout debug_io_1 ,
inout debug_io_2 ,
inout debug_io_3 ,
input debug_io_3 ,
inout debug_io_4 ,
inout debug_io_5 ,
inout debug_io_6 ,
@@ -449,31 +449,40 @@ wire rf_auto_start_vio ;
wire rf_ctrl_mode_vio ;
wire switch_next_freq_vio;
wire switch_last_freq_vio;
wire [15:0] cnt_valid_to_switch_vio;
wire [31:0] cnt_valid_to_switch_vio;
wire [31:0] cnt_switch_to_freq_start_vio;
wire [31:0] cnt_sync_in_vio;
wire [31:0] cnt_sync_in_high_vio;
wire vio_switch;
wire vio_switch_auto;
wire [15:0] vio_frequency;
wire [15:0] vio_frequency_auto;
(*dont_touch = "true"*) wire vio_switch;
(*dont_touch = "true"*) wire vio_switch_auto;
(*dont_touch = "true"*) wire [15:0] vio_frequency;
(*dont_touch = "true"*) wire [15:0] vio_frequency_auto;
wire hop_words_valid_auto;
wire freq_comp_start_auto ;
rf_auto_switch_freq u_rf_auto_switch_freq(
.clk (clk_48m ),
.rst (sys_rst ),
.clk (clk_48m ),
.rst (sys_rst ),
// vio control
.start (rf_auto_start_vio ), // rise-edge active, if start, change freq word to the first
.rf_ctrl_mode (rf_ctrl_mode_vio ), // 1 : auto switch, 0 : manual switch
.switch_next_freq (switch_next_freq_vio ), // rise-edge active
.switch_last_freq (switch_last_freq_vio ), // rise-edge active
.cnt_valid_to_switch (cnt_valid_to_switch_vio ),
.start (rf_auto_start_vio ), // rise-edge active, if start, change freq word to the first
.rf_ctrl_mode (rf_ctrl_mode_vio ), // 1 : auto switch, 0 : manual switch
.switch_next_freq (switch_next_freq_vio ), // rise-edge active
.switch_last_freq (switch_last_freq_vio ), // rise-edge active
.cnt_valid_to_switch (cnt_valid_to_switch_vio ),
.cnt_switch_to_freq_start (cnt_switch_to_freq_start_vio ),
.cnt_sync_in (cnt_sync_in_vio[31:0] ),
.cnt_sync_in_high (cnt_sync_in_high_vio[31:0] ),
// input
.freq_hop_words_vio (vio_frequency[15:0] ),
.hop_words_valid_vio (1'b0 ),
.freq_hop_switch_vio (vio_switch ),
.sync_in (debug_io_3 ),
.freq_hop_words_vio (vio_frequency[15:0] ),
.hop_words_valid_vio (1'b0 ),
.freq_hop_switch_vio (vio_switch ),
// output
.freq_hop_words_auto (vio_frequency_auto[15:0] ),
.hop_words_valid_auto (hop_words_valid_auto ),
.freq_hop_switch_auto (vio_switch_auto )
.freq_hop_words_auto (vio_frequency_auto[15:0] ),
.hop_words_valid_auto (hop_words_valid_auto ),
.freq_hop_switch_auto (vio_switch_auto ),
.freq_comp_start (freq_comp_start_auto )
);
ant_rf_ctrl u_ant_rf_ctrl
@@ -576,10 +585,10 @@ tx_pre_process #(
.clk (sys_clk ),
.rst (sys_rst ),
// input data
.tx_data_ch1_i (tx_ch1_i ),
.tx_data_ch1_q (tx_ch1_q ),
.tx_data_ch2_i (tx_ch2_i ),
.tx_data_ch2_q (tx_ch2_q ),
.tx_data_ch1_i (tx_data_i ),
.tx_data_ch1_q (tx_data_q ),
.tx_data_ch2_i (tx_data_i ),
.tx_data_ch2_q (tx_data_q ),
// ad9361 calibration interface
.ad9361_tx_switch (ad9361_tx_switch ),
//
@@ -600,7 +609,11 @@ wire [31:0] freq_set ;
wire [ 1:0] iq_sel ;
wire [ 3:0] bb_rshift ;
tx_qpsk u_tx_qpsk
tx_qpsk #(
.BIT_DATA (1024'b0000000100100010000011001001101000010010101000011110101110101101101100000000110000011011001100001010110101110001101111110001000111100111101101101000000010100001011010101000111110111100100101100000100110010001010001101101110000001111000111011111110010000110001011011101000011010101100111100101101100100000100010010011000000101100010100111011001110001011111101010001011101101011000011001101101010000011101001111010011010100100111000001111100111001101111010001010101101111100001001110100011101011111011010010000100001010010101100011100111111101100001000110100111001001111000011011101100011000111101111101001001010000001101000110010111010010110100010001011001101001010010001100001110110111100000101110010101110011101110111001100111010101110111101100101000100110110001000011100101111100101001100110010101010011111100110001101011110011010110100110001001011100001011110101010101111111101000001010100101111000101011110111010100110111001000111000111111111100000001110000111111011100010011111000110011111010110010110010010010000000001),
.BIT_DATA_LEN (1024),
.CLK_FREQ (48000000)
) u_tx_qpsk
(
.clk (sys_clk ), // input clk
.rst (sys_rst ), // input rst
@@ -627,11 +640,6 @@ wire [11:0] rx_cal_ch2_i, rx_cal_ch2_q;
wire [11:0] rx_cal_ch3_i, rx_cal_ch3_q;
wire [11:0] rx_cal_ch4_i, rx_cal_ch4_q;
wire [15:0] phase_ch1, phase_ch2, phase_ch3, phase_ch4;
wire rx_data_valid;
wire [29:0] rx_data_i, rx_data_q;
ad9361_rx_map_cmos_dual u_ad9361_1_rx_map
(
.clk_2x_in (ad9361_1_clk_2x ), // input clk_2x_in
@@ -705,8 +713,11 @@ ad9361_phase_cal_coarse u_ad9361_phase_cal
// <----------------------- insert receiver logic below ----------------------->
// <--------------------------------------------------------------------------->
wire freq_comp_start ;
wire freq_comp_auto_enable_vio;
wire freq_comp_start_vio;
wire freq_comp_busy ;
wire [7:0] dmf_num_per_ch ;
wire dmf_continuous ;
wire [31:0] freq_manual ;
wire freq_manual_en ;
wire [31:0] freq_target ;
@@ -716,28 +727,31 @@ wire ch_peak_valid ;
wire [17:0] ch1_peak_value_abs ;
wire [17:0] ch1_peak_value_i ;
wire [17:0] ch1_peak_value_q ;
wire [ 9:0] ch1_peak_index ;
wire [10:0] ch1_peak_index ;
wire [17:0] ch2_peak_value_abs ;
wire [17:0] ch2_peak_value_i ;
wire [17:0] ch2_peak_value_q ;
wire [ 9:0] ch2_peak_index ;
wire [10:0] ch2_peak_index ;
wire [17:0] ch3_peak_value_abs ;
wire [17:0] ch3_peak_value_i ;
wire [17:0] ch3_peak_value_q ;
wire [ 9:0] ch3_peak_index ;
wire [10:0] ch3_peak_index ;
wire [17:0] ch4_peak_value_abs ;
wire [17:0] ch4_peak_value_i ;
wire [17:0] ch4_peak_value_q ;
wire [ 9:0] ch4_peak_index ;
wire [10:0] ch4_peak_index ;
assign freq_comp_start = (freq_comp_auto_enable_vio == 1'b1) ? freq_comp_start_auto : freq_comp_start_vio;
freq_comp #(
.FREQ_WORD_LOWER (-4194304 ),
.FREQ_WORD_UPPER (4194303 ),
.FREQ_WORD_LOWER (-1048576 ),
.FREQ_WORD_UPPER (1048575 ),
.FREQ_WORD_STEP (1024 )
) u_freq_comp
(
// clock & reset
.clk (sys_clk ), // input clk
.clk_4x (sys_clk_4x ), // input clk_4x
.rst (sys_rst ), // input rst
// input data
@@ -756,6 +770,7 @@ freq_comp #(
// configuration
.dmf_num_per_ch (dmf_num_per_ch ), // input [$clog2(MAX_DMF_NUM)-1 : 0] dmf_num_per_ch
.dmf_continuous (dmf_continuous ),
.freq_manual (freq_manual ), // input [FREQ_WORD_WIDTH-1 : 0] freq_manual
.freq_manual_en (freq_manual_en ), // input freq_manual_en
@@ -788,6 +803,17 @@ freq_comp #(
.ch4_peak_index (ch4_peak_index ) // output reg [$clog2(PRBS_POS-1) : 0] ch4_peak_index
);
reg [12:0] chip_cnt = 'b0;
always @(posedge sys_clk) begin
if (sys_rst) begin
chip_cnt <= 'b0;
end
else begin
chip_cnt <= chip_cnt + 1'b1;
end
end
////////////////////////////////////////////////////////////////////////////////
//////////////////////////////// ILAs and VIOs /////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
@@ -818,8 +844,12 @@ vio_rfcontrl u_vio_rfcontrl
.probe_out14(rf_ctrl_mode_vio ), // output wire [0 : 0] probe_out14
.probe_out15(switch_next_freq_vio ), // output wire [0 : 0] probe_out15
.probe_out16(switch_last_freq_vio ), // output wire [0 : 0] probe_out16
.probe_out17(cnt_valid_to_switch_vio[15:0] ), // output wire [15: 0] probe_out17
.probe_in0 (vio_frequency_auto[15:0] ) // input wire [10: 0] probe_in0
.probe_out17(cnt_valid_to_switch_vio[31:0] ), // output wire [15: 0] probe_out17
.probe_out18(cnt_switch_to_freq_start_vio[31:0] ), // output wire [15: 0] probe_out18
.probe_out19(cnt_sync_in_vio[31:0] ), // output wire [31: 0] probe_out19
.probe_out20(cnt_sync_in_high_vio[31:0] ), // output wire [31: 0] probe_out20
.probe_in0 (vio_frequency_auto[15:0] ), // input wire [15: 0] probe_in0
.probe_in1 (debug_io_3 ) // input wire [0: 0] probe_in1
);
vio_ant_test u_vio_ant_test
@@ -831,78 +861,78 @@ vio_ant_test u_vio_ant_test
.probe_out3 (u_ant_rf_ctrl.vio_hoptime[15:0] )
);
ila_rfcontrl u_ila_rfcontrl
(
.clk (clk_48m ), // input wire clk
.probe0 (u_ant_rf_ctrl.SPI_MOSI_F ), // input wire [0:0]
.probe1 (u_ant_rf_ctrl.SPI_MISO_F ), // input wire [0:0]
.probe2 (u_ant_rf_ctrl.SPI_SYN_F ), // input wire [0:0]
.probe3 (u_ant_rf_ctrl.TP_EN_F ), // input wire [0:0]
.probe4 (u_ant_rf_ctrl.TR_MGC_F ), // input wire [0:0]
.probe5 (u_ant_rf_ctrl.CAL_F ), // input wire [0:0]
.probe6 (u_ant_rf_ctrl.PRF ), // input wire [0:0]
.probe7 (u_ant_rf_ctrl.rf_standby ), // input wire [0:0]
.probe8 (u_ant_rf_ctrl.rf_sw_pll ), // input wire [0:0]
.probe9 (u_ant_rf_ctrl.rf_t ), // input wire [0:0]
.probe10(u_ant_rf_ctrl.rf_r ), // input wire [0:0]
.probe11(u_ant_rf_ctrl.rf_sw_bpf ), // input wire [0:0]
.probe12(u_ant_rf_ctrl.rf_sclk1 ), // input wire [0:0]
.probe13(u_ant_rf_ctrl.rf_sdio1 ), // input wire [0:0]
.probe14(u_ant_rf_ctrl.rf_cs1 ), // input wire [0:0]
.probe15(u_ant_rf_ctrl.rf_ld1 ), // input wire [0:0]
.probe16(u_ant_rf_ctrl.rf_sclk2 ), // input wire [0:0]
.probe17(u_ant_rf_ctrl.rf_sdio2 ), // input wire [0:0]
.probe18(u_ant_rf_ctrl.rf_cs2 ), // input wire [0:0]
.probe19(u_ant_rf_ctrl.rf_ld2 ), // input wire [0:0]
.probe20(u_ant_rf_ctrl.rf_sclk3 ), // input wire [0:0]
.probe21(u_ant_rf_ctrl.rf_sdio3 ), // input wire [0:0]
.probe22(u_ant_rf_ctrl.rf_cs3 ), // input wire [0:0]
.probe23(u_ant_rf_ctrl.rf_ld3 ), // input wire [0:0]
.probe24(u_ant_rf_ctrl.rf_tmgc_16 ), // input wire [0:0]
.probe25(u_ant_rf_ctrl.rf_tmgc_8 ), // input wire [0:0]
.probe26(u_ant_rf_ctrl.rf_tmgc_4 ), // input wire [0:0]
.probe27(u_ant_rf_ctrl.rf_tmgc_2 ), // input wire [0:0]
.probe28(u_ant_rf_ctrl.rf_tmgc_1 ), // input wire [0:0]
.probe29(u_ant_rf_ctrl.rf_rmgc_16 ), // input wire [0:0]
.probe30(u_ant_rf_ctrl.rf_rmgc_8 ), // input wire [0:0]
.probe31(u_ant_rf_ctrl.rf_rmgc_4 ), // input wire [0:0]
.probe32(u_ant_rf_ctrl.rf_rmgc_2 ), // input wire [0:0]
.probe33(u_ant_rf_ctrl.rf_rmgc_1 ), // input wire [0:0]
.probe34(u_ant_rf_ctrl.rf_enable ), // input wire [0:0]
.probe35(u_ant_rf_ctrl.rf_sc ), // input wire [0:0]
.probe36(u_ant_rf_ctrl.rf_sd ), // input wire [0:0]
.probe37(u_ant_rf_ctrl.rf_endsyn ), // input wire [0:0]
.probe38(u_ant_rf_ctrl.rf_sdout ), // input wire [0:0]
.probe39(u_ant_rf_ctrl.state_rfdata[1:0] ), // input wire [0:0]
.probe40(u_ant_rf_ctrl.RF_temperature[7:0] ), // input wire [0:0]
.probe41(u_ant_rf_ctrl.RF_IFlocked[7:0] ), // input wire [0:0]
.probe42(u_ant_rf_ctrl.RF_RFAlocked[7:0] ), // input wire [0:0]
.probe43(u_ant_rf_ctrl.RF_RFBlocked[7:0] ), // input wire [0:0]
.probe44(u_ant_rf_ctrl.RF_ch1mgc[3:0] ), // input wire [0:0]
.probe45(u_ant_rf_ctrl.RF_ch2mgc[3:0] ), // input wire [0:0]
.probe46(u_ant_rf_ctrl.RF_ch3mgc[3:0] ), // input wire [0:0]
.probe47(u_ant_rf_ctrl.RF_ch4mgc[3:0] ), // input wire [0:0]
.probe48(u_ant_rf_ctrl.RF_Framecount[31:0] ), // input wire [0:0]
.probe49(u_ant_rf_ctrl.RF_RecvWord[95:0] ) // input wire [0:0]
);
// ila_rfcontrl u_ila_rfcontrl
// (
// .clk (clk_48m ), // input wire clk
// .probe0 (u_ant_rf_ctrl.SPI_MOSI_F ), // input wire [0:0]
// .probe1 (u_ant_rf_ctrl.SPI_MISO_F ), // input wire [0:0]
// .probe2 (u_ant_rf_ctrl.SPI_SYN_F ), // input wire [0:0]
// .probe3 (u_ant_rf_ctrl.TP_EN_F ), // input wire [0:0]
// .probe4 (u_ant_rf_ctrl.TR_MGC_F ), // input wire [0:0]
// .probe5 (u_ant_rf_ctrl.CAL_F ), // input wire [0:0]
// .probe6 (u_ant_rf_ctrl.PRF ), // input wire [0:0]
// .probe7 (u_ant_rf_ctrl.rf_standby ), // input wire [0:0]
// .probe8 (u_ant_rf_ctrl.rf_sw_pll ), // input wire [0:0]
// .probe9 (u_ant_rf_ctrl.rf_t ), // input wire [0:0]
// .probe10(u_ant_rf_ctrl.rf_r ), // input wire [0:0]
// .probe11(u_ant_rf_ctrl.rf_sw_bpf ), // input wire [0:0]
// .probe12(u_ant_rf_ctrl.rf_sclk1 ), // input wire [0:0]
// .probe13(u_ant_rf_ctrl.rf_sdio1 ), // input wire [0:0]
// .probe14(u_ant_rf_ctrl.rf_cs1 ), // input wire [0:0]
// .probe15(u_ant_rf_ctrl.rf_ld1 ), // input wire [0:0]
// .probe16(u_ant_rf_ctrl.rf_sclk2 ), // input wire [0:0]
// .probe17(u_ant_rf_ctrl.rf_sdio2 ), // input wire [0:0]
// .probe18(u_ant_rf_ctrl.rf_cs2 ), // input wire [0:0]
// .probe19(u_ant_rf_ctrl.rf_ld2 ), // input wire [0:0]
// .probe20(u_ant_rf_ctrl.rf_sclk3 ), // input wire [0:0]
// .probe21(u_ant_rf_ctrl.rf_sdio3 ), // input wire [0:0]
// .probe22(u_ant_rf_ctrl.rf_cs3 ), // input wire [0:0]
// .probe23(u_ant_rf_ctrl.rf_ld3 ), // input wire [0:0]
// .probe24(u_ant_rf_ctrl.rf_tmgc_16 ), // input wire [0:0]
// .probe25(u_ant_rf_ctrl.rf_tmgc_8 ), // input wire [0:0]
// .probe26(u_ant_rf_ctrl.rf_tmgc_4 ), // input wire [0:0]
// .probe27(u_ant_rf_ctrl.rf_tmgc_2 ), // input wire [0:0]
// .probe28(u_ant_rf_ctrl.rf_tmgc_1 ), // input wire [0:0]
// .probe29(u_ant_rf_ctrl.rf_rmgc_16 ), // input wire [0:0]
// .probe30(u_ant_rf_ctrl.rf_rmgc_8 ), // input wire [0:0]
// .probe31(u_ant_rf_ctrl.rf_rmgc_4 ), // input wire [0:0]
// .probe32(u_ant_rf_ctrl.rf_rmgc_2 ), // input wire [0:0]
// .probe33(u_ant_rf_ctrl.rf_rmgc_1 ), // input wire [0:0]
// .probe34(u_ant_rf_ctrl.rf_enable ), // input wire [0:0]
// .probe35(u_ant_rf_ctrl.rf_sc ), // input wire [0:0]
// .probe36(u_ant_rf_ctrl.rf_sd ), // input wire [0:0]
// .probe37(u_ant_rf_ctrl.rf_endsyn ), // input wire [0:0]
// .probe38(u_ant_rf_ctrl.rf_sdout ), // input wire [0:0]
// .probe39(u_ant_rf_ctrl.state_rfdata[1:0] ), // input wire [0:0]
// .probe40(u_ant_rf_ctrl.RF_temperature[7:0] ), // input wire [0:0]
// .probe41(u_ant_rf_ctrl.RF_IFlocked[7:0] ), // input wire [0:0]
// .probe42(u_ant_rf_ctrl.RF_RFAlocked[7:0] ), // input wire [0:0]
// .probe43(u_ant_rf_ctrl.RF_RFBlocked[7:0] ), // input wire [0:0]
// .probe44(u_ant_rf_ctrl.RF_ch1mgc[3:0] ), // input wire [0:0]
// .probe45(u_ant_rf_ctrl.RF_ch2mgc[3:0] ), // input wire [0:0]
// .probe46(u_ant_rf_ctrl.RF_ch3mgc[3:0] ), // input wire [0:0]
// .probe47(u_ant_rf_ctrl.RF_ch4mgc[3:0] ), // input wire [0:0]
// .probe48(u_ant_rf_ctrl.RF_Framecount[31:0] ), // input wire [0:0]
// .probe49(u_ant_rf_ctrl.RF_RecvWord[95:0] ) // input wire [0:0]
// );
ila_AntCtrl u_ila_AntCtrl
(
.clk (clk_96m ), // input wire clk
.probe0 (u_ant_rf_ctrl.ant_clk ), // input wire [0:0] probe0
.probe1 (u_ant_rf_ctrl.ant_en ), // input wire [0:0] probe1
.probe2 (u_ant_rf_ctrl.ant_data ), // input wire [0:0] probe2
.probe3 (u_ant_rf_ctrl.ant_tr ), // input wire [0:0] probe3
.probe4 (u_ant_rf_ctrl.ant_dary ), // input wire [0:0] probe4
.probe5 (u_ant_rf_ctrl.ant_dout ), // input wire [0:0] probe5
.probe6 (u_ant_rf_ctrl.state_antdata[1:0] ), // input wire [0:0] probe5
.probe7 (u_ant_rf_ctrl.Ant_Ant_Volt[7:0] ), // input wire [0:0] probe5
.probe8 (u_ant_rf_ctrl.Ant_RF_Volt[7:0] ), // input wire [0:0] probe5
.probe9 (u_ant_rf_ctrl.Ant_IF_Volt[7:0] ), // input wire [0:0] probe5
.probe10(u_ant_rf_ctrl.Ant_state[7:0] ), // input wire [0:0] probe5
.probe11(u_ant_rf_ctrl.Ant_Framecount[31:0] ), // input wire [0:0] probe5
.probe12(u_ant_rf_ctrl.Ant_RecvWord[95:0] ) // input wire [0:0] probe5
);
// ila_AntCtrl u_ila_AntCtrl
// (
// .clk (clk_96m ), // input wire clk
// .probe0 (u_ant_rf_ctrl.ant_clk ), // input wire [0:0] probe0
// .probe1 (u_ant_rf_ctrl.ant_en ), // input wire [0:0] probe1
// .probe2 (u_ant_rf_ctrl.ant_data ), // input wire [0:0] probe2
// .probe3 (u_ant_rf_ctrl.ant_tr ), // input wire [0:0] probe3
// .probe4 (u_ant_rf_ctrl.ant_dary ), // input wire [0:0] probe4
// .probe5 (u_ant_rf_ctrl.ant_dout ), // input wire [0:0] probe5
// .probe6 (u_ant_rf_ctrl.state_antdata[1:0] ), // input wire [0:0] probe5
// .probe7 (u_ant_rf_ctrl.Ant_Ant_Volt[7:0] ), // input wire [0:0] probe5
// .probe8 (u_ant_rf_ctrl.Ant_RF_Volt[7:0] ), // input wire [0:0] probe5
// .probe9 (u_ant_rf_ctrl.Ant_IF_Volt[7:0] ), // input wire [0:0] probe5
// .probe10(u_ant_rf_ctrl.Ant_state[7:0] ), // input wire [0:0] probe5
// .probe11(u_ant_rf_ctrl.Ant_Framecount[31:0] ), // input wire [0:0] probe5
// .probe12(u_ant_rf_ctrl.Ant_RecvWord[95:0] ) // input wire [0:0] probe5
// );
vio_rf_rd u_vio_rf_rd (
.clk (clk_96m ), // input wire clk
@@ -935,17 +965,19 @@ ila_2x12x1024 u_ila_tx
.probe1 (tx_ch1_q ) // input wire [11:0] probe1
);
ila_8x12_8192 u_ila_rx
ila_rx_data_cnt u_ila_rx
(
.clk (sys_clk ), // input wire clk
.probe0 (rx_cal_ch1_i ), // input wire [11:0] probe0
.probe1 (rx_cal_ch1_q ), // input wire [11:0] probe1
.probe2 (rx_cal_ch2_i ), // input wire [11:0] probe2
.probe3 (rx_cal_ch2_q ), // input wire [11:0] probe3
.probe4 (rx_cal_ch3_i ), // input wire [11:0] probe4
.probe5 (rx_cal_ch3_q ), // input wire [11:0] probe5
.probe6 (rx_cal_ch4_i ), // input wire [11:0] probe6
.probe7 (rx_cal_ch4_q ) // input wire [11:0] probe7
.clk (sys_clk ), // input wire clk
.probe0 (rx_cal_ch1_i ), // input wire [11:0] probe0
.probe1 (rx_cal_ch1_q ), // input wire [11:0] probe1
.probe2 (rx_cal_ch2_i ), // input wire [11:0] probe2
.probe3 (rx_cal_ch2_q ), // input wire [11:0] probe3
.probe4 (rx_cal_ch3_i ), // input wire [11:0] probe4
.probe5 (rx_cal_ch3_q ), // input wire [11:0] probe5
.probe6 (rx_cal_ch4_i ), // input wire [11:0] probe6
.probe7 (rx_cal_ch4_q ), // input wire [11:0] probe7
.probe8 (vio_frequency_auto[11:0] ), // input wire [11:0] probe8
.probe9 (chip_cnt ) // input wire [12:0] probe9
);
ila_cal u_ila_cal
@@ -980,39 +1012,40 @@ vio_manual_ctrl u_vio_manual_ctrl
vio_freq_comp u_vio_freq_comp
(
.clk (sys_clk ), // input wire clk
.probe_in0 (freq_comp_busy ), // input wire [0 : 0] probe_in0
.probe_out0 (freq_comp_start ), // output wire [0 : 0] probe_out0
.probe_out1 (dmf_num_per_ch ), // output wire [7 : 0] probe_out1
.probe_out2 (freq_manual_en ), // output wire [0 : 0] probe_out2
.probe_out3 (freq_manual ) // output wire [31 : 0] probe_out3
.clk (sys_clk_4x ), // input wire clk
.probe_in0 (freq_comp_busy ), // input wire [0 : 0] probe_in0
.probe_out0 (freq_comp_start_vio ), // output wire [0 : 0] probe_out0
.probe_out1 (dmf_num_per_ch ), // output wire [7 : 0] probe_out1
.probe_out2 (freq_manual_en ), // output wire [0 : 0] probe_out2
.probe_out3 (freq_manual ), // output wire [31 : 0] probe_out3
.probe_out4 (freq_comp_auto_enable_vio ), // output wire [0 : 0] probe_out4
.probe_out5 (dmf_continuous ) // output wire [0 : 0] probe_out5
);
ila_freq_comp u_ila_freq_comp
(
.clk (sys_clk ), // input wire clk
.probe0 (ch1_peak_value_i ), // input wire [17:0] probe0
.probe1 (ch1_peak_value_q ), // input wire [17:0] probe1
.probe2 (ch2_peak_value_i ), // input wire [17:0] probe2
.probe3 (ch2_peak_value_q ), // input wire [17:0] probe3
.probe4 (ch3_peak_value_i ), // input wire [17:0] probe4
.probe5 (ch3_peak_value_q ), // input wire [17:0] probe5
.probe6 (ch4_peak_value_i ), // input wire [17:0] probe6
.probe7 (ch4_peak_value_q ), // input wire [17:0] probe7
.probe8 (u_freq_comp.u_rx_dmf.moduli_abs), // input wire [17:0] probe8
.probe9 (u_freq_comp.state_curr ), // input wire [2:0] probe9
.probe10(freq_comp_start ), // input wire [0:0] probe10
.probe11(u_freq_comp.dmf_peak_valid ), // input wire [0:0] probe11
.probe12(ch_peak_valid ), // input wire [0:0] probe12
.probe13(u_freq_comp.freq_word ), // input wire [31:0] probe13
.probe14(freq_target_valid ), // input wire [0:0] probe14
.probe15(freq_target ), // input wire [31:0] probe15
.probe16(u_freq_comp.din_cxr_real ), // input wire [11:0] probe16
.probe17(u_freq_comp.din_cxr_imag ), // input wire [11:0] probe17
.probe18(ch1_peak_index ), // input wire [9:0] probe18
.probe19(ch2_peak_index ), // input wire [9:0] probe19
.probe20(ch3_peak_index ), // input wire [9:0] probe20
.probe21(ch4_peak_index ) // input wire [9:0] probe21
.clk (sys_clk_4x ), // input wire clk
.probe0 (ch_peak_valid ), // input wire [0:0] probe0
.probe1 (ch1_peak_value_i ), // input wire [17:0] probe1
.probe2 (ch1_peak_value_q ), // input wire [17:0] probe2
.probe3 (ch2_peak_value_i ), // input wire [17:0] probe3
.probe4 (ch2_peak_value_q ), // input wire [17:0] probe4
.probe5 (ch3_peak_value_i ), // input wire [17:0] probe5
.probe6 (ch3_peak_value_q ), // input wire [17:0] probe6
.probe7 (ch4_peak_value_i ), // input wire [17:0] probe7
.probe8 (ch4_peak_value_q ), // input wire [17:0] probe8
.probe9 (ch1_peak_index ), // input wire [10:0] probe9
.probe10(ch2_peak_index ), // input wire [10:0] probe10
.probe11(ch3_peak_index ), // input wire [10:0] probe11
.probe12(ch4_peak_index ), // input wire [10:0] probe12
.probe13(freq_comp_start ), // input wire [0:0] probe13
.probe14(u_freq_comp.state_curr ), // input wire [2:0] probe14
.probe15(u_freq_comp.din_freq_cxr_real ), // input wire [11:0] probe15
.probe16(u_freq_comp.din_freq_cxr_imag ), // input wire [11:0] probe16
.probe17(u_freq_comp.dmf_freq_moduli_abs ), // input wire [17:0] probe17
.probe18(u_freq_comp.dmf_ch_moduli_abs[0] ), // input wire [17:0] probe18
.probe19(u_freq_comp.freq_word ), // input wire [31:0] probe19
.probe20(vio_frequency_auto[11:0] ) // input wire [11:0] probe20
);
endmodule