change online acq pn code length, change 814 online acq to the same

修改了在线捕获程序的PN码长和频偏搜索步进,修改了地检发送程序的PN码长,使用对飞相控阵进行了测试,得到正确结果;将程序移植到814平台,同样能够正常工作;对地检程序(20230512),对飞程序(20230512)和814程序(20230415)进行归档

projects/duifei/duifei_online_acq_par/ip/coe/prbs7_invert_rep2.coe

@@ -1,258 +0,0 @@
-RADIX = 10;
-COEFDATA = 
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
--1,
--1,
--1,
--1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
--1,
--1,
-1,
-1,
--1,
--1,
-1,
-1,
-1,
-1,
-1,
-1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
-1,
-1,
-1,
-1,
--1,
--1,
-1,
-1,
-1,
-1,
-1,
-1,
--1,
--1,
-1,
-1,
--1,
--1,
--1,
--1,
-1,
-1,
-1,
-1,
--1,
--1,
--1,
--1,
--1,
--1,
-1,
-1,
--1,
--1,
-1,
-1,
--1,
--1,
-1,
-1,
-1,
-1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
-1,
-1,
--1,
--1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
--1,
--1,
--1,
--1,
--1,
--1,
-1,
-1,
-1,
-1,
-1,
-1,
--1,
--1,
-1,
-1,
-1,
-1,
--1,
--1,
-1,
-1,
-1,
-1,
--1,
--1,
--1,
--1,
-1,
-1,
--1,
--1,
--1,
--1,
-1,
-1,
--1,
--1,
-1,
-1,
--1,
--1,
--1,
--1,
-1,
-1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
-1,
-1,
--1,
--1,
--1,
--1,
-1,
-1,
-1,
-1,
-1,
-1,
--1,
--1,
--1,
--1,
-1,
-1,
--1,
--1,
-1,
-1,
-1,
-1,
--1,
--1,
-1,
-1,
--1,
--1,
--1,
--1,
--1,
--1,
-1,
-1,
--1,
--1,
--1,
--1,
--1,
--1,
-1,
-1,
-1,
-1,
--1,
--1,
--1,
--1,
-1,
-1,
-1,
-1,
--1,
--1,
-1,
-1,
--1,
--1,
-1,
-1,
--1,
--1,
-1,
-1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
--1,
--1;

projects/duifei/duifei_online_acq_par/ip/coe/prbs7_invert_rep4.coe

@@ -1,514 +0,0 @@
-RADIX = 10;
-COEFDATA = 
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
--1,
--1,
--1,
--1,
-1,
-1,
-1,
-1,
--1,
--1,
--1,
--1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
--1,
--1,
--1,
--1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
--1,
--1,
--1,
--1,
-1,
-1,
-1,
-1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
-1,
-1,
-1,
-1,
--1,
--1,
--1,
--1,
-1,
-1,
-1,
-1,
--1,
--1,
--1,
--1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
-1,
-1,
-1,
-1,
--1,
--1,
--1,
--1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
--1,
--1,
--1,
--1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
--1,
--1,
--1,
--1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
-1,
-1,
-1,
-1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
-1,
-1,
-1,
-1,
--1,
--1,
--1,
--1,
-1,
-1,
-1,
-1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
-1,
-1,
-1,
-1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
-1,
-1,
-1,
-1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
-1,
-1,
-1,
-1,
--1,
--1,
--1,
--1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
--1,
--1,
--1,
--1,
-1,
-1,
-1,
-1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
-1,
-1,
-1,
-1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
--1,
--1,
--1,
--1,
-1,
-1,
-1,
-1,
--1,
--1,
--1,
--1,
-1,
-1,
-1,
-1,
--1,
--1,
--1,
--1,
-1,
-1,
-1,
-1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
--1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
-1,
--1,
--1,
--1,
--1;

projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fifo_rx_data/fifo_rx_data.veo

@@ -0,0 +1,73 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+// IP VLNV: xilinx.com:ip:fifo_generator:13.2
+// IP Revision: 4
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+fifo_rx_data your_instance_name (
+  .rst(rst),        // input wire rst
+  .wr_clk(wr_clk),  // input wire wr_clk
+  .rd_clk(rd_clk),  // input wire rd_clk
+  .din(din),        // input wire [95 : 0] din
+  .wr_en(wr_en),    // input wire wr_en
+  .rd_en(rd_en),    // input wire rd_en
+  .dout(dout),      // output wire [95 : 0] dout
+  .full(full),      // output wire full
+  .empty(empty)    // output wire empty
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file fifo_rx_data.v when simulating
+// the core, fifo_rx_data. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+

projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fifo_rx_data/fifo_rx_data.vho

@@ -0,0 +1,91 @@
+-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:fifo_generator:13.2
+-- IP Revision: 4
+
+-- The following code must appear in the VHDL architecture header.
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT fifo_rx_data
+  PORT (
+    rst : IN STD_LOGIC;
+    wr_clk : IN STD_LOGIC;
+    rd_clk : IN STD_LOGIC;
+    din : IN STD_LOGIC_VECTOR(95 DOWNTO 0);
+    wr_en : IN STD_LOGIC;
+    rd_en : IN STD_LOGIC;
+    dout : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
+    full : OUT STD_LOGIC;
+    empty : OUT STD_LOGIC
+  );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : fifo_rx_data
+  PORT MAP (
+    rst => rst,
+    wr_clk => wr_clk,
+    rd_clk => rd_clk,
+    din => din,
+    wr_en => wr_en,
+    rd_en => rd_en,
+    dout => dout,
+    full => full,
+    empty => empty
+  );
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+-- You must compile the wrapper file fifo_rx_data.vhd when simulating
+-- the core, fifo_rx_data. When compiling the wrapper file, be sure to
+-- reference the VHDL simulation library.
+

projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fifo_rx_data/fifo_rx_data_stub.v

@@ -0,0 +1,29 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+// Date        : Thu May 11 21:41:35 2023
+// Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
+// Command     : write_verilog -force -mode synth_stub
+//               /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data_stub.v
+// Design      : fifo_rx_data
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z100ffg900-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "fifo_generator_v13_2_4,Vivado 2019.1.3" *)
+module fifo_rx_data(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, 
+  empty)
+/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[95:0],wr_en,rd_en,dout[95:0],full,empty" */;
+  input rst;
+  input wr_clk;
+  input rd_clk;
+  input [95:0]din;
+  input wr_en;
+  input rd_en;
+  output [95:0]dout;
+  output full;
+  output empty;
+endmodule

projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fifo_rx_data/fifo_rx_data_stub.vhdl

@@ -0,0 +1,38 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+-- Date        : Thu May 11 21:41:35 2023
+-- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
+-- Command     : write_vhdl -force -mode synth_stub
+--               /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fifo_rx_data_synth_1/fifo_rx_data_stub.vhdl
+-- Design      : fifo_rx_data
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7z100ffg900-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity fifo_rx_data is
+  Port ( 
+    rst : in STD_LOGIC;
+    wr_clk : in STD_LOGIC;
+    rd_clk : in STD_LOGIC;
+    din : in STD_LOGIC_VECTOR ( 95 downto 0 );
+    wr_en : in STD_LOGIC;
+    rd_en : in STD_LOGIC;
+    dout : out STD_LOGIC_VECTOR ( 95 downto 0 );
+    full : out STD_LOGIC;
+    empty : out STD_LOGIC
+  );
+
+end fifo_rx_data;
+
+architecture stub of fifo_rx_data is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "rst,wr_clk,rd_clk,din[95:0],wr_en,rd_en,dout[95:0],full,empty";
+attribute x_core_info : string;
+attribute x_core_info of stub : architecture is "fifo_generator_v13_2_4,Vivado 2019.1.3";
+begin
+end;

projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fifo_rx_data/sim/fifo_rx_data.v

@@ -0,0 +1,524 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:fifo_generator:13.2
+// IP Revision: 4
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module fifo_rx_data (
+  rst,
+  wr_clk,
+  rd_clk,
+  din,
+  wr_en,
+  rd_en,
+  dout,
+  full,
+  empty
+);
+
+input wire rst;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME write_clk, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 write_clk CLK" *)
+input wire wr_clk;
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME read_clk, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 read_clk CLK" *)
+input wire rd_clk;
+(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *)
+input wire [95 : 0] din;
+(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *)
+input wire wr_en;
+(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *)
+input wire rd_en;
+(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *)
+output wire [95 : 0] dout;
+(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *)
+output wire full;
+(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *)
+output wire empty;
+
+  fifo_generator_v13_2_4 #(
+    .C_COMMON_CLOCK(0),
+    .C_SELECT_XPM(0),
+    .C_COUNT_TYPE(0),
+    .C_DATA_COUNT_WIDTH(4),
+    .C_DEFAULT_VALUE("BlankString"),
+    .C_DIN_WIDTH(96),
+    .C_DOUT_RST_VAL("0"),
+    .C_DOUT_WIDTH(96),
+    .C_ENABLE_RLOCS(0),
+    .C_FAMILY("zynq"),
+    .C_FULL_FLAGS_RST_VAL(1),
+    .C_HAS_ALMOST_EMPTY(0),
+    .C_HAS_ALMOST_FULL(0),
+    .C_HAS_BACKUP(0),
+    .C_HAS_DATA_COUNT(0),
+    .C_HAS_INT_CLK(0),
+    .C_HAS_MEMINIT_FILE(0),
+    .C_HAS_OVERFLOW(0),
+    .C_HAS_RD_DATA_COUNT(0),
+    .C_HAS_RD_RST(0),
+    .C_HAS_RST(1),
+    .C_HAS_SRST(0),
+    .C_HAS_UNDERFLOW(0),
+    .C_HAS_VALID(0),
+    .C_HAS_WR_ACK(0),
+    .C_HAS_WR_DATA_COUNT(0),
+    .C_HAS_WR_RST(0),
+    .C_IMPLEMENTATION_TYPE(2),
+    .C_INIT_WR_PNTR_VAL(0),
+    .C_MEMORY_TYPE(2),
+    .C_MIF_FILE_NAME("BlankString"),
+    .C_OPTIMIZATION_MODE(0),
+    .C_OVERFLOW_LOW(0),
+    .C_PRELOAD_LATENCY(1),
+    .C_PRELOAD_REGS(0),
+    .C_PRIM_FIFO_TYPE("512x72"),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
+    .C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
+    .C_PROG_EMPTY_TYPE(0),
+    .C_PROG_FULL_THRESH_ASSERT_VAL(13),
+    .C_PROG_FULL_THRESH_NEGATE_VAL(12),
+    .C_PROG_FULL_TYPE(0),
+    .C_RD_DATA_COUNT_WIDTH(4),
+    .C_RD_DEPTH(16),
+    .C_RD_FREQ(1),
+    .C_RD_PNTR_WIDTH(4),
+    .C_UNDERFLOW_LOW(0),
+    .C_USE_DOUT_RST(1),
+    .C_USE_ECC(0),
+    .C_USE_EMBEDDED_REG(0),
+    .C_USE_PIPELINE_REG(0),
+    .C_POWER_SAVING_MODE(0),
+    .C_USE_FIFO16_FLAGS(0),
+    .C_USE_FWFT_DATA_COUNT(0),
+    .C_VALID_LOW(0),
+    .C_WR_ACK_LOW(0),
+    .C_WR_DATA_COUNT_WIDTH(4),
+    .C_WR_DEPTH(16),
+    .C_WR_FREQ(1),
+    .C_WR_PNTR_WIDTH(4),
+    .C_WR_RESPONSE_LATENCY(1),
+    .C_MSGON_VAL(1),
+    .C_ENABLE_RST_SYNC(1),
+    .C_EN_SAFETY_CKT(0),
+    .C_ERROR_INJECTION_TYPE(0),
+    .C_SYNCHRONIZER_STAGE(3),
+    .C_INTERFACE_TYPE(0),
+    .C_AXI_TYPE(1),
+    .C_HAS_AXI_WR_CHANNEL(1),
+    .C_HAS_AXI_RD_CHANNEL(1),
+    .C_HAS_SLAVE_CE(0),
+    .C_HAS_MASTER_CE(0),
+    .C_ADD_NGC_CONSTRAINT(0),
+    .C_USE_COMMON_OVERFLOW(0),
+    .C_USE_COMMON_UNDERFLOW(0),
+    .C_USE_DEFAULT_SETTINGS(0),
+    .C_AXI_ID_WIDTH(1),
+    .C_AXI_ADDR_WIDTH(32),
+    .C_AXI_DATA_WIDTH(64),
+    .C_AXI_LEN_WIDTH(8),
+    .C_AXI_LOCK_WIDTH(1),
+    .C_HAS_AXI_ID(0),
+    .C_HAS_AXI_AWUSER(0),
+    .C_HAS_AXI_WUSER(0),
+    .C_HAS_AXI_BUSER(0),
+    .C_HAS_AXI_ARUSER(0),
+    .C_HAS_AXI_RUSER(0),
+    .C_AXI_ARUSER_WIDTH(1),
+    .C_AXI_AWUSER_WIDTH(1),
+    .C_AXI_WUSER_WIDTH(1),
+    .C_AXI_BUSER_WIDTH(1),
+    .C_AXI_RUSER_WIDTH(1),
+    .C_HAS_AXIS_TDATA(1),
+    .C_HAS_AXIS_TID(0),
+    .C_HAS_AXIS_TDEST(0),
+    .C_HAS_AXIS_TUSER(1),
+    .C_HAS_AXIS_TREADY(1),
+    .C_HAS_AXIS_TLAST(0),
+    .C_HAS_AXIS_TSTRB(0),
+    .C_HAS_AXIS_TKEEP(0),
+    .C_AXIS_TDATA_WIDTH(8),
+    .C_AXIS_TID_WIDTH(1),
+    .C_AXIS_TDEST_WIDTH(1),
+    .C_AXIS_TUSER_WIDTH(4),
+    .C_AXIS_TSTRB_WIDTH(1),
+    .C_AXIS_TKEEP_WIDTH(1),
+    .C_WACH_TYPE(0),
+    .C_WDCH_TYPE(0),
+    .C_WRCH_TYPE(0),
+    .C_RACH_TYPE(0),
+    .C_RDCH_TYPE(0),
+    .C_AXIS_TYPE(0),
+    .C_IMPLEMENTATION_TYPE_WACH(1),
+    .C_IMPLEMENTATION_TYPE_WDCH(1),
+    .C_IMPLEMENTATION_TYPE_WRCH(1),
+    .C_IMPLEMENTATION_TYPE_RACH(1),
+    .C_IMPLEMENTATION_TYPE_RDCH(1),
+    .C_IMPLEMENTATION_TYPE_AXIS(1),
+    .C_APPLICATION_TYPE_WACH(0),
+    .C_APPLICATION_TYPE_WDCH(0),
+    .C_APPLICATION_TYPE_WRCH(0),
+    .C_APPLICATION_TYPE_RACH(0),
+    .C_APPLICATION_TYPE_RDCH(0),
+    .C_APPLICATION_TYPE_AXIS(0),
+    .C_PRIM_FIFO_TYPE_WACH("512x36"),
+    .C_PRIM_FIFO_TYPE_WDCH("1kx36"),
+    .C_PRIM_FIFO_TYPE_WRCH("512x36"),
+    .C_PRIM_FIFO_TYPE_RACH("512x36"),
+    .C_PRIM_FIFO_TYPE_RDCH("1kx36"),
+    .C_PRIM_FIFO_TYPE_AXIS("1kx18"),
+    .C_USE_ECC_WACH(0),
+    .C_USE_ECC_WDCH(0),
+    .C_USE_ECC_WRCH(0),
+    .C_USE_ECC_RACH(0),
+    .C_USE_ECC_RDCH(0),
+    .C_USE_ECC_AXIS(0),
+    .C_ERROR_INJECTION_TYPE_WACH(0),
+    .C_ERROR_INJECTION_TYPE_WDCH(0),
+    .C_ERROR_INJECTION_TYPE_WRCH(0),
+    .C_ERROR_INJECTION_TYPE_RACH(0),
+    .C_ERROR_INJECTION_TYPE_RDCH(0),
+    .C_ERROR_INJECTION_TYPE_AXIS(0),
+    .C_DIN_WIDTH_WACH(1),
+    .C_DIN_WIDTH_WDCH(64),
+    .C_DIN_WIDTH_WRCH(2),
+    .C_DIN_WIDTH_RACH(32),
+    .C_DIN_WIDTH_RDCH(64),
+    .C_DIN_WIDTH_AXIS(1),
+    .C_WR_DEPTH_WACH(16),
+    .C_WR_DEPTH_WDCH(1024),
+    .C_WR_DEPTH_WRCH(16),
+    .C_WR_DEPTH_RACH(16),
+    .C_WR_DEPTH_RDCH(1024),
+    .C_WR_DEPTH_AXIS(1024),
+    .C_WR_PNTR_WIDTH_WACH(4),
+    .C_WR_PNTR_WIDTH_WDCH(10),
+    .C_WR_PNTR_WIDTH_WRCH(4),
+    .C_WR_PNTR_WIDTH_RACH(4),
+    .C_WR_PNTR_WIDTH_RDCH(10),
+    .C_WR_PNTR_WIDTH_AXIS(10),
+    .C_HAS_DATA_COUNTS_WACH(0),
+    .C_HAS_DATA_COUNTS_WDCH(0),
+    .C_HAS_DATA_COUNTS_WRCH(0),
+    .C_HAS_DATA_COUNTS_RACH(0),
+    .C_HAS_DATA_COUNTS_RDCH(0),
+    .C_HAS_DATA_COUNTS_AXIS(0),
+    .C_HAS_PROG_FLAGS_WACH(0),
+    .C_HAS_PROG_FLAGS_WDCH(0),
+    .C_HAS_PROG_FLAGS_WRCH(0),
+    .C_HAS_PROG_FLAGS_RACH(0),
+    .C_HAS_PROG_FLAGS_RDCH(0),
+    .C_HAS_PROG_FLAGS_AXIS(0),
+    .C_PROG_FULL_TYPE_WACH(0),
+    .C_PROG_FULL_TYPE_WDCH(0),
+    .C_PROG_FULL_TYPE_WRCH(0),
+    .C_PROG_FULL_TYPE_RACH(0),
+    .C_PROG_FULL_TYPE_RDCH(0),
+    .C_PROG_FULL_TYPE_AXIS(0),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
+    .C_PROG_EMPTY_TYPE_WACH(0),
+    .C_PROG_EMPTY_TYPE_WDCH(0),
+    .C_PROG_EMPTY_TYPE_WRCH(0),
+    .C_PROG_EMPTY_TYPE_RACH(0),
+    .C_PROG_EMPTY_TYPE_RDCH(0),
+    .C_PROG_EMPTY_TYPE_AXIS(0),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
+    .C_REG_SLICE_MODE_WACH(0),
+    .C_REG_SLICE_MODE_WDCH(0),
+    .C_REG_SLICE_MODE_WRCH(0),
+    .C_REG_SLICE_MODE_RACH(0),
+    .C_REG_SLICE_MODE_RDCH(0),
+    .C_REG_SLICE_MODE_AXIS(0)
+  ) inst (
+    .backup(1'D0),
+    .backup_marker(1'D0),
+    .clk(1'D0),
+    .rst(rst),
+    .srst(1'D0),
+    .wr_clk(wr_clk),
+    .wr_rst(1'D0),
+    .rd_clk(rd_clk),
+    .rd_rst(1'D0),
+    .din(din),
+    .wr_en(wr_en),
+    .rd_en(rd_en),
+    .prog_empty_thresh(4'B0),
+    .prog_empty_thresh_assert(4'B0),
+    .prog_empty_thresh_negate(4'B0),
+    .prog_full_thresh(4'B0),
+    .prog_full_thresh_assert(4'B0),
+    .prog_full_thresh_negate(4'B0),
+    .int_clk(1'D0),
+    .injectdbiterr(1'D0),
+    .injectsbiterr(1'D0),
+    .sleep(1'D0),
+    .dout(dout),
+    .full(full),
+    .almost_full(),
+    .wr_ack(),
+    .overflow(),
+    .empty(empty),
+    .almost_empty(),
+    .valid(),
+    .underflow(),
+    .data_count(),
+    .rd_data_count(),
+    .wr_data_count(),
+    .prog_full(),
+    .prog_empty(),
+    .sbiterr(),
+    .dbiterr(),
+    .wr_rst_busy(),
+    .rd_rst_busy(),
+    .m_aclk(1'D0),
+    .s_aclk(1'D0),
+    .s_aresetn(1'D0),
+    .m_aclk_en(1'D0),
+    .s_aclk_en(1'D0),
+    .s_axi_awid(1'B0),
+    .s_axi_awaddr(32'B0),
+    .s_axi_awlen(8'B0),
+    .s_axi_awsize(3'B0),
+    .s_axi_awburst(2'B0),
+    .s_axi_awlock(1'B0),
+    .s_axi_awcache(4'B0),
+    .s_axi_awprot(3'B0),
+    .s_axi_awqos(4'B0),
+    .s_axi_awregion(4'B0),
+    .s_axi_awuser(1'B0),
+    .s_axi_awvalid(1'D0),
+    .s_axi_awready(),
+    .s_axi_wid(1'B0),
+    .s_axi_wdata(64'B0),
+    .s_axi_wstrb(8'B0),
+    .s_axi_wlast(1'D0),
+    .s_axi_wuser(1'B0),
+    .s_axi_wvalid(1'D0),
+    .s_axi_wready(),
+    .s_axi_bid(),
+    .s_axi_bresp(),
+    .s_axi_buser(),
+    .s_axi_bvalid(),
+    .s_axi_bready(1'D0),
+    .m_axi_awid(),
+    .m_axi_awaddr(),
+    .m_axi_awlen(),
+    .m_axi_awsize(),
+    .m_axi_awburst(),
+    .m_axi_awlock(),
+    .m_axi_awcache(),
+    .m_axi_awprot(),
+    .m_axi_awqos(),
+    .m_axi_awregion(),
+    .m_axi_awuser(),
+    .m_axi_awvalid(),
+    .m_axi_awready(1'D0),
+    .m_axi_wid(),
+    .m_axi_wdata(),
+    .m_axi_wstrb(),
+    .m_axi_wlast(),
+    .m_axi_wuser(),
+    .m_axi_wvalid(),
+    .m_axi_wready(1'D0),
+    .m_axi_bid(1'B0),
+    .m_axi_bresp(2'B0),
+    .m_axi_buser(1'B0),
+    .m_axi_bvalid(1'D0),
+    .m_axi_bready(),
+    .s_axi_arid(1'B0),
+    .s_axi_araddr(32'B0),
+    .s_axi_arlen(8'B0),
+    .s_axi_arsize(3'B0),
+    .s_axi_arburst(2'B0),
+    .s_axi_arlock(1'B0),
+    .s_axi_arcache(4'B0),
+    .s_axi_arprot(3'B0),
+    .s_axi_arqos(4'B0),
+    .s_axi_arregion(4'B0),
+    .s_axi_aruser(1'B0),
+    .s_axi_arvalid(1'D0),
+    .s_axi_arready(),
+    .s_axi_rid(),
+    .s_axi_rdata(),
+    .s_axi_rresp(),
+    .s_axi_rlast(),
+    .s_axi_ruser(),
+    .s_axi_rvalid(),
+    .s_axi_rready(1'D0),
+    .m_axi_arid(),
+    .m_axi_araddr(),
+    .m_axi_arlen(),
+    .m_axi_arsize(),
+    .m_axi_arburst(),
+    .m_axi_arlock(),
+    .m_axi_arcache(),
+    .m_axi_arprot(),
+    .m_axi_arqos(),
+    .m_axi_arregion(),
+    .m_axi_aruser(),
+    .m_axi_arvalid(),
+    .m_axi_arready(1'D0),
+    .m_axi_rid(1'B0),
+    .m_axi_rdata(64'B0),
+    .m_axi_rresp(2'B0),
+    .m_axi_rlast(1'D0),
+    .m_axi_ruser(1'B0),
+    .m_axi_rvalid(1'D0),
+    .m_axi_rready(),
+    .s_axis_tvalid(1'D0),
+    .s_axis_tready(),
+    .s_axis_tdata(8'B0),
+    .s_axis_tstrb(1'B0),
+    .s_axis_tkeep(1'B0),
+    .s_axis_tlast(1'D0),
+    .s_axis_tid(1'B0),
+    .s_axis_tdest(1'B0),
+    .s_axis_tuser(4'B0),
+    .m_axis_tvalid(),
+    .m_axis_tready(1'D0),
+    .m_axis_tdata(),
+    .m_axis_tstrb(),
+    .m_axis_tkeep(),
+    .m_axis_tlast(),
+    .m_axis_tid(),
+    .m_axis_tdest(),
+    .m_axis_tuser(),
+    .axi_aw_injectsbiterr(1'D0),
+    .axi_aw_injectdbiterr(1'D0),
+    .axi_aw_prog_full_thresh(4'B0),
+    .axi_aw_prog_empty_thresh(4'B0),
+    .axi_aw_data_count(),
+    .axi_aw_wr_data_count(),
+    .axi_aw_rd_data_count(),
+    .axi_aw_sbiterr(),
+    .axi_aw_dbiterr(),
+    .axi_aw_overflow(),
+    .axi_aw_underflow(),
+    .axi_aw_prog_full(),
+    .axi_aw_prog_empty(),
+    .axi_w_injectsbiterr(1'D0),
+    .axi_w_injectdbiterr(1'D0),
+    .axi_w_prog_full_thresh(10'B0),
+    .axi_w_prog_empty_thresh(10'B0),
+    .axi_w_data_count(),
+    .axi_w_wr_data_count(),
+    .axi_w_rd_data_count(),
+    .axi_w_sbiterr(),
+    .axi_w_dbiterr(),
+    .axi_w_overflow(),
+    .axi_w_underflow(),
+    .axi_w_prog_full(),
+    .axi_w_prog_empty(),
+    .axi_b_injectsbiterr(1'D0),
+    .axi_b_injectdbiterr(1'D0),
+    .axi_b_prog_full_thresh(4'B0),
+    .axi_b_prog_empty_thresh(4'B0),
+    .axi_b_data_count(),
+    .axi_b_wr_data_count(),
+    .axi_b_rd_data_count(),
+    .axi_b_sbiterr(),
+    .axi_b_dbiterr(),
+    .axi_b_overflow(),
+    .axi_b_underflow(),
+    .axi_b_prog_full(),
+    .axi_b_prog_empty(),
+    .axi_ar_injectsbiterr(1'D0),
+    .axi_ar_injectdbiterr(1'D0),
+    .axi_ar_prog_full_thresh(4'B0),
+    .axi_ar_prog_empty_thresh(4'B0),
+    .axi_ar_data_count(),
+    .axi_ar_wr_data_count(),
+    .axi_ar_rd_data_count(),
+    .axi_ar_sbiterr(),
+    .axi_ar_dbiterr(),
+    .axi_ar_overflow(),
+    .axi_ar_underflow(),
+    .axi_ar_prog_full(),
+    .axi_ar_prog_empty(),
+    .axi_r_injectsbiterr(1'D0),
+    .axi_r_injectdbiterr(1'D0),
+    .axi_r_prog_full_thresh(10'B0),
+    .axi_r_prog_empty_thresh(10'B0),
+    .axi_r_data_count(),
+    .axi_r_wr_data_count(),
+    .axi_r_rd_data_count(),
+    .axi_r_sbiterr(),
+    .axi_r_dbiterr(),
+    .axi_r_overflow(),
+    .axi_r_underflow(),
+    .axi_r_prog_full(),
+    .axi_r_prog_empty(),
+    .axis_injectsbiterr(1'D0),
+    .axis_injectdbiterr(1'D0),
+    .axis_prog_full_thresh(10'B0),
+    .axis_prog_empty_thresh(10'B0),
+    .axis_data_count(),
+    .axis_wr_data_count(),
+    .axis_rd_data_count(),
+    .axis_sbiterr(),
+    .axis_dbiterr(),
+    .axis_overflow(),
+    .axis_underflow(),
+    .axis_prog_full(),
+    .axis_prog_empty()
+  );
+endmodule

projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs10_invert_rep2/demo_tb/tb_fir_prbs10_invert_rep2.vhd

@@ -0,0 +1,272 @@
+--------------------------------------------------------------------------------
+-- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--------------------------------------------------------------------------------
+-- Description:
+-- This is an example testbench for the FIR Compiler IP core.
+-- The testbench has been generated by Vivado to accompany the IP core
+-- instance you have generated.
+--
+-- This testbench is for demonstration purposes only.  See note below for
+-- instructions on how to use it with your core.
+--
+-- See the FIR Compiler product guide for further information
+-- about this core.
+--
+--------------------------------------------------------------------------------
+-- Using this testbench
+--
+-- This testbench instantiates your generated FIR Compiler core
+-- instance named "fir_prbs10_invert_rep2".
+--
+-- Use Vivado's Run Simulation flow to run this testbench.  See the Vivado
+-- documentation for details.
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tb_fir_prbs10_invert_rep2 is
+end tb_fir_prbs10_invert_rep2;
+
+architecture tb of tb_fir_prbs10_invert_rep2 is
+
+  -----------------------------------------------------------------------
+  -- Timing constants
+  -----------------------------------------------------------------------
+  constant CLOCK_PERIOD : time := 100 ns;
+  constant T_HOLD       : time := 10 ns;
+  constant T_STROBE     : time := CLOCK_PERIOD - (1 ns);
+
+  -----------------------------------------------------------------------
+  -- DUT signals
+  -----------------------------------------------------------------------
+
+  -- General signals
+  signal aclk                            : std_logic := '0';  -- the master clock
+  signal aresetn                         : std_logic := '1';  -- synchronous active low reset
+
+  -- Data slave channel signals
+  signal s_axis_data_tvalid              : std_logic := '0';  -- payload is valid
+  signal s_axis_data_tready              : std_logic := '1';  -- slave is ready
+  signal s_axis_data_tdata               : std_logic_vector(15 downto 0) := (others => '0');  -- data payload
+
+  -- Data master channel signals
+  signal m_axis_data_tvalid              : std_logic := '0';  -- payload is valid
+  signal m_axis_data_tdata               : std_logic_vector(23 downto 0) := (others => '0');  -- data payload
+
+  -----------------------------------------------------------------------
+  -- Aliases for AXI channel TDATA and TUSER fields
+  -- These are a convenience for viewing data in a simulator waveform viewer.
+  -- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
+  -- to prevent the simulator optimizing away these signals.
+  -----------------------------------------------------------------------
+
+  -- Data slave channel alias signals
+  signal s_axis_data_tdata_data        : std_logic_vector(11 downto 0) := (others => '0');
+
+  -- Data master channel alias signals
+  signal m_axis_data_tdata_data        : std_logic_vector(22 downto 0) := (others => '0');
+
+
+begin
+
+  -----------------------------------------------------------------------
+  -- Instantiate the DUT
+  -----------------------------------------------------------------------
+
+  dut : entity work.fir_prbs10_invert_rep2
+    port map (
+      aclk                            => aclk,
+      aresetn                         => aresetn,
+      s_axis_data_tvalid              => s_axis_data_tvalid,
+      s_axis_data_tready              => s_axis_data_tready,
+      s_axis_data_tdata               => s_axis_data_tdata,
+      m_axis_data_tvalid              => m_axis_data_tvalid,
+      m_axis_data_tdata               => m_axis_data_tdata
+      );
+
+  -----------------------------------------------------------------------
+  -- Generate clock
+  -----------------------------------------------------------------------
+
+  clock_gen : process
+  begin
+    aclk <= '0';
+    wait for CLOCK_PERIOD;
+    loop
+      aclk <= '0';
+      wait for CLOCK_PERIOD/2;
+      aclk <= '1';
+      wait for CLOCK_PERIOD/2;
+    end loop;
+  end process clock_gen;
+
+  -----------------------------------------------------------------------
+  -- Generate inputs
+  -----------------------------------------------------------------------
+
+  stimuli : process
+
+    -- Procedure to drive a number of input samples with specific data
+    -- data is the data value to drive on the tdata signal
+    -- samples is the number of zero-data input samples to drive
+    procedure drive_data ( data    : std_logic_vector(15 downto 0);
+                           samples : natural := 1 ) is
+      variable ip_count : integer := 0;
+    begin
+      ip_count := 0;
+      loop
+        s_axis_data_tvalid <= '1';
+        s_axis_data_tdata  <= data;
+        loop
+          wait until rising_edge(aclk);
+          exit when s_axis_data_tready = '1';
+        end loop;
+        ip_count := ip_count + 1;
+        wait for T_HOLD;
+      -- Input rate is 1 input each 16 clock cycles: drive valid inputs at this rate
+        s_axis_data_tvalid <= '0';
+        wait for CLOCK_PERIOD * 15;
+        exit when ip_count >= samples;
+      end loop;
+    end procedure drive_data;
+
+    -- Procedure to drive a number of zero-data input samples
+    -- samples is the number of zero-data input samples to drive
+    procedure drive_zeros ( samples : natural := 1 ) is
+    begin
+      drive_data((others => '0'), samples);
+    end procedure drive_zeros;
+
+    -- Procedure to drive an impulse and let the impulse response emerge on the data master channel
+    -- samples is the number of input samples to drive; default is enough for impulse response output to emerge
+    procedure drive_impulse ( samples : natural := 2062 ) is
+      variable impulse : std_logic_vector(15 downto 0);
+    begin
+      impulse := (others => '0');  -- initialize unused bits to zero
+      impulse(11 downto 0) := "010000000000";
+      drive_data(impulse);
+      if samples > 1 then
+        drive_zeros(samples-1);
+      end if;
+    end procedure drive_impulse;
+
+  begin
+
+    -- Drive inputs T_HOLD time after rising edge of clock
+    wait until rising_edge(aclk) and aresetn = '1';
+    wait for T_HOLD;
+
+    -- Drive a single impulse and let the impulse response emerge
+    drive_impulse;
+
+    -- Drive another impulse, during which demonstrate use and effect of AXI handshaking signals
+    drive_impulse(2);  -- start of impulse; data is now zero
+    s_axis_data_tvalid <= '0';
+    wait for CLOCK_PERIOD * 80;  -- provide no data for 5 input samples worth
+    drive_zeros(2);  -- 2 normal input samples
+    s_axis_data_tvalid <= '1';
+    wait for CLOCK_PERIOD * 80;  -- provide data as fast as the core can accept it for 5 input samples worth
+    drive_zeros(2053);  -- back to normal operation
+
+    -- Drive another impulse, during which demonstrate:
+    --   reset (aresetn)
+    drive_impulse(521);  -- to partway through impulse response
+    s_axis_data_tvalid <= '0';
+    aresetn <= '0';  -- assert reset (active low)
+    wait for CLOCK_PERIOD * 2;  -- hold reset active for 2 clock cycles, as recommended in FIR Compiler Datasheet
+    aresetn <= '1';  -- deassert reset
+    drive_impulse;  -- send new impulse, following reset
+
+    -- End of test
+    report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;
+    wait;
+
+  end process stimuli;
+
+  -----------------------------------------------------------------------
+  -- Check outputs
+  -----------------------------------------------------------------------
+
+  check_outputs : process
+    variable check_ok : boolean := true;
+  begin
+
+    -- Check outputs T_STROBE time after rising edge of clock
+    wait until rising_edge(aclk);
+    wait for T_STROBE;
+
+    -- Do not check the output payload values, as this requires the behavioral model
+    -- which would make this demonstration testbench unwieldy.
+    -- Instead, check the protocol of the master DATA channel:
+    -- check that the payload is valid (not X) when TVALID is high
+
+    if m_axis_data_tvalid = '1' and aresetn = '1' then
+      if is_x(m_axis_data_tdata) then
+        report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error;
+        check_ok := false;
+      end if;
+
+    end if;
+
+    assert check_ok
+      report "ERROR: terminating test with failures." severity failure;
+
+  end process check_outputs;
+
+  -----------------------------------------------------------------------
+  -- Assign TDATA / TUSER fields to aliases, for easy simulator waveform viewing
+  -----------------------------------------------------------------------
+
+  -- Data slave channel alias signals
+  s_axis_data_tdata_data        <= s_axis_data_tdata(11 downto 0);
+
+  -- Data master channel alias signals: update these only when they are valid
+  m_axis_data_tdata_data        <= m_axis_data_tdata(22 downto 0) when m_axis_data_tvalid = '1';
+
+end tb;

projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs10_invert_rep2/fir_prbs10_invert_rep2.veo

@@ -0,0 +1,71 @@
+// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+// IP VLNV: xilinx.com:ip:fir_compiler:7.2
+// IP Revision: 12
+
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+fir_prbs10_invert_rep2 your_instance_name (
+  .aresetn(aresetn),                        // input wire aresetn
+  .aclk(aclk),                              // input wire aclk
+  .s_axis_data_tvalid(s_axis_data_tvalid),  // input wire s_axis_data_tvalid
+  .s_axis_data_tready(s_axis_data_tready),  // output wire s_axis_data_tready
+  .s_axis_data_tdata(s_axis_data_tdata),    // input wire [15 : 0] s_axis_data_tdata
+  .m_axis_data_tvalid(m_axis_data_tvalid),  // output wire m_axis_data_tvalid
+  .m_axis_data_tdata(m_axis_data_tdata)    // output wire [23 : 0] m_axis_data_tdata
+);
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file fir_prbs10_invert_rep2.v when simulating
+// the core, fir_prbs10_invert_rep2. When compiling the wrapper file, be sure to
+// reference the Verilog simulation library.
+

projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs10_invert_rep2/fir_prbs10_invert_rep2.vho

@@ -0,0 +1,87 @@
+-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
+-- IP Revision: 12
+
+-- The following code must appear in the VHDL architecture header.
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+COMPONENT fir_prbs10_invert_rep2
+  PORT (
+    aresetn : IN STD_LOGIC;
+    aclk : IN STD_LOGIC;
+    s_axis_data_tvalid : IN STD_LOGIC;
+    s_axis_data_tready : OUT STD_LOGIC;
+    s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+    m_axis_data_tvalid : OUT STD_LOGIC;
+    m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+  );
+END COMPONENT;
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : fir_prbs10_invert_rep2
+  PORT MAP (
+    aresetn => aresetn,
+    aclk => aclk,
+    s_axis_data_tvalid => s_axis_data_tvalid,
+    s_axis_data_tready => s_axis_data_tready,
+    s_axis_data_tdata => s_axis_data_tdata,
+    m_axis_data_tvalid => m_axis_data_tvalid,
+    m_axis_data_tdata => m_axis_data_tdata
+  );
+-- INST_TAG_END ------ End INSTANTIATION Template ---------
+
+-- You must compile the wrapper file fir_prbs10_invert_rep2.vhd when simulating
+-- the core, fir_prbs10_invert_rep2. When compiling the wrapper file, be sure to
+-- reference the VHDL simulation library.
+

projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs10_invert_rep2/fir_prbs10_invert_rep2_stub.v

@@ -0,0 +1,27 @@
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+// Date        : Thu May 11 21:56:08 2023
+// Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
+// Command     : write_verilog -force -mode synth_stub
+//               /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2_stub.v
+// Design      : fir_prbs10_invert_rep2
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7z100ffg900-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "fir_compiler_v7_2_12,Vivado 2019.1.3" *)
+module fir_prbs10_invert_rep2(aresetn, aclk, s_axis_data_tvalid, 
+  s_axis_data_tready, s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata)
+/* synthesis syn_black_box black_box_pad_pin="aresetn,aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[15:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]" */;
+  input aresetn;
+  input aclk;
+  input s_axis_data_tvalid;
+  output s_axis_data_tready;
+  input [15:0]s_axis_data_tdata;
+  output m_axis_data_tvalid;
+  output [23:0]m_axis_data_tdata;
+endmodule

projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs10_invert_rep2/fir_prbs10_invert_rep2_stub.vhdl

@@ -0,0 +1,36 @@
+-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
+-- Date        : Thu May 11 21:56:08 2023
+-- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
+-- Command     : write_vhdl -force -mode synth_stub
+--               /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/fir_prbs10_invert_rep2_synth_1/fir_prbs10_invert_rep2_stub.vhdl
+-- Design      : fir_prbs10_invert_rep2
+-- Purpose     : Stub declaration of top-level module interface
+-- Device      : xc7z100ffg900-2
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity fir_prbs10_invert_rep2 is
+  Port ( 
+    aresetn : in STD_LOGIC;
+    aclk : in STD_LOGIC;
+    s_axis_data_tvalid : in STD_LOGIC;
+    s_axis_data_tready : out STD_LOGIC;
+    s_axis_data_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    m_axis_data_tvalid : out STD_LOGIC;
+    m_axis_data_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 )
+  );
+
+end fir_prbs10_invert_rep2;
+
+architecture stub of fir_prbs10_invert_rep2 is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "aresetn,aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[15:0],m_axis_data_tvalid,m_axis_data_tdata[23:0]";
+attribute x_core_info : string;
+attribute x_core_info of stub : architecture is "fir_compiler_v7_2_12,Vivado 2019.1.3";
+begin
+end;

projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/fir_prbs10_invert_rep2/sim/fir_prbs10_invert_rep2.vhd

@@ -0,0 +1,284 @@
+-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
+-- IP Revision: 12
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY fir_compiler_v7_2_12;
+USE fir_compiler_v7_2_12.fir_compiler_v7_2_12;
+
+ENTITY fir_prbs10_invert_rep2 IS
+  PORT (
+    aresetn : IN STD_LOGIC;
+    aclk : IN STD_LOGIC;
+    s_axis_data_tvalid : IN STD_LOGIC;
+    s_axis_data_tready : OUT STD_LOGIC;
+    s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+    m_axis_data_tvalid : OUT STD_LOGIC;
+    m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
+  );
+END fir_prbs10_invert_rep2;
+
+ARCHITECTURE fir_prbs10_invert_rep2_arch OF fir_prbs10_invert_rep2 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF fir_prbs10_invert_rep2_arch: ARCHITECTURE IS "yes";
+  COMPONENT fir_compiler_v7_2_12 IS
+    GENERIC (
+      C_XDEVICEFAMILY : STRING;
+      C_ELABORATION_DIR : STRING;
+      C_COMPONENT_NAME : STRING;
+      C_COEF_FILE : STRING;
+      C_COEF_FILE_LINES : INTEGER;
+      C_FILTER_TYPE : INTEGER;
+      C_INTERP_RATE : INTEGER;
+      C_DECIM_RATE : INTEGER;
+      C_ZERO_PACKING_FACTOR : INTEGER;
+      C_SYMMETRY : INTEGER;
+      C_NUM_FILTS : INTEGER;
+      C_NUM_TAPS : INTEGER;
+      C_NUM_CHANNELS : INTEGER;
+      C_CHANNEL_PATTERN : STRING;
+      C_ROUND_MODE : INTEGER;
+      C_COEF_RELOAD : INTEGER;
+      C_NUM_RELOAD_SLOTS : INTEGER;
+      C_COL_MODE : INTEGER;
+      C_COL_PIPE_LEN : INTEGER;
+      C_COL_CONFIG : STRING;
+      C_OPTIMIZATION : INTEGER;
+      C_DATA_PATH_WIDTHS : STRING;
+      C_DATA_IP_PATH_WIDTHS : STRING;
+      C_DATA_PX_PATH_WIDTHS : STRING;
+      C_DATA_WIDTH : INTEGER;
+      C_COEF_PATH_WIDTHS : STRING;
+      C_COEF_WIDTH : INTEGER;
+      C_DATA_PATH_SRC : STRING;
+      C_COEF_PATH_SRC : STRING;
+      C_PX_PATH_SRC : STRING;
+      C_DATA_PATH_SIGN : STRING;
+      C_COEF_PATH_SIGN : STRING;
+      C_ACCUM_PATH_WIDTHS : STRING;
+      C_OUTPUT_WIDTH : INTEGER;
+      C_OUTPUT_PATH_WIDTHS : STRING;
+      C_ACCUM_OP_PATH_WIDTHS : STRING;
+      C_EXT_MULT_CNFG : STRING;
+      C_DATA_PATH_PSAMP_SRC : STRING;
+      C_OP_PATH_PSAMP_SRC : STRING;
+      C_NUM_MADDS : INTEGER;
+      C_OPT_MADDS : STRING;
+      C_OVERSAMPLING_RATE : INTEGER;
+      C_INPUT_RATE : INTEGER;
+      C_OUTPUT_RATE : INTEGER;
+      C_DATA_MEMTYPE : INTEGER;
+      C_COEF_MEMTYPE : INTEGER;
+      C_IPBUFF_MEMTYPE : INTEGER;
+      C_OPBUFF_MEMTYPE : INTEGER;
+      C_DATAPATH_MEMTYPE : INTEGER;
+      C_MEM_ARRANGEMENT : INTEGER;
+      C_DATA_MEM_PACKING : INTEGER;
+      C_COEF_MEM_PACKING : INTEGER;
+      C_FILTS_PACKED : INTEGER;
+      C_LATENCY : INTEGER;
+      C_HAS_ARESETn : INTEGER;
+      C_HAS_ACLKEN : INTEGER;
+      C_DATA_HAS_TLAST : INTEGER;
+      C_S_DATA_HAS_FIFO : INTEGER;
+      C_S_DATA_HAS_TUSER : INTEGER;
+      C_S_DATA_TDATA_WIDTH : INTEGER;
+      C_S_DATA_TUSER_WIDTH : INTEGER;
+      C_M_DATA_HAS_TREADY : INTEGER;
+      C_M_DATA_HAS_TUSER : INTEGER;
+      C_M_DATA_TDATA_WIDTH : INTEGER;
+      C_M_DATA_TUSER_WIDTH : INTEGER;
+      C_HAS_CONFIG_CHANNEL : INTEGER;
+      C_CONFIG_SYNC_MODE : INTEGER;
+      C_CONFIG_PACKET_SIZE : INTEGER;
+      C_CONFIG_TDATA_WIDTH : INTEGER;
+      C_RELOAD_TDATA_WIDTH : INTEGER
+    );
+    PORT (
+      aresetn : IN STD_LOGIC;
+      aclk : IN STD_LOGIC;
+      aclken : IN STD_LOGIC;
+      s_axis_data_tvalid : IN STD_LOGIC;
+      s_axis_data_tready : OUT STD_LOGIC;
+      s_axis_data_tlast : IN STD_LOGIC;
+      s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+      s_axis_config_tvalid : IN STD_LOGIC;
+      s_axis_config_tready : OUT STD_LOGIC;
+      s_axis_config_tlast : IN STD_LOGIC;
+      s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      s_axis_reload_tvalid : IN STD_LOGIC;
+      s_axis_reload_tready : OUT STD_LOGIC;
+      s_axis_reload_tlast : IN STD_LOGIC;
+      s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      m_axis_data_tvalid : OUT STD_LOGIC;
+      m_axis_data_tready : IN STD_LOGIC;
+      m_axis_data_tlast : OUT STD_LOGIC;
+      m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      m_axis_data_tdata : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
+      event_s_data_tlast_missing : OUT STD_LOGIC;
+      event_s_data_tlast_unexpected : OUT STD_LOGIC;
+      event_s_data_chanid_incorrect : OUT STD_LOGIC;
+      event_s_config_tlast_missing : OUT STD_LOGIC;
+      event_s_config_tlast_unexpected : OUT STD_LOGIC;
+      event_s_reload_tlast_missing : OUT STD_LOGIC;
+      event_s_reload_tlast_unexpected : OUT STD_LOGIC
+    );
+  END COMPONENT fir_compiler_v7_2_12;
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_DATA, TDATA_NUM_BYTES 3, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_data_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_DATA, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF aresetn: SIGNAL IS "XIL_INTERFACENAME aresetn_intf, POLARITY ACTIVE_LOW, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 aresetn_intf RST";
+BEGIN
+  U0 : fir_compiler_v7_2_12
+    GENERIC MAP (
+      C_XDEVICEFAMILY => "zynq",
+      C_ELABORATION_DIR => "./",
+      C_COMPONENT_NAME => "fir_prbs10_invert_rep2",
+      C_COEF_FILE => "fir_prbs10_invert_rep2.mif",
+      C_COEF_FILE_LINES => 2048,
+      C_FILTER_TYPE => 0,
+      C_INTERP_RATE => 1,
+      C_DECIM_RATE => 1,
+      C_ZERO_PACKING_FACTOR => 1,
+      C_SYMMETRY => 0,
+      C_NUM_FILTS => 1,
+      C_NUM_TAPS => 2048,
+      C_NUM_CHANNELS => 1,
+      C_CHANNEL_PATTERN => "fixed",
+      C_ROUND_MODE => 0,
+      C_COEF_RELOAD => 0,
+      C_NUM_RELOAD_SLOTS => 1,
+      C_COL_MODE => 1,
+      C_COL_PIPE_LEN => 4,
+      C_COL_CONFIG => "128",
+      C_OPTIMIZATION => 0,
+      C_DATA_PATH_WIDTHS => "12",
+      C_DATA_IP_PATH_WIDTHS => "12",
+      C_DATA_PX_PATH_WIDTHS => "12",
+      C_DATA_WIDTH => 12,
+      C_COEF_PATH_WIDTHS => "2",
+      C_COEF_WIDTH => 2,
+      C_DATA_PATH_SRC => "0",
+      C_COEF_PATH_SRC => "0",
+      C_PX_PATH_SRC => "0",
+      C_DATA_PATH_SIGN => "0",
+      C_COEF_PATH_SIGN => "0",
+      C_ACCUM_PATH_WIDTHS => "23",
+      C_OUTPUT_WIDTH => 23,
+      C_OUTPUT_PATH_WIDTHS => "23",
+      C_ACCUM_OP_PATH_WIDTHS => "23",
+      C_EXT_MULT_CNFG => "none",
+      C_DATA_PATH_PSAMP_SRC => "0",
+      C_OP_PATH_PSAMP_SRC => "0",
+      C_NUM_MADDS => 128,
+      C_OPT_MADDS => "none",
+      C_OVERSAMPLING_RATE => 16,
+      C_INPUT_RATE => 16,
+      C_OUTPUT_RATE => 16,
+      C_DATA_MEMTYPE => 0,
+      C_COEF_MEMTYPE => 2,
+      C_IPBUFF_MEMTYPE => 0,
+      C_OPBUFF_MEMTYPE => 0,
+      C_DATAPATH_MEMTYPE => 0,
+      C_MEM_ARRANGEMENT => 0,
+      C_DATA_MEM_PACKING => 0,
+      C_COEF_MEM_PACKING => 0,
+      C_FILTS_PACKED => 0,
+      C_LATENCY => 151,
+      C_HAS_ARESETn => 1,
+      C_HAS_ACLKEN => 0,
+      C_DATA_HAS_TLAST => 0,
+      C_S_DATA_HAS_FIFO => 0,
+      C_S_DATA_HAS_TUSER => 0,
+      C_S_DATA_TDATA_WIDTH => 16,
+      C_S_DATA_TUSER_WIDTH => 1,
+      C_M_DATA_HAS_TREADY => 0,
+      C_M_DATA_HAS_TUSER => 0,
+      C_M_DATA_TDATA_WIDTH => 24,
+      C_M_DATA_TUSER_WIDTH => 1,
+      C_HAS_CONFIG_CHANNEL => 0,
+      C_CONFIG_SYNC_MODE => 0,
+      C_CONFIG_PACKET_SIZE => 0,
+      C_CONFIG_TDATA_WIDTH => 1,
+      C_RELOAD_TDATA_WIDTH => 1
+    )
+    PORT MAP (
+      aresetn => aresetn,
+      aclk => aclk,
+      aclken => '1',
+      s_axis_data_tvalid => s_axis_data_tvalid,
+      s_axis_data_tready => s_axis_data_tready,
+      s_axis_data_tlast => '0',
+      s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      s_axis_data_tdata => s_axis_data_tdata,
+      s_axis_config_tvalid => '0',
+      s_axis_config_tlast => '0',
+      s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      s_axis_reload_tvalid => '0',
+      s_axis_reload_tlast => '0',
+      s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      m_axis_data_tvalid => m_axis_data_tvalid,
+      m_axis_data_tready => '1',
+      m_axis_data_tdata => m_axis_data_tdata
+    );
+END fir_prbs10_invert_rep2_arch;

projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_freq_comp/ila_freq_comp.veo

@@ -66,21 +66,18 @@ ila_freq_comp your_instance_name (
 	.probe6(probe6), // input wire [17:0]  probe6 
 	.probe7(probe7), // input wire [17:0]  probe7 
 	.probe8(probe8), // input wire [17:0]  probe8 
-	.probe9(probe9), // input wire [7:0]  probe9 
-	.probe10(probe10), // input wire [7:0]  probe10 
-	.probe11(probe11), // input wire [7:0]  probe11 
-	.probe12(probe12), // input wire [7:0]  probe12 
+	.probe9(probe9), // input wire [10:0]  probe9 
+	.probe10(probe10), // input wire [10:0]  probe10 
+	.probe11(probe11), // input wire [10:0]  probe11 
+	.probe12(probe12), // input wire [10:0]  probe12 
 	.probe13(probe13), // input wire [0:0]  probe13 
 	.probe14(probe14), // input wire [2:0]  probe14 
 	.probe15(probe15), // input wire [11:0]  probe15 
 	.probe16(probe16), // input wire [11:0]  probe16 
 	.probe17(probe17), // input wire [17:0]  probe17 
 	.probe18(probe18), // input wire [17:0]  probe18 
-	.probe19(probe19), // input wire [17:0]  probe19 
-	.probe20(probe20), // input wire [17:0]  probe20 
-	.probe21(probe21), // input wire [17:0]  probe21 
-	.probe22(probe22), // input wire [31:0]  probe22 
-	.probe23(probe23) // input wire [11:0]  probe23
+	.probe19(probe19), // input wire [31:0]  probe19 
+	.probe20(probe20) // input wire [11:0]  probe20
 );
 
 // INST_TAG_END ------ End INSTANTIATION Template ---------

projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_freq_comp/ila_freq_comp_stub.v

@@ -1,7 +1,7 @@
 // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 // --------------------------------------------------------------------------------
 // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
-// Date        : Tue May  9 13:39:41 2023
+// Date        : Fri May 12 09:36:40 2023
 // Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
 // Command     : write_verilog -force -mode synth_stub
 //               /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_stub.v
@@ -16,8 +16,8 @@
 (* X_CORE_INFO = "ila,Vivado 2019.1.3" *)
 module ila_freq_comp(clk, probe0, probe1, probe2, probe3, probe4, probe5, 
   probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17, 
-  probe18, probe19, probe20, probe21, probe22, probe23)
-/* synthesis syn_black_box black_box_pad_pin="clk,probe0[0:0],probe1[17:0],probe2[17:0],probe3[17:0],probe4[17:0],probe5[17:0],probe6[17:0],probe7[17:0],probe8[17:0],probe9[7:0],probe10[7:0],probe11[7:0],probe12[7:0],probe13[0:0],probe14[2:0],probe15[11:0],probe16[11:0],probe17[17:0],probe18[17:0],probe19[17:0],probe20[17:0],probe21[17:0],probe22[31:0],probe23[11:0]" */;
+  probe18, probe19, probe20)
+/* synthesis syn_black_box black_box_pad_pin="clk,probe0[0:0],probe1[17:0],probe2[17:0],probe3[17:0],probe4[17:0],probe5[17:0],probe6[17:0],probe7[17:0],probe8[17:0],probe9[10:0],probe10[10:0],probe11[10:0],probe12[10:0],probe13[0:0],probe14[2:0],probe15[11:0],probe16[11:0],probe17[17:0],probe18[17:0],probe19[31:0],probe20[11:0]" */;
   input clk;
   input [0:0]probe0;
   input [17:0]probe1;
@@ -28,19 +28,16 @@ module ila_freq_comp(clk, probe0, probe1, probe2, probe3, probe4, probe5,
   input [17:0]probe6;
   input [17:0]probe7;
   input [17:0]probe8;
-  input [7:0]probe9;
-  input [7:0]probe10;
-  input [7:0]probe11;
-  input [7:0]probe12;
+  input [10:0]probe9;
+  input [10:0]probe10;
+  input [10:0]probe11;
+  input [10:0]probe12;
   input [0:0]probe13;
   input [2:0]probe14;
   input [11:0]probe15;
   input [11:0]probe16;
   input [17:0]probe17;
   input [17:0]probe18;
-  input [17:0]probe19;
-  input [17:0]probe20;
-  input [17:0]probe21;
-  input [31:0]probe22;
-  input [11:0]probe23;
+  input [31:0]probe19;
+  input [11:0]probe20;
 endmodule

projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_freq_comp/ila_freq_comp_stub.vhdl

@@ -1,7 +1,7 @@
 -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 -- --------------------------------------------------------------------------------
 -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
--- Date        : Tue May  9 13:39:41 2023
+-- Date        : Fri May 12 09:36:40 2023
 -- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
 -- Command     : write_vhdl -force -mode synth_stub
 --               /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_freq_comp_synth_1/ila_freq_comp_stub.vhdl
@@ -24,21 +24,18 @@ entity ila_freq_comp is
     probe6 : in STD_LOGIC_VECTOR ( 17 downto 0 );
     probe7 : in STD_LOGIC_VECTOR ( 17 downto 0 );
     probe8 : in STD_LOGIC_VECTOR ( 17 downto 0 );
-    probe9 : in STD_LOGIC_VECTOR ( 7 downto 0 );
-    probe10 : in STD_LOGIC_VECTOR ( 7 downto 0 );
-    probe11 : in STD_LOGIC_VECTOR ( 7 downto 0 );
-    probe12 : in STD_LOGIC_VECTOR ( 7 downto 0 );
+    probe9 : in STD_LOGIC_VECTOR ( 10 downto 0 );
+    probe10 : in STD_LOGIC_VECTOR ( 10 downto 0 );
+    probe11 : in STD_LOGIC_VECTOR ( 10 downto 0 );
+    probe12 : in STD_LOGIC_VECTOR ( 10 downto 0 );
     probe13 : in STD_LOGIC_VECTOR ( 0 to 0 );
     probe14 : in STD_LOGIC_VECTOR ( 2 downto 0 );
     probe15 : in STD_LOGIC_VECTOR ( 11 downto 0 );
     probe16 : in STD_LOGIC_VECTOR ( 11 downto 0 );
     probe17 : in STD_LOGIC_VECTOR ( 17 downto 0 );
     probe18 : in STD_LOGIC_VECTOR ( 17 downto 0 );
-    probe19 : in STD_LOGIC_VECTOR ( 17 downto 0 );
-    probe20 : in STD_LOGIC_VECTOR ( 17 downto 0 );
-    probe21 : in STD_LOGIC_VECTOR ( 17 downto 0 );
-    probe22 : in STD_LOGIC_VECTOR ( 31 downto 0 );
-    probe23 : in STD_LOGIC_VECTOR ( 11 downto 0 )
+    probe19 : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    probe20 : in STD_LOGIC_VECTOR ( 11 downto 0 )
   );
 
 end ila_freq_comp;
@@ -47,7 +44,7 @@ architecture stub of ila_freq_comp is
 attribute syn_black_box : boolean;
 attribute black_box_pad_pin : string;
 attribute syn_black_box of stub : architecture is true;
-attribute black_box_pad_pin of stub : architecture is "clk,probe0[0:0],probe1[17:0],probe2[17:0],probe3[17:0],probe4[17:0],probe5[17:0],probe6[17:0],probe7[17:0],probe8[17:0],probe9[7:0],probe10[7:0],probe11[7:0],probe12[7:0],probe13[0:0],probe14[2:0],probe15[11:0],probe16[11:0],probe17[17:0],probe18[17:0],probe19[17:0],probe20[17:0],probe21[17:0],probe22[31:0],probe23[11:0]";
+attribute black_box_pad_pin of stub : architecture is "clk,probe0[0:0],probe1[17:0],probe2[17:0],probe3[17:0],probe4[17:0],probe5[17:0],probe6[17:0],probe7[17:0],probe8[17:0],probe9[10:0],probe10[10:0],probe11[10:0],probe12[10:0],probe13[0:0],probe14[2:0],probe15[11:0],probe16[11:0],probe17[17:0],probe18[17:0],probe19[31:0],probe20[11:0]";
 attribute X_CORE_INFO : string;
 attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3";
 begin

projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_freq_comp/sim/ila_freq_comp.v

@@ -70,10 +70,7 @@ probe16,
 probe17,
 probe18,
 probe19,
-probe20,
-probe21,
-probe22,
-probe23
+probe20
 );
 
 input clk;
@@ -88,21 +85,18 @@ input [17 : 0] probe5;
 input [17 : 0] probe6;
 input [17 : 0] probe7;
 input [17 : 0] probe8;
-input [7 : 0] probe9;
-input [7 : 0] probe10;
-input [7 : 0] probe11;
-input [7 : 0] probe12;
+input [10 : 0] probe9;
+input [10 : 0] probe10;
+input [10 : 0] probe11;
+input [10 : 0] probe12;
 input [0 : 0] probe13;
 input [2 : 0] probe14;
 input [11 : 0] probe15;
 input [11 : 0] probe16;
 input [17 : 0] probe17;
 input [17 : 0] probe18;
-input [17 : 0] probe19;
-input [17 : 0] probe20;
-input [17 : 0] probe21;
-input [31 : 0] probe22;
-input [11 : 0] probe23;
+input [31 : 0] probe19;
+input [11 : 0] probe20;
 
 
 endmodule

projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt.veo

@@ -66,7 +66,7 @@ ila_rx_data_cnt your_instance_name (
 	.probe6(probe6), // input wire [11:0]  probe6 
 	.probe7(probe7), // input wire [11:0]  probe7 
 	.probe8(probe8), // input wire [11:0]  probe8 
-	.probe9(probe9) // input wire [9:0]  probe9
+	.probe9(probe9) // input wire [12:0]  probe9
 );
 
 // INST_TAG_END ------ End INSTANTIATION Template ---------

projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_stub.v

@@ -1,7 +1,7 @@
 // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 // --------------------------------------------------------------------------------
 // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
-// Date        : Wed May 10 18:23:01 2023
+// Date        : Fri May 12 10:13:05 2023
 // Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
 // Command     : write_verilog -force -mode synth_stub
 //               /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.v
@@ -16,7 +16,7 @@
 (* X_CORE_INFO = "ila,Vivado 2019.1.3" *)
 module ila_rx_data_cnt(clk, probe0, probe1, probe2, probe3, probe4, probe5, 
   probe6, probe7, probe8, probe9)
-/* synthesis syn_black_box black_box_pad_pin="clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0],probe8[11:0],probe9[9:0]" */;
+/* synthesis syn_black_box black_box_pad_pin="clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0],probe8[11:0],probe9[12:0]" */;
   input clk;
   input [11:0]probe0;
   input [11:0]probe1;
@@ -27,5 +27,5 @@ module ila_rx_data_cnt(clk, probe0, probe1, probe2, probe3, probe4, probe5,
   input [11:0]probe6;
   input [11:0]probe7;
   input [11:0]probe8;
-  input [9:0]probe9;
+  input [12:0]probe9;
 endmodule

projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/ila_rx_data_cnt_stub.vhdl

@@ -1,7 +1,7 @@
 -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 -- --------------------------------------------------------------------------------
 -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
--- Date        : Wed May 10 18:23:01 2023
+-- Date        : Fri May 12 10:13:05 2023
 -- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
 -- Command     : write_vhdl -force -mode synth_stub
 --               /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/ila_rx_data_cnt_synth_1/ila_rx_data_cnt_stub.vhdl
@@ -24,7 +24,7 @@ entity ila_rx_data_cnt is
     probe6 : in STD_LOGIC_VECTOR ( 11 downto 0 );
     probe7 : in STD_LOGIC_VECTOR ( 11 downto 0 );
     probe8 : in STD_LOGIC_VECTOR ( 11 downto 0 );
-    probe9 : in STD_LOGIC_VECTOR ( 9 downto 0 )
+    probe9 : in STD_LOGIC_VECTOR ( 12 downto 0 )
   );
 
 end ila_rx_data_cnt;
@@ -33,7 +33,7 @@ architecture stub of ila_rx_data_cnt is
 attribute syn_black_box : boolean;
 attribute black_box_pad_pin : string;
 attribute syn_black_box of stub : architecture is true;
-attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0],probe8[11:0],probe9[9:0]";
+attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[11:0],probe2[11:0],probe3[11:0],probe4[11:0],probe5[11:0],probe6[11:0],probe7[11:0],probe8[11:0],probe9[12:0]";
 attribute X_CORE_INFO : string;
 attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3";
 begin

projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/ila_rx_data_cnt/sim/ila_rx_data_cnt.v

@@ -74,7 +74,7 @@ input [11 : 0] probe5;
 input [11 : 0] probe6;
 input [11 : 0] probe7;
 input [11 : 0] probe8;
-input [9 : 0] probe9;
+input [12 : 0] probe9;
 
 
 endmodule

projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/sim/vio_freq_comp.v

@@ -53,7 +53,8 @@ probe_out0,
 probe_out1,
 probe_out2,
 probe_out3,
-probe_out4
+probe_out4,
+probe_out5
 );
 
 input clk;
@@ -64,6 +65,7 @@ output reg [7 : 0] probe_out1 = 'h0A ;
 output reg [0 : 0] probe_out2 = 'h0 ;
 output reg [31 : 0] probe_out3 = 'h00000000 ;
 output reg [0 : 0] probe_out4 = 'h0 ;
+output reg [0 : 0] probe_out5 = 'h0 ;
 
 
 endmodule

projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp.veo

@@ -61,7 +61,8 @@ vio_freq_comp your_instance_name (
   .probe_out1(probe_out1),  // output wire [7 : 0] probe_out1
   .probe_out2(probe_out2),  // output wire [0 : 0] probe_out2
   .probe_out3(probe_out3),  // output wire [31 : 0] probe_out3
-  .probe_out4(probe_out4)  // output wire [0 : 0] probe_out4
+  .probe_out4(probe_out4),  // output wire [0 : 0] probe_out4
+  .probe_out5(probe_out5)  // output wire [0 : 0] probe_out5
 );
 // INST_TAG_END ------ End INSTANTIATION Template ---------
 

projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp.vho

@@ -60,7 +60,8 @@ COMPONENT vio_freq_comp
     probe_out1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
     probe_out2 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
     probe_out3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-    probe_out4 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
+    probe_out4 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+    probe_out5 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
   );
 END COMPONENT;
 -- COMP_TAG_END ------ End COMPONENT Declaration ------------
@@ -77,7 +78,8 @@ your_instance_name : vio_freq_comp
     probe_out1 => probe_out1,
     probe_out2 => probe_out2,
     probe_out3 => probe_out3,
-    probe_out4 => probe_out4
+    probe_out4 => probe_out4,
+    probe_out5 => probe_out5
   );
 -- INST_TAG_END ------ End INSTANTIATION Template ---------
 

projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_stub.v

@@ -1,7 +1,7 @@
 // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 // --------------------------------------------------------------------------------
 // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
-// Date        : Wed May 10 18:23:14 2023
+// Date        : Fri May 12 09:41:14 2023
 // Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
 // Command     : write_verilog -force -mode synth_stub
 //               /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.v
@@ -15,8 +15,8 @@
 // Please paste the declaration into a Verilog source file or add the file as an additional source.
 (* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
 module vio_freq_comp(clk, probe_in0, probe_out0, probe_out1, 
-  probe_out2, probe_out3, probe_out4)
-/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_out0[0:0],probe_out1[7:0],probe_out2[0:0],probe_out3[31:0],probe_out4[0:0]" */;
+  probe_out2, probe_out3, probe_out4, probe_out5)
+/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_out0[0:0],probe_out1[7:0],probe_out2[0:0],probe_out3[31:0],probe_out4[0:0],probe_out5[0:0]" */;
   input clk;
   input [0:0]probe_in0;
   output [0:0]probe_out0;
@@ -24,4 +24,5 @@ module vio_freq_comp(clk, probe_in0, probe_out0, probe_out1,
   output [0:0]probe_out2;
   output [31:0]probe_out3;
   output [0:0]probe_out4;
+  output [0:0]probe_out5;
 endmodule

projects/duifei/duifei_online_acq_par/ip/ip_user_files/ip/vio_freq_comp/vio_freq_comp_stub.vhdl

@@ -1,7 +1,7 @@
 -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
 -- --------------------------------------------------------------------------------
 -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep  4 09:44:18 MDT 2019
--- Date        : Wed May 10 18:23:14 2023
+-- Date        : Fri May 12 09:41:14 2023
 -- Host        : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
 -- Command     : write_vhdl -force -mode synth_stub
 --               /home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.runs/vio_freq_comp_synth_1/vio_freq_comp_stub.vhdl
@@ -20,7 +20,8 @@ entity vio_freq_comp is
     probe_out1 : out STD_LOGIC_VECTOR ( 7 downto 0 );
     probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 );
     probe_out3 : out STD_LOGIC_VECTOR ( 31 downto 0 );
-    probe_out4 : out STD_LOGIC_VECTOR ( 0 to 0 )
+    probe_out4 : out STD_LOGIC_VECTOR ( 0 to 0 );
+    probe_out5 : out STD_LOGIC_VECTOR ( 0 to 0 )
   );
 
 end vio_freq_comp;
@@ -29,7 +30,7 @@ architecture stub of vio_freq_comp is
 attribute syn_black_box : boolean;
 attribute black_box_pad_pin : string;
 attribute syn_black_box of stub : architecture is true;
-attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[0:0],probe_out0[0:0],probe_out1[7:0],probe_out2[0:0],probe_out3[31:0],probe_out4[0:0]";
+attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[0:0],probe_out0[0:0],probe_out1[7:0],probe_out2[0:0],probe_out3[31:0],probe_out4[0:0],probe_out5[0:0]";
 attribute X_CORE_INFO : string;
 attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
 begin

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/README.txt

@@ -0,0 +1,83 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required
+#             to simulate the design for a simulator, the directory structure
+#             and the generated exported files.
+#
+################################################################################
+
+1. Simulate Design
+
+To simulate design, cd to the simulator directory and execute the script.
+
+For example:-
+
+% cd questa
+% ./top.sh
+
+The export simulation flow requires the Xilinx pre-compiled simulation library
+components for the target simulator. These components are referred using the
+'-lib_map_path' switch. If this switch is specified, then the export simulation
+will automatically set this library path in the generated script and update,
+copy the simulator setup file(s) in the exported directory.
+
+If '-lib_map_path' is not specified, then the pre-compiled simulation library
+information will not be included in the exported scripts and that may cause
+simulation errors when running this script. Alternatively, you can provide the
+library information using this switch while executing the generated script.
+
+For example:-
+
+% ./top.sh -lib_map_path /design/questa/clibs
+
+Please refer to the generated script header 'Prerequisite' section for more details.
+
+2. Directory Structure
+
+By default, if the -directory switch is not specified, export_simulation will
+create the following directory structure:-
+
+<current_working_directory>/export_sim/<simulator>
+
+For example, if the current working directory is /tmp/test, export_simulation
+will create the following directory path:-
+
+/tmp/test/export_sim/questa
+
+If -directory switch is specified, export_simulation will create a simulator
+sub-directory under the specified directory path.
+
+For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
+command will create the following directory:-
+
+/tmp/test/my_test_area/func_sim/questa
+
+By default, if -simulator is not specified, export_simulation will create a
+simulator sub-directory for each simulator and export the files for each simulator
+in this sub-directory respectively.
+
+IMPORTANT: Please note that the simulation library path must be specified manually
+in the generated script for the respective simulator. Please refer to the generated
+script header 'Prerequisite' section for more details.
+
+3. Exported script and files
+
+Export simulation will create the driver shell script, setup files and copy the
+design sources in the output directory path.
+
+By default, when the -script_name switch is not specified, export_simulation will
+create the following script name:-
+
+<simulation_top>.sh  (Unix)
+When exporting the files for an IP using the -of_objects switch, export_simulation
+will create the following script name:-
+
+<ip-name>.sh  (Unix)
+Export simulation will create the setup files for the target simulator specified
+with the -simulator switch.
+
+For example, if the target simulator is "ies", export_simulation will create the
+'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
+file.
+

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/activehdl/README.txt

@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Thu May 11 21:41:10 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./fifo_rx_data.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './fifo_rx_data.sh' script.
+
+./fifo_rx_data.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./fifo_rx_data.sh -noclean_files
+
+For more information on the script, please type './fifo_rx_data.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/activehdl/compile.do

@@ -0,0 +1,33 @@
+vlib work
+vlib activehdl
+
+vlib activehdl/xil_defaultlib
+vlib activehdl/xpm
+vlib activehdl/fifo_generator_v13_2_4
+
+vmap xil_defaultlib activehdl/xil_defaultlib
+vmap xpm activehdl/xpm
+vmap fifo_generator_v13_2_4 activehdl/fifo_generator_v13_2_4
+
+vlog -work xil_defaultlib  -sv2k12 \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work fifo_generator_v13_2_4  -v2k5 \
+"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \
+
+vcom -work fifo_generator_v13_2_4 -93 \
+"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \
+
+vlog -work fifo_generator_v13_2_4  -v2k5 \
+"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \
+
+vlog -work xil_defaultlib  -v2k5 \
+"../../../ip/fifo_rx_data/sim/fifo_rx_data.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/activehdl/fifo_rx_data.sh

@@ -0,0 +1,152 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : fifo_rx_data.sh
+# Simulator   : Aldec Active-HDL Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Thu May 11 21:41:10 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: fifo_rx_data.sh [-help]
+# usage: fifo_rx_data.sh [-lib_map_path]
+# usage: fifo_rx_data.sh [-noclean_files]
+# usage: fifo_rx_data.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'fifo_rx_data.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "fifo_rx_data.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./fifo_rx_data.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  lib_map_path=""
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./fifo_rx_data.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: fifo_rx_data.sh [-help]\n\
+Usage: fifo_rx_data.sh [-lib_map_path]\n\
+Usage: fifo_rx_data.sh [-reset_run]\n\
+Usage: fifo_rx_data.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/activehdl/file_info.txt

@@ -0,0 +1,8 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/simulation/fifo_generator_vlog_beh.v,
+fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd,
+fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v,
+fifo_rx_data.v,verilog,xil_defaultlib,../../../ip/fifo_rx_data/sim/fifo_rx_data.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/activehdl/glbl.v

@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/activehdl/simulate.do

@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim -t 1ps +access +r +m+fifo_rx_data -L xil_defaultlib -L xpm -L fifo_generator_v13_2_4 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.fifo_rx_data xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {fifo_rx_data.udo}
+
+run -all
+
+endsim
+
+quit -force

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/activehdl/wave.do

@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/ies/README.txt

@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Thu May 11 21:41:10 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./fifo_rx_data.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './fifo_rx_data.sh' script.
+
+./fifo_rx_data.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./fifo_rx_data.sh -noclean_files
+
+For more information on the script, please type './fifo_rx_data.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/ies/fifo_rx_data.sh

@@ -0,0 +1,175 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : fifo_rx_data.sh
+# Simulator   : Cadence Incisive Enterprise Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Thu May 11 21:41:10 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: fifo_rx_data.sh [-help]
+# usage: fifo_rx_data.sh [-lib_map_path]
+# usage: fifo_rx_data.sh [-noclean_files]
+# usage: fifo_rx_data.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'fifo_rx_data.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xil_defaultlib xpm fifo_generator_v13_2_4)
+
+# Simulation root library directory
+sim_lib_dir="ies_lib"
+
+# Script info
+echo -e "fifo_rx_data.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  irun $irun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.fifo_rx_data \
+       -f run.f \
+       -top glbl \
+       glbl.v
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./fifo_rx_data.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./fifo_rx_data.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: fifo_rx_data.sh [-help]\n\
+Usage: fifo_rx_data.sh [-lib_map_path]\n\
+Usage: fifo_rx_data.sh [-reset_run]\n\
+Usage: fifo_rx_data.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/ies/file_info.txt

@@ -0,0 +1,8 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/simulation/fifo_generator_vlog_beh.v,
+fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd,
+fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v,
+fifo_rx_data.v,verilog,xil_defaultlib,../../../ip/fifo_rx_data/sim/fifo_rx_data.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/ies/glbl.v

@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/ies/run.f

@@ -0,0 +1,23 @@
+-makelib ies_lib/xil_defaultlib -sv \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+-endlib
+-makelib ies_lib/xpm \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib ies_lib/fifo_generator_v13_2_4 \
+  "../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \
+-endlib
+-makelib ies_lib/fifo_generator_v13_2_4 \
+  "../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \
+-endlib
+-makelib ies_lib/fifo_generator_v13_2_4 \
+  "../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  "../../../ip/fifo_rx_data/sim/fifo_rx_data.v" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+  glbl.v
+-endlib
+

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/modelsim/README.txt

@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Thu May 11 21:41:10 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./fifo_rx_data.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './fifo_rx_data.sh' script.
+
+./fifo_rx_data.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./fifo_rx_data.sh -noclean_files
+
+For more information on the script, please type './fifo_rx_data.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/modelsim/compile.do

@@ -0,0 +1,14 @@
+vlib modelsim_lib/work
+vlib modelsim_lib/msim
+
+vlib modelsim_lib/msim/xil_defaultlib
+
+vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
+
+vlog -work xil_defaultlib -64 -incr \
+"../../../ip/fifo_rx_data/sim/fifo_rx_data.v" \
+
+
+vlog -work xil_defaultlib \
+"glbl.v"
+

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/modelsim/fifo_rx_data.sh

@@ -0,0 +1,167 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : fifo_rx_data.sh
+# Simulator   : Mentor Graphics ModelSim Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Thu May 11 21:41:10 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: fifo_rx_data.sh [-help]
+# usage: fifo_rx_data.sh [-lib_map_path]
+# usage: fifo_rx_data.sh [-noclean_files]
+# usage: fifo_rx_data.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'fifo_rx_data.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "fifo_rx_data.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./fifo_rx_data.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/josh/Software/Xilinx/CompLib/Model/2019.1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="modelsim_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./fifo_rx_data.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: fifo_rx_data.sh [-help]\n\
+Usage: fifo_rx_data.sh [-lib_map_path]\n\
+Usage: fifo_rx_data.sh [-reset_run]\n\
+Usage: fifo_rx_data.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/modelsim/file_info.txt

@@ -0,0 +1,2 @@
+fifo_rx_data.v,verilog,xil_defaultlib,../../../ip/fifo_rx_data/sim/fifo_rx_data.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/modelsim/glbl.v

@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/modelsim/simulate.do

@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -voptargs="+acc" -t 1ps -L fifo_generator_v13_2_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.fifo_rx_data xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {fifo_rx_data.udo}
+
+run -all
+
+quit -force

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/modelsim/wave.do

@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/questa/README.txt

@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Thu May 11 21:41:10 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./fifo_rx_data.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './fifo_rx_data.sh' script.
+
+./fifo_rx_data.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./fifo_rx_data.sh -noclean_files
+
+For more information on the script, please type './fifo_rx_data.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/questa/compile.do

@@ -0,0 +1,33 @@
+vlib questa_lib/work
+vlib questa_lib/msim
+
+vlib questa_lib/msim/xil_defaultlib
+vlib questa_lib/msim/xpm
+vlib questa_lib/msim/fifo_generator_v13_2_4
+
+vmap xil_defaultlib questa_lib/msim/xil_defaultlib
+vmap xpm questa_lib/msim/xpm
+vmap fifo_generator_v13_2_4 questa_lib/msim/fifo_generator_v13_2_4
+
+vlog -work xil_defaultlib -64 -sv \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -64 -93 \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work fifo_generator_v13_2_4 -64 \
+"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \
+
+vcom -work fifo_generator_v13_2_4 -64 -93 \
+"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \
+
+vlog -work fifo_generator_v13_2_4 -64 \
+"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \
+
+vlog -work xil_defaultlib -64 \
+"../../../ip/fifo_rx_data/sim/fifo_rx_data.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/questa/elaborate.do

@@ -0,0 +1 @@
+vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L fifo_generator_v13_2_4 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.fifo_rx_data xil_defaultlib.glbl -o fifo_rx_data_opt

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/questa/fifo_rx_data.sh

@@ -0,0 +1,174 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : fifo_rx_data.sh
+# Simulator   : Mentor Graphics Questa Advanced Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Thu May 11 21:41:10 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: fifo_rx_data.sh [-help]
+# usage: fifo_rx_data.sh [-lib_map_path]
+# usage: fifo_rx_data.sh [-noclean_files]
+# usage: fifo_rx_data.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'fifo_rx_data.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "fifo_rx_data.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  source elaborate.do 2>&1 | tee -a elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./fifo_rx_data.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+  file="modelsim.ini"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    cp $src_file .
+  fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+  lib_dir="questa_lib"
+  if [[ -e $lib_dir ]]; then
+    rm -rf $lib_dir
+  fi
+
+  mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./fifo_rx_data.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: fifo_rx_data.sh [-help]\n\
+Usage: fifo_rx_data.sh [-lib_map_path]\n\
+Usage: fifo_rx_data.sh [-reset_run]\n\
+Usage: fifo_rx_data.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/questa/file_info.txt

@@ -0,0 +1,8 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/simulation/fifo_generator_vlog_beh.v,
+fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd,
+fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v,
+fifo_rx_data.v,verilog,xil_defaultlib,../../../ip/fifo_rx_data/sim/fifo_rx_data.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/questa/glbl.v

@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/questa/simulate.do

@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -t 1ps -lib xil_defaultlib fifo_rx_data_opt
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {fifo_rx_data.udo}
+
+run -all
+
+quit -force

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/questa/wave.do

@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/riviera/README.txt

@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Thu May 11 21:41:10 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./fifo_rx_data.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './fifo_rx_data.sh' script.
+
+./fifo_rx_data.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./fifo_rx_data.sh -noclean_files
+
+For more information on the script, please type './fifo_rx_data.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/riviera/compile.do

@@ -0,0 +1,33 @@
+vlib work
+vlib riviera
+
+vlib riviera/xil_defaultlib
+vlib riviera/xpm
+vlib riviera/fifo_generator_v13_2_4
+
+vmap xil_defaultlib riviera/xil_defaultlib
+vmap xpm riviera/xpm
+vmap fifo_generator_v13_2_4 riviera/fifo_generator_v13_2_4
+
+vlog -work xil_defaultlib  -sv2k12 \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+
+vcom -work xpm -93 \
+"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work fifo_generator_v13_2_4  -v2k5 \
+"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \
+
+vcom -work fifo_generator_v13_2_4 -93 \
+"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \
+
+vlog -work fifo_generator_v13_2_4  -v2k5 \
+"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \
+
+vlog -work xil_defaultlib  -v2k5 \
+"../../../ip/fifo_rx_data/sim/fifo_rx_data.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/riviera/fifo_rx_data.sh

@@ -0,0 +1,153 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : fifo_rx_data.sh
+# Simulator   : Aldec Riviera-PRO Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Thu May 11 21:41:10 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: fifo_rx_data.sh [-help]
+# usage: fifo_rx_data.sh [-lib_map_path]
+# usage: fifo_rx_data.sh [-noclean_files]
+# usage: fifo_rx_data.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'fifo_rx_data.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "fifo_rx_data.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./fifo_rx_data.sh -help\" for more information)\n"
+        exit 1
+      fi
+     map_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     map_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+  file="library.cfg"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/josh/Workspace/vivado-git/projects/duifei/duifei_online_acq_par/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      vmap -link $lib_map_path
+    fi
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./fifo_rx_data.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: fifo_rx_data.sh [-help]\n\
+Usage: fifo_rx_data.sh [-lib_map_path]\n\
+Usage: fifo_rx_data.sh [-reset_run]\n\
+Usage: fifo_rx_data.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/riviera/file_info.txt

@@ -0,0 +1,8 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/simulation/fifo_generator_vlog_beh.v,
+fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd,
+fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v,
+fifo_rx_data.v,verilog,xil_defaultlib,../../../ip/fifo_rx_data/sim/fifo_rx_data.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/riviera/glbl.v

@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/riviera/simulate.do

@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim -t 1ps +access +r +m+fifo_rx_data -L xil_defaultlib -L xpm -L fifo_generator_v13_2_4 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.fifo_rx_data xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {fifo_rx_data.udo}
+
+run -all
+
+endsim
+
+quit -force

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/riviera/wave.do

@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/vcs/README.txt

@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Thu May 11 21:41:10 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./fifo_rx_data.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './fifo_rx_data.sh' script.
+
+./fifo_rx_data.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./fifo_rx_data.sh -noclean_files
+
+For more information on the script, please type './fifo_rx_data.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/vcs/fifo_rx_data.sh

@@ -0,0 +1,221 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : fifo_rx_data.sh
+# Simulator   : Synopsys Verilog Compiler Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Thu May 11 21:41:10 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: fifo_rx_data.sh [-help]
+# usage: fifo_rx_data.sh [-lib_map_path]
+# usage: fifo_rx_data.sh [-noclean_files]
+# usage: fifo_rx_data.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'fifo_rx_data.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Command line options
+vlogan_opts="-full64"
+vhdlan_opts="-full64"
+vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log"
+vcs_sim_opts="-ucli -licqueue -l simulate.log"
+
+# Design libraries
+design_libs=(xil_defaultlib)
+
+# Simulation root library directory
+sim_lib_dir="vcs_lib"
+
+# Script info
+echo -e "fifo_rx_data.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  vlogan -work xil_defaultlib $vlogan_opts +v2k \
+    "$ref_dir/../../../ip/fifo_rx_data/sim/fifo_rx_data.v" \
+  2>&1 | tee -a vlogan.log
+
+
+  vlogan -work xil_defaultlib $vlogan_opts +v2k \
+    glbl.v \
+  2>&1 | tee -a vlogan.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  vcs $vcs_elab_opts xil_defaultlib.fifo_rx_data xil_defaultlib.glbl -o fifo_rx_data_simv
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  ./fifo_rx_data_simv $vcs_sim_opts -do simulate.do
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./fifo_rx_data.sh -help\" for more information)\n"
+        exit 1
+      fi
+      create_lib_mappings $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+      create_lib_mappings $2
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Define design library mappings
+create_lib_mappings()
+{
+  file="synopsys_sim.setup"
+  if [[ -e $file ]]; then
+    if [[ ($1 == "") ]]; then
+      return
+    else
+      rm -rf $file
+    fi
+  fi
+
+  touch $file
+
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  else
+    lib_map_path="/home/josh/Software/Xilinx/CompLib/VCS/2019.1"
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    mapping="$lib:$sim_lib_dir/$lib"
+    echo $mapping >> $file
+  done
+
+  if [[ ($lib_map_path != "") ]]; then
+    incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup"
+    echo $incl_ref >> $file
+  fi
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(ucli.key fifo_rx_data_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc fifo_rx_data_simv.daidir)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./fifo_rx_data.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: fifo_rx_data.sh [-help]\n\
+Usage: fifo_rx_data.sh [-lib_map_path]\n\
+Usage: fifo_rx_data.sh [-reset_run]\n\
+Usage: fifo_rx_data.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/vcs/file_info.txt

@@ -0,0 +1,2 @@
+fifo_rx_data.v,verilog,xil_defaultlib,../../../ip/fifo_rx_data/sim/fifo_rx_data.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/vcs/glbl.v

@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/vcs/simulate.do

@@ -0,0 +1,2 @@
+run
+quit

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/xcelium/README.txt

@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Thu May 11 21:41:10 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./fifo_rx_data.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './fifo_rx_data.sh' script.
+
+./fifo_rx_data.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./fifo_rx_data.sh -noclean_files
+
+For more information on the script, please type './fifo_rx_data.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/xcelium/fifo_rx_data.sh

@@ -0,0 +1,175 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : fifo_rx_data.sh
+# Simulator   : Cadence Xcelium Parallel Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Thu May 11 21:41:10 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: fifo_rx_data.sh [-help]
+# usage: fifo_rx_data.sh [-lib_map_path]
+# usage: fifo_rx_data.sh [-noclean_files]
+# usage: fifo_rx_data.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'fifo_rx_data.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+  ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xil_defaultlib xpm fifo_generator_v13_2_4)
+
+# Simulation root library directory
+sim_lib_dir="xcelium_lib"
+
+# Script info
+echo -e "fifo_rx_data.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+  xrun $xrun_opts \
+       -reflib "$ref_lib_dir/unisim:unisim" \
+       -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+       -reflib "$ref_lib_dir/secureip:secureip" \
+       -reflib "$ref_lib_dir/unimacro:unimacro" \
+       -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+       -top xil_defaultlib.fifo_rx_data \
+       -f run.f \
+       -top glbl \
+       glbl.v
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./fifo_rx_data.sh -help\" for more information)\n"
+        exit 1
+      else
+        ref_lib_dir=$2
+      fi
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+  esac
+
+  create_lib_dir
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+  if [[ -e $sim_lib_dir ]]; then
+    rm -rf $sim_lib_dir
+  fi
+
+  for (( i=0; i<${#design_libs[*]}; i++ )); do
+    lib="${design_libs[i]}"
+    lib_dir="$sim_lib_dir/$lib"
+    if [[ ! -e $lib_dir ]]; then
+      mkdir -p $lib_dir
+    fi
+  done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+
+  create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./fifo_rx_data.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: fifo_rx_data.sh [-help]\n\
+Usage: fifo_rx_data.sh [-lib_map_path]\n\
+Usage: fifo_rx_data.sh [-reset_run]\n\
+Usage: fifo_rx_data.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/xcelium/file_info.txt

@@ -0,0 +1,8 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
+xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
+xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
+fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/simulation/fifo_generator_vlog_beh.v,
+fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd,
+fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v,
+fifo_rx_data.v,verilog,xil_defaultlib,../../../ip/fifo_rx_data/sim/fifo_rx_data.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/xcelium/glbl.v

@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/xcelium/run.f

@@ -0,0 +1,23 @@
+-makelib xcelium_lib/xil_defaultlib -sv \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
+-endlib
+-makelib xcelium_lib/xpm \
+  "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib xcelium_lib/fifo_generator_v13_2_4 \
+  "../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \
+-endlib
+-makelib xcelium_lib/fifo_generator_v13_2_4 \
+  "../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \
+-endlib
+-makelib xcelium_lib/fifo_generator_v13_2_4 \
+  "../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  "../../../ip/fifo_rx_data/sim/fifo_rx_data.v" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+  glbl.v
+-endlib
+

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/xsim/README.txt

@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+#             run the exported script and information about the source files.
+#
+# Generated by export_simulation on Thu May 11 21:41:10 CST 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./fifo_rx_data.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './fifo_rx_data.sh' script.
+
+./fifo_rx_data.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./fifo_rx_data.sh -noclean_files
+
+For more information on the script, please type './fifo_rx_data.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name   : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+         when export_simulation was executed from Vivado. The file contains information
+         about the file type, name, whether it is part of the IP, associated library
+         and the file path information.

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/xsim/cmd.tcl

@@ -0,0 +1,12 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+  if { [llength [get_objects]] > 0} {
+    add_wave /
+    set_property needs_save false [current_wave_config]
+  } else {
+     send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+  }
+}
+
+run -all
+quit

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/xsim/fifo_rx_data.sh

@@ -0,0 +1,214 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2019.1.3 (64-bit)
+#
+# Filename    : fifo_rx_data.sh
+# Simulator   : Xilinx Vivado Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+#               The script will automatically create the design libraries sub-directories in the run
+#               directory, add the library logical mappings in the simulator setup file, create default
+#               'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Thu May 11 21:41:10 CST 2023
+# SW Build 2644227 on Wed Sep  4 09:44:18 MDT 2019
+#
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. 
+#
+# usage: fifo_rx_data.sh [-help]
+# usage: fifo_rx_data.sh [-lib_map_path]
+# usage: fifo_rx_data.sh [-noclean_files]
+# usage: fifo_rx_data.sh [-reset_run]
+#
+#*********************************************************************************************************
+
+# Command line options
+xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0
+xvlog_opts="--relax"
+xvhdl_opts="--relax"
+
+
+# Script info
+echo -e "fifo_rx_data.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+  check_args $# $1
+  setup $1 $2
+  compile
+  elaborate
+  simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+  # Compile design files
+  xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log
+  xvhdl $xvhdl_opts -prj vhdl.prj 2>&1 | tee compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+  xelab --relax --debug typical --mt auto -L fifo_generator_v13_2_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot fifo_rx_data xil_defaultlib.fifo_rx_data xil_defaultlib.glbl -log elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+  xsim fifo_rx_data -key {Behavioral:sim_1:Functional:fifo_rx_data} -tclbatch cmd.tcl -log simulate.log
+}
+
+# STEP: setup
+setup()
+{
+  case $1 in
+    "-lib_map_path" )
+      if [[ ($2 == "") ]]; then
+        echo -e "ERROR: Simulation library directory path not specified (type \"./fifo_rx_data.sh -help\" for more information)\n"
+        exit 1
+      fi
+     copy_setup_file $2
+    ;;
+    "-reset_run" )
+      reset_run
+      echo -e "INFO: Simulation run files deleted.\n"
+      exit 0
+    ;;
+    "-noclean_files" )
+      # do not remove previous data
+    ;;
+    * )
+     copy_setup_file $2
+  esac
+
+  # Add any setup/initialization commands here:-
+
+  # <user specific commands>
+
+}
+
+# Copy xsim.ini file
+copy_setup_file()
+{
+  file="xsim.ini"
+  lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim"
+  if [[ ($1 != "") ]]; then
+    lib_map_path="$1"
+  fi
+  if [[ ($lib_map_path != "") ]]; then
+    src_file="$lib_map_path/$file"
+    if [[ -e $src_file ]]; then
+      cp $src_file .
+    fi
+
+    # Map local design libraries to xsim.ini
+    map_local_libs
+
+  fi
+}
+
+# Map local design libraries
+map_local_libs()
+{
+  updated_mappings=()
+  local_mappings=()
+
+  # Local design libraries
+  local_libs=()
+
+  if [[ 0 == ${#local_libs[@]} ]]; then
+    return
+  fi
+
+  file="xsim.ini"
+  file_backup="xsim.ini.bak"
+
+  if [[ -e $file ]]; then
+    rm -f $file_backup
+    # Create a backup copy of the xsim.ini file
+    cp $file $file_backup
+    # Read libraries from backup file and search in local library collection
+    while read -r line
+    do
+      IN=$line
+      # Split mapping entry with '=' delimiter to fetch library name and mapping
+      read lib_name mapping <<<$(IFS="="; echo $IN)
+      # If local library found, then construct the local mapping and add to local mapping collection
+      if `echo ${local_libs[@]} | grep -wq $lib_name` ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        local_mappings+=("$lib_name")
+      fi
+      # Add to updated library mapping collection
+      updated_mappings+=("$line")
+    done < "$file_backup"
+    # Append local libraries not found originally from xsim.ini
+    for (( i=0; i<${#local_libs[*]}; i++ )); do
+      lib_name="${local_libs[i]}"
+      if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then
+        line="$lib_name=xsim.dir/$lib_name"
+        updated_mappings+=("$line")
+      fi
+    done
+    # Write updated mappings in xsim.ini
+    rm -f $file
+    for (( i=0; i<${#updated_mappings[*]}; i++ )); do
+      lib_name="${updated_mappings[i]}"
+      echo $lib_name >> $file
+    done
+  else
+    for (( i=0; i<${#local_libs[*]}; i++ )); do
+      lib_name="${local_libs[i]}"
+      mapping="$lib_name=xsim.dir/$lib_name"
+      echo $mapping >> $file
+    done
+  fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+  files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb fifo_rx_data.wdb xsim.dir)
+  for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+    file="${files_to_remove[i]}"
+    if [[ -e $file ]]; then
+      rm -rf $file
+    fi
+  done
+}
+
+# Check command line arguments
+check_args()
+{
+  if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+    echo -e "ERROR: Unknown option specified '$2' (type \"./fifo_rx_data.sh -help\" for more information)\n"
+    exit 1
+  fi
+
+  if [[ ($2 == "-help" || $2 == "-h") ]]; then
+    usage
+  fi
+}
+
+# Script usage
+usage()
+{
+  msg="Usage: fifo_rx_data.sh [-help]\n\
+Usage: fifo_rx_data.sh [-lib_map_path]\n\
+Usage: fifo_rx_data.sh [-reset_run]\n\
+Usage: fifo_rx_data.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+  echo -e $msg
+  exit 1
+}
+
+# Launch script
+run $1 $2

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/xsim/file_info.txt

@@ -0,0 +1,2 @@
+fifo_rx_data.v,verilog,xil_defaultlib,../../../ip/fifo_rx_data/sim/fifo_rx_data.v,
+glbl.v,Verilog,xil_defaultlib,glbl.v

projects/duifei/duifei_online_acq_par/ip/ip_user_files/sim_scripts/fifo_rx_data/xsim/glbl.v

@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+endmodule
+`endif