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change online acq pn code length, change 814 online acq to the same

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修改了在线捕获程序的PN码长和频偏搜索步进,修改了地检发送程序的PN码长,使用对飞相控阵进行了测试,得到正确结果;将程序移植到814平台,同样能够正常工作;对地检程序(20230512),对飞程序(20230512)和814程序(20230415)进行归档
This commit is contained in:
josh
2023-05-14 12:51:10 +08:00
parent 0f97436c8f
commit c32d684223
1071 changed files with 222689 additions and 31208 deletions
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projects/duifei/duifei_online_acq_par/rtl/freq_comp.v
+100 -29
View File
@@ -26,25 +26,26 @@ module freq_comp
parameter DATA_O_WIDTH = 18,
parameter FREQ_WORD_WIDTH = 32,
parameter FREQ_WORD_LOWER = -4194304,
parameter FREQ_WORD_UPPER = 4194303,
parameter FREQ_WORD_LOWER = -1048576,
parameter FREQ_WORD_UPPER = 1048575,
parameter FREQ_WORD_STEP = 1024,
parameter MAX_DMF_NUM = 64,
parameter CHANNEL_NUM = 4,
// length of pseudorandom bit sequence, need to be a power of 2
parameter PRBS_LEN = 128,
parameter PRBS_LEN = 1024,
// interpolation of input signal, need to be a power of 2
parameter INTERP_RATE = 8,
parameter INTERP_RATE = 32,
// signal processing interpolation, need to be a power of 2
parameter PROCESS_INTERP = 2,
parameter PROCESS_INTERP = 2,
// possible position of pn code
parameter PRBS_POS = PRBS_LEN*PROCESS_INTERP
)
(
// clock & reset
input clk ,
input clk_4x ,
input rst ,
// module enable switch
@@ -64,6 +65,7 @@ module freq_comp
// configuration
input [$clog2(MAX_DMF_NUM)-1 : 0] dmf_num_per_ch ,
input dmf_continuous ,
input [FREQ_WORD_WIDTH-1 : 0] freq_manual ,
input freq_manual_en ,
@@ -119,6 +121,73 @@ localparam CMPY_OUTPUT_WIDTH = DATA_I_WIDTH;
genvar m;
// input data clock domain crossing
wire [DATA_I_WIDTH*CHANNEL_NUM*2-1 : 0] fifo_din;
wire [DATA_I_WIDTH*CHANNEL_NUM*2-1 : 0] fifo_dout;
reg [1:0] fifo_rd_cnt = 'b0;
reg fifo_rd_en = 'b0;
wire [DATA_I_WIDTH-1 : 0] rx_cdc_ch1_i;
wire [DATA_I_WIDTH-1 : 0] rx_cdc_ch1_q;
wire [DATA_I_WIDTH-1 : 0] rx_cdc_ch2_i;
wire [DATA_I_WIDTH-1 : 0] rx_cdc_ch2_q;
wire [DATA_I_WIDTH-1 : 0] rx_cdc_ch3_i;
wire [DATA_I_WIDTH-1 : 0] rx_cdc_ch3_q;
wire [DATA_I_WIDTH-1 : 0] rx_cdc_ch4_i;
wire [DATA_I_WIDTH-1 : 0] rx_cdc_ch4_q;
assign fifo_din = {
rx_ch1_i,
rx_ch1_q,
rx_ch2_i,
rx_ch2_q,
rx_ch3_i,
rx_ch3_q,
rx_ch4_i,
rx_ch4_q};
assign {
rx_cdc_ch1_i,
rx_cdc_ch1_q,
rx_cdc_ch2_i,
rx_cdc_ch2_q,
rx_cdc_ch3_i,
rx_cdc_ch3_q,
rx_cdc_ch4_i,
rx_cdc_ch4_q
} = fifo_dout;
always @(posedge clk_4x) begin
if (rst) begin
fifo_rd_cnt <= 'b0;
end
else begin
fifo_rd_cnt <= fifo_rd_cnt + 1'b1;
end
end
always @(posedge clk_4x) begin
if (rst) begin
fifo_rd_en <= 'b0;
end
else begin
fifo_rd_en <= (fifo_rd_cnt == 2'd3) ? 1'b1 : 'b0;
end
end
fifo_rx_data u_fifo_rx_data
(
.rst (rst ), // input wire rst
.wr_clk (clk ), // input wire wr_clk
.rd_clk (clk_4x ), // input wire rd_clk
.din (fifo_din ), // input wire [95 : 0] din
.wr_en (1'b1 ), // input wire wr_en
.rd_en (fifo_rd_en ), // input wire rd_en
.dout (fifo_dout ), // output wire [95 : 0] dout
.full ( ), // output wire full
.empty ( ) // output wire empty
);
////////////////////////////////////////////////////////////////////////////////
///////////////////////////// Center State Control /////////////////////////////
////////////////////////////////////////////////////////////////////////////////
@@ -146,7 +215,7 @@ reg freq_end = 'b0;
// -----------------------------------------------------------------------------
// 1st always block, sequential state transition
// -----------------------------------------------------------------------------
always @(posedge clk) begin
always @(posedge clk_4x) begin
if (rst) begin
state_curr <= STATE_IDLE;
end
@@ -219,7 +288,7 @@ end
// -----------------------------------------------------------------------------
// edge detection
// -----------------------------------------------------------------------------
always @(posedge clk) begin
always @(posedge clk_4x) begin
freq_comp_start_d1 <= freq_comp_start;
freq_comp_start_d2 <= freq_comp_start_d1;
end
@@ -231,7 +300,7 @@ reg freq_comp_busy_buf = 'b0;
assign freq_comp_busy = freq_comp_busy_buf;
always @(posedge clk) begin
always @(posedge clk_4x) begin
if (rst) begin
freq_comp_busy_buf <= 'b0;
end
@@ -251,7 +320,7 @@ end
// -----------------------------------------------------------------------------
// stable counter, for dds frequency and complex multiplier to be ready
// -----------------------------------------------------------------------------
always @(posedge clk) begin
always @(posedge clk_4x) begin
if (rst) begin
cnt_stable <= 'b0;
end
@@ -269,7 +338,7 @@ end
// record the frequency word generating the maximum peak
reg [FREQ_WORD_WIDTH-1 : 0] max_freq_peak_freq = 'b0;
always @(posedge clk) begin
always @(posedge clk_4x) begin
if (rst) begin
freq_word <= FREQ_WORD_LOWER;
end
@@ -297,7 +366,7 @@ end
// -----------------------------------------------------------------------------
// frequency scan finish indicator
// -----------------------------------------------------------------------------
always @(posedge clk) begin
always @(posedge clk_4x) begin
if (rst) begin
freq_end <= 'b0;
end
@@ -332,7 +401,7 @@ assign {sin_dds,cos_dds} = dds_m_axis_data_ttdata;
dds_32b_8b u_dds_bb_shift
(
.aclk (clk ), // input wire aclk
.aclk (clk_4x ), // input wire aclk
.s_axis_config_tvalid (dds_s_axis_config_tvalid ), // input wire s_axis_config_tvalid
.s_axis_config_tdata (dds_s_axis_config_ttdata ), // input wire [31 : 0] s_axis_config_tdata
.m_axis_data_tvalid (dds_m_axis_data_tvalid ), // output wire m_axis_data_tvalid
@@ -350,8 +419,8 @@ localparam AXIS_CMPY_P_WIDTH = 8*((CMPY_P_FULL_WIDTH-1)/8+1);
wire [DATA_I_WIDTH-1 : 0] din_freq_real;
wire [DATA_I_WIDTH-1 : 0] din_freq_imag;
assign din_freq_real = rx_ch2_i;
assign din_freq_imag = rx_ch2_q;
assign din_freq_real = rx_cdc_ch2_i;
assign din_freq_imag = rx_cdc_ch2_q;
// cmpy
wire [CMPY_OUTPUT_WIDTH-1 : 0] din_freq_cxr_real;
@@ -388,7 +457,7 @@ end
cmpy_12x8 u_cmpy_12x8_freq
(
.aclk (clk ), // input wire aclk
.aclk (clk_4x ), // input wire aclk
.s_axis_a_tvalid (cmpy_a_valid ), // input wire s_axis_a_tvalid
.s_axis_a_tdata (cmpy_a ), // input wire [31 : 0] s_axis_a_tdata
.s_axis_b_tvalid (cmpy_b_valid ), // input wire s_axis_b_tvalid
@@ -432,7 +501,7 @@ end
// -----------------------------------------------------------------------------
// dmf start control
// -----------------------------------------------------------------------------
always @(posedge clk) begin
always @(posedge clk_4x) begin
if (rst) begin
dmf_freq_start <= 'b0;
end
@@ -451,13 +520,14 @@ rx_dmf #(
.DATA_O_WIDTH (DATA_O_WIDTH )
) u_rx_dmf_freq
(
.clk (clk ),
.clk (clk_4x ),
.rst (rst ),
.dmf_start (dmf_freq_start ),
.dmf_busy (dmf_freq_busy ),
.dmf_num (1 ),
.dmf_continuous (1'b0 ),
.din_valid (dmf_freq_din_valid ),
.din_real (dmf_freq_din_real ),
@@ -486,7 +556,7 @@ reg [$clog2(PRBS_POS)-1 : 0] max_freq_peak_index = 'b0;
assign freq_target_valid = max_freq_peak_valid;
assign freq_target = max_freq_peak_freq;
always @(posedge clk) begin
always @(posedge clk_4x) begin
if (rst) begin
max_freq_peak_valid <= 'b0;
max_freq_peak_value_abs <= 'b0;
@@ -549,14 +619,14 @@ end
wire [CMPY_OUTPUT_WIDTH-1 : 0] din_ch_real [0 : CHANNEL_NUM-1];
wire [CMPY_OUTPUT_WIDTH-1 : 0] din_ch_imag [0 : CHANNEL_NUM-1];
assign din_ch_real[0] = rx_ch1_i;
assign din_ch_real[1] = rx_ch2_i;
assign din_ch_real[2] = rx_ch3_i;
assign din_ch_real[3] = rx_ch4_i;
assign din_ch_imag[0] = rx_ch1_q;
assign din_ch_imag[1] = rx_ch2_q;
assign din_ch_imag[2] = rx_ch3_q;
assign din_ch_imag[3] = rx_ch4_q;
assign din_ch_real[0] = rx_cdc_ch1_i;
assign din_ch_real[1] = rx_cdc_ch2_i;
assign din_ch_real[2] = rx_cdc_ch3_i;
assign din_ch_real[3] = rx_cdc_ch4_i;
assign din_ch_imag[0] = rx_cdc_ch1_q;
assign din_ch_imag[1] = rx_cdc_ch2_q;
assign din_ch_imag[2] = rx_cdc_ch3_q;
assign din_ch_imag[3] = rx_cdc_ch4_q;
// cmpy output
wire [CMPY_OUTPUT_WIDTH-1 : 0] din_ch_cxr_real [0 : CHANNEL_NUM-1];
@@ -596,7 +666,7 @@ for (m = 0; m < CHANNEL_NUM; m = m + 1) begin: cmpy_ch
cmpy_12x8 u_cmpy_12x8_ch
(
.aclk (clk ), // input wire aclk
.aclk (clk_4x ), // input wire aclk
.s_axis_a_tvalid (cmpy_a_valid ), // input wire s_axis_a_tvalid
.s_axis_a_tdata (cmpy_a ), // input wire [31 : 0] s_axis_a_tdata
.s_axis_b_tvalid (cmpy_b_valid ), // input wire s_axis_b_tvalid
@@ -630,7 +700,7 @@ wire [DATA_O_WIDTH-1 : 0] dmf_ch_moduli_abs [0 : CHANNEL_NUM-1];
// -----------------------------------------------------------------------------
// dmf start control
// -----------------------------------------------------------------------------
always @(posedge clk) begin
always @(posedge clk_4x) begin
if (rst) begin
dmf_ch_start <= 'b0;
end
@@ -665,13 +735,14 @@ for (m = 0; m < CHANNEL_NUM; m = m + 1) begin: dmf_ch
.DATA_O_WIDTH (DATA_O_WIDTH )
) u_rx_dmf_ch
(
.clk (clk ),
.clk (clk_4x ),
.rst (rst ),
.dmf_start (dmf_ch_start ),
.dmf_busy (dmf_ch_busy[m] ),
.dmf_num (dmf_num_per_ch ),
.dmf_continuous (dmf_continuous ),
.din_valid (dmf_ch_din_valid[m] ),
.din_real (dmf_ch_din_real[m] ),
projects/duifei/duifei_online_acq_par/rtl/rx_dmf.v
+11 -10
View File
@@ -28,16 +28,16 @@
module rx_dmf
#(
// length of pseudorandom bit sequence, need to be a power of 2
parameter PRBS_LEN = 128,
parameter PRBS_LEN = 1024,
// interpolation of input signal, need to be a power of 2
parameter INTERP_RATE = 8,
parameter INTERP_RATE = 32,
// signal processing interpolation, need to be a power of 2
parameter PROCESS_INTERP = 2,
parameter PROCESS_INTERP = 2,
// possible position of pn code
parameter PRBS_POS = PRBS_LEN*PROCESS_INTERP,
parameter MAX_DMF_NUM = 64,
parameter DATA_I_WIDTH = 12,
parameter DATA_O_WIDTH = 18
parameter MAX_DMF_NUM = 64,
parameter DATA_I_WIDTH = 12,
parameter DATA_O_WIDTH = 18
)
(
input clk ,
@@ -51,6 +51,7 @@ module rx_dmf
input [DATA_I_WIDTH-1 : 0] din_imag ,
input [$clog2(MAX_DMF_NUM+1)-1 : 0] dmf_num ,
input dmf_continuous ,
output peak_valid ,
output last_peak_valid ,
@@ -106,7 +107,7 @@ always @(posedge clk) begin
if (rst) begin
dmf_busy_buf <= 'b0;
end
else if (cnt_dmf_num == dmf_num+1) begin
else if (cnt_dmf_num == dmf_num+1 && ~dmf_continuous) begin
// clear when output is valid
dmf_busy_buf <= 'b0;
end
@@ -200,7 +201,7 @@ assign dmf_axis_o_imag = m_axis_data_ttdata_imag;
assign dmf_o_valid = m_axis_data_tvalid_real;
// fir ip core instantiation
fir_prbs7_invert_rep2 u_dmf_real
fir_prbs10_invert_rep2 u_dmf_real
(
.aclk (clk ), // input wire aclk
.aresetn (dmf_busy ), // input aresetn
@@ -211,7 +212,7 @@ fir_prbs7_invert_rep2 u_dmf_real
.m_axis_data_tdata (m_axis_data_ttdata_real) // output wire [23 : 0] m_axis_data_tdata
);
fir_prbs7_invert_rep2 u_dmf_imag
fir_prbs10_invert_rep2 u_dmf_imag
(
.aclk (clk ), // input wire aclk
.aresetn (dmf_busy ), // input aresetn
@@ -456,7 +457,7 @@ always @(posedge clk) begin
peak_value_q_buf <= moduli_max_imag ;
peak_index_buf <= moduli_max_index;
last_peak_valid_buf<= (cnt_dmf_num == dmf_num) ? 1'b1 : 'b0;
last_peak_valid_buf<= ((cnt_dmf_num == dmf_num) && ~dmf_continuous) ? 1'b1 : 'b0;
end
else begin
peak_valid_buf <= 1'b0;
projects/duifei/duifei_online_acq_par/rtl/system_top.v
+43 -38
View File
@@ -167,7 +167,7 @@ module system_top
inout debug_io_1 ,
inout debug_io_2 ,
// 3.3v ports
inout debug_io_3 ,
input debug_io_3 ,
inout debug_io_4 ,
inout debug_io_5 ,
inout debug_io_6 ,
@@ -572,7 +572,11 @@ wire [31:0] freq_set ;
wire [ 1:0] iq_sel ;
wire [ 3:0] bb_rshift ;
tx_qpsk u_tx_qpsk
tx_qpsk #(
.BIT_DATA (1024'b0000000100100010000011001001101000010010101000011110101110101101101100000000110000011011001100001010110101110001101111110001000111100111101101101000000010100001011010101000111110111100100101100000100110010001010001101101110000001111000111011111110010000110001011011101000011010101100111100101101100100000100010010011000000101100010100111011001110001011111101010001011101101011000011001101101010000011101001111010011010100100111000001111100111001101111010001010101101111100001001110100011101011111011010010000100001010010101100011100111111101100001000110100111001001111000011011101100011000111101111101001001010000001101000110010111010010110100010001011001101001010010001100001110110111100000101110010101110011101110111001100111010101110111101100101000100110110001000011100101111100101001100110010101010011111100110001101011110011010110100110001001011100001011110101010101111111101000001010100101111000101011110111010100110111001000111000111111111100000001110000111111011100010011111000110011111010110010110010010010000000001),
.BIT_DATA_LEN (1024),
.CLK_FREQ (48000000)
) u_tx_qpsk
(
.clk (sys_clk ), // input clk
.rst (sys_rst ), // input rst
@@ -677,6 +681,7 @@ wire freq_comp_auto_enable_vio;
wire freq_comp_start_vio;
wire freq_comp_busy ;
wire [7:0] dmf_num_per_ch ;
wire dmf_continuous ;
wire [31:0] freq_manual ;
wire freq_manual_en ;
wire [31:0] freq_target ;
@@ -686,30 +691,31 @@ wire ch_peak_valid ;
wire [17:0] ch1_peak_value_abs ;
wire [17:0] ch1_peak_value_i ;
wire [17:0] ch1_peak_value_q ;
wire [ 9:0] ch1_peak_index ;
wire [10:0] ch1_peak_index ;
wire [17:0] ch2_peak_value_abs ;
wire [17:0] ch2_peak_value_i ;
wire [17:0] ch2_peak_value_q ;
wire [ 9:0] ch2_peak_index ;
wire [10:0] ch2_peak_index ;
wire [17:0] ch3_peak_value_abs ;
wire [17:0] ch3_peak_value_i ;
wire [17:0] ch3_peak_value_q ;
wire [ 9:0] ch3_peak_index ;
wire [10:0] ch3_peak_index ;
wire [17:0] ch4_peak_value_abs ;
wire [17:0] ch4_peak_value_i ;
wire [17:0] ch4_peak_value_q ;
wire [ 9:0] ch4_peak_index ;
wire [10:0] ch4_peak_index ;
assign freq_comp_start = (freq_comp_auto_enable_vio == 1'b1) ? freq_comp_start_auto : freq_comp_start_vio;
freq_comp #(
.FREQ_WORD_LOWER (-4194304 ),
.FREQ_WORD_UPPER (4194303 ),
.FREQ_WORD_LOWER (-1048576 ),
.FREQ_WORD_UPPER (1048575 ),
.FREQ_WORD_STEP (1024 )
) u_freq_comp
(
// clock & reset
.clk (sys_clk ), // input clk
.clk_4x (sys_clk_4x ), // input clk_4x
.rst (sys_rst ), // input rst
// input data
@@ -728,6 +734,7 @@ freq_comp #(
// configuration
.dmf_num_per_ch (dmf_num_per_ch ), // input [$clog2(MAX_DMF_NUM)-1 : 0] dmf_num_per_ch
.dmf_continuous (dmf_continuous ),
.freq_manual (freq_manual ), // input [FREQ_WORD_WIDTH-1 : 0] freq_manual
.freq_manual_en (freq_manual_en ), // input freq_manual_en
@@ -760,7 +767,7 @@ freq_comp #(
.ch4_peak_index (ch4_peak_index ) // output reg [$clog2(PRBS_POS-1) : 0] ch4_peak_index
);
reg [9:0] chip_cnt = 'b0;
reg [12:0] chip_cnt = 'b0;
always @(posedge sys_clk) begin
if (sys_rst) begin
@@ -884,23 +891,23 @@ ila_rf_auto_control u_ila_rf_auto_control
.probe5 (u_rf_auto_switch_freq.freq_word_cnt ) // 8
);
ila_AntCtrl u_ila_AntCtrl
(
.clk (clk_96m ), // input wire clk
.probe0 (u_ant_rf_ctrl.ant_clk ), // input wire [0:0] probe0
.probe1 (u_ant_rf_ctrl.ant_en ), // input wire [0:0] probe1
.probe2 (u_ant_rf_ctrl.ant_data ), // input wire [0:0] probe2
.probe3 (u_ant_rf_ctrl.ant_tr ), // input wire [0:0] probe3
.probe4 (u_ant_rf_ctrl.ant_dary ), // input wire [0:0] probe4
.probe5 (u_ant_rf_ctrl.ant_dout ), // input wire [0:0] probe5
.probe6 (u_ant_rf_ctrl.state_antdata[1:0] ), // input wire [0:0] probe5
.probe7 (u_ant_rf_ctrl.Ant_Ant_Volt[7:0] ), // input wire [0:0] probe5
.probe8 (u_ant_rf_ctrl.Ant_RF_Volt[7:0] ), // input wire [0:0] probe5
.probe9 (u_ant_rf_ctrl.Ant_IF_Volt[7:0] ), // input wire [0:0] probe5
.probe10(u_ant_rf_ctrl.Ant_state[7:0] ), // input wire [0:0] probe5
.probe11(u_ant_rf_ctrl.Ant_Framecount[31:0] ), // input wire [0:0] probe5
.probe12(u_ant_rf_ctrl.Ant_RecvWord[95:0] ) // input wire [0:0] probe5
);
// ila_AntCtrl u_ila_AntCtrl
// (
// .clk (clk_96m ), // input wire clk
// .probe0 (u_ant_rf_ctrl.ant_clk ), // input wire [0:0] probe0
// .probe1 (u_ant_rf_ctrl.ant_en ), // input wire [0:0] probe1
// .probe2 (u_ant_rf_ctrl.ant_data ), // input wire [0:0] probe2
// .probe3 (u_ant_rf_ctrl.ant_tr ), // input wire [0:0] probe3
// .probe4 (u_ant_rf_ctrl.ant_dary ), // input wire [0:0] probe4
// .probe5 (u_ant_rf_ctrl.ant_dout ), // input wire [0:0] probe5
// .probe6 (u_ant_rf_ctrl.state_antdata[1:0] ), // input wire [0:0] probe5
// .probe7 (u_ant_rf_ctrl.Ant_Ant_Volt[7:0] ), // input wire [0:0] probe5
// .probe8 (u_ant_rf_ctrl.Ant_RF_Volt[7:0] ), // input wire [0:0] probe5
// .probe9 (u_ant_rf_ctrl.Ant_IF_Volt[7:0] ), // input wire [0:0] probe5
// .probe10(u_ant_rf_ctrl.Ant_state[7:0] ), // input wire [0:0] probe5
// .probe11(u_ant_rf_ctrl.Ant_Framecount[31:0] ), // input wire [0:0] probe5
// .probe12(u_ant_rf_ctrl.Ant_RecvWord[95:0] ) // input wire [0:0] probe5
// );
vio_rf_rd u_vio_rf_rd (
.clk (clk_96m ), // input wire clk
@@ -980,18 +987,19 @@ vio_manual_ctrl u_vio_manual_ctrl
vio_freq_comp u_vio_freq_comp
(
.clk (sys_clk ), // input wire clk
.clk (sys_clk_4x ), // input wire clk
.probe_in0 (freq_comp_busy ), // input wire [0 : 0] probe_in0
.probe_out0 (freq_comp_start_vio ), // output wire [0 : 0] probe_out0
.probe_out1 (dmf_num_per_ch ), // output wire [7 : 0] probe_out1
.probe_out2 (freq_manual_en ), // output wire [0 : 0] probe_out2
.probe_out3 (freq_manual ), // output wire [31 : 0] probe_out3
.probe_out4 (freq_comp_auto_enable_vio ) // output wire [0 : 0] probe_out4
.probe_out4 (freq_comp_auto_enable_vio ), // output wire [0 : 0] probe_out4
.probe_out5 (dmf_continuous ) // output wire [0 : 0] probe_out5
);
ila_freq_comp u_ila_freq_comp
(
.clk (sys_clk ), // input wire clk
.clk (sys_clk_4x ), // input wire clk
.probe0 (ch_peak_valid ), // input wire [0:0] probe0
.probe1 (ch1_peak_value_i ), // input wire [17:0] probe1
.probe2 (ch1_peak_value_q ), // input wire [17:0] probe2
@@ -1001,21 +1009,18 @@ ila_freq_comp u_ila_freq_comp
.probe6 (ch3_peak_value_q ), // input wire [17:0] probe6
.probe7 (ch4_peak_value_i ), // input wire [17:0] probe7
.probe8 (ch4_peak_value_q ), // input wire [17:0] probe8
.probe9 (ch1_peak_index ), // input wire [7:0] probe9
.probe10(ch2_peak_index ), // input wire [7:0] probe10
.probe11(ch3_peak_index ), // input wire [7:0] probe11
.probe12(ch4_peak_index ), // input wire [7:0] probe12
.probe9 (ch1_peak_index ), // input wire [10:0] probe9
.probe10(ch2_peak_index ), // input wire [10:0] probe10
.probe11(ch3_peak_index ), // input wire [10:0] probe11
.probe12(ch4_peak_index ), // input wire [10:0] probe12
.probe13(freq_comp_start ), // input wire [0:0] probe13
.probe14(u_freq_comp.state_curr ), // input wire [2:0] probe14
.probe15(u_freq_comp.din_freq_cxr_real ), // input wire [11:0] probe15
.probe16(u_freq_comp.din_freq_cxr_imag ), // input wire [11:0] probe16
.probe17(u_freq_comp.dmf_freq_moduli_abs ), // input wire [17:0] probe17
.probe18(u_freq_comp.dmf_ch_moduli_abs[0] ), // input wire [17:0] probe18
.probe19(u_freq_comp.dmf_ch_moduli_abs[1] ), // input wire [17:0] probe19
.probe20(u_freq_comp.dmf_ch_moduli_abs[2] ), // input wire [17:0] probe20
.probe21(u_freq_comp.dmf_ch_moduli_abs[3] ), // input wire [17:0] probe21
.probe22(u_freq_comp.freq_word ), // input wire [31:0] probe22
.probe23(vio_frequency_auto[11:0] ) // input wire [11:0] probe23
.probe19(u_freq_comp.freq_word ), // input wire [31:0] probe19
.probe20(vio_frequency_auto[11:0] ) // input wire [11:0] probe20
);
endmodule