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change online acq pn code length, change 814 online acq to the same

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修改了在线捕获程序的PN码长和频偏搜索步进,修改了地检发送程序的PN码长,使用对飞相控阵进行了测试,得到正确结果;将程序移植到814平台,同样能够正常工作;对地检程序(20230512),对飞程序(20230512)和814程序(20230415)进行归档
This commit is contained in:
josh
2023-05-14 12:51:10 +08:00
parent 0f97436c8f
commit c32d684223
1071 changed files with 222689 additions and 31208 deletions
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projects/duifei/duifei_online_acq_par/rtl/freq_comp.v
+100 -29
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@@ -26,25 +26,26 @@ module freq_comp
parameter DATA_O_WIDTH = 18,
parameter FREQ_WORD_WIDTH = 32,
parameter FREQ_WORD_LOWER = -4194304,
parameter FREQ_WORD_UPPER = 4194303,
parameter FREQ_WORD_LOWER = -1048576,
parameter FREQ_WORD_UPPER = 1048575,
parameter FREQ_WORD_STEP = 1024,
parameter MAX_DMF_NUM = 64,
parameter CHANNEL_NUM = 4,
// length of pseudorandom bit sequence, need to be a power of 2
parameter PRBS_LEN = 128,
parameter PRBS_LEN = 1024,
// interpolation of input signal, need to be a power of 2
parameter INTERP_RATE = 8,
parameter INTERP_RATE = 32,
// signal processing interpolation, need to be a power of 2
parameter PROCESS_INTERP = 2,
parameter PROCESS_INTERP = 2,
// possible position of pn code
parameter PRBS_POS = PRBS_LEN*PROCESS_INTERP
)
(
// clock & reset
input clk ,
input clk_4x ,
input rst ,
// module enable switch
@@ -64,6 +65,7 @@ module freq_comp
// configuration
input [$clog2(MAX_DMF_NUM)-1 : 0] dmf_num_per_ch ,
input dmf_continuous ,
input [FREQ_WORD_WIDTH-1 : 0] freq_manual ,
input freq_manual_en ,
@@ -119,6 +121,73 @@ localparam CMPY_OUTPUT_WIDTH = DATA_I_WIDTH;
genvar m;
// input data clock domain crossing
wire [DATA_I_WIDTH*CHANNEL_NUM*2-1 : 0] fifo_din;
wire [DATA_I_WIDTH*CHANNEL_NUM*2-1 : 0] fifo_dout;
reg [1:0] fifo_rd_cnt = 'b0;
reg fifo_rd_en = 'b0;
wire [DATA_I_WIDTH-1 : 0] rx_cdc_ch1_i;
wire [DATA_I_WIDTH-1 : 0] rx_cdc_ch1_q;
wire [DATA_I_WIDTH-1 : 0] rx_cdc_ch2_i;
wire [DATA_I_WIDTH-1 : 0] rx_cdc_ch2_q;
wire [DATA_I_WIDTH-1 : 0] rx_cdc_ch3_i;
wire [DATA_I_WIDTH-1 : 0] rx_cdc_ch3_q;
wire [DATA_I_WIDTH-1 : 0] rx_cdc_ch4_i;
wire [DATA_I_WIDTH-1 : 0] rx_cdc_ch4_q;
assign fifo_din = {
rx_ch1_i,
rx_ch1_q,
rx_ch2_i,
rx_ch2_q,
rx_ch3_i,
rx_ch3_q,
rx_ch4_i,
rx_ch4_q};
assign {
rx_cdc_ch1_i,
rx_cdc_ch1_q,
rx_cdc_ch2_i,
rx_cdc_ch2_q,
rx_cdc_ch3_i,
rx_cdc_ch3_q,
rx_cdc_ch4_i,
rx_cdc_ch4_q
} = fifo_dout;
always @(posedge clk_4x) begin
if (rst) begin
fifo_rd_cnt <= 'b0;
end
else begin
fifo_rd_cnt <= fifo_rd_cnt + 1'b1;
end
end
always @(posedge clk_4x) begin
if (rst) begin
fifo_rd_en <= 'b0;
end
else begin
fifo_rd_en <= (fifo_rd_cnt == 2'd3) ? 1'b1 : 'b0;
end
end
fifo_rx_data u_fifo_rx_data
(
.rst (rst ), // input wire rst
.wr_clk (clk ), // input wire wr_clk
.rd_clk (clk_4x ), // input wire rd_clk
.din (fifo_din ), // input wire [95 : 0] din
.wr_en (1'b1 ), // input wire wr_en
.rd_en (fifo_rd_en ), // input wire rd_en
.dout (fifo_dout ), // output wire [95 : 0] dout
.full ( ), // output wire full
.empty ( ) // output wire empty
);
////////////////////////////////////////////////////////////////////////////////
///////////////////////////// Center State Control /////////////////////////////
////////////////////////////////////////////////////////////////////////////////
@@ -146,7 +215,7 @@ reg freq_end = 'b0;
// -----------------------------------------------------------------------------
// 1st always block, sequential state transition
// -----------------------------------------------------------------------------
always @(posedge clk) begin
always @(posedge clk_4x) begin
if (rst) begin
state_curr <= STATE_IDLE;
end
@@ -219,7 +288,7 @@ end
// -----------------------------------------------------------------------------
// edge detection
// -----------------------------------------------------------------------------
always @(posedge clk) begin
always @(posedge clk_4x) begin
freq_comp_start_d1 <= freq_comp_start;
freq_comp_start_d2 <= freq_comp_start_d1;
end
@@ -231,7 +300,7 @@ reg freq_comp_busy_buf = 'b0;
assign freq_comp_busy = freq_comp_busy_buf;
always @(posedge clk) begin
always @(posedge clk_4x) begin
if (rst) begin
freq_comp_busy_buf <= 'b0;
end
@@ -251,7 +320,7 @@ end
// -----------------------------------------------------------------------------
// stable counter, for dds frequency and complex multiplier to be ready
// -----------------------------------------------------------------------------
always @(posedge clk) begin
always @(posedge clk_4x) begin
if (rst) begin
cnt_stable <= 'b0;
end
@@ -269,7 +338,7 @@ end
// record the frequency word generating the maximum peak
reg [FREQ_WORD_WIDTH-1 : 0] max_freq_peak_freq = 'b0;
always @(posedge clk) begin
always @(posedge clk_4x) begin
if (rst) begin
freq_word <= FREQ_WORD_LOWER;
end
@@ -297,7 +366,7 @@ end
// -----------------------------------------------------------------------------
// frequency scan finish indicator
// -----------------------------------------------------------------------------
always @(posedge clk) begin
always @(posedge clk_4x) begin
if (rst) begin
freq_end <= 'b0;
end
@@ -332,7 +401,7 @@ assign {sin_dds,cos_dds} = dds_m_axis_data_ttdata;
dds_32b_8b u_dds_bb_shift
(
.aclk (clk ), // input wire aclk
.aclk (clk_4x ), // input wire aclk
.s_axis_config_tvalid (dds_s_axis_config_tvalid ), // input wire s_axis_config_tvalid
.s_axis_config_tdata (dds_s_axis_config_ttdata ), // input wire [31 : 0] s_axis_config_tdata
.m_axis_data_tvalid (dds_m_axis_data_tvalid ), // output wire m_axis_data_tvalid
@@ -350,8 +419,8 @@ localparam AXIS_CMPY_P_WIDTH = 8*((CMPY_P_FULL_WIDTH-1)/8+1);
wire [DATA_I_WIDTH-1 : 0] din_freq_real;
wire [DATA_I_WIDTH-1 : 0] din_freq_imag;
assign din_freq_real = rx_ch2_i;
assign din_freq_imag = rx_ch2_q;
assign din_freq_real = rx_cdc_ch2_i;
assign din_freq_imag = rx_cdc_ch2_q;
// cmpy
wire [CMPY_OUTPUT_WIDTH-1 : 0] din_freq_cxr_real;
@@ -388,7 +457,7 @@ end
cmpy_12x8 u_cmpy_12x8_freq
(
.aclk (clk ), // input wire aclk
.aclk (clk_4x ), // input wire aclk
.s_axis_a_tvalid (cmpy_a_valid ), // input wire s_axis_a_tvalid
.s_axis_a_tdata (cmpy_a ), // input wire [31 : 0] s_axis_a_tdata
.s_axis_b_tvalid (cmpy_b_valid ), // input wire s_axis_b_tvalid
@@ -432,7 +501,7 @@ end
// -----------------------------------------------------------------------------
// dmf start control
// -----------------------------------------------------------------------------
always @(posedge clk) begin
always @(posedge clk_4x) begin
if (rst) begin
dmf_freq_start <= 'b0;
end
@@ -451,13 +520,14 @@ rx_dmf #(
.DATA_O_WIDTH (DATA_O_WIDTH )
) u_rx_dmf_freq
(
.clk (clk ),
.clk (clk_4x ),
.rst (rst ),
.dmf_start (dmf_freq_start ),
.dmf_busy (dmf_freq_busy ),
.dmf_num (1 ),
.dmf_continuous (1'b0 ),
.din_valid (dmf_freq_din_valid ),
.din_real (dmf_freq_din_real ),
@@ -486,7 +556,7 @@ reg [$clog2(PRBS_POS)-1 : 0] max_freq_peak_index = 'b0;
assign freq_target_valid = max_freq_peak_valid;
assign freq_target = max_freq_peak_freq;
always @(posedge clk) begin
always @(posedge clk_4x) begin
if (rst) begin
max_freq_peak_valid <= 'b0;
max_freq_peak_value_abs <= 'b0;
@@ -549,14 +619,14 @@ end
wire [CMPY_OUTPUT_WIDTH-1 : 0] din_ch_real [0 : CHANNEL_NUM-1];
wire [CMPY_OUTPUT_WIDTH-1 : 0] din_ch_imag [0 : CHANNEL_NUM-1];
assign din_ch_real[0] = rx_ch1_i;
assign din_ch_real[1] = rx_ch2_i;
assign din_ch_real[2] = rx_ch3_i;
assign din_ch_real[3] = rx_ch4_i;
assign din_ch_imag[0] = rx_ch1_q;
assign din_ch_imag[1] = rx_ch2_q;
assign din_ch_imag[2] = rx_ch3_q;
assign din_ch_imag[3] = rx_ch4_q;
assign din_ch_real[0] = rx_cdc_ch1_i;
assign din_ch_real[1] = rx_cdc_ch2_i;
assign din_ch_real[2] = rx_cdc_ch3_i;
assign din_ch_real[3] = rx_cdc_ch4_i;
assign din_ch_imag[0] = rx_cdc_ch1_q;
assign din_ch_imag[1] = rx_cdc_ch2_q;
assign din_ch_imag[2] = rx_cdc_ch3_q;
assign din_ch_imag[3] = rx_cdc_ch4_q;
// cmpy output
wire [CMPY_OUTPUT_WIDTH-1 : 0] din_ch_cxr_real [0 : CHANNEL_NUM-1];
@@ -596,7 +666,7 @@ for (m = 0; m < CHANNEL_NUM; m = m + 1) begin: cmpy_ch
cmpy_12x8 u_cmpy_12x8_ch
(
.aclk (clk ), // input wire aclk
.aclk (clk_4x ), // input wire aclk
.s_axis_a_tvalid (cmpy_a_valid ), // input wire s_axis_a_tvalid
.s_axis_a_tdata (cmpy_a ), // input wire [31 : 0] s_axis_a_tdata
.s_axis_b_tvalid (cmpy_b_valid ), // input wire s_axis_b_tvalid
@@ -630,7 +700,7 @@ wire [DATA_O_WIDTH-1 : 0] dmf_ch_moduli_abs [0 : CHANNEL_NUM-1];
// -----------------------------------------------------------------------------
// dmf start control
// -----------------------------------------------------------------------------
always @(posedge clk) begin
always @(posedge clk_4x) begin
if (rst) begin
dmf_ch_start <= 'b0;
end
@@ -665,13 +735,14 @@ for (m = 0; m < CHANNEL_NUM; m = m + 1) begin: dmf_ch
.DATA_O_WIDTH (DATA_O_WIDTH )
) u_rx_dmf_ch
(
.clk (clk ),
.clk (clk_4x ),
.rst (rst ),
.dmf_start (dmf_ch_start ),
.dmf_busy (dmf_ch_busy[m] ),
.dmf_num (dmf_num_per_ch ),
.dmf_continuous (dmf_continuous ),
.din_valid (dmf_ch_din_valid[m] ),
.din_real (dmf_ch_din_real[m] ),