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update phase comp with cmpy; add var cal module

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josh
2023-06-12 17:35:52 +08:00
parent f7eb53ced7
commit d7cca991f1
220 changed files with 87094 additions and 1041 deletions
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projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf
+15 -11
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@@ -1,30 +1,34 @@
version:1
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projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf
+5 -4
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version:1
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projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc
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projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml
+21 -16
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@@ -3,7 +3,7 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Mon Jun 5 20:29:05 2023">
<application name="pa" timeStamp="Mon Jun 12 11:42:01 2023">
<section name="Project Information" visible="false">
<property name="ProjectID" value="cf48733ed6784c129006f962746a20c1" type="ProjectID"/>
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
@@ -17,45 +17,50 @@ This means code written to parse this file will need to be revisited each subseq
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
</item>
<item name="Java Command Handlers">
<property name="AddExistingIPHandler" value="16" type="JavaHandler"/>
<property name="CloseProject" value="10" type="JavaHandler"/>
<property name="AddExistingIPHandler" value="17" type="JavaHandler"/>
<property name="CloseProject" value="11" type="JavaHandler"/>
<property name="CopyIPHandler" value="13" type="JavaHandler"/>
<property name="CustomizeCore" value="2" type="JavaHandler"/>
<property name="EditDelete" value="9" type="JavaHandler"/>
<property name="ManageCompositeTargets" value="5" type="JavaHandler"/>
<property name="NewIPLocationHandler" value="1" type="JavaHandler"/>
<property name="OpenIPLocationHandler" value="9" type="JavaHandler"/>
<property name="OpenIPLocationHandler" value="10" type="JavaHandler"/>
<property name="OpenPreviousIPHandler" value="6" type="JavaHandler"/>
<property name="OpenProject" value="1" type="JavaHandler"/>
<property name="RecustomizeCore" value="62" type="JavaHandler"/>
<property name="ShowView" value="1" type="JavaHandler"/>
</item>
<item name="Gui Handlers">
<property name="BaseDialog_CANCEL" value="28" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="66" type="GuiHandlerData"/>
<property name="BaseDialog_CANCEL" value="29" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="67" type="GuiHandlerData"/>
<property name="CmdMsgDialog_OK" value="3" type="GuiHandlerData"/>
<property name="CopyIPHandler_DESTINATION_IP_NAME" value="12" type="GuiHandlerData"/>
<property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="15" type="GuiHandlerData"/>
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="19" type="GuiHandlerData"/>
<property name="FPGAChooser_FPGA_TABLE" value="1" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="324" type="GuiHandlerData"/>
<property name="GettingStartedView_MANAGE_IP" value="10" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="333" type="GuiHandlerData"/>
<property name="GettingStartedView_MANAGE_IP" value="11" type="GuiHandlerData"/>
<property name="GettingStartedView_OPEN_PROJECT" value="1" type="GuiHandlerData"/>
<property name="GettingStartedView_START_USING_VIVADO_WITH_IP_CATALOG" value="3" type="GuiHandlerData"/>
<property name="HACGCIPSymbol_SHOW_DISABLED_PORTS" value="1" type="GuiHandlerData"/>
<property name="HJFileChooserHelpers_JUMP_TO_RECENT_PROJECT_DIRECTORY" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_EXPORT" value="3" type="GuiHandlerData"/>
<property name="MainMenuMgr_FILE" value="22" type="GuiHandlerData"/>
<property name="MainMenuMgr_FILE" value="24" type="GuiHandlerData"/>
<property name="MainMenuMgr_IP" value="8" type="GuiHandlerData"/>
<property name="MainMenuMgr_PROJECT" value="13" type="GuiHandlerData"/>
<property name="MainMenuMgr_PROJECT" value="14" type="GuiHandlerData"/>
<property name="MainMenuMgr_REPORTS" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_TEXT_EDITOR" value="5" type="GuiHandlerData"/>
<property name="MainMenuMgr_TOOLS" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_WINDOW" value="2" type="GuiHandlerData"/>
<property name="MainToolbarMgr_OPEN" value="1" type="GuiHandlerData"/>
<property name="NewIPProjectWizard_IP_LOCATION" value="1" type="GuiHandlerData"/>
<property name="NewIPProjectWizard_PART" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_ADD_EXISTING_IP" value="16" type="GuiHandlerData"/>
<property name="PACommandNames_CLOSE_PROJECT" value="10" type="GuiHandlerData"/>
<property name="PACommandNames_ADD_EXISTING_IP" value="17" type="GuiHandlerData"/>
<property name="PACommandNames_CLOSE_PROJECT" value="11" type="GuiHandlerData"/>
<property name="PACommandNames_COPY_IP" value="13" type="GuiHandlerData"/>
<property name="PACommandNames_GENERATE_COMPOSITE_FILE" value="3" type="GuiHandlerData"/>
<property name="PACommandNames_OPEN_IP_LOCATION" value="8" type="GuiHandlerData"/>
<property name="PACommandNames_OPEN_IP_LOCATION" value="9" type="GuiHandlerData"/>
<property name="PACommandNames_PROPERTIES_WINDOW" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_RESET_COMPOSITE_FILE" value="2" type="GuiHandlerData"/>
<property name="ProgressDialog_BACKGROUND" value="5" type="GuiHandlerData"/>
<property name="RDICommands_DELETE" value="1" type="GuiHandlerData"/>
@@ -65,13 +70,13 @@ This means code written to parse this file will need to be revisited each subseq
<property name="SimpleOutputProductDialog_RESET_OUTPUT_PRODUCTS" value="1" type="GuiHandlerData"/>
<property name="SrcChooserPanel_ADD_CONFIGURABLE_IP_FILES" value="15" type="GuiHandlerData"/>
<property name="SrcChooserPanel_MAKE_LOCAL_COPY_OF_THESE_FILES_INTO" value="1" type="GuiHandlerData"/>
<property name="SrcMenu_IP_DOCUMENTATION" value="19" type="GuiHandlerData"/>
<property name="SrcMenu_IP_DOCUMENTATION" value="20" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_IP_LOCATIONS" value="6" type="GuiHandlerData"/>
</item>
<item name="Other">
<property name="GuiMode" value="9" type="GuiMode"/>
<property name="GuiMode" value="11" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="4" type="TclMode"/>
<property name="TclMode" value="6" type="TclMode"/>
</item>
</section>
</application>
projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/hdl/vio_v3_0_20_vio_include.v
-283
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@@ -1,283 +0,0 @@
`pragma protect begin_protected
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`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
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`pragma protect key_block
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`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
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`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12464)
`pragma protect data_block
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`pragma protect end_protected
projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/sim/vio_phase_comp.v
+23 -6
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@@ -48,19 +48,36 @@
`timescale 1ns / 1ps
module vio_phase_comp (
clk,
probe_in0,probe_in1,probe_in2,
probe_out0,
probe_out1,
probe_out2,
probe_out3
probe_out3,
probe_out4,
probe_out5,
probe_out6,
probe_out7,
probe_out8,
probe_out9,
probe_out10
);
input clk;
input [31 : 0] probe_in0;
input [0 : 0] probe_in1;
input [0 : 0] probe_in2;
output reg [15 : 0] probe_out0 = 'h0000 ;
output reg [15 : 0] probe_out1 = 'h0000 ;
output reg [15 : 0] probe_out2 = 'h0000 ;
output reg [15 : 0] probe_out3 = 'h0000 ;
output reg [0 : 0] probe_out0 = 'h0 ;
output reg [0 : 0] probe_out1 = 'h0 ;
output reg [11 : 0] probe_out2 = 'h000 ;
output reg [11 : 0] probe_out3 = 'h000 ;
output reg [11 : 0] probe_out4 = 'h000 ;
output reg [11 : 0] probe_out5 = 'h000 ;
output reg [11 : 0] probe_out6 = 'h000 ;
output reg [11 : 0] probe_out7 = 'h000 ;
output reg [11 : 0] probe_out8 = 'h000 ;
output reg [11 : 0] probe_out9 = 'h000 ;
output reg [4 : 0] probe_out10 = 'h09 ;
endmodule
projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp.veo
+15 -5
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@@ -55,11 +55,21 @@
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
vio_phase_comp your_instance_name (
.clk(clk), // input wire clk
.probe_out0(probe_out0), // output wire [15 : 0] probe_out0
.probe_out1(probe_out1), // output wire [15 : 0] probe_out1
.probe_out2(probe_out2), // output wire [15 : 0] probe_out2
.probe_out3(probe_out3) // output wire [15 : 0] probe_out3
.clk(clk), // input wire clk
.probe_in0(probe_in0), // input wire [31 : 0] probe_in0
.probe_in1(probe_in1), // input wire [0 : 0] probe_in1
.probe_in2(probe_in2), // input wire [0 : 0] probe_in2
.probe_out0(probe_out0), // output wire [0 : 0] probe_out0
.probe_out1(probe_out1), // output wire [0 : 0] probe_out1
.probe_out2(probe_out2), // output wire [11 : 0] probe_out2
.probe_out3(probe_out3), // output wire [11 : 0] probe_out3
.probe_out4(probe_out4), // output wire [11 : 0] probe_out4
.probe_out5(probe_out5), // output wire [11 : 0] probe_out5
.probe_out6(probe_out6), // output wire [11 : 0] probe_out6
.probe_out7(probe_out7), // output wire [11 : 0] probe_out7
.probe_out8(probe_out8), // output wire [11 : 0] probe_out8
.probe_out9(probe_out9), // output wire [11 : 0] probe_out9
.probe_out10(probe_out10) // output wire [4 : 0] probe_out10
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp.vho
+25 -5
View File
@@ -55,10 +55,20 @@
COMPONENT vio_phase_comp
PORT (
clk : IN STD_LOGIC;
probe_out0 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
probe_out1 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
probe_out2 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
probe_out3 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
probe_in0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
probe_in1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe_in2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
probe_out1 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
probe_out2 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
probe_out3 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
probe_out4 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
probe_out5 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
probe_out6 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
probe_out7 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
probe_out8 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
probe_out9 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
probe_out10 : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
@@ -70,10 +80,20 @@ END COMPONENT;
your_instance_name : vio_phase_comp
PORT MAP (
clk => clk,
probe_in0 => probe_in0,
probe_in1 => probe_in1,
probe_in2 => probe_in2,
probe_out0 => probe_out0,
probe_out1 => probe_out1,
probe_out2 => probe_out2,
probe_out3 => probe_out3
probe_out3 => probe_out3,
probe_out4 => probe_out4,
probe_out5 => probe_out5,
probe_out6 => probe_out6,
probe_out7 => probe_out7,
probe_out8 => probe_out8,
probe_out9 => probe_out9,
probe_out10 => probe_out10
);
-- INST_TAG_END ------ End INSTANTIATION Template ---------
projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_sim_netlist.v
LFS
BIN
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projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_sim_netlist.vhdl
LFS
BIN
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projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_stub.v
+20 -9
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@@ -1,10 +1,10 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Wed May 17 22:20:56 2023
// Date : Mon Jun 12 15:47:42 2023
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
// Command : write_verilog -force -mode synth_stub
// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.v
// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.v
// Design : vio_phase_comp
// Purpose : Stub declaration of top-level module interface
// Device : xc7k410tffg900-2
@@ -14,12 +14,23 @@
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
module vio_phase_comp(clk, probe_out0, probe_out1, probe_out2,
probe_out3)
/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[15:0],probe_out1[15:0],probe_out2[15:0],probe_out3[15:0]" */;
module vio_phase_comp(clk, probe_in0, probe_in1, probe_in2, probe_out0,
probe_out1, probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8,
probe_out9, probe_out10)
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[31:0],probe_in1[0:0],probe_in2[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[11:0],probe_out3[11:0],probe_out4[11:0],probe_out5[11:0],probe_out6[11:0],probe_out7[11:0],probe_out8[11:0],probe_out9[11:0],probe_out10[4:0]" */;
input clk;
output [15:0]probe_out0;
output [15:0]probe_out1;
output [15:0]probe_out2;
output [15:0]probe_out3;
input [31:0]probe_in0;
input [0:0]probe_in1;
input [0:0]probe_in2;
output [0:0]probe_out0;
output [0:0]probe_out1;
output [11:0]probe_out2;
output [11:0]probe_out3;
output [11:0]probe_out4;
output [11:0]probe_out5;
output [11:0]probe_out6;
output [11:0]probe_out7;
output [11:0]probe_out8;
output [11:0]probe_out9;
output [4:0]probe_out10;
endmodule
projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp/vio_phase_comp_stub.vhdl
+17 -7
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@@ -1,10 +1,10 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Wed May 17 22:20:56 2023
-- Date : Mon Jun 12 15:47:42 2023
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
-- Command : write_vhdl -force -mode synth_stub
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.vhdl
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.vhdl
-- Design : vio_phase_comp
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k410tffg900-2
@@ -15,10 +15,20 @@ use IEEE.STD_LOGIC_1164.ALL;
entity vio_phase_comp is
Port (
clk : in STD_LOGIC;
probe_out0 : out STD_LOGIC_VECTOR ( 15 downto 0 );
probe_out1 : out STD_LOGIC_VECTOR ( 15 downto 0 );
probe_out2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
probe_out3 : out STD_LOGIC_VECTOR ( 15 downto 0 )
probe_in0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out2 : out STD_LOGIC_VECTOR ( 11 downto 0 );
probe_out3 : out STD_LOGIC_VECTOR ( 11 downto 0 );
probe_out4 : out STD_LOGIC_VECTOR ( 11 downto 0 );
probe_out5 : out STD_LOGIC_VECTOR ( 11 downto 0 );
probe_out6 : out STD_LOGIC_VECTOR ( 11 downto 0 );
probe_out7 : out STD_LOGIC_VECTOR ( 11 downto 0 );
probe_out8 : out STD_LOGIC_VECTOR ( 11 downto 0 );
probe_out9 : out STD_LOGIC_VECTOR ( 11 downto 0 );
probe_out10 : out STD_LOGIC_VECTOR ( 4 downto 0 )
);
end vio_phase_comp;
@@ -27,7 +37,7 @@ architecture stub of vio_phase_comp is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[15:0],probe_out1[15:0],probe_out2[15:0],probe_out3[15:0]";
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[31:0],probe_in1[0:0],probe_in2[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[11:0],probe_out3[11:0],probe_out4[11:0],probe_out5[11:0],probe_out6[11:0],probe_out7[11:0],probe_out8[11:0],probe_out9[11:0],probe_out10[4:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
begin
projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd
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0HUsuBRSVmFNMyTzHRUEc9TihHMzkfPcsbaaBBV1W2TroM9sSzpM5dCgKJ9kFxFxiInPShuiMFzU
BusnTFj3irHB53mh+oTAlZXzeOZgoaythvBEzdmwGCK1H03lgltWCqw115f9q4KFi0nd1Qv6mqo7
+GL/YwY7KCPomFXh87vWGUYbWyyGlwlG73e20bXs3E3iCGdZfhgNDAKeZJVHkqEKbcMd+faQ6Z7o
8zgdlWul5f1o1AmuzVYSjVJQzV5tPfH8TIbCwfb0dkgYgThLk26meQweU5RpRhx67I9v2jdNE3ff
Ebqc6CAF/1ItmoNEKXWN36Z/xDSlXV1fu4Pz2Pq7C7HB7LEZtmvMTbOFC2vOuyO6DAl/aTA7D3aW
NxaYWWI+Pdp1t54aadWPv1fYTE0cydJMrcOmxpU9agDTbC8OxXbSX7GVvg4NUuyXJB8ZoLUI4pGw
BiuKUhAgtpyczOIHiLybxLg81LTI3KefMkJ+y4AV1zm7Owz6ouqZ8Gatmpc3+UeYyjlIyZ7ZflHt
CNjHx5pKufSCCFuYKCwzTqN4NfcY6fYM0rmdunYGd/PchaFK5o6qwiK7yboJv4K8Y21s5Ni2LmGQ
qKYEvar6pNuemQ5NRYH2ahvgqsY0ikDweU2SGusfQXuWEJHqD4evRs5vpC5idr2mDxDSwhM/61SP
QztsBt14ZqvqDk6IH+VrqRf11a3MGDwRpg89m7S0js52Ot9nrt+WUsr0wdDfia2g3V+xYeoybXyK
j7/XfbffrYSelPUJHJLEX2Z3czu9rXO/aQ2pm2rVgG6zGRA8+MLtZk2MSQsOKCXFbWkBz/s5NiXe
54LL27huT01nasvfvWV4VSgjD5OwHFVHH+IYl0q1IDm5lRRturrnGotw2afxgQOXo5qMjm6P1sGM
KbHybLf+puGCFh86aSHDOzDPaX3IyrAe70msFMG8nk5nMB8JhBnxvbYT02fHSAjjoLesJkeC1Bmg
pVX5m2/5jKiHogdJ/vzCvCTKAhIJVjpJo/p3kp5WcQtpn4iY/OGNXGpJdqrfEnuLsQzQUH0Okizv
KnmRsadIXQ==
`protect end_protected
projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd
+2392
View File
File diff suppressed because it is too large Load Diff
projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/README.txt
+1 -1
View File
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Sun May 21 16:31:40 CST 2023
# Generated by export_simulation on Mon Jun 12 15:47:25 CST 2023
#
################################################################################
projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/compile.do
+2 -2
View File
@@ -8,10 +8,10 @@ vmap xil_defaultlib activehdl/xil_defaultlib
vmap xpm activehdl/xpm
vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/vio_phase_comp/hdl/verilog" "+incdir+../../../ip/vio_phase_comp/hdl" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
vcom -work xpm -93 \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/vio_phase_comp/hdl/verilog" "+incdir+../../../ip/vio_phase_comp/hdl" \
"../../../ip/vio_phase_comp/sim/vio_phase_comp.v" \
projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/file_info.txt
+2 -2
View File
@@ -1,4 +1,4 @@
xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
xpm_memory.sv,systemverilog,xil_defaultlib,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
xpm_VCOMP.vhd,vhdl,xpm,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
vio_phase_comp.v,verilog,xil_defaultlib,../../../ip/vio_phase_comp/sim/vio_phase_comp.v,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
glbl.v,Verilog,xil_defaultlib,glbl.v
projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/activehdl/vio_phase_comp.sh
+1 -1
View File
@@ -9,7 +9,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Sun May 21 16:31:40 CST 2023
# Generated by Vivado on Mon Jun 12 15:47:25 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/ies/README.txt
+1 -1
View File
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Sun May 21 16:31:40 CST 2023
# Generated by export_simulation on Mon Jun 12 15:47:25 CST 2023
#
################################################################################
projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/ies/file_info.txt
+2 -2
View File
@@ -1,4 +1,4 @@
xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
xpm_memory.sv,systemverilog,xil_defaultlib,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
xpm_VCOMP.vhd,vhdl,xpm,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
vio_phase_comp.v,verilog,xil_defaultlib,../../../ip/vio_phase_comp/sim/vio_phase_comp.v,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
glbl.v,Verilog,xil_defaultlib,glbl.v
projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/ies/run.f
+2 -2
View File
@@ -1,8 +1,8 @@
-makelib ies_lib/xil_defaultlib -sv \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
-endlib
-makelib ies_lib/xpm \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
-endlib
-makelib ies_lib/xil_defaultlib \
"../../../ip/vio_phase_comp/sim/vio_phase_comp.v" \
projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/ies/vio_phase_comp.sh
+1 -1
View File
@@ -9,7 +9,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Sun May 21 16:31:40 CST 2023
# Generated by Vivado on Mon Jun 12 15:47:25 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/README.txt
+1 -1
View File
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Sun May 21 16:31:40 CST 2023
# Generated by export_simulation on Mon Jun 12 15:47:25 CST 2023
#
################################################################################
projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/compile.do
-8
View File
@@ -2,16 +2,8 @@ vlib modelsim_lib/work
vlib modelsim_lib/msim
vlib modelsim_lib/msim/xil_defaultlib
vlib modelsim_lib/msim/xpm
vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
vmap xpm modelsim_lib/msim/xpm
vlog -work xil_defaultlib -64 -incr -sv "+incdir+../../../ip/vio_phase_comp/hdl/verilog" "+incdir+../../../ip/vio_phase_comp/hdl" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
vcom -work xpm -64 -93 \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
vlog -work xil_defaultlib -64 -incr "+incdir+../../../ip/vio_phase_comp/hdl/verilog" "+incdir+../../../ip/vio_phase_comp/hdl" \
"../../../ip/vio_phase_comp/sim/vio_phase_comp.v" \
projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/file_info.txt
-2
View File
@@ -1,4 +1,2 @@
xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
vio_phase_comp.v,verilog,xil_defaultlib,../../../ip/vio_phase_comp/sim/vio_phase_comp.v,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
glbl.v,Verilog,xil_defaultlib,glbl.v
projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/simulate.do
+1 -1
View File
@@ -1,7 +1,7 @@
onbreak {quit -f}
onerror {quit -f}
vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.vio_phase_comp xil_defaultlib.glbl
vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.vio_phase_comp xil_defaultlib.glbl
do {wave.do}
projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/modelsim/vio_phase_comp.sh
+3 -4
View File
@@ -9,7 +9,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Sun May 21 16:31:40 CST 2023
# Generated by Vivado on Mon Jun 12 15:47:25 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
@@ -95,11 +95,10 @@ setup()
copy_setup_file()
{
file="modelsim.ini"
lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
if [[ ($1 != "" && -e $1) ]]; then
if [[ ($1 != "") ]]; then
lib_map_path="$1"
else
echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
lib_map_path="/home/josh/Software/Xilinx/CompLib/Model/2019.1"
fi
if [[ ($lib_map_path != "") ]]; then
src_file="$lib_map_path/$file"
projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/README.txt
+1 -1
View File
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Sun May 21 16:31:40 CST 2023
# Generated by export_simulation on Mon Jun 12 15:47:25 CST 2023
#
################################################################################
projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/compile.do
+2 -2
View File
@@ -8,10 +8,10 @@ vmap xil_defaultlib questa_lib/msim/xil_defaultlib
vmap xpm questa_lib/msim/xpm
vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/vio_phase_comp/hdl/verilog" "+incdir+../../../ip/vio_phase_comp/hdl" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
vcom -work xpm -64 -93 \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
vlog -work xil_defaultlib -64 "+incdir+../../../ip/vio_phase_comp/hdl/verilog" "+incdir+../../../ip/vio_phase_comp/hdl" \
"../../../ip/vio_phase_comp/sim/vio_phase_comp.v" \
projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/file_info.txt
+2 -2
View File
@@ -1,4 +1,4 @@
xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
xpm_memory.sv,systemverilog,xil_defaultlib,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
xpm_VCOMP.vhd,vhdl,xpm,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
vio_phase_comp.v,verilog,xil_defaultlib,../../../ip/vio_phase_comp/sim/vio_phase_comp.v,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
glbl.v,Verilog,xil_defaultlib,glbl.v
projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/questa/vio_phase_comp.sh
+3 -2
View File
@@ -9,7 +9,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Sun May 21 16:31:40 CST 2023
# Generated by Vivado on Mon Jun 12 15:47:25 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
@@ -102,9 +102,10 @@ setup()
copy_setup_file()
{
file="modelsim.ini"
lib_map_path=""
if [[ ($1 != "") ]]; then
lib_map_path="$1"
else
lib_map_path="/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa"
fi
if [[ ($lib_map_path != "") ]]; then
src_file="$lib_map_path/$file"
projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/README.txt
+1 -1
View File
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Sun May 21 16:31:40 CST 2023
# Generated by export_simulation on Mon Jun 12 15:47:25 CST 2023
#
################################################################################
projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/compile.do
+2 -2
View File
@@ -8,10 +8,10 @@ vmap xil_defaultlib riviera/xil_defaultlib
vmap xpm riviera/xpm
vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/vio_phase_comp/hdl/verilog" "+incdir+../../../ip/vio_phase_comp/hdl" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
vcom -work xpm -93 \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/vio_phase_comp/hdl/verilog" "+incdir+../../../ip/vio_phase_comp/hdl" \
"../../../ip/vio_phase_comp/sim/vio_phase_comp.v" \
projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/file_info.txt
+2 -2
View File
@@ -1,4 +1,4 @@
xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
xpm_memory.sv,systemverilog,xil_defaultlib,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
xpm_VCOMP.vhd,vhdl,xpm,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
vio_phase_comp.v,verilog,xil_defaultlib,../../../ip/vio_phase_comp/sim/vio_phase_comp.v,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
glbl.v,Verilog,xil_defaultlib,glbl.v
projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/riviera/vio_phase_comp.sh
+3 -2
View File
@@ -9,7 +9,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Sun May 21 16:31:40 CST 2023
# Generated by Vivado on Mon Jun 12 15:47:25 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
@@ -93,9 +93,10 @@ setup()
map_setup_file()
{
file="library.cfg"
lib_map_path=""
if [[ ($1 != "") ]]; then
lib_map_path="$1"
else
lib_map_path="/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera"
fi
if [[ ($lib_map_path != "") ]]; then
src_file="$lib_map_path/$file"
projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/vcs/README.txt
+1 -1
View File
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Sun May 21 16:31:40 CST 2023
# Generated by export_simulation on Mon Jun 12 15:47:25 CST 2023
#
################################################################################
projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/vcs/file_info.txt
-2
View File
@@ -1,4 +1,2 @@
xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
vio_phase_comp.v,verilog,xil_defaultlib,../../../ip/vio_phase_comp/sim/vio_phase_comp.v,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
glbl.v,Verilog,xil_defaultlib,glbl.v
projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/vcs/vio_phase_comp.sh
+4 -11
View File
@@ -9,7 +9,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Sun May 21 16:31:40 CST 2023
# Generated by Vivado on Mon Jun 12 15:47:25 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
@@ -48,7 +48,7 @@ vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log"
vcs_sim_opts="-ucli -licqueue -l simulate.log"
# Design libraries
design_libs=(xil_defaultlib xpm)
design_libs=(xil_defaultlib)
# Simulation root library directory
sim_lib_dir="vcs_lib"
@@ -70,14 +70,6 @@ run()
compile()
{
# Compile design files
vlogan -work xil_defaultlib $vlogan_opts -sverilog +incdir+"$ref_dir/../../../ip/vio_phase_comp/hdl/verilog" +incdir+"$ref_dir/../../../ip/vio_phase_comp/hdl" \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
2>&1 | tee -a vlogan.log
vhdlan -work xpm $vhdlan_opts \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
2>&1 | tee -a vhdlan.log
vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ip/vio_phase_comp/hdl/verilog" +incdir+"$ref_dir/../../../ip/vio_phase_comp/hdl" \
"$ref_dir/../../../ip/vio_phase_comp/sim/vio_phase_comp.v" \
2>&1 | tee -a vlogan.log
@@ -146,9 +138,10 @@ create_lib_mappings()
touch $file
lib_map_path=""
if [[ ($1 != "") ]]; then
lib_map_path="$1"
else
lib_map_path="/home/josh/Software/Xilinx/CompLib/VCS/2019.1"
fi
for (( i=0; i<${#design_libs[*]}; i++ )); do
projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xcelium/README.txt
+1 -1
View File
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Sun May 21 16:31:40 CST 2023
# Generated by export_simulation on Mon Jun 12 15:47:25 CST 2023
#
################################################################################
projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xcelium/file_info.txt
+2 -2
View File
@@ -1,4 +1,4 @@
xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
xpm_memory.sv,systemverilog,xil_defaultlib,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
xpm_VCOMP.vhd,vhdl,xpm,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
vio_phase_comp.v,verilog,xil_defaultlib,../../../ip/vio_phase_comp/sim/vio_phase_comp.v,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
glbl.v,Verilog,xil_defaultlib,glbl.v
projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xcelium/run.f
+2 -2
View File
@@ -1,8 +1,8 @@
-makelib xcelium_lib/xil_defaultlib -sv \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
-endlib
-makelib xcelium_lib/xpm \
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
-endlib
-makelib xcelium_lib/xil_defaultlib \
"../../../ip/vio_phase_comp/sim/vio_phase_comp.v" \
projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xcelium/vio_phase_comp.sh
+1 -1
View File
@@ -9,7 +9,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Sun May 21 16:31:40 CST 2023
# Generated by Vivado on Mon Jun 12 15:47:25 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xsim/README.txt
+1 -1
View File
@@ -4,7 +4,7 @@
# README.txt: Please read the sections below to understand the steps required to
# run the exported script and information about the source files.
#
# Generated by export_simulation on Sun May 21 16:31:40 CST 2023
# Generated by export_simulation on Mon Jun 12 15:47:25 CST 2023
#
################################################################################
projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/sim_scripts/vio_phase_comp/xsim/vio_phase_comp.sh
+3 -3
View File
@@ -9,7 +9,7 @@
# directory, add the library logical mappings in the simulator setup file, create default
# 'do/prj' file, execute compilation, elaboration and simulation steps.
#
# Generated by Vivado on Sun May 21 16:31:40 CST 2023
# Generated by Vivado on Mon Jun 12 15:47:25 CST 2023
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
#
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
@@ -22,7 +22,7 @@
#*********************************************************************************************************
# Command line options
xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0
xv_boost_lib_path=/home/josh/Software/Xilinx/Vivado/2019.1/tps/boost_1_64_0
xvlog_opts="--relax"
@@ -92,7 +92,7 @@ setup()
copy_setup_file()
{
file="xsim.ini"
lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim"
lib_map_path="/home/josh/Software/Xilinx/Vivado/2019.1/data/xsim"
if [[ ($1 != "") ]]; then
lib_map_path="$1"
fi
projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/199e9237e9cad44f/199e9237e9cad44f.xci
+810
View File
@@ -0,0 +1,810 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>ipcache</spirit:library>
<spirit:name>199e9237e9cad44f</spirit:name>
<spirit:version>0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>vio_phase_comp</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="vio" spirit:version="3.0"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EN_SYNCHRONIZATION">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PROBE_IN">3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PROBE_OUT">11</spirit:configurableElementValue>
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projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/199e9237e9cad44f/vio_phase_comp.dcp
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projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/199e9237e9cad44f/vio_phase_comp_sim_netlist.v
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projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/199e9237e9cad44f/vio_phase_comp_sim_netlist.vhdl
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projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/199e9237e9cad44f/vio_phase_comp_stub.v
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Mon Jun 12 15:47:42 2023
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_phase_comp_stub.v
// Design : vio_phase_comp
// Purpose : Stub declaration of top-level module interface
// Device : xc7k410tffg900-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_in0, probe_in1, probe_in2, probe_out0,
probe_out1, probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8,
probe_out9, probe_out10)
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[31:0],probe_in1[0:0],probe_in2[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[11:0],probe_out3[11:0],probe_out4[11:0],probe_out5[11:0],probe_out6[11:0],probe_out7[11:0],probe_out8[11:0],probe_out9[11:0],probe_out10[4:0]" */;
input clk;
input [31:0]probe_in0;
input [0:0]probe_in1;
input [0:0]probe_in2;
output [0:0]probe_out0;
output [0:0]probe_out1;
output [11:0]probe_out2;
output [11:0]probe_out3;
output [11:0]probe_out4;
output [11:0]probe_out5;
output [11:0]probe_out6;
output [11:0]probe_out7;
output [11:0]probe_out8;
output [11:0]probe_out9;
output [4:0]probe_out10;
endmodule
projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/199e9237e9cad44f/vio_phase_comp_stub.vhdl
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-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Mon Jun 12 15:47:42 2023
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_phase_comp_stub.vhdl
-- Design : vio_phase_comp
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k410tffg900-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clk : in STD_LOGIC;
probe_in0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out2 : out STD_LOGIC_VECTOR ( 11 downto 0 );
probe_out3 : out STD_LOGIC_VECTOR ( 11 downto 0 );
probe_out4 : out STD_LOGIC_VECTOR ( 11 downto 0 );
probe_out5 : out STD_LOGIC_VECTOR ( 11 downto 0 );
probe_out6 : out STD_LOGIC_VECTOR ( 11 downto 0 );
probe_out7 : out STD_LOGIC_VECTOR ( 11 downto 0 );
probe_out8 : out STD_LOGIC_VECTOR ( 11 downto 0 );
probe_out9 : out STD_LOGIC_VECTOR ( 11 downto 0 );
probe_out10 : out STD_LOGIC_VECTOR ( 4 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[31:0],probe_in1[0:0],probe_in2[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[11:0],probe_out3[11:0],probe_out4[11:0],probe_out5[11:0],probe_out6[11:0],probe_out7[11:0],probe_out8[11:0],probe_out9[11:0],probe_out10[4:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
begin
end;
projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6bc6069ea4e9d318/6bc6069ea4e9d318.xci
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projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6bc6069ea4e9d318/vio_phase_comp.dcp
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projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6bc6069ea4e9d318/vio_phase_comp_stub.v
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Sun Jun 11 17:20:35 2023
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_phase_comp_stub.v
// Design : vio_phase_comp
// Purpose : Stub declaration of top-level module interface
// Device : xc7k410tffg900-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_in0, probe_out0, probe_out1,
probe_out2, probe_out3, probe_out4)
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[31:0],probe_out0[15:0],probe_out1[15:0],probe_out2[15:0],probe_out3[15:0],probe_out4[0:0]" */;
input clk;
input [31:0]probe_in0;
output [15:0]probe_out0;
output [15:0]probe_out1;
output [15:0]probe_out2;
output [15:0]probe_out3;
output [0:0]probe_out4;
endmodule
projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6bc6069ea4e9d318/vio_phase_comp_stub.vhdl
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-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Sun Jun 11 17:20:35 2023
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_phase_comp_stub.vhdl
-- Design : vio_phase_comp
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k410tffg900-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clk : in STD_LOGIC;
probe_in0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
probe_out0 : out STD_LOGIC_VECTOR ( 15 downto 0 );
probe_out1 : out STD_LOGIC_VECTOR ( 15 downto 0 );
probe_out2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
probe_out3 : out STD_LOGIC_VECTOR ( 15 downto 0 );
probe_out4 : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[31:0],probe_out0[15:0],probe_out1[15:0],probe_out2[15:0],probe_out3[15:0],probe_out4[0:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
begin
end;
projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6c756528e746e3c7/6c756528e746e3c7.xci
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projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6c756528e746e3c7/vio_phase_comp.dcp
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Mon Jun 12 14:39:21 2023
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_phase_comp_stub.v
// Design : vio_phase_comp
// Purpose : Stub declaration of top-level module interface
// Device : xc7k410tffg900-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_in0, probe_in1, probe_in2, probe_out0,
probe_out1, probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8,
probe_out9)
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[31:0],probe_in1[0:0],probe_in2[0:0],probe_out0[0:0],probe_out1[11:0],probe_out2[11:0],probe_out3[11:0],probe_out4[11:0],probe_out5[11:0],probe_out6[11:0],probe_out7[11:0],probe_out8[11:0],probe_out9[4:0]" */;
input clk;
input [31:0]probe_in0;
input [0:0]probe_in1;
input [0:0]probe_in2;
output [0:0]probe_out0;
output [11:0]probe_out1;
output [11:0]probe_out2;
output [11:0]probe_out3;
output [11:0]probe_out4;
output [11:0]probe_out5;
output [11:0]probe_out6;
output [11:0]probe_out7;
output [11:0]probe_out8;
output [4:0]probe_out9;
endmodule
projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6c756528e746e3c7/vio_phase_comp_stub.vhdl
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-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Mon Jun 12 14:39:21 2023
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_phase_comp_stub.vhdl
-- Design : vio_phase_comp
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k410tffg900-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clk : in STD_LOGIC;
probe_in0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_in2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
probe_out1 : out STD_LOGIC_VECTOR ( 11 downto 0 );
probe_out2 : out STD_LOGIC_VECTOR ( 11 downto 0 );
probe_out3 : out STD_LOGIC_VECTOR ( 11 downto 0 );
probe_out4 : out STD_LOGIC_VECTOR ( 11 downto 0 );
probe_out5 : out STD_LOGIC_VECTOR ( 11 downto 0 );
probe_out6 : out STD_LOGIC_VECTOR ( 11 downto 0 );
probe_out7 : out STD_LOGIC_VECTOR ( 11 downto 0 );
probe_out8 : out STD_LOGIC_VECTOR ( 11 downto 0 );
probe_out9 : out STD_LOGIC_VECTOR ( 4 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[31:0],probe_in1[0:0],probe_in2[0:0],probe_out0[0:0],probe_out1[11:0],probe_out2[11:0],probe_out3[11:0],probe_out4[11:0],probe_out5[11:0],probe_out6[11:0],probe_out7[11:0],probe_out8[11:0],probe_out9[4:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
begin
end;
projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/7ceac1c5ccccf5df/7ceac1c5ccccf5df.xci
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:name>7ceac1c5ccccf5df</spirit:name>
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<spirit:instanceName>cmpy_18x18</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="cmpy" spirit:version="6.0"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACLKEN">false</spirit:configurableElementValue>
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projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/7ceac1c5ccccf5df/cmpy_18x18.dcp
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projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/7ceac1c5ccccf5df/cmpy_18x18_stub.v
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Sun Jun 11 14:38:07 2023
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ cmpy_18x18_stub.v
// Design : cmpy_18x18
// Purpose : Stub declaration of top-level module interface
// Device : xc7k410tffg900-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "cmpy_v6_0_17,Vivado 2019.1.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, s_axis_a_tvalid, s_axis_a_tdata,
s_axis_b_tvalid, s_axis_b_tdata, m_axis_dout_tvalid, m_axis_dout_tdata)
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_a_tvalid,s_axis_a_tdata[47:0],s_axis_b_tvalid,s_axis_b_tdata[47:0],m_axis_dout_tvalid,m_axis_dout_tdata[79:0]" */;
input aclk;
input s_axis_a_tvalid;
input [47:0]s_axis_a_tdata;
input s_axis_b_tvalid;
input [47:0]s_axis_b_tdata;
output m_axis_dout_tvalid;
output [79:0]m_axis_dout_tdata;
endmodule
projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/7ceac1c5ccccf5df/cmpy_18x18_stub.vhdl
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-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Sun Jun 11 14:38:07 2023
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ cmpy_18x18_stub.vhdl
-- Design : cmpy_18x18
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k410tffg900-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
aclk : in STD_LOGIC;
s_axis_a_tvalid : in STD_LOGIC;
s_axis_a_tdata : in STD_LOGIC_VECTOR ( 47 downto 0 );
s_axis_b_tvalid : in STD_LOGIC;
s_axis_b_tdata : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axis_dout_tvalid : out STD_LOGIC;
m_axis_dout_tdata : out STD_LOGIC_VECTOR ( 79 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_a_tvalid,s_axis_a_tdata[47:0],s_axis_b_tvalid,s_axis_b_tdata[47:0],m_axis_dout_tvalid,m_axis_dout_tdata[79:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "cmpy_v6_0_17,Vivado 2019.1.3";
begin
end;
projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c8b4974eb08248f9/c8b4974eb08248f9.xci
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<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>ipcache</spirit:library>
<spirit:name>c8b4974eb08248f9</spirit:name>
<spirit:version>0</spirit:version>
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<spirit:instanceName>vio_phase_comp</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="vio" spirit:version="3.0"/>
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projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c8b4974eb08248f9/vio_phase_comp.dcp
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projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c8b4974eb08248f9/vio_phase_comp_sim_netlist.v
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projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c8b4974eb08248f9/vio_phase_comp_sim_netlist.vhdl
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projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c8b4974eb08248f9/vio_phase_comp_stub.v
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Sun Jun 11 17:23:44 2023
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_phase_comp_stub.v
// Design : vio_phase_comp
// Purpose : Stub declaration of top-level module interface
// Device : xc7k410tffg900-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_in0, probe_in1, probe_out0,
probe_out1, probe_out2, probe_out3, probe_out4)
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[31:0],probe_in1[0:0],probe_out0[15:0],probe_out1[15:0],probe_out2[15:0],probe_out3[15:0],probe_out4[0:0]" */;
input clk;
input [31:0]probe_in0;
input [0:0]probe_in1;
output [15:0]probe_out0;
output [15:0]probe_out1;
output [15:0]probe_out2;
output [15:0]probe_out3;
output [0:0]probe_out4;
endmodule
projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/c8b4974eb08248f9/vio_phase_comp_stub.vhdl
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-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Sun Jun 11 17:23:44 2023
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_phase_comp_stub.vhdl
-- Design : vio_phase_comp
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k410tffg900-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clk : in STD_LOGIC;
probe_in0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe_out0 : out STD_LOGIC_VECTOR ( 15 downto 0 );
probe_out1 : out STD_LOGIC_VECTOR ( 15 downto 0 );
probe_out2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
probe_out3 : out STD_LOGIC_VECTOR ( 15 downto 0 );
probe_out4 : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[31:0],probe_in1[0:0],probe_out0[15:0],probe_out1[15:0],probe_out2[15:0],probe_out3[15:0],probe_out4[0:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
begin
end;
projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf
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projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml
+22 -21
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@@ -3,7 +3,7 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Sun May 21 16:32:31 2023">
<application name="pa" timeStamp="Mon Jun 12 15:47:48 2023">
<section name="Project Information" visible="false">
<property name="ProjectID" value="ce818763e31a4de8ac7850431f15fb5a" type="ProjectID"/>
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
@@ -17,49 +17,50 @@ This means code written to parse this file will need to be revisited each subseq
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
</item>
<item name="Java Command Handlers">
<property name="AddExistingIPHandler" value="4" type="JavaHandler"/>
<property name="CloseProject" value="5" type="JavaHandler"/>
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<property name="EditDelete" value="7" type="JavaHandler"/>
<property name="ManageCompositeTargets" value="3" type="JavaHandler"/>
<property name="NewIPLocationHandler" value="1" type="JavaHandler"/>
<property name="OpenIPLocationHandler" value="3" type="JavaHandler"/>
<property name="OpenIPLocationHandler" value="7" type="JavaHandler"/>
<property name="OpenPreviousIPHandler" value="9" type="JavaHandler"/>
<property name="RecustomizeCore" value="20" type="JavaHandler"/>
<property name="RecustomizeCore" value="27" type="JavaHandler"/>
</item>
<item name="Gui Handlers">
<property name="BaseDialog_CANCEL" value="10" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="30" type="GuiHandlerData"/>
<property name="BaseDialog_CANCEL" value="16" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="39" type="GuiHandlerData"/>
<property name="CopyIPHandler_DESTINATION_IP_NAME" value="3" type="GuiHandlerData"/>
<property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="4" type="GuiHandlerData"/>
<property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="10" type="GuiHandlerData"/>
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="10" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="104" type="GuiHandlerData"/>
<property name="GettingStartedView_MANAGE_IP" value="4" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="137" type="GuiHandlerData"/>
<property name="GettingStartedView_MANAGE_IP" value="8" type="GuiHandlerData"/>
<property name="GettingStartedView_START_USING_VIVADO_WITH_IP_CATALOG" value="1" type="GuiHandlerData"/>
<property name="HACGCCoeFileWidget_BROWSE" value="1" type="GuiHandlerData"/>
<property name="HJFileChooserHelpers_JUMP_TO_RECENT_PROJECT_DIRECTORY" value="1" type="GuiHandlerData"/>
<property name="IPCoreView_TABBED_PANE" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_FILE" value="10" type="GuiHandlerData"/>
<property name="MainMenuMgr_EDIT" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_FILE" value="20" type="GuiHandlerData"/>
<property name="MainMenuMgr_OPEN_RECENT_PROJECT" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_PROJECT" value="6" type="GuiHandlerData"/>
<property name="MainMenuMgr_PROJECT" value="10" type="GuiHandlerData"/>
<property name="NewIPProjectWizard_IP_LOCATION" value="1" type="GuiHandlerData"/>
<property name="NewIPProjectWizard_PART" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_ADD_EXISTING_IP" value="4" type="GuiHandlerData"/>
<property name="PACommandNames_CLOSE_PROJECT" value="5" type="GuiHandlerData"/>
<property name="PACommandNames_ADD_EXISTING_IP" value="5" type="GuiHandlerData"/>
<property name="PACommandNames_CLOSE_PROJECT" value="9" type="GuiHandlerData"/>
<property name="PACommandNames_COPY_IP" value="3" type="GuiHandlerData"/>
<property name="PACommandNames_GENERATE_COMPOSITE_FILE" value="3" type="GuiHandlerData"/>
<property name="PACommandNames_OPEN_IP_LOCATION" value="3" type="GuiHandlerData"/>
<property name="RemoveSourcesDialog_ALSO_DELETE" value="6" type="GuiHandlerData"/>
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="15" type="GuiHandlerData"/>
<property name="PACommandNames_OPEN_IP_LOCATION" value="7" type="GuiHandlerData"/>
<property name="RemoveSourcesDialog_ALSO_DELETE" value="7" type="GuiHandlerData"/>
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="20" type="GuiHandlerData"/>
<property name="SrcChooserPanel_ADD_CONFIGURABLE_IP_FILES" value="5" type="GuiHandlerData"/>
<property name="SrcMenu_IP_DOCUMENTATION" value="5" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_IP_LOCATIONS" value="9" type="GuiHandlerData"/>
</item>
<item name="Other">
<property name="GuiMode" value="144" type="GuiMode"/>
<property name="GuiMode" value="11" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="101" type="TclMode"/>
<property name="TclMode" value="6" type="TclMode"/>
</item>
</section>
</application>
projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_13.xml
+8
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@@ -0,0 +1,8 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="cmpy_18x18_synth_1" LaunchDir="/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x18_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>
projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_14.xml
+8
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@@ -0,0 +1,8 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="vio_phase_comp_synth_1" LaunchDir="/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>
projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_15.xml
+8
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@@ -0,0 +1,8 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="vio_phase_comp_synth_1" LaunchDir="/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>
projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_16.xml
+8
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@@ -0,0 +1,8 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="vio_phase_comp_synth_1" LaunchDir="/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>
projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_17.xml
+8
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@@ -0,0 +1,8 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="vio_phase_comp_synth_1" LaunchDir="/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>
projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/gen_run.xml
+1 -1
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@@ -1,9 +1,9 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="vio_manual_ctrl_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1682237933">
<File Type="PA-TCL" Name="vio_manual_ctrl.tcl"/>
<File Type="RDS-DCP" Name="vio_manual_ctrl.dcp"/>
<File Type="REPORTS-TCL" Name="vio_manual_ctrl_reports.tcl"/>
<File Type="RDS-RDS" Name="vio_manual_ctrl.vds"/>
<File Type="RDS-DCP" Name="vio_manual_ctrl.dcp"/>
<File Type="RDS-UTIL-PB" Name="vio_manual_ctrl_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="vio_manual_ctrl_utilization_synth.rpt"/>
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_manual_ctrl">
projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/.Vivado_Synthesis.queue.rst
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projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/.vivado.begin.rst
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<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command="vivado" Owner="josh" Host="JOSH-ASUS-Z690" Pid="2733262" HostCore="20" HostMemory="65588992">
</Process>
</ProcessHandle>
projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/.vivado.end.rst
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projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/ISEWrap.js
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//
// Vivado(TM)
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved.
//
// GLOBAL VARIABLES
var ISEShell = new ActiveXObject( "WScript.Shell" );
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
var ISERunDir = "";
var ISELogFile = "runme.log";
var ISELogFileStr = null;
var ISELogEcho = true;
var ISEOldVersionWSH = false;
// BOOTSTRAP
ISEInit();
//
// ISE FUNCTIONS
//
function ISEInit() {
// 1. RUN DIR setup
var ISEScrFP = WScript.ScriptFullName;
var ISEScrN = WScript.ScriptName;
ISERunDir =
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
// 2. LOG file setup
ISELogFileStr = ISEOpenFile( ISELogFile );
// 3. LOG echo?
var ISEScriptArgs = WScript.Arguments;
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
if ( ISEScriptArgs(loopi) == "-quiet" ) {
ISELogEcho = false;
break;
}
}
// 4. WSH version check
var ISEOptimalVersionWSH = 5.6;
var ISECurrentVersionWSH = WScript.Version;
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
ISEStdErr( "" );
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
ISEOptimalVersionWSH + " or higher. Downloads" );
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
ISEStdErr( "" );
ISEOldVersionWSH = true;
}
}
function ISEStep( ISEProg, ISEArgs ) {
// CHECK for a STOP FILE
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
ISEStdErr( "" );
ISEStdErr( "*** Halting run - EA reset detected ***" );
ISEStdErr( "" );
WScript.Quit( 1 );
}
// WRITE STEP HEADER to LOG
ISEStdOut( "" );
ISEStdOut( "*** Running " + ISEProg );
ISEStdOut( " with args " + ISEArgs );
ISEStdOut( "" );
// LAUNCH!
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
if ( ISEExitCode != 0 ) {
WScript.Quit( ISEExitCode );
}
}
function ISEExec( ISEProg, ISEArgs ) {
var ISEStep = ISEProg;
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
ISEProg += ".bat";
}
var ISECmdLine = ISEProg + " " + ISEArgs;
var ISEExitCode = 1;
if ( ISEOldVersionWSH ) { // WSH 5.1
// BEGIN file creation
ISETouchFile( ISEStep, "begin" );
// LAUNCH!
ISELogFileStr.Close();
ISECmdLine =
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
ISELogFileStr = ISEOpenFile( ISELogFile );
} else { // WSH 5.6
// LAUNCH!
ISEShell.CurrentDirectory = ISERunDir;
// Redirect STDERR to STDOUT
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
var ISEProcess = ISEShell.Exec( ISECmdLine );
// BEGIN file creation
var wbemFlagReturnImmediately = 0x10;
var wbemFlagForwardOnly = 0x20;
var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
var NOC = 0;
var NOLP = 0;
var TPM = 0;
var cpuInfos = new Enumerator(processor);
for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
var cpuInfo = cpuInfos.item();
NOC += cpuInfo.NumberOfCores;
NOLP += cpuInfo.NumberOfLogicalProcessors;
}
var csInfos = new Enumerator(computerSystem);
for(;!csInfos.atEnd(); csInfos.moveNext()) {
var csInfo = csInfos.item();
TPM += csInfo.TotalPhysicalMemory;
}
var ISEHOSTCORE = NOLP
var ISEMEMTOTAL = TPM
var ISENetwork = WScript.CreateObject( "WScript.Network" );
var ISEHost = ISENetwork.ComputerName;
var ISEUser = ISENetwork.UserName;
var ISEPid = ISEProcess.ProcessID;
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
"\" Owner=\"" + ISEUser +
"\" Host=\"" + ISEHost +
"\" Pid=\"" + ISEPid +
"\" HostCore=\"" + ISEHOSTCORE +
"\" HostMemory=\"" + ISEMEMTOTAL +
"\">" );
ISEBeginFile.WriteLine( " </Process>" );
ISEBeginFile.WriteLine( "</ProcessHandle>" );
ISEBeginFile.Close();
var ISEOutStr = ISEProcess.StdOut;
var ISEErrStr = ISEProcess.StdErr;
// WAIT for ISEStep to finish
while ( ISEProcess.Status == 0 ) {
// dump stdout then stderr - feels a little arbitrary
while ( !ISEOutStr.AtEndOfStream ) {
ISEStdOut( ISEOutStr.ReadLine() );
}
WScript.Sleep( 100 );
}
ISEExitCode = ISEProcess.ExitCode;
}
ISELogFileStr.Close();
// END/ERROR file creation
if ( ISEExitCode != 0 ) {
ISETouchFile( ISEStep, "error" );
} else {
ISETouchFile( ISEStep, "end" );
}
return ISEExitCode;
}
//
// UTILITIES
//
function ISEStdOut( ISELine ) {
ISELogFileStr.WriteLine( ISELine );
if ( ISELogEcho ) {
WScript.StdOut.WriteLine( ISELine );
}
}
function ISEStdErr( ISELine ) {
ISELogFileStr.WriteLine( ISELine );
if ( ISELogEcho ) {
WScript.StdErr.WriteLine( ISELine );
}
}
function ISETouchFile( ISERoot, ISEStatus ) {
var ISETFile =
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
ISETFile.Close();
}
function ISEOpenFile( ISEFilename ) {
// This function has been updated to deal with a problem seen in CR #870871.
// In that case the user runs a script that runs impl_1, and then turns around
// and runs impl_1 -to_step write_bitstream. That second run takes place in
// the same directory, which means we may hit some of the same files, and in
// particular, we will open the runme.log file. Even though this script closes
// the file (now), we see cases where a subsequent attempt to open the file
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
// play? In any case, we try to work around this by first waiting if the file
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
// and try to open the file 10 times with a one second delay after each attempt.
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
// If there is an unrecognized exception when trying to open the file, we output
// an error message and write details to an exception.log file.
var ISEFullPath = ISERunDir + "/" + ISEFilename;
if (ISEFileSys.FileExists(ISEFullPath)) {
// File is already there. This could be a problem. Wait in case it is still in use.
WScript.Sleep(5000);
}
var i;
for (i = 0; i < 10; ++i) {
try {
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
} catch (exception) {
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
if (error_code == 52) { // 52 is bad file name or number.
// Wait a second and try again.
WScript.Sleep(1000);
continue;
} else {
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
var exceptionFilePath = ISERunDir + "/exception.log";
if (!ISEFileSys.FileExists(exceptionFilePath)) {
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
exceptionFile.WriteLine("\tException name: " + exception.name);
exceptionFile.WriteLine("\tException error code: " + error_code);
exceptionFile.WriteLine("\tException message: " + exception.message);
exceptionFile.Close();
}
throw exception;
}
}
}
// If we reached this point, we failed to open the file after 10 attempts.
// We need to error out.
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
WScript.Quit(1);
}
projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/ISEWrap.sh
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#!/bin/sh
#
# Vivado(TM)
# ISEWrap.sh: Vivado Runs Script for UNIX
# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
#
HD_LOG=$1
shift
# CHECK for a STOP FILE
if [ -f .stop.rst ]
then
echo "" >> $HD_LOG
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
echo "" >> $HD_LOG
exit 1
fi
ISE_STEP=$1
shift
# WRITE STEP HEADER to LOG
echo "" >> $HD_LOG
echo "*** Running $ISE_STEP" >> $HD_LOG
echo " with args $@" >> $HD_LOG
echo "" >> $HD_LOG
# LAUNCH!
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
# BEGIN file creation
ISE_PID=$!
if [ X != X$HOSTNAME ]
then
ISE_HOST=$HOSTNAME #bash
else
ISE_HOST=$HOST #csh
fi
ISE_USER=$USER
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
ISE_BEGINFILE=.$ISE_STEP.begin.rst
/bin/touch $ISE_BEGINFILE
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
echo " </Process>" >> $ISE_BEGINFILE
echo "</ProcessHandle>" >> $ISE_BEGINFILE
# WAIT for ISEStep to finish
wait $ISE_PID
# END/ERROR file creation
RETVAL=$?
if [ $RETVAL -eq 0 ]
then
/bin/touch .$ISE_STEP.end.rst
else
/bin/touch .$ISE_STEP.error.rst
fi
exit $RETVAL
projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/__synthesis_is_complete__
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projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/gen_run.xml
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<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="vio_phase_comp_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1686556045">
<File Type="VDS-TIMING-PB" Name="vio_phase_comp_timing_summary_synth.pb"/>
<File Type="VDS-TIMINGSUMMARY" Name="vio_phase_comp_timing_summary_synth.rpt"/>
<File Type="RDS-DCP" Name="vio_phase_comp.dcp"/>
<File Type="RDS-UTIL-PB" Name="vio_phase_comp_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="vio_phase_comp_utilization_synth.rpt"/>
<File Type="RDS-PROPCONSTRS" Name="vio_phase_comp_drc_synth.rpt"/>
<File Type="RDS-RDS" Name="vio_phase_comp.vds"/>
<File Type="REPORTS-TCL" Name="vio_phase_comp_reports.tcl"/>
<File Type="PA-TCL" Name="vio_phase_comp.tcl"/>
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_phase_comp">
<File Path="$PPRDIR/../rx_pre_process/vio_phase_comp.xcix">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../rx_pre_process/vio_phase_comp/vio_phase_comp.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="vio_phase_comp"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="constrs_in" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_phase_comp">
<File Path="$PPRDIR/../rx_pre_process/vio_phase_comp.xcix">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../rx_pre_process/vio_phase_comp/vio_phase_comp.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="vio_phase_comp"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
</GenRun>
projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/htr.txt
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#
# Vivado(TM)
# htr.txt: a Vivado-generated description of how-to-repeat the
# the basic steps of a run. Note that runme.bat/sh needs
# to be invoked for Vivado to track run status.
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
#
vivado -log vio_phase_comp.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_phase_comp.tcl
projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/project.wdf
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version:1
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00
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70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:35:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:35:00:00
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70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
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70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f6d616e75616c5f6374726c:636f72655f636f6e7461696e6572:74727565:00:00
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f70686173655f636f6d70:636f72655f636f6e7461696e6572:74727565:00:00
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70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
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70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
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70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3234:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3234:00:00
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70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3234:00:00
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eof:2331005995
projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/rundef.js
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//
// Vivado(TM)
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
//
echo "This script was generated under a different operating system."
echo "Please update the PATH variable below, before executing this script"
exit
var WshShell = new ActiveXObject( "WScript.Shell" );
var ProcEnv = WshShell.Environment( "Process" );
var PathVal = ProcEnv("PATH");
if ( PathVal.length == 0 ) {
PathVal = "/home/josh/Software/Xilinx/SDK/2019.1/bin:/home/josh/Software/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/home/josh/Software/Xilinx/Vivado/2019.1/bin;";
} else {
PathVal = "/home/josh/Software/Xilinx/SDK/2019.1/bin:/home/josh/Software/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/home/josh/Software/Xilinx/Vivado/2019.1/bin;" + PathVal;
}
ProcEnv("PATH") = PathVal;
var RDScrFP = WScript.ScriptFullName;
var RDScrN = WScript.ScriptName;
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
eval( EAInclude(ISEJScriptLib) );
ISEStep( "vivado",
"-log vio_phase_comp.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_phase_comp.tcl" );
function EAInclude( EAInclFilename ) {
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
var EAIFContents = EAInclFile.ReadAll();
EAInclFile.Close();
return EAIFContents;
}
projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/runme.bat
+11
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@echo off
rem Vivado (TM)
rem runme.bat: a Vivado-generated Script
rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
set HD_SDIR=%~dp0
cd /d "%HD_SDIR%"
set PATH=%SYSTEMROOT%\system32;%PATH%
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*

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