Archived
change rotate to radians, fix phase comp port connections
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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// --------------------------------------------------------------------------------
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// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
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// Date : Wed Apr 12 20:00:12 2023
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// Date : Mon Jun 5 20:29:00 2023
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// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
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// Command : write_verilog -force -mode synth_stub
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// /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_stub.v
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@@ -1,7 +1,7 @@
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-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Wed Apr 12 20:00:12 2023
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-- Date : Mon Jun 5 20:29:01 2023
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-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
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-- Command : write_vhdl -force -mode synth_stub
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-- /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_stub.vhdl
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@@ -0,0 +1,376 @@
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--------------------------------------------------------------------------------
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||||
-- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--------------------------------------------------------------------------------
|
||||
-- Description:
|
||||
-- This is an example testbench for the CORDIC IP core.
|
||||
-- The testbench has been generated by Vivado to accompany the IP core
|
||||
-- instance you have generated.
|
||||
--
|
||||
-- This testbench is for demonstration purposes only. See note below for
|
||||
-- instructions on how to use it with your core.
|
||||
--
|
||||
-- See the CORDIC product guide for further information
|
||||
-- about this core.
|
||||
--
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||||
--------------------------------------------------------------------------------
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||||
-- Using this testbench
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--
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-- This testbench instantiates your generated CORDIC core
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-- instance named "atan2_16b".
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--
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-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado
|
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-- documentation for details.
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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entity tb_atan2_16b is
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end tb_atan2_16b;
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architecture tb of tb_atan2_16b is
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-----------------------------------------------------------------------
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-- Timing constants
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-----------------------------------------------------------------------
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constant CLOCK_PERIOD : time := 100 ns;
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constant T_HOLD : time := 10 ns;
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constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
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constant TEST_CYCLES : integer := 3000;
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constant PHASE_CYCLES : integer := 1000;
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-----------------------------------------------------------------------
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||||
-- DUT input signals
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-----------------------------------------------------------------------
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-- General inputs
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signal aclk : std_logic := '0'; -- the master clock
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-- Slave channel CARTESIAN inputs
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signal s_axis_cartesian_tvalid : std_logic := '0'; -- TVALID for channel S_AXIS_CARTESIAN
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signal s_axis_cartesian_tdata : std_logic_vector(31 downto 0) := (others => 'X'); -- TDATA for channel S_AXIS_CARTESIAN
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-- Slave channel PHASE inputs
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signal s_axis_phase_tvalid : std_logic := '0'; -- TVALID for channel S_AXIS_PHASE
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signal s_axis_phase_tdata : std_logic_vector(15 downto 0) := (others => 'X'); -- TDATA for channel S_AXIS_PHASE
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-----------------------------------------------------------------------
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-- DUT output signals
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-----------------------------------------------------------------------
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-- Master channel DOUT outputs
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signal m_axis_dout_tvalid : std_logic := '0'; -- TVALID for channel M_AXIS_DOUT
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signal m_axis_dout_tdata : std_logic_vector(15 downto 0) := (others => '0'); -- TDATA for channel M_AXIS_DOUT
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-----------------------------------------------------------------------
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-- Aliases for AXI channel TDATA fields
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-- These are a convenience for viewing data in a simulator waveform viewer.
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-- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
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-- to prevent the simulator optimizing away these signals.
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-----------------------------------------------------------------------
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signal s_axis_cartesian_tdata_real : std_logic_vector(15 downto 0) := (others => '0');
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signal s_axis_cartesian_tdata_imag : std_logic_vector(15 downto 0) := (others => '0');
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signal s_axis_phase_tdata_real : std_logic_vector(15 downto 0) := (others => '0');
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signal m_axis_dout_tdata_real : std_logic_vector(15 downto 0) := (others => '0');
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signal m_axis_dout_tdata_imag : std_logic_vector(15 downto 0) := (others => '0');
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signal m_axis_dout_tdata_phase : std_logic_vector(15 downto 0) := (others => '0');
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-----------------------------------------------------------------------
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-- Testbench signals
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-----------------------------------------------------------------------
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signal cycles : integer := 0; -- Clock cycle counter
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-----------------------------------------------------------------------
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-- Constants, types and functions to create input data
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-- The CORDIC is fed two sinusoids exp(+/-jwt) of different frequencies and amplitudes:
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-- channel CARTESIAN: exp(+jwt), frequency = clock / 30,
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-- channel PHASE: exp(-jwt), frequency = clock / 32,
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-----------------------------------------------------------------------
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constant IP_CARTESIAN_DEPTH : integer := 30;
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constant IP_CARTESIAN_WIDTH : integer := 16;
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constant IP_CARTESIAN_SHIFT : integer := 3; -- bit shift for amplitude
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constant IP_PHASE_DEPTH : integer := 32;
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constant IP_PHASE_WIDTH : integer := 16;
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constant IP_PHASE_SHIFT : integer := 0; -- no bit shift, max amplitude
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type T_IP_INT_ENTRY is record
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re : integer;
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im : integer;
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end record;
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type T_IP_CARTESIAN_ENTRY is record
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re : std_logic_vector(IP_CARTESIAN_WIDTH-1 downto 0);
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im : std_logic_vector(IP_CARTESIAN_WIDTH-1 downto 0);
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end record;
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type T_IP_PHASE_ENTRY is record
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re : std_logic_vector(IP_PHASE_WIDTH-1 downto 0);
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end record;
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type T_IP_CARTESIAN_TABLE is array (0 to IP_CARTESIAN_DEPTH-1) of T_IP_CARTESIAN_ENTRY;
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type T_IP_PHASE_TABLE is array (0 to IP_PHASE_DEPTH-1) of T_IP_PHASE_ENTRY;
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-- Common function to calculate sine and cosine values
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function create_ip_entry(index, depth, width : integer) return T_IP_INT_ENTRY is
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variable result : T_IP_INT_ENTRY;
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variable theta : real;
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variable limited_width : integer := width - 2;
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begin
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if limited_width > 30 then
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limited_width := 30; --avoid integer overflow
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end if;
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theta := real(index) / real(depth) * 2.0 * MATH_PI;
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result.re := integer(round(cos(theta) * real(2**limited_width)));
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result.im := integer(round(sin(theta) * real(2**limited_width)));
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return result;
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end function create_ip_entry;
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-- Use separate functions to calculate channel S_AXIS_CARTESIAN and S_AXIS_PHASE sinusoids as they return different types
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function create_ip_cartesian_table return T_IP_CARTESIAN_TABLE is
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variable result : T_IP_CARTESIAN_TABLE;
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variable entry_int : T_IP_INT_ENTRY;
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begin
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for i in 0 to IP_CARTESIAN_DEPTH-1 loop
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entry_int := create_ip_entry(i, IP_CARTESIAN_DEPTH, IP_CARTESIAN_WIDTH - IP_CARTESIAN_SHIFT);
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result(i).re := std_logic_vector(to_signed(entry_int.re, IP_CARTESIAN_WIDTH));
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result(i).im := std_logic_vector(to_signed(entry_int.im, IP_CARTESIAN_WIDTH));
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end loop;
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return result;
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end function create_ip_cartesian_table;
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function create_ip_phase_table return T_IP_PHASE_TABLE is
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variable result : T_IP_PHASE_TABLE;
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variable entry_int : T_IP_INT_ENTRY;
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begin
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for i in 0 to IP_PHASE_DEPTH-1 loop
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entry_int := create_ip_entry(IP_PHASE_DEPTH-1-i, IP_PHASE_DEPTH, IP_PHASE_WIDTH - IP_PHASE_SHIFT); -- note rotation direction
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result(i).re := std_logic_vector(to_signed(entry_int.re, IP_PHASE_WIDTH));
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end loop;
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return result;
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end function create_ip_phase_table;
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-- Call the functions to create the data
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constant IP_CARTESIAN_DATA : T_IP_CARTESIAN_TABLE := create_ip_cartesian_table;
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constant IP_PHASE_DATA : T_IP_PHASE_TABLE := create_ip_phase_table;
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begin
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-----------------------------------------------------------------------
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-- Instantiate the DUT
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-----------------------------------------------------------------------
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dut : entity work.atan2_16b
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port map (
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aclk => aclk,
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s_axis_cartesian_tvalid => s_axis_cartesian_tvalid,
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s_axis_cartesian_tdata => s_axis_cartesian_tdata,
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m_axis_dout_tvalid => m_axis_dout_tvalid,
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m_axis_dout_tdata => m_axis_dout_tdata
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);
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-----------------------------------------------------------------------
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-- Generate clock
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-----------------------------------------------------------------------
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clock_gen : process
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begin
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aclk <= '0';
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wait for CLOCK_PERIOD;
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loop
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cycles <= cycles + 1;
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aclk <= '0';
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wait for CLOCK_PERIOD/2;
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aclk <= '1';
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wait for CLOCK_PERIOD/2;
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if cycles >= TEST_CYCLES then
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report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;
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wait;
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end if;
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end loop;
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end process clock_gen;
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-----------------------------------------------------------------------
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-- Generate inputs
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-----------------------------------------------------------------------
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stimuli : process
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variable ip_cartesian_index : integer := 0;
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variable ip_phase_index : integer := 0;
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variable cartesian_tvalid_nxt : std_logic := '0';
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variable phase_tvalid_nxt : std_logic := '0';
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variable phase2_cycles : integer := 1;
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variable phase2_count : integer := 0;
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constant PHASE2_LIMIT : integer := 30;
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begin
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-- Test is stopped in clock_gen process, use endless loop here
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loop
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-- Drive inputs T_HOLD time after rising edge of clock
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wait until rising_edge(aclk);
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wait for T_HOLD;
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-- Drive AXI TVALID signals to demonstrate different types of operation
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case cycles is -- do different types of operation at different phases of the test
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when 0 to PHASE_CYCLES * 1 - 1 =>
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-- Phase 1: inputs always valid, no missing input data
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cartesian_tvalid_nxt := '1';
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phase_tvalid_nxt := '1';
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when PHASE_CYCLES * 1 to PHASE_CYCLES * 2 - 1 =>
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-- Phase 2: deprive channel S_AXIS_CARTESIAN of valid transactions at an increasing rate
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phase_tvalid_nxt := '1';
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if phase2_count < phase2_cycles then
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cartesian_tvalid_nxt := '0';
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else
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cartesian_tvalid_nxt := '1';
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end if;
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phase2_count := phase2_count + 1;
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if phase2_count >= PHASE2_LIMIT then
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phase2_count := 0;
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phase2_cycles := phase2_cycles + 1;
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end if;
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when PHASE_CYCLES * 2 to PHASE_CYCLES * 3 - 1 =>
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-- Phase 3: deprive channel S_AXIS_CARTESIAN of 1 out of 2 transactions, and channel S_AXIS_PHASE of 1 out of 3 transactions
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if cycles mod 2 = 0 then
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cartesian_tvalid_nxt := '0';
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else
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cartesian_tvalid_nxt := '1';
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end if;
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if cycles mod 3 = 0 then
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phase_tvalid_nxt := '0';
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else
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phase_tvalid_nxt := '1';
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end if;
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when others =>
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-- Test will stop imminently - do nothing
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null;
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end case;
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-- Drive handshake signals with local variable values
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s_axis_cartesian_tvalid <= cartesian_tvalid_nxt;
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s_axis_phase_tvalid <= phase_tvalid_nxt;
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-- Drive AXI slave channel CARTESIAN payload
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-- Drive 'X's on payload signals when not valid
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if cartesian_tvalid_nxt /= '1' then
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s_axis_cartesian_tdata <= (others => 'X');
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else
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-- TDATA: Real and imaginary components are each 16 bits wide and byte-aligned at their LSBs
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s_axis_cartesian_tdata(15 downto 0) <= IP_CARTESIAN_DATA(ip_cartesian_index).re;
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s_axis_cartesian_tdata(31 downto 16) <= IP_CARTESIAN_DATA(ip_cartesian_index).im;
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||||
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||||
end if;
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||||
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||||
-- Drive AXI slave channel PHASE payload
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||||
-- Drive 'X's on payload signals when not valid
|
||||
if phase_tvalid_nxt /= '1' then
|
||||
s_axis_phase_tdata <= (others => 'X');
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||||
else
|
||||
-- TDATA: Real component is 16 bits wide and byte-aligned at its LSBs
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||||
s_axis_phase_tdata(15 downto 0) <= IP_PHASE_DATA(ip_phase_index).re;
|
||||
end if;
|
||||
|
||||
-- Increment input data indices
|
||||
if cartesian_tvalid_nxt = '1' then
|
||||
ip_cartesian_index := ip_cartesian_index + 1;
|
||||
if ip_cartesian_index = IP_CARTESIAN_DEPTH then
|
||||
ip_cartesian_index := 0;
|
||||
end if;
|
||||
end if;
|
||||
if phase_tvalid_nxt = '1' then
|
||||
ip_phase_index := ip_phase_index + 1;
|
||||
if ip_phase_index = IP_PHASE_DEPTH then
|
||||
ip_phase_index := 0;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end loop;
|
||||
|
||||
end process stimuli;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Check outputs
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
check_outputs : process
|
||||
variable check_ok : boolean := true;
|
||||
begin
|
||||
|
||||
-- Check outputs T_STROBE time after rising edge of clock
|
||||
wait until rising_edge(aclk);
|
||||
wait for T_STROBE;
|
||||
|
||||
-- Do not check the output payload values, as this requires the behavioral model
|
||||
-- which would make this demonstration testbench unwieldy.
|
||||
-- Instead, check the protocol of the DOUT channel:
|
||||
-- check that the payload is valid (not X) when TVALID is high
|
||||
|
||||
if m_axis_dout_tvalid = '1' then
|
||||
if is_x(m_axis_dout_tdata) then
|
||||
report "ERROR: m_axis_dout_tdata is invalid when m_axis_dout_tvalid is high" severity error;
|
||||
check_ok := false;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
assert check_ok
|
||||
report "ERROR: terminating test with failures." severity failure;
|
||||
|
||||
end process check_outputs;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Assign TDATA fields to aliases, for easy simulator waveform viewing
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
s_axis_cartesian_tdata_real <= s_axis_cartesian_tdata(15 downto 0);
|
||||
s_axis_cartesian_tdata_imag <= s_axis_cartesian_tdata(31 downto 16);
|
||||
|
||||
m_axis_dout_tdata_phase <= m_axis_dout_tdata(15 downto 0);
|
||||
|
||||
end tb;
|
||||
|
||||
@@ -0,0 +1,186 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:cordic:6.0
|
||||
-- IP Revision: 15
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY cordic_v6_0_15;
|
||||
USE cordic_v6_0_15.cordic_v6_0_15;
|
||||
|
||||
ENTITY atan2_16b IS
|
||||
PORT (
|
||||
aclk : IN STD_LOGIC;
|
||||
s_axis_cartesian_tvalid : IN STD_LOGIC;
|
||||
s_axis_cartesian_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axis_dout_tvalid : OUT STD_LOGIC;
|
||||
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
|
||||
);
|
||||
END atan2_16b;
|
||||
|
||||
ARCHITECTURE atan2_16b_arch OF atan2_16b IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF atan2_16b_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT cordic_v6_0_15 IS
|
||||
GENERIC (
|
||||
C_ARCHITECTURE : INTEGER;
|
||||
C_CORDIC_FUNCTION : INTEGER;
|
||||
C_COARSE_ROTATE : INTEGER;
|
||||
C_DATA_FORMAT : INTEGER;
|
||||
C_XDEVICEFAMILY : STRING;
|
||||
C_HAS_ACLKEN : INTEGER;
|
||||
C_HAS_ACLK : INTEGER;
|
||||
C_HAS_S_AXIS_CARTESIAN : INTEGER;
|
||||
C_HAS_S_AXIS_PHASE : INTEGER;
|
||||
C_HAS_ARESETN : INTEGER;
|
||||
C_INPUT_WIDTH : INTEGER;
|
||||
C_ITERATIONS : INTEGER;
|
||||
C_OUTPUT_WIDTH : INTEGER;
|
||||
C_PHASE_FORMAT : INTEGER;
|
||||
C_PIPELINE_MODE : INTEGER;
|
||||
C_PRECISION : INTEGER;
|
||||
C_ROUND_MODE : INTEGER;
|
||||
C_SCALE_COMP : INTEGER;
|
||||
C_THROTTLE_SCHEME : INTEGER;
|
||||
C_TLAST_RESOLUTION : INTEGER;
|
||||
C_HAS_S_AXIS_PHASE_TUSER : INTEGER;
|
||||
C_HAS_S_AXIS_PHASE_TLAST : INTEGER;
|
||||
C_S_AXIS_PHASE_TDATA_WIDTH : INTEGER;
|
||||
C_S_AXIS_PHASE_TUSER_WIDTH : INTEGER;
|
||||
C_HAS_S_AXIS_CARTESIAN_TUSER : INTEGER;
|
||||
C_HAS_S_AXIS_CARTESIAN_TLAST : INTEGER;
|
||||
C_S_AXIS_CARTESIAN_TDATA_WIDTH : INTEGER;
|
||||
C_S_AXIS_CARTESIAN_TUSER_WIDTH : INTEGER;
|
||||
C_M_AXIS_DOUT_TDATA_WIDTH : INTEGER;
|
||||
C_M_AXIS_DOUT_TUSER_WIDTH : INTEGER
|
||||
);
|
||||
PORT (
|
||||
aclk : IN STD_LOGIC;
|
||||
aclken : IN STD_LOGIC;
|
||||
aresetn : IN STD_LOGIC;
|
||||
s_axis_phase_tvalid : IN STD_LOGIC;
|
||||
s_axis_phase_tready : OUT STD_LOGIC;
|
||||
s_axis_phase_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axis_phase_tlast : IN STD_LOGIC;
|
||||
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
s_axis_cartesian_tvalid : IN STD_LOGIC;
|
||||
s_axis_cartesian_tready : OUT STD_LOGIC;
|
||||
s_axis_cartesian_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axis_cartesian_tlast : IN STD_LOGIC;
|
||||
s_axis_cartesian_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axis_dout_tvalid : OUT STD_LOGIC;
|
||||
m_axis_dout_tready : IN STD_LOGIC;
|
||||
m_axis_dout_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axis_dout_tlast : OUT STD_LOGIC;
|
||||
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT cordic_v6_0_15;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TDATA";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_dout_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_DOUT, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_cartesian_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CARTESIAN TDATA";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_cartesian_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_CARTESIAN, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_cartesian_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CARTESIAN TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF M_AXIS_DOUT:S_AXIS_PHASE:S_AXIS_CARTESIAN, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 1000000, PHASE 0.000, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
|
||||
BEGIN
|
||||
U0 : cordic_v6_0_15
|
||||
GENERIC MAP (
|
||||
C_ARCHITECTURE => 2,
|
||||
C_CORDIC_FUNCTION => 3,
|
||||
C_COARSE_ROTATE => 1,
|
||||
C_DATA_FORMAT => 0,
|
||||
C_XDEVICEFAMILY => "kintex7",
|
||||
C_HAS_ACLKEN => 0,
|
||||
C_HAS_ACLK => 1,
|
||||
C_HAS_S_AXIS_CARTESIAN => 1,
|
||||
C_HAS_S_AXIS_PHASE => 0,
|
||||
C_HAS_ARESETN => 0,
|
||||
C_INPUT_WIDTH => 16,
|
||||
C_ITERATIONS => 0,
|
||||
C_OUTPUT_WIDTH => 16,
|
||||
C_PHASE_FORMAT => 0,
|
||||
C_PIPELINE_MODE => -2,
|
||||
C_PRECISION => 0,
|
||||
C_ROUND_MODE => 0,
|
||||
C_SCALE_COMP => 0,
|
||||
C_THROTTLE_SCHEME => 3,
|
||||
C_TLAST_RESOLUTION => 0,
|
||||
C_HAS_S_AXIS_PHASE_TUSER => 0,
|
||||
C_HAS_S_AXIS_PHASE_TLAST => 0,
|
||||
C_S_AXIS_PHASE_TDATA_WIDTH => 16,
|
||||
C_S_AXIS_PHASE_TUSER_WIDTH => 1,
|
||||
C_HAS_S_AXIS_CARTESIAN_TUSER => 0,
|
||||
C_HAS_S_AXIS_CARTESIAN_TLAST => 0,
|
||||
C_S_AXIS_CARTESIAN_TDATA_WIDTH => 32,
|
||||
C_S_AXIS_CARTESIAN_TUSER_WIDTH => 1,
|
||||
C_M_AXIS_DOUT_TDATA_WIDTH => 16,
|
||||
C_M_AXIS_DOUT_TUSER_WIDTH => 1
|
||||
)
|
||||
PORT MAP (
|
||||
aclk => aclk,
|
||||
aclken => '1',
|
||||
aresetn => '1',
|
||||
s_axis_phase_tvalid => '0',
|
||||
s_axis_phase_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axis_phase_tlast => '0',
|
||||
s_axis_phase_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
|
||||
s_axis_cartesian_tvalid => s_axis_cartesian_tvalid,
|
||||
s_axis_cartesian_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axis_cartesian_tlast => '0',
|
||||
s_axis_cartesian_tdata => s_axis_cartesian_tdata,
|
||||
m_axis_dout_tvalid => m_axis_dout_tvalid,
|
||||
m_axis_dout_tready => '0',
|
||||
m_axis_dout_tdata => m_axis_dout_tdata
|
||||
);
|
||||
END atan2_16b_arch;
|
||||
@@ -0,0 +1,380 @@
|
||||
--------------------------------------------------------------------------------
|
||||
-- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--------------------------------------------------------------------------------
|
||||
-- Description:
|
||||
-- This is an example testbench for the CORDIC IP core.
|
||||
-- The testbench has been generated by Vivado to accompany the IP core
|
||||
-- instance you have generated.
|
||||
--
|
||||
-- This testbench is for demonstration purposes only. See note below for
|
||||
-- instructions on how to use it with your core.
|
||||
--
|
||||
-- See the CORDIC product guide for further information
|
||||
-- about this core.
|
||||
--
|
||||
--------------------------------------------------------------------------------
|
||||
-- Using this testbench
|
||||
--
|
||||
-- This testbench instantiates your generated CORDIC core
|
||||
-- instance named "rotate_16b".
|
||||
--
|
||||
-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado
|
||||
-- documentation for details.
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee.math_real.all;
|
||||
|
||||
entity tb_rotate_16b is
|
||||
end tb_rotate_16b;
|
||||
|
||||
architecture tb of tb_rotate_16b is
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Timing constants
|
||||
-----------------------------------------------------------------------
|
||||
constant CLOCK_PERIOD : time := 100 ns;
|
||||
constant T_HOLD : time := 10 ns;
|
||||
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
|
||||
constant TEST_CYCLES : integer := 3000;
|
||||
constant PHASE_CYCLES : integer := 1000;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- DUT input signals
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
-- General inputs
|
||||
signal aclk : std_logic := '0'; -- the master clock
|
||||
|
||||
-- Slave channel CARTESIAN inputs
|
||||
signal s_axis_cartesian_tvalid : std_logic := '0'; -- TVALID for channel S_AXIS_CARTESIAN
|
||||
signal s_axis_cartesian_tdata : std_logic_vector(31 downto 0) := (others => 'X'); -- TDATA for channel S_AXIS_CARTESIAN
|
||||
|
||||
-- Slave channel PHASE inputs
|
||||
signal s_axis_phase_tvalid : std_logic := '0'; -- TVALID for channel S_AXIS_PHASE
|
||||
signal s_axis_phase_tdata : std_logic_vector(15 downto 0) := (others => 'X'); -- TDATA for channel S_AXIS_PHASE
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- DUT output signals
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
-- Master channel DOUT outputs
|
||||
signal m_axis_dout_tvalid : std_logic := '0'; -- TVALID for channel M_AXIS_DOUT
|
||||
signal m_axis_dout_tdata : std_logic_vector(31 downto 0) := (others => '0'); -- TDATA for channel M_AXIS_DOUT
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Aliases for AXI channel TDATA fields
|
||||
-- These are a convenience for viewing data in a simulator waveform viewer.
|
||||
-- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
|
||||
-- to prevent the simulator optimizing away these signals.
|
||||
-----------------------------------------------------------------------
|
||||
signal s_axis_cartesian_tdata_real : std_logic_vector(15 downto 0) := (others => '0');
|
||||
signal s_axis_cartesian_tdata_imag : std_logic_vector(15 downto 0) := (others => '0');
|
||||
signal s_axis_phase_tdata_real : std_logic_vector(15 downto 0) := (others => '0');
|
||||
|
||||
signal m_axis_dout_tdata_real : std_logic_vector(15 downto 0) := (others => '0');
|
||||
signal m_axis_dout_tdata_imag : std_logic_vector(15 downto 0) := (others => '0');
|
||||
signal m_axis_dout_tdata_phase : std_logic_vector(15 downto 0) := (others => '0');
|
||||
-----------------------------------------------------------------------
|
||||
-- Testbench signals
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
signal cycles : integer := 0; -- Clock cycle counter
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Constants, types and functions to create input data
|
||||
-- The CORDIC is fed two sinusoids exp(+/-jwt) of different frequencies and amplitudes:
|
||||
-- channel CARTESIAN: exp(+jwt), frequency = clock / 30,
|
||||
-- channel PHASE: exp(-jwt), frequency = clock / 32,
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
constant IP_CARTESIAN_DEPTH : integer := 30;
|
||||
constant IP_CARTESIAN_WIDTH : integer := 16;
|
||||
constant IP_CARTESIAN_SHIFT : integer := 3; -- bit shift for amplitude
|
||||
constant IP_PHASE_DEPTH : integer := 32;
|
||||
constant IP_PHASE_WIDTH : integer := 16;
|
||||
constant IP_PHASE_SHIFT : integer := 0; -- no bit shift, max amplitude
|
||||
type T_IP_INT_ENTRY is record
|
||||
re : integer;
|
||||
im : integer;
|
||||
end record;
|
||||
type T_IP_CARTESIAN_ENTRY is record
|
||||
re : std_logic_vector(IP_CARTESIAN_WIDTH-1 downto 0);
|
||||
im : std_logic_vector(IP_CARTESIAN_WIDTH-1 downto 0);
|
||||
end record;
|
||||
type T_IP_PHASE_ENTRY is record
|
||||
re : std_logic_vector(IP_PHASE_WIDTH-1 downto 0);
|
||||
end record;
|
||||
type T_IP_CARTESIAN_TABLE is array (0 to IP_CARTESIAN_DEPTH-1) of T_IP_CARTESIAN_ENTRY;
|
||||
type T_IP_PHASE_TABLE is array (0 to IP_PHASE_DEPTH-1) of T_IP_PHASE_ENTRY;
|
||||
|
||||
-- Common function to calculate sine and cosine values
|
||||
function create_ip_entry(index, depth, width : integer) return T_IP_INT_ENTRY is
|
||||
variable result : T_IP_INT_ENTRY;
|
||||
variable theta : real;
|
||||
variable limited_width : integer := width - 2;
|
||||
begin
|
||||
if limited_width > 30 then
|
||||
limited_width := 30; --avoid integer overflow
|
||||
end if;
|
||||
theta := real(index) / real(depth) * 2.0 * MATH_PI;
|
||||
result.re := integer(round(cos(theta) * real(2**limited_width)));
|
||||
result.im := integer(round(sin(theta) * real(2**limited_width)));
|
||||
return result;
|
||||
end function create_ip_entry;
|
||||
|
||||
-- Use separate functions to calculate channel S_AXIS_CARTESIAN and S_AXIS_PHASE sinusoids as they return different types
|
||||
function create_ip_cartesian_table return T_IP_CARTESIAN_TABLE is
|
||||
variable result : T_IP_CARTESIAN_TABLE;
|
||||
variable entry_int : T_IP_INT_ENTRY;
|
||||
begin
|
||||
for i in 0 to IP_CARTESIAN_DEPTH-1 loop
|
||||
entry_int := create_ip_entry(i, IP_CARTESIAN_DEPTH, IP_CARTESIAN_WIDTH - IP_CARTESIAN_SHIFT);
|
||||
result(i).re := std_logic_vector(to_signed(entry_int.re, IP_CARTESIAN_WIDTH));
|
||||
result(i).im := std_logic_vector(to_signed(entry_int.im, IP_CARTESIAN_WIDTH));
|
||||
end loop;
|
||||
return result;
|
||||
end function create_ip_cartesian_table;
|
||||
|
||||
function create_ip_phase_table return T_IP_PHASE_TABLE is
|
||||
variable result : T_IP_PHASE_TABLE;
|
||||
variable entry_int : T_IP_INT_ENTRY;
|
||||
begin
|
||||
for i in 0 to IP_PHASE_DEPTH-1 loop
|
||||
entry_int := create_ip_entry(IP_PHASE_DEPTH-1-i, IP_PHASE_DEPTH, IP_PHASE_WIDTH - IP_PHASE_SHIFT); -- note rotation direction
|
||||
result(i).re := std_logic_vector(to_signed(entry_int.re, IP_PHASE_WIDTH));
|
||||
end loop;
|
||||
return result;
|
||||
end function create_ip_phase_table;
|
||||
|
||||
-- Call the functions to create the data
|
||||
constant IP_CARTESIAN_DATA : T_IP_CARTESIAN_TABLE := create_ip_cartesian_table;
|
||||
constant IP_PHASE_DATA : T_IP_PHASE_TABLE := create_ip_phase_table;
|
||||
|
||||
|
||||
begin
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Instantiate the DUT
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
dut : entity work.rotate_16b
|
||||
port map (
|
||||
aclk => aclk,
|
||||
s_axis_cartesian_tvalid => s_axis_cartesian_tvalid,
|
||||
s_axis_cartesian_tdata => s_axis_cartesian_tdata,
|
||||
s_axis_phase_tvalid => s_axis_phase_tvalid,
|
||||
s_axis_phase_tdata => s_axis_phase_tdata,
|
||||
m_axis_dout_tvalid => m_axis_dout_tvalid,
|
||||
m_axis_dout_tdata => m_axis_dout_tdata
|
||||
);
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Generate clock
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
clock_gen : process
|
||||
begin
|
||||
aclk <= '0';
|
||||
wait for CLOCK_PERIOD;
|
||||
loop
|
||||
cycles <= cycles + 1;
|
||||
aclk <= '0';
|
||||
wait for CLOCK_PERIOD/2;
|
||||
aclk <= '1';
|
||||
wait for CLOCK_PERIOD/2;
|
||||
if cycles >= TEST_CYCLES then
|
||||
report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;
|
||||
wait;
|
||||
end if;
|
||||
end loop;
|
||||
end process clock_gen;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Generate inputs
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
stimuli : process
|
||||
variable ip_cartesian_index : integer := 0;
|
||||
variable ip_phase_index : integer := 0;
|
||||
variable cartesian_tvalid_nxt : std_logic := '0';
|
||||
variable phase_tvalid_nxt : std_logic := '0';
|
||||
variable phase2_cycles : integer := 1;
|
||||
variable phase2_count : integer := 0;
|
||||
constant PHASE2_LIMIT : integer := 30;
|
||||
begin
|
||||
|
||||
-- Test is stopped in clock_gen process, use endless loop here
|
||||
loop
|
||||
|
||||
-- Drive inputs T_HOLD time after rising edge of clock
|
||||
wait until rising_edge(aclk);
|
||||
wait for T_HOLD;
|
||||
|
||||
-- Drive AXI TVALID signals to demonstrate different types of operation
|
||||
case cycles is -- do different types of operation at different phases of the test
|
||||
when 0 to PHASE_CYCLES * 1 - 1 =>
|
||||
-- Phase 1: inputs always valid, no missing input data
|
||||
cartesian_tvalid_nxt := '1';
|
||||
phase_tvalid_nxt := '1';
|
||||
when PHASE_CYCLES * 1 to PHASE_CYCLES * 2 - 1 =>
|
||||
-- Phase 2: deprive channel S_AXIS_CARTESIAN of valid transactions at an increasing rate
|
||||
phase_tvalid_nxt := '1';
|
||||
if phase2_count < phase2_cycles then
|
||||
cartesian_tvalid_nxt := '0';
|
||||
else
|
||||
cartesian_tvalid_nxt := '1';
|
||||
end if;
|
||||
phase2_count := phase2_count + 1;
|
||||
if phase2_count >= PHASE2_LIMIT then
|
||||
phase2_count := 0;
|
||||
phase2_cycles := phase2_cycles + 1;
|
||||
end if;
|
||||
when PHASE_CYCLES * 2 to PHASE_CYCLES * 3 - 1 =>
|
||||
-- Phase 3: deprive channel S_AXIS_CARTESIAN of 1 out of 2 transactions, and channel S_AXIS_PHASE of 1 out of 3 transactions
|
||||
if cycles mod 2 = 0 then
|
||||
cartesian_tvalid_nxt := '0';
|
||||
else
|
||||
cartesian_tvalid_nxt := '1';
|
||||
end if;
|
||||
if cycles mod 3 = 0 then
|
||||
phase_tvalid_nxt := '0';
|
||||
else
|
||||
phase_tvalid_nxt := '1';
|
||||
end if;
|
||||
when others =>
|
||||
-- Test will stop imminently - do nothing
|
||||
null;
|
||||
end case;
|
||||
|
||||
-- Drive handshake signals with local variable values
|
||||
s_axis_cartesian_tvalid <= cartesian_tvalid_nxt;
|
||||
s_axis_phase_tvalid <= phase_tvalid_nxt;
|
||||
|
||||
-- Drive AXI slave channel CARTESIAN payload
|
||||
-- Drive 'X's on payload signals when not valid
|
||||
if cartesian_tvalid_nxt /= '1' then
|
||||
s_axis_cartesian_tdata <= (others => 'X');
|
||||
else
|
||||
-- TDATA: Real and imaginary components are each 16 bits wide and byte-aligned at their LSBs
|
||||
s_axis_cartesian_tdata(15 downto 0) <= IP_CARTESIAN_DATA(ip_cartesian_index).re;
|
||||
s_axis_cartesian_tdata(31 downto 16) <= IP_CARTESIAN_DATA(ip_cartesian_index).im;
|
||||
|
||||
end if;
|
||||
|
||||
-- Drive AXI slave channel PHASE payload
|
||||
-- Drive 'X's on payload signals when not valid
|
||||
if phase_tvalid_nxt /= '1' then
|
||||
s_axis_phase_tdata <= (others => 'X');
|
||||
else
|
||||
-- TDATA: Real component is 16 bits wide and byte-aligned at its LSBs
|
||||
s_axis_phase_tdata(15 downto 0) <= IP_PHASE_DATA(ip_phase_index).re;
|
||||
end if;
|
||||
|
||||
-- Increment input data indices
|
||||
if cartesian_tvalid_nxt = '1' then
|
||||
ip_cartesian_index := ip_cartesian_index + 1;
|
||||
if ip_cartesian_index = IP_CARTESIAN_DEPTH then
|
||||
ip_cartesian_index := 0;
|
||||
end if;
|
||||
end if;
|
||||
if phase_tvalid_nxt = '1' then
|
||||
ip_phase_index := ip_phase_index + 1;
|
||||
if ip_phase_index = IP_PHASE_DEPTH then
|
||||
ip_phase_index := 0;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end loop;
|
||||
|
||||
end process stimuli;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Check outputs
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
check_outputs : process
|
||||
variable check_ok : boolean := true;
|
||||
begin
|
||||
|
||||
-- Check outputs T_STROBE time after rising edge of clock
|
||||
wait until rising_edge(aclk);
|
||||
wait for T_STROBE;
|
||||
|
||||
-- Do not check the output payload values, as this requires the behavioral model
|
||||
-- which would make this demonstration testbench unwieldy.
|
||||
-- Instead, check the protocol of the DOUT channel:
|
||||
-- check that the payload is valid (not X) when TVALID is high
|
||||
|
||||
if m_axis_dout_tvalid = '1' then
|
||||
if is_x(m_axis_dout_tdata) then
|
||||
report "ERROR: m_axis_dout_tdata is invalid when m_axis_dout_tvalid is high" severity error;
|
||||
check_ok := false;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
assert check_ok
|
||||
report "ERROR: terminating test with failures." severity failure;
|
||||
|
||||
end process check_outputs;
|
||||
|
||||
-----------------------------------------------------------------------
|
||||
-- Assign TDATA fields to aliases, for easy simulator waveform viewing
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
s_axis_cartesian_tdata_real <= s_axis_cartesian_tdata(15 downto 0);
|
||||
s_axis_cartesian_tdata_imag <= s_axis_cartesian_tdata(31 downto 16);
|
||||
s_axis_phase_tdata_real <= s_axis_phase_tdata(15 downto 0);
|
||||
|
||||
m_axis_dout_tdata_real <= m_axis_dout_tdata(15 downto 0);
|
||||
m_axis_dout_tdata_imag <= m_axis_dout_tdata(31 downto 16);
|
||||
|
||||
end tb;
|
||||
|
||||
Binary file not shown.
BIN
Binary file not shown.
@@ -1,7 +1,7 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Wed Apr 12 20:00:10 2023
|
||||
// Date : Mon Jun 5 20:28:46 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_stub.v
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Wed Apr 12 20:00:10 2023
|
||||
-- Date : Mon Jun 5 20:28:46 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_stub.vhdl
|
||||
|
||||
@@ -0,0 +1,191 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:cordic:6.0
|
||||
-- IP Revision: 15
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY cordic_v6_0_15;
|
||||
USE cordic_v6_0_15.cordic_v6_0_15;
|
||||
|
||||
ENTITY rotate_16b IS
|
||||
PORT (
|
||||
aclk : IN STD_LOGIC;
|
||||
s_axis_phase_tvalid : IN STD_LOGIC;
|
||||
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
s_axis_cartesian_tvalid : IN STD_LOGIC;
|
||||
s_axis_cartesian_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axis_dout_tvalid : OUT STD_LOGIC;
|
||||
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END rotate_16b;
|
||||
|
||||
ARCHITECTURE rotate_16b_arch OF rotate_16b IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF rotate_16b_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT cordic_v6_0_15 IS
|
||||
GENERIC (
|
||||
C_ARCHITECTURE : INTEGER;
|
||||
C_CORDIC_FUNCTION : INTEGER;
|
||||
C_COARSE_ROTATE : INTEGER;
|
||||
C_DATA_FORMAT : INTEGER;
|
||||
C_XDEVICEFAMILY : STRING;
|
||||
C_HAS_ACLKEN : INTEGER;
|
||||
C_HAS_ACLK : INTEGER;
|
||||
C_HAS_S_AXIS_CARTESIAN : INTEGER;
|
||||
C_HAS_S_AXIS_PHASE : INTEGER;
|
||||
C_HAS_ARESETN : INTEGER;
|
||||
C_INPUT_WIDTH : INTEGER;
|
||||
C_ITERATIONS : INTEGER;
|
||||
C_OUTPUT_WIDTH : INTEGER;
|
||||
C_PHASE_FORMAT : INTEGER;
|
||||
C_PIPELINE_MODE : INTEGER;
|
||||
C_PRECISION : INTEGER;
|
||||
C_ROUND_MODE : INTEGER;
|
||||
C_SCALE_COMP : INTEGER;
|
||||
C_THROTTLE_SCHEME : INTEGER;
|
||||
C_TLAST_RESOLUTION : INTEGER;
|
||||
C_HAS_S_AXIS_PHASE_TUSER : INTEGER;
|
||||
C_HAS_S_AXIS_PHASE_TLAST : INTEGER;
|
||||
C_S_AXIS_PHASE_TDATA_WIDTH : INTEGER;
|
||||
C_S_AXIS_PHASE_TUSER_WIDTH : INTEGER;
|
||||
C_HAS_S_AXIS_CARTESIAN_TUSER : INTEGER;
|
||||
C_HAS_S_AXIS_CARTESIAN_TLAST : INTEGER;
|
||||
C_S_AXIS_CARTESIAN_TDATA_WIDTH : INTEGER;
|
||||
C_S_AXIS_CARTESIAN_TUSER_WIDTH : INTEGER;
|
||||
C_M_AXIS_DOUT_TDATA_WIDTH : INTEGER;
|
||||
C_M_AXIS_DOUT_TUSER_WIDTH : INTEGER
|
||||
);
|
||||
PORT (
|
||||
aclk : IN STD_LOGIC;
|
||||
aclken : IN STD_LOGIC;
|
||||
aresetn : IN STD_LOGIC;
|
||||
s_axis_phase_tvalid : IN STD_LOGIC;
|
||||
s_axis_phase_tready : OUT STD_LOGIC;
|
||||
s_axis_phase_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axis_phase_tlast : IN STD_LOGIC;
|
||||
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
s_axis_cartesian_tvalid : IN STD_LOGIC;
|
||||
s_axis_cartesian_tready : OUT STD_LOGIC;
|
||||
s_axis_cartesian_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axis_cartesian_tlast : IN STD_LOGIC;
|
||||
s_axis_cartesian_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
m_axis_dout_tvalid : OUT STD_LOGIC;
|
||||
m_axis_dout_tready : IN STD_LOGIC;
|
||||
m_axis_dout_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
m_axis_dout_tlast : OUT STD_LOGIC;
|
||||
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT cordic_v6_0_15;
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TDATA";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_dout_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_DOUT, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_cartesian_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CARTESIAN TDATA";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_cartesian_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_CARTESIAN, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_cartesian_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CARTESIAN TVALID";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_phase_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_PHASE TDATA";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_phase_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_PHASE, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF s_axis_phase_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_PHASE TVALID";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF M_AXIS_DOUT:S_AXIS_PHASE:S_AXIS_CARTESIAN, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 1000000, PHASE 0.000, INSERT_VIP 0";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
|
||||
BEGIN
|
||||
U0 : cordic_v6_0_15
|
||||
GENERIC MAP (
|
||||
C_ARCHITECTURE => 2,
|
||||
C_CORDIC_FUNCTION => 0,
|
||||
C_COARSE_ROTATE => 1,
|
||||
C_DATA_FORMAT => 0,
|
||||
C_XDEVICEFAMILY => "kintex7",
|
||||
C_HAS_ACLKEN => 0,
|
||||
C_HAS_ACLK => 1,
|
||||
C_HAS_S_AXIS_CARTESIAN => 1,
|
||||
C_HAS_S_AXIS_PHASE => 1,
|
||||
C_HAS_ARESETN => 0,
|
||||
C_INPUT_WIDTH => 16,
|
||||
C_ITERATIONS => 0,
|
||||
C_OUTPUT_WIDTH => 16,
|
||||
C_PHASE_FORMAT => 0,
|
||||
C_PIPELINE_MODE => -2,
|
||||
C_PRECISION => 0,
|
||||
C_ROUND_MODE => 0,
|
||||
C_SCALE_COMP => 0,
|
||||
C_THROTTLE_SCHEME => 3,
|
||||
C_TLAST_RESOLUTION => 0,
|
||||
C_HAS_S_AXIS_PHASE_TUSER => 0,
|
||||
C_HAS_S_AXIS_PHASE_TLAST => 0,
|
||||
C_S_AXIS_PHASE_TDATA_WIDTH => 16,
|
||||
C_S_AXIS_PHASE_TUSER_WIDTH => 1,
|
||||
C_HAS_S_AXIS_CARTESIAN_TUSER => 0,
|
||||
C_HAS_S_AXIS_CARTESIAN_TLAST => 0,
|
||||
C_S_AXIS_CARTESIAN_TDATA_WIDTH => 32,
|
||||
C_S_AXIS_CARTESIAN_TUSER_WIDTH => 1,
|
||||
C_M_AXIS_DOUT_TDATA_WIDTH => 32,
|
||||
C_M_AXIS_DOUT_TUSER_WIDTH => 1
|
||||
)
|
||||
PORT MAP (
|
||||
aclk => aclk,
|
||||
aclken => '1',
|
||||
aresetn => '1',
|
||||
s_axis_phase_tvalid => s_axis_phase_tvalid,
|
||||
s_axis_phase_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axis_phase_tlast => '0',
|
||||
s_axis_phase_tdata => s_axis_phase_tdata,
|
||||
s_axis_cartesian_tvalid => s_axis_cartesian_tvalid,
|
||||
s_axis_cartesian_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axis_cartesian_tlast => '0',
|
||||
s_axis_cartesian_tdata => s_axis_cartesian_tdata,
|
||||
m_axis_dout_tvalid => m_axis_dout_tvalid,
|
||||
m_axis_dout_tready => '0',
|
||||
m_axis_dout_tdata => m_axis_dout_tdata
|
||||
);
|
||||
END rotate_16b_arch;
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 12 20:00:17 CST 2023
|
||||
# Generated by export_simulation on Mon Jun 05 20:28:33 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Wed Apr 12 20:00:17 CST 2023
|
||||
# Generated by Vivado on Mon Jun 05 20:28:33 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+3
-3
@@ -30,11 +30,11 @@ vmap axi_utils_v2_0_6 activehdl/axi_utils_v2_0_6
|
||||
vmap cordic_v6_0_15 activehdl/cordic_v6_0_15
|
||||
|
||||
vlog -work xil_defaultlib -sv2k12 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -93 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vcom -work xbip_utils_v3_0_10 -93 \
|
||||
"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
|
||||
|
||||
+3
-3
@@ -1,6 +1,6 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
|
||||
c_reg_fd_v12_0_vh_rfs.vhd,vhdl,c_reg_fd_v12_0_6,../../../ipstatic/hdl/c_reg_fd_v12_0_vh_rfs.vhd,
|
||||
xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_wrapper_v3_0_4,../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,
|
||||
|
||||
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 12 20:00:17 CST 2023
|
||||
# Generated by export_simulation on Mon Jun 05 20:28:33 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Wed Apr 12 20:00:17 CST 2023
|
||||
# Generated by Vivado on Mon Jun 05 20:28:33 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
|
||||
c_reg_fd_v12_0_vh_rfs.vhd,vhdl,c_reg_fd_v12_0_6,../../../ipstatic/hdl/c_reg_fd_v12_0_vh_rfs.vhd,
|
||||
xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_wrapper_v3_0_4,../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
-makelib ies_lib/xil_defaultlib -sv \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
-endlib
|
||||
-makelib ies_lib/xpm \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
-endlib
|
||||
-makelib ies_lib/xbip_utils_v3_0_10 \
|
||||
"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
|
||||
|
||||
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 12 20:00:17 CST 2023
|
||||
# Generated by export_simulation on Mon Jun 05 20:28:33 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Wed Apr 12 20:00:17 CST 2023
|
||||
# Generated by Vivado on Mon Jun 05 20:28:33 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
@@ -30,11 +30,11 @@ vmap axi_utils_v2_0_6 modelsim_lib/msim/axi_utils_v2_0_6
|
||||
vmap cordic_v6_0_15 modelsim_lib/msim/cordic_v6_0_15
|
||||
|
||||
vlog -work xil_defaultlib -64 -incr -sv \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -64 -93 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vcom -work xbip_utils_v3_0_10 -64 -93 \
|
||||
"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
|
||||
|
||||
+3
-3
@@ -1,6 +1,6 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
|
||||
c_reg_fd_v12_0_vh_rfs.vhd,vhdl,c_reg_fd_v12_0_6,../../../ipstatic/hdl/c_reg_fd_v12_0_vh_rfs.vhd,
|
||||
xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_wrapper_v3_0_4,../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,
|
||||
|
||||
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 12 20:00:17 CST 2023
|
||||
# Generated by export_simulation on Mon Jun 05 20:28:33 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Wed Apr 12 20:00:17 CST 2023
|
||||
# Generated by Vivado on Mon Jun 05 20:28:33 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
@@ -30,11 +30,11 @@ vmap axi_utils_v2_0_6 questa_lib/msim/axi_utils_v2_0_6
|
||||
vmap cordic_v6_0_15 questa_lib/msim/cordic_v6_0_15
|
||||
|
||||
vlog -work xil_defaultlib -64 -sv \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -64 -93 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vcom -work xbip_utils_v3_0_10 -64 -93 \
|
||||
"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
|
||||
|
||||
+3
-3
@@ -1,6 +1,6 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
|
||||
c_reg_fd_v12_0_vh_rfs.vhd,vhdl,c_reg_fd_v12_0_6,../../../ipstatic/hdl/c_reg_fd_v12_0_vh_rfs.vhd,
|
||||
xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_wrapper_v3_0_4,../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,
|
||||
|
||||
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 12 20:00:17 CST 2023
|
||||
# Generated by export_simulation on Mon Jun 05 20:28:33 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Wed Apr 12 20:00:17 CST 2023
|
||||
# Generated by Vivado on Mon Jun 05 20:28:33 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
@@ -30,11 +30,11 @@ vmap axi_utils_v2_0_6 riviera/axi_utils_v2_0_6
|
||||
vmap cordic_v6_0_15 riviera/cordic_v6_0_15
|
||||
|
||||
vlog -work xil_defaultlib -sv2k12 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -93 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vcom -work xbip_utils_v3_0_10 -93 \
|
||||
"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
|
||||
|
||||
+3
-3
@@ -1,6 +1,6 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
|
||||
c_reg_fd_v12_0_vh_rfs.vhd,vhdl,c_reg_fd_v12_0_6,../../../ipstatic/hdl/c_reg_fd_v12_0_vh_rfs.vhd,
|
||||
xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_wrapper_v3_0_4,../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,
|
||||
|
||||
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 12 20:00:17 CST 2023
|
||||
# Generated by export_simulation on Mon Jun 05 20:28:33 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Wed Apr 12 20:00:17 CST 2023
|
||||
# Generated by Vivado on Mon Jun 05 20:28:33 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
@@ -71,12 +71,12 @@ compile()
|
||||
{
|
||||
# Compile design files
|
||||
vlogan -work xil_defaultlib $vlogan_opts -sverilog \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
2>&1 | tee -a vlogan.log
|
||||
|
||||
vhdlan -work xpm $vhdlan_opts \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
2>&1 | tee -a vhdlan.log
|
||||
|
||||
vhdlan -work xbip_utils_v3_0_10 $vhdlan_opts \
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
|
||||
c_reg_fd_v12_0_vh_rfs.vhd,vhdl,c_reg_fd_v12_0_6,../../../ipstatic/hdl/c_reg_fd_v12_0_vh_rfs.vhd,
|
||||
xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_wrapper_v3_0_4,../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,
|
||||
|
||||
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 12 20:00:17 CST 2023
|
||||
# Generated by export_simulation on Mon Jun 05 20:28:33 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Wed Apr 12 20:00:17 CST 2023
|
||||
# Generated by Vivado on Mon Jun 05 20:28:33 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+3
-3
@@ -1,6 +1,6 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
|
||||
c_reg_fd_v12_0_vh_rfs.vhd,vhdl,c_reg_fd_v12_0_6,../../../ipstatic/hdl/c_reg_fd_v12_0_vh_rfs.vhd,
|
||||
xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_wrapper_v3_0_4,../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
-makelib xcelium_lib/xil_defaultlib -sv \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
-endlib
|
||||
-makelib xcelium_lib/xpm \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
-endlib
|
||||
-makelib xcelium_lib/xbip_utils_v3_0_10 \
|
||||
"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
|
||||
|
||||
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 12 20:00:17 CST 2023
|
||||
# Generated by export_simulation on Mon Jun 05 20:28:33 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Wed Apr 12 20:00:17 CST 2023
|
||||
# Generated by Vivado on Mon Jun 05 20:28:33 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
@@ -22,7 +22,7 @@
|
||||
#*********************************************************************************************************
|
||||
|
||||
# Command line options
|
||||
xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0
|
||||
xv_boost_lib_path=/home/josh/Software/Xilinx/Vivado/2019.1/tps/boost_1_64_0
|
||||
xvlog_opts="--relax"
|
||||
xvhdl_opts="--relax"
|
||||
|
||||
@@ -94,7 +94,7 @@ setup()
|
||||
copy_setup_file()
|
||||
{
|
||||
file="xsim.ini"
|
||||
lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim"
|
||||
lib_map_path="/home/josh/Software/Xilinx/Vivado/2019.1/data/xsim"
|
||||
if [[ ($1 != "") ]]; then
|
||||
lib_map_path="$1"
|
||||
fi
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 12 20:01:03 CST 2023
|
||||
# Generated by export_simulation on Mon Jun 05 20:28:18 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+3
-3
@@ -30,11 +30,11 @@ vmap axi_utils_v2_0_6 activehdl/axi_utils_v2_0_6
|
||||
vmap cordic_v6_0_15 activehdl/cordic_v6_0_15
|
||||
|
||||
vlog -work xil_defaultlib -sv2k12 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -93 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vcom -work xbip_utils_v3_0_10 -93 \
|
||||
"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
|
||||
|
||||
+3
-3
@@ -1,6 +1,6 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
|
||||
c_reg_fd_v12_0_vh_rfs.vhd,vhdl,c_reg_fd_v12_0_6,../../../ipstatic/hdl/c_reg_fd_v12_0_vh_rfs.vhd,
|
||||
xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_wrapper_v3_0_4,../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Wed Apr 12 20:01:03 CST 2023
|
||||
# Generated by Vivado on Mon Jun 05 20:28:18 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 12 20:01:03 CST 2023
|
||||
# Generated by export_simulation on Mon Jun 05 20:28:18 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
|
||||
c_reg_fd_v12_0_vh_rfs.vhd,vhdl,c_reg_fd_v12_0_6,../../../ipstatic/hdl/c_reg_fd_v12_0_vh_rfs.vhd,
|
||||
xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_wrapper_v3_0_4,../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,
|
||||
|
||||
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Wed Apr 12 20:01:03 CST 2023
|
||||
# Generated by Vivado on Mon Jun 05 20:28:18 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
-makelib ies_lib/xil_defaultlib -sv \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
-endlib
|
||||
-makelib ies_lib/xpm \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
-endlib
|
||||
-makelib ies_lib/xbip_utils_v3_0_10 \
|
||||
"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 12 20:01:03 CST 2023
|
||||
# Generated by export_simulation on Mon Jun 05 20:28:18 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+3
-3
@@ -30,11 +30,11 @@ vmap axi_utils_v2_0_6 modelsim_lib/msim/axi_utils_v2_0_6
|
||||
vmap cordic_v6_0_15 modelsim_lib/msim/cordic_v6_0_15
|
||||
|
||||
vlog -work xil_defaultlib -64 -incr -sv \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -64 -93 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vcom -work xbip_utils_v3_0_10 -64 -93 \
|
||||
"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
|
||||
|
||||
+3
-3
@@ -1,6 +1,6 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
|
||||
c_reg_fd_v12_0_vh_rfs.vhd,vhdl,c_reg_fd_v12_0_6,../../../ipstatic/hdl/c_reg_fd_v12_0_vh_rfs.vhd,
|
||||
xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_wrapper_v3_0_4,../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Wed Apr 12 20:01:03 CST 2023
|
||||
# Generated by Vivado on Mon Jun 05 20:28:18 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 12 20:01:03 CST 2023
|
||||
# Generated by export_simulation on Mon Jun 05 20:28:18 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
@@ -30,11 +30,11 @@ vmap axi_utils_v2_0_6 questa_lib/msim/axi_utils_v2_0_6
|
||||
vmap cordic_v6_0_15 questa_lib/msim/cordic_v6_0_15
|
||||
|
||||
vlog -work xil_defaultlib -64 -sv \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -64 -93 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vcom -work xbip_utils_v3_0_10 -64 -93 \
|
||||
"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
|
||||
|
||||
+3
-3
@@ -1,6 +1,6 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
|
||||
c_reg_fd_v12_0_vh_rfs.vhd,vhdl,c_reg_fd_v12_0_6,../../../ipstatic/hdl/c_reg_fd_v12_0_vh_rfs.vhd,
|
||||
xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_wrapper_v3_0_4,../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Wed Apr 12 20:01:03 CST 2023
|
||||
# Generated by Vivado on Mon Jun 05 20:28:18 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 12 20:01:03 CST 2023
|
||||
# Generated by export_simulation on Mon Jun 05 20:28:18 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
@@ -30,11 +30,11 @@ vmap axi_utils_v2_0_6 riviera/axi_utils_v2_0_6
|
||||
vmap cordic_v6_0_15 riviera/cordic_v6_0_15
|
||||
|
||||
vlog -work xil_defaultlib -sv2k12 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -93 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vcom -work xbip_utils_v3_0_10 -93 \
|
||||
"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
|
||||
|
||||
+3
-3
@@ -1,6 +1,6 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
|
||||
c_reg_fd_v12_0_vh_rfs.vhd,vhdl,c_reg_fd_v12_0_6,../../../ipstatic/hdl/c_reg_fd_v12_0_vh_rfs.vhd,
|
||||
xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_wrapper_v3_0_4,../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Wed Apr 12 20:01:03 CST 2023
|
||||
# Generated by Vivado on Mon Jun 05 20:28:18 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 12 20:01:03 CST 2023
|
||||
# Generated by export_simulation on Mon Jun 05 20:28:18 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
|
||||
c_reg_fd_v12_0_vh_rfs.vhd,vhdl,c_reg_fd_v12_0_6,../../../ipstatic/hdl/c_reg_fd_v12_0_vh_rfs.vhd,
|
||||
xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_wrapper_v3_0_4,../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,
|
||||
|
||||
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Wed Apr 12 20:01:03 CST 2023
|
||||
# Generated by Vivado on Mon Jun 05 20:28:18 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
@@ -71,12 +71,12 @@ compile()
|
||||
{
|
||||
# Compile design files
|
||||
vlogan -work xil_defaultlib $vlogan_opts -sverilog \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
2>&1 | tee -a vlogan.log
|
||||
|
||||
vhdlan -work xpm $vhdlan_opts \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
2>&1 | tee -a vhdlan.log
|
||||
|
||||
vhdlan -work xbip_utils_v3_0_10 $vhdlan_opts \
|
||||
|
||||
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 12 20:01:03 CST 2023
|
||||
# Generated by export_simulation on Mon Jun 05 20:28:18 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+3
-3
@@ -1,6 +1,6 @@
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,
|
||||
xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,
|
||||
c_reg_fd_v12_0_vh_rfs.vhd,vhdl,c_reg_fd_v12_0_6,../../../ipstatic/hdl/c_reg_fd_v12_0_vh_rfs.vhd,
|
||||
xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_wrapper_v3_0_4,../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Wed Apr 12 20:01:03 CST 2023
|
||||
# Generated by Vivado on Mon Jun 05 20:28:18 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
@@ -1,9 +1,9 @@
|
||||
-makelib xcelium_lib/xil_defaultlib -sv \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
-endlib
|
||||
-makelib xcelium_lib/xpm \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
-endlib
|
||||
-makelib xcelium_lib/xbip_utils_v3_0_10 \
|
||||
"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \
|
||||
|
||||
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Wed Apr 12 20:01:03 CST 2023
|
||||
# Generated by export_simulation on Mon Jun 05 20:28:18 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Wed Apr 12 20:01:03 CST 2023
|
||||
# Generated by Vivado on Mon Jun 05 20:28:18 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
@@ -22,7 +22,7 @@
|
||||
#*********************************************************************************************************
|
||||
|
||||
# Command line options
|
||||
xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0
|
||||
xv_boost_lib_path=/home/josh/Software/Xilinx/Vivado/2019.1/tps/boost_1_64_0
|
||||
xvlog_opts="--relax"
|
||||
xvhdl_opts="--relax"
|
||||
|
||||
@@ -94,7 +94,7 @@ setup()
|
||||
copy_setup_file()
|
||||
{
|
||||
file="xsim.ini"
|
||||
lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim"
|
||||
lib_map_path="/home/josh/Software/Xilinx/Vivado/2019.1/data/xsim"
|
||||
if [[ ($1 != "") ]]; then
|
||||
lib_map_path="$1"
|
||||
fi
|
||||
|
||||
+64
@@ -0,0 +1,64 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
|
||||
<spirit:name>35ef934e18fcbb85</spirit:name>
|
||||
<spirit:version>0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>atan2_16b</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="cordic" spirit:version="6.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.FREQ_HZ">1000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACLKEN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARESETN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Architectural_Configuration">Parallel</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coarse_Rotation">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Compensation_Scaling">No_Scale_Compensation</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">atan2_16b</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Format">SignedFraction</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Functional_Selection">Arc_Tan</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Width">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Iterations">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Width">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phase_Format">Radians</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipelining_Mode">Maximum</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Precision">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Round_Mode">Truncate</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cartesian_has_tlast">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cartesian_has_tuser">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cartesian_tuser_width">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.flow_control">NonBlocking</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.optimize_goal">Performance</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.out_tlast_behv">Null</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.out_tready">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.phase_has_tlast">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.phase_has_tuser">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.phase_tuser_width">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">35ef934e18fcbb85</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">fa73b4fd</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">22</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">15</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
BIN
Binary file not shown.
LFS
Executable
BIN
Binary file not shown.
LFS
Executable
BIN
Binary file not shown.
+25
@@ -0,0 +1,25 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Mon Jun 5 20:29:00 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ atan2_16b_stub.v
|
||||
// Design : atan2_16b
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "cordic_v6_0_15,Vivado 2019.1.3" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, s_axis_cartesian_tvalid,
|
||||
s_axis_cartesian_tdata, m_axis_dout_tvalid, m_axis_dout_tdata)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_cartesian_tvalid,s_axis_cartesian_tdata[31:0],m_axis_dout_tvalid,m_axis_dout_tdata[15:0]" */;
|
||||
input aclk;
|
||||
input s_axis_cartesian_tvalid;
|
||||
input [31:0]s_axis_cartesian_tdata;
|
||||
output m_axis_dout_tvalid;
|
||||
output [15:0]m_axis_dout_tdata;
|
||||
endmodule
|
||||
+34
@@ -0,0 +1,34 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Mon Jun 5 20:29:00 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ atan2_16b_stub.vhdl
|
||||
-- Design : atan2_16b
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
s_axis_cartesian_tvalid : in STD_LOGIC;
|
||||
s_axis_cartesian_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axis_dout_tvalid : out STD_LOGIC;
|
||||
m_axis_dout_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_cartesian_tvalid,s_axis_cartesian_tdata[31:0],m_axis_dout_tvalid,m_axis_dout_tdata[15:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "cordic_v6_0_15,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+65
@@ -0,0 +1,65 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
|
||||
<spirit:name>6d0942f1ca8f60d5</spirit:name>
|
||||
<spirit:version>0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>rotate_16b</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="cordic" spirit:version="6.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.FREQ_HZ">1000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACLKEN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARESETN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Architectural_Configuration">Parallel</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coarse_Rotation">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Compensation_Scaling">No_Scale_Compensation</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">rotate_16b</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Format">SignedFraction</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Functional_Selection">Rotate</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Width">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Iterations">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Width">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Phase_Format">Radians</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipelining_Mode">Maximum</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Precision">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Round_Mode">Truncate</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cartesian_has_tlast">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cartesian_has_tuser">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.cartesian_tuser_width">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.flow_control">NonBlocking</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.optimize_goal">Performance</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.out_tlast_behv">Null</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.out_tready">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.phase_has_tlast">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.phase_has_tuser">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.phase_tuser_width">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">6d0942f1ca8f60d5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">fa73b4fd</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">24</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">15</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
BIN
Binary file not shown.
LFS
Executable
BIN
Binary file not shown.
LFS
Executable
BIN
Binary file not shown.
+28
@@ -0,0 +1,28 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Mon Jun 5 20:28:45 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rotate_16b_stub.v
|
||||
// Design : rotate_16b
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "cordic_v6_0_15,Vivado 2019.1.3" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, s_axis_phase_tvalid,
|
||||
s_axis_phase_tdata, s_axis_cartesian_tvalid, s_axis_cartesian_tdata,
|
||||
m_axis_dout_tvalid, m_axis_dout_tdata)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_phase_tvalid,s_axis_phase_tdata[15:0],s_axis_cartesian_tvalid,s_axis_cartesian_tdata[31:0],m_axis_dout_tvalid,m_axis_dout_tdata[31:0]" */;
|
||||
input aclk;
|
||||
input s_axis_phase_tvalid;
|
||||
input [15:0]s_axis_phase_tdata;
|
||||
input s_axis_cartesian_tvalid;
|
||||
input [31:0]s_axis_cartesian_tdata;
|
||||
output m_axis_dout_tvalid;
|
||||
output [31:0]m_axis_dout_tdata;
|
||||
endmodule
|
||||
+36
@@ -0,0 +1,36 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Mon Jun 5 20:28:45 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rotate_16b_stub.vhdl
|
||||
-- Design : rotate_16b
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
s_axis_phase_tvalid : in STD_LOGIC;
|
||||
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
s_axis_cartesian_tvalid : in STD_LOGIC;
|
||||
s_axis_cartesian_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
m_axis_dout_tvalid : out STD_LOGIC;
|
||||
m_axis_dout_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_phase_tvalid,s_axis_phase_tdata[15:0],s_axis_cartesian_tvalid,s_axis_cartesian_tdata[31:0],m_axis_dout_tvalid,m_axis_dout_tdata[31:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "cordic_v6_0_15,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+6
-6
@@ -1,13 +1,13 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:3238:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3634:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3636:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f7079697068616e646c65725f64657374696e6174696f6e5f69705f6e616d65:3132:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f7265747265657461626c6570616e656c5f636f72655f747265655f7461626c65:3135:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:65787072756e7472656570616e656c5f6578705f72756e5f747265655f7461626c65:3139:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6670676163686f6f7365725f667067615f7461626c65:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:333138:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6d616e6167655f6970:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:333234:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6d616e6167655f6970:3130:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6f70656e5f70726f6a656374:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f73746172745f7573696e675f76697661646f5f776974685f69705f636174616c6f67:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6861636763697073796d626f6c5f73686f775f64697361626c65645f706f727473:31:00:00
|
||||
@@ -24,16 +24,16 @@ version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f636c6f73655f70726f6a656374:3130:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f636f70795f6970:3133:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f67656e65726174655f636f6d706f736974655f66696c65:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6f70656e5f69705f6c6f636174696f6e:37:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6f70656e5f69705f6c6f636174696f6e:38:00:00
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
eof:162730464
|
||||
eof:1509944053
|
||||
|
||||
+3
-3
@@ -6,8 +6,8 @@ version:1
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:39:00:00
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726576696f7573697068616e646c6572:36:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265637573746f6d697a65636f7265:3630:00:00
|
||||
eof:63932490
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265637573746f6d697a65636f7265:3632:00:00
|
||||
eof:3995730525
|
||||
|
||||
+1
-1
@@ -1,3 +1,3 @@
|
||||
version:1
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:14
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:15
|
||||
eof:
|
||||
|
||||
+5
-5
@@ -1,7 +1,7 @@
|
||||
version:1
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863376b343130746666673930302d32:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:696c615f387831325f38313932:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:6174616e325f313662:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
@@ -33,7 +33,7 @@ version:1
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a353873:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323332332e3438304d42:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3930362e3039304d42:00:00
|
||||
eof:3884629691
|
||||
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313773:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323039312e3437374d42:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3639302e3535394d42:00:00
|
||||
eof:3006227906
|
||||
|
||||
+10
-10
@@ -3,7 +3,7 @@
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pa" timeStamp="Sun May 7 16:50:26 2023">
|
||||
<application name="pa" timeStamp="Mon Jun 5 20:29:05 2023">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="cf48733ed6784c129006f962746a20c1" type="ProjectID"/>
|
||||
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
|
||||
@@ -24,21 +24,21 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="EditDelete" value="9" type="JavaHandler"/>
|
||||
<property name="ManageCompositeTargets" value="5" type="JavaHandler"/>
|
||||
<property name="NewIPLocationHandler" value="1" type="JavaHandler"/>
|
||||
<property name="OpenIPLocationHandler" value="8" type="JavaHandler"/>
|
||||
<property name="OpenIPLocationHandler" value="9" type="JavaHandler"/>
|
||||
<property name="OpenPreviousIPHandler" value="6" type="JavaHandler"/>
|
||||
<property name="OpenProject" value="1" type="JavaHandler"/>
|
||||
<property name="RecustomizeCore" value="60" type="JavaHandler"/>
|
||||
<property name="RecustomizeCore" value="62" type="JavaHandler"/>
|
||||
</item>
|
||||
<item name="Gui Handlers">
|
||||
<property name="BaseDialog_CANCEL" value="28" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_OK" value="64" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_OK" value="66" type="GuiHandlerData"/>
|
||||
<property name="CmdMsgDialog_OK" value="3" type="GuiHandlerData"/>
|
||||
<property name="CopyIPHandler_DESTINATION_IP_NAME" value="12" type="GuiHandlerData"/>
|
||||
<property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="15" type="GuiHandlerData"/>
|
||||
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="19" type="GuiHandlerData"/>
|
||||
<property name="FPGAChooser_FPGA_TABLE" value="1" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="318" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_MANAGE_IP" value="9" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="324" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_MANAGE_IP" value="10" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_OPEN_PROJECT" value="1" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_START_USING_VIVADO_WITH_IP_CATALOG" value="3" type="GuiHandlerData"/>
|
||||
<property name="HACGCIPSymbol_SHOW_DISABLED_PORTS" value="1" type="GuiHandlerData"/>
|
||||
@@ -55,13 +55,13 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="PACommandNames_CLOSE_PROJECT" value="10" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_COPY_IP" value="13" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_GENERATE_COMPOSITE_FILE" value="3" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_OPEN_IP_LOCATION" value="7" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_OPEN_IP_LOCATION" value="8" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_RESET_COMPOSITE_FILE" value="2" type="GuiHandlerData"/>
|
||||
<property name="ProgressDialog_BACKGROUND" value="5" type="GuiHandlerData"/>
|
||||
<property name="RDICommands_DELETE" value="1" type="GuiHandlerData"/>
|
||||
<property name="RemoveSourcesDialog_ALSO_DELETE" value="8" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_CLOSE_DIALOG_UNSAVED_CHANGES_WILL" value="6" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="19" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="21" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_RESET_OUTPUT_PRODUCTS" value="1" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_ADD_CONFIGURABLE_IP_FILES" value="15" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_MAKE_LOCAL_COPY_OF_THESE_FILES_INTO" value="1" type="GuiHandlerData"/>
|
||||
@@ -69,9 +69,9 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="SyntheticaGettingStartedView_RECENT_IP_LOCATIONS" value="6" type="GuiHandlerData"/>
|
||||
</item>
|
||||
<item name="Other">
|
||||
<property name="GuiMode" value="116" type="GuiMode"/>
|
||||
<property name="GuiMode" value="9" type="GuiMode"/>
|
||||
<property name="BatchMode" value="0" type="BatchMode"/>
|
||||
<property name="TclMode" value="82" type="TclMode"/>
|
||||
<property name="TclMode" value="4" type="TclMode"/>
|
||||
</item>
|
||||
</section>
|
||||
</application>
|
||||
|
||||
+8
@@ -0,0 +1,8 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="rotate_16b_synth_1" LaunchDir="/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
+8
@@ -0,0 +1,8 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="atan2_16b_synth_1" LaunchDir="/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="add_s24_s32_s32_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300767">
|
||||
<File Type="RDS-UTIL" Name="add_s24_s32_s32_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="add_s24_s32_s32_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="add_s24_s32_s32_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="add_s24_s32_s32.vds"/>
|
||||
<File Type="RDS-DCP" Name="add_s24_s32_s32.dcp"/>
|
||||
<File Type="PA-TCL" Name="add_s24_s32_s32.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="ant_clk_gen_stg1_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300767">
|
||||
<File Type="RDS-UTIL" Name="ant_clk_gen_stg1_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ant_clk_gen_stg1_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="ant_clk_gen_stg1_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="ant_clk_gen_stg1.vds"/>
|
||||
<File Type="RDS-DCP" Name="ant_clk_gen_stg1.dcp"/>
|
||||
<File Type="PA-TCL" Name="ant_clk_gen_stg1.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="ant_clk_gen_stg2_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300767">
|
||||
<File Type="RDS-UTIL" Name="ant_clk_gen_stg2_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ant_clk_gen_stg2_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="ant_clk_gen_stg2_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="ant_clk_gen_stg2.vds"/>
|
||||
<File Type="RDS-DCP" Name="ant_clk_gen_stg2.dcp"/>
|
||||
<File Type="PA-TCL" Name="ant_clk_gen_stg2.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,5 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado" Owner="josh" Host="JOSH-ASUS-Z690" Pid="277330" HostCore="20" HostMemory="65589000">
|
||||
<Process Command="vivado" Owner="josh" Host="JOSH-ASUS-Z690" Pid="1070164" HostCore="20" HostMemory="65588996">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
|
||||
BIN
Binary file not shown.
-2
@@ -17,8 +17,6 @@ proc create_report { reportName command } {
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
set_param simulator.modelsimInstallPath /home/josh/Software/Mentor/modeltech/bin
|
||||
set_param simulator.vcsmxInstallPath /usr/synopsys/vcs/T-2022.06/bin
|
||||
set_param project.vivado.isBlockSynthRun true
|
||||
set_msg_config -msgmgr_mode ooc_run
|
||||
create_project -in_memory -part xc7k410tffg900-2
|
||||
|
||||
+50
-51
@@ -2,8 +2,8 @@
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Wed Apr 12 19:59:29 2023
|
||||
# Process ID: 277922
|
||||
# Start of session at: Mon Jun 5 20:28:34 2023
|
||||
# Process ID: 1070203
|
||||
# Current directory: /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1
|
||||
# Command line: vivado -log atan2_16b.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source atan2_16b.tcl
|
||||
# Log file: /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b.vds
|
||||
@@ -16,9 +16,9 @@ Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t'
|
||||
INFO: [Device 21-403] Loading part xc7k410tffg900-2
|
||||
INFO: Launching helper process for spawning children vivado processes
|
||||
INFO: Helper process launched with PID 278285
|
||||
INFO: Helper process launched with PID 1070336
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 1824.492 ; gain = 152.719 ; free physical = 675 ; free virtual = 44056
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1825.977 ; gain = 153.719 ; free physical = 1830 ; free virtual = 37269
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-638] synthesizing module 'atan2_16b' [/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/atan2_16b/synth/atan2_16b.vhd:69]
|
||||
Parameter C_ARCHITECTURE bound to: 2 - type: integer
|
||||
@@ -34,7 +34,7 @@ INFO: [Synth 8-638] synthesizing module 'atan2_16b' [/home/josh/Workspace/vivado
|
||||
Parameter C_INPUT_WIDTH bound to: 16 - type: integer
|
||||
Parameter C_ITERATIONS bound to: 0 - type: integer
|
||||
Parameter C_OUTPUT_WIDTH bound to: 16 - type: integer
|
||||
Parameter C_PHASE_FORMAT bound to: 1 - type: integer
|
||||
Parameter C_PHASE_FORMAT bound to: 0 - type: integer
|
||||
Parameter C_PIPELINE_MODE bound to: -2 - type: integer
|
||||
Parameter C_PRECISION bound to: 0 - type: integer
|
||||
Parameter C_ROUND_MODE bound to: 0 - type: integer
|
||||
@@ -155,7 +155,7 @@ WARNING: [Synth 8-3331] design c_addsub_v12_0_13_legacy has unconnected port a_s
|
||||
WARNING: [Synth 8-3331] design c_addsub_v12_0_13_legacy has unconnected port b_signed
|
||||
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1926.211 ; gain = 254.438 ; free physical = 6153 ; free virtual = 48543
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1926.695 ; gain = 254.438 ; free physical = 2821 ; free virtual = 38104
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
@@ -168,10 +168,10 @@ Report Check Netlist:
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1926.211 ; gain = 254.438 ; free physical = 6276 ; free virtual = 48667
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1926.695 ; gain = 254.438 ; free physical = 2820 ; free virtual = 38105
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1926.211 ; gain = 254.438 ; free physical = 6276 ; free virtual = 48666
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1926.695 ; gain = 254.438 ; free physical = 2820 ; free virtual = 38105
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Netlist 29-17] Analyzing 1931 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
@@ -185,30 +185,30 @@ Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/ma
|
||||
Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/dont_touch.xdc]
|
||||
Completed Processing XDC Constraints
|
||||
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2090.992 ; gain = 0.000 ; free physical = 6905 ; free virtual = 49302
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2091.477 ; gain = 0.000 ; free physical = 2695 ; free virtual = 37993
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2090.992 ; gain = 0.000 ; free physical = 6897 ; free virtual = 49296
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2091.477 ; gain = 0.000 ; free physical = 2695 ; free virtual = 37993
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 7497 ; free virtual = 49905
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2766 ; free virtual = 38073
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7k410tffg900-2
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 7497 ; free virtual = 49905
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2766 ; free virtual = 38073
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying 'set_property' XDC Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
Applied set_property DONT_TOUCH = true for U0. (constraint file /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/dont_touch.xdc, line 9).
|
||||
---------------------------------------------------------------------------------
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 7496 ; free virtual = 49904
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2766 ; free virtual = 38073
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 7580 ; free virtual = 50002
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2763 ; free virtual = 38072
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
@@ -276,26 +276,25 @@ INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[17]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[19]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[18]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[19]'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[19] )
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[0]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[0]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[10]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[1]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[2]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[3]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[4]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[5]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[6]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[7]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[8]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[9]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[10]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[11]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[12]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[13]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[14]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[15]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[17]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[18]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[18]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[19]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[6]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[11]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[7]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[8]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[8]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[9]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[9]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[12]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[10]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[13]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[11]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[14]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[12]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[15]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[13]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[16]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[14]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[18]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[15]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[19]'
|
||||
INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[17]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]'
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 8146 ; free virtual = 50611
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2788 ; free virtual = 38104
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
@@ -307,13 +306,13 @@ Report RTL Partitions:
|
||||
Start Applying XDC Timing Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:25 ; elapsed = 00:00:29 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 8656 ; free virtual = 51196
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2643 ; free virtual = 37981
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:25 ; elapsed = 00:00:29 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 8735 ; free virtual = 51282
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2637 ; free virtual = 37975
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
@@ -325,7 +324,7 @@ Report RTL Partitions:
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:25 ; elapsed = 00:00:30 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 8641 ; free virtual = 51225
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2634 ; free virtual = 37976
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
@@ -349,7 +348,7 @@ Start Final Netlist Cleanup
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:26 ; elapsed = 00:00:30 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 8644 ; free virtual = 51253
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2632 ; free virtual = 37976
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
@@ -362,7 +361,7 @@ Report Check Netlist:
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:26 ; elapsed = 00:00:30 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 8643 ; free virtual = 51252
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2632 ; free virtual = 37976
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
@@ -374,25 +373,25 @@ Report RTL Partitions:
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:26 ; elapsed = 00:00:30 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 8614 ; free virtual = 51232
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2632 ; free virtual = 37976
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:26 ; elapsed = 00:00:30 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 8609 ; free virtual = 51229
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2632 ; free virtual = 37976
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:26 ; elapsed = 00:00:30 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 8600 ; free virtual = 51220
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2632 ; free virtual = 37976
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:26 ; elapsed = 00:00:30 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 8599 ; free virtual = 51220
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2632 ; free virtual = 37976
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
@@ -408,46 +407,46 @@ Report Cell Usage:
|
||||
+------+--------+------+
|
||||
| |Cell |Count |
|
||||
+------+--------+------+
|
||||
|1 |LUT1 | 69|
|
||||
|2 |LUT2 | 344|
|
||||
|3 |LUT3 | 527|
|
||||
|1 |LUT1 | 65|
|
||||
|2 |LUT2 | 335|
|
||||
|3 |LUT3 | 537|
|
||||
|4 |LUT4 | 32|
|
||||
|5 |MUXCY | 838|
|
||||
|6 |SRL16E | 5|
|
||||
|7 |SRLC32E | 1|
|
||||
|8 |XORCY | 806|
|
||||
|9 |FDRE | 929|
|
||||
|9 |FDRE | 930|
|
||||
+------+--------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:26 ; elapsed = 00:00:30 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 8598 ; free virtual = 51219
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2632 ; free virtual = 37976
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 308 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2090.992 ; gain = 254.438 ; free physical = 8624 ; free virtual = 51252
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:26 ; elapsed = 00:00:31 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 8622 ; free virtual = 51251
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 2091.477 ; gain = 254.438 ; free physical = 2684 ; free virtual = 38028
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2684 ; free virtual = 38028
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Netlist 29-17] Analyzing 1644 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2090.992 ; gain = 0.000 ; free physical = 9379 ; free virtual = 52041
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2091.477 ; gain = 0.000 ; free physical = 2623 ; free virtual = 37972
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
A total of 222 instances were transformed.
|
||||
(MUXCY,XORCY) => CARRY4: 222 instances
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
70 Infos, 100 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
69 Infos, 100 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2090.992 ; gain = 697.527 ; free physical = 9577 ; free virtual = 52238
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2090.992 ; gain = 0.000 ; free physical = 9589 ; free virtual = 52251
|
||||
synth_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 2091.477 ; gain = 696.496 ; free physical = 2715 ; free virtual = 38064
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2091.477 ; gain = 0.000 ; free physical = 2715 ; free virtual = 38064
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b.dcp' has been generated.
|
||||
WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
|
||||
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP atan2_16b, cache-ID = d02f40fcf613a5a3
|
||||
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP atan2_16b, cache-ID = 35ef934e18fcbb85
|
||||
INFO: [Coretcl 2-1174] Renamed 350 cell refs.
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2115.004 ; gain = 0.000 ; free physical = 10245 ; free virtual = 52938
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2115.488 ; gain = 0.000 ; free physical = 2711 ; free virtual = 38080
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file atan2_16b_utilization_synth.rpt -pb atan2_16b_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Wed Apr 12 20:00:13 2023...
|
||||
INFO: [Common 17-206] Exiting Vivado at Mon Jun 5 20:29:01 2023...
|
||||
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
+1
-1
@@ -1,7 +1,7 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Wed Apr 12 20:00:12 2023
|
||||
// Date : Mon Jun 5 20:29:00 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_stub.v
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Wed Apr 12 20:00:12 2023
|
||||
-- Date : Mon Jun 5 20:29:01 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_stub.vhdl
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user