Archived
update phase comp with cmpy; add var cal module
This commit is contained in:
-283
@@ -1,283 +0,0 @@
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`pragma protect begin_protected
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`pragma protect version = 1
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`pragma protect encrypt_agent = "XILINX"
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`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1"
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`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
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`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`pragma protect key_block
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`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
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`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`pragma protect key_block
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`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
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`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`pragma protect key_block
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`pragma protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
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`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`pragma protect key_block
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`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa"
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`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`pragma protect key_block
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`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
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`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`pragma protect key_block
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R19uHYIhWP+7IpmjTiQ=
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`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
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`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`pragma protect key_block
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`pragma protect data_method = "AES128-CBC"
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`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12464)
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`pragma protect data_block
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dB5LUUJUKbnsl6q5E9b8DkJqSnAaHRLJDnEvMp6EfGlpc52On3lCg0wI5XERerziamjcMH44VZfd
|
||||
j8z1WUyHlyOSmkvZdJ66PfYWu5BxCG7hfdtSGROPtIxs36iLmesyYm4yHKwwbWgNIrLgra92DF2L
|
||||
R6e0RM1WWkcJHei4v89Nmwym4k0dKMTX1HkfTogoprrdIyDYj4qMmeTqfl0U8pRehVs6/zy4x8HS
|
||||
0V2+smFFQ/BZxLQ4eV8NHKeszc4kI6jJ3OCncsP57tfkE6TmVTtWKiimERISYB4KhUpblsbN6zyX
|
||||
Bni5ezNwl9XdaBq9c90k+QQmaMGeyQbczdGy9ufcC269vB1FU5+a67Ew8h0jPAPeYHvsw4kGsTSh
|
||||
xnhGNUHRuPoNmQYBjI2LztvnbGuoucUVntUi5quKpKAK1fOZerZTh+kr5PjaW0YlozpL5CtElvS3
|
||||
eqqkVT8a5mdW+sWTxJxTjqronag0QACsSwbA9qurCW9IdcOO+0D7nzfIJIFrWKx+D71JhKNvOmUa
|
||||
NmCy9l+wzdpcLs1zvS3o3zwEgUWOOHzITgzOxtDhIuBcJkg9lS+o5b+W+U9fplCbVFjYd5ZDa2sX
|
||||
90/8XCJA0a9VcsSrh1LoO0V3YX80VWdNPY79OUOlqftl3rNXVXE=
|
||||
`pragma protect end_protected
|
||||
+23
-6
@@ -48,19 +48,36 @@
|
||||
`timescale 1ns / 1ps
|
||||
module vio_phase_comp (
|
||||
clk,
|
||||
|
||||
probe_in0,probe_in1,probe_in2,
|
||||
probe_out0,
|
||||
probe_out1,
|
||||
probe_out2,
|
||||
probe_out3
|
||||
probe_out3,
|
||||
probe_out4,
|
||||
probe_out5,
|
||||
probe_out6,
|
||||
probe_out7,
|
||||
probe_out8,
|
||||
probe_out9,
|
||||
probe_out10
|
||||
);
|
||||
|
||||
input clk;
|
||||
input [31 : 0] probe_in0;
|
||||
input [0 : 0] probe_in1;
|
||||
input [0 : 0] probe_in2;
|
||||
|
||||
output reg [15 : 0] probe_out0 = 'h0000 ;
|
||||
output reg [15 : 0] probe_out1 = 'h0000 ;
|
||||
output reg [15 : 0] probe_out2 = 'h0000 ;
|
||||
output reg [15 : 0] probe_out3 = 'h0000 ;
|
||||
output reg [0 : 0] probe_out0 = 'h0 ;
|
||||
output reg [0 : 0] probe_out1 = 'h0 ;
|
||||
output reg [11 : 0] probe_out2 = 'h000 ;
|
||||
output reg [11 : 0] probe_out3 = 'h000 ;
|
||||
output reg [11 : 0] probe_out4 = 'h000 ;
|
||||
output reg [11 : 0] probe_out5 = 'h000 ;
|
||||
output reg [11 : 0] probe_out6 = 'h000 ;
|
||||
output reg [11 : 0] probe_out7 = 'h000 ;
|
||||
output reg [11 : 0] probe_out8 = 'h000 ;
|
||||
output reg [11 : 0] probe_out9 = 'h000 ;
|
||||
output reg [4 : 0] probe_out10 = 'h09 ;
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
+15
-5
@@ -55,11 +55,21 @@
|
||||
|
||||
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
||||
vio_phase_comp your_instance_name (
|
||||
.clk(clk), // input wire clk
|
||||
.probe_out0(probe_out0), // output wire [15 : 0] probe_out0
|
||||
.probe_out1(probe_out1), // output wire [15 : 0] probe_out1
|
||||
.probe_out2(probe_out2), // output wire [15 : 0] probe_out2
|
||||
.probe_out3(probe_out3) // output wire [15 : 0] probe_out3
|
||||
.clk(clk), // input wire clk
|
||||
.probe_in0(probe_in0), // input wire [31 : 0] probe_in0
|
||||
.probe_in1(probe_in1), // input wire [0 : 0] probe_in1
|
||||
.probe_in2(probe_in2), // input wire [0 : 0] probe_in2
|
||||
.probe_out0(probe_out0), // output wire [0 : 0] probe_out0
|
||||
.probe_out1(probe_out1), // output wire [0 : 0] probe_out1
|
||||
.probe_out2(probe_out2), // output wire [11 : 0] probe_out2
|
||||
.probe_out3(probe_out3), // output wire [11 : 0] probe_out3
|
||||
.probe_out4(probe_out4), // output wire [11 : 0] probe_out4
|
||||
.probe_out5(probe_out5), // output wire [11 : 0] probe_out5
|
||||
.probe_out6(probe_out6), // output wire [11 : 0] probe_out6
|
||||
.probe_out7(probe_out7), // output wire [11 : 0] probe_out7
|
||||
.probe_out8(probe_out8), // output wire [11 : 0] probe_out8
|
||||
.probe_out9(probe_out9), // output wire [11 : 0] probe_out9
|
||||
.probe_out10(probe_out10) // output wire [4 : 0] probe_out10
|
||||
);
|
||||
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
|
||||
+25
-5
@@ -55,10 +55,20 @@
|
||||
COMPONENT vio_phase_comp
|
||||
PORT (
|
||||
clk : IN STD_LOGIC;
|
||||
probe_out0 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
probe_out1 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
probe_out2 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
|
||||
probe_out3 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
|
||||
probe_in0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
probe_in1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe_in2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe_out1 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
probe_out2 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
|
||||
probe_out3 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
|
||||
probe_out4 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
|
||||
probe_out5 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
|
||||
probe_out6 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
|
||||
probe_out7 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
|
||||
probe_out8 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
|
||||
probe_out9 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
|
||||
probe_out10 : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
|
||||
@@ -70,10 +80,20 @@ END COMPONENT;
|
||||
your_instance_name : vio_phase_comp
|
||||
PORT MAP (
|
||||
clk => clk,
|
||||
probe_in0 => probe_in0,
|
||||
probe_in1 => probe_in1,
|
||||
probe_in2 => probe_in2,
|
||||
probe_out0 => probe_out0,
|
||||
probe_out1 => probe_out1,
|
||||
probe_out2 => probe_out2,
|
||||
probe_out3 => probe_out3
|
||||
probe_out3 => probe_out3,
|
||||
probe_out4 => probe_out4,
|
||||
probe_out5 => probe_out5,
|
||||
probe_out6 => probe_out6,
|
||||
probe_out7 => probe_out7,
|
||||
probe_out8 => probe_out8,
|
||||
probe_out9 => probe_out9,
|
||||
probe_out10 => probe_out10
|
||||
);
|
||||
-- INST_TAG_END ------ End INSTANTIATION Template ---------
|
||||
|
||||
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
+20
-9
@@ -1,10 +1,10 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Wed May 17 22:20:56 2023
|
||||
// Date : Mon Jun 12 15:47:42 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.v
|
||||
// /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.v
|
||||
// Design : vio_phase_comp
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
@@ -14,12 +14,23 @@
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
|
||||
module vio_phase_comp(clk, probe_out0, probe_out1, probe_out2,
|
||||
probe_out3)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[15:0],probe_out1[15:0],probe_out2[15:0],probe_out3[15:0]" */;
|
||||
module vio_phase_comp(clk, probe_in0, probe_in1, probe_in2, probe_out0,
|
||||
probe_out1, probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8,
|
||||
probe_out9, probe_out10)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[31:0],probe_in1[0:0],probe_in2[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[11:0],probe_out3[11:0],probe_out4[11:0],probe_out5[11:0],probe_out6[11:0],probe_out7[11:0],probe_out8[11:0],probe_out9[11:0],probe_out10[4:0]" */;
|
||||
input clk;
|
||||
output [15:0]probe_out0;
|
||||
output [15:0]probe_out1;
|
||||
output [15:0]probe_out2;
|
||||
output [15:0]probe_out3;
|
||||
input [31:0]probe_in0;
|
||||
input [0:0]probe_in1;
|
||||
input [0:0]probe_in2;
|
||||
output [0:0]probe_out0;
|
||||
output [0:0]probe_out1;
|
||||
output [11:0]probe_out2;
|
||||
output [11:0]probe_out3;
|
||||
output [11:0]probe_out4;
|
||||
output [11:0]probe_out5;
|
||||
output [11:0]probe_out6;
|
||||
output [11:0]probe_out7;
|
||||
output [11:0]probe_out8;
|
||||
output [11:0]probe_out9;
|
||||
output [4:0]probe_out10;
|
||||
endmodule
|
||||
|
||||
+17
-7
@@ -1,10 +1,10 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Wed May 17 22:20:56 2023
|
||||
-- Date : Mon Jun 12 15:47:42 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_online_acq/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.vhdl
|
||||
-- /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.vhdl
|
||||
-- Design : vio_phase_comp
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
@@ -15,10 +15,20 @@ use IEEE.STD_LOGIC_1164.ALL;
|
||||
entity vio_phase_comp is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe_out0 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out1 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out3 : out STD_LOGIC_VECTOR ( 15 downto 0 )
|
||||
probe_in0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_in2 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out2 : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe_out3 : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe_out4 : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe_out5 : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe_out6 : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe_out7 : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe_out8 : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe_out9 : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe_out10 : out STD_LOGIC_VECTOR ( 4 downto 0 )
|
||||
);
|
||||
|
||||
end vio_phase_comp;
|
||||
@@ -27,7 +37,7 @@ architecture stub of vio_phase_comp is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[15:0],probe_out1[15:0],probe_out2[15:0],probe_out3[15:0]";
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[31:0],probe_in1[0:0],probe_in2[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[11:0],probe_out3[11:0],probe_out4[11:0],probe_out5[11:0],probe_out6[11:0],probe_out7[11:0],probe_out8[11:0],probe_out9[11:0],probe_out10[4:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
|
||||
begin
|
||||
|
||||
+3821
File diff suppressed because it is too large
Load Diff
+12017
File diff suppressed because it is too large
Load Diff
+17045
File diff suppressed because it is too large
Load Diff
+1367
File diff suppressed because it is too large
Load Diff
+418
@@ -0,0 +1,418 @@
|
||||
`protect begin_protected
|
||||
`protect version = 1
|
||||
`protect encrypt_agent = "XILINX"
|
||||
`protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1"
|
||||
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
|
||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
|
||||
`protect key_block
|
||||
IijDYFYeRdzkel5iYnZFe2NzgYX9UDO+g6PdWiHeOm5P1+m9Kt//ktx0y9l3PqUsSWKKIi5tWbDg
|
||||
OqtBZeM3zQ==
|
||||
|
||||
`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
|
||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`protect key_block
|
||||
TXFD8G5gE6CUfZ/9/aBQvAaQuQ9Q6vcW5KJtFkYqsiROk19a5PsS1gCxUXtSJ+Xt20njQCTMz6jx
|
||||
UaSmsNRyiV6PuCAgdQYvfeJWiNmQq7kXQnkYSjycSJyNe/xoXEYIK0mHX7J2x9ouXxNx6jQFR5Lm
|
||||
jxY8fR7N9m3PTkCqNTI=
|
||||
|
||||
`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
|
||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`protect key_block
|
||||
0bdD7I2gr0nFDramUUXzPCEqtk/eE+vK1bghpNlKE+S5t5/NbqJI7gNd3XLwYh6qEIInU1StLpm1
|
||||
ZEERnCmEf4+rQBAW7x7u7nIsJjSOmPWtDc9DLn5S3e1Tg+IzLUqT0rFFh5TiwuYq9A6oIvI4ufWQ
|
||||
WwoeY/gITSdj6C0JQ3GFyIRhxG7psQKO9U4fj8El/Lb3YXG1+IGuXZsygyLPjjOU5LRXKo6kKsub
|
||||
X1PFDvdm4rWaB9AqoPLCqp654KCyKSCoufeM/jiWRTNXwf6kL56WQKDXuyAhrasBOno4KOT3c5VP
|
||||
WEHGNdGBSdU4oUFYiOmAKlCKGeUNCxMxx765QA==
|
||||
|
||||
`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
|
||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`protect key_block
|
||||
ppkak8ss4yKmNiAZjxFq8nn58TDV/6CNcvQivN+uaaTC1viFh2EDUvJp8zqZ2dJOE2mTN9WJY0VD
|
||||
93fjF/bEPMptIxFj5D6ldjwJu+xdHqS9FJ9Wajnbu++DCTUtAQE+y05rqhCz8aZWKGNejsRfG8bE
|
||||
xGYNUIbFoZ9PYrDIdRcDSdZRUBadrAC+WcEM6+/HxxJq4Ly/w0BVbiEq22B0+4wVDXszrocC0mKJ
|
||||
RPXzPj9v5D5aBX2ijUGbICpT6JkVGAjlIEP7HZoc+Ooxppwgc01k8snVnPVI4IVVYOjjlTQgT/qU
|
||||
t0doYgFMU9nD5a1hefzXRkszYn9RHVZE5bl6NA==
|
||||
|
||||
`protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa"
|
||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`protect key_block
|
||||
KtmDUKyPqH21pzMoqq9CPc/SXFhh6Oz2JrLSFRZBS3mGc7ebGc8cQjlvJpJA0WNJlGqACicdvN1t
|
||||
A7mG3V1xKtoRdR+2MhucMQ7loisN8yDj3+zqgbM5bAdlz+62WovuGfaM4EK24l8CXSfBLVGQ35JP
|
||||
2zB0abBrel1cOw3DxvSIS/5wueR9/Ul+GoLmD6yF7cV2ne7eGwNXQ2OsCqdcb9wK8gNO1YfC3kE6
|
||||
WwdUtjutDvyXnV49wmg6nCC8RAPNWbIhHiMMtpDjux6E1Rkd3xdCMDrxrupZyNQNtVmzcN8ITAn5
|
||||
BYoTBON1CKVljCmLov84lxcdcXGcSaBAtLIiAg==
|
||||
|
||||
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
|
||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
|
||||
`protect key_block
|
||||
sjMrK19OPSOpuNhtGVc8GPvvQoA4nRSUShUtMXVan8pbxWL4SmeH0c+Lr407Kf0YXDBqUDDkheov
|
||||
bvkczAmQfT+dVPmRtr9F/s03c46gcXSPX3D/EHROl21MVjaptRm/lAFzU2JR3vIcBrSyn9KnB+G8
|
||||
cTUA3hZ8VcZWUlsE5EU=
|
||||
|
||||
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
|
||||
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
|
||||
`protect key_block
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||||
KnmRsadIXQ==
|
||||
`protect end_protected
|
||||
+2392
File diff suppressed because it is too large
Load Diff
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Sun May 21 16:31:40 CST 2023
|
||||
# Generated by export_simulation on Mon Jun 12 15:47:25 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+2
-2
@@ -8,10 +8,10 @@ vmap xil_defaultlib activehdl/xil_defaultlib
|
||||
vmap xpm activehdl/xpm
|
||||
|
||||
vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/vio_phase_comp/hdl/verilog" "+incdir+../../../ip/vio_phase_comp/hdl" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -93 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/vio_phase_comp/hdl/verilog" "+incdir+../../../ip/vio_phase_comp/hdl" \
|
||||
"../../../ip/vio_phase_comp/sim/vio_phase_comp.v" \
|
||||
|
||||
+2
-2
@@ -1,4 +1,4 @@
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
|
||||
vio_phase_comp.v,verilog,xil_defaultlib,../../../ip/vio_phase_comp/sim/vio_phase_comp.v,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Sun May 21 16:31:40 CST 2023
|
||||
# Generated by Vivado on Mon Jun 12 15:47:25 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Sun May 21 16:31:40 CST 2023
|
||||
# Generated by export_simulation on Mon Jun 12 15:47:25 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+2
-2
@@ -1,4 +1,4 @@
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
|
||||
vio_phase_comp.v,verilog,xil_defaultlib,../../../ip/vio_phase_comp/sim/vio_phase_comp.v,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
|
||||
+2
-2
@@ -1,8 +1,8 @@
|
||||
-makelib ies_lib/xil_defaultlib -sv \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
-endlib
|
||||
-makelib ies_lib/xpm \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
-endlib
|
||||
-makelib ies_lib/xil_defaultlib \
|
||||
"../../../ip/vio_phase_comp/sim/vio_phase_comp.v" \
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Sun May 21 16:31:40 CST 2023
|
||||
# Generated by Vivado on Mon Jun 12 15:47:25 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Sun May 21 16:31:40 CST 2023
|
||||
# Generated by export_simulation on Mon Jun 12 15:47:25 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
-8
@@ -2,16 +2,8 @@ vlib modelsim_lib/work
|
||||
vlib modelsim_lib/msim
|
||||
|
||||
vlib modelsim_lib/msim/xil_defaultlib
|
||||
vlib modelsim_lib/msim/xpm
|
||||
|
||||
vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
|
||||
vmap xpm modelsim_lib/msim/xpm
|
||||
|
||||
vlog -work xil_defaultlib -64 -incr -sv "+incdir+../../../ip/vio_phase_comp/hdl/verilog" "+incdir+../../../ip/vio_phase_comp/hdl" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -64 -93 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vlog -work xil_defaultlib -64 -incr "+incdir+../../../ip/vio_phase_comp/hdl/verilog" "+incdir+../../../ip/vio_phase_comp/hdl" \
|
||||
"../../../ip/vio_phase_comp/sim/vio_phase_comp.v" \
|
||||
|
||||
-2
@@ -1,4 +1,2 @@
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
|
||||
vio_phase_comp.v,verilog,xil_defaultlib,../../../ip/vio_phase_comp/sim/vio_phase_comp.v,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
onbreak {quit -f}
|
||||
onerror {quit -f}
|
||||
|
||||
vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.vio_phase_comp xil_defaultlib.glbl
|
||||
vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.vio_phase_comp xil_defaultlib.glbl
|
||||
|
||||
do {wave.do}
|
||||
|
||||
|
||||
+3
-4
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Sun May 21 16:31:40 CST 2023
|
||||
# Generated by Vivado on Mon Jun 12 15:47:25 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
@@ -95,11 +95,10 @@ setup()
|
||||
copy_setup_file()
|
||||
{
|
||||
file="modelsim.ini"
|
||||
lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
|
||||
if [[ ($1 != "" && -e $1) ]]; then
|
||||
if [[ ($1 != "") ]]; then
|
||||
lib_map_path="$1"
|
||||
else
|
||||
echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
|
||||
lib_map_path="/home/josh/Software/Xilinx/CompLib/Model/2019.1"
|
||||
fi
|
||||
if [[ ($lib_map_path != "") ]]; then
|
||||
src_file="$lib_map_path/$file"
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Sun May 21 16:31:40 CST 2023
|
||||
# Generated by export_simulation on Mon Jun 12 15:47:25 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+2
-2
@@ -8,10 +8,10 @@ vmap xil_defaultlib questa_lib/msim/xil_defaultlib
|
||||
vmap xpm questa_lib/msim/xpm
|
||||
|
||||
vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/vio_phase_comp/hdl/verilog" "+incdir+../../../ip/vio_phase_comp/hdl" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -64 -93 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vlog -work xil_defaultlib -64 "+incdir+../../../ip/vio_phase_comp/hdl/verilog" "+incdir+../../../ip/vio_phase_comp/hdl" \
|
||||
"../../../ip/vio_phase_comp/sim/vio_phase_comp.v" \
|
||||
|
||||
+2
-2
@@ -1,4 +1,4 @@
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
|
||||
vio_phase_comp.v,verilog,xil_defaultlib,../../../ip/vio_phase_comp/sim/vio_phase_comp.v,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
|
||||
+3
-2
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Sun May 21 16:31:40 CST 2023
|
||||
# Generated by Vivado on Mon Jun 12 15:47:25 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
@@ -102,9 +102,10 @@ setup()
|
||||
copy_setup_file()
|
||||
{
|
||||
file="modelsim.ini"
|
||||
lib_map_path=""
|
||||
if [[ ($1 != "") ]]; then
|
||||
lib_map_path="$1"
|
||||
else
|
||||
lib_map_path="/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa"
|
||||
fi
|
||||
if [[ ($lib_map_path != "") ]]; then
|
||||
src_file="$lib_map_path/$file"
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Sun May 21 16:31:40 CST 2023
|
||||
# Generated by export_simulation on Mon Jun 12 15:47:25 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+2
-2
@@ -8,10 +8,10 @@ vmap xil_defaultlib riviera/xil_defaultlib
|
||||
vmap xpm riviera/xpm
|
||||
|
||||
vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/vio_phase_comp/hdl/verilog" "+incdir+../../../ip/vio_phase_comp/hdl" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
|
||||
vcom -work xpm -93 \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
|
||||
vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/vio_phase_comp/hdl/verilog" "+incdir+../../../ip/vio_phase_comp/hdl" \
|
||||
"../../../ip/vio_phase_comp/sim/vio_phase_comp.v" \
|
||||
|
||||
+2
-2
@@ -1,4 +1,4 @@
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
|
||||
vio_phase_comp.v,verilog,xil_defaultlib,../../../ip/vio_phase_comp/sim/vio_phase_comp.v,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
|
||||
+3
-2
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Sun May 21 16:31:40 CST 2023
|
||||
# Generated by Vivado on Mon Jun 12 15:47:25 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
@@ -93,9 +93,10 @@ setup()
|
||||
map_setup_file()
|
||||
{
|
||||
file="library.cfg"
|
||||
lib_map_path=""
|
||||
if [[ ($1 != "") ]]; then
|
||||
lib_map_path="$1"
|
||||
else
|
||||
lib_map_path="/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera"
|
||||
fi
|
||||
if [[ ($lib_map_path != "") ]]; then
|
||||
src_file="$lib_map_path/$file"
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Sun May 21 16:31:40 CST 2023
|
||||
# Generated by export_simulation on Mon Jun 12 15:47:25 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
-2
@@ -1,4 +1,2 @@
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
|
||||
vio_phase_comp.v,verilog,xil_defaultlib,../../../ip/vio_phase_comp/sim/vio_phase_comp.v,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
|
||||
+4
-11
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Sun May 21 16:31:40 CST 2023
|
||||
# Generated by Vivado on Mon Jun 12 15:47:25 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
@@ -48,7 +48,7 @@ vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log"
|
||||
vcs_sim_opts="-ucli -licqueue -l simulate.log"
|
||||
|
||||
# Design libraries
|
||||
design_libs=(xil_defaultlib xpm)
|
||||
design_libs=(xil_defaultlib)
|
||||
|
||||
# Simulation root library directory
|
||||
sim_lib_dir="vcs_lib"
|
||||
@@ -70,14 +70,6 @@ run()
|
||||
compile()
|
||||
{
|
||||
# Compile design files
|
||||
vlogan -work xil_defaultlib $vlogan_opts -sverilog +incdir+"$ref_dir/../../../ip/vio_phase_comp/hdl/verilog" +incdir+"$ref_dir/../../../ip/vio_phase_comp/hdl" \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
2>&1 | tee -a vlogan.log
|
||||
|
||||
vhdlan -work xpm $vhdlan_opts \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
2>&1 | tee -a vhdlan.log
|
||||
|
||||
vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ip/vio_phase_comp/hdl/verilog" +incdir+"$ref_dir/../../../ip/vio_phase_comp/hdl" \
|
||||
"$ref_dir/../../../ip/vio_phase_comp/sim/vio_phase_comp.v" \
|
||||
2>&1 | tee -a vlogan.log
|
||||
@@ -146,9 +138,10 @@ create_lib_mappings()
|
||||
|
||||
touch $file
|
||||
|
||||
lib_map_path=""
|
||||
if [[ ($1 != "") ]]; then
|
||||
lib_map_path="$1"
|
||||
else
|
||||
lib_map_path="/home/josh/Software/Xilinx/CompLib/VCS/2019.1"
|
||||
fi
|
||||
|
||||
for (( i=0; i<${#design_libs[*]}; i++ )); do
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Sun May 21 16:31:40 CST 2023
|
||||
# Generated by export_simulation on Mon Jun 12 15:47:25 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+2
-2
@@ -1,4 +1,4 @@
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
|
||||
xpm_memory.sv,systemverilog,xil_defaultlib,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
|
||||
xpm_VCOMP.vhd,vhdl,xpm,../../josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
|
||||
vio_phase_comp.v,verilog,xil_defaultlib,../../../ip/vio_phase_comp/sim/vio_phase_comp.v,incdir="../../../ip/vio_phase_comp/hdl/verilog"incdir="../../../ip/vio_phase_comp/hdl"
|
||||
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||
|
||||
+2
-2
@@ -1,8 +1,8 @@
|
||||
-makelib xcelium_lib/xil_defaultlib -sv \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \
|
||||
-endlib
|
||||
-makelib xcelium_lib/xpm \
|
||||
"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \
|
||||
-endlib
|
||||
-makelib xcelium_lib/xil_defaultlib \
|
||||
"../../../ip/vio_phase_comp/sim/vio_phase_comp.v" \
|
||||
|
||||
+1
-1
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Sun May 21 16:31:40 CST 2023
|
||||
# Generated by Vivado on Mon Jun 12 15:47:25 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
+1
-1
@@ -4,7 +4,7 @@
|
||||
# README.txt: Please read the sections below to understand the steps required to
|
||||
# run the exported script and information about the source files.
|
||||
#
|
||||
# Generated by export_simulation on Sun May 21 16:31:40 CST 2023
|
||||
# Generated by export_simulation on Mon Jun 12 15:47:25 CST 2023
|
||||
#
|
||||
################################################################################
|
||||
|
||||
|
||||
+3
-3
@@ -9,7 +9,7 @@
|
||||
# directory, add the library logical mappings in the simulator setup file, create default
|
||||
# 'do/prj' file, execute compilation, elaboration and simulation steps.
|
||||
#
|
||||
# Generated by Vivado on Sun May 21 16:31:40 CST 2023
|
||||
# Generated by Vivado on Mon Jun 12 15:47:25 CST 2023
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
#
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
@@ -22,7 +22,7 @@
|
||||
#*********************************************************************************************************
|
||||
|
||||
# Command line options
|
||||
xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0
|
||||
xv_boost_lib_path=/home/josh/Software/Xilinx/Vivado/2019.1/tps/boost_1_64_0
|
||||
xvlog_opts="--relax"
|
||||
|
||||
|
||||
@@ -92,7 +92,7 @@ setup()
|
||||
copy_setup_file()
|
||||
{
|
||||
file="xsim.ini"
|
||||
lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim"
|
||||
lib_map_path="/home/josh/Software/Xilinx/Vivado/2019.1/data/xsim"
|
||||
if [[ ($1 != "") ]]; then
|
||||
lib_map_path="$1"
|
||||
fi
|
||||
|
||||
+810
@@ -0,0 +1,810 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
|
||||
<spirit:name>199e9237e9cad44f</spirit:name>
|
||||
<spirit:version>0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>vio_phase_comp</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="vio" spirit:version="3.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EN_PROBE_IN_ACTIVITY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EN_SYNCHRONIZATION">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PROBE_IN">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PROBE_OUT">11</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN0_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN100_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN101_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN102_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN103_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN104_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN105_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN106_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN107_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN108_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN109_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN10_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN110_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN111_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN112_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN113_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN114_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN115_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN116_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN117_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN118_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN119_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN11_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN120_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN121_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN122_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN123_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN124_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN125_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN126_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN127_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN128_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN129_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN12_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN130_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN131_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN132_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN133_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN134_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN135_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN136_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN137_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN138_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN139_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN13_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN140_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN141_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN142_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN143_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN144_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN145_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN146_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN147_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN148_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN149_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN14_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN150_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN151_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN152_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN153_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN154_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN155_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN156_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN157_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN158_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN159_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN15_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN160_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN161_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN162_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN163_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN164_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN165_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN166_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN167_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN168_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN169_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN16_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN170_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN171_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN172_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN173_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN174_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN175_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN176_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN177_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN178_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN179_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN17_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN180_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN181_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN182_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN183_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN184_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN185_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN186_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN187_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN188_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN189_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN18_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN190_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN191_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN192_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN193_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN194_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN195_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN196_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN197_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN198_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN199_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN19_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN1_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN200_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN201_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN202_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN203_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN204_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN205_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN206_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN207_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN208_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN209_WIDTH">1</spirit:configurableElementValue>
|
||||
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BIN
Binary file not shown.
BIN
Binary file not shown.
BIN
Binary file not shown.
+36
@@ -0,0 +1,36 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Mon Jun 12 15:47:42 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_phase_comp_stub.v
|
||||
// Design : vio_phase_comp
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_in0, probe_in1, probe_in2, probe_out0,
|
||||
probe_out1, probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8,
|
||||
probe_out9, probe_out10)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[31:0],probe_in1[0:0],probe_in2[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[11:0],probe_out3[11:0],probe_out4[11:0],probe_out5[11:0],probe_out6[11:0],probe_out7[11:0],probe_out8[11:0],probe_out9[11:0],probe_out10[4:0]" */;
|
||||
input clk;
|
||||
input [31:0]probe_in0;
|
||||
input [0:0]probe_in1;
|
||||
input [0:0]probe_in2;
|
||||
output [0:0]probe_out0;
|
||||
output [0:0]probe_out1;
|
||||
output [11:0]probe_out2;
|
||||
output [11:0]probe_out3;
|
||||
output [11:0]probe_out4;
|
||||
output [11:0]probe_out5;
|
||||
output [11:0]probe_out6;
|
||||
output [11:0]probe_out7;
|
||||
output [11:0]probe_out8;
|
||||
output [11:0]probe_out9;
|
||||
output [4:0]probe_out10;
|
||||
endmodule
|
||||
+44
@@ -0,0 +1,44 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Mon Jun 12 15:47:42 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_phase_comp_stub.vhdl
|
||||
-- Design : vio_phase_comp
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe_in0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_in2 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out2 : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe_out3 : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe_out4 : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe_out5 : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe_out6 : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe_out7 : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe_out8 : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe_out9 : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe_out10 : out STD_LOGIC_VECTOR ( 4 downto 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[31:0],probe_in1[0:0],probe_in2[0:0],probe_out0[0:0],probe_out1[0:0],probe_out2[11:0],probe_out3[11:0],probe_out4[11:0],probe_out5[11:0],probe_out6[11:0],probe_out7[11:0],probe_out8[11:0],probe_out9[11:0],probe_out10[4:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
|
||||
begin
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+810
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BIN
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BIN
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BIN
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+27
@@ -0,0 +1,27 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Sun Jun 11 17:20:35 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_phase_comp_stub.v
|
||||
// Design : vio_phase_comp
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_in0, probe_out0, probe_out1,
|
||||
probe_out2, probe_out3, probe_out4)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[31:0],probe_out0[15:0],probe_out1[15:0],probe_out2[15:0],probe_out3[15:0],probe_out4[0:0]" */;
|
||||
input clk;
|
||||
input [31:0]probe_in0;
|
||||
output [15:0]probe_out0;
|
||||
output [15:0]probe_out1;
|
||||
output [15:0]probe_out2;
|
||||
output [15:0]probe_out3;
|
||||
output [0:0]probe_out4;
|
||||
endmodule
|
||||
+36
@@ -0,0 +1,36 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Sun Jun 11 17:20:35 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_phase_comp_stub.vhdl
|
||||
-- Design : vio_phase_comp
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe_in0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_out0 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out1 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out3 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out4 : out STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[31:0],probe_out0[15:0],probe_out1[15:0],probe_out2[15:0],probe_out3[15:0],probe_out4[0:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
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|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">vio_phase_comp</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">6c756528e746e3c7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">9a10a187</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">13</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">20</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
BIN
Binary file not shown.
+35
@@ -0,0 +1,35 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Mon Jun 12 14:39:21 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_phase_comp_stub.v
|
||||
// Design : vio_phase_comp
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_in0, probe_in1, probe_in2, probe_out0,
|
||||
probe_out1, probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8,
|
||||
probe_out9)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[31:0],probe_in1[0:0],probe_in2[0:0],probe_out0[0:0],probe_out1[11:0],probe_out2[11:0],probe_out3[11:0],probe_out4[11:0],probe_out5[11:0],probe_out6[11:0],probe_out7[11:0],probe_out8[11:0],probe_out9[4:0]" */;
|
||||
input clk;
|
||||
input [31:0]probe_in0;
|
||||
input [0:0]probe_in1;
|
||||
input [0:0]probe_in2;
|
||||
output [0:0]probe_out0;
|
||||
output [11:0]probe_out1;
|
||||
output [11:0]probe_out2;
|
||||
output [11:0]probe_out3;
|
||||
output [11:0]probe_out4;
|
||||
output [11:0]probe_out5;
|
||||
output [11:0]probe_out6;
|
||||
output [11:0]probe_out7;
|
||||
output [11:0]probe_out8;
|
||||
output [4:0]probe_out9;
|
||||
endmodule
|
||||
+43
@@ -0,0 +1,43 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Mon Jun 12 14:39:21 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_phase_comp_stub.vhdl
|
||||
-- Design : vio_phase_comp
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe_in0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_in2 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out1 : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe_out2 : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe_out3 : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe_out4 : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe_out5 : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe_out6 : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe_out7 : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe_out8 : out STD_LOGIC_VECTOR ( 11 downto 0 );
|
||||
probe_out9 : out STD_LOGIC_VECTOR ( 4 downto 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[31:0],probe_in1[0:0],probe_in2[0:0],probe_out0[0:0],probe_out1[11:0],probe_out2[11:0],probe_out3[11:0],probe_out4[11:0],probe_out5[11:0],probe_out6[11:0],probe_out7[11:0],probe_out8[11:0],probe_out9[4:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+62
@@ -0,0 +1,62 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
|
||||
<spirit:name>7ceac1c5ccccf5df</spirit:name>
|
||||
<spirit:version>0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>cmpy_18x18</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="cmpy" spirit:version="6.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.FREQ_HZ">10000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_A.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_B.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACLKEN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.APortWidth">18</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARESETN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ATUSERWidth">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BPortWidth">18</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BTUSERWidth">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CTRLTUSERWidth">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">cmpy_18x18</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FlowControl">NonBlocking</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HasATLAST">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HasATUSER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HasBTLAST">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HasBTUSER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HasCTRLTLAST">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HasCTRLTUSER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LatencyConfig">Automatic</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MinimumLatency">6</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MultType">Use_Mults</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OptimizeGoal">Resources</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OutTLASTBehv">Null</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OutputWidth">37</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RoundMode">Truncate</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k410t</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">7ceac1c5ccccf5df</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">c296bec2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">17</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
BIN
Binary file not shown.
+27
@@ -0,0 +1,27 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Sun Jun 11 14:38:07 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ cmpy_18x18_stub.v
|
||||
// Design : cmpy_18x18
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "cmpy_v6_0_17,Vivado 2019.1.3" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, s_axis_a_tvalid, s_axis_a_tdata,
|
||||
s_axis_b_tvalid, s_axis_b_tdata, m_axis_dout_tvalid, m_axis_dout_tdata)
|
||||
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_a_tvalid,s_axis_a_tdata[47:0],s_axis_b_tvalid,s_axis_b_tdata[47:0],m_axis_dout_tvalid,m_axis_dout_tdata[79:0]" */;
|
||||
input aclk;
|
||||
input s_axis_a_tvalid;
|
||||
input [47:0]s_axis_a_tdata;
|
||||
input s_axis_b_tvalid;
|
||||
input [47:0]s_axis_b_tdata;
|
||||
output m_axis_dout_tvalid;
|
||||
output [79:0]m_axis_dout_tdata;
|
||||
endmodule
|
||||
+36
@@ -0,0 +1,36 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Sun Jun 11 14:38:07 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ cmpy_18x18_stub.vhdl
|
||||
-- Design : cmpy_18x18
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
aclk : in STD_LOGIC;
|
||||
s_axis_a_tvalid : in STD_LOGIC;
|
||||
s_axis_a_tdata : in STD_LOGIC_VECTOR ( 47 downto 0 );
|
||||
s_axis_b_tvalid : in STD_LOGIC;
|
||||
s_axis_b_tdata : in STD_LOGIC_VECTOR ( 47 downto 0 );
|
||||
m_axis_dout_tvalid : out STD_LOGIC;
|
||||
m_axis_dout_tdata : out STD_LOGIC_VECTOR ( 79 downto 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_a_tvalid,s_axis_a_tdata[47:0],s_axis_b_tvalid,s_axis_b_tdata[47:0],m_axis_dout_tvalid,m_axis_dout_tdata[79:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "cmpy_v6_0_17,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+810
@@ -0,0 +1,810 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>ipcache</spirit:library>
|
||||
<spirit:name>c8b4974eb08248f9</spirit:name>
|
||||
<spirit:version>0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>vio_phase_comp</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="vio" spirit:version="3.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EN_PROBE_IN_ACTIVITY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EN_SYNCHRONIZATION">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PROBE_IN">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PROBE_OUT">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN0_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN100_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN101_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN102_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN103_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN104_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN105_WIDTH">1</spirit:configurableElementValue>
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BIN
Binary file not shown.
BIN
Binary file not shown.
BIN
Binary file not shown.
+28
@@ -0,0 +1,28 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
// Date : Sun Jun 11 17:23:44 2023
|
||||
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_phase_comp_stub.v
|
||||
// Design : vio_phase_comp
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7k410tffg900-2
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* X_CORE_INFO = "vio,Vivado 2019.1.3" *)
|
||||
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_in0, probe_in1, probe_out0,
|
||||
probe_out1, probe_out2, probe_out3, probe_out4)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[31:0],probe_in1[0:0],probe_out0[15:0],probe_out1[15:0],probe_out2[15:0],probe_out3[15:0],probe_out4[0:0]" */;
|
||||
input clk;
|
||||
input [31:0]probe_in0;
|
||||
input [0:0]probe_in1;
|
||||
output [15:0]probe_out0;
|
||||
output [15:0]probe_out1;
|
||||
output [15:0]probe_out2;
|
||||
output [15:0]probe_out3;
|
||||
output [0:0]probe_out4;
|
||||
endmodule
|
||||
+37
@@ -0,0 +1,37 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
|
||||
-- Date : Sun Jun 11 17:23:44 2023
|
||||
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
|
||||
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_phase_comp_stub.vhdl
|
||||
-- Design : vio_phase_comp
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7k410tffg900-2
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
Port (
|
||||
clk : in STD_LOGIC;
|
||||
probe_in0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
probe_out0 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out1 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out3 : out STD_LOGIC_VECTOR ( 15 downto 0 );
|
||||
probe_out4 : out STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
|
||||
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
|
||||
|
||||
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[31:0],probe_in1[0:0],probe_out0[15:0],probe_out1[15:0],probe_out2[15:0],probe_out3[15:0],probe_out4[0:0]";
|
||||
attribute X_CORE_INFO : string;
|
||||
attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3";
|
||||
begin
|
||||
end;
|
||||
+14
-13
@@ -1,28 +1,29 @@
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version:1
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|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636f7079697068616e646c6572:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:637573746f6d697a65636f7265:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:36:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:637573746f6d697a65636f7265:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:37:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6d616e616765636f6d706f7369746574617267657473:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657769706c6f636174696f6e68616e646c6572:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e69706c6f636174696f6e68616e646c6572:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e69706c6f636174696f6e68616e646c6572:37:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726576696f7573697068616e646c6572:39:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265637573746f6d697a65636f7265:3230:00:00
|
||||
eof:2577552565
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265637573746f6d697a65636f7265:3237:00:00
|
||||
eof:976246183
|
||||
|
||||
+1
-1
@@ -1,3 +1,3 @@
|
||||
version:1
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:12
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:16
|
||||
eof:
|
||||
|
||||
+4
-4
@@ -1,7 +1,7 @@
|
||||
version:1
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863376b343130746666673930302d32:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:76696f5f6d616e75616c5f6374726c:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:76696f5f70686173655f636f6d70:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
@@ -34,6 +34,6 @@ version:1
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313073:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323037392e3638344d42:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3637362e3830314d42:00:00
|
||||
eof:3750586285
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323038362e3136304d42:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3638332e3237374d42:00:00
|
||||
eof:1830882776
|
||||
|
||||
+22
-21
@@ -3,7 +3,7 @@
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pa" timeStamp="Sun May 21 16:32:31 2023">
|
||||
<application name="pa" timeStamp="Mon Jun 12 15:47:48 2023">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="ce818763e31a4de8ac7850431f15fb5a" type="ProjectID"/>
|
||||
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
|
||||
@@ -17,49 +17,50 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
|
||||
</item>
|
||||
<item name="Java Command Handlers">
|
||||
<property name="AddExistingIPHandler" value="4" type="JavaHandler"/>
|
||||
<property name="CloseProject" value="5" type="JavaHandler"/>
|
||||
<property name="AddExistingIPHandler" value="5" type="JavaHandler"/>
|
||||
<property name="CloseProject" value="9" type="JavaHandler"/>
|
||||
<property name="CopyIPHandler" value="3" type="JavaHandler"/>
|
||||
<property name="CustomizeCore" value="1" type="JavaHandler"/>
|
||||
<property name="EditDelete" value="6" type="JavaHandler"/>
|
||||
<property name="CustomizeCore" value="3" type="JavaHandler"/>
|
||||
<property name="EditDelete" value="7" type="JavaHandler"/>
|
||||
<property name="ManageCompositeTargets" value="3" type="JavaHandler"/>
|
||||
<property name="NewIPLocationHandler" value="1" type="JavaHandler"/>
|
||||
<property name="OpenIPLocationHandler" value="3" type="JavaHandler"/>
|
||||
<property name="OpenIPLocationHandler" value="7" type="JavaHandler"/>
|
||||
<property name="OpenPreviousIPHandler" value="9" type="JavaHandler"/>
|
||||
<property name="RecustomizeCore" value="20" type="JavaHandler"/>
|
||||
<property name="RecustomizeCore" value="27" type="JavaHandler"/>
|
||||
</item>
|
||||
<item name="Gui Handlers">
|
||||
<property name="BaseDialog_CANCEL" value="10" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_OK" value="30" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_CANCEL" value="16" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_OK" value="39" type="GuiHandlerData"/>
|
||||
<property name="CopyIPHandler_DESTINATION_IP_NAME" value="3" type="GuiHandlerData"/>
|
||||
<property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="4" type="GuiHandlerData"/>
|
||||
<property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="10" type="GuiHandlerData"/>
|
||||
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="10" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="104" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_MANAGE_IP" value="4" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="137" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_MANAGE_IP" value="8" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_START_USING_VIVADO_WITH_IP_CATALOG" value="1" type="GuiHandlerData"/>
|
||||
<property name="HACGCCoeFileWidget_BROWSE" value="1" type="GuiHandlerData"/>
|
||||
<property name="HJFileChooserHelpers_JUMP_TO_RECENT_PROJECT_DIRECTORY" value="1" type="GuiHandlerData"/>
|
||||
<property name="IPCoreView_TABBED_PANE" value="2" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_FILE" value="10" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_EDIT" value="2" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_FILE" value="20" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_OPEN_RECENT_PROJECT" value="2" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_PROJECT" value="6" type="GuiHandlerData"/>
|
||||
<property name="MainMenuMgr_PROJECT" value="10" type="GuiHandlerData"/>
|
||||
<property name="NewIPProjectWizard_IP_LOCATION" value="1" type="GuiHandlerData"/>
|
||||
<property name="NewIPProjectWizard_PART" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_ADD_EXISTING_IP" value="4" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_CLOSE_PROJECT" value="5" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_ADD_EXISTING_IP" value="5" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_CLOSE_PROJECT" value="9" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_COPY_IP" value="3" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_GENERATE_COMPOSITE_FILE" value="3" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_OPEN_IP_LOCATION" value="3" type="GuiHandlerData"/>
|
||||
<property name="RemoveSourcesDialog_ALSO_DELETE" value="6" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="15" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_OPEN_IP_LOCATION" value="7" type="GuiHandlerData"/>
|
||||
<property name="RemoveSourcesDialog_ALSO_DELETE" value="7" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="20" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_ADD_CONFIGURABLE_IP_FILES" value="5" type="GuiHandlerData"/>
|
||||
<property name="SrcMenu_IP_DOCUMENTATION" value="5" type="GuiHandlerData"/>
|
||||
<property name="SyntheticaGettingStartedView_RECENT_IP_LOCATIONS" value="9" type="GuiHandlerData"/>
|
||||
</item>
|
||||
<item name="Other">
|
||||
<property name="GuiMode" value="144" type="GuiMode"/>
|
||||
<property name="GuiMode" value="11" type="GuiMode"/>
|
||||
<property name="BatchMode" value="0" type="BatchMode"/>
|
||||
<property name="TclMode" value="101" type="TclMode"/>
|
||||
<property name="TclMode" value="6" type="TclMode"/>
|
||||
</item>
|
||||
</section>
|
||||
</application>
|
||||
|
||||
+8
@@ -0,0 +1,8 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="cmpy_18x18_synth_1" LaunchDir="/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/cmpy_18x18_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
+8
@@ -0,0 +1,8 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="vio_phase_comp_synth_1" LaunchDir="/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
+8
@@ -0,0 +1,8 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="vio_phase_comp_synth_1" LaunchDir="/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
+8
@@ -0,0 +1,8 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="vio_phase_comp_synth_1" LaunchDir="/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
+8
@@ -0,0 +1,8 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="vio_phase_comp_synth_1" LaunchDir="/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
+1
-1
@@ -1,9 +1,9 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="vio_manual_ctrl_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1682237933">
|
||||
<File Type="PA-TCL" Name="vio_manual_ctrl.tcl"/>
|
||||
<File Type="RDS-DCP" Name="vio_manual_ctrl.dcp"/>
|
||||
<File Type="REPORTS-TCL" Name="vio_manual_ctrl_reports.tcl"/>
|
||||
<File Type="RDS-RDS" Name="vio_manual_ctrl.vds"/>
|
||||
<File Type="RDS-DCP" Name="vio_manual_ctrl.dcp"/>
|
||||
<File Type="RDS-UTIL-PB" Name="vio_manual_ctrl_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="vio_manual_ctrl_utilization_synth.rpt"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_manual_ctrl">
|
||||
|
||||
+5
@@ -0,0 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado" Owner="josh" Host="JOSH-ASUS-Z690" Pid="2733262" HostCore="20" HostMemory="65588992">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
+270
@@ -0,0 +1,270 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
// GLOBAL VARIABLES
|
||||
var ISEShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var ISERunDir = "";
|
||||
var ISELogFile = "runme.log";
|
||||
var ISELogFileStr = null;
|
||||
var ISELogEcho = true;
|
||||
var ISEOldVersionWSH = false;
|
||||
|
||||
|
||||
|
||||
// BOOTSTRAP
|
||||
ISEInit();
|
||||
|
||||
|
||||
|
||||
//
|
||||
// ISE FUNCTIONS
|
||||
//
|
||||
function ISEInit() {
|
||||
|
||||
// 1. RUN DIR setup
|
||||
var ISEScrFP = WScript.ScriptFullName;
|
||||
var ISEScrN = WScript.ScriptName;
|
||||
ISERunDir =
|
||||
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
|
||||
|
||||
// 2. LOG file setup
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
// 3. LOG echo?
|
||||
var ISEScriptArgs = WScript.Arguments;
|
||||
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
|
||||
if ( ISEScriptArgs(loopi) == "-quiet" ) {
|
||||
ISELogEcho = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// 4. WSH version check
|
||||
var ISEOptimalVersionWSH = 5.6;
|
||||
var ISECurrentVersionWSH = WScript.Version;
|
||||
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
|
||||
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
|
||||
ISEOptimalVersionWSH + " or higher. Downloads" );
|
||||
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
|
||||
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
|
||||
ISEStdErr( "" );
|
||||
|
||||
ISEOldVersionWSH = true;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEStep( ISEProg, ISEArgs ) {
|
||||
|
||||
// CHECK for a STOP FILE
|
||||
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "*** Halting run - EA reset detected ***" );
|
||||
ISEStdErr( "" );
|
||||
WScript.Quit( 1 );
|
||||
}
|
||||
|
||||
// WRITE STEP HEADER to LOG
|
||||
ISEStdOut( "" );
|
||||
ISEStdOut( "*** Running " + ISEProg );
|
||||
ISEStdOut( " with args " + ISEArgs );
|
||||
ISEStdOut( "" );
|
||||
|
||||
// LAUNCH!
|
||||
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
|
||||
if ( ISEExitCode != 0 ) {
|
||||
WScript.Quit( ISEExitCode );
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEExec( ISEProg, ISEArgs ) {
|
||||
|
||||
var ISEStep = ISEProg;
|
||||
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
|
||||
ISEProg += ".bat";
|
||||
}
|
||||
|
||||
var ISECmdLine = ISEProg + " " + ISEArgs;
|
||||
var ISEExitCode = 1;
|
||||
|
||||
if ( ISEOldVersionWSH ) { // WSH 5.1
|
||||
|
||||
// BEGIN file creation
|
||||
ISETouchFile( ISEStep, "begin" );
|
||||
|
||||
// LAUNCH!
|
||||
ISELogFileStr.Close();
|
||||
ISECmdLine =
|
||||
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
|
||||
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
} else { // WSH 5.6
|
||||
|
||||
// LAUNCH!
|
||||
ISEShell.CurrentDirectory = ISERunDir;
|
||||
|
||||
// Redirect STDERR to STDOUT
|
||||
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
|
||||
var ISEProcess = ISEShell.Exec( ISECmdLine );
|
||||
|
||||
// BEGIN file creation
|
||||
var wbemFlagReturnImmediately = 0x10;
|
||||
var wbemFlagForwardOnly = 0x20;
|
||||
var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
|
||||
var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var NOC = 0;
|
||||
var NOLP = 0;
|
||||
var TPM = 0;
|
||||
|
||||
var cpuInfos = new Enumerator(processor);
|
||||
for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
|
||||
var cpuInfo = cpuInfos.item();
|
||||
NOC += cpuInfo.NumberOfCores;
|
||||
NOLP += cpuInfo.NumberOfLogicalProcessors;
|
||||
}
|
||||
var csInfos = new Enumerator(computerSystem);
|
||||
for(;!csInfos.atEnd(); csInfos.moveNext()) {
|
||||
var csInfo = csInfos.item();
|
||||
TPM += csInfo.TotalPhysicalMemory;
|
||||
}
|
||||
|
||||
var ISEHOSTCORE = NOLP
|
||||
var ISEMEMTOTAL = TPM
|
||||
|
||||
var ISENetwork = WScript.CreateObject( "WScript.Network" );
|
||||
var ISEHost = ISENetwork.ComputerName;
|
||||
var ISEUser = ISENetwork.UserName;
|
||||
var ISEPid = ISEProcess.ProcessID;
|
||||
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
|
||||
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
|
||||
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
|
||||
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
|
||||
"\" Owner=\"" + ISEUser +
|
||||
"\" Host=\"" + ISEHost +
|
||||
"\" Pid=\"" + ISEPid +
|
||||
"\" HostCore=\"" + ISEHOSTCORE +
|
||||
"\" HostMemory=\"" + ISEMEMTOTAL +
|
||||
"\">" );
|
||||
ISEBeginFile.WriteLine( " </Process>" );
|
||||
ISEBeginFile.WriteLine( "</ProcessHandle>" );
|
||||
ISEBeginFile.Close();
|
||||
|
||||
var ISEOutStr = ISEProcess.StdOut;
|
||||
var ISEErrStr = ISEProcess.StdErr;
|
||||
|
||||
// WAIT for ISEStep to finish
|
||||
while ( ISEProcess.Status == 0 ) {
|
||||
|
||||
// dump stdout then stderr - feels a little arbitrary
|
||||
while ( !ISEOutStr.AtEndOfStream ) {
|
||||
ISEStdOut( ISEOutStr.ReadLine() );
|
||||
}
|
||||
|
||||
WScript.Sleep( 100 );
|
||||
}
|
||||
|
||||
ISEExitCode = ISEProcess.ExitCode;
|
||||
}
|
||||
|
||||
ISELogFileStr.Close();
|
||||
|
||||
// END/ERROR file creation
|
||||
if ( ISEExitCode != 0 ) {
|
||||
ISETouchFile( ISEStep, "error" );
|
||||
|
||||
} else {
|
||||
ISETouchFile( ISEStep, "end" );
|
||||
}
|
||||
|
||||
return ISEExitCode;
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// UTILITIES
|
||||
//
|
||||
function ISEStdOut( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdOut.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISEStdErr( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdErr.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISETouchFile( ISERoot, ISEStatus ) {
|
||||
|
||||
var ISETFile =
|
||||
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
|
||||
ISETFile.Close();
|
||||
}
|
||||
|
||||
function ISEOpenFile( ISEFilename ) {
|
||||
|
||||
// This function has been updated to deal with a problem seen in CR #870871.
|
||||
// In that case the user runs a script that runs impl_1, and then turns around
|
||||
// and runs impl_1 -to_step write_bitstream. That second run takes place in
|
||||
// the same directory, which means we may hit some of the same files, and in
|
||||
// particular, we will open the runme.log file. Even though this script closes
|
||||
// the file (now), we see cases where a subsequent attempt to open the file
|
||||
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
|
||||
// play? In any case, we try to work around this by first waiting if the file
|
||||
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
|
||||
// and try to open the file 10 times with a one second delay after each attempt.
|
||||
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
|
||||
// If there is an unrecognized exception when trying to open the file, we output
|
||||
// an error message and write details to an exception.log file.
|
||||
var ISEFullPath = ISERunDir + "/" + ISEFilename;
|
||||
if (ISEFileSys.FileExists(ISEFullPath)) {
|
||||
// File is already there. This could be a problem. Wait in case it is still in use.
|
||||
WScript.Sleep(5000);
|
||||
}
|
||||
var i;
|
||||
for (i = 0; i < 10; ++i) {
|
||||
try {
|
||||
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
|
||||
} catch (exception) {
|
||||
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
|
||||
if (error_code == 52) { // 52 is bad file name or number.
|
||||
// Wait a second and try again.
|
||||
WScript.Sleep(1000);
|
||||
continue;
|
||||
} else {
|
||||
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
var exceptionFilePath = ISERunDir + "/exception.log";
|
||||
if (!ISEFileSys.FileExists(exceptionFilePath)) {
|
||||
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
|
||||
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
|
||||
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
exceptionFile.WriteLine("\tException name: " + exception.name);
|
||||
exceptionFile.WriteLine("\tException error code: " + error_code);
|
||||
exceptionFile.WriteLine("\tException message: " + exception.message);
|
||||
exceptionFile.Close();
|
||||
}
|
||||
throw exception;
|
||||
}
|
||||
}
|
||||
}
|
||||
// If we reached this point, we failed to open the file after 10 attempts.
|
||||
// We need to error out.
|
||||
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
|
||||
WScript.Quit(1);
|
||||
}
|
||||
+67
@@ -0,0 +1,67 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# ISEWrap.sh: Vivado Runs Script for UNIX
|
||||
# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
HD_LOG=$1
|
||||
shift
|
||||
|
||||
# CHECK for a STOP FILE
|
||||
if [ -f .stop.rst ]
|
||||
then
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
exit 1
|
||||
fi
|
||||
|
||||
ISE_STEP=$1
|
||||
shift
|
||||
|
||||
# WRITE STEP HEADER to LOG
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Running $ISE_STEP" >> $HD_LOG
|
||||
echo " with args $@" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
|
||||
# LAUNCH!
|
||||
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
|
||||
|
||||
# BEGIN file creation
|
||||
ISE_PID=$!
|
||||
if [ X != X$HOSTNAME ]
|
||||
then
|
||||
ISE_HOST=$HOSTNAME #bash
|
||||
else
|
||||
ISE_HOST=$HOST #csh
|
||||
fi
|
||||
ISE_USER=$USER
|
||||
|
||||
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
|
||||
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
|
||||
|
||||
ISE_BEGINFILE=.$ISE_STEP.begin.rst
|
||||
/bin/touch $ISE_BEGINFILE
|
||||
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
|
||||
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
|
||||
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
|
||||
echo " </Process>" >> $ISE_BEGINFILE
|
||||
echo "</ProcessHandle>" >> $ISE_BEGINFILE
|
||||
|
||||
# WAIT for ISEStep to finish
|
||||
wait $ISE_PID
|
||||
|
||||
# END/ERROR file creation
|
||||
RETVAL=$?
|
||||
if [ $RETVAL -eq 0 ]
|
||||
then
|
||||
/bin/touch .$ISE_STEP.end.rst
|
||||
else
|
||||
/bin/touch .$ISE_STEP.error.rst
|
||||
fi
|
||||
|
||||
exit $RETVAL
|
||||
|
||||
+62
@@ -0,0 +1,62 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="vio_phase_comp_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1686556045">
|
||||
<File Type="VDS-TIMING-PB" Name="vio_phase_comp_timing_summary_synth.pb"/>
|
||||
<File Type="VDS-TIMINGSUMMARY" Name="vio_phase_comp_timing_summary_synth.rpt"/>
|
||||
<File Type="RDS-DCP" Name="vio_phase_comp.dcp"/>
|
||||
<File Type="RDS-UTIL-PB" Name="vio_phase_comp_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="vio_phase_comp_utilization_synth.rpt"/>
|
||||
<File Type="RDS-PROPCONSTRS" Name="vio_phase_comp_drc_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="vio_phase_comp.vds"/>
|
||||
<File Type="REPORTS-TCL" Name="vio_phase_comp_reports.tcl"/>
|
||||
<File Type="PA-TCL" Name="vio_phase_comp.tcl"/>
|
||||
<FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_phase_comp">
|
||||
<File Path="$PPRDIR/../rx_pre_process/vio_phase_comp.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../rx_pre_process/vio_phase_comp/vio_phase_comp.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="vio_phase_comp"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_phase_comp">
|
||||
<File Path="$PPRDIR/../rx_pre_process/vio_phase_comp.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../rx_pre_process/vio_phase_comp/vio_phase_comp.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="vio_phase_comp"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
+9
@@ -0,0 +1,9 @@
|
||||
#
|
||||
# Vivado(TM)
|
||||
# htr.txt: a Vivado-generated description of how-to-repeat the
|
||||
# the basic steps of a run. Note that runme.bat/sh needs
|
||||
# to be invoked for Vivado to track run status.
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
vivado -log vio_phase_comp.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_phase_comp.tcl
|
||||
+36
@@ -0,0 +1,36 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:33:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:35:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c626c6b5f6d656d5f67656e5f76385f345f335c726f6d5f686f705f64617461:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f63616c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f686f70:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f6d616e75616c5f6374726c:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f70686173655f636f6d70:636f72655f636f6e7461696e6572:74727565:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3234:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3234:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3234:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3234:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3234:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3234:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3234:00:00
|
||||
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3966393835363732626435303431393139633038356339623061353561633562:506172656e742050412070726f6a656374204944:00
|
||||
eof:2331005995
|
||||
+40
@@ -0,0 +1,40 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
echo "This script was generated under a different operating system."
|
||||
echo "Please update the PATH variable below, before executing this script"
|
||||
exit
|
||||
|
||||
var WshShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ProcEnv = WshShell.Environment( "Process" );
|
||||
var PathVal = ProcEnv("PATH");
|
||||
if ( PathVal.length == 0 ) {
|
||||
PathVal = "/home/josh/Software/Xilinx/SDK/2019.1/bin:/home/josh/Software/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/home/josh/Software/Xilinx/Vivado/2019.1/bin;";
|
||||
} else {
|
||||
PathVal = "/home/josh/Software/Xilinx/SDK/2019.1/bin:/home/josh/Software/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/home/josh/Software/Xilinx/Vivado/2019.1/bin;" + PathVal;
|
||||
}
|
||||
|
||||
ProcEnv("PATH") = PathVal;
|
||||
|
||||
var RDScrFP = WScript.ScriptFullName;
|
||||
var RDScrN = WScript.ScriptName;
|
||||
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
|
||||
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
|
||||
eval( EAInclude(ISEJScriptLib) );
|
||||
|
||||
|
||||
ISEStep( "vivado",
|
||||
"-log vio_phase_comp.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_phase_comp.tcl" );
|
||||
|
||||
|
||||
|
||||
function EAInclude( EAInclFilename ) {
|
||||
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
|
||||
var EAIFContents = EAInclFile.ReadAll();
|
||||
EAInclFile.Close();
|
||||
return EAIFContents;
|
||||
}
|
||||
+11
@@ -0,0 +1,11 @@
|
||||
@echo off
|
||||
|
||||
rem Vivado (TM)
|
||||
rem runme.bat: a Vivado-generated Script
|
||||
rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
|
||||
|
||||
set HD_SDIR=%~dp0
|
||||
cd /d "%HD_SDIR%"
|
||||
set PATH=%SYSTEMROOT%\system32;%PATH%
|
||||
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
|
||||
+39
@@ -0,0 +1,39 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# runme.sh: a Vivado-generated Runs Script for UNIX
|
||||
# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
if [ -z "$PATH" ]; then
|
||||
PATH=/home/josh/Software/Xilinx/SDK/2019.1/bin:/home/josh/Software/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/home/josh/Software/Xilinx/Vivado/2019.1/bin
|
||||
else
|
||||
PATH=/home/josh/Software/Xilinx/SDK/2019.1/bin:/home/josh/Software/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/home/josh/Software/Xilinx/Vivado/2019.1/bin:$PATH
|
||||
fi
|
||||
export PATH
|
||||
|
||||
if [ -z "$LD_LIBRARY_PATH" ]; then
|
||||
LD_LIBRARY_PATH=
|
||||
else
|
||||
LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
|
||||
fi
|
||||
export LD_LIBRARY_PATH
|
||||
|
||||
HD_PWD='/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1'
|
||||
cd "$HD_PWD"
|
||||
|
||||
HD_LOG=runme.log
|
||||
/bin/touch $HD_LOG
|
||||
|
||||
ISEStep="./ISEWrap.sh"
|
||||
EAStep()
|
||||
{
|
||||
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
|
||||
if [ $? -ne 0 ]
|
||||
then
|
||||
exit
|
||||
fi
|
||||
}
|
||||
|
||||
EAStep vivado -log vio_phase_comp.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_phase_comp.tcl
|
||||
BIN
Binary file not shown.
+154
@@ -0,0 +1,154 @@
|
||||
#
|
||||
# Synthesis run script generated by Vivado
|
||||
#
|
||||
|
||||
set TIME_start [clock seconds]
|
||||
proc create_report { reportName command } {
|
||||
set status "."
|
||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
|
||||
set fp [open $status w]
|
||||
close $fp
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
set_param chipscope.maxJobs 5
|
||||
set_param project.vivado.isBlockSynthRun true
|
||||
set_msg_config -msgmgr_mode ooc_run
|
||||
create_project -in_memory -part xc7k410tffg900-2
|
||||
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
set_param project.compositeFile.enableAutoGeneration 0
|
||||
set_param synth.vivado.isSynthRun true
|
||||
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
|
||||
set_property webtalk.parent_dir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/wt [current_project]
|
||||
set_property parent.project_path /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.xpr [current_project]
|
||||
set_property XPM_LIBRARIES XPM_MEMORY [current_project]
|
||||
set_property default_lib xil_defaultlib [current_project]
|
||||
set_property target_language Verilog [current_project]
|
||||
set_property ip_output_repo /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
read_ip -quiet /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/rx_pre_process/vio_phase_comp/vio_phase_comp.xci
|
||||
set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/rx_pre_process/vio_phase_comp/vio_phase_comp.xdc]
|
||||
set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/rx_pre_process/vio_phase_comp/vio_phase_comp_ooc.xdc]
|
||||
|
||||
# Mark all dcp files as not used in implementation to prevent them from being
|
||||
# stitched into the results of this synthesis run. Any black boxes in the
|
||||
# design are intentionally left as such for best results. Dcp files will be
|
||||
# stitched into the design at a later time, either when this synthesis run is
|
||||
# opened, or when it is stitched into a dependent implementation run.
|
||||
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||
set_property used_in_implementation false $dcp
|
||||
}
|
||||
set_param ips.enableIPCacheLiteLoad 1
|
||||
|
||||
set cached_ip [config_ip_cache -export -no_bom -dir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1 -new_name vio_phase_comp -ip [get_ips vio_phase_comp]]
|
||||
|
||||
if { $cached_ip eq {} } {
|
||||
close [open __synthesis_is_running__ w]
|
||||
|
||||
synth_design -top vio_phase_comp -part xc7k410tffg900-2 -mode out_of_context
|
||||
|
||||
#---------------------------------------------------------
|
||||
# Generate Checkpoint/Stub/Simulation Files For IP Cache
|
||||
#---------------------------------------------------------
|
||||
# disable binary constraint mode for IPCache checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
|
||||
catch {
|
||||
write_checkpoint -force -noxdef -rename_prefix vio_phase_comp_ vio_phase_comp.dcp
|
||||
|
||||
set ipCachedFiles {}
|
||||
write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_phase_comp_stub.v
|
||||
lappend ipCachedFiles vio_phase_comp_stub.v
|
||||
|
||||
write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_phase_comp_stub.vhdl
|
||||
lappend ipCachedFiles vio_phase_comp_stub.vhdl
|
||||
|
||||
write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_phase_comp_sim_netlist.v
|
||||
lappend ipCachedFiles vio_phase_comp_sim_netlist.v
|
||||
|
||||
write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_phase_comp_sim_netlist.vhdl
|
||||
lappend ipCachedFiles vio_phase_comp_sim_netlist.vhdl
|
||||
set TIME_taken [expr [clock seconds] - $TIME_start]
|
||||
|
||||
config_ip_cache -add -dcp vio_phase_comp.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips vio_phase_comp]
|
||||
}
|
||||
|
||||
rename_ref -prefix_all vio_phase_comp_
|
||||
|
||||
# disable binary constraint mode for synth run checkpoints
|
||||
set_param constraints.enableBinaryConstraints false
|
||||
write_checkpoint -force -noxdef vio_phase_comp.dcp
|
||||
create_report "vio_phase_comp_synth_1_synth_report_utilization_0" "report_utilization -file vio_phase_comp_utilization_synth.rpt -pb vio_phase_comp_utilization_synth.pb"
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_verilog -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_sim_netlist.v
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
if { [catch {
|
||||
write_vhdl -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_sim_netlist.vhdl
|
||||
} _RESULT ] } {
|
||||
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||
}
|
||||
|
||||
|
||||
} else {
|
||||
|
||||
|
||||
}; # end if cached_ip
|
||||
|
||||
add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/rx_pre_process/vio_phase_comp/vio_phase_comp.xci]
|
||||
|
||||
add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/rx_pre_process/vio_phase_comp/vio_phase_comp.xci]
|
||||
|
||||
add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_sim_netlist.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/rx_pre_process/vio_phase_comp/vio_phase_comp.xci]
|
||||
|
||||
add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_sim_netlist.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/rx_pre_process/vio_phase_comp/vio_phase_comp.xci]
|
||||
|
||||
add_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.dcp -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/rx_pre_process/vio_phase_comp/vio_phase_comp.xci]
|
||||
|
||||
if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp]} {
|
||||
catch {
|
||||
file copy -force /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_sim_netlist.v /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp]} {
|
||||
catch {
|
||||
file copy -force /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_sim_netlist.vhdl /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp]} {
|
||||
catch {
|
||||
file copy -force /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.v /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp
|
||||
}
|
||||
}
|
||||
|
||||
if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp]} {
|
||||
catch {
|
||||
file copy -force /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp_stub.vhdl /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/ip_user_files/ip/vio_phase_comp
|
||||
}
|
||||
}
|
||||
file delete __synthesis_is_running__
|
||||
close [open __synthesis_is_complete__ w]
|
||||
+629
@@ -0,0 +1,629 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2019.1.3 (64-bit)
|
||||
# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019
|
||||
# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019
|
||||
# Start of session at: Mon Jun 12 15:47:26 2023
|
||||
# Process ID: 2733301
|
||||
# Current directory: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1
|
||||
# Command line: vivado -log vio_phase_comp.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_phase_comp.tcl
|
||||
# Log file: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.vds
|
||||
# Journal file: /home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vivado.jou
|
||||
#-----------------------------------------------------------
|
||||
source vio_phase_comp.tcl -notrace
|
||||
Command: synth_design -top vio_phase_comp -part xc7k410tffg900-2 -mode out_of_context
|
||||
Starting synth_design
|
||||
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t'
|
||||
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t'
|
||||
INFO: [Device 21-403] Loading part xc7k410tffg900-2
|
||||
INFO: Launching helper process for spawning children vivado processes
|
||||
INFO: Helper process launched with PID 2733353
|
||||
---------------------------------------------------------------------------------
|
||||
Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1829.879 ; gain = 149.688 ; free physical = 17235 ; free virtual = 44627
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Synth 8-6157] synthesizing module 'vio_phase_comp' [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/rx_pre_process/vio_phase_comp/synth/vio_phase_comp.v:59]
|
||||
WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_phase_comp does not have driver. [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/rx_pre_process/vio_phase_comp/synth/vio_phase_comp.v:94]
|
||||
INFO: [Synth 8-6155] done synthesizing module 'vio_phase_comp' (8#1) [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/rx_pre_process/vio_phase_comp/synth/vio_phase_comp.v:59]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Read
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[15]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[14]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[13]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[12]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[11]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[10]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[9]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[8]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[7]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[6]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[5]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Internal_cnt_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Read
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[15]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[14]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[13]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[12]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Internal_cnt_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Read
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[15]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[14]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[13]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[12]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[11]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[10]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[9]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[8]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[7]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[6]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[5]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[4]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[3]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[2]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[1]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Internal_cnt_rst
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in3[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in4[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in5[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in6[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in7[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in8[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in9[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in10[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in11[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in12[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in13[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in14[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in15[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in16[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in17[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in18[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in19[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in20[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in21[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in22[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in23[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in24[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in25[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in26[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in27[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in28[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in29[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in30[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in31[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in32[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in33[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in34[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in35[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in36[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in37[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in38[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in39[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in40[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in41[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in42[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in43[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in44[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in45[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in46[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in47[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in48[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in49[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in50[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in51[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in52[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in53[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in54[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in55[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in56[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in57[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in58[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in59[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in60[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in61[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in62[0]
|
||||
WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in63[0]
|
||||
INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1891.598 ; gain = 211.406 ; free physical = 17255 ; free virtual = 44648
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1894.566 ; gain = 214.375 ; free physical = 17256 ; free virtual = 44649
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1894.566 ; gain = 214.375 ; free physical = 17256 ; free virtual = 44649
|
||||
---------------------------------------------------------------------------------
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
|
||||
Processing XDC Constraints
|
||||
Initializing timing engine
|
||||
Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/rx_pre_process/vio_phase_comp/vio_phase_comp_ooc.xdc]
|
||||
Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/rx_pre_process/vio_phase_comp/vio_phase_comp_ooc.xdc]
|
||||
Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/rx_pre_process/vio_phase_comp/vio_phase_comp.xdc]
|
||||
Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/rx_pre_process/vio_phase_comp/vio_phase_comp.xdc]
|
||||
Completed Processing XDC Constraints
|
||||
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2078.223 ; gain = 0.000 ; free physical = 17127 ; free virtual = 44519
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2086.160 ; gain = 7.938 ; free physical = 17125 ; free virtual = 44517
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2086.160 ; gain = 405.969 ; free physical = 17226 ; free virtual = 44618
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Loading Part and Timing Information
|
||||
---------------------------------------------------------------------------------
|
||||
Loading part: xc7k410tffg900-2
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2086.160 ; gain = 405.969 ; free physical = 17226 ; free virtual = 44618
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying 'set_property' XDC Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2086.160 ; gain = 405.969 ; free physical = 17227 ; free virtual = 44620
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2086.160 ; gain = 405.969 ; free physical = 17218 ; free virtual = 44612
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
2 Input 4 Bit Adders := 1
|
||||
2 Input 3 Bit Adders := 1
|
||||
2 Input 1 Bit Adders := 1
|
||||
+---Registers :
|
||||
128 Bit Registers := 1
|
||||
34 Bit Registers := 5
|
||||
16 Bit Registers := 19
|
||||
12 Bit Registers := 9
|
||||
7 Bit Registers := 1
|
||||
5 Bit Registers := 2
|
||||
4 Bit Registers := 2
|
||||
3 Bit Registers := 3
|
||||
1 Bit Registers := 28
|
||||
+---Muxes :
|
||||
2 Input 16 Bit Muxes := 2
|
||||
6 Input 12 Bit Muxes := 1
|
||||
2 Input 1 Bit Muxes := 17
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
Hierarchical RTL Component report
|
||||
Module vio_v3_0_20_probe_in_one
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
2 Input 4 Bit Adders := 1
|
||||
+---Registers :
|
||||
34 Bit Registers := 5
|
||||
16 Bit Registers := 1
|
||||
4 Bit Registers := 1
|
||||
1 Bit Registers := 2
|
||||
Module vio_v3_0_20_probe_width
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
2 Input 1 Bit Adders := 1
|
||||
+---Registers :
|
||||
16 Bit Registers := 1
|
||||
1 Bit Registers := 1
|
||||
Module vio_v3_0_20_probe_out_one
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
16 Bit Registers := 1
|
||||
1 Bit Registers := 1
|
||||
+---Muxes :
|
||||
2 Input 1 Bit Muxes := 1
|
||||
Module vio_v3_0_20_probe_out_one__parameterized0
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
16 Bit Registers := 1
|
||||
12 Bit Registers := 1
|
||||
+---Muxes :
|
||||
2 Input 1 Bit Muxes := 1
|
||||
Module vio_v3_0_20_probe_out_one__parameterized1
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
16 Bit Registers := 1
|
||||
5 Bit Registers := 1
|
||||
+---Muxes :
|
||||
2 Input 1 Bit Muxes := 1
|
||||
Module vio_v3_0_20_probe_out_all
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
16 Bit Registers := 1
|
||||
4 Bit Registers := 1
|
||||
1 Bit Registers := 13
|
||||
+---Muxes :
|
||||
2 Input 1 Bit Muxes := 2
|
||||
Module vio_v3_0_20_probe_width__parameterized0
|
||||
Detailed RTL Component Info :
|
||||
+---Adders :
|
||||
2 Input 3 Bit Adders := 1
|
||||
+---Registers :
|
||||
12 Bit Registers := 1
|
||||
3 Bit Registers := 1
|
||||
+---Muxes :
|
||||
6 Input 12 Bit Muxes := 1
|
||||
Module xsdbs_v1_0_2_xsdbs
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
128 Bit Registers := 1
|
||||
16 Bit Registers := 2
|
||||
1 Bit Registers := 1
|
||||
+---Muxes :
|
||||
2 Input 16 Bit Muxes := 1
|
||||
2 Input 1 Bit Muxes := 1
|
||||
Module vio_v3_0_20_decoder
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
16 Bit Registers := 2
|
||||
7 Bit Registers := 1
|
||||
5 Bit Registers := 1
|
||||
3 Bit Registers := 2
|
||||
1 Bit Registers := 9
|
||||
+---Muxes :
|
||||
2 Input 16 Bit Muxes := 1
|
||||
2 Input 1 Bit Muxes := 3
|
||||
Module vio_v3_0_20_vio
|
||||
Detailed RTL Component Info :
|
||||
+---Registers :
|
||||
16 Bit Registers := 1
|
||||
---------------------------------------------------------------------------------
|
||||
Finished RTL Hierarchical Component Statistics
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
Part Resources:
|
||||
DSPs: 1540 (col length:140)
|
||||
BRAMs: 1590 (col length: RAMB18 140 RAMB36 70)
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Part Resource Summary
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Cross Boundary and Area Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
Warning: Parallel synthesis criteria is not met
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[2]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[2]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[4]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[5]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[5]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[6]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[6]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[6]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[8]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[8]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[8]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[9]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[9]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[9]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[10]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[10]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[10]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[11]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[11]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[11]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[12]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[12]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[12]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[13]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[13]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[13]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[13]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[13]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[13]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[13]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[13]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[13]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[13]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[13]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[14]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[14]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[14]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[14]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[14]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[14]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[14]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[14]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[14]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[14]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[14]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[15]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[15]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[15]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[15]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[15]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[15]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[15]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[15]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[15]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[15]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[15]'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[15] )
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[15] )
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[15] )
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[15] )
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[15] )
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[15] )
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[15] )
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[15] )
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[15] )
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[15] )
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[15] )
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/addr_p1_reg[0]' (FD) to 'inst/DECODER_INST/xsdb_addr_2_0_p1_reg[0]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/addr_p1_reg[1]' (FD) to 'inst/DECODER_INST/xsdb_addr_2_0_p1_reg[1]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/addr_p1_reg[2]' (FD) to 'inst/DECODER_INST/xsdb_addr_2_0_p1_reg[2]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[0]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[1]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[0]' (FDR) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[1]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[1]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[1]' (FDR) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[2]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[2]' (FDR) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[3]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[3]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[8]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[3]' (FDR) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[4]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[4]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[5]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[5]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[6]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[5]' (FDR) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[15]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[6]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[7]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[6]' (FDR) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[15]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[7]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[10]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[7]' (FDR) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[15]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[8]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[9]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[8]' (FDR) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[15]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[9]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[11]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[9]' (FDR) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[15]'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_WIDTH_INST/probe_width_int_reg[10] )
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[10]' (FDR) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[15]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[11]' (FDR) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[15]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[12]' (FDR) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[15]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[13]' (FDR) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[15]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[14]' (FDR) to 'inst/PROBE_IN_WIDTH_INST/probe_width_int_reg[15]'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_IN_WIDTH_INST/probe_width_int_reg[15] )
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[12]' (FD) to 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[10]' (FD) to 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[13]' (FD) to 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15]'
|
||||
INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[14]' (FD) to 'inst/PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15]'
|
||||
INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/Probe_out_reg_int_reg[15] )
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2086.160 ; gain = 405.969 ; free physical = 17208 ; free virtual = 44605
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Applying XDC Timing Constraints
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2086.160 ; gain = 405.969 ; free physical = 17094 ; free virtual = 44491
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Timing Optimization
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Timing Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2086.160 ; gain = 405.969 ; free physical = 17094 ; free virtual = 44491
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Technology Mapping
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2086.160 ; gain = 405.969 ; free physical = 17087 ; free virtual = 44484
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Flattening Before IO Insertion
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Final Netlist Cleanup
|
||||
---------------------------------------------------------------------------------
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[36] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[35] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[34] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[33] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[32] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[31] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[30] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[29] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[28] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[27] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[26] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[25] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[24] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[23] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[22] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[21] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[20] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[19] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[18] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[17] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[16] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[15] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[14] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[13] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[12] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[11] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[10] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[9] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[8] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[7] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[6] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[5] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[4] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[3] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[2] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[1] to constant 0
|
||||
WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0
|
||||
---------------------------------------------------------------------------------
|
||||
Finished IO Insertion : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2086.160 ; gain = 405.969 ; free physical = 17089 ; free virtual = 44486
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report Check Netlist:
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
| |Item |Errors |Warnings |Status |Description |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
|
||||
+------+------------------+-------+---------+-------+------------------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Instances
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Instances : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2086.160 ; gain = 405.969 ; free physical = 17089 ; free virtual = 44486
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report RTL Partitions:
|
||||
+-+--------------+------------+----------+
|
||||
| |RTL Partition |Replication |Instances |
|
||||
+-+--------------+------------+----------+
|
||||
+-+--------------+------------+----------+
|
||||
---------------------------------------------------------------------------------
|
||||
Start Rebuilding User Hierarchy
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2086.160 ; gain = 405.969 ; free physical = 17089 ; free virtual = 44486
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Ports
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Ports : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2086.160 ; gain = 405.969 ; free physical = 17089 ; free virtual = 44486
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Handling Custom Attributes
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2086.160 ; gain = 405.969 ; free physical = 17089 ; free virtual = 44486
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Renaming Generated Nets
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Renaming Generated Nets : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2086.160 ; gain = 405.969 ; free physical = 17089 ; free virtual = 44486
|
||||
---------------------------------------------------------------------------------
|
||||
---------------------------------------------------------------------------------
|
||||
Start Writing Synthesis Report
|
||||
---------------------------------------------------------------------------------
|
||||
|
||||
Report BlackBoxes:
|
||||
+-+--------------+----------+
|
||||
| |BlackBox name |Instances |
|
||||
+-+--------------+----------+
|
||||
+-+--------------+----------+
|
||||
|
||||
Report Cell Usage:
|
||||
+------+-----+------+
|
||||
| |Cell |Count |
|
||||
+------+-----+------+
|
||||
|1 |LUT1 | 3|
|
||||
|2 |LUT2 | 12|
|
||||
|3 |LUT3 | 29|
|
||||
|4 |LUT4 | 99|
|
||||
|5 |LUT5 | 35|
|
||||
|6 |LUT6 | 127|
|
||||
|7 |FDRE | 655|
|
||||
|8 |FDSE | 4|
|
||||
+------+-----+------+
|
||||
|
||||
Report Instance Areas:
|
||||
+------+----------------------------------------+--------------------------------------------+------+
|
||||
| |Instance |Module |Cells |
|
||||
+------+----------------------------------------+--------------------------------------------+------+
|
||||
|1 |top | | 964|
|
||||
|2 | inst |vio_v3_0_20_vio | 964|
|
||||
|3 | U_XSDB_SLAVE |xsdbs_v1_0_2_xsdbs | 248|
|
||||
|4 | DECODER_INST |vio_v3_0_20_decoder | 89|
|
||||
|5 | PROBE_IN_INST |vio_v3_0_20_probe_in_one | 302|
|
||||
|6 | PROBE_IN_WIDTH_INST |vio_v3_0_20_probe_width | 3|
|
||||
|7 | PROBE_OUT_ALL_INST |vio_v3_0_20_probe_out_all | 296|
|
||||
|8 | \G_PROBE_OUT[0].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one | 3|
|
||||
|9 | \G_PROBE_OUT[10].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1 | 10|
|
||||
|10 | \G_PROBE_OUT[1].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_0 | 3|
|
||||
|11 | \G_PROBE_OUT[2].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0 | 24|
|
||||
|12 | \G_PROBE_OUT[3].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0_1 | 24|
|
||||
|13 | \G_PROBE_OUT[4].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0_2 | 24|
|
||||
|14 | \G_PROBE_OUT[5].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0_3 | 24|
|
||||
|15 | \G_PROBE_OUT[6].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0_4 | 24|
|
||||
|16 | \G_PROBE_OUT[7].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0_5 | 24|
|
||||
|17 | \G_PROBE_OUT[8].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0_6 | 24|
|
||||
|18 | \G_PROBE_OUT[9].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0_7 | 24|
|
||||
|19 | PROBE_OUT_WIDTH_INST |vio_v3_0_20_probe_width__parameterized0 | 10|
|
||||
+------+----------------------------------------+--------------------------------------------+------+
|
||||
---------------------------------------------------------------------------------
|
||||
Finished Writing Synthesis Report : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2086.160 ; gain = 405.969 ; free physical = 17089 ; free virtual = 44486
|
||||
---------------------------------------------------------------------------------
|
||||
Synthesis finished with 0 errors, 0 critical warnings and 290 warnings.
|
||||
Synthesis Optimization Runtime : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2086.160 ; gain = 214.375 ; free physical = 17143 ; free virtual = 44540
|
||||
Synthesis Optimization Complete : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2086.160 ; gain = 405.969 ; free physical = 17157 ; free virtual = 44553
|
||||
INFO: [Project 1-571] Translating synthesized netlist
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2086.160 ; gain = 0.000 ; free physical = 17069 ; free virtual = 44466
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
INFO: [Common 17-83] Releasing license: Synthesis
|
||||
118 Infos, 138 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
synth_design completed successfully
|
||||
synth_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2086.160 ; gain = 687.246 ; free physical = 17163 ; free virtual = 44560
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2086.160 ; gain = 0.000 ; free physical = 17163 ; free virtual = 44560
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.dcp' has been generated.
|
||||
WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used.
|
||||
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_phase_comp, cache-ID = 199e9237e9cad44f
|
||||
INFO: [Coretcl 2-1174] Renamed 18 cell refs.
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2110.172 ; gain = 0.000 ; free physical = 17166 ; free virtual = 44564
|
||||
WARNING: [Constraints 18-5210] No constraints selected for write.
|
||||
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
|
||||
INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/dl814_k7_cal_coarse/ip/managed_ip_project/managed_ip_project.runs/vio_phase_comp_synth_1/vio_phase_comp.dcp' has been generated.
|
||||
INFO: [runtcl-4] Executing : report_utilization -file vio_phase_comp_utilization_synth.rpt -pb vio_phase_comp_utilization_synth.pb
|
||||
INFO: [Common 17-206] Exiting Vivado at Mon Jun 12 15:47:43 2023...
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user