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update phase comp with cmpy; add var cal module

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This commit is contained in:
josh
2023-06-12 17:35:52 +08:00
parent f7eb53ced7
commit d7cca991f1
220 changed files with 87094 additions and 1041 deletions
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projects/dl814_k7/dl814_k7_cal_coarse/rtl/rx_pre_process/phase_compensate.v
+196
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@@ -0,0 +1,196 @@
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2023/05/16 02:00:43
// Design Name:
// Module Name: phase_compensate
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module phase_compensate(
input clk ,
input rst ,
input [11:0] vio_sin_0 ,
input [11:0] vio_sin_1 ,
input [11:0] vio_sin_2 ,
input [11:0] vio_sin_3 ,
input [11:0] vio_cos_0 ,
input [11:0] vio_cos_1 ,
input [11:0] vio_cos_2 ,
input [11:0] vio_cos_3 ,
input [11:0] din_i_0 ,
input [11:0] din_i_1 ,
input [11:0] din_i_2 ,
input [11:0] din_i_3 ,
input [11:0] din_q_0 ,
input [11:0] din_q_1 ,
input [11:0] din_q_2 ,
input [11:0] din_q_3 ,
input [4:0] vio_trunc ,
output [11:0] dout_0_i ,
output [11:0] dout_1_i ,
output [11:0] dout_2_i ,
output [11:0] dout_3_i ,
output [11:0] dout_0_q ,
output [11:0] dout_1_q ,
output [11:0] dout_2_q ,
output [11:0] dout_3_q ,
output trunc_overflow
);
wire [63:0] dout_comp_0;
wire [63:0] dout_comp_1;
wire [63:0] dout_comp_2;
wire [63:0] dout_comp_3;
cmpy_12x12 cmpy_12x12_0 (
.aclk(clk), // input wire aclk
.s_axis_a_tvalid(1'd1), // input wire s_axis_a_tvalid
.s_axis_a_tdata({{4{vio_sin_0[11]}},vio_sin_0[11:0],{4{vio_cos_0[11]}},vio_cos_0[11:0]}), // input wire [31 : 0] s_axis_a_tdata
.s_axis_b_tvalid(1'd1), // input wire s_axis_b_tvalid
.s_axis_b_tdata({{4{din_q_0[11]}},din_q_0[11:0],{4{din_i_0[11]}},din_i_0[11:0]}), // input wire [31 : 0] s_axis_b_tdata
.m_axis_dout_tvalid(), // output wire m_axis_dout_tvalid
.m_axis_dout_tdata(dout_comp_0) // output wire [63 : 0] m_axis_dout_tdata
);
cmpy_12x12 cmpy_12x12_1 (
.aclk(clk), // input wire aclk
.s_axis_a_tvalid(1'd1), // input wire s_axis_a_tvalid
.s_axis_a_tdata({{4{vio_sin_1[11]}},vio_sin_1[11:0],{4{vio_cos_1[11]}},vio_cos_1[11:0]}), // input wire [31 : 0] s_axis_a_tdata
.s_axis_b_tvalid(1'd1), // input wire s_axis_b_tvalid
.s_axis_b_tdata({{4{din_q_1[11]}},din_q_1[11:0],{4{din_i_1[11]}},din_i_1[11:0]}), // input wire [31 : 0] s_axis_b_tdata
.m_axis_dout_tvalid(), // output wire m_axis_dout_tvalid
.m_axis_dout_tdata(dout_comp_1) // output wire [63 : 0] m_axis_dout_tdata
);
cmpy_12x12 cmpy_12x12_2 (
.aclk(clk), // input wire aclk
.s_axis_a_tvalid(1'd1), // input wire s_axis_a_tvalid
.s_axis_a_tdata({{4{vio_sin_2[11]}},vio_sin_2[11:0],{4{vio_cos_2[11]}},vio_cos_2[11:0]}), // input wire [31 : 0] s_axis_a_tdata
.s_axis_b_tvalid(1'd1), // input wire s_axis_b_tvalid
.s_axis_b_tdata({{4{din_q_2[11]}},din_q_2[11:0],{4{din_i_2[11]}},din_i_2[11:0]}), // input wire [31 : 0] s_axis_b_tdata
.m_axis_dout_tvalid(), // output wire m_axis_dout_tvalid
.m_axis_dout_tdata(dout_comp_2) // output wire [63 : 0] m_axis_dout_tdata
);
cmpy_12x12 cmpy_12x12_3 (
.aclk(clk), // input wire aclk
.s_axis_a_tvalid(1'd1), // input wire s_axis_a_tvalid
.s_axis_a_tdata({{4{vio_sin_3[11]}},vio_sin_3[11:0],{4{vio_cos_3[11]}},vio_cos_3[11:0]}), // input wire [31 : 0] s_axis_a_tdata
.s_axis_b_tvalid(1'd1), // input wire s_axis_b_tvalid
.s_axis_b_tdata({{4{din_q_3[11]}},din_q_3[11:0],{4{din_i_3[11]}},din_i_3[11:0]}), // input wire [31 : 0] s_axis_b_tdata
.m_axis_dout_tvalid(), // output wire m_axis_dout_tvalid
.m_axis_dout_tdata(dout_comp_3) // output wire [63 : 0] m_axis_dout_tdata
);
wire [11:0] dout_trunc_0i, dout_trunc_0q;
wire [11:0] dout_trunc_1i, dout_trunc_1q;
wire [11:0] dout_trunc_2i, dout_trunc_2q;
wire [11:0] dout_trunc_3i, dout_trunc_3q;
wire [11:0] trunc_overflow_0i, trunc_overflow_0q;
wire [11:0] trunc_overflow_1i, trunc_overflow_1q;
wire [11:0] trunc_overflow_2i, trunc_overflow_2q;
wire [11:0] trunc_overflow_3i, trunc_overflow_3q;
trunc_32bit_to_12bit trunc_32bit_to_12bit_0i(
.clk(clk),
.rst(rst),
.trunc_32bit_in({{7{dout_comp_0[24]}},dout_comp_0[24:0]}),
.vio_trunc(vio_trunc),
.trunc_12bit_out(dout_trunc_0i),
.trunc_overflow(trunc_overflow_0i)
);
trunc_32bit_to_12bit trunc_32bit_to_12bit_0q(
.clk(clk),
.rst(rst),
.trunc_32bit_in({{7{dout_comp_0[56]}},dout_comp_0[56:32]}),
.vio_trunc(vio_trunc),
.trunc_12bit_out(dout_trunc_0q),
.trunc_overflow(trunc_overflow_0q)
);
trunc_32bit_to_12bit trunc_32bit_to_12bit_1i(
.clk(clk),
.rst(rst),
.trunc_32bit_in({{7{dout_comp_1[24]}},dout_comp_1[24:0]}),
.vio_trunc(vio_trunc),
.trunc_12bit_out(dout_trunc_1i),
.trunc_overflow(trunc_overflow_1i)
);
trunc_32bit_to_12bit trunc_32bit_to_12bit_1q(
.clk(clk),
.rst(rst),
.trunc_32bit_in({{7{dout_comp_1[56]}},dout_comp_1[56:32]}),
.vio_trunc(vio_trunc),
.trunc_12bit_out(dout_trunc_1q),
.trunc_overflow(trunc_overflow_1q)
);
trunc_32bit_to_12bit trunc_32bit_to_12bit_2i(
.clk(clk),
.rst(rst),
.trunc_32bit_in({{7{dout_comp_2[24]}},dout_comp_2[24:0]}),
.vio_trunc(vio_trunc),
.trunc_12bit_out(dout_trunc_2i),
.trunc_overflow(trunc_overflow_2i)
);
trunc_32bit_to_12bit trunc_32bit_to_12bit_2q(
.clk(clk),
.rst(rst),
.trunc_32bit_in({{7{dout_comp_2[56]}},dout_comp_2[56:32]}),
.vio_trunc(vio_trunc),
.trunc_12bit_out(dout_trunc_2q),
.trunc_overflow(trunc_overflow_2q)
);
trunc_32bit_to_12bit trunc_32bit_to_12bit_3i(
.clk(clk),
.rst(rst),
.trunc_32bit_in({{7{dout_comp_3[24]}},dout_comp_3[24:0]}),
.vio_trunc(vio_trunc),
.trunc_12bit_out(dout_trunc_3i),
.trunc_overflow(trunc_overflow_3i)
);
trunc_32bit_to_12bit trunc_32bit_to_12bit_3q(
.clk(clk),
.rst(rst),
.trunc_32bit_in({{7{dout_comp_3[56]}},dout_comp_3[56:32]}),
.vio_trunc(vio_trunc),
.trunc_12bit_out(dout_trunc_3q),
.trunc_overflow(trunc_overflow_3q)
);
assign dout_0_i = dout_trunc_0i;
assign dout_1_i = dout_trunc_1i;
assign dout_2_i = dout_trunc_2i;
assign dout_3_i = dout_trunc_3i;
assign dout_0_q = dout_trunc_0q;
assign dout_1_q = dout_trunc_1q;
assign dout_2_q = dout_trunc_2q;
assign dout_3_q = dout_trunc_3q;
assign trunc_overflow = trunc_overflow_3q || trunc_overflow_2q || trunc_overflow_1q || trunc_overflow_0q || trunc_overflow_3i || trunc_overflow_2i || trunc_overflow_1i || trunc_overflow_0i;
endmodule
projects/dl814_k7/dl814_k7_cal_coarse/rtl/rx_pre_process/rx_pre_process.v
+88 -27
View File
@@ -153,41 +153,102 @@ ad9361_phase_cal_coarse u_ad9361_phase_cal
////////////////////////////// Phase Compensation //////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// input data
wire phase_comp_din_valid;
wire [CHANNEL_NUM*PHASE_WIDTH-1 : 0] phase_comp_phase;
wire [CHANNEL_NUM*ADC_DATA_WIDTH-1 : 0] phase_comp_din_real;
wire [CHANNEL_NUM*ADC_DATA_WIDTH-1 : 0] phase_comp_din_imag;
// wire phase_comp_din_valid;
// wire [CHANNEL_NUM*PHASE_WIDTH-1 : 0] phase_comp_phase;
// wire [CHANNEL_NUM*ADC_DATA_WIDTH-1 : 0] phase_comp_din_real;
// wire [CHANNEL_NUM*ADC_DATA_WIDTH-1 : 0] phase_comp_din_imag;
assign phase_comp_din_valid = ad9361_cal_valid;
assign phase_comp_phase = {phase_ch4, phase_ch3, phase_ch2, phase_ch1};
assign phase_comp_din_real = {rx_cal_ch4_i, rx_cal_ch3_i, rx_cal_ch2_i, rx_cal_ch1_i};
assign phase_comp_din_imag = {rx_cal_ch4_q, rx_cal_ch3_q, rx_cal_ch2_q, rx_cal_ch1_q};
// assign phase_comp_din_valid = ad9361_cal_valid;
// assign phase_comp_phase = {phase_ch4, phase_ch3, phase_ch2, phase_ch1};
// assign phase_comp_din_real = {rx_cal_ch4_i, rx_cal_ch3_i, rx_cal_ch2_i, rx_cal_ch1_i};
// assign phase_comp_din_imag = {rx_cal_ch4_q, rx_cal_ch3_q, rx_cal_ch2_q, rx_cal_ch1_q};
// output data
wire phase_comp_dout_valid;
wire [CHANNEL_NUM*ADC_DATA_WIDTH-1:0] phase_comp_dout_real;
wire [CHANNEL_NUM*ADC_DATA_WIDTH-1:0] phase_comp_dout_imag;
phase_comp #(
.DATA_WIDTH (ADC_DATA_WIDTH ),
.CORDIC_WIDTH (PHASE_WIDTH ),
.CHANNEL_NUM (CHANNEL_NUM )
) u_phase_comp
// phase_comp #(
// .DATA_WIDTH (ADC_DATA_WIDTH ),
// .CORDIC_WIDTH (PHASE_WIDTH ),
// .CHANNEL_NUM (CHANNEL_NUM )
// ) u_phase_comp
// (
// // clock & reset
// .clk (sys_clk ),
// .rst (sys_rst ),
// // input data
// .din_valid (phase_comp_din_valid ),
// .phase (phase_comp_phase ),
// .din_real (phase_comp_din_real ),
// .din_imag (phase_comp_din_imag ),
// // output data
// .dout_valid (phase_comp_dout_valid ),
// .dout_real (phase_comp_dout_real ),
// .dout_imag (phase_comp_dout_imag )
// );
(*dont_touch = "true"*) wire [11:0] vio_sin_0;
(*dont_touch = "true"*) wire [11:0] vio_sin_1;
(*dont_touch = "true"*) wire [11:0] vio_sin_2;
(*dont_touch = "true"*) wire [11:0] vio_sin_3;
(*dont_touch = "true"*) wire [11:0] vio_cos_0;
(*dont_touch = "true"*) wire [11:0] vio_cos_1;
(*dont_touch = "true"*) wire [11:0] vio_cos_2;
(*dont_touch = "true"*) wire [11:0] vio_cos_3;
(*dont_touch = "true"*) wire [ 4:0] vio_trunc;
(*dont_touch = "true"*) wire trunc_overflow;
(*dont_touch = "true"*) wire [11:0] rx_comp_ch1_i;
(*dont_touch = "true"*) wire [11:0] rx_comp_ch1_q;
(*dont_touch = "true"*) wire [11:0] rx_comp_ch2_i;
(*dont_touch = "true"*) wire [11:0] rx_comp_ch2_q;
(*dont_touch = "true"*) wire [11:0] rx_comp_ch3_i;
(*dont_touch = "true"*) wire [11:0] rx_comp_ch3_q;
(*dont_touch = "true"*) wire [11:0] rx_comp_ch4_i;
(*dont_touch = "true"*) wire [11:0] rx_comp_ch4_q;
assign phase_comp_dout_valid = ad9361_cal_valid;
assign phase_comp_dout_real = {rx_comp_ch4_i, rx_comp_ch3_i, rx_comp_ch2_i, rx_comp_ch1_i};
assign phase_comp_dout_imag = {rx_comp_ch4_q, rx_comp_ch3_q, rx_comp_ch2_q, rx_comp_ch1_q};
phase_compensate u_phase_compensate
(
// clock & reset
.clk (sys_clk ),
.rst (sys_rst ),
.clk (sys_clk ),
.rst (sys_rst ),
// input data
.din_valid (phase_comp_din_valid ),
.phase (phase_comp_phase ),
.din_real (phase_comp_din_real ),
.din_imag (phase_comp_din_imag ),
.vio_sin_0 (vio_sin_0 ),
.vio_sin_1 (vio_sin_1 ),
.vio_sin_2 (vio_sin_2 ),
.vio_sin_3 (vio_sin_3 ),
.vio_cos_0 (vio_cos_0 ),
.vio_cos_1 (vio_cos_1 ),
.vio_cos_2 (vio_cos_2 ),
.vio_cos_3 (vio_cos_3 ),
// output data
.dout_valid (phase_comp_dout_valid ),
.dout_real (phase_comp_dout_real ),
.dout_imag (phase_comp_dout_imag )
.din_i_0 (rx_cal_ch1_i ),
.din_i_1 (rx_cal_ch2_i ),
.din_i_2 (rx_cal_ch3_i ),
.din_i_3 (rx_cal_ch4_i ),
.din_q_0 (rx_cal_ch1_q ),
.din_q_1 (rx_cal_ch2_q ),
.din_q_2 (rx_cal_ch3_q ),
.din_q_3 (rx_cal_ch4_q ),
.vio_trunc (vio_trunc ),
.dout_0_i (rx_comp_ch1_i ),
.dout_1_i (rx_comp_ch2_i ),
.dout_2_i (rx_comp_ch3_i ),
.dout_3_i (rx_comp_ch4_i ),
.dout_0_q (rx_comp_ch1_q ),
.dout_1_q (rx_comp_ch2_q ),
.dout_2_q (rx_comp_ch3_q ),
.dout_3_q (rx_comp_ch4_q ),
.trunc_overflow (trunc_overflow )
);
////////////////////////////////////////////////////////////////////////////////
@@ -304,8 +365,8 @@ wire [CHANNEL_NUM*ADC_DATA_WIDTH-1 : 0] acorr_din_real;
wire [CHANNEL_NUM*ADC_DATA_WIDTH-1 : 0] acorr_din_imag;
assign acorr_din_valid = snapshot_valid;
assign acorr_din_real = phase_comp_din_real;
assign acorr_din_imag = phase_comp_din_imag;
assign acorr_din_real = phase_comp_dout_real;
assign acorr_din_imag = phase_comp_dout_imag;
// output data
wire acorr_dout_valid;
projects/dl814_k7/dl814_k7_cal_coarse/rtl/system_top.v
+51 -31
View File
@@ -730,21 +730,6 @@ rx_pre_process #(
.rx_data_q (rx_data_q ) // sync to [sys_clk]
);
(*dont_touch = "true"*) wire [11:0] rx_rot_ch1_i, rx_rot_ch1_q;
(*dont_touch = "true"*) wire [11:0] rx_rot_ch2_i, rx_rot_ch2_q;
(*dont_touch = "true"*) wire [11:0] rx_rot_ch3_i, rx_rot_ch3_q;
(*dont_touch = "true"*) wire [11:0] rx_rot_ch4_i, rx_rot_ch4_q;
assign rx_rot_ch1_i = u_rx_pre_process.phase_comp_dout_real[11: 0];
assign rx_rot_ch2_i = u_rx_pre_process.phase_comp_dout_real[23:12];
assign rx_rot_ch3_i = u_rx_pre_process.phase_comp_dout_real[35:24];
assign rx_rot_ch4_i = u_rx_pre_process.phase_comp_dout_real[47:36];
assign rx_rot_ch1_q = u_rx_pre_process.phase_comp_dout_imag[11: 0];
assign rx_rot_ch2_q = u_rx_pre_process.phase_comp_dout_imag[23:12];
assign rx_rot_ch3_q = u_rx_pre_process.phase_comp_dout_imag[35:24];
assign rx_rot_ch4_q = u_rx_pre_process.phase_comp_dout_imag[47:36];
// temporary test cases
rx_pre_test u_rx_pre_test
(
@@ -772,7 +757,32 @@ rx_pre_test u_rx_pre_test
// <--------------------------------------------------------------------------->
// <----------------------- insert receiver logic below ----------------------->
// <--------------------------------------------------------------------------->
wire var_cal_start;
wire cal_auto_en;
wire var_cal_busy;
wire var_valid;
wire [31:0] var;
var_cal #(
.ACCUM_NUM (16384 ),
.DATA_I_WIDTH (30 ),
.DATA_O_WIDTH (32 )
) u_var_cal
(
.clk (sys_clk ),
.rst (sys_rst ),
.cal_start (var_cal_start ),
.cal_auto_en(cal_auto_en ),
.cal_busy (var_cal_busy ),
.din_valid (rx_data_valid ),
.din_real (rx_data_i ),
.din_imag (rx_data_q ),
.var_valid (var_valid ),
.var (var )
);
////////////////////////////////////////////////////////////////////////////////
//////////////////////////////// ILAs and VIOs /////////////////////////////////
@@ -917,17 +927,17 @@ ila_2x12x1024 u_ila_tx
ila_8x12_2x30_131072 u_ila_rx
(
.clk (sys_clk ), // input wire clk
.probe0 (rx_rot_ch1_i ), // input wire [11:0] probe0
.probe1 (rx_rot_ch1_q ), // input wire [11:0] probe1
.probe2 (rx_rot_ch2_i ), // input wire [11:0] probe2
.probe3 (rx_rot_ch2_q ), // input wire [11:0] probe3
.probe4 (rx_rot_ch3_i ), // input wire [11:0] probe4
.probe5 (rx_rot_ch3_q ), // input wire [11:0] probe5
.probe6 (rx_rot_ch4_i ), // input wire [11:0] probe6
.probe7 (rx_rot_ch4_q ), // input wire [11:0] probe7
.probe8 (rx_data_i ), // input wire [29:0] probe8
.probe9 (rx_data_q ) // input wire [29:0] probe9
.clk (sys_clk ), // input wire clk
.probe0 (u_rx_pre_process.rx_comp_ch1_i ), // input wire [11:0] probe0
.probe1 (u_rx_pre_process.rx_comp_ch1_q ), // input wire [11:0] probe1
.probe2 (u_rx_pre_process.rx_comp_ch2_i ), // input wire [11:0] probe2
.probe3 (u_rx_pre_process.rx_comp_ch2_q ), // input wire [11:0] probe3
.probe4 (u_rx_pre_process.rx_comp_ch3_i ), // input wire [11:0] probe4
.probe5 (u_rx_pre_process.rx_comp_ch3_q ), // input wire [11:0] probe5
.probe6 (u_rx_pre_process.rx_comp_ch4_i ), // input wire [11:0] probe6
.probe7 (u_rx_pre_process.rx_comp_ch4_q ), // input wire [11:0] probe7
.probe8 (rx_data_i ), // input wire [29:0] probe8
.probe9 (rx_data_q ) // input wire [29:0] probe9
);
ila_cal u_ila_cal
@@ -1001,11 +1011,21 @@ vio_hop u_vio_hop
vio_phase_comp u_vio_phase_comp
(
.clk (sys_clk ), // input wire clk
.probe_out0 (phase_ch1 ), // output wire [15 : 0] probe_out0
.probe_out1 (phase_ch2 ), // output wire [15 : 0] probe_out1
.probe_out2 (phase_ch3 ), // output wire [15 : 0] probe_out2
.probe_out3 (phase_ch4 ) // output wire [15 : 0] probe_out3
.clk (sys_clk ), // input wire clk
.probe_in0 (var ), // output wire [31 : 0] probe_in0
.probe_in1 (var_cal_busy ), // output wire [0 : 0] probe_in1
.probe_in2 (u_rx_pre_process.trunc_overflow), // output wire [0 : 0] probe_in1
.probe_out0 (var_cal_start ), // output wire [0 : 0] probe_out0
.probe_out1 (cal_auto_en ), // output wire [0 : 0] probe_out1
.probe_out2 (u_rx_pre_process.vio_sin_0 ), // output wire [11 : 0] probe_out2
.probe_out3 (u_rx_pre_process.vio_sin_1 ), // output wire [11 : 0] probe_out3
.probe_out4 (u_rx_pre_process.vio_sin_2 ), // output wire [11 : 0] probe_out4
.probe_out5 (u_rx_pre_process.vio_sin_3 ), // output wire [11 : 0] probe_out5
.probe_out6 (u_rx_pre_process.vio_cos_0 ), // output wire [11 : 0] probe_out6
.probe_out7 (u_rx_pre_process.vio_cos_1 ), // output wire [11 : 0] probe_out7
.probe_out8 (u_rx_pre_process.vio_cos_2 ), // output wire [11 : 0] probe_out8
.probe_out9 (u_rx_pre_process.vio_cos_3 ), // output wire [11 : 0] probe_out9
.probe_out10(u_rx_pre_process.vio_trunc ) // output wire [4 : 0] probe_out10
);
endmodule