add simulation files
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version https://git-lfs.github.com/spec/v1
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oid sha256:608698bb466222716a943421803cceb8633aab062e2e0e22f371400e3366d24a
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size 743640
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+3
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version https://git-lfs.github.com/spec/v1
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oid sha256:ca7f4f48ab8b2d4f82ad8f3beb225bd6cf5102221db57e7318ff96f6754d9d8e
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size 743640
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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// _ _ ____
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// | | ___ ___| |__ / ___| __ _ ___
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// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
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// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
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// \___/ \___/|___/_| |_| \____|\__,_|\___/
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//
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// Create Date: 2022/10/30 20:46:26
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// Last Simulate Data: 2023/07/17 15:51
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// Design Name:
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// Module Name: tb_accum
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description: Testbench for [accum_cmplx_mat]
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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// -------------------------------
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// MATLAB Code for data generation
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// -------------------------------
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// COLUMN_NUM = 4;
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// DATA_I_WIDTH = 12;
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// ACC_NUM = 10;
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// rng(0);
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// data = rand(4,2)*2-1;
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// d_12b = round(data.*(2^(DATA_I_WIDTH-1)-1));
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// d_12b_cmplx = d_12b(:,1) + 1i*d_12b(:,2);
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// d_12b_cmplx = d_12b_cmplx(end:-1:1,:);
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// d_12b_acorr = d_12b_cmplx*d_12b_cmplx';
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// d_12b_acorr_real_sim = reshape(flip(reshape(real(d_12b_acorr)',1,16)),4,4);
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// d_12b_acorr_imag_sim = reshape(flip(reshape(imag(d_12b_acorr)',1,16)),4,4);
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// d_12b_acorr_real_sim_sum = ACC_NUM*d_12b_acorr_real_sim;
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// d_12b_acorr_imag_sim_sum = ACC_NUM*d_12b_acorr_imag_sim;
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module tb_accum;
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localparam DATA_I_WIDTH = 24;
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localparam DATA_O_WIDTH = 32;
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localparam ROW_NUM = 4;
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localparam COL_NUM = 4;
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localparam ACC_NUM = 2048;
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reg acc_rst = 1'b0;
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reg clk = 1'b1;
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reg rst = 1'b1;
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reg din_valid = 'b0;
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// reg [ROW_NUM*COL_NUM*DATA_I_WIDTH-1:0] din_real = {
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// 24'd1952708, 24'd1246152, -24'd2458370, 24'd2283360,
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// 24'd1246152, 24'd5474825, -24'd1041611, 24'd2493996,
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// -24'd2458370, -24'd1041611, 24'd3154378, -24'd2757828,
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// 24'd2283360, 24'd2493996, -24'd2757828, 24'd2899728
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// };
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// reg [ROW_NUM*COL_NUM*DATA_I_WIDTH-1:0] din_real = {
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// 24'd0, -24'd3022886, -24'd340582, -24'd669768,
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// 24'd3022886, 24'd0, -24'd4023023, 24'd3107328,
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// 24'd340582, 24'd4023023, 24'd0, 24'd1241460,
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// 24'd669768, -24'd3107328, -24'd1241460, 24'd0
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// };
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reg [ROW_NUM*COL_NUM*DATA_I_WIDTH-1:0] din_real = {
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24'd1952708, 24'd1246152, -24'd2458370, 24'd2283360,
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24'd1246152, 24'd5474825, -24'd1041611, 24'd2493996,
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-24'd2458370, -24'd1041611, 24'd3154378, 24'h7F_FFFF,
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24'd2283360, 24'd2493996, -24'd2757828, 24'h80_0000
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};
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reg [ROW_NUM*COL_NUM*DATA_I_WIDTH-1:0] din_imag = {
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24'd0, -24'd3022886, -24'd340582, -24'd669768,
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24'd3022886, 24'd0, -24'd4023023, 24'd3107328,
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24'd340582, 24'd4023023, 24'd0, 24'd1241460,
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24'd669768, -24'd3107328, -24'd1241460, 24'd0
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};
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wire dout_valid;
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wire [ROW_NUM*COL_NUM*DATA_O_WIDTH-1:0] dout_real, dout_imag;
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accum_cmplx_mat #(
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.ROW_NUM (ROW_NUM),
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.COL_NUM (COL_NUM),
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.DATA_I_WIDTH (DATA_I_WIDTH),
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.DATA_O_WIDTH (DATA_O_WIDTH),
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.ACC_NUM (ACC_NUM)
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) u_accum_cmplx_mat
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(
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// clock & reset
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.clk (clk ),
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.rst (rst ),
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.acc_rst (acc_rst ), // [acc_rst] should assert before accumulation starts
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// input data
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.din_valid (din_valid ),
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.din_real (din_real ),
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.din_imag (din_imag ),
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// output data
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.dout_valid (dout_valid ),
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.dout_real (dout_real ),
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.dout_imag (dout_imag )
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);
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initial begin
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#102
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rst = 1'b0;
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// reset
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#222
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acc_rst = 1'b1;
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#20
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acc_rst = 1'b0;
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// input data valid lasts [ACC_NUM] clock cycles
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#222
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@(posedge clk)
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#1
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din_valid = 1'b1;
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#(20*ACC_NUM)
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din_valid = 1'b0;
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// reset
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#222
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acc_rst = 1'b1;
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#20
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acc_rst = 1'b0;
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// input data valid lasts [ACC_NUM] clock cycles
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#222
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@(posedge clk)
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#1
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din_valid = 1'b1;
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#(20*ACC_NUM)
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din_valid = 1'b0;
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#222
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$stop;
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end
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always #10 clk = ~clk;
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endmodule
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+105
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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// _ _ ____
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// | | ___ ___| |__ / ___| __ _ ___
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||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
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||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
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||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
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//
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// Create Date: 2022/10/30 20:46:26
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// Design Name:
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// Module Name: acorr_tb
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description: Testbench for [acorr_cmplx_col_vec]
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module tb_acorr;
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localparam ROW_NUM = 1;
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localparam COL_NUM = 4;
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localparam DATA_I_WIDTH = 12;
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localparam DATA_O_WIDTH = 23;
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reg acc_rst = 1'b0;
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reg clk = 1'b1;
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reg rst = 1'b1;
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reg din_valid = 'b0;
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reg [COL_NUM*DATA_I_WIDTH-1:0] din_real = 'b0, din_imag = 'b0;
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wire dout_valid;
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wire [COL_NUM*COL_NUM*DATA_O_WIDTH-1:0] dout_real, dout_imag;
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acorr_cmplx_col_vec #(
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.COL_NUM (COL_NUM),
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.DATA_I_WIDTH (DATA_I_WIDTH),
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.DATA_O_WIDTH (DATA_O_WIDTH)
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) u_acorr_cmplx_col_vec
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(
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// clock & reset
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.clk (clk ),
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.rst (rst ),
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// input data
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.din_valid (din_valid ),
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.din_real (din_real ),
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.din_imag (din_imag ),
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// output data
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.dout_valid (dout_valid ),
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.dout_real (dout_real ),
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.dout_imag (dout_imag )
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);
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initial begin
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#102 rst = 1'b0;
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#222;
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@(posedge clk)
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din_valid = 1'b1;
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din_real = {
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12'd1351,
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-12'd1219,
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12'd1326,
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12'd1029};
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din_imag = {
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12'd1538,
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-12'd1119,
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12'd1519,
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12'd1495};
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@(posedge clk)
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din_valid = 1'b0;
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@(posedge clk)
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din_valid = 1'b1;
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din_real = {
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12'd153 ,
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-12'd724 ,
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-12'd1315,
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12'd433 };
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din_imag = {
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-12'd1170,
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12'd981 ,
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-12'd48 ,
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12'd1494};
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end
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always #10 clk = ~clk;
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endmodule
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+80
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 07/18/2023 11:22:10 AM
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// Design Name:
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// Module Name: tb_null_ctrl
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module tb_null_ctrl;
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localparam HOP_CNT_192 = 192*200;
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reg clk = 1'b1;
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reg clk_2x = 1'b1;
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reg clk_4x = 1'b1;
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reg rst = 1'b1;
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reg hop_flag_in = 1'b0;
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reg sync_flag_phy = 1'b0;
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reg sync_null_en_phy = 1'b1;
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wire hop_flag_out_phy;
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null_ctrl u_null_ctrl
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(
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.clk (clk ),
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.clk_phy (clk_4x ),
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.rst (rst ),
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.hop_flag_in_phy (hop_flag_in ),
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.sync_flag_phy (sync_flag_phy ),
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.sync_null_en_phy (sync_null_en_phy ),
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.hop_flag_out_phy (hop_flag_out_phy ),
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.adc_din_valid (1'b1 )
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);
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// clock & reset
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initial begin
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#102
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rst = 1'b0;
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end
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always #5 clk_4x = ~clk_4x;
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always @(posedge clk_4x) begin
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clk_2x = ~clk_2x;
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end
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always @(posedge clk_2x) begin
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clk = ~clk;
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end
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// hop control
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reg [$clog2(HOP_CNT_192)-1 : 0] hop_cnt = 'b0;
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always @(posedge clk_4x) begin
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if (rst) begin
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hop_cnt <= 'b0;
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hop_flag_in <= 'b0;
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end
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else begin
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hop_cnt <= (hop_cnt == HOP_CNT_192-1) ? 'b0 : hop_cnt + 1'b1;
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hop_flag_in <= (hop_cnt == 120) ? 1'b1 : 'b0;
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end
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end
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endmodule
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+110
@@ -0,0 +1,110 @@
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%%%%%%%%%%%%%%%%%%%%%%%%%%
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%本仿真基于以下环境，64元矩形方阵，每若干个阵元通过TR通道和合路器，合成一路子阵信号，然后AD采样进入阵列信号处理单元；
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% - 子阵分割均匀，（16，16，16，16），共有4个子阵
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% - 1个已知方向的期望来波，3个未知方向的干扰信号；
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% - 信干比60dB；
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%θ表示俯仰角（来波与Z轴正向夹角）；φ表示方位角（来波在XOY平面投影与X轴正向夹角）；X轴与阵列每列平行，Y轴与阵列每行平行
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%通过空域滤波得到抑制干扰后的信号
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%%%%%%%%%%%%%%%%%%%%%%%%
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clc;
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clear all;
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Tt=256;%快拍数，用于阵列信号处理的采样点数
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Tmax = 32768;
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t=1:Tmax;
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%%%%%%%%%此处假设来波均为单频信号，可按自身定义修改
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f1=0.1*pi;
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f2=0.2*pi;
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f3=0.3*pi;
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f4=0.4*pi;
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%% 通信基带信号
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%% 窄带白噪声干扰信号
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filter_name = 'lpf_fs100_fpass5_fstop6.mat';
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%%
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snr=0;%信噪比可根据应用场景确定
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sjr=(60+snr);%干信比
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s1=sqrt(2*10^(snr/10))*exp(1i*f1*t);
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s2=sqrt(2*10^(sjr/10))*exp(1i*f2*t);
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s3=sqrt(2*10^(sjr/10))*exp(1i*f3*t);
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s4=sqrt(2*10^(sjr/10))*exp(1i*f4*t);
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%%%%%%%由信噪比和干信比计算出信号的幅度
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lamuda=1;%当前载频的波长，可根据载频输入实际值d
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d=0.5;%阵元间距，需小于最高工作频率半波长，可根据实际情况输入实际值
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theta1=20;%期望来波俯仰角
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phi1=30;%期望来波方位角
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theta2=-20;%干扰1俯仰角
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phi2=50;%干扰1方位角
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theta3=-40;%干扰2俯仰角
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phi3=80;%干扰2方位角
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theta4=-60;%干扰3俯仰角
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phi4=120;%干扰3方位角
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%%%%%%%%
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m=8;%列
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n=8;%行
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L=m*n;
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a1=exp(1i*2*pi*d/lamuda*(-(m/2-1/2):1:(m/2-1/2)).'*sin(theta1/180*pi)*sin(phi1/180*pi));
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b1=exp(1i*2*pi*d/lamuda*(-(n/2-1/2):1:(n/2-1/2)).'*sin(theta1/180*pi)*cos(phi1/180*pi));
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A1=kron(b1,a1);
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a2=exp(1i*2*pi*d/lamuda*(-(m/2-1/2):1:(m/2-1/2)).'*sin(theta2/180*pi)*sin(phi2/180*pi));
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b2=exp(1i*2*pi*d/lamuda*(-(n/2-1/2):1:(n/2-1/2)).'*sin(theta2/180*pi)*cos(phi2/180*pi));
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A2=kron(b2,a2);
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a3=exp(1i*2*pi*d/lamuda*(-(m/2-1/2):1:(m/2-1/2)).'*sin(theta3/180*pi)*sin(phi3/180*pi));
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b3=exp(1i*2*pi*d/lamuda*(-(n/2-1/2):1:(n/2-1/2)).'*sin(theta3/180*pi)*cos(phi3/180*pi));
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A3=kron(b3,a3);
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a4=exp(1i*2*pi*d/lamuda*(-(m/2-1/2):1:(m/2-1/2)).'*sin(theta4/180*pi)*sin(phi4/180*pi));
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b4=exp(1i*2*pi*d/lamuda*(-(n/2-1/2):1:(n/2-1/2)).'*sin(theta4/180*pi)*cos(phi4/180*pi));
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A4=kron(b4,a4);
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As=[A1,A2,A3,A4];%阵列流型
|
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rng(0);
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x=As*[s1;s2;s3;s4]+randn(L,Tmax);
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||||
%%%%%%%%%%%%%%%4元子阵
|
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%
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||||
N1=4;
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C1=zeros(N1,64);
|
||||
D1=zeros(N1,64);
|
||||
for kk=0:3
|
||||
C1(1,(kk*8+1):(kk*8+4))=ones(1,4);
|
||||
C1(2,(kk*8+5):(kk*8+8))=ones(1,4);
|
||||
C1(3,(kk*8+33):(kk*8+36))=ones(1,4);
|
||||
C1(4,(kk*8+37):(kk*8+40))=ones(1,4);
|
||||
end
|
||||
%}
|
||||
%%%%%%%%%%%%%%%%%%%%%%
|
||||
D1=C1*diag(A1');%4元 阵元通道移相后，每16路合路为一个子阵
|
||||
% D2=C2*diag(A1');%6元 阵元通道移相后，每(16,8)路合路为一个子阵
|
||||
% D3=C3*diag(A1');%8元 阵元通道移相后，每8路合路为一个子阵
|
||||
% %%%%%%%%%%%%%%%%%
|
||||
xs1=D1*x(:,1:Tt);
|
||||
Rx1=xs1*xs1';%4元子阵协方差矩阵
|
||||
Ax1=D1*A1;%期望来波方向的子阵导向矢量
|
||||
wx1=inv(Rx1)*Ax1/(Ax1'*inv(Rx1)*Ax1);%4子阵的LCMV权值
|
||||
|
||||
xs1_long = D1*x;
|
||||
s_new1=wx1'*xs1_long;%4子阵情况下的空域滤波后的信号
|
||||
% s_new1=[1,1,1,1]*xs1;
|
||||
|
||||
%% 数据导出
|
||||
xs1_long_12b = round(xs1_long/max(max(abs(xs1_long)))*(2^11-1));
|
||||
xs1_real_12b = real(xs1_long_12b);
|
||||
xs1_imag_12b = imag(xs1_long_12b);
|
||||
|
||||
% writematrix(xs1_real_12b,'./xs1_real.csv');
|
||||
% writematrix(xs1_imag_12b,'./xs1_imag.csv');
|
||||
|
||||
tb_snap = xs1_long_12b(:,(0:255)+54);
|
||||
tb_acorr = tb_snap*tb_snap';
|
||||
|
||||
wx1_32b = round(wx1/max(abs(wx1))*(2^31-1));
|
||||
wx1_16b = floor(wx1_32b/2^16);
|
||||
s_new1_30b = wx1_16b'*xs1_long_12b;
|
||||
s_new1_12b = s_new1_30b/2^18;
|
||||
+285
@@ -0,0 +1,285 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 2022/09/15 11:12:45
|
||||
// Last Modified Data: 2022/11/02
|
||||
// Design Name:
|
||||
// Module Name: tb_ad9361_cal
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description: testbench for [rx_pre_process]
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module tb_rx_pre;
|
||||
|
||||
localparam COL_NUM = 4;
|
||||
localparam PS_PL_WIDTH = 32;
|
||||
localparam OUTPUT_DATA_WIDTH = 30;
|
||||
|
||||
localparam FRAME_HEAD = 32'h7E7E7E7E;
|
||||
localparam FRAME_BITS = (2+COL_NUM*2)*PS_PL_WIDTH;
|
||||
|
||||
reg [FRAME_BITS-1 : 0] weight_stream_buf =
|
||||
{
|
||||
FRAME_HEAD, 32'd40,
|
||||
-32'd1145474114, 32'd1816473250 ,
|
||||
32'd2059208152, -32'd254581925 ,
|
||||
32'd2062565030, 32'd244279278 ,
|
||||
-32'd1154406364, -32'd1806170603
|
||||
};
|
||||
|
||||
reg sys_clk = 1'b1;
|
||||
reg sys_clk_4x = 1'b1;
|
||||
reg sys_rst = 1'b1;
|
||||
reg clk_96m = 1'b1;
|
||||
reg ant_rst = 1'b1;
|
||||
|
||||
reg ad9361_1_cal_start = 'b0;
|
||||
wire ad9361_1_cal_done ;
|
||||
reg ad9361_2_cal_start = 'b0;
|
||||
wire ad9361_2_cal_done ;
|
||||
wire ad9361_cal_result ;
|
||||
wire ad9361_cal_valid ;
|
||||
reg ad9361_recal = 'b0;
|
||||
|
||||
// phase difference of 0 degree
|
||||
wire [11:0] rx_ch1_i;
|
||||
wire [11:0] rx_ch1_q;
|
||||
wire [11:0] rx_ch2_i;
|
||||
wire [11:0] rx_ch2_q;
|
||||
wire [11:0] rx_ch3_q;
|
||||
wire [11:0] rx_ch3_i;
|
||||
wire [11:0] rx_ch4_i;
|
||||
wire [11:0] rx_ch4_q;
|
||||
|
||||
reg hop_start_flag = 1'b0;
|
||||
wire hop_flag_out;
|
||||
wire accor_stream_valid;
|
||||
wire accor_stream_data;
|
||||
wire weight_stream_data;
|
||||
wire rx_data_valid;
|
||||
wire [OUTPUT_DATA_WIDTH-1:0] rx_data_i, rx_data_q;
|
||||
|
||||
rx_pre_process #(
|
||||
.OUTPUT_WIDTH (OUTPUT_DATA_WIDTH ),
|
||||
.SYNC_HOP_INTVL (48*200 )
|
||||
) u_rx_pre_process
|
||||
(
|
||||
// clock & reset
|
||||
.sys_clk (sys_clk ), // input sys_clk
|
||||
.sys_clk_phy (sys_clk_4x ), // input sys_clk_4x
|
||||
.sys_rst (sys_rst ), // input sys_rst
|
||||
.clk_96m (clk_96m ), // input clk_96m
|
||||
.ant_rst (ant_rst ), // input ant_rst
|
||||
// input data interface
|
||||
.rx_ch1_i (rx_ch1_i ), // input [11:0] rx_ch1_i
|
||||
.rx_ch1_q (rx_ch1_q ), // input [11:0] rx_ch1_q
|
||||
.rx_ch2_i (-rx_ch2_i ), // input [11:0] rx_ch2_i
|
||||
.rx_ch2_q (-rx_ch2_q ), // input [11:0] rx_ch2_q
|
||||
.rx_ch3_i (rx_ch3_i ), // input [11:0] rx_ch3_i
|
||||
.rx_ch3_q (rx_ch3_q ), // input [11:0] rx_ch3_q
|
||||
.rx_ch4_i (-rx_ch4_i ), // input [11:0] rx_ch4_i
|
||||
.rx_ch4_q (-rx_ch4_q ), // input [11:0] rx_ch4_q
|
||||
// input channel phase
|
||||
.phase_ch1 ('b0 ),
|
||||
.phase_ch2 ('b0 ),
|
||||
.phase_ch3 ('b0 ),
|
||||
.phase_ch4 ('b0 ),
|
||||
// ad9361 calibration interface
|
||||
.ad9361_1_cal_start (ad9361_1_cal_start ), // input ad9361_1_cal_start
|
||||
.ad9361_1_cal_done (ad9361_1_cal_done ), // output ad9361_1_cal_done
|
||||
.ad9361_2_cal_start (ad9361_2_cal_start ), // input ad9361_2_cal_start
|
||||
.ad9361_2_cal_done (ad9361_2_cal_done ), // output ad9361_2_cal_done
|
||||
.ad9361_cal_result (ad9361_cal_result ), // output ad9361_cal_result
|
||||
.ad9361_cal_valid (ad9361_cal_valid ), // output ad9361_cal_valid
|
||||
.ad9361_recal (ad9361_recal ), // input ad9361_recal
|
||||
// nulling algotithm interface
|
||||
.hop_flag_in_phy (hop_start_flag ), // input hop_start_flag
|
||||
.sync_flag_phy (1'b0 ),
|
||||
.lcmv_en_phy (1'b1 ),
|
||||
.hop_flag_out (hop_flag_out ),
|
||||
|
||||
.accor_stream_valid (accor_stream_valid ), // output accor_stream_valid
|
||||
.accor_stream_data (accor_stream_data ), // output accor_stream_data
|
||||
.weight_stream_data (weight_stream_data ), // input weight_stream_data
|
||||
.rx_data_valid (rx_data_valid ),
|
||||
.rx_data_i (rx_data_i ),
|
||||
.rx_data_q (rx_data_q )
|
||||
);
|
||||
|
||||
// system clock generation
|
||||
always begin
|
||||
#6;
|
||||
sys_clk = ~sys_clk;
|
||||
#14;
|
||||
end
|
||||
|
||||
always begin
|
||||
#5 sys_clk_4x = ~sys_clk_4x;
|
||||
end
|
||||
|
||||
always begin
|
||||
#7;
|
||||
clk_96m = ~clk_96m;
|
||||
#3;
|
||||
end
|
||||
|
||||
initial begin
|
||||
#102
|
||||
sys_rst = 1'b0;
|
||||
ant_rst = 1'b0;
|
||||
#100
|
||||
ad9361_1_cal_start = 1'b1;
|
||||
end
|
||||
|
||||
always @(posedge sys_clk) begin
|
||||
if (ad9361_1_cal_done) begin
|
||||
ad9361_2_cal_start <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
ad9361_2_cal_start <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
integer r_file_real;
|
||||
integer r_file_imag;
|
||||
integer w_file_real;
|
||||
integer w_file_imag;
|
||||
|
||||
reg signed [11:0] rx_ch1_i_data = 'b0, rx_ch1_q_data = 'b0;
|
||||
reg signed [11:0] rx_ch2_i_data = 'b0, rx_ch2_q_data = 'b0;
|
||||
reg signed [11:0] rx_ch3_i_data = 'b0, rx_ch3_q_data = 'b0;
|
||||
reg signed [11:0] rx_ch4_i_data = 'b0, rx_ch4_q_data = 'b0;
|
||||
|
||||
reg [11:0] rx_ch1_i_cal = 12'd2047;
|
||||
reg [11:0] rx_ch1_q_cal = 12'd2047;
|
||||
reg [11:0] rx_ch2_i_cal = -12'd2047;
|
||||
reg [11:0] rx_ch2_q_cal = -12'd2047;
|
||||
reg [11:0] rx_ch3_q_cal = 12'd2047;
|
||||
reg [11:0] rx_ch3_i_cal = 12'd2047;
|
||||
reg [11:0] rx_ch4_i_cal = -12'd2047;
|
||||
reg [11:0] rx_ch4_q_cal = -12'd2047;
|
||||
|
||||
assign rx_ch1_i = ad9361_cal_valid ? rx_ch1_i_data : rx_ch1_i_cal;
|
||||
assign rx_ch1_q = ad9361_cal_valid ? rx_ch1_q_data : rx_ch1_q_cal;
|
||||
assign rx_ch2_i = ad9361_cal_valid ? rx_ch2_i_data : rx_ch2_i_cal;
|
||||
assign rx_ch2_q = ad9361_cal_valid ? rx_ch2_q_data : rx_ch2_q_cal;
|
||||
assign rx_ch3_i = ad9361_cal_valid ? rx_ch3_i_data : rx_ch3_i_cal;
|
||||
assign rx_ch3_q = ad9361_cal_valid ? rx_ch3_q_data : rx_ch3_q_cal;
|
||||
assign rx_ch4_i = ad9361_cal_valid ? rx_ch4_i_data : rx_ch4_i_cal;
|
||||
assign rx_ch4_q = ad9361_cal_valid ? rx_ch4_q_data : rx_ch4_q_cal;
|
||||
|
||||
initial begin
|
||||
forever begin
|
||||
@(posedge sys_clk)
|
||||
// 校准数据
|
||||
#720
|
||||
rx_ch1_i_cal = ~rx_ch1_i_cal;
|
||||
rx_ch2_i_cal = ~rx_ch2_i_cal;
|
||||
rx_ch3_i_cal = ~rx_ch3_i_cal;
|
||||
rx_ch4_i_cal = ~rx_ch4_i_cal;
|
||||
#240
|
||||
rx_ch1_q_cal = ~rx_ch1_q_cal;
|
||||
rx_ch2_q_cal = ~rx_ch2_q_cal;
|
||||
rx_ch3_q_cal = ~rx_ch3_q_cal;
|
||||
rx_ch4_q_cal = ~rx_ch4_q_cal;
|
||||
end
|
||||
end
|
||||
|
||||
initial begin
|
||||
r_file_real = $fopen("../../../../dl814_k7_cal_coarse.srcs/sim_1/new/xs1_real.csv","r");
|
||||
r_file_imag = $fopen("../../../../dl814_k7_cal_coarse.srcs/sim_1/new/xs1_imag.csv","r");
|
||||
|
||||
w_file_real = $fopen("../../../../dl814_k7_cal_coarse.srcs/sim_1/new/out_real.csv","w");
|
||||
w_file_imag = $fopen("../../../../dl814_k7_cal_coarse.srcs/sim_1/new/out_imag.csv","w");
|
||||
|
||||
@(posedge ad9361_cal_valid)
|
||||
|
||||
forever begin
|
||||
@(posedge sys_clk)
|
||||
$fscanf(r_file_real,"%d,%d,%d,%d",
|
||||
rx_ch1_i_data,
|
||||
rx_ch2_i_data,
|
||||
rx_ch3_i_data,
|
||||
rx_ch4_i_data);
|
||||
$fscanf(r_file_imag,"%d,%d,%d,%d",
|
||||
rx_ch1_q_data,
|
||||
rx_ch2_q_data,
|
||||
rx_ch3_q_data,
|
||||
rx_ch4_q_data);
|
||||
$fdisplay(w_file_real,"%d,%d,%d,%d,%d",
|
||||
$signed(u_rx_pre_process.rx_comp_ch1_i),
|
||||
$signed(u_rx_pre_process.rx_comp_ch2_i),
|
||||
$signed(u_rx_pre_process.rx_comp_ch3_i),
|
||||
$signed(u_rx_pre_process.rx_comp_ch4_i),
|
||||
$signed(rx_data_i));
|
||||
$fdisplay(w_file_imag,"%d,%d,%d,%d,%d",
|
||||
$signed(u_rx_pre_process.rx_comp_ch1_q),
|
||||
$signed(u_rx_pre_process.rx_comp_ch2_q),
|
||||
$signed(u_rx_pre_process.rx_comp_ch3_q),
|
||||
$signed(u_rx_pre_process.rx_comp_ch4_q),
|
||||
$signed(rx_data_q));
|
||||
end
|
||||
end
|
||||
|
||||
// hop flag counter
|
||||
reg [$clog2(38400)-1 : 0] hop_cnt = 'b0;
|
||||
|
||||
always @(posedge sys_clk_4x) begin
|
||||
if (sys_rst) begin
|
||||
hop_cnt <= 'b0;
|
||||
hop_start_flag <= 1'b0;
|
||||
end
|
||||
else if (ad9361_cal_valid) begin
|
||||
hop_cnt <= (hop_cnt == 200*48*4-1) ? 'b0 : hop_cnt + 1'b1;
|
||||
hop_start_flag <= (hop_cnt == 127) ? 1'b1 : 1'b0;
|
||||
end
|
||||
else begin
|
||||
hop_cnt <= hop_cnt;
|
||||
hop_start_flag <= hop_start_flag;
|
||||
end
|
||||
end
|
||||
|
||||
//
|
||||
reg weight_stream_valid = 'b0;
|
||||
|
||||
always @(negedge accor_stream_valid) begin
|
||||
if (~sys_rst) begin
|
||||
#((48*50)*40+18); // 50us of 48M clock
|
||||
weight_stream_valid = 'b1;
|
||||
#(FRAME_BITS*20);
|
||||
weight_stream_valid = 'b0;
|
||||
end
|
||||
end
|
||||
|
||||
reg [$clog2(FRAME_BITS)-1 : 0] weight_stream_cnt;
|
||||
|
||||
always @(posedge clk_96m) begin
|
||||
if (sys_rst) begin
|
||||
weight_stream_cnt <= 'b0;
|
||||
end
|
||||
else begin
|
||||
weight_stream_cnt <= (weight_stream_valid & ~(weight_stream_cnt == FRAME_BITS - 1)) ? weight_stream_cnt + 1'b1 : 'b0;
|
||||
end
|
||||
end
|
||||
|
||||
assign weight_stream_data = weight_stream_buf[FRAME_BITS-1-weight_stream_cnt];
|
||||
|
||||
endmodule
|
||||
|
||||
+278
@@ -0,0 +1,278 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 2022/11/16 15:58:28
|
||||
// Design Name:
|
||||
// Module Name: tb_rx_pre_test
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description: Co-simulation testbench for [rx_pre_process] and [rx_pre_test]
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module tb_rx_pre_test;
|
||||
|
||||
localparam COL_NUM = 4;
|
||||
localparam PS_PL_WIDTH = 32;
|
||||
|
||||
localparam FRAME_HEAD = 32'h7E7E7E7E;
|
||||
localparam FRAME_BITS = (2+COL_NUM*2)*PS_PL_WIDTH;
|
||||
|
||||
reg [FRAME_BITS-1 : 0] weight_stream_buf =
|
||||
{
|
||||
FRAME_HEAD, 32'd40,
|
||||
-32'd1145474114, 32'd1816473250,
|
||||
32'd2059208152, -32'd254581925 ,
|
||||
32'd2062565030, 32'd244279278 ,
|
||||
-32'd1154406364, -32'd1806170603
|
||||
};
|
||||
|
||||
reg sys_clk = 1'b1;
|
||||
reg sys_clk_2x = 1'b1;
|
||||
reg sys_clk_4x = 1'b1;
|
||||
reg sys_rst = 1'b1;
|
||||
wire clk_96m;
|
||||
wire ant_rst;
|
||||
|
||||
reg ad9361_1_cal_start = 'b0;
|
||||
wire ad9361_1_cal_done ;
|
||||
reg ad9361_2_cal_start = 'b0;
|
||||
wire ad9361_2_cal_done ;
|
||||
wire ad9361_cal_result ;
|
||||
wire ad9361_cal_valid ;
|
||||
reg ad9361_recal = 'b0;
|
||||
|
||||
// phase difference of 0 degree
|
||||
reg [11:0] rx_ch1_i = 0, rx_ch1_q = 0;
|
||||
reg [11:0] rx_ch2_i = 0, rx_ch2_q = 0;
|
||||
reg [11:0] rx_ch3_i = 0, rx_ch3_q = 0;
|
||||
reg [11:0] rx_ch4_i = 0, rx_ch4_q = 0;
|
||||
|
||||
wire [11:0] rx_ch1_i_test, rx_ch1_q_test;
|
||||
wire [11:0] rx_ch2_i_test, rx_ch2_q_test;
|
||||
wire [11:0] rx_ch3_i_test, rx_ch3_q_test;
|
||||
wire [11:0] rx_ch4_i_test, rx_ch4_q_test;
|
||||
|
||||
reg [11:0] rx_ch1_i_cal = 12'd2047;
|
||||
reg [11:0] rx_ch1_q_cal = 12'd2047;
|
||||
reg [11:0] rx_ch2_i_cal = -12'd2047;
|
||||
reg [11:0] rx_ch2_q_cal = -12'd2047;
|
||||
reg [11:0] rx_ch3_q_cal = 12'd2047;
|
||||
reg [11:0] rx_ch3_i_cal = 12'd2047;
|
||||
reg [11:0] rx_ch4_i_cal = -12'd2047;
|
||||
reg [11:0] rx_ch4_q_cal = -12'd2047;
|
||||
|
||||
wire hop_start_flag;
|
||||
wire hop_flag_out;
|
||||
wire accor_stream_valid;
|
||||
wire accor_stream_data;
|
||||
wire weight_stream_data;
|
||||
wire rx_data_valid;
|
||||
wire [29:0] rx_data_i, rx_data_q;
|
||||
|
||||
reg hop_trigger = 1'b0;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/////////////////////////////// Clock Generation ///////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
always #5 sys_clk_4x = ~sys_clk_4x;
|
||||
|
||||
always @(posedge sys_clk_4x) begin
|
||||
sys_clk_2x <= ~sys_clk_2x;
|
||||
end
|
||||
|
||||
always @(posedge sys_clk_2x) begin
|
||||
sys_clk <= ~sys_clk;
|
||||
end
|
||||
|
||||
assign #3 clk_96m = sys_clk_2x;
|
||||
assign #3 ant_rst = sys_rst;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
///////////////////////////// Stimulus Generation //////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
initial begin
|
||||
#102
|
||||
sys_rst = 1'b0;
|
||||
#100
|
||||
ad9361_1_cal_start = 1'b1;
|
||||
wait(ad9361_cal_valid);
|
||||
#1000
|
||||
hop_trigger = 1'b1;
|
||||
|
||||
#(192*200*10) // after 200us, trig again
|
||||
hop_trigger = 1'b0;
|
||||
|
||||
#(192*200*10) // after 200us, trig again
|
||||
hop_trigger = 1'b1;
|
||||
|
||||
#(192*200*10) // after 200us, trig again
|
||||
hop_trigger = 1'b0;
|
||||
|
||||
#(192*200*10) // after 200us, trig again
|
||||
hop_trigger = 1'b1;
|
||||
|
||||
#(192*200*10) // after 200us, trig again
|
||||
hop_trigger = 1'b0;
|
||||
|
||||
#(192*200*10) // after 200us, trig again
|
||||
hop_trigger = 1'b1;
|
||||
end
|
||||
|
||||
always @(posedge sys_clk) begin
|
||||
if (ad9361_1_cal_done) begin
|
||||
ad9361_2_cal_start <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
ad9361_2_cal_start <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge sys_clk) begin
|
||||
if (ad9361_cal_valid) begin
|
||||
rx_ch1_i <= rx_ch1_i_test;
|
||||
rx_ch1_q <= rx_ch1_q_test;
|
||||
rx_ch2_i <= rx_ch2_i_test;
|
||||
rx_ch2_q <= rx_ch2_q_test;
|
||||
rx_ch3_i <= rx_ch3_i_test;
|
||||
rx_ch3_q <= rx_ch3_q_test;
|
||||
rx_ch4_i <= rx_ch4_i_test;
|
||||
rx_ch4_q <= rx_ch4_q_test;
|
||||
end
|
||||
else begin
|
||||
rx_ch1_i <= rx_ch1_i_cal;
|
||||
rx_ch1_q <= rx_ch1_q_cal;
|
||||
rx_ch2_i <= rx_ch2_i_cal;
|
||||
rx_ch2_q <= rx_ch2_q_cal;
|
||||
rx_ch3_i <= rx_ch3_i_cal;
|
||||
rx_ch3_q <= rx_ch3_q_cal;
|
||||
rx_ch4_i <= rx_ch4_i_cal;
|
||||
rx_ch4_q <= rx_ch4_q_cal;
|
||||
end
|
||||
end
|
||||
|
||||
// 校准数据
|
||||
always @(posedge sys_clk) begin
|
||||
rx_ch1_i_cal = ~rx_ch1_i_cal;
|
||||
rx_ch1_q_cal = ~rx_ch1_q_cal;
|
||||
rx_ch2_i_cal = ~rx_ch2_i_cal;
|
||||
rx_ch2_q_cal = ~rx_ch2_q_cal;
|
||||
rx_ch3_i_cal = ~rx_ch3_i_cal;
|
||||
rx_ch3_q_cal = ~rx_ch3_q_cal;
|
||||
rx_ch4_i_cal = ~rx_ch4_i_cal;
|
||||
rx_ch4_q_cal = ~rx_ch4_q_cal;
|
||||
end
|
||||
|
||||
reg weight_stream_valid = 'b0;
|
||||
|
||||
always @(negedge accor_stream_valid) begin
|
||||
#((48*50)*40+18); // 50us of 48M clock
|
||||
weight_stream_valid = 'b1;
|
||||
#(FRAME_BITS*20);
|
||||
weight_stream_valid = 'b0;
|
||||
end
|
||||
|
||||
reg [$clog2(FRAME_BITS)-1 : 0] weight_stream_cnt = FRAME_BITS - 1;
|
||||
|
||||
always @(posedge clk_96m) begin
|
||||
if (sys_rst) begin
|
||||
weight_stream_cnt <= FRAME_BITS - 1;
|
||||
end
|
||||
else begin
|
||||
weight_stream_cnt <= (weight_stream_valid & ~(weight_stream_cnt == FRAME_BITS - 1)) ? weight_stream_cnt + 1'b1 : 'b0;
|
||||
end
|
||||
end
|
||||
|
||||
assign weight_stream_data = weight_stream_buf[FRAME_BITS-1-weight_stream_cnt];
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/////////////////////// Simulation Module Instantiation ////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
rx_pre_process #(
|
||||
.OUTPUT_WIDTH (30 ),
|
||||
.SYNC_HOP_INTVL (48*200 )
|
||||
) u_rx_pre_process
|
||||
(
|
||||
// clock & reset
|
||||
.sys_clk (sys_clk ), // sync to adc data
|
||||
.sys_clk_phy (sys_clk_4x ), // sync to physical layer
|
||||
.sys_rst (sys_rst ), // sync to [sys_clk]
|
||||
.clk_96m (clk_96m ), // sync to c2c data
|
||||
.ant_rst (ant_rst ), // sync to [clk_96m]
|
||||
// input data interface
|
||||
.rx_ch1_i (rx_ch1_i ),
|
||||
.rx_ch1_q (rx_ch1_q ),
|
||||
.rx_ch2_i (rx_ch2_i ),
|
||||
.rx_ch2_q (rx_ch2_q ),
|
||||
.rx_ch3_i (rx_ch3_i ),
|
||||
.rx_ch3_q (rx_ch3_q ),
|
||||
.rx_ch4_i (rx_ch4_i ),
|
||||
.rx_ch4_q (rx_ch4_q ),
|
||||
// input channel phase
|
||||
.phase_ch1 ('b0 ),
|
||||
.phase_ch2 ('b0 ),
|
||||
.phase_ch3 ('b0 ),
|
||||
.phase_ch4 ('b0 ),
|
||||
// ad9361 calibration interface
|
||||
.ad9361_1_cal_start (ad9361_1_cal_start ),
|
||||
.ad9361_1_cal_done (ad9361_1_cal_done ),
|
||||
.ad9361_2_cal_start (ad9361_2_cal_start ),
|
||||
.ad9361_2_cal_done (ad9361_2_cal_done ),
|
||||
.ad9361_cal_result (ad9361_cal_result ),
|
||||
.ad9361_cal_valid (ad9361_cal_valid ),
|
||||
.ad9361_recal (ad9361_recal ),
|
||||
// nulling algotithm interface
|
||||
.hop_flag_in_phy (hop_start_flag ), // input hop_start_flag
|
||||
.sync_flag_phy (1'b0 ),
|
||||
.lcmv_en_phy (1'b1 ),
|
||||
.hop_flag_out (hop_flag_out ),
|
||||
|
||||
.accor_stream_valid (accor_stream_valid ), // output accor_stream_valid
|
||||
.accor_stream_data (accor_stream_data ), // output accor_stream_data
|
||||
.weight_stream_data (weight_stream_data ), // input weight_stream_data
|
||||
.rx_data_valid (rx_data_valid ),
|
||||
.rx_data_i (rx_data_i ),
|
||||
.rx_data_q (rx_data_q )
|
||||
);
|
||||
|
||||
// temporary test cases
|
||||
rx_pre_test u_rx_pre_test
|
||||
(
|
||||
// clock & reset
|
||||
.clk (sys_clk ),
|
||||
.rst (sys_rst ),
|
||||
.clk_phy (sys_clk_4x ),
|
||||
.hop_trigger (hop_trigger ),
|
||||
.hop_trigger_en (1'b1 ),
|
||||
// calc result
|
||||
.ad9361_cal_result (ad9361_cal_result ),
|
||||
.ad9361_cal_valid (ad9361_cal_valid ),
|
||||
// output test data
|
||||
.rx_ch1_i (rx_ch1_i_test ),
|
||||
.rx_ch1_q (rx_ch1_q_test ),
|
||||
.rx_ch2_i (rx_ch2_i_test ),
|
||||
.rx_ch2_q (rx_ch2_q_test ),
|
||||
.rx_ch3_i (rx_ch3_i_test ),
|
||||
.rx_ch3_q (rx_ch3_q_test ),
|
||||
.rx_ch4_i (rx_ch4_i_test ),
|
||||
.rx_ch4_q (rx_ch4_q_test ),
|
||||
.hop_start_flag (hop_start_flag )
|
||||
);
|
||||
|
||||
endmodule
|
||||
+115
@@ -0,0 +1,115 @@
|
||||
%%%%%%%%%%%%%%%%%%%%%%%%%%
|
||||
%本仿真基于以下环境，64元矩形方阵，每若干个阵元通过TR通道和合路器，合成一路子阵信号，然后AD采样进入阵列信号处理单元；
|
||||
% - 子阵分割均匀，（16，16，16，16），共有4个子阵
|
||||
% - 1个已知方向的期望来波，3个未知方向的干扰信号；
|
||||
% - 信干比60dB；
|
||||
%θ表示俯仰角（来波与Z轴正向夹角）；φ表示方位角（来波在XOY平面投影与X轴正向夹角）；X轴与阵列每列平行，Y轴与阵列每行平行
|
||||
%通过空域滤波得到抑制干扰后的信号
|
||||
%%%%%%%%%%%%%%%%%%%%%%%%
|
||||
clc;
|
||||
clear all;
|
||||
Tt=256;%快拍数，用于阵列信号处理的采样点数
|
||||
Tmax = 32768;
|
||||
t=1:Tmax;
|
||||
%%%%%%%%%此处假设来波均为单频信号，可按自身定义修改
|
||||
f1=0.1*pi;
|
||||
f2=0.2*pi;
|
||||
f3=0.3*pi;
|
||||
f4=0.4*pi;
|
||||
|
||||
%% 通信基带信号
|
||||
|
||||
%% 窄带白噪声干扰信号
|
||||
filter_name = 'lpf_fs100_fpass5_fstop6.mat';
|
||||
%%
|
||||
snr=0;%信噪比可根据应用场景确定
|
||||
sjr=(60+snr);%干信比
|
||||
s1=sqrt(2*10^(snr/10))*exp(1i*f1*t);
|
||||
s2=sqrt(2*10^(sjr/10))*exp(1i*f2*t);
|
||||
s3=sqrt(2*10^(sjr/10))*exp(1i*f3*t);
|
||||
s4=sqrt(2*10^(sjr/10))*exp(1i*f4*t);
|
||||
%%%%%%%由信噪比和干信比计算出信号的幅度
|
||||
lamuda=1;%当前载频的波长，可根据载频输入实际值d
|
||||
d=0.5;%阵元间距，需小于最高工作频率半波长，可根据实际情况输入实际值
|
||||
|
||||
theta1=20;%期望来波俯仰角
|
||||
phi1=30;%期望来波方位角
|
||||
|
||||
theta2=-20;%干扰1俯仰角
|
||||
phi2=50;%干扰1方位角
|
||||
|
||||
theta3=-40;%干扰2俯仰角
|
||||
phi3=80;%干扰2方位角
|
||||
|
||||
theta4=-60;%干扰3俯仰角
|
||||
phi4=120;%干扰3方位角
|
||||
|
||||
%%%%%%%%
|
||||
m=8;%列
|
||||
n=8;%行
|
||||
L=m*n;
|
||||
a1=exp(1i*2*pi*d/lamuda*(-(m/2-1/2):1:(m/2-1/2)).'*sin(theta1/180*pi)*sin(phi1/180*pi));
|
||||
b1=exp(1i*2*pi*d/lamuda*(-(n/2-1/2):1:(n/2-1/2)).'*sin(theta1/180*pi)*cos(phi1/180*pi));
|
||||
A1=kron(b1,a1);
|
||||
|
||||
a2=exp(1i*2*pi*d/lamuda*(-(m/2-1/2):1:(m/2-1/2)).'*sin(theta2/180*pi)*sin(phi2/180*pi));
|
||||
b2=exp(1i*2*pi*d/lamuda*(-(n/2-1/2):1:(n/2-1/2)).'*sin(theta2/180*pi)*cos(phi2/180*pi));
|
||||
A2=kron(b2,a2);
|
||||
|
||||
a3=exp(1i*2*pi*d/lamuda*(-(m/2-1/2):1:(m/2-1/2)).'*sin(theta3/180*pi)*sin(phi3/180*pi));
|
||||
b3=exp(1i*2*pi*d/lamuda*(-(n/2-1/2):1:(n/2-1/2)).'*sin(theta3/180*pi)*cos(phi3/180*pi));
|
||||
A3=kron(b3,a3);
|
||||
|
||||
a4=exp(1i*2*pi*d/lamuda*(-(m/2-1/2):1:(m/2-1/2)).'*sin(theta4/180*pi)*sin(phi4/180*pi));
|
||||
b4=exp(1i*2*pi*d/lamuda*(-(n/2-1/2):1:(n/2-1/2)).'*sin(theta4/180*pi)*cos(phi4/180*pi));
|
||||
A4=kron(b4,a4);
|
||||
|
||||
As=[A1,A2,A3,A4];%阵列流型
|
||||
rng(0);
|
||||
x=As*[s1;s2;s3;s4]+randn(L,Tmax);
|
||||
%%%%%%%%%%%%%%%4元子阵
|
||||
%
|
||||
N1=4;
|
||||
C1=zeros(N1,64);
|
||||
D1=zeros(N1,64);
|
||||
for kk=0:3
|
||||
C1(1,(kk*8+1):(kk*8+4))=ones(1,4);
|
||||
C1(2,(kk*8+5):(kk*8+8))=ones(1,4);
|
||||
C1(3,(kk*8+33):(kk*8+36))=ones(1,4);
|
||||
C1(4,(kk*8+37):(kk*8+40))=ones(1,4);
|
||||
end
|
||||
%}
|
||||
%%%%%%%%%%%%%%%%%%%%%%
|
||||
D1=C1*diag(A1');%4元 阵元通道移相后，每16路合路为一个子阵
|
||||
% D2=C2*diag(A1');%6元 阵元通道移相后，每(16,8)路合路为一个子阵
|
||||
% D3=C3*diag(A1');%8元 阵元通道移相后，每8路合路为一个子阵
|
||||
% %%%%%%%%%%%%%%%%%
|
||||
xs1=D1*x(:,1:Tt);
|
||||
Rx1=xs1*xs1';%4元子阵协方差矩阵
|
||||
Ax1=D1*A1;%期望来波方向的子阵导向矢量
|
||||
wx1=inv(Rx1)*Ax1/(Ax1'*inv(Rx1)*Ax1);%4子阵的LCMV权值
|
||||
|
||||
xs1_long = D1*x;
|
||||
s_new1=wx1'*xs1_long;%4子阵情况下的空域滤波后的信号
|
||||
% s_new1=[1,1,1,1]*xs1;
|
||||
|
||||
%% 数据导出
|
||||
xs1_long_12b = round(xs1_long/max(max(abs(xs1_long)))*(2^11-1));
|
||||
xs1_real_12b = real(xs1_long_12b);
|
||||
xs1_imag_12b = imag(xs1_long_12b);
|
||||
|
||||
xs1_12b_bin_join = strings(9600,96);
|
||||
|
||||
for i = 1:9600
|
||||
xs1_real_12b_bin = dec2bin(xs1_real_12b(:,i),16);
|
||||
xs1_real_12b_bin_join_tmp = '';
|
||||
xs1_imag_12b_bin = dec2bin(xs1_imag_12b(:,i),16);
|
||||
xs1_imag_12b_bin_join_tmp = '';
|
||||
for j = 1:4
|
||||
xs1_real_12b_bin_trunc = xs1_real_12b_bin(j,5:16);
|
||||
xs1_real_12b_bin_join_tmp = [xs1_real_12b_bin_join_tmp,xs1_real_12b_bin_trunc];
|
||||
xs1_imag_12b_bin_trunc = xs1_imag_12b_bin(j,5:16);
|
||||
xs1_imag_12b_bin_join_tmp = [xs1_imag_12b_bin_join_tmp,xs1_imag_12b_bin_trunc];
|
||||
end
|
||||
xs1_12b_bin_join(i) = [xs1_real_12b_bin_join_tmp,xs1_imag_12b_bin_join_tmp];
|
||||
end
|
||||
+85
@@ -0,0 +1,85 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 2022/11/16 15:08:02
|
||||
// Design Name:
|
||||
// Module Name: tb_rx_test
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description: testbench for [rx_pre_test]
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module tb_rx_test;
|
||||
|
||||
reg sys_clk = 1'b1;
|
||||
reg sys_clk_4x = 1'b1;
|
||||
reg sys_rst = 1'b1;
|
||||
reg hop_trigger = 1'b0;
|
||||
|
||||
reg ad9361_cal_result = 1'b0;
|
||||
reg ad9361_cal_valid = 1'b0;
|
||||
|
||||
wire [11:0] rx_ch1_i;
|
||||
wire [11:0] rx_ch1_q;
|
||||
wire [11:0] rx_ch2_i;
|
||||
wire [11:0] rx_ch2_q;
|
||||
wire [11:0] rx_ch3_i;
|
||||
wire [11:0] rx_ch3_q;
|
||||
wire [11:0] rx_ch4_i;
|
||||
wire [11:0] rx_ch4_q;
|
||||
wire hop_start_flag;
|
||||
|
||||
rx_pre_test u_rx_pre_test
|
||||
(
|
||||
// clock & reset
|
||||
.clk (sys_clk ),
|
||||
.rst (sys_rst ),
|
||||
.hop_trigger (hop_trigger ),
|
||||
// calc result
|
||||
.ad9361_cal_result (ad9361_cal_result ),
|
||||
.ad9361_cal_valid (ad9361_cal_valid ),
|
||||
// output test data
|
||||
.rx_ch1_i (rx_ch1_i ),
|
||||
.rx_ch1_q (rx_ch1_q ),
|
||||
.rx_ch2_i (rx_ch2_i ),
|
||||
.rx_ch2_q (rx_ch2_q ),
|
||||
.rx_ch3_i (rx_ch3_i ),
|
||||
.rx_ch3_q (rx_ch3_q ),
|
||||
.rx_ch4_i (rx_ch4_i ),
|
||||
.rx_ch4_q (rx_ch4_q ),
|
||||
.hop_start_flag (hop_start_flag )
|
||||
);
|
||||
|
||||
// system clock generation
|
||||
always begin
|
||||
#5 sys_clk = ~sys_clk;
|
||||
end
|
||||
|
||||
initial begin
|
||||
#102
|
||||
sys_rst = 1'b0;
|
||||
#100
|
||||
ad9361_cal_valid = 1'b1;
|
||||
#1000
|
||||
hop_trigger = 1'b1;
|
||||
#100
|
||||
hop_trigger = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
+93
@@ -0,0 +1,93 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 2023/02/25 15:50:45
|
||||
// Design Name:
|
||||
// Module Name: tb_tx_pre_process
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module tb_tx_pre_process;
|
||||
|
||||
reg clk = 1'b1;
|
||||
reg rst = 1'b1;
|
||||
|
||||
reg [11:0] tx_data_ch1_i = 'b0;
|
||||
reg [11:0] tx_data_ch1_q = 'b0;
|
||||
reg [11:0] tx_data_ch2_i = 'b0;
|
||||
reg [11:0] tx_data_ch2_q = 'b0;
|
||||
|
||||
reg ad9361_tx_switch = 1'b0;
|
||||
|
||||
reg [3:0] bb_rshift = 4'd3;
|
||||
|
||||
wire [11:0] tx_ch1_i;
|
||||
wire [11:0] tx_ch1_q;
|
||||
wire [11:0] tx_ch2_i;
|
||||
wire [11:0] tx_ch2_q;
|
||||
|
||||
tx_pre_process #(
|
||||
.CAL_MOD_FINE (1 )
|
||||
) u_tx_pre_process
|
||||
(
|
||||
// clock & reset
|
||||
.clk (clk ),
|
||||
.rst (rst ),
|
||||
// input data
|
||||
.tx_data_ch1_i (tx_data_ch1_i ),
|
||||
.tx_data_ch1_q (tx_data_ch1_q ),
|
||||
.tx_data_ch2_i (tx_data_ch2_i ),
|
||||
.tx_data_ch2_q (tx_data_ch2_q ),
|
||||
// ad9361 calibration interface
|
||||
.ad9361_tx_switch (ad9361_tx_switch ),
|
||||
//
|
||||
.bb_rshift (bb_rshift ),
|
||||
// output data
|
||||
.tx_ch1_i (tx_ch1_i ),
|
||||
.tx_ch1_q (tx_ch1_q ),
|
||||
.tx_ch2_i (tx_ch2_i ),
|
||||
.tx_ch2_q (tx_ch2_q )
|
||||
);
|
||||
|
||||
initial begin
|
||||
#102 rst = 1'b0;
|
||||
#100 ad9361_tx_switch = 1'b1;
|
||||
#10000 ad9361_tx_switch = 1'b0;
|
||||
end
|
||||
|
||||
always #10 clk = ~clk;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
tx_data_ch1_i <= 'b0;
|
||||
tx_data_ch1_q <= 'b0;
|
||||
tx_data_ch2_i <= 'b0;
|
||||
tx_data_ch2_q <= 'b0;
|
||||
end
|
||||
else begin
|
||||
tx_data_ch1_i <= tx_data_ch1_i + 12'd1;
|
||||
tx_data_ch1_q <= tx_data_ch1_q + 12'd2;
|
||||
tx_data_ch2_i <= tx_data_ch2_i + 12'd3;
|
||||
tx_data_ch2_q <= tx_data_ch2_q + 12'd4;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
+86
@@ -0,0 +1,86 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 03/29/2023 09:02:30 PM
|
||||
// Design Name:
|
||||
// Module Name: tb_xpm_cdc_pulse
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module tb_xpm_cdc_pulse;
|
||||
|
||||
reg sys_clk = 1'b1;
|
||||
reg sys_clk_4x = 1'b1;
|
||||
reg sys_rst = 1'b1;
|
||||
|
||||
reg src_pulse = 1'b0;
|
||||
wire dest_pulse;
|
||||
|
||||
xpm_cdc_pulse #(
|
||||
.DEST_SYNC_FF (4), // DECIMAL; range: 2-10
|
||||
.INIT_SYNC_FF (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
.REG_OUTPUT (1), // DECIMAL; 0=disable registered output, 1=enable registered output
|
||||
.RST_USED (1), // DECIMAL; 0=no reset, 1=implement reset
|
||||
.SIM_ASSERT_CHK (1) // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
) u_xpm_cdc_pulse
|
||||
(
|
||||
.dest_pulse (dest_pulse ), // 1-bit output: Outputs a pulse the size of one dest_clk period when a pulse
|
||||
// transfer is correctly initiated on src_pulse input. This output is
|
||||
// combinatorial unless REG_OUTPUT is set to 1.
|
||||
.dest_clk (sys_clk ), // 1-bit input: Destination clock.
|
||||
.dest_rst (sys_rst ), // 1-bit input: optional; required when RST_USED = 1
|
||||
.src_clk (sys_clk_4x ), // 1-bit input: Source clock.
|
||||
.src_pulse (src_pulse ), // 1-bit input: Rising edge of this signal initiates a pulse transfer to the
|
||||
// destination clock domain. The minimum gap between each pulse transfer must be
|
||||
// at the minimum 2*(larger(src_clk period, dest_clk period)). This is measured
|
||||
// between the falling edge of a src_pulse to the rising edge of the next
|
||||
// src_pulse. This minimum gap will guarantee that each rising edge of src_pulse
|
||||
// will generate a pulse the size of one dest_clk period in the destination
|
||||
// clock domain. When RST_USED = 1, pulse transfers will not be guaranteed while
|
||||
// src_rst and/or dest_rst are asserted.
|
||||
.src_rst (sys_rst ) // 1-bit input: optional; required when RST_USED = 1
|
||||
);
|
||||
|
||||
initial begin
|
||||
#102;
|
||||
sys_rst = 1'b0;
|
||||
end
|
||||
|
||||
always begin
|
||||
#3;
|
||||
sys_clk = ~sys_clk;
|
||||
#37;
|
||||
end
|
||||
|
||||
always begin
|
||||
#5;
|
||||
sys_clk_4x = ~sys_clk_4x;
|
||||
end
|
||||
|
||||
reg [3:0] pulse_cnt = 'b0;
|
||||
|
||||
always @(posedge sys_clk_4x) begin
|
||||
if (sys_rst) begin
|
||||
src_pulse <= 1'b0;
|
||||
pulse_cnt <= 'b0;
|
||||
end
|
||||
else begin
|
||||
pulse_cnt <= pulse_cnt + 1'b1;
|
||||
src_pulse <= (pulse_cnt == 4'd15) ? 1'b1 : 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
LFS
BIN
Binary file not shown.
|
LFS
BIN
Binary file not shown.
|
@@ -9,12 +9,12 @@
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="c9336677cb8e467b997961f59fea4aa0"/>
|
||||
<Option Name="Part" Val="xc7k410tffg900-2"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDir" Val="$PPRDIR/../../../../../../Tools/XilCompLib/vcs/2023.2"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PPRDIR/../../../../../../Tools/XilCompLib/vcs/2023.2"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
||||
@@ -43,6 +43,7 @@
|
||||
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
|
||||
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
||||
<Option Name="TargetSimulator" Val="VCS"/>
|
||||
<Option Name="BoardPart" Val=""/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
@@ -64,7 +65,7 @@
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="10"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="34"/>
|
||||
@@ -563,11 +564,73 @@
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sim_1/new/tb_rx_pre.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sim_1/new/tb_rx_pre_test.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sim_1/new/tb_acorr.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sim_1/new/tb_null_ctrl.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sim_1/new/tb_accum.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sim_1/new/tb_xpm_cdc_pulse.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sim_1/new/tb_rx_test.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sim_1/new/tb_tx_pre_process.v">
|
||||
<FileInfo>
|
||||
<Attr Name="AutoDisabled" Val="1"/>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="system_top"/>
|
||||
<Option Name="TopModule" Val="tb_rx_pre"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||
@@ -576,6 +639,8 @@
|
||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
<Option Name="vcs.compile.vlogan.more_options" Val="-v2005 -kdb"/>
|
||||
<Option Name="vcs.elaborate.vcs.more_options" Val="-debug_access+all"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
@@ -1011,7 +1076,9 @@
|
||||
<Runs Version="1" Minor="21">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7k410tffg900-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/system_top.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
@@ -1391,7 +1458,9 @@
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 18 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
|
||||
Reference in New Issue
Block a user