change xilinx spi to adi spi, with 3-wire support
This commit is contained in:
+6
-116
@@ -581,116 +581,6 @@
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}
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]
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},
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{
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"type": "ILA_V3",
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"name": "u_system_bd_wrapper/system_bd_i/ila_spi",
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"spec": "labtools_ila_v6",
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"ipName": "ila",
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"core_location": {
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"user_chain": 1,
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"slave_index": 2,
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"bscan_switch_index": 0
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},
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"uuid": "CB9485C3DF3B5651BD89B030E5DB6A08",
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"pins": [
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{
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"name": "probe0",
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"id": 10,
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"type": "DATA_TRIGGER",
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"direction": "IN",
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"isVector": false,
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"leftIndex": 0,
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"rightIndex": 0,
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"portIndex": 0,
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"nets": [
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{
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"name": "u_system_bd_wrapper/system_bd_i/processing_system7_0_SPI0_SCLK_O",
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"isBus": false
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}
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]
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},
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{
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"name": "probe1",
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"id": 11,
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"type": "DATA_TRIGGER",
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"direction": "IN",
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"isVector": false,
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"leftIndex": 0,
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"rightIndex": 0,
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"portIndex": 1,
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"nets": [
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{
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"name": "u_system_bd_wrapper/system_bd_i/processing_system7_0_SPI0_MOSI_O",
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"isBus": false
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}
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]
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},
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{
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"name": "probe2",
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"id": 12,
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"type": "DATA_TRIGGER",
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"direction": "IN",
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"isVector": false,
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"leftIndex": 0,
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"rightIndex": 0,
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"portIndex": 2,
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"nets": [
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{
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"name": "u_system_bd_wrapper/system_bd_i/SPI0_MISO_I_0_1",
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"isBus": false
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}
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]
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},
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{
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"name": "probe3",
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"id": 13,
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"type": "DATA_TRIGGER",
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"direction": "IN",
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"isVector": false,
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"leftIndex": 0,
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"rightIndex": 0,
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"portIndex": 3,
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"nets": [
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{
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"name": "u_system_bd_wrapper/system_bd_i/processing_system7_0_SPI0_SS_O",
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"isBus": false
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}
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]
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},
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{
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"name": "probe4",
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"id": 14,
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"type": "DATA_TRIGGER",
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"direction": "IN",
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"isVector": false,
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"leftIndex": 0,
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"rightIndex": 0,
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"portIndex": 4,
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"nets": [
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{
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"name": "u_system_bd_wrapper/system_bd_i/processing_system7_0_SPI0_SS1_O",
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"isBus": false
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}
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]
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},
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{
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"name": "probe5",
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"id": 15,
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"type": "DATA_TRIGGER",
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"direction": "IN",
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"isVector": false,
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"leftIndex": 0,
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"rightIndex": 0,
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"portIndex": 5,
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"nets": [
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{
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"name": "u_system_bd_wrapper/system_bd_i/processing_system7_0_SPI0_SS2_O",
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"isBus": false
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}
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]
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}
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]
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},
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{
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"type": "VIO_V2",
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"name": "u_vio_manual_ctrl",
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@@ -698,14 +588,14 @@
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"ipName": "vio",
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"core_location": {
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"user_chain": 1,
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"slave_index": 3,
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"slave_index": 2,
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"bscan_switch_index": 0
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},
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"uuid": "6DFBBD640CB857419C054C66C7EA7B27",
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"pins": [
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{
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"name": "probe_out0",
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"id": 16,
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"id": 10,
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"type": "DATA",
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"direction": "OUT",
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"isVector": true,
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@@ -729,7 +619,7 @@
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},
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{
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"name": "probe_out1",
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"id": 17,
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"id": 11,
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"type": "DATA",
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"direction": "OUT",
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"isVector": false,
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@@ -745,7 +635,7 @@
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},
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{
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"name": "probe_out2",
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"id": 18,
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"id": 12,
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"type": "DATA",
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"direction": "OUT",
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"isVector": true,
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@@ -859,7 +749,7 @@
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},
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{
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"name": "probe_out3",
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"id": 19,
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"id": 13,
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"type": "DATA",
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"direction": "OUT",
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"isVector": true,
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@@ -883,7 +773,7 @@
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},
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{
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"name": "probe_out4",
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"id": 20,
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"id": 14,
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"type": "DATA",
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"direction": "OUT",
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"isVector": true,
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BIN
Binary file not shown.
+6
-116
@@ -581,116 +581,6 @@
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}
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]
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},
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{
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"type": "ILA_V3",
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"name": "u_system_bd_wrapper/system_bd_i/ila_spi",
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"spec": "labtools_ila_v6",
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"ipName": "ila",
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"core_location": {
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"user_chain": 1,
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"slave_index": 2,
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"bscan_switch_index": 0
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},
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"uuid": "CB9485C3DF3B5651BD89B030E5DB6A08",
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"pins": [
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{
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"name": "probe0",
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||||
"id": 10,
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||||
"type": "DATA_TRIGGER",
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"direction": "IN",
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"isVector": false,
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"leftIndex": 0,
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"rightIndex": 0,
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"portIndex": 0,
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"nets": [
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{
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"name": "u_system_bd_wrapper/system_bd_i/processing_system7_0_SPI0_SCLK_O",
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"isBus": false
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}
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]
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},
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{
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"name": "probe1",
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"id": 11,
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"type": "DATA_TRIGGER",
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"direction": "IN",
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"isVector": false,
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"leftIndex": 0,
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"rightIndex": 0,
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"portIndex": 1,
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"nets": [
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{
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"name": "u_system_bd_wrapper/system_bd_i/processing_system7_0_SPI0_MOSI_O",
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"isBus": false
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}
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]
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},
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{
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"name": "probe2",
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"id": 12,
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"type": "DATA_TRIGGER",
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"direction": "IN",
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"isVector": false,
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"leftIndex": 0,
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"rightIndex": 0,
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"portIndex": 2,
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"nets": [
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{
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"name": "u_system_bd_wrapper/system_bd_i/SPI0_MISO_I_0_1",
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"isBus": false
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}
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]
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},
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{
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"name": "probe3",
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"id": 13,
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"type": "DATA_TRIGGER",
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||||
"direction": "IN",
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||||
"isVector": false,
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"leftIndex": 0,
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"rightIndex": 0,
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"portIndex": 3,
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"nets": [
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{
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"name": "u_system_bd_wrapper/system_bd_i/processing_system7_0_SPI0_SS_O",
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"isBus": false
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}
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]
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},
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{
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"name": "probe4",
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"id": 14,
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"type": "DATA_TRIGGER",
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"direction": "IN",
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"isVector": false,
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"leftIndex": 0,
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"rightIndex": 0,
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"portIndex": 4,
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"nets": [
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{
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"name": "u_system_bd_wrapper/system_bd_i/processing_system7_0_SPI0_SS1_O",
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"isBus": false
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}
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]
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},
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{
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"name": "probe5",
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"id": 15,
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"type": "DATA_TRIGGER",
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||||
"direction": "IN",
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||||
"isVector": false,
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"leftIndex": 0,
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"rightIndex": 0,
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"portIndex": 5,
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"nets": [
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{
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"name": "u_system_bd_wrapper/system_bd_i/processing_system7_0_SPI0_SS2_O",
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"isBus": false
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}
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]
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}
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]
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},
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{
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"type": "VIO_V2",
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"name": "u_vio_manual_ctrl",
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@@ -698,14 +588,14 @@
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"ipName": "vio",
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"core_location": {
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"user_chain": 1,
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"slave_index": 3,
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"slave_index": 2,
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"bscan_switch_index": 0
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||||
},
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"uuid": "6DFBBD640CB857419C054C66C7EA7B27",
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||||
"pins": [
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{
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"name": "probe_out0",
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||||
"id": 16,
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||||
"id": 10,
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||||
"type": "DATA",
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||||
"direction": "OUT",
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"isVector": true,
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@@ -729,7 +619,7 @@
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},
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{
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"name": "probe_out1",
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||||
"id": 17,
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||||
"id": 11,
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||||
"type": "DATA",
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||||
"direction": "OUT",
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"isVector": false,
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@@ -745,7 +635,7 @@
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},
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{
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"name": "probe_out2",
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"id": 18,
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"id": 12,
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||||
"type": "DATA",
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"direction": "OUT",
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"isVector": true,
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@@ -859,7 +749,7 @@
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},
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{
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"name": "probe_out3",
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"id": 19,
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"id": 13,
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"type": "DATA",
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||||
"direction": "OUT",
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||||
"isVector": true,
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@@ -883,7 +773,7 @@
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},
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{
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"name": "probe_out4",
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"id": 20,
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||||
"id": 14,
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"type": "DATA",
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||||
"direction": "OUT",
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"isVector": true,
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+301
@@ -0,0 +1,301 @@
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{
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"schema": "xilinx.com:schema:json_instance:1.0",
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"ip_inst": {
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"xci_name": "system_bd_auto_pc_0",
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"cell_name": "ps7_axi_periph/s00_couplers/auto_pc",
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"component_reference": "xilinx.com:ip:axi_protocol_converter:2.1",
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"ip_revision": "30",
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"gen_directory": "../../../../../../duifei_cmos_1t2r.gen/sources_1/bd/system_bd/ip/system_bd_auto_pc_0",
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"parameters": {
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"component_parameters": {
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"SI_PROTOCOL": [ { "value": "AXI3", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
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"MI_PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
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"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
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"TRANSLATION_MODE": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"ADDR_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"DATA_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"ID_WIDTH": [ { "value": "12", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"AWUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"RUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"WUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_bd_auto_pc_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_M_AXI_PROTOCOL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_PROTOCOL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_IGNORE_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_ID_WIDTH": [ { "value": "12", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_SUPPORTS_WRITE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_SUPPORTS_READ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_SUPPORTS_USER_SIGNALS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_AWUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_ARUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_WUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_RUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_BUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_TRANSLATION_MODE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z100" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "30" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../duifei_cmos_1t2r.gen/sources_1/bd/system_bd/ip/system_bd_auto_pc_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "rtl" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.2.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in" } ],
|
||||
"s_axi_awid": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0x000" } ],
|
||||
"s_axi_awaddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
|
||||
"s_axi_awlen": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x1" } ],
|
||||
"s_axi_awlock": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axi_awready": [ { "direction": "out" } ],
|
||||
"s_axi_wid": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0x000" } ],
|
||||
"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
|
||||
"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0xF" } ],
|
||||
"s_axi_wlast": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axi_wready": [ { "direction": "out" } ],
|
||||
"s_axi_bid": [ { "direction": "out", "size_left": "11", "size_right": "0" } ],
|
||||
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_bvalid": [ { "direction": "out" } ],
|
||||
"s_axi_bready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axi_arid": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0x000" } ],
|
||||
"s_axi_araddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
|
||||
"s_axi_arlen": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_arsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_arburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x1" } ],
|
||||
"s_axi_arlock": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_arcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_arqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_arvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axi_arready": [ { "direction": "out" } ],
|
||||
"s_axi_rid": [ { "direction": "out", "size_left": "11", "size_right": "0" } ],
|
||||
"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_rlast": [ { "direction": "out" } ],
|
||||
"s_axi_rvalid": [ { "direction": "out" } ],
|
||||
"s_axi_rready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"m_axi_awaddr": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"m_axi_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"m_axi_awvalid": [ { "direction": "out" } ],
|
||||
"m_axi_awready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"m_axi_wdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"m_axi_wstrb": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"m_axi_wvalid": [ { "direction": "out" } ],
|
||||
"m_axi_wready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"m_axi_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"m_axi_bvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"m_axi_bready": [ { "direction": "out" } ],
|
||||
"m_axi_araddr": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"m_axi_arprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"m_axi_arvalid": [ { "direction": "out" } ],
|
||||
"m_axi_arready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"m_axi_rdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
|
||||
"m_axi_rresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"m_axi_rvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"m_axi_rready": [ { "direction": "out" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI3", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "12", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "16", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "4", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "4", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWID": [ { "physical_name": "s_axi_awid" } ],
|
||||
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||
"AWLEN": [ { "physical_name": "s_axi_awlen" } ],
|
||||
"AWSIZE": [ { "physical_name": "s_axi_awsize" } ],
|
||||
"AWBURST": [ { "physical_name": "s_axi_awburst" } ],
|
||||
"AWLOCK": [ { "physical_name": "s_axi_awlock" } ],
|
||||
"AWCACHE": [ { "physical_name": "s_axi_awcache" } ],
|
||||
"AWPROT": [ { "physical_name": "s_axi_awprot" } ],
|
||||
"AWQOS": [ { "physical_name": "s_axi_awqos" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||
"WID": [ { "physical_name": "s_axi_wid" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||
"WLAST": [ { "physical_name": "s_axi_wlast" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||
"BID": [ { "physical_name": "s_axi_bid" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_bready" } ],
|
||||
"ARID": [ { "physical_name": "s_axi_arid" } ],
|
||||
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
|
||||
"ARLEN": [ { "physical_name": "s_axi_arlen" } ],
|
||||
"ARSIZE": [ { "physical_name": "s_axi_arsize" } ],
|
||||
"ARBURST": [ { "physical_name": "s_axi_arburst" } ],
|
||||
"ARLOCK": [ { "physical_name": "s_axi_arlock" } ],
|
||||
"ARCACHE": [ { "physical_name": "s_axi_arcache" } ],
|
||||
"ARPROT": [ { "physical_name": "s_axi_arprot" } ],
|
||||
"ARQOS": [ { "physical_name": "s_axi_arqos" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
|
||||
"RID": [ { "physical_name": "s_axi_rid" } ],
|
||||
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
|
||||
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
|
||||
"RLAST": [ { "physical_name": "s_axi_rlast" } ],
|
||||
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
|
||||
"RREADY": [ { "physical_name": "s_axi_rready" } ]
|
||||
}
|
||||
},
|
||||
"M_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "4", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "4", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "m_axi_awaddr" } ],
|
||||
"AWPROT": [ { "physical_name": "m_axi_awprot" } ],
|
||||
"AWVALID": [ { "physical_name": "m_axi_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "m_axi_awready" } ],
|
||||
"WDATA": [ { "physical_name": "m_axi_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "m_axi_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "m_axi_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "m_axi_wready" } ],
|
||||
"BRESP": [ { "physical_name": "m_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "m_axi_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "m_axi_bready" } ],
|
||||
"ARADDR": [ { "physical_name": "m_axi_araddr" } ],
|
||||
"ARPROT": [ { "physical_name": "m_axi_arprot" } ],
|
||||
"ARVALID": [ { "physical_name": "m_axi_arvalid" } ],
|
||||
"ARREADY": [ { "physical_name": "m_axi_arready" } ],
|
||||
"RDATA": [ { "physical_name": "m_axi_rdata" } ],
|
||||
"RRESP": [ { "physical_name": "m_axi_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "m_axi_rvalid" } ],
|
||||
"RREADY": [ { "physical_name": "m_axi_rready" } ]
|
||||
}
|
||||
},
|
||||
"CLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI:M_AXI", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "ARESETN", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
},
|
||||
"RST": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+293
@@ -0,0 +1,293 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_bd_axi_spi_engine_0_0",
|
||||
"cell_name": "spi_engine/axi_spi_engine",
|
||||
"component_reference": "analog.com:user:axi_spi_engine:1.0",
|
||||
"ip_revision": "1",
|
||||
"gen_directory": "../../../../../../duifei_cmos_1t2r.gen/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"CMD_FIFO_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SYNC_FIFO_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SDO_FIFO_ADDRESS_WIDTH": [ { "value": "5", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SDI_FIFO_ADDRESS_WIDTH": [ { "value": "5", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MM_IF_TYPE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ASYNC_SPI_CLK": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"NUM_OFFLOAD": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"OFFLOAD0_CMD_MEM_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"OFFLOAD0_SDO_MEM_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ID": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_OF_SDI": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CFG_INFO_0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CFG_INFO_1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CFG_INFO_2": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CFG_INFO_3": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_bd_axi_spi_engine_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"CMD_FIFO_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SYNC_FIFO_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SDO_FIFO_ADDRESS_WIDTH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SDI_FIFO_ADDRESS_WIDTH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"MM_IF_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"ASYNC_SPI_CLK": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"NUM_OFFLOAD": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"OFFLOAD0_CMD_MEM_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"OFFLOAD0_SDO_MEM_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"NUM_OF_SDI": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"CFG_INFO_0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"CFG_INFO_1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"CFG_INFO_2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"CFG_INFO_3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z100" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "1" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../duifei_cmos_1t2r.gen/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.2.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axi_aclk": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_aresetn": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_awaddr": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awready": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wready": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"s_axi_bvalid": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_araddr": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arready": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"s_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_rvalid": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"s_axi_rready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"irq": [ { "direction": "out" } ],
|
||||
"spi_clk": [ { "direction": "in" } ],
|
||||
"spi_resetn": [ { "direction": "out" } ],
|
||||
"cmd_ready": [ { "direction": "in" } ],
|
||||
"cmd_valid": [ { "direction": "out" } ],
|
||||
"cmd_data": [ { "direction": "out", "size_left": "15", "size_right": "0" } ],
|
||||
"sdo_data_ready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"sdo_data_valid": [ { "direction": "out" } ],
|
||||
"sdo_data": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||
"sdi_data_ready": [ { "direction": "out" } ],
|
||||
"sdi_data_valid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"sdi_data": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"sync_ready": [ { "direction": "out" } ],
|
||||
"sync_valid": [ { "direction": "in" } ],
|
||||
"sync_data": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"s_axi": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "s_axi",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "16", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "4", "value_src": "constant_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "4", "value_src": "constant_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||
"AWPROT": [ { "physical_name": "s_axi_awprot" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_bready" } ],
|
||||
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
|
||||
"ARPROT": [ { "physical_name": "s_axi_arprot" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
|
||||
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
|
||||
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
|
||||
"RREADY": [ { "physical_name": "s_axi_rready" } ]
|
||||
}
|
||||
},
|
||||
"s_axi_aclk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "s_axi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axi_aclk" } ]
|
||||
}
|
||||
},
|
||||
"s_axi_aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axi_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"spi_engine_ctrl": {
|
||||
"vlnv": "analog.com:interface:spi_engine_ctrl:1.0",
|
||||
"abstraction_type": "analog.com:interface:spi_engine_ctrl_rtl:1.0",
|
||||
"mode": "master",
|
||||
"port_maps": {
|
||||
"CMD_READY": [ { "physical_name": "cmd_ready" } ],
|
||||
"CMD_VALID": [ { "physical_name": "cmd_valid" } ],
|
||||
"CMD_DATA": [ { "physical_name": "cmd_data" } ],
|
||||
"SDO_READY": [ { "physical_name": "sdo_data_ready" } ],
|
||||
"SDO_VALID": [ { "physical_name": "sdo_data_valid" } ],
|
||||
"SDO_DATA": [ { "physical_name": "sdo_data" } ],
|
||||
"SDI_READY": [ { "physical_name": "sdi_data_ready" } ],
|
||||
"SDI_VALID": [ { "physical_name": "sdi_data_valid" } ],
|
||||
"SDI_DATA": [ { "physical_name": "sdi_data" } ],
|
||||
"SYNC_READY": [ { "physical_name": "sync_ready" } ],
|
||||
"SYNC_VALID": [ { "physical_name": "sync_valid" } ],
|
||||
"SYNC_DATA": [ { "physical_name": "sync_data" } ]
|
||||
}
|
||||
},
|
||||
"spi_engine_ctrl_signal_clock": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "spi_engine_ctrl", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "spi_resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "spi_clk" } ]
|
||||
}
|
||||
},
|
||||
"spi_engine_ctrl_signal_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "spi_resetn" } ]
|
||||
}
|
||||
},
|
||||
"spi_engine_offload_ctrl0_s_axi_signal_clock": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "spi_engine_offload_ctrl0:s_axi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axi_aclk" } ]
|
||||
}
|
||||
},
|
||||
"spi_engine_offload_ctrl0_s_axi_signal_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axi_aresetn" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"s_axi": {
|
||||
"address_blocks": {
|
||||
"axi_lite": {
|
||||
"base_address": "0",
|
||||
"range": "65536"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
-6304
File diff suppressed because it is too large
Load Diff
+182
-68
@@ -2,7 +2,7 @@
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_bd_processing_system7_0_0",
|
||||
"cell_name": "processing_system7_0",
|
||||
"cell_name": "processing_system7",
|
||||
"component_reference": "xilinx.com:ip:processing_system7:5.5",
|
||||
"ip_revision": "6",
|
||||
"gen_directory": "../../../../../../duifei_cmos_1t2r.gen/sources_1/bd/system_bd/ip/system_bd_processing_system7_0_0",
|
||||
@@ -18,8 +18,8 @@
|
||||
"PCW_I2C0_HIGHADDR": [ { "value": "0xE0004FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"PCW_I2C1_BASEADDR": [ { "value": "0xE0005000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"PCW_I2C1_HIGHADDR": [ { "value": "0xE0005FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SPI0_BASEADDR": [ { "value": "0xE0006000", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_SPI0_HIGHADDR": [ { "value": "0xE0006FFF", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"PCW_SPI0_BASEADDR": [ { "value": "0xE0006000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SPI0_HIGHADDR": [ { "value": "0xE0006FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SPI1_BASEADDR": [ { "value": "0xE0007000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SPI1_HIGHADDR": [ { "value": "0xE0007FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
"PCW_CAN0_BASEADDR": [ { "value": "0xE0008000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
|
||||
@@ -152,7 +152,7 @@
|
||||
"PCW_ACT_USB1_PERIPHERAL_FREQMHZ": [ { "value": "60", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PCW_ACT_SDIO_PERIPHERAL_FREQMHZ": [ { "value": "10.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PCW_ACT_UART_PERIPHERAL_FREQMHZ": [ { "value": "10.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PCW_ACT_SPI_PERIPHERAL_FREQMHZ": [ { "value": "166.666672", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PCW_ACT_SPI_PERIPHERAL_FREQMHZ": [ { "value": "10.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PCW_ACT_CAN_PERIPHERAL_FREQMHZ": [ { "value": "10.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PCW_ACT_CAN0_PERIPHERAL_FREQMHZ": [ { "value": "23.8095", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PCW_ACT_CAN1_PERIPHERAL_FREQMHZ": [ { "value": "23.8095", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
@@ -179,17 +179,17 @@
|
||||
"PCW_CPU_PERIPHERAL_DIVISOR0": [ { "value": "2", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_DDR_PERIPHERAL_DIVISOR0": [ { "value": "2", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SMC_PERIPHERAL_DIVISOR0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_QSPI_PERIPHERAL_DIVISOR0": [ { "value": "5", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_QSPI_PERIPHERAL_DIVISOR0": [ { "value": "9", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SDIO_PERIPHERAL_DIVISOR0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_UART_PERIPHERAL_DIVISOR0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SPI_PERIPHERAL_DIVISOR0": [ { "value": "6", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SPI_PERIPHERAL_DIVISOR0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_CAN_PERIPHERAL_DIVISOR0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_CAN_PERIPHERAL_DIVISOR1": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_FCLK0_PERIPHERAL_DIVISOR0": [ { "value": "5", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_FCLK0_PERIPHERAL_DIVISOR0": [ { "value": "6", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_FCLK1_PERIPHERAL_DIVISOR0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_FCLK2_PERIPHERAL_DIVISOR0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_FCLK3_PERIPHERAL_DIVISOR0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_FCLK0_PERIPHERAL_DIVISOR1": [ { "value": "2", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_FCLK0_PERIPHERAL_DIVISOR1": [ { "value": "3", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_FCLK1_PERIPHERAL_DIVISOR1": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_FCLK2_PERIPHERAL_DIVISOR1": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_FCLK3_PERIPHERAL_DIVISOR1": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
@@ -200,7 +200,7 @@
|
||||
"PCW_TPIU_PERIPHERAL_DIVISOR0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_DCI_PERIPHERAL_DIVISOR0": [ { "value": "15", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_DCI_PERIPHERAL_DIVISOR1": [ { "value": "7", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_PCAP_PERIPHERAL_DIVISOR0": [ { "value": "5", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_PCAP_PERIPHERAL_DIVISOR0": [ { "value": "9", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
@@ -209,14 +209,14 @@
|
||||
"PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_WDT_PERIPHERAL_DIVISOR0": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_ARMPLL_CTRL_FBDIV": [ { "value": "40", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_IOPLL_CTRL_FBDIV": [ { "value": "30", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_IOPLL_CTRL_FBDIV": [ { "value": "54", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_DDRPLL_CTRL_FBDIV": [ { "value": "32", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_CPU_CPU_PLL_FREQMHZ": [ { "value": "1333.333", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_IO_IO_PLL_FREQMHZ": [ { "value": "1000.000", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_IO_IO_PLL_FREQMHZ": [ { "value": "1800.000", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_DDR_DDR_PLL_FREQMHZ": [ { "value": "1066.667", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SMC_PERIPHERAL_VALID": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_SDIO_PERIPHERAL_VALID": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_SPI_PERIPHERAL_VALID": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_SPI_PERIPHERAL_VALID": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_CAN_PERIPHERAL_VALID": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_UART_PERIPHERAL_VALID": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_CAN0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
@@ -235,7 +235,7 @@
|
||||
"PCW_EN_EMIO_SDIO1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_CD_SDIO1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_WP_SDIO1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_SPI0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_SPI0": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_SPI1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_UART0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_UART1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
@@ -246,7 +246,7 @@
|
||||
"PCW_EN_EMIO_WDT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_EMIO_TRACE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_AXI_NONSECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_M_AXI_GP0": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_M_AXI_GP0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_M_AXI_GP1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_S_AXI_GP0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_S_AXI_GP1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
@@ -255,7 +255,7 @@
|
||||
"PCW_USE_S_AXI_HP1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_S_AXI_HP2": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_S_AXI_HP3": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_M_AXI_GP0_FREQMHZ": [ { "value": "10", "value_permission": "bd", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_M_AXI_GP0_FREQMHZ": [ { "value": "100", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_M_AXI_GP1_FREQMHZ": [ { "value": "10", "value_permission": "bd", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_S_AXI_GP0_FREQMHZ": [ { "value": "10", "value_permission": "bd", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_S_AXI_GP1_FREQMHZ": [ { "value": "10", "value_permission": "bd", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
@@ -287,7 +287,7 @@
|
||||
"PCW_USE_CR_FABRIC": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_AXI_FABRIC_IDLE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_DDR_BYPASS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_FABRIC_INTERRUPT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_FABRIC_INTERRUPT": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_PROC_EVENT_BUS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_EXPANDED_IOP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_USE_HIGH_OCM": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
@@ -303,10 +303,10 @@
|
||||
"PCW_UART0_BAUD_RATE": [ { "value": "115200", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_UART1_BAUD_RATE": [ { "value": "115200", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_EN_4K_TIMER": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_M_AXI_GP0_ID_WIDTH": [ { "value": "12", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_M_AXI_GP0_ENABLE_STATIC_REMAP": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_M_AXI_GP0_SUPPORT_NARROW_BURST": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_M_AXI_GP0_THREAD_ID_WIDTH": [ { "value": "12", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_M_AXI_GP0_ID_WIDTH": [ { "value": "12", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_M_AXI_GP0_ENABLE_STATIC_REMAP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_M_AXI_GP0_SUPPORT_NARROW_BURST": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_M_AXI_GP0_THREAD_ID_WIDTH": [ { "value": "12", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_M_AXI_GP1_ID_WIDTH": [ { "value": "12", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_M_AXI_GP1_ENABLE_STATIC_REMAP": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_M_AXI_GP1_SUPPORT_NARROW_BURST": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
@@ -326,7 +326,7 @@
|
||||
"PCW_S_AXI_HP2_DATA_WIDTH": [ { "value": "64", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_S_AXI_HP3_ID_WIDTH": [ { "value": "6", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_S_AXI_HP3_DATA_WIDTH": [ { "value": "64", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_NUM_F2P_INTR_INPUTS": [ { "value": "1", "value_permission": "bd", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_NUM_F2P_INTR_INPUTS": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_DDR": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_SMC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_QSPI": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
@@ -340,7 +340,7 @@
|
||||
"PCW_EN_PJTAG": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_SDIO0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_SDIO1": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_SPI0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_SPI0": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_SPI1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_UART0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_EN_UART1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
@@ -378,7 +378,7 @@
|
||||
"PCW_P2F_DMAC6_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_DMAC7_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_SMC_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_QSPI_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_QSPI_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_P2F_CTI_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_GPIO_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_USB0_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
@@ -395,12 +395,12 @@
|
||||
"PCW_P2F_SPI1_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_UART1_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_P2F_CAN1_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_IRQ_F2P_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_IRQ_F2P_INTR": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_IRQ_F2P_MODE": [ { "value": "DIRECT", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_CORE0_FIQ_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_CORE0_IRQ_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_CORE1_FIQ_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_CORE1_IRQ_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PCW_CORE0_FIQ_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_CORE0_IRQ_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_CORE1_FIQ_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_CORE1_IRQ_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_VALUE_SILVERSION": [ { "value": "3", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_GP0_EN_MODIFIABLE_TXN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCW_GP1_EN_MODIFIABLE_TXN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
@@ -510,14 +510,14 @@
|
||||
"PCW_UART1_UART1_IO": [ { "value": "<Select>", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_UART1_GRP_FULL_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_UART1_GRP_FULL_IO": [ { "value": "<Select>", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SPI0_PERIPHERAL_ENABLE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_SPI0_SPI0_IO": [ { "value": "EMIO", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_SPI0_GRP_SS0_ENABLE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SPI0_GRP_SS0_IO": [ { "value": "EMIO", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SPI0_GRP_SS1_ENABLE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SPI0_GRP_SS1_IO": [ { "value": "EMIO", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SPI0_GRP_SS2_ENABLE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SPI0_GRP_SS2_IO": [ { "value": "EMIO", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SPI0_PERIPHERAL_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_SPI0_SPI0_IO": [ { "value": "<Select>", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SPI0_GRP_SS0_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SPI0_GRP_SS0_IO": [ { "value": "<Select>", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SPI0_GRP_SS1_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SPI0_GRP_SS1_IO": [ { "value": "<Select>", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SPI0_GRP_SS2_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SPI0_GRP_SS2_IO": [ { "value": "<Select>", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SPI1_PERIPHERAL_ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"PCW_SPI1_SPI1_IO": [ { "value": "<Select>", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"PCW_SPI1_GRP_SS0_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
@@ -927,7 +927,7 @@
|
||||
"C_MIO_PRIMITIVE": [ { "value": "54", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_TRACE_INTERNAL_WIDTH": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_USE_AXI_NONSECURE": [ { "value": "0", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_USE_M_AXI_GP0": [ { "value": "0", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_USE_M_AXI_GP0": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_USE_M_AXI_GP1": [ { "value": "0", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_USE_S_AXI_GP0": [ { "value": "0", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
"C_USE_S_AXI_GP1": [ { "value": "0", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
|
||||
@@ -974,20 +974,46 @@
|
||||
"GPIO_I": [ { "direction": "in", "size_left": "47", "size_right": "0", "driver_value": "0" } ],
|
||||
"GPIO_O": [ { "direction": "out", "size_left": "47", "size_right": "0" } ],
|
||||
"GPIO_T": [ { "direction": "out", "size_left": "47", "size_right": "0" } ],
|
||||
"SPI0_SCLK_I": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"SPI0_SCLK_O": [ { "direction": "out" } ],
|
||||
"SPI0_SCLK_T": [ { "direction": "out" } ],
|
||||
"SPI0_MOSI_I": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"SPI0_MOSI_O": [ { "direction": "out" } ],
|
||||
"SPI0_MOSI_T": [ { "direction": "out" } ],
|
||||
"SPI0_MISO_I": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"SPI0_MISO_O": [ { "direction": "out" } ],
|
||||
"SPI0_MISO_T": [ { "direction": "out" } ],
|
||||
"SPI0_SS_I": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"SPI0_SS_O": [ { "direction": "out" } ],
|
||||
"SPI0_SS1_O": [ { "direction": "out" } ],
|
||||
"SPI0_SS2_O": [ { "direction": "out" } ],
|
||||
"SPI0_SS_T": [ { "direction": "out" } ],
|
||||
"M_AXI_GP0_ARVALID": [ { "direction": "out" } ],
|
||||
"M_AXI_GP0_AWVALID": [ { "direction": "out" } ],
|
||||
"M_AXI_GP0_BREADY": [ { "direction": "out" } ],
|
||||
"M_AXI_GP0_RREADY": [ { "direction": "out" } ],
|
||||
"M_AXI_GP0_WLAST": [ { "direction": "out" } ],
|
||||
"M_AXI_GP0_WVALID": [ { "direction": "out" } ],
|
||||
"M_AXI_GP0_ARID": [ { "direction": "out", "size_left": "11", "size_right": "0" } ],
|
||||
"M_AXI_GP0_AWID": [ { "direction": "out", "size_left": "11", "size_right": "0" } ],
|
||||
"M_AXI_GP0_WID": [ { "direction": "out", "size_left": "11", "size_right": "0" } ],
|
||||
"M_AXI_GP0_ARBURST": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"M_AXI_GP0_ARLOCK": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"M_AXI_GP0_ARSIZE": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"M_AXI_GP0_AWBURST": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"M_AXI_GP0_AWLOCK": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"M_AXI_GP0_AWSIZE": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"M_AXI_GP0_ARPROT": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"M_AXI_GP0_AWPROT": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"M_AXI_GP0_ARADDR": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"M_AXI_GP0_AWADDR": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"M_AXI_GP0_WDATA": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"M_AXI_GP0_ARCACHE": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"M_AXI_GP0_ARLEN": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"M_AXI_GP0_ARQOS": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"M_AXI_GP0_AWCACHE": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"M_AXI_GP0_AWLEN": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"M_AXI_GP0_AWQOS": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"M_AXI_GP0_WSTRB": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"M_AXI_GP0_ACLK": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M_AXI_GP0_ARREADY": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M_AXI_GP0_AWREADY": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M_AXI_GP0_BVALID": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M_AXI_GP0_RLAST": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M_AXI_GP0_RVALID": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M_AXI_GP0_WREADY": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"M_AXI_GP0_BID": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0" } ],
|
||||
"M_AXI_GP0_RID": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0" } ],
|
||||
"M_AXI_GP0_BRESP": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"M_AXI_GP0_RRESP": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"M_AXI_GP0_RDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"IRQ_F2P": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"FCLK_CLK0": [ { "direction": "out" } ],
|
||||
"FCLK_RESET0_N": [ { "direction": "out" } ],
|
||||
"MIO": [ { "direction": "inout", "size_left": "53", "size_right": "0" } ],
|
||||
@@ -1077,25 +1103,83 @@
|
||||
"PS_PORB": [ { "physical_name": "PS_PORB" } ]
|
||||
}
|
||||
},
|
||||
"SPI_0": {
|
||||
"vlnv": "xilinx.com:interface:spi:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:spi_rtl:1.0",
|
||||
"M_AXI_GP0": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "master",
|
||||
"address_space_ref": "Data",
|
||||
"parameters": {
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI3", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "12", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "16", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "4", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "4", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"SCK_I": [ { "physical_name": "SPI0_SCLK_I" } ],
|
||||
"SCK_O": [ { "physical_name": "SPI0_SCLK_O" } ],
|
||||
"SCK_T": [ { "physical_name": "SPI0_SCLK_T" } ],
|
||||
"IO0_I": [ { "physical_name": "SPI0_MOSI_I" } ],
|
||||
"IO0_O": [ { "physical_name": "SPI0_MOSI_O" } ],
|
||||
"IO0_T": [ { "physical_name": "SPI0_MOSI_T" } ],
|
||||
"IO1_I": [ { "physical_name": "SPI0_MISO_I" } ],
|
||||
"IO1_O": [ { "physical_name": "SPI0_MISO_O" } ],
|
||||
"IO1_T": [ { "physical_name": "SPI0_MISO_T" } ],
|
||||
"SS_I": [ { "physical_name": "SPI0_SS_I" } ],
|
||||
"SS_O": [ { "physical_name": "SPI0_SS_O" } ],
|
||||
"SS1_O": [ { "physical_name": "SPI0_SS1_O" } ],
|
||||
"SS2_O": [ { "physical_name": "SPI0_SS2_O" } ],
|
||||
"SS_T": [ { "physical_name": "SPI0_SS_T" } ]
|
||||
"ARVALID": [ { "physical_name": "M_AXI_GP0_ARVALID" } ],
|
||||
"AWVALID": [ { "physical_name": "M_AXI_GP0_AWVALID" } ],
|
||||
"BREADY": [ { "physical_name": "M_AXI_GP0_BREADY" } ],
|
||||
"RREADY": [ { "physical_name": "M_AXI_GP0_RREADY" } ],
|
||||
"WLAST": [ { "physical_name": "M_AXI_GP0_WLAST" } ],
|
||||
"WVALID": [ { "physical_name": "M_AXI_GP0_WVALID" } ],
|
||||
"ARID": [ { "physical_name": "M_AXI_GP0_ARID" } ],
|
||||
"AWID": [ { "physical_name": "M_AXI_GP0_AWID" } ],
|
||||
"WID": [ { "physical_name": "M_AXI_GP0_WID" } ],
|
||||
"ARBURST": [ { "physical_name": "M_AXI_GP0_ARBURST" } ],
|
||||
"ARLOCK": [ { "physical_name": "M_AXI_GP0_ARLOCK" } ],
|
||||
"ARSIZE": [ { "physical_name": "M_AXI_GP0_ARSIZE" } ],
|
||||
"AWBURST": [ { "physical_name": "M_AXI_GP0_AWBURST" } ],
|
||||
"AWLOCK": [ { "physical_name": "M_AXI_GP0_AWLOCK" } ],
|
||||
"AWSIZE": [ { "physical_name": "M_AXI_GP0_AWSIZE" } ],
|
||||
"ARPROT": [ { "physical_name": "M_AXI_GP0_ARPROT" } ],
|
||||
"AWPROT": [ { "physical_name": "M_AXI_GP0_AWPROT" } ],
|
||||
"ARADDR": [ { "physical_name": "M_AXI_GP0_ARADDR" } ],
|
||||
"AWADDR": [ { "physical_name": "M_AXI_GP0_AWADDR" } ],
|
||||
"WDATA": [ { "physical_name": "M_AXI_GP0_WDATA" } ],
|
||||
"ARCACHE": [ { "physical_name": "M_AXI_GP0_ARCACHE" } ],
|
||||
"ARLEN": [ { "physical_name": "M_AXI_GP0_ARLEN" } ],
|
||||
"ARQOS": [ { "physical_name": "M_AXI_GP0_ARQOS" } ],
|
||||
"AWCACHE": [ { "physical_name": "M_AXI_GP0_AWCACHE" } ],
|
||||
"AWLEN": [ { "physical_name": "M_AXI_GP0_AWLEN" } ],
|
||||
"AWQOS": [ { "physical_name": "M_AXI_GP0_AWQOS" } ],
|
||||
"WSTRB": [ { "physical_name": "M_AXI_GP0_WSTRB" } ],
|
||||
"ARREADY": [ { "physical_name": "M_AXI_GP0_ARREADY" } ],
|
||||
"AWREADY": [ { "physical_name": "M_AXI_GP0_AWREADY" } ],
|
||||
"BVALID": [ { "physical_name": "M_AXI_GP0_BVALID" } ],
|
||||
"RLAST": [ { "physical_name": "M_AXI_GP0_RLAST" } ],
|
||||
"RVALID": [ { "physical_name": "M_AXI_GP0_RVALID" } ],
|
||||
"WREADY": [ { "physical_name": "M_AXI_GP0_WREADY" } ],
|
||||
"BID": [ { "physical_name": "M_AXI_GP0_BID" } ],
|
||||
"RID": [ { "physical_name": "M_AXI_GP0_RID" } ],
|
||||
"BRESP": [ { "physical_name": "M_AXI_GP0_BRESP" } ],
|
||||
"RRESP": [ { "physical_name": "M_AXI_GP0_RRESP" } ],
|
||||
"RDATA": [ { "physical_name": "M_AXI_GP0_RDATA" } ]
|
||||
}
|
||||
},
|
||||
"FCLK_CLK0": {
|
||||
@@ -1127,6 +1211,36 @@
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "FCLK_RESET0_N" } ]
|
||||
}
|
||||
},
|
||||
"IRQ_F2P": {
|
||||
"vlnv": "xilinx.com:signal:interrupt:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"PortWidth": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"INTERRUPT": [ { "physical_name": "IRQ_F2P" } ]
|
||||
}
|
||||
},
|
||||
"M_AXI_GP0_ACLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "M_AXI_GP0", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "M_AXI_GP0_ACLK" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"address_spaces": {
|
||||
|
||||
+352
@@ -0,0 +1,352 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_bd_ps7_axi_periph_0",
|
||||
"cell_name": "ps7_axi_periph",
|
||||
"component_reference": "xilinx.com:ip:axi_interconnect:2.1",
|
||||
"ip_revision": "31",
|
||||
"gen_directory": "../../../../../../duifei_cmos_1t2r.gen/sources_1/bd/system_bd/ip/system_bd_ps7_axi_periph_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"NUM_SI": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_MI": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"STRATEGY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ENABLE_ADVANCED_OPTIONS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ENABLE_PROTOCOL_CHECKERS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
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}
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}
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}
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||||
+195
@@ -0,0 +1,195 @@
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||||
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|
||||
"Component_Name": [ { "value": "system_bd_rst_ps7_100M_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_EXT_RST_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AUX_RST_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EXT_RESET_HIGH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AUX_RESET_HIGH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_BUS_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_PERP_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_INTERCONNECT_ARESETN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_PERP_ARESETN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z100" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "14" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../duifei_cmos_1t2r.gen/sources_1/bd/system_bd/ip/system_bd_rst_ps7_100M_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.2.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"slowest_sync_clk": [ { "direction": "in" } ],
|
||||
"ext_reset_in": [ { "direction": "in" } ],
|
||||
"aux_reset_in": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"mb_debug_sys_rst": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"dcm_locked": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"mb_reset": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||
"bus_struct_reset": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"peripheral_reset": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"interconnect_aresetn": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "1" } ],
|
||||
"peripheral_aresetn": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "1" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"clock": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_RESET": [ { "value": "mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "slowest_sync_clk" } ]
|
||||
}
|
||||
},
|
||||
"ext_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"BOARD.ASSOCIATED_PARAM": [ { "value": "RESET_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "ext_reset_in" } ]
|
||||
}
|
||||
},
|
||||
"aux_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aux_reset_in" } ]
|
||||
}
|
||||
},
|
||||
"dbg_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "mb_debug_sys_rst" } ]
|
||||
}
|
||||
},
|
||||
"mb_rst": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"TYPE": [ { "value": "PROCESSOR", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "mb_reset" } ]
|
||||
}
|
||||
},
|
||||
"bus_struct_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"TYPE": [ { "value": "INTERCONNECT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "bus_struct_reset" } ]
|
||||
}
|
||||
},
|
||||
"interconnect_low_rst": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"TYPE": [ { "value": "INTERCONNECT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "interconnect_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"peripheral_high_rst": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"TYPE": [ { "value": "PERIPHERAL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "peripheral_reset" } ]
|
||||
}
|
||||
},
|
||||
"peripheral_low_rst": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"TYPE": [ { "value": "PERIPHERAL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "peripheral_aresetn" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+175
@@ -0,0 +1,175 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_bd_spi_engine_execution_0_0",
|
||||
"cell_name": "spi_engine/spi_engine_execution",
|
||||
"component_reference": "analog.com:user:spi_engine_execution:1.0",
|
||||
"ip_revision": "1",
|
||||
"gen_directory": "../../../../../../duifei_cmos_1t2r.gen/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"NUM_OF_CS": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DEFAULT_SPI_CFG": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DEFAULT_CLK_DIV": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_OF_SDI": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SDO_DEFAULT": [ { "value": "\"0\"", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"ECHO_SCLK": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SDI_DELAY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_bd_spi_engine_execution_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"NUM_OF_CS": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DEFAULT_SPI_CFG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DEFAULT_CLK_DIV": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"NUM_OF_SDI": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SDO_DEFAULT": [ { "value": "\"0\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"ECHO_SCLK": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"SDI_DELAY": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z100" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "1" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../duifei_cmos_1t2r.gen/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.2.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clk": [ { "direction": "in" } ],
|
||||
"resetn": [ { "direction": "in" } ],
|
||||
"active": [ { "direction": "out" } ],
|
||||
"cmd_ready": [ { "direction": "out" } ],
|
||||
"cmd_valid": [ { "direction": "in" } ],
|
||||
"cmd": [ { "direction": "in", "size_left": "15", "size_right": "0" } ],
|
||||
"sdo_data_valid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"sdo_data_ready": [ { "direction": "out" } ],
|
||||
"sdo_data": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"sdi_data_ready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"sdi_data_valid": [ { "direction": "out" } ],
|
||||
"sdi_data": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||
"sync_ready": [ { "direction": "in" } ],
|
||||
"sync_valid": [ { "direction": "out" } ],
|
||||
"sync": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||
"sclk": [ { "direction": "out" } ],
|
||||
"sdo": [ { "direction": "out" } ],
|
||||
"sdo_t": [ { "direction": "out" } ],
|
||||
"sdi": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"cs": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"three_wire": [ { "direction": "out" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"ctrl": {
|
||||
"vlnv": "analog.com:interface:spi_engine_ctrl:1.0",
|
||||
"abstraction_type": "analog.com:interface:spi_engine_ctrl_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"port_maps": {
|
||||
"CMD_READY": [ { "physical_name": "cmd_ready" } ],
|
||||
"CMD_VALID": [ { "physical_name": "cmd_valid" } ],
|
||||
"CMD_DATA": [ { "physical_name": "cmd" } ],
|
||||
"SDO_READY": [ { "physical_name": "sdo_data_ready" } ],
|
||||
"SDO_VALID": [ { "physical_name": "sdo_data_valid" } ],
|
||||
"SDO_DATA": [ { "physical_name": "sdo_data" } ],
|
||||
"SDI_READY": [ { "physical_name": "sdi_data_ready" } ],
|
||||
"SDI_VALID": [ { "physical_name": "sdi_data_valid" } ],
|
||||
"SDI_DATA": [ { "physical_name": "sdi_data" } ],
|
||||
"SYNC_READY": [ { "physical_name": "sync_ready" } ],
|
||||
"SYNC_VALID": [ { "physical_name": "sync_valid" } ],
|
||||
"SYNC_DATA": [ { "physical_name": "sync" } ]
|
||||
}
|
||||
},
|
||||
"ctrl_signal_clock": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "ctrl", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "clk" } ]
|
||||
}
|
||||
},
|
||||
"ctrl_signal_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "resetn" } ]
|
||||
}
|
||||
},
|
||||
"spi": {
|
||||
"vlnv": "analog.com:interface:spi_master:1.0",
|
||||
"abstraction_type": "analog.com:interface:spi_master_rtl:1.0",
|
||||
"mode": "master",
|
||||
"port_maps": {
|
||||
"SCLK": [ { "physical_name": "sclk" } ],
|
||||
"SDI": [ { "physical_name": "sdi" } ],
|
||||
"SDO": [ { "physical_name": "sdo" } ],
|
||||
"SDO_T": [ { "physical_name": "sdo_t" } ],
|
||||
"THREE_WIRE": [ { "physical_name": "three_wire" } ],
|
||||
"CS": [ { "physical_name": "cs" } ]
|
||||
}
|
||||
},
|
||||
"spi_signal_clock": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "spi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "clk" } ]
|
||||
}
|
||||
},
|
||||
"spi_signal_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "resetn" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+306
@@ -0,0 +1,306 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_bd_xlconcat_0_0",
|
||||
"cell_name": "xlconcat_irq",
|
||||
"component_reference": "xilinx.com:ip:xlconcat:2.1",
|
||||
"ip_revision": "5",
|
||||
"gen_directory": "../../../../../../duifei_cmos_1t2r.gen/sources_1/bd/system_bd/ip/system_bd_xlconcat_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "system_bd_xlconcat_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"NUM_PORTS": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN0_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN1_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN2_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN3_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN4_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN5_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN6_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN7_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN8_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN9_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN10_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN11_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN12_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN13_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN14_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN15_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN16_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN17_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN18_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN19_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN20_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN21_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN22_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN23_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN24_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN25_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN26_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN27_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN28_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN29_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN30_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN31_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN32_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN33_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN34_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN35_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN36_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN37_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN38_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN39_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN40_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN41_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN42_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN43_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN44_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN45_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN46_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN47_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN48_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN49_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN50_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN51_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN52_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN53_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN54_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN55_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN56_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN57_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN58_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN59_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN60_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN61_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN62_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN63_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN64_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN65_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN66_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN67_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN68_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN69_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN70_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN71_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN72_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN73_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN74_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN75_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN76_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN77_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN78_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN79_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN80_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN81_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN82_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN83_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN84_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN85_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN86_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN87_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN88_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN89_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN90_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN91_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN92_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN93_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN94_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN95_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN96_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN97_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"SWVERSION": [ { "value": "2023.2.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"In0": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"dout": [ { "direction": "out", "size_left": "0", "size_right": "0" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
-49
@@ -1,49 +0,0 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_bd_xlconstant_0_0",
|
||||
"cell_name": "xlconstant_vcc",
|
||||
"component_reference": "xilinx.com:ip:xlconstant:1.1",
|
||||
"ip_revision": "8",
|
||||
"gen_directory": "../../../../../../duifei_cmos_1t2r.gen/sources_1/bd/system_bd/ip/system_bd_xlconstant_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "system_bd_xlconstant_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"CONST_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CONST_VAL": [ { "value": "1", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"CONST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"CONST_VAL": [ { "value": "0x1", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z100" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "8" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../duifei_cmos_1t2r.gen/sources_1/bd/system_bd/ip/system_bd_xlconstant_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.2.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"dout": [ { "direction": "out", "size_left": "0", "size_right": "0" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+605
-106
@@ -1,7 +1,7 @@
|
||||
{
|
||||
"design": {
|
||||
"design_info": {
|
||||
"boundary_crc": "0xA2DC993BA9BF7C0",
|
||||
"boundary_crc": "0x5FBD1CCA8A8679DB",
|
||||
"device": "xc7z100ffg900-2",
|
||||
"gen_directory": "../../../../duifei_cmos_1t2r.gen/sources_1/bd/system_bd",
|
||||
"name": "system_bd",
|
||||
@@ -11,9 +11,18 @@
|
||||
"validated": "true"
|
||||
},
|
||||
"design_tree": {
|
||||
"processing_system7_0": "",
|
||||
"xlconstant_vcc": "",
|
||||
"ila_spi": ""
|
||||
"processing_system7": "",
|
||||
"axi_spi_engine": {
|
||||
"axi_spi_engine": "",
|
||||
"spi_engine_execution": ""
|
||||
},
|
||||
"ps7_axi_periph": {
|
||||
"s00_couplers": {
|
||||
"auto_pc": ""
|
||||
}
|
||||
},
|
||||
"rst_ps7_100M": "",
|
||||
"xlconcat_irq": ""
|
||||
},
|
||||
"interface_ports": {
|
||||
"DDR": {
|
||||
@@ -183,50 +192,70 @@
|
||||
"direction": "IO"
|
||||
}
|
||||
}
|
||||
},
|
||||
"spi": {
|
||||
"mode": "Master",
|
||||
"vlnv_bus_definition": "analog.com:interface:spi_master:1.0",
|
||||
"vlnv": "analog.com:interface:spi_master_rtl:1.0",
|
||||
"port_maps": {
|
||||
"SCLK": {
|
||||
"physical_name": "spi_sclk",
|
||||
"direction": "O"
|
||||
},
|
||||
"SDI": {
|
||||
"physical_name": "spi_sdi",
|
||||
"direction": "I",
|
||||
"left": "0",
|
||||
"right": "0"
|
||||
},
|
||||
"SDO": {
|
||||
"physical_name": "spi_sdo",
|
||||
"direction": "O"
|
||||
},
|
||||
"SDO_T": {
|
||||
"physical_name": "spi_sdo_t",
|
||||
"direction": "O"
|
||||
},
|
||||
"THREE_WIRE": {
|
||||
"physical_name": "spi_three_wire",
|
||||
"direction": "O"
|
||||
},
|
||||
"CS": {
|
||||
"physical_name": "spi_cs",
|
||||
"direction": "O",
|
||||
"left": "2",
|
||||
"right": "0"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"ports": {
|
||||
"SPI0_SS_O_0": {
|
||||
"direction": "O"
|
||||
},
|
||||
"SPI0_SS1_O_0": {
|
||||
"direction": "O"
|
||||
},
|
||||
"SPI0_SS2_O_0": {
|
||||
"direction": "O"
|
||||
},
|
||||
"SPI0_SCLK_O_0": {
|
||||
"direction": "O"
|
||||
},
|
||||
"SPI0_MOSI_O_0": {
|
||||
"direction": "O"
|
||||
},
|
||||
"SPI0_MISO_I_0": {
|
||||
"direction": "I"
|
||||
},
|
||||
"GPIO_O_0": {
|
||||
"GPIO_O": {
|
||||
"direction": "O",
|
||||
"left": "47",
|
||||
"right": "0"
|
||||
},
|
||||
"GPIO_I_0": {
|
||||
"GPIO_I": {
|
||||
"direction": "I",
|
||||
"left": "47",
|
||||
"right": "0"
|
||||
},
|
||||
"GPIO_T_0": {
|
||||
"GPIO_T": {
|
||||
"direction": "O",
|
||||
"left": "47",
|
||||
"right": "0"
|
||||
},
|
||||
"spi_active": {
|
||||
"direction": "O"
|
||||
}
|
||||
},
|
||||
"components": {
|
||||
"processing_system7_0": {
|
||||
"processing_system7": {
|
||||
"vlnv": "xilinx.com:ip:processing_system7:5.5",
|
||||
"ip_revision": "6",
|
||||
"xci_name": "system_bd_processing_system7_0_0",
|
||||
"xci_path": "ip/system_bd_processing_system7_0_0/system_bd_processing_system7_0_0.xci",
|
||||
"inst_hier_path": "processing_system7_0",
|
||||
"inst_hier_path": "processing_system7",
|
||||
"parameters": {
|
||||
"PCW_ACT_APU_PERIPHERAL_FREQMHZ": {
|
||||
"value": "666.666687"
|
||||
@@ -268,7 +297,7 @@
|
||||
"value": "10.000000"
|
||||
},
|
||||
"PCW_ACT_SPI_PERIPHERAL_FREQMHZ": {
|
||||
"value": "166.666672"
|
||||
"value": "10.000000"
|
||||
},
|
||||
"PCW_ACT_TPIU_PERIPHERAL_FREQMHZ": {
|
||||
"value": "200.000000"
|
||||
@@ -322,7 +351,7 @@
|
||||
"value": "0"
|
||||
},
|
||||
"PCW_EN_EMIO_SPI0": {
|
||||
"value": "1"
|
||||
"value": "0"
|
||||
},
|
||||
"PCW_EN_EMIO_WP_SDIO1": {
|
||||
"value": "0"
|
||||
@@ -334,7 +363,7 @@
|
||||
"value": "0"
|
||||
},
|
||||
"PCW_EN_SPI0": {
|
||||
"value": "1"
|
||||
"value": "0"
|
||||
},
|
||||
"PCW_FPGA0_PERIPHERAL_FREQMHZ": {
|
||||
"value": "100"
|
||||
@@ -351,6 +380,9 @@
|
||||
"PCW_GPIO_EMIO_GPIO_WIDTH": {
|
||||
"value": "48"
|
||||
},
|
||||
"PCW_IRQ_F2P_INTR": {
|
||||
"value": "1"
|
||||
},
|
||||
"PCW_MIO_1_IOTYPE": {
|
||||
"value": "LVCMOS 3.3V"
|
||||
},
|
||||
@@ -433,16 +465,13 @@
|
||||
"value": "x4"
|
||||
},
|
||||
"PCW_SPI0_PERIPHERAL_ENABLE": {
|
||||
"value": "1"
|
||||
},
|
||||
"PCW_SPI0_SPI0_IO": {
|
||||
"value": "EMIO"
|
||||
"value": "0"
|
||||
},
|
||||
"PCW_SPI_PERIPHERAL_FREQMHZ": {
|
||||
"value": "166.666666"
|
||||
},
|
||||
"PCW_SPI_PERIPHERAL_VALID": {
|
||||
"value": "1"
|
||||
"value": "0"
|
||||
},
|
||||
"PCW_UIPARAM_ACT_DDR_FREQ_MHZ": {
|
||||
"value": "533.333374"
|
||||
@@ -456,133 +485,603 @@
|
||||
"PCW_UIPARAM_DDR_PARTNO": {
|
||||
"value": "MT41J256M16 RE-125"
|
||||
},
|
||||
"PCW_USE_FABRIC_INTERRUPT": {
|
||||
"value": "1"
|
||||
},
|
||||
"PCW_USE_M_AXI_GP0": {
|
||||
"value": "0"
|
||||
"value": "1"
|
||||
}
|
||||
},
|
||||
"interface_ports": {
|
||||
"M_AXI_GP0": {
|
||||
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "Master",
|
||||
"address_space_ref": "Data",
|
||||
"base_address": {
|
||||
"minimum": "0x40000000",
|
||||
"maximum": "0x7FFFFFFF",
|
||||
"width": "32"
|
||||
}
|
||||
}
|
||||
},
|
||||
"addressing": {
|
||||
"address_spaces": {
|
||||
"Data": {
|
||||
"range": "4G",
|
||||
"width": "32",
|
||||
"local_memory_map": {
|
||||
"name": "Data",
|
||||
"description": "Address Space Segments",
|
||||
"address_blocks": {
|
||||
"segment1": {
|
||||
"name": "segment1",
|
||||
"display_name": "segment1",
|
||||
"base_address": "0x00000000",
|
||||
"range": "256K",
|
||||
"width": "18",
|
||||
"usage": "register"
|
||||
},
|
||||
"segment2": {
|
||||
"name": "segment2",
|
||||
"display_name": "segment2",
|
||||
"base_address": "0x00040000",
|
||||
"range": "256K",
|
||||
"width": "19",
|
||||
"usage": "register"
|
||||
},
|
||||
"segment3": {
|
||||
"name": "segment3",
|
||||
"display_name": "segment3",
|
||||
"base_address": "0x00080000",
|
||||
"range": "512K",
|
||||
"width": "20",
|
||||
"usage": "register"
|
||||
},
|
||||
"segment4": {
|
||||
"name": "segment4",
|
||||
"display_name": "segment4",
|
||||
"base_address": "0x00100000",
|
||||
"range": "1023M",
|
||||
"width": "30",
|
||||
"usage": "register"
|
||||
},
|
||||
"M_AXI_GP0": {
|
||||
"name": "M_AXI_GP0",
|
||||
"display_name": "M_AXI_GP0",
|
||||
"base_address": "0x40000000",
|
||||
"range": "1G",
|
||||
"width": "31",
|
||||
"usage": "register"
|
||||
},
|
||||
"M_AXI_GP1": {
|
||||
"name": "M_AXI_GP1",
|
||||
"display_name": "M_AXI_GP1",
|
||||
"base_address": "0x80000000",
|
||||
"range": "1G",
|
||||
"width": "32",
|
||||
"usage": "register"
|
||||
},
|
||||
"IO_Peripheral_Registers": {
|
||||
"name": "IO_Peripheral_Registers",
|
||||
"display_name": "IO Peripheral Registers",
|
||||
"base_address": "0xE0000000",
|
||||
"range": "3M",
|
||||
"width": "32",
|
||||
"usage": "register"
|
||||
},
|
||||
"SMC_Memories": {
|
||||
"name": "SMC_Memories",
|
||||
"display_name": "SMC Memories",
|
||||
"base_address": "0xE1000000",
|
||||
"range": "80M",
|
||||
"width": "32",
|
||||
"usage": "register"
|
||||
},
|
||||
"SLCR_Registers": {
|
||||
"name": "SLCR_Registers",
|
||||
"display_name": "SLCR Registers",
|
||||
"base_address": "0xF8000000",
|
||||
"range": "3K",
|
||||
"width": "32",
|
||||
"usage": "register"
|
||||
},
|
||||
"PS_System_Registers": {
|
||||
"name": "PS_System_Registers",
|
||||
"display_name": "PS System Registers",
|
||||
"base_address": "0xF8001000",
|
||||
"range": "8252K",
|
||||
"width": "32",
|
||||
"usage": "register"
|
||||
},
|
||||
"CPU_Private_Registers": {
|
||||
"name": "CPU_Private_Registers",
|
||||
"display_name": "CPU Private Registers",
|
||||
"base_address": "0xF8900000",
|
||||
"range": "6156K",
|
||||
"width": "32",
|
||||
"usage": "register"
|
||||
},
|
||||
"segment5": {
|
||||
"name": "segment5",
|
||||
"display_name": "segment5",
|
||||
"base_address": "0xFC000000",
|
||||
"range": "32M",
|
||||
"width": "32",
|
||||
"usage": "register"
|
||||
},
|
||||
"segment6": {
|
||||
"name": "segment6",
|
||||
"display_name": "segment6",
|
||||
"base_address": "0xFFFC0000",
|
||||
"range": "256K",
|
||||
"width": "32",
|
||||
"usage": "register"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"xlconstant_vcc": {
|
||||
"vlnv": "xilinx.com:ip:xlconstant:1.1",
|
||||
"ip_revision": "8",
|
||||
"xci_name": "system_bd_xlconstant_0_0",
|
||||
"xci_path": "ip/system_bd_xlconstant_0_0/system_bd_xlconstant_0_0.xci",
|
||||
"inst_hier_path": "xlconstant_vcc"
|
||||
"axi_spi_engine": {
|
||||
"interface_ports": {
|
||||
"s_axi": {
|
||||
"mode": "Slave",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
|
||||
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
||||
},
|
||||
"spi": {
|
||||
"mode": "Master",
|
||||
"vlnv_bus_definition": "analog.com:interface:spi_master:1.0",
|
||||
"vlnv": "analog.com:interface:spi_master_rtl:1.0"
|
||||
}
|
||||
},
|
||||
"ports": {
|
||||
"irq": {
|
||||
"direction": "O"
|
||||
},
|
||||
"s_axi_aclk": {
|
||||
"type": "clk",
|
||||
"direction": "I"
|
||||
},
|
||||
"s_axi_aresetn": {
|
||||
"type": "rst",
|
||||
"direction": "I"
|
||||
},
|
||||
"spi_clk": {
|
||||
"type": "clk",
|
||||
"direction": "I"
|
||||
},
|
||||
"active": {
|
||||
"direction": "O"
|
||||
}
|
||||
},
|
||||
"components": {
|
||||
"axi_spi_engine": {
|
||||
"vlnv": "analog.com:user:axi_spi_engine:1.0",
|
||||
"ip_revision": "1",
|
||||
"xci_name": "system_bd_axi_spi_engine_0_0",
|
||||
"xci_path": "ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xci",
|
||||
"inst_hier_path": "axi_spi_engine/axi_spi_engine"
|
||||
},
|
||||
"spi_engine_execution": {
|
||||
"vlnv": "analog.com:user:spi_engine_execution:1.0",
|
||||
"ip_revision": "1",
|
||||
"xci_name": "system_bd_spi_engine_execution_0_0",
|
||||
"xci_path": "ip/system_bd_spi_engine_execution_0_0/system_bd_spi_engine_execution_0_0.xci",
|
||||
"inst_hier_path": "axi_spi_engine/spi_engine_execution",
|
||||
"parameters": {
|
||||
"NUM_OF_CS": {
|
||||
"value": "3"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"interface_nets": {
|
||||
"Conn1": {
|
||||
"interface_ports": [
|
||||
"axi_spi_engine/s_axi",
|
||||
"s_axi"
|
||||
]
|
||||
},
|
||||
"Conn2": {
|
||||
"interface_ports": [
|
||||
"spi_engine_execution/spi",
|
||||
"spi"
|
||||
]
|
||||
},
|
||||
"axi_spi_engine_spi_engine_ctrl": {
|
||||
"interface_ports": [
|
||||
"axi_spi_engine/spi_engine_ctrl",
|
||||
"spi_engine_execution/ctrl"
|
||||
]
|
||||
}
|
||||
},
|
||||
"nets": {
|
||||
"axi_spi_engine_irq": {
|
||||
"ports": [
|
||||
"axi_spi_engine/irq",
|
||||
"irq"
|
||||
]
|
||||
},
|
||||
"axi_spi_engine_spi_resetn": {
|
||||
"ports": [
|
||||
"axi_spi_engine/spi_resetn",
|
||||
"spi_engine_execution/resetn"
|
||||
]
|
||||
},
|
||||
"s_axi_aclk_0_1": {
|
||||
"ports": [
|
||||
"s_axi_aclk",
|
||||
"axi_spi_engine/s_axi_aclk"
|
||||
]
|
||||
},
|
||||
"s_axi_aresetn_1": {
|
||||
"ports": [
|
||||
"s_axi_aresetn",
|
||||
"axi_spi_engine/s_axi_aresetn"
|
||||
]
|
||||
},
|
||||
"spi_clk_0_1": {
|
||||
"ports": [
|
||||
"spi_clk",
|
||||
"axi_spi_engine/spi_clk",
|
||||
"spi_engine_execution/clk"
|
||||
]
|
||||
},
|
||||
"spi_engine_execution_active": {
|
||||
"ports": [
|
||||
"spi_engine_execution/active",
|
||||
"active"
|
||||
]
|
||||
}
|
||||
}
|
||||
},
|
||||
"ila_spi": {
|
||||
"vlnv": "xilinx.com:ip:ila:6.2",
|
||||
"ip_revision": "14",
|
||||
"xci_name": "system_bd_ila_0_0",
|
||||
"xci_path": "ip/system_bd_ila_0_0/system_bd_ila_0_0.xci",
|
||||
"inst_hier_path": "ila_spi",
|
||||
"ps7_axi_periph": {
|
||||
"vlnv": "xilinx.com:ip:axi_interconnect:2.1",
|
||||
"xci_path": "ip/system_bd_ps7_axi_periph_0/system_bd_ps7_axi_periph_0.xci",
|
||||
"inst_hier_path": "ps7_axi_periph",
|
||||
"xci_name": "system_bd_ps7_axi_periph_0",
|
||||
"parameters": {
|
||||
"ALL_PROBE_SAME_MU_CNT": {
|
||||
"value": "6"
|
||||
},
|
||||
"C_ADV_TRIGGER": {
|
||||
"value": "true"
|
||||
},
|
||||
"C_DATA_DEPTH": {
|
||||
"value": "16384"
|
||||
},
|
||||
"C_EN_STRG_QUAL": {
|
||||
"NUM_MI": {
|
||||
"value": "1"
|
||||
}
|
||||
},
|
||||
"interface_ports": {
|
||||
"S00_AXI": {
|
||||
"mode": "Slave",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
|
||||
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
||||
},
|
||||
"C_MONITOR_TYPE": {
|
||||
"value": "Native"
|
||||
"M00_AXI": {
|
||||
"mode": "Master",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
|
||||
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
||||
}
|
||||
},
|
||||
"ports": {
|
||||
"ACLK": {
|
||||
"type": "clk",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"ASSOCIATED_RESET": {
|
||||
"value": "ARESETN"
|
||||
}
|
||||
}
|
||||
},
|
||||
"C_NUM_OF_PROBES": {
|
||||
"value": "6"
|
||||
"ARESETN": {
|
||||
"type": "rst",
|
||||
"direction": "I"
|
||||
},
|
||||
"S00_ACLK": {
|
||||
"type": "clk",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": {
|
||||
"value": "S00_AXI"
|
||||
},
|
||||
"ASSOCIATED_RESET": {
|
||||
"value": "S00_ARESETN"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S00_ARESETN": {
|
||||
"type": "rst",
|
||||
"direction": "I"
|
||||
},
|
||||
"M00_ACLK": {
|
||||
"type": "clk",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": {
|
||||
"value": "M00_AXI"
|
||||
},
|
||||
"ASSOCIATED_RESET": {
|
||||
"value": "M00_ARESETN"
|
||||
}
|
||||
}
|
||||
},
|
||||
"M00_ARESETN": {
|
||||
"type": "rst",
|
||||
"direction": "I"
|
||||
}
|
||||
},
|
||||
"components": {
|
||||
"s00_couplers": {
|
||||
"interface_ports": {
|
||||
"M_AXI": {
|
||||
"mode": "Master",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
|
||||
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
||||
},
|
||||
"S_AXI": {
|
||||
"mode": "Slave",
|
||||
"vlnv_bus_definition": "xilinx.com:interface:aximm:1.0",
|
||||
"vlnv": "xilinx.com:interface:aximm_rtl:1.0"
|
||||
}
|
||||
},
|
||||
"ports": {
|
||||
"M_ACLK": {
|
||||
"type": "clk",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": {
|
||||
"value": "M_AXI"
|
||||
},
|
||||
"ASSOCIATED_RESET": {
|
||||
"value": "M_ARESETN"
|
||||
}
|
||||
}
|
||||
},
|
||||
"M_ARESETN": {
|
||||
"type": "rst",
|
||||
"direction": "I"
|
||||
},
|
||||
"S_ACLK": {
|
||||
"type": "clk",
|
||||
"direction": "I",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": {
|
||||
"value": "S_AXI"
|
||||
},
|
||||
"ASSOCIATED_RESET": {
|
||||
"value": "S_ARESETN"
|
||||
}
|
||||
}
|
||||
},
|
||||
"S_ARESETN": {
|
||||
"type": "rst",
|
||||
"direction": "I"
|
||||
}
|
||||
},
|
||||
"components": {
|
||||
"auto_pc": {
|
||||
"vlnv": "xilinx.com:ip:axi_protocol_converter:2.1",
|
||||
"ip_revision": "30",
|
||||
"xci_name": "system_bd_auto_pc_0",
|
||||
"xci_path": "ip/system_bd_auto_pc_0/system_bd_auto_pc_0.xci",
|
||||
"inst_hier_path": "ps7_axi_periph/s00_couplers/auto_pc",
|
||||
"parameters": {
|
||||
"MI_PROTOCOL": {
|
||||
"value": "AXI4LITE"
|
||||
},
|
||||
"SI_PROTOCOL": {
|
||||
"value": "AXI3"
|
||||
}
|
||||
},
|
||||
"interface_ports": {
|
||||
"S_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "Slave",
|
||||
"bridges": [
|
||||
"M_AXI"
|
||||
]
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"interface_nets": {
|
||||
"auto_pc_to_s00_couplers": {
|
||||
"interface_ports": [
|
||||
"M_AXI",
|
||||
"auto_pc/M_AXI"
|
||||
]
|
||||
},
|
||||
"s00_couplers_to_auto_pc": {
|
||||
"interface_ports": [
|
||||
"S_AXI",
|
||||
"auto_pc/S_AXI"
|
||||
]
|
||||
}
|
||||
},
|
||||
"nets": {
|
||||
"S_ACLK_1": {
|
||||
"ports": [
|
||||
"S_ACLK",
|
||||
"auto_pc/aclk"
|
||||
]
|
||||
},
|
||||
"S_ARESETN_1": {
|
||||
"ports": [
|
||||
"S_ARESETN",
|
||||
"auto_pc/aresetn"
|
||||
]
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"interface_nets": {
|
||||
"ps7_axi_periph_to_s00_couplers": {
|
||||
"interface_ports": [
|
||||
"S00_AXI",
|
||||
"s00_couplers/S_AXI"
|
||||
]
|
||||
},
|
||||
"s00_couplers_to_ps7_axi_periph": {
|
||||
"interface_ports": [
|
||||
"s00_couplers/M_AXI",
|
||||
"M00_AXI"
|
||||
]
|
||||
}
|
||||
},
|
||||
"nets": {
|
||||
"S00_ACLK_1": {
|
||||
"ports": [
|
||||
"S00_ACLK",
|
||||
"s00_couplers/S_ACLK"
|
||||
]
|
||||
},
|
||||
"S00_ARESETN_1": {
|
||||
"ports": [
|
||||
"S00_ARESETN",
|
||||
"s00_couplers/S_ARESETN"
|
||||
]
|
||||
},
|
||||
"ps7_axi_periph_ACLK_net": {
|
||||
"ports": [
|
||||
"M00_ACLK",
|
||||
"s00_couplers/M_ACLK"
|
||||
]
|
||||
},
|
||||
"ps7_axi_periph_ARESETN_net": {
|
||||
"ports": [
|
||||
"M00_ARESETN",
|
||||
"s00_couplers/M_ARESETN"
|
||||
]
|
||||
}
|
||||
}
|
||||
},
|
||||
"rst_ps7_100M": {
|
||||
"vlnv": "xilinx.com:ip:proc_sys_reset:5.0",
|
||||
"ip_revision": "14",
|
||||
"xci_name": "system_bd_rst_ps7_100M_0",
|
||||
"xci_path": "ip/system_bd_rst_ps7_100M_0/system_bd_rst_ps7_100M_0.xci",
|
||||
"inst_hier_path": "rst_ps7_100M"
|
||||
},
|
||||
"xlconcat_irq": {
|
||||
"vlnv": "xilinx.com:ip:xlconcat:2.1",
|
||||
"ip_revision": "5",
|
||||
"xci_name": "system_bd_xlconcat_0_0",
|
||||
"xci_path": "ip/system_bd_xlconcat_0_0/system_bd_xlconcat_0_0.xci",
|
||||
"inst_hier_path": "xlconcat_irq",
|
||||
"parameters": {
|
||||
"NUM_PORTS": {
|
||||
"value": "1"
|
||||
}
|
||||
}
|
||||
}
|
||||
},
|
||||
"interface_nets": {
|
||||
"axi_spi_engine_spi": {
|
||||
"interface_ports": [
|
||||
"spi",
|
||||
"axi_spi_engine/spi"
|
||||
]
|
||||
},
|
||||
"processing_system7_0_DDR": {
|
||||
"interface_ports": [
|
||||
"DDR",
|
||||
"processing_system7_0/DDR"
|
||||
"processing_system7/DDR"
|
||||
]
|
||||
},
|
||||
"processing_system7_0_FIXED_IO": {
|
||||
"interface_ports": [
|
||||
"FIXED_IO",
|
||||
"processing_system7_0/FIXED_IO"
|
||||
"processing_system7/FIXED_IO"
|
||||
]
|
||||
},
|
||||
"processing_system7_M_AXI_GP0": {
|
||||
"interface_ports": [
|
||||
"processing_system7/M_AXI_GP0",
|
||||
"ps7_axi_periph/S00_AXI"
|
||||
]
|
||||
},
|
||||
"ps7_axi_periph_M00_AXI": {
|
||||
"interface_ports": [
|
||||
"ps7_axi_periph/M00_AXI",
|
||||
"axi_spi_engine/s_axi"
|
||||
]
|
||||
}
|
||||
},
|
||||
"nets": {
|
||||
"GPIO_I_0_1": {
|
||||
"ports": [
|
||||
"GPIO_I_0",
|
||||
"processing_system7_0/GPIO_I"
|
||||
"GPIO_I",
|
||||
"processing_system7/GPIO_I"
|
||||
]
|
||||
},
|
||||
"SPI0_MISO_I_0_1": {
|
||||
"axi_spi_engine_active": {
|
||||
"ports": [
|
||||
"SPI0_MISO_I_0",
|
||||
"processing_system7_0/SPI0_MISO_I",
|
||||
"ila_spi/probe2"
|
||||
"axi_spi_engine/active",
|
||||
"spi_active"
|
||||
]
|
||||
},
|
||||
"processing_system7_0_FCLK_CLK0": {
|
||||
"axi_spi_engine_irq": {
|
||||
"ports": [
|
||||
"processing_system7_0/FCLK_CLK0",
|
||||
"ila_spi/clk"
|
||||
"axi_spi_engine/irq",
|
||||
"xlconcat_irq/In0"
|
||||
]
|
||||
},
|
||||
"processing_system7_0_GPIO_O": {
|
||||
"ports": [
|
||||
"processing_system7_0/GPIO_O",
|
||||
"GPIO_O_0"
|
||||
"processing_system7/GPIO_O",
|
||||
"GPIO_O"
|
||||
]
|
||||
},
|
||||
"processing_system7_0_GPIO_T": {
|
||||
"ports": [
|
||||
"processing_system7_0/GPIO_T",
|
||||
"GPIO_T_0"
|
||||
"processing_system7/GPIO_T",
|
||||
"GPIO_T"
|
||||
]
|
||||
},
|
||||
"processing_system7_0_SPI0_MOSI_O": {
|
||||
"processing_system7_FCLK_CLK0": {
|
||||
"ports": [
|
||||
"processing_system7_0/SPI0_MOSI_O",
|
||||
"SPI0_MOSI_O_0",
|
||||
"ila_spi/probe1"
|
||||
"processing_system7/FCLK_CLK0",
|
||||
"processing_system7/M_AXI_GP0_ACLK",
|
||||
"ps7_axi_periph/S00_ACLK",
|
||||
"rst_ps7_100M/slowest_sync_clk",
|
||||
"axi_spi_engine/s_axi_aclk",
|
||||
"ps7_axi_periph/M00_ACLK",
|
||||
"ps7_axi_periph/ACLK",
|
||||
"axi_spi_engine/spi_clk"
|
||||
]
|
||||
},
|
||||
"processing_system7_0_SPI0_SCLK_O": {
|
||||
"processing_system7_FCLK_RESET0_N": {
|
||||
"ports": [
|
||||
"processing_system7_0/SPI0_SCLK_O",
|
||||
"SPI0_SCLK_O_0",
|
||||
"ila_spi/probe0"
|
||||
"processing_system7/FCLK_RESET0_N",
|
||||
"rst_ps7_100M/ext_reset_in"
|
||||
]
|
||||
},
|
||||
"processing_system7_0_SPI0_SS1_O": {
|
||||
"rst_ps7_100M_peripheral_aresetn": {
|
||||
"ports": [
|
||||
"processing_system7_0/SPI0_SS1_O",
|
||||
"SPI0_SS1_O_0",
|
||||
"ila_spi/probe4"
|
||||
"rst_ps7_100M/peripheral_aresetn",
|
||||
"ps7_axi_periph/S00_ARESETN",
|
||||
"axi_spi_engine/s_axi_aresetn",
|
||||
"ps7_axi_periph/M00_ARESETN",
|
||||
"ps7_axi_periph/ARESETN"
|
||||
]
|
||||
},
|
||||
"processing_system7_0_SPI0_SS2_O": {
|
||||
"xlconcat_irq_dout": {
|
||||
"ports": [
|
||||
"processing_system7_0/SPI0_SS2_O",
|
||||
"SPI0_SS2_O_0",
|
||||
"ila_spi/probe5"
|
||||
]
|
||||
},
|
||||
"processing_system7_0_SPI0_SS_O": {
|
||||
"ports": [
|
||||
"processing_system7_0/SPI0_SS_O",
|
||||
"SPI0_SS_O_0",
|
||||
"ila_spi/probe3"
|
||||
]
|
||||
},
|
||||
"xlconstant_vcc_dout": {
|
||||
"ports": [
|
||||
"xlconstant_vcc/dout",
|
||||
"processing_system7_0/SPI0_SS_I"
|
||||
"xlconcat_irq/dout",
|
||||
"processing_system7/IRQ_F2P"
|
||||
]
|
||||
}
|
||||
},
|
||||
"addressing": {
|
||||
"/processing_system7": {
|
||||
"address_spaces": {
|
||||
"Data": {
|
||||
"segments": {
|
||||
"SEG_axi_spi_engine_axi_lite": {
|
||||
"address_block": "/axi_spi_engine/axi_spi_engine/s_axi/axi_lite",
|
||||
"offset": "0x43C00000",
|
||||
"range": "64K"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+23
@@ -187,6 +187,24 @@
|
||||
"VH": "2",
|
||||
"VT": "PM",
|
||||
"TU": "active"
|
||||
},
|
||||
"V3": {
|
||||
"VT": "AC",
|
||||
"BA": "0x43C00000",
|
||||
"HA": "0x43C0FFFF",
|
||||
"BP": "C_BASEADDR",
|
||||
"HP": "C_HIGHADDR",
|
||||
"MA": "Data",
|
||||
"MX": "/processing_system7",
|
||||
"MI": "M_AXI_GP0",
|
||||
"MS": "SEG_axi_spi_engine_axi_lite",
|
||||
"MV": "xilinx.com:ip:processing_system7:5.5",
|
||||
"SX": "/axi_spi_engine/axi_spi_engine",
|
||||
"SI": "s_axi",
|
||||
"SS": "axi_lite",
|
||||
"SV": "analog.com:user:axi_spi_engine:1.0",
|
||||
"TM": "both",
|
||||
"TU": "register"
|
||||
}
|
||||
},
|
||||
"edges": [
|
||||
@@ -197,6 +215,11 @@
|
||||
{
|
||||
"src": "V1",
|
||||
"trg": "V2"
|
||||
},
|
||||
{
|
||||
"src": "V3",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
}
|
||||
]
|
||||
}
|
||||
|
||||
+30
-30
@@ -1,41 +1,41 @@
|
||||
{
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"1.0",
|
||||
"Default View_TopLeft":"-486,-176",
|
||||
"Default View_TopLeft":"-393,-47",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 TLS
|
||||
# -string -flagsOSRD
|
||||
preplace port DDR -pg 1 -lvl 3 -x 600 -y 140 -defaultsOSRD
|
||||
preplace port FIXED_IO -pg 1 -lvl 3 -x 600 -y 160 -defaultsOSRD
|
||||
preplace port port-id_SPI0_SS_O_0 -pg 1 -lvl 3 -x 600 -y 240 -defaultsOSRD
|
||||
preplace port port-id_SPI0_SS1_O_0 -pg 1 -lvl 3 -x 600 -y 260 -defaultsOSRD
|
||||
preplace port port-id_SPI0_SS2_O_0 -pg 1 -lvl 3 -x 600 -y 280 -defaultsOSRD
|
||||
preplace port port-id_SPI0_SCLK_O_0 -pg 1 -lvl 3 -x 600 -y 180 -defaultsOSRD
|
||||
preplace port port-id_SPI0_MOSI_O_0 -pg 1 -lvl 3 -x 600 -y 200 -defaultsOSRD
|
||||
preplace port port-id_SPI0_MISO_I_0 -pg 1 -lvl 3 -x 600 -y 220 -defaultsOSRD -right
|
||||
preplace portBus GPIO_O_0 -pg 1 -lvl 3 -x 600 -y 100 -defaultsOSRD
|
||||
preplace portBus GPIO_I_0 -pg 1 -lvl 3 -x 600 -y 80 -defaultsOSRD -right
|
||||
preplace portBus GPIO_T_0 -pg 1 -lvl 3 -x 600 -y 120 -defaultsOSRD
|
||||
preplace inst processing_system7_0 -pg 1 -lvl 1 -x 160 -y 210 -defaultsOSRD
|
||||
preplace inst xlconstant_vcc -pg 1 -lvl 1 -x 160 -y 460 -defaultsOSRD
|
||||
preplace inst ila_spi -pg 1 -lvl 2 -x 480 -y 400 -defaultsOSRD
|
||||
preplace netloc GPIO_I_0_1 1 1 2 N 80 N
|
||||
preplace netloc SPI0_MISO_I_0_1 1 1 2 350 220 N
|
||||
preplace netloc processing_system7_0_GPIO_O 1 1 2 N 100 N
|
||||
preplace netloc processing_system7_0_SPI0_MOSI_O 1 1 2 340 200 N
|
||||
preplace netloc processing_system7_0_SPI0_SCLK_O 1 1 2 330 180 N
|
||||
preplace netloc processing_system7_0_SPI0_SS1_O 1 1 2 370 260 N
|
||||
preplace netloc processing_system7_0_SPI0_SS2_O 1 1 2 380 280 N
|
||||
preplace netloc processing_system7_0_SPI0_SS_O 1 1 2 360 240 N
|
||||
preplace netloc xlconstant_vcc_dout 1 1 1 320 260n
|
||||
preplace netloc processing_system7_0_GPIO_T 1 1 2 N 120 N
|
||||
preplace netloc processing_system7_0_FCLK_CLK0 1 1 1 N 340
|
||||
preplace netloc processing_system7_0_DDR 1 1 2 NJ 140 N
|
||||
preplace netloc processing_system7_0_FIXED_IO 1 1 2 NJ 160 N
|
||||
levelinfo -pg 1 0 160 480 600
|
||||
pagesize -pg 1 -db -bbox -sgen 0 0 770 520
|
||||
preplace port DDR -pg 1 -lvl 3 -x 870 -y 180 -defaultsOSRD
|
||||
preplace port FIXED_IO -pg 1 -lvl 3 -x 870 -y 200 -defaultsOSRD
|
||||
preplace port spi -pg 1 -lvl 3 -x 870 -y 590 -defaultsOSRD
|
||||
preplace port port-id_spi_active -pg 1 -lvl 3 -x 870 -y 630 -defaultsOSRD
|
||||
preplace portBus GPIO_O -pg 1 -lvl 3 -x 870 -y 140 -defaultsOSRD
|
||||
preplace portBus GPIO_I -pg 1 -lvl 3 -x 870 -y 120 -defaultsOSRD -right
|
||||
preplace portBus GPIO_T -pg 1 -lvl 3 -x 870 -y 160 -defaultsOSRD
|
||||
preplace inst processing_system7 -pg 1 -lvl 1 -x 270 -y 180 -defaultsOSRD
|
||||
preplace inst axi_spi_engine -pg 1 -lvl 1 -x 270 -y 610 -defaultsOSRD
|
||||
preplace inst ps7_axi_periph -pg 1 -lvl 1 -x 270 -y 420 -defaultsOSRD
|
||||
preplace inst rst_ps7_100M -pg 1 -lvl 2 -x 670 -y 300 -defaultsOSRD
|
||||
preplace inst xlconcat_irq -pg 1 -lvl 2 -x 670 -y 530 -defaultsOSRD -orient R180
|
||||
preplace netloc GPIO_I_0_1 1 1 2 N 120 N
|
||||
preplace netloc axi_spi_engine_active 1 1 2 NJ 630 NJ
|
||||
preplace netloc axi_spi_engine_irq 1 1 2 N 610 840
|
||||
preplace netloc processing_system7_0_GPIO_O 1 1 2 N 140 N
|
||||
preplace netloc processing_system7_0_GPIO_T 1 1 2 N 160 N
|
||||
preplace netloc processing_system7_FCLK_CLK0 1 0 2 70 30 470
|
||||
preplace netloc processing_system7_FCLK_RESET0_N 1 1 1 460 260n
|
||||
preplace netloc rst_ps7_100M_peripheral_aresetn 1 0 3 50 20 NJ 20 840
|
||||
preplace netloc xlconcat_irq_dout 1 0 2 60 700 470
|
||||
preplace netloc axi_spi_engine_spi 1 1 2 NJ 590 NJ
|
||||
preplace netloc processing_system7_0_DDR 1 1 2 NJ 180 N
|
||||
preplace netloc processing_system7_0_FIXED_IO 1 1 2 NJ 200 N
|
||||
preplace netloc processing_system7_M_AXI_GP0 1 0 2 80 40 460J
|
||||
preplace netloc ps7_axi_periph_M00_AXI 1 0 2 80 690 460J
|
||||
levelinfo -pg 1 0 270 670 870
|
||||
pagesize -pg 1 -db -bbox -sgen 0 0 1020 710
|
||||
"
|
||||
}
|
||||
{
|
||||
"da_axi4_cnt":"1",
|
||||
"da_ps7_cnt":"1"
|
||||
}
|
||||
|
||||
+30
@@ -0,0 +1,30 @@
|
||||
{
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"1.0",
|
||||
"Default View_TopLeft":"-778,-240",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 TLS
|
||||
# -string -flagsOSRD
|
||||
preplace port s_axi -pg 1 -lvl 0 -x 0 -y 70 -defaultsOSRD
|
||||
preplace port spi -pg 1 -lvl 2 -x 340 -y 230 -defaultsOSRD
|
||||
preplace port port-id_irq -pg 1 -lvl 2 -x 340 -y 100 -defaultsOSRD
|
||||
preplace port port-id_s_axi_aclk -pg 1 -lvl 0 -x 0 -y 90 -defaultsOSRD
|
||||
preplace port port-id_s_axi_aresetn -pg 1 -lvl 0 -x 0 -y 110 -defaultsOSRD
|
||||
preplace port port-id_spi_clk -pg 1 -lvl 0 -x 0 -y 130 -defaultsOSRD
|
||||
preplace port port-id_active -pg 1 -lvl 2 -x 340 -y 250 -defaultsOSRD
|
||||
preplace inst axi_spi_engine -pg 1 -lvl 1 -x 180 -y 90 -defaultsOSRD
|
||||
preplace inst spi_engine_execution -pg 1 -lvl 1 -x 180 -y 240 -defaultsOSRD
|
||||
preplace netloc axi_spi_engine_spi_resetn 1 0 2 40 320 320
|
||||
preplace netloc axi_spi_engine_irq 1 1 1 320J 90n
|
||||
preplace netloc s_axi_aclk_0_1 1 0 1 20 80n
|
||||
preplace netloc spi_clk_0_1 1 0 1 30 120n
|
||||
preplace netloc spi_engine_execution_active 1 1 1 N 250
|
||||
preplace netloc s_axi_aresetn_1 1 0 1 20 100n
|
||||
preplace netloc axi_spi_engine_spi_engine_ctrl 1 0 2 40 0 320
|
||||
preplace netloc Conn1 1 0 1 20 60n
|
||||
preplace netloc Conn2 1 1 1 N 230
|
||||
levelinfo -pg 1 0 180 340
|
||||
pagesize -pg 1 -db -bbox -sgen -150 -10 440 350
|
||||
"
|
||||
}
|
||||
|
||||
+32
-31
@@ -284,41 +284,41 @@ wire [47:0] gpio_i;
|
||||
wire [47:0] gpio_o;
|
||||
wire [47:0] gpio_t;
|
||||
wire ad9361_rx_fifo_rst;
|
||||
wire spi_sdo_t;
|
||||
|
||||
assign gpio_i[47:39] = gpio_o[47:39];
|
||||
|
||||
// hmc7044
|
||||
assign hmc7044_reset = gpio_o[ 0]; // hmc7044 reset
|
||||
assign hmc7044_sync = gpio_o[ 1]; // hmc7044 multichip synchronization
|
||||
assign hmc7044_gpio[0] = gpio_t[ 2] ? gpio_i[ 2] : gpio_o[ 2];
|
||||
assign hmc7044_gpio[1] = gpio_t[ 3] ? gpio_i[ 3] : gpio_o[ 3];
|
||||
assign hmc7044_gpio[2] = gpio_t[ 4] ? gpio_i[ 4] : gpio_o[ 4];
|
||||
assign hmc7044_gpio[3] = gpio_t[ 5] ? gpio_i[ 5] : gpio_o[ 5];
|
||||
assign hmc7044_reset = gpio_o[ 0]; // hmc7044 reset
|
||||
assign hmc7044_sync = gpio_o[ 1]; // hmc7044 multichip synchronization
|
||||
assign hmc7044_gpio[0] = gpio_t[ 2] ? gpio_i[ 2] : gpio_o[ 2];
|
||||
assign hmc7044_gpio[1] = gpio_t[ 3] ? gpio_i[ 3] : gpio_o[ 3];
|
||||
assign hmc7044_gpio[2] = gpio_t[ 4] ? gpio_i[ 4] : gpio_o[ 4];
|
||||
assign hmc7044_gpio[3] = gpio_t[ 5] ? gpio_i[ 5] : gpio_o[ 5];
|
||||
// ad9361-1
|
||||
assign ad9361_1_txnrx = gpio_o[ 6]; // ad9361 enable state machine control
|
||||
assign ad9361_1_enable = gpio_o[ 7]; // ad9361 enable state machine control
|
||||
assign ad9361_1_en_agc = gpio_o[ 8]; // ad9361 agc control
|
||||
assign ad9361_1_reset_b = gpio_o[ 9]; // ad9361 reset
|
||||
assign ad9361_1_ctrl_out = gpio_o[17:10];
|
||||
assign ad9361_1_txnrx = gpio_o[ 6]; // ad9361 enable state machine control
|
||||
assign ad9361_1_enable = gpio_o[ 7]; // ad9361 enable state machine control
|
||||
assign ad9361_1_en_agc = gpio_o[ 8]; // ad9361 agc control
|
||||
assign ad9361_1_reset_b = gpio_o[ 9]; // ad9361 reset
|
||||
assign ad9361_1_ctrl_out = gpio_o[17:10];
|
||||
assign gpio_i[21:18] = ad9361_1_ctrl_in;
|
||||
// ad9361-2
|
||||
assign ad9361_2_txnrx = gpio_o[22]; // ad9361 enable state machine control
|
||||
assign ad9361_2_enable = gpio_o[23]; // ad9361 enable state machine control
|
||||
assign ad9361_2_en_agc = gpio_o[24]; // ad9361 agc control
|
||||
assign ad9361_2_reset_b = gpio_o[25]; // ad9361 reset
|
||||
assign ad9361_2_ctrl_out = gpio_o[33:26];
|
||||
assign ad9361_2_txnrx = gpio_o[22]; // ad9361 enable state machine control
|
||||
assign ad9361_2_enable = gpio_o[23]; // ad9361 enable state machine control
|
||||
assign ad9361_2_en_agc = gpio_o[24]; // ad9361 agc control
|
||||
assign ad9361_2_reset_b = gpio_o[25]; // ad9361 reset
|
||||
assign ad9361_2_ctrl_out = gpio_o[33:26];
|
||||
assign gpio_i[37:34] = ad9361_2_ctrl_in;
|
||||
// ad9361 rx fifo reset
|
||||
assign ad9361_rx_fifo_rst = gpio_o[38];
|
||||
// 3-wire spi inout tri-state control
|
||||
assign spi_sdo_t = gpio_o[39];
|
||||
assign ad9361_rx_fifo_rst= gpio_o[38];
|
||||
|
||||
// spi interface
|
||||
wire spi_sclk ;
|
||||
wire [ 2:0] spi_cs ;
|
||||
reg spi_sdi ;
|
||||
wire spi_sdo ;
|
||||
wire spi_sdo_t ;
|
||||
wire spi_three_wire;
|
||||
wire spi_active ;
|
||||
|
||||
// hmc7044 - three-wire spi
|
||||
assign hmc7044_spi_clk = spi_sclk;
|
||||
@@ -337,9 +337,9 @@ always @(*) begin
|
||||
if (~hmc7044_spi_csn)
|
||||
spi_sdi = hmc7044_spi_sdio;
|
||||
else if (~ad9361_1_spi_csn)
|
||||
spi_sdi = ad9361_1_spi_miso;
|
||||
spi_sdi = spi_three_wire ? ad9361_1_spi_mosi : ad9361_1_spi_miso;
|
||||
else if (~ad9361_2_spi_csn)
|
||||
spi_sdi = ad9361_2_spi_miso;
|
||||
spi_sdi = spi_three_wire ? ad9361_2_spi_mosi : ad9361_2_spi_miso;
|
||||
else
|
||||
spi_sdi = 1'bz;
|
||||
end
|
||||
@@ -372,17 +372,18 @@ system_bd_wrapper u_system_bd_wrapper
|
||||
.FIXED_IO_ps_srstb (fixed_io_ps_srstb ), // inout FIXED_IO_ps_srstb
|
||||
|
||||
// gpio, for control signals
|
||||
.GPIO_I_0 (gpio_i ), // input [47:0]GPIO_I_0
|
||||
.GPIO_O_0 (gpio_o ), // output [47:0]GPIO_O_0
|
||||
.GPIO_T_0 (gpio_t ), // output [47:0]GPIO_T_0
|
||||
.GPIO_I (gpio_i ), // input [47:0]GPIO_I_0
|
||||
.GPIO_O (gpio_o ), // output [47:0]GPIO_O_0
|
||||
.GPIO_T (gpio_t ), // output [47:0]GPIO_T_0
|
||||
|
||||
// spi interface
|
||||
.SPI0_MISO_I_0 (spi_sdi ), // input SPI0_MISO_I_0
|
||||
.SPI0_MOSI_O_0 (spi_sdo ), // output SPI0_MOSI_O_0
|
||||
.SPI0_SCLK_O_0 (spi_sclk ), // output SPI0_SCLK_O_0
|
||||
.SPI0_SS_O_0 (spi_cs[0] ), // output SPI0_SS_O_0
|
||||
.SPI0_SS1_O_0 (spi_cs[1] ), // output SPI0_SS1_O_0
|
||||
.SPI0_SS2_O_0 (spi_cs[2] ) // output SPI0_SS2_O_0
|
||||
.spi_sclk (spi_sclk ), // output spi_sclk
|
||||
.spi_cs (spi_cs ), // output [2:0]spi_cs
|
||||
.spi_sdi (spi_sdi ), // input [0:0]spi_sdi
|
||||
.spi_sdo (spi_sdo ), // output spi_sdo
|
||||
.spi_sdo_t (spi_sdo_t ), // output spi_sdo_t
|
||||
.spi_three_wire (spi_three_wire ), // output spi_three_wire
|
||||
.spi_active (spi_active ) // output spi_active
|
||||
);
|
||||
|
||||
|
||||
|
||||
BIN
Binary file not shown.
@@ -47,6 +47,7 @@
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../../vivado_pub/adi_library"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
@@ -140,12 +141,18 @@
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_ila_0_0/system_bd_ila_0_0.xci">
|
||||
<Proxy FileSetName="system_bd_ila_0_0"/>
|
||||
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xci">
|
||||
<Proxy FileSetName="system_bd_axi_spi_engine_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_processing_system7_0_0/system_bd_processing_system7_0_0.xci">
|
||||
<Proxy FileSetName="system_bd_processing_system7_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_rst_ps7_100M_0/system_bd_rst_ps7_100M_0.xci">
|
||||
<Proxy FileSetName="system_bd_rst_ps7_100M_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_spi_engine_execution_0_0/system_bd_spi_engine_execution_0_0.xci">
|
||||
<Proxy FileSetName="system_bd_spi_engine_execution_0_0"/>
|
||||
</CompFileExtendedInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../../../../vivado_pub/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_cmos_dual.v">
|
||||
<FileInfo>
|
||||
@@ -329,9 +336,21 @@
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="system_bd_ila_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_ila_0_0" RelGenDir="$PGENDIR/system_bd_ila_0_0">
|
||||
<FileSet Name="system_bd_rst_ps7_100M_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_rst_ps7_100M_0" RelGenDir="$PGENDIR/system_bd_rst_ps7_100M_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="system_bd_ila_0_0"/>
|
||||
<Option Name="TopModule" Val="system_bd_rst_ps7_100M_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="system_bd_spi_engine_execution_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_spi_engine_execution_0_0" RelGenDir="$PGENDIR/system_bd_spi_engine_execution_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="system_bd_spi_engine_execution_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="system_bd_axi_spi_engine_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_axi_spi_engine_0_0" RelGenDir="$PGENDIR/system_bd_axi_spi_engine_0_0">
|
||||
<Config>
|
||||
<Option Name="TopModule" Val="system_bd_axi_spi_engine_0_0"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
@@ -360,7 +379,9 @@
|
||||
<Runs Version="1" Minor="21">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z100ffg900-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/system_top.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
@@ -370,9 +391,7 @@
|
||||
</Run>
|
||||
<Run Id="ad9361_clk_gen_cmos_2t2r_synth_1" Type="Ft3:Synth" SrcSet="ad9361_clk_gen_cmos_2t2r" Part="xc7z100ffg900-2" ConstrsSet="ad9361_clk_gen_cmos_2t2r" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ad9361_clk_gen_cmos_2t2r_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ad9361_clk_gen_cmos_2t2r_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ad9361_clk_gen_cmos_2t2r_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
@@ -382,9 +401,7 @@
|
||||
</Run>
|
||||
<Run Id="ant_clk_gen_stg1_synth_1" Type="Ft3:Synth" SrcSet="ant_clk_gen_stg1" Part="xc7z100ffg900-2" ConstrsSet="ant_clk_gen_stg1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ant_clk_gen_stg1_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ant_clk_gen_stg1_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ant_clk_gen_stg1_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
@@ -394,9 +411,7 @@
|
||||
</Run>
|
||||
<Run Id="ant_clk_gen_stg2_synth_1" Type="Ft3:Synth" SrcSet="ant_clk_gen_stg2" Part="xc7z100ffg900-2" ConstrsSet="ant_clk_gen_stg2" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ant_clk_gen_stg2_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ant_clk_gen_stg2_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ant_clk_gen_stg2_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
@@ -406,9 +421,7 @@
|
||||
</Run>
|
||||
<Run Id="ila_8x12x131072_synth_1" Type="Ft3:Synth" SrcSet="ila_8x12x131072" Part="xc7z100ffg900-2" ConstrsSet="ila_8x12x131072" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ila_8x12x131072_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_8x12x131072_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_8x12x131072_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
@@ -418,9 +431,7 @@
|
||||
</Run>
|
||||
<Run Id="vio_manual_ctrl_synth_1" Type="Ft3:Synth" SrcSet="vio_manual_ctrl" Part="xc7z100ffg900-2" ConstrsSet="vio_manual_ctrl" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/vio_manual_ctrl_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_manual_ctrl_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_manual_ctrl_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
@@ -429,6 +440,16 @@
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_bd_processing_system7_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_processing_system7_0_0" Part="xc7z100ffg900-2" ConstrsSet="system_bd_processing_system7_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_processing_system7_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_processing_system7_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_processing_system7_0_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_bd_rst_ps7_100M_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_rst_ps7_100M_0" Part="xc7z100ffg900-2" ConstrsSet="system_bd_rst_ps7_100M_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_rst_ps7_100M_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_rst_ps7_100M_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_rst_ps7_100M_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
@@ -440,7 +461,19 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_bd_ila_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_ila_0_0" Part="xc7z100ffg900-2" ConstrsSet="system_bd_ila_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_ila_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_ila_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_ila_0_0_synth_1">
|
||||
<Run Id="system_bd_spi_engine_execution_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_spi_engine_execution_0_0" Part="xc7z100ffg900-2" ConstrsSet="system_bd_spi_engine_execution_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_spi_engine_execution_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_spi_engine_execution_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_spi_engine_execution_0_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_bd_axi_spi_engine_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_axi_spi_engine_0_0" Part="xc7z100ffg900-2" ConstrsSet="system_bd_axi_spi_engine_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_axi_spi_engine_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_axi_spi_engine_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_axi_spi_engine_0_0_synth_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
@@ -454,7 +487,9 @@
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 18 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
@@ -472,9 +507,7 @@
|
||||
</Run>
|
||||
<Run Id="ad9361_clk_gen_cmos_2t2r_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="ad9361_clk_gen_cmos_2t2r" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ad9361_clk_gen_cmos_2t2r_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ad9361_clk_gen_cmos_2t2r_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ad9361_clk_gen_cmos_2t2r_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
@@ -491,9 +524,7 @@
|
||||
</Run>
|
||||
<Run Id="ant_clk_gen_stg1_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="ant_clk_gen_stg1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ant_clk_gen_stg1_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ant_clk_gen_stg1_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ant_clk_gen_stg1_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
@@ -510,9 +541,7 @@
|
||||
</Run>
|
||||
<Run Id="ant_clk_gen_stg2_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="ant_clk_gen_stg2" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ant_clk_gen_stg2_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ant_clk_gen_stg2_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ant_clk_gen_stg2_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
@@ -529,9 +558,7 @@
|
||||
</Run>
|
||||
<Run Id="ila_8x12x131072_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="ila_8x12x131072" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ila_8x12x131072_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_8x12x131072_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_8x12x131072_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
@@ -548,9 +575,7 @@
|
||||
</Run>
|
||||
<Run Id="vio_manual_ctrl_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="vio_manual_ctrl" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="vio_manual_ctrl_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_manual_ctrl_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_manual_ctrl_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
@@ -566,6 +591,23 @@
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_bd_processing_system7_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="system_bd_processing_system7_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_processing_system7_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_processing_system7_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_processing_system7_0_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_bd_rst_ps7_100M_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="system_bd_rst_ps7_100M_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_rst_ps7_100M_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_rst_ps7_100M_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_rst_ps7_100M_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
@@ -584,7 +626,26 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_bd_ila_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="system_bd_ila_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_ila_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_ila_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_ila_0_0_impl_1">
|
||||
<Run Id="system_bd_spi_engine_execution_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="system_bd_spi_engine_execution_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_spi_engine_execution_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_spi_engine_execution_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_spi_engine_execution_0_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="system_bd_axi_spi_engine_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z100ffg900-2" ConstrsSet="system_bd_axi_spi_engine_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_axi_spi_engine_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_axi_spi_engine_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_axi_spi_engine_0_0_impl_1">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
|
||||
Binary file not shown.
@@ -3,9 +3,9 @@
|
||||
|
||||
<storageModule moduleId="org.eclipse.cdt.core.settings">
|
||||
|
||||
<cconfiguration id="xilinx.gnu.armv7.exe.debug.1922579181">
|
||||
<cconfiguration id="xilinx.gnu.armv7.exe.debug.860548130">
|
||||
|
||||
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="xilinx.gnu.armv7.exe.debug.1922579181" moduleId="org.eclipse.cdt.core.settings" name="Debug">
|
||||
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="xilinx.gnu.armv7.exe.debug.860548130" moduleId="org.eclipse.cdt.core.settings" name="Debug">
|
||||
|
||||
<externalSettings/>
|
||||
|
||||
@@ -29,47 +29,47 @@
|
||||
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
|
||||
<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" id="xilinx.gnu.armv7.exe.debug.1922579181" name="Debug" parent="xilinx.gnu.armv7.exe.debug" prebuildStep="a9-linaro-pre-build-step">
|
||||
<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" id="xilinx.gnu.armv7.exe.debug.860548130" name="Debug" parent="xilinx.gnu.armv7.exe.debug" prebuildStep="a9-linaro-pre-build-step">
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||||
|
||||
<folderInfo id="xilinx.gnu.armv7.exe.debug.1922579181." name="/" resourcePath="">
|
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<folderInfo id="xilinx.gnu.armv7.exe.debug.860548130." name="/" resourcePath="">
|
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|
||||
<toolChain id="xilinx.gnu.armv7.exe.debug.toolchain.6397833" name="Vitis ARM v7 GNU Toolchain" superClass="xilinx.gnu.armv7.exe.debug.toolchain">
|
||||
<toolChain id="xilinx.gnu.armv7.exe.debug.toolchain.6494536" name="Vitis ARM v7 GNU Toolchain" superClass="xilinx.gnu.armv7.exe.debug.toolchain">
|
||||
|
||||
<targetPlatform binaryParser="com.xilinx.sdk.managedbuilder.XELF.arm.a53.x32" id="xilinx.armv7.target.gnu.base.debug.595896898" isAbstract="false" name="Debug Platform" superClass="xilinx.armv7.target.gnu.base.debug"/>
|
||||
<targetPlatform binaryParser="com.xilinx.sdk.managedbuilder.XELF.arm.a53.x32" id="xilinx.armv7.target.gnu.base.debug.967844318" isAbstract="false" name="Debug Platform" superClass="xilinx.armv7.target.gnu.base.debug"/>
|
||||
|
||||
<builder buildPath="${workspace_loc:/duifei_cmos}/Debug" enableAutoBuild="true" id="xilinx.gnu.armv7.toolchain.builder.debug.547693526" managedBuildOn="true" name="GNU make.Debug" superClass="xilinx.gnu.armv7.toolchain.builder.debug"/>
|
||||
<builder buildPath="${workspace_loc:/duifei_cmos}/Debug" enableAutoBuild="true" id="xilinx.gnu.armv7.toolchain.builder.debug.1385723027" managedBuildOn="true" name="GNU make.Debug" superClass="xilinx.gnu.armv7.toolchain.builder.debug"/>
|
||||
|
||||
<tool id="xilinx.gnu.armv7.c.toolchain.assembler.debug.1953295836" name="ARM v7 gcc assembler" superClass="xilinx.gnu.armv7.c.toolchain.assembler.debug">
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||||
<tool id="xilinx.gnu.armv7.c.toolchain.assembler.debug.2057042995" name="ARM v7 gcc assembler" superClass="xilinx.gnu.armv7.c.toolchain.assembler.debug">
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|
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<inputType id="xilinx.gnu.assembler.input.214008413" superClass="xilinx.gnu.assembler.input"/>
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<inputType id="xilinx.gnu.assembler.input.899804932" superClass="xilinx.gnu.assembler.input"/>
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|
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</tool>
|
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|
||||
<tool id="xilinx.gnu.armv7.c.toolchain.compiler.debug.340142942" name="ARM v7 gcc compiler" superClass="xilinx.gnu.armv7.c.toolchain.compiler.debug">
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<tool id="xilinx.gnu.armv7.c.toolchain.compiler.debug.870185296" name="ARM v7 gcc compiler" superClass="xilinx.gnu.armv7.c.toolchain.compiler.debug">
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|
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<option defaultValue="gnu.c.optimization.level.none" id="xilinx.gnu.compiler.option.optimization.level.1984921397" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>
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<option defaultValue="gnu.c.optimization.level.none" id="xilinx.gnu.compiler.option.optimization.level.514991326" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>
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<option id="xilinx.gnu.compiler.option.debugging.level.1982669170" superClass="xilinx.gnu.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.c.debugging.level.max" valueType="enumerated"/>
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<option id="xilinx.gnu.compiler.option.debugging.level.1853636934" superClass="xilinx.gnu.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.c.debugging.level.max" valueType="enumerated"/>
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<option id="xilinx.gnu.compiler.inferred.swplatform.includes.1487603795" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
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<option id="xilinx.gnu.compiler.inferred.swplatform.includes.138044369" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
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<listOptionValue builtIn="false" value="${resolvePlatformFile:project=duifei_cmos,fileType=bspInclude}"/>
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</option>
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|
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<option id="xilinx.gnu.compiler.misc.other.1115529594" superClass="xilinx.gnu.compiler.misc.other" value="-c -fmessage-length=0 -MT"$@" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard" valueType="string"/>
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||||
<option id="xilinx.gnu.compiler.misc.other.1400087263" superClass="xilinx.gnu.compiler.misc.other" value="-c -fmessage-length=0 -MT"$@" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard" valueType="string"/>
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||||
|
||||
<inputType id="xilinx.gnu.armv7.c.compiler.input.2110611050" name="C source files" superClass="xilinx.gnu.armv7.c.compiler.input"/>
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||||
<inputType id="xilinx.gnu.armv7.c.compiler.input.1499460340" name="C source files" superClass="xilinx.gnu.armv7.c.compiler.input"/>
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||||
|
||||
</tool>
|
||||
|
||||
<tool id="xilinx.gnu.armv7.cxx.toolchain.compiler.debug.1650796208" name="ARM v7 g++ compiler" superClass="xilinx.gnu.armv7.cxx.toolchain.compiler.debug">
|
||||
<tool id="xilinx.gnu.armv7.cxx.toolchain.compiler.debug.588326062" name="ARM v7 g++ compiler" superClass="xilinx.gnu.armv7.cxx.toolchain.compiler.debug">
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||||
|
||||
<option defaultValue="gnu.c.optimization.level.none" id="xilinx.gnu.compiler.option.optimization.level.840346476" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>
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||||
<option defaultValue="gnu.c.optimization.level.none" id="xilinx.gnu.compiler.option.optimization.level.454005282" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>
|
||||
|
||||
<option id="xilinx.gnu.compiler.option.debugging.level.1108296474" superClass="xilinx.gnu.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.c.debugging.level.max" valueType="enumerated"/>
|
||||
<option id="xilinx.gnu.compiler.option.debugging.level.387798453" superClass="xilinx.gnu.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.c.debugging.level.max" valueType="enumerated"/>
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||||
|
||||
<option id="xilinx.gnu.compiler.inferred.swplatform.includes.294937386" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
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||||
<option id="xilinx.gnu.compiler.inferred.swplatform.includes.379256758" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
|
||||
|
||||
<listOptionValue builtIn="false" value="${resolvePlatformFile:project=duifei_cmos,fileType=bspInclude}"/>
|
||||
|
||||
@@ -77,27 +77,27 @@
|
||||
|
||||
</tool>
|
||||
|
||||
<tool id="xilinx.gnu.armv7.toolchain.archiver.268205143" name="ARM v7 archiver" superClass="xilinx.gnu.armv7.toolchain.archiver"/>
|
||||
<tool id="xilinx.gnu.armv7.toolchain.archiver.1813942088" name="ARM v7 archiver" superClass="xilinx.gnu.armv7.toolchain.archiver"/>
|
||||
|
||||
<tool id="xilinx.gnu.armv7.c.toolchain.linker.debug.234050966" name="ARM v7 gcc linker" superClass="xilinx.gnu.armv7.c.toolchain.linker.debug">
|
||||
<tool id="xilinx.gnu.armv7.c.toolchain.linker.debug.1175577400" name="ARM v7 gcc linker" superClass="xilinx.gnu.armv7.c.toolchain.linker.debug">
|
||||
|
||||
<option id="xilinx.gnu.linker.inferred.swplatform.lpath.1324430527" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
|
||||
<option id="xilinx.gnu.linker.inferred.swplatform.lpath.290470162" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
|
||||
|
||||
<listOptionValue builtIn="false" value="${resolvePlatformFile:project=duifei_cmos,fileType=bspLib}"/>
|
||||
|
||||
</option>
|
||||
|
||||
<option id="xilinx.gnu.linker.inferred.swplatform.flags.366793251" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
|
||||
<option id="xilinx.gnu.linker.inferred.swplatform.flags.317290934" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
|
||||
|
||||
<listOptionValue builtIn="false" value="-Wl,--start-group,-lxil,-lgcc,-lc,--end-group"/>
|
||||
|
||||
</option>
|
||||
|
||||
<option id="xilinx.gnu.c.linker.option.lscript.932687614" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
|
||||
<option id="xilinx.gnu.c.linker.option.lscript.805217118" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
|
||||
|
||||
<option id="xilinx.gnu.c.link.option.ldflags.1108521635" superClass="xilinx.gnu.c.link.option.ldflags" value=" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-build-id=none -specs=Xilinx.spec" valueType="string"/>
|
||||
<option id="xilinx.gnu.c.link.option.ldflags.1227001195" superClass="xilinx.gnu.c.link.option.ldflags" value=" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-build-id=none -specs=Xilinx.spec" valueType="string"/>
|
||||
|
||||
<inputType id="xilinx.gnu.linker.input.725635447" superClass="xilinx.gnu.linker.input">
|
||||
<inputType id="xilinx.gnu.linker.input.574478156" superClass="xilinx.gnu.linker.input">
|
||||
|
||||
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
|
||||
|
||||
@@ -105,29 +105,29 @@
|
||||
|
||||
</inputType>
|
||||
|
||||
<inputType id="xilinx.gnu.linker.input.lscript.1023466264" name="Linker Script" superClass="xilinx.gnu.linker.input.lscript"/>
|
||||
<inputType id="xilinx.gnu.linker.input.lscript.1398008072" name="Linker Script" superClass="xilinx.gnu.linker.input.lscript"/>
|
||||
|
||||
</tool>
|
||||
|
||||
<tool id="xilinx.gnu.armv7.cxx.toolchain.linker.debug.1488657506" name="ARM v7 g++ linker" superClass="xilinx.gnu.armv7.cxx.toolchain.linker.debug">
|
||||
<tool id="xilinx.gnu.armv7.cxx.toolchain.linker.debug.203036784" name="ARM v7 g++ linker" superClass="xilinx.gnu.armv7.cxx.toolchain.linker.debug">
|
||||
|
||||
<option id="xilinx.gnu.linker.inferred.swplatform.lpath.111933901" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
|
||||
<option id="xilinx.gnu.linker.inferred.swplatform.lpath.1235881425" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
|
||||
|
||||
<listOptionValue builtIn="false" value="${resolvePlatformFile:project=duifei_cmos,fileType=bspLib}"/>
|
||||
|
||||
</option>
|
||||
|
||||
<option id="xilinx.gnu.linker.inferred.swplatform.flags.412326066" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
|
||||
<option id="xilinx.gnu.linker.inferred.swplatform.flags.646585101" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
|
||||
|
||||
<listOptionValue builtIn="false" value="-Wl,--start-group,-lxil,-lgcc,-lc,--end-group"/>
|
||||
|
||||
</option>
|
||||
|
||||
<option id="xilinx.gnu.c.linker.option.lscript.1397000659" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
|
||||
<option id="xilinx.gnu.c.linker.option.lscript.1531389732" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
|
||||
|
||||
</tool>
|
||||
|
||||
<tool id="xilinx.gnu.armv7.size.debug.932225883" name="ARM v7 Print Size" superClass="xilinx.gnu.armv7.size.debug"/>
|
||||
<tool id="xilinx.gnu.armv7.size.debug.1726860223" name="ARM v7 Print Size" superClass="xilinx.gnu.armv7.size.debug"/>
|
||||
|
||||
</toolChain>
|
||||
|
||||
@@ -147,9 +147,9 @@
|
||||
|
||||
</cconfiguration>
|
||||
|
||||
<cconfiguration id="xilinx.gnu.armv7.exe.release.1195692792">
|
||||
<cconfiguration id="xilinx.gnu.armv7.exe.release.184671342">
|
||||
|
||||
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="xilinx.gnu.armv7.exe.release.1195692792" moduleId="org.eclipse.cdt.core.settings" name="Release">
|
||||
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="xilinx.gnu.armv7.exe.release.184671342" moduleId="org.eclipse.cdt.core.settings" name="Release">
|
||||
|
||||
<externalSettings/>
|
||||
|
||||
@@ -173,47 +173,47 @@
|
||||
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
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||||
|
||||
<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="rm -rf" description="" id="xilinx.gnu.armv7.exe.release.1195692792" name="Release" parent="xilinx.gnu.armv7.exe.release" prebuildStep="a9-linaro-pre-build-step">
|
||||
<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="rm -rf" description="" id="xilinx.gnu.armv7.exe.release.184671342" name="Release" parent="xilinx.gnu.armv7.exe.release" prebuildStep="a9-linaro-pre-build-step">
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||||
|
||||
<folderInfo id="xilinx.gnu.armv7.exe.release.1195692792." name="/" resourcePath="">
|
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<folderInfo id="xilinx.gnu.armv7.exe.release.184671342." name="/" resourcePath="">
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|
||||
<toolChain id="xilinx.gnu.armv7.exe.release.toolchain.1206940423" name="Vitis ARM v7 GNU Toolchain" superClass="xilinx.gnu.armv7.exe.release.toolchain">
|
||||
<toolChain id="xilinx.gnu.armv7.exe.release.toolchain.1681504327" name="Vitis ARM v7 GNU Toolchain" superClass="xilinx.gnu.armv7.exe.release.toolchain">
|
||||
|
||||
<targetPlatform binaryParser="com.xilinx.sdk.managedbuilder.XELF.arm.a53.x32" id="xilinx.armv7.target.gnu.base.release.1750620231" isAbstract="false" name="Release Platform" superClass="xilinx.armv7.target.gnu.base.release"/>
|
||||
<targetPlatform binaryParser="com.xilinx.sdk.managedbuilder.XELF.arm.a53.x32" id="xilinx.armv7.target.gnu.base.release.607425787" isAbstract="false" name="Release Platform" superClass="xilinx.armv7.target.gnu.base.release"/>
|
||||
|
||||
<builder buildPath="${workspace_loc:/duifei_cmos}/Release" enableAutoBuild="true" id="xilinx.gnu.armv7.toolchain.builder.release.349472528" managedBuildOn="true" name="GNU make.Release" superClass="xilinx.gnu.armv7.toolchain.builder.release"/>
|
||||
<builder buildPath="${workspace_loc:/duifei_cmos}/Release" enableAutoBuild="true" id="xilinx.gnu.armv7.toolchain.builder.release.28406040" managedBuildOn="true" name="GNU make.Release" superClass="xilinx.gnu.armv7.toolchain.builder.release"/>
|
||||
|
||||
<tool id="xilinx.gnu.armv7.c.toolchain.assembler.release.1219354178" name="ARM v7 gcc assembler" superClass="xilinx.gnu.armv7.c.toolchain.assembler.release">
|
||||
<tool id="xilinx.gnu.armv7.c.toolchain.assembler.release.652493520" name="ARM v7 gcc assembler" superClass="xilinx.gnu.armv7.c.toolchain.assembler.release">
|
||||
|
||||
<inputType id="xilinx.gnu.assembler.input.1420679357" superClass="xilinx.gnu.assembler.input"/>
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||||
<inputType id="xilinx.gnu.assembler.input.201531030" superClass="xilinx.gnu.assembler.input"/>
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||||
|
||||
</tool>
|
||||
|
||||
<tool id="xilinx.gnu.armv7.c.toolchain.compiler.release.1800613106" name="ARM v7 gcc compiler" superClass="xilinx.gnu.armv7.c.toolchain.compiler.release">
|
||||
<tool id="xilinx.gnu.armv7.c.toolchain.compiler.release.1208724391" name="ARM v7 gcc compiler" superClass="xilinx.gnu.armv7.c.toolchain.compiler.release">
|
||||
|
||||
<option defaultValue="gnu.c.optimization.level.more" id="xilinx.gnu.compiler.option.optimization.level.340744156" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>
|
||||
<option defaultValue="gnu.c.optimization.level.more" id="xilinx.gnu.compiler.option.optimization.level.1979134276" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>
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||||
|
||||
<option id="xilinx.gnu.compiler.option.debugging.level.1784605729" superClass="xilinx.gnu.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.c.debugging.level.none" valueType="enumerated"/>
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||||
<option id="xilinx.gnu.compiler.option.debugging.level.1794124812" superClass="xilinx.gnu.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.c.debugging.level.none" valueType="enumerated"/>
|
||||
|
||||
<option id="xilinx.gnu.compiler.inferred.swplatform.includes.1301534353" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
|
||||
<option id="xilinx.gnu.compiler.inferred.swplatform.includes.842281809" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
|
||||
|
||||
<listOptionValue builtIn="false" value="${resolvePlatformFile:project=duifei_cmos,fileType=bspInclude}"/>
|
||||
|
||||
</option>
|
||||
|
||||
<option id="xilinx.gnu.compiler.misc.other.2076232636" superClass="xilinx.gnu.compiler.misc.other" value="-c -fmessage-length=0 -MT"$@" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard" valueType="string"/>
|
||||
<option id="xilinx.gnu.compiler.misc.other.260250884" superClass="xilinx.gnu.compiler.misc.other" value="-c -fmessage-length=0 -MT"$@" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard" valueType="string"/>
|
||||
|
||||
<inputType id="xilinx.gnu.armv7.c.compiler.input.144407802" name="C source files" superClass="xilinx.gnu.armv7.c.compiler.input"/>
|
||||
<inputType id="xilinx.gnu.armv7.c.compiler.input.75581125" name="C source files" superClass="xilinx.gnu.armv7.c.compiler.input"/>
|
||||
|
||||
</tool>
|
||||
|
||||
<tool id="xilinx.gnu.armv7.cxx.toolchain.compiler.release.238332506" name="ARM v7 g++ compiler" superClass="xilinx.gnu.armv7.cxx.toolchain.compiler.release">
|
||||
<tool id="xilinx.gnu.armv7.cxx.toolchain.compiler.release.109604626" name="ARM v7 g++ compiler" superClass="xilinx.gnu.armv7.cxx.toolchain.compiler.release">
|
||||
|
||||
<option defaultValue="gnu.c.optimization.level.more" id="xilinx.gnu.compiler.option.optimization.level.1090745445" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>
|
||||
<option defaultValue="gnu.c.optimization.level.more" id="xilinx.gnu.compiler.option.optimization.level.342666718" superClass="xilinx.gnu.compiler.option.optimization.level" valueType="enumerated"/>
|
||||
|
||||
<option id="xilinx.gnu.compiler.option.debugging.level.2131070934" superClass="xilinx.gnu.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.c.debugging.level.none" valueType="enumerated"/>
|
||||
<option id="xilinx.gnu.compiler.option.debugging.level.121164574" superClass="xilinx.gnu.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.c.debugging.level.none" valueType="enumerated"/>
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||||
|
||||
<option id="xilinx.gnu.compiler.inferred.swplatform.includes.1664917914" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
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||||
<option id="xilinx.gnu.compiler.inferred.swplatform.includes.76554455" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
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|
||||
<listOptionValue builtIn="false" value="${resolvePlatformFile:project=duifei_cmos,fileType=bspInclude}"/>
|
||||
|
||||
@@ -221,27 +221,27 @@
|
||||
|
||||
</tool>
|
||||
|
||||
<tool id="xilinx.gnu.armv7.toolchain.archiver.109932874" name="ARM v7 archiver" superClass="xilinx.gnu.armv7.toolchain.archiver"/>
|
||||
<tool id="xilinx.gnu.armv7.toolchain.archiver.1788110374" name="ARM v7 archiver" superClass="xilinx.gnu.armv7.toolchain.archiver"/>
|
||||
|
||||
<tool id="xilinx.gnu.armv7.c.toolchain.linker.release.321587554" name="ARM v7 gcc linker" superClass="xilinx.gnu.armv7.c.toolchain.linker.release">
|
||||
<tool id="xilinx.gnu.armv7.c.toolchain.linker.release.580636194" name="ARM v7 gcc linker" superClass="xilinx.gnu.armv7.c.toolchain.linker.release">
|
||||
|
||||
<option id="xilinx.gnu.linker.inferred.swplatform.lpath.1715686993" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
|
||||
<option id="xilinx.gnu.linker.inferred.swplatform.lpath.1323422293" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
|
||||
|
||||
<listOptionValue builtIn="false" value="${resolvePlatformFile:project=duifei_cmos,fileType=bspLib}"/>
|
||||
|
||||
</option>
|
||||
|
||||
<option id="xilinx.gnu.linker.inferred.swplatform.flags.2003479492" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
|
||||
<option id="xilinx.gnu.linker.inferred.swplatform.flags.1971254299" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
|
||||
|
||||
<listOptionValue builtIn="false" value="-Wl,--start-group,-lxil,-lgcc,-lc,--end-group"/>
|
||||
|
||||
</option>
|
||||
|
||||
<option id="xilinx.gnu.c.linker.option.lscript.1574668467" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
|
||||
<option id="xilinx.gnu.c.linker.option.lscript.355987481" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
|
||||
|
||||
<option id="xilinx.gnu.c.link.option.ldflags.1858673862" superClass="xilinx.gnu.c.link.option.ldflags" value=" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-build-id=none -specs=Xilinx.spec" valueType="string"/>
|
||||
<option id="xilinx.gnu.c.link.option.ldflags.1511301299" superClass="xilinx.gnu.c.link.option.ldflags" value=" -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-build-id=none -specs=Xilinx.spec" valueType="string"/>
|
||||
|
||||
<inputType id="xilinx.gnu.linker.input.851691832" superClass="xilinx.gnu.linker.input">
|
||||
<inputType id="xilinx.gnu.linker.input.1226165606" superClass="xilinx.gnu.linker.input">
|
||||
|
||||
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
|
||||
|
||||
@@ -249,29 +249,29 @@
|
||||
|
||||
</inputType>
|
||||
|
||||
<inputType id="xilinx.gnu.linker.input.lscript.1392921746" name="Linker Script" superClass="xilinx.gnu.linker.input.lscript"/>
|
||||
<inputType id="xilinx.gnu.linker.input.lscript.8217714" name="Linker Script" superClass="xilinx.gnu.linker.input.lscript"/>
|
||||
|
||||
</tool>
|
||||
|
||||
<tool id="xilinx.gnu.armv7.cxx.toolchain.linker.release.1619349892" name="ARM v7 g++ linker" superClass="xilinx.gnu.armv7.cxx.toolchain.linker.release">
|
||||
<tool id="xilinx.gnu.armv7.cxx.toolchain.linker.release.772831392" name="ARM v7 g++ linker" superClass="xilinx.gnu.armv7.cxx.toolchain.linker.release">
|
||||
|
||||
<option id="xilinx.gnu.linker.inferred.swplatform.lpath.285862495" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
|
||||
<option id="xilinx.gnu.linker.inferred.swplatform.lpath.1401846693" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
|
||||
|
||||
<listOptionValue builtIn="false" value="${resolvePlatformFile:project=duifei_cmos,fileType=bspLib}"/>
|
||||
|
||||
</option>
|
||||
|
||||
<option id="xilinx.gnu.linker.inferred.swplatform.flags.1819123554" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
|
||||
<option id="xilinx.gnu.linker.inferred.swplatform.flags.1263194462" superClass="xilinx.gnu.linker.inferred.swplatform.flags" valueType="libs">
|
||||
|
||||
<listOptionValue builtIn="false" value="-Wl,--start-group,-lxil,-lgcc,-lc,--end-group"/>
|
||||
|
||||
</option>
|
||||
|
||||
<option id="xilinx.gnu.c.linker.option.lscript.2050968881" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
|
||||
<option id="xilinx.gnu.c.linker.option.lscript.296625684" superClass="xilinx.gnu.c.linker.option.lscript" value="../src/lscript.ld" valueType="string"/>
|
||||
|
||||
</tool>
|
||||
|
||||
<tool id="xilinx.gnu.armv7.size.release.1090450355" name="ARM v7 Print Size" superClass="xilinx.gnu.armv7.size.release"/>
|
||||
<tool id="xilinx.gnu.armv7.size.release.1281028490" name="ARM v7 Print Size" superClass="xilinx.gnu.armv7.size.release"/>
|
||||
|
||||
</toolChain>
|
||||
|
||||
@@ -297,7 +297,7 @@
|
||||
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
|
||||
<project id="duifei_cmos.xilinx.gnu.armv7.exe.247172068" name="Vitis ARM v7 Executable" projectType="xilinx.gnu.armv7.exe"/>
|
||||
<project id="duifei_cmos.xilinx.gnu.armv7.exe.2041406573" name="Vitis ARM v7 Executable" projectType="xilinx.gnu.armv7.exe"/>
|
||||
|
||||
</storageModule>
|
||||
|
||||
@@ -305,25 +305,25 @@
|
||||
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
|
||||
<scannerConfigBuildInfo instanceId="xilinx.gnu.armv7.exe.debug.1922579181;xilinx.gnu.armv7.exe.debug.1922579181.">
|
||||
<scannerConfigBuildInfo instanceId="xilinx.gnu.armv7.exe.release.184671342;xilinx.gnu.armv7.exe.release.184671342.;xilinx.gnu.armv7.c.toolchain.compiler.release.1208724391;xilinx.gnu.armv7.c.compiler.input.75581125">
|
||||
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMA53X32GCCManagedMakePerProjectProfileC"/>
|
||||
|
||||
</scannerConfigBuildInfo>
|
||||
|
||||
<scannerConfigBuildInfo instanceId="xilinx.gnu.armv7.exe.release.1195692792;xilinx.gnu.armv7.exe.release.1195692792.">
|
||||
<scannerConfigBuildInfo instanceId="xilinx.gnu.armv7.exe.debug.860548130;xilinx.gnu.armv7.exe.debug.860548130.">
|
||||
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMA53X32GCCManagedMakePerProjectProfileC"/>
|
||||
|
||||
</scannerConfigBuildInfo>
|
||||
|
||||
<scannerConfigBuildInfo instanceId="xilinx.gnu.armv7.exe.release.1195692792;xilinx.gnu.armv7.exe.release.1195692792.;xilinx.gnu.armv7.c.toolchain.compiler.release.1800613106;xilinx.gnu.armv7.c.compiler.input.144407802">
|
||||
<scannerConfigBuildInfo instanceId="xilinx.gnu.armv7.exe.release.184671342;xilinx.gnu.armv7.exe.release.184671342.">
|
||||
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMA53X32GCCManagedMakePerProjectProfileC"/>
|
||||
|
||||
</scannerConfigBuildInfo>
|
||||
|
||||
<scannerConfigBuildInfo instanceId="xilinx.gnu.armv7.exe.debug.1922579181;xilinx.gnu.armv7.exe.debug.1922579181.;xilinx.gnu.armv7.c.toolchain.compiler.debug.340142942;xilinx.gnu.armv7.c.compiler.input.2110611050">
|
||||
<scannerConfigBuildInfo instanceId="xilinx.gnu.armv7.exe.debug.860548130;xilinx.gnu.armv7.exe.debug.860548130.;xilinx.gnu.armv7.c.toolchain.compiler.debug.870185296;xilinx.gnu.armv7.c.compiler.input.1499460340">
|
||||
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="com.xilinx.managedbuilder.ui.ARMA53X32GCCManagedMakePerProjectProfileC"/>
|
||||
|
||||
|
||||
BIN
Binary file not shown.
@@ -1 +1 @@
|
||||
2358263786
|
||||
2512825001
|
||||
+18
-21
@@ -16,8 +16,8 @@ proc ps7_pll_init_data_3_0 {} {
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x001452C0
|
||||
mask_write 0XF8000108 0x0007F000 0x0001E000
|
||||
mask_write 0XF8000118 0x003FFFF0 0x000FA240
|
||||
mask_write 0XF8000108 0x0007F000 0x00036000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
@@ -28,12 +28,11 @@ proc ps7_pll_init_data_3_0 {} {
|
||||
proc ps7_clock_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||
mask_write 0XF800014C 0x00003F31 0x00000501
|
||||
mask_write 0XF8000158 0x00003F33 0x00000601
|
||||
mask_write 0XF8000168 0x00003F31 0x00000501
|
||||
mask_write 0XF8000170 0x03F03F30 0x00200500
|
||||
mask_write 0XF800014C 0x00003F31 0x00000901
|
||||
mask_write 0XF8000168 0x00003F31 0x00000901
|
||||
mask_write 0XF8000170 0x03F03F30 0x00300600
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01CC400D
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01CC000D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_3_0 {} {
|
||||
@@ -184,8 +183,8 @@ proc ps7_pll_init_data_2_0 {} {
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x001452C0
|
||||
mask_write 0XF8000108 0x0007F000 0x0001E000
|
||||
mask_write 0XF8000118 0x003FFFF0 0x000FA240
|
||||
mask_write 0XF8000108 0x0007F000 0x00036000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
@@ -196,12 +195,11 @@ proc ps7_pll_init_data_2_0 {} {
|
||||
proc ps7_clock_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||
mask_write 0XF800014C 0x00003F31 0x00000501
|
||||
mask_write 0XF8000158 0x00003F33 0x00000601
|
||||
mask_write 0XF8000168 0x00003F31 0x00000501
|
||||
mask_write 0XF8000170 0x03F03F30 0x00200500
|
||||
mask_write 0XF800014C 0x00003F31 0x00000901
|
||||
mask_write 0XF8000168 0x00003F31 0x00000901
|
||||
mask_write 0XF8000170 0x03F03F30 0x00300600
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01CC400D
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01CC000D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_2_0 {} {
|
||||
@@ -353,8 +351,8 @@ proc ps7_pll_init_data_1_0 {} {
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x001452C0
|
||||
mask_write 0XF8000108 0x0007F000 0x0001E000
|
||||
mask_write 0XF8000118 0x003FFFF0 0x000FA240
|
||||
mask_write 0XF8000108 0x0007F000 0x00036000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
@@ -365,12 +363,11 @@ proc ps7_pll_init_data_1_0 {} {
|
||||
proc ps7_clock_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||
mask_write 0XF800014C 0x00003F31 0x00000501
|
||||
mask_write 0XF8000158 0x00003F33 0x00000601
|
||||
mask_write 0XF8000168 0x00003F31 0x00000501
|
||||
mask_write 0XF8000170 0x03F03F30 0x00200500
|
||||
mask_write 0XF800014C 0x00003F31 0x00000901
|
||||
mask_write 0XF8000168 0x00003F31 0x00000901
|
||||
mask_write 0XF8000170 0x03F03F30 0x00300600
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01CC400D
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01CC000D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_1_0 {} {
|
||||
|
||||
@@ -1,10 +1,10 @@
|
||||
<?xml version="1.0" encoding="ASCII"?>
|
||||
<sdkproject:SdkProject xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:sdkproject="http://www.xilinx.com/sdkproject" name="duifei_cmos" location="/home/josh/Workspace/vivado/vivado_pvt/projects/duifei/duifei_cmos_1t2r/vitis/duifei_cmos" platform="/home/josh/Workspace/vivado/vivado_pvt/projects/duifei/duifei_cmos_1t2r/vitis/duifei_platform/export/duifei_platform/duifei_platform.xpfm" platformUID="xilinx:::0.0(custom)" systemProject="duifei_cmos_system" sysConfig="duifei_platform" runtime="C/C++" cpu="standalone_domain" cpuInstance="ps7_cortexa9_0" os="standalone" mssSignature="dc4c634824bf159397371bd4302d29fe">
|
||||
<configuration name="Debug" id="xilinx.gnu.armv7.exe.debug.1922579181" dirty="true">
|
||||
<sdkproject:SdkProject xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:sdkproject="http://www.xilinx.com/sdkproject" name="duifei_cmos" location="/home/josh/Workspace/vivado/vivado_pvt/projects/duifei/duifei_cmos_1t2r/vitis/duifei_cmos" platform="/home/josh/Workspace/vivado/vivado_pvt/projects/duifei/duifei_cmos_1t2r/vitis/duifei_platform/export/duifei_platform/duifei_platform.xpfm" platformUID="xilinx:::0.0(custom)" systemProject="duifei_cmos_system" sysConfig="duifei_platform" runtime="C/C++" cpu="standalone_domain" cpuInstance="ps7_cortexa9_0" os="standalone" mssSignature="a06fc5f50fb58e7be39c2e24b733999d">
|
||||
<configuration name="Debug" id="xilinx.gnu.armv7.exe.debug.860548130">
|
||||
<configBuildOptions xsi:type="sdkproject:SdkOptions"/>
|
||||
<lastBuildOptions xsi:type="sdkproject:SdkOptions"/>
|
||||
</configuration>
|
||||
<configuration name="Release" id="xilinx.gnu.armv7.exe.release.1195692792" dirty="true">
|
||||
<configuration name="Release" id="xilinx.gnu.armv7.exe.release.184671342" dirty="true">
|
||||
<configBuildOptions xsi:type="sdkproject:SdkOptions"/>
|
||||
</configuration>
|
||||
<template appTemplateName="empty_application"/>
|
||||
|
||||
+128
@@ -0,0 +1,128 @@
|
||||
/***************************************************************************//**
|
||||
* @file ad9694.c
|
||||
* @brief Implementation of AD9680 Driver.
|
||||
* @author DBogdan ([email protected])
|
||||
********************************************************************************
|
||||
* Copyright 2014-2016(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
#include <stdlib.h>
|
||||
#include <stdio.h>
|
||||
#include "ad9694.h"
|
||||
#include "../../../include/error.h"
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief ad9694_read
|
||||
*******************************************************************************/
|
||||
int32_t ad9694_read(struct ad9694_dev *dev,
|
||||
uint16_t reg_addr,
|
||||
uint8_t *reg_data)
|
||||
{
|
||||
uint8_t tx_buf[2];
|
||||
uint8_t rx_buf[1];
|
||||
int32_t ret;
|
||||
|
||||
tx_buf[0] = 0x80 | (reg_addr >> 8);
|
||||
tx_buf[1] = reg_addr & 0xFF;
|
||||
|
||||
|
||||
ret = spi_write_and_read_3wire(dev->spi_desc,
|
||||
tx_buf, rx_buf, 2, 1);
|
||||
|
||||
*reg_data = rx_buf[0];
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief ad9694_write
|
||||
*******************************************************************************/
|
||||
int32_t ad9694_write(struct ad9694_dev *dev,
|
||||
uint16_t reg_addr,
|
||||
uint8_t reg_data)
|
||||
{
|
||||
uint8_t buf[3];
|
||||
|
||||
int32_t ret;
|
||||
|
||||
buf[0] = reg_addr >> 8;
|
||||
buf[1] = reg_addr & 0xFF;
|
||||
buf[2] = reg_data;
|
||||
|
||||
ret = spi_write_and_read_3wire(dev->spi_desc,
|
||||
buf, NULL, 3, 0);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief ad9694_init
|
||||
*******************************************************************************/
|
||||
int32_t ad9694_init(struct ad9694_dev **device,
|
||||
const struct ad9694_init_param *init_param)
|
||||
{
|
||||
int ret = SUCCESS;
|
||||
struct ad9694_dev *dev;
|
||||
|
||||
dev = (struct ad9694_dev *)malloc(sizeof(*dev));
|
||||
if (!dev)
|
||||
return FAILURE;
|
||||
|
||||
/* SPI */
|
||||
ret = spi_init(&dev->spi_desc, init_param->spi_init);
|
||||
|
||||
*device = dev;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief Free the resources allocated by ad9694_setup().
|
||||
*
|
||||
* @param dev - The device structure.
|
||||
*
|
||||
* @return SUCCESS in case of success, negative error code otherwise.
|
||||
*******************************************************************************/
|
||||
int32_t ad9694_remove(struct ad9694_dev *dev)
|
||||
{
|
||||
int32_t ret;
|
||||
|
||||
ret = spi_remove(dev->spi_desc);
|
||||
|
||||
free(dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
+231
@@ -0,0 +1,231 @@
|
||||
/***************************************************************************//**
|
||||
* @file ad9694.h
|
||||
* @brief Header file of AD9694 Driver.
|
||||
* @author DBogdan ([email protected])
|
||||
********************************************************************************
|
||||
* Copyright 2014-2016(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
#ifndef AD9694_H_
|
||||
#define AD9694_H_
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
#include <stdint.h>
|
||||
#include "../../../include/delay.h"
|
||||
#include "../../../include/spi.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/********************** Macros and Constants Definitions **********************/
|
||||
/******************************************************************************/
|
||||
#define AD9694_REG_GLOBAL_MAP_SPI_CONF_A 0x0000
|
||||
#define AD9694_REG_GLOBAL_MAP_SPI_CONF_B 0x0001
|
||||
#define AD9694_REG_CH_MAP_CHIP_CONF 0x0002
|
||||
#define AD9694_REG_PAIR_MAP_CHIP_TYPE 0x0003
|
||||
#define AD9694_REG_PAIR_MAP_CHIP_ID_LSB 0x0004
|
||||
#define AD9694_REG_PAIR_MAP_CHIP_GRADE 0x0006
|
||||
#define AD9694_REG_PAIR_MAP_DEV_INDEX 0x0008
|
||||
#define AD9694_REG_GLOBAL_MAP_PAIR_INDEX 0x0009
|
||||
#define AD9694_REG_PAIR_MAP_SCRATCH_PAD 0x000A
|
||||
#define AD9694_REG_PAIR_MAP_SPI_REVISION 0x000B
|
||||
#define AD9694_REG_PAIR_MAP_VENDOR_ID_LSB 0x000C
|
||||
#define AD9694_REG_PAIR_MAP_VENDOR_ID_MSB 0x000D
|
||||
#define AD9694_REG_CH_MAP_CHIP_PD_PIN 0x003F
|
||||
#define AD9694_REG_PAIR_MAP_CHIP_PIN_CTRL_1 0x0040
|
||||
#define AD9694_REG_PAIR_MAP_CLK_DIV_CTRL 0x0108
|
||||
#define AD9694_REG_CH_MAP_CLK_DIV_PHASE 0x0109
|
||||
#define AD9694_REG_PAIR_MAP_CLK_DIV_SYSREF_CTRL 0x010A
|
||||
#define AD9694_REG_PAIR_MAP_CLK_DELAY_CTRL 0x0110
|
||||
#define AD9694_REG_CH_MAP_CLK_SUPER_FINE_DELAY 0x0111
|
||||
#define AD9694_REG_CH_MAP_CLK_FINE_DELAY 0x0112
|
||||
#define AD9694_REG_CLK_DETN_CTRL 0x011A
|
||||
#define AD9694_REG_PAIR_MAP_CLK_STAT 0x011B
|
||||
#define AD9694_REG_CLK_DCS_CTRL_1 0x011C
|
||||
#define AD9694_REG_CLK_DCS_CTRL_2 0x011E
|
||||
#define AD9694_REG_CLK_DCS_CTRL_3 0x011F
|
||||
#define AD9694_REG_PAIR_MAP_SYSREF_CTRL_1 0x0120
|
||||
#define AD9694_REG_PAIR_MAP_SYSREF_CTRL_2 0x0121
|
||||
#define AD9694_REG_PAIR_MAP_SYSREF_CTRL_4 0x0123
|
||||
#define AD9694_REG_PAIR_MAP_SYSREF_STAT_1 0x0128
|
||||
#define AD9694_REG_PAIR_MAP_SYSREF_STAT_2 0x0129
|
||||
#define AD9694_REG_PAIR_MAP_SYSREF_STAT_3 0x012A
|
||||
#define AD9694_REG_PAIR_MAP_CHIP_SYNC 0x01FF
|
||||
#define AD9694_REG_PAIR_MAP_CHIP_MODE 0x0200
|
||||
#define AD9694_REG_PAIR_MAP_CHIP_DEC_RATIO 0x0201
|
||||
#define AD9694_REG_CH_MAP_CUSTOM_OFFSET 0x0228
|
||||
#define AD9694_REG_CH_MAP_FD_CTRL 0x0245
|
||||
#define AD9694_REG_CH_MAP_FD_UT_LSB 0x0247
|
||||
#define AD9694_REG_CH_MAP_FD_UT_MSB 0x0248
|
||||
#define AD9694_REG_CH_MAP_FD_LT_LSB 0x0249
|
||||
#define AD9694_REG_CH_MAP_FD_LT_MSB 0x024A
|
||||
#define AD9694_REG_CH_MAP_FD_DWELL_TIME_LSB 0x024B
|
||||
#define AD9694_REG_CH_MAP_FD_DWELL_TIME_MSB 0x024C
|
||||
#define AD9694_REG_PAIR_MAP_SIG_MON_SYNC_CTRL 0x026F
|
||||
#define AD9694_REG_CH_MAP_SIG_MON_CTRL 0x0270
|
||||
#define AD9694_REG_CH_MAP_SIG_MON_PERIOD_0 0x0271
|
||||
#define AD9694_REG_CH_MAP_SIG_MON_PERIOD_1 0x0272
|
||||
#define AD9694_REG_CH_MAP_SIG_MON_PERIOD_2 0x0273
|
||||
#define AD9694_REG_CH_MAP_SIG_MON_STAT_CTRL 0x0274
|
||||
#define AD9694_REG_CH_MAP_SIG_MON_STAT_0 0x0275
|
||||
#define AD9694_REG_CH_MAP_SIG_MON_STAT_1 0x0276
|
||||
#define AD9694_REG_CH_MAP_SIG_MON_STAT_2 0x0277
|
||||
#define AD9694_REG_CH_MAP_SIG_MON_STAT_FRAME_CNT 0x0278
|
||||
#define AD9694_REG_CH_MAP_SIG_MON_SERIAL_FRAMER_CTRL 0x0279
|
||||
#define AD9694_REG_SPORT_OVER_JESD204B_INPUT_SEL 0x027A
|
||||
#define AD9694_REG_PAIR_MAP_DDC_SYNC_CTRL 0x0300
|
||||
#define AD9694_REG_PAIR_MAP_DDC_0_CTRL 0x0310
|
||||
#define AD9694_REG_PAIR_MAP_DDC_0_INPUT_SEL 0x0311
|
||||
#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_0 0x0314
|
||||
#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_1 0x0315
|
||||
#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_2 0x0316
|
||||
#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_3 0x0317
|
||||
#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_4 0x0318
|
||||
#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_5 0x031A
|
||||
#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_0 0x031D
|
||||
#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_1 0x031E
|
||||
#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_2 0x031F
|
||||
#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_3 0x0320
|
||||
#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_4 0x0321
|
||||
#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_5 0x0322
|
||||
#define AD9694_REG_PAIR_MAP_DDC_0_TEST_ENABLE 0x0327
|
||||
#define AD9694_REG_PAIR_MAP_DDC_1_CTRL 0x0330
|
||||
#define AD9694_REG_PAIR_MAP_DDC_1_INPUT_SEL 0x0331
|
||||
#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_0 0x0334
|
||||
#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_1 0x0335
|
||||
#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_2 0x0336
|
||||
#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_3 0x0337
|
||||
#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_4 0x0338
|
||||
#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_5 0x033A
|
||||
#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_0 0x033D
|
||||
#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_1 0x033E
|
||||
#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_2 0x033F
|
||||
#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_3 0x0340
|
||||
#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_4 0x0341
|
||||
#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_5 0x0342
|
||||
#define AD9694_REG_PAIR_MAP_DDC_1_TEST_ENABLE 0x0347
|
||||
#define AD9694_REG_CH_MAP_TEST_MODE_CTRL 0x0550
|
||||
#define AD9694_REG_PAIR_MAP_USER_PATTERN_1_LSB 0x0551
|
||||
#define AD9694_REG_PAIR_MAP_USER_PATTERN_1_MSB 0x0552
|
||||
#define AD9694_REG_PAIR_MAP_USER_PATTERN_2_LSB 0x0553
|
||||
#define AD9694_REG_PAIR_MAP_USER_PATTERN_2_MSB 0x0554
|
||||
#define AD9694_REG_PAIR_MAP_USER_PATTERN_3_LSB 0x0555
|
||||
#define AD9694_REG_PAIR_MAP_USER_PATTERN_3_MSB 0x0556
|
||||
#define AD9694_REG_PAIR_MAP_USER_PATTERN_4_LSB 0x0557
|
||||
#define AD9694_REG_PAIR_MAP_USER_PATTERN_4_MSB 0x0558
|
||||
#define AD9694_REG_PAIR_MAP_OUTPUT_CTRL_MODE_0 0x0559
|
||||
#define AD9694_REG_PAIR_MAP_OUTPUT_CTRL_MODE_1 0x055A
|
||||
#define AD9694_REG_PAIR_MAP_OUTPUT_SAMPLE_MODE 0x0561
|
||||
#define AD9694_REG_PAIR_MAP_OUTPUT_CH_SEL 0x0564
|
||||
#define AD9694_REG_JESD204B_MAP_PLL_CTRL 0x056E
|
||||
#define AD9694_REG_JESD204B_MAP_PLL_STAT 0x056F
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_QUICK_CONF 0x0570
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_LINK_CTRL_1 0x0571
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_LINK_CTRL_2 0x0572
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_LINK_CTRL_3 0x0573
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_LINK_CTRL_4 0x0574
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_LMFC_OFFSET 0x0578
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_DID_CONF 0x0580
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_BID_CONF 0x0581
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_LID_0_CONF 0x0583
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_LID_1_CONF 0x0585
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_SCR_L_CONF 0x058B
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_F_CONF 0x058C
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_K_CONF 0x058D
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_M_CONF 0x058E
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_CS_N_CONF 0x058F
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_SUBCLASS_CONF 0x0590
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_S_CONF 0x0591
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_HD_CF_CONF 0x0592
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_CHECKSUM_0_CONF 0x05A0
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_CHECKSUM_1_CONF 0x05A1
|
||||
#define AD9694_REG_SERDOUTX0_SERDOUTX1_LANE_PD 0x05B0
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_LANE_ASSIGN_1 0x05B2
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_LANE_ASSIGN_2 0x05B3
|
||||
#define AD9694_REG_JESD204B_MAP_SERD_ADJUST_0 0x05C0
|
||||
#define AD9694_REG_JESD204B_MAP_SERD_ADJUST_1 0x05C1
|
||||
#define AD9694_REG_JESD204B_SER_PE_SEL_LANE_0 0x05C4
|
||||
#define AD9694_REG_JESD204B_SER_PE_SEL_LANE_1 0x05C6
|
||||
#define AD9694_REG_LARGE_DITHER_CTRL 0x0922
|
||||
#define AD9694_REG_PLL_CAL 0x1222
|
||||
#define AD9694_REG_JESD204B_STARTUP_CIRCUIT_RST 0x1228
|
||||
#define AD9694_REG_PLL_LOSS_OF_LOCK_CTRL 0x1262
|
||||
#define AD9694_REG_DC_OFFSET_CAL_CTRL 0x0701
|
||||
#define AD9694_REG_DC_OFFSET_CAL_CTRL_2 0x073B
|
||||
#define AD9694_REG_PAIR_MAP_VREF_CTRL 0x18A6
|
||||
#define AD9694_REG_EXT_VCM_BUF_CTRL_1 0x18E0
|
||||
#define AD9694_REG_EXT_VCM_BUF_CTRL_2 0x18E1
|
||||
#define AD9694_REG_EXT_VCM_BUF_CTRL_3 0x18E2
|
||||
#define AD9694_REG_EXT_VCM_BUF_CTRL 0x18E3
|
||||
#define AD9694_REG_TEMP_DIODE_EXPORT 0x18E6
|
||||
#define AD9694_REG_CH_MAP_ANALOG_INPUT_CTRL 0x1908
|
||||
#define AD9694_REG_CH_MAP_INPUT_FULLSCALE_RANGE 0x1910
|
||||
#define AD9694_REG_CH_MAP_BUF_CTRL_1 0x1A4C
|
||||
#define AD9694_REG_CH_MAP_BUF_CTRL_2 0x1A4D
|
||||
|
||||
/******************************************************************************/
|
||||
/*************************** Types Declarations *******************************/
|
||||
/******************************************************************************/
|
||||
struct ad9694_dev {
|
||||
/* SPI */
|
||||
spi_desc *spi_desc;
|
||||
};
|
||||
|
||||
struct ad9694_init_param {
|
||||
/* SPI */
|
||||
spi_init_param *spi_init;
|
||||
};
|
||||
|
||||
struct ad9694_config {
|
||||
uint16_t addr;
|
||||
uint8_t value;
|
||||
};
|
||||
|
||||
/******************************************************************************/
|
||||
/************************ Functions Declarations ******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
int32_t ad9694_read(struct ad9694_dev *dev,
|
||||
uint16_t reg_addr,
|
||||
uint8_t *reg_data);
|
||||
|
||||
int32_t ad9694_write(struct ad9694_dev *dev,
|
||||
uint16_t reg_addr,
|
||||
uint8_t reg_data);
|
||||
|
||||
int32_t ad9694_init(struct ad9694_dev **device,
|
||||
const struct ad9694_init_param *init_param);
|
||||
|
||||
int32_t ad9694_remove(struct ad9694_dev *dev);
|
||||
|
||||
#endif
|
||||
+184
@@ -0,0 +1,184 @@
|
||||
/***************************************************************************//**
|
||||
* @file gpio.c
|
||||
* @brief Implementation of the GPIO Interface
|
||||
* @author Antoniu Miclaus ([email protected])
|
||||
********************************************************************************
|
||||
* Copyright 2020(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
#include <inttypes.h>
|
||||
#include <stdlib.h>
|
||||
#include "../../include/gpio.h"
|
||||
#include "../../include/error.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/************************ Functions Definitions *******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief Obtain the GPIO decriptor.
|
||||
* @param desc - The GPIO descriptor.
|
||||
* @param param - GPIO Initialization parameters.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t gpio_get(struct gpio_desc **desc,
|
||||
const struct gpio_init_param *param)
|
||||
{
|
||||
if (!param)
|
||||
return FAILURE;
|
||||
|
||||
if ((param->platform_ops->gpio_ops_get(desc, param)))
|
||||
return FAILURE;
|
||||
|
||||
(*desc)->platform_ops = param->platform_ops;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the value of an optional GPIO.
|
||||
* @param desc - The GPIO descriptor.
|
||||
* @param param - GPIO Initialization parameters.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t gpio_get_optional(struct gpio_desc **desc,
|
||||
const struct gpio_init_param *param)
|
||||
{
|
||||
if (!param || (param->number == -1)) {
|
||||
*desc = NULL;
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
if ((param->platform_ops->gpio_ops_get_optional(desc, param)))
|
||||
return FAILURE;
|
||||
|
||||
(*desc)->platform_ops = param->platform_ops;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
/**
|
||||
* @brief Free the resources allocated by gpio_get().
|
||||
* @param desc - The GPIO descriptor.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t gpio_remove(struct gpio_desc *desc)
|
||||
{
|
||||
if (desc)
|
||||
return desc->platform_ops->gpio_ops_remove(desc);
|
||||
else
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the input direction of the specified GPIO.
|
||||
* @param desc - The GPIO descriptor.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t gpio_direction_input(struct gpio_desc *desc)
|
||||
{
|
||||
if (desc)
|
||||
return desc->platform_ops->gpio_ops_direction_input(desc);
|
||||
else
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the output direction of the specified GPIO.
|
||||
* @param desc - The GPIO descriptor.
|
||||
* @param value - The value.
|
||||
* Example: GPIO_HIGH
|
||||
* GPIO_LOW
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t gpio_direction_output(struct gpio_desc *desc,
|
||||
uint8_t value)
|
||||
{
|
||||
if (desc)
|
||||
return desc->platform_ops->
|
||||
gpio_ops_direction_output(desc, value);
|
||||
else
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the direction of the specified GPIO.
|
||||
* @param desc - The GPIO descriptor.
|
||||
* @param direction - The direction.
|
||||
* Example: GPIO_OUT
|
||||
* GPIO_IN
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t gpio_get_direction(struct gpio_desc *desc,
|
||||
uint8_t *direction)
|
||||
{
|
||||
if (desc)
|
||||
return desc->platform_ops->
|
||||
gpio_ops_get_direction(desc, direction);
|
||||
else
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the value of the specified GPIO.
|
||||
* @param desc - The GPIO descriptor.
|
||||
* @param value - The value.
|
||||
* Example: GPIO_HIGH
|
||||
* GPIO_LOW
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t gpio_set_value(struct gpio_desc *desc,
|
||||
uint8_t value)
|
||||
{
|
||||
if (desc)
|
||||
return desc->platform_ops->gpio_ops_set_value(desc, value);
|
||||
else
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the value of the specified GPIO.
|
||||
* @param desc - The GPIO descriptor.
|
||||
* @param value - The value.
|
||||
* Example: GPIO_HIGH
|
||||
* GPIO_LOW
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t gpio_get_value(struct gpio_desc *desc,
|
||||
uint8_t *value)
|
||||
{
|
||||
if (desc)
|
||||
return desc->platform_ops->gpio_ops_get_value(desc, value);
|
||||
else
|
||||
return SUCCESS;
|
||||
}
|
||||
+153
@@ -0,0 +1,153 @@
|
||||
/***************************************************************************//**
|
||||
* @file irq.c
|
||||
* @brief Implementation of the IRQ Interface
|
||||
* @author Andrei Porumb ([email protected])
|
||||
********************************************************************************
|
||||
* Copyright 2021(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
#include <inttypes.h>
|
||||
#include <stdlib.h>
|
||||
#include "../../include/irq.h"
|
||||
#include "../../include/error.h"
|
||||
|
||||
/**
|
||||
* @brief Initialize the IRQ interrupts.
|
||||
* @param desc - The IRQ descriptor.
|
||||
* @param param - The structure that contains the IRQ parameters.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t irq_ctrl_init(struct irq_ctrl_desc **desc,
|
||||
const struct irq_init_param *param)
|
||||
{
|
||||
if (!param)
|
||||
return FAILURE;
|
||||
|
||||
if ((param->platform_ops->init(desc, param)))
|
||||
return FAILURE;
|
||||
|
||||
(*desc)->platform_ops = param->platform_ops;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Free the resources allocated by irq_ctrl_init().
|
||||
* @param desc - The SPI descriptor.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t irq_ctrl_remove(struct irq_ctrl_desc *desc)
|
||||
{
|
||||
return desc->platform_ops->remove(desc);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Register a callback to handle the irq events.
|
||||
* @param desc - The IRQ controller descriptor.
|
||||
* @param irq_id - Interrupt identifier.
|
||||
* @param callback_desc - Callback descriptor
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t irq_register_callback(struct irq_ctrl_desc *desc, uint32_t irq_id,
|
||||
struct callback_desc *callback_desc)
|
||||
{
|
||||
return desc->platform_ops->register_callback(desc, irq_id, callback_desc);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Unregisters a generic IRQ handling function.
|
||||
* @param desc - The IRQ controller descriptor.
|
||||
* @param irq_id - Interrupt identifier.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t irq_unregister(struct irq_ctrl_desc *desc, uint32_t irq_id)
|
||||
{
|
||||
return desc->platform_ops->unregister(desc, irq_id);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable global interrupts.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t irq_global_enable(struct irq_ctrl_desc *desc)
|
||||
{
|
||||
return desc->platform_ops->global_enable(desc);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable global interrupts.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t irq_global_disable(struct irq_ctrl_desc *desc)
|
||||
{
|
||||
return desc->platform_ops->global_disable(desc);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set interrupt trigger level.
|
||||
* @param desc - The IRQ controller descriptor.
|
||||
* @param irq_id - Interrupt identifier.
|
||||
* @param trig - New trigger level for the interrupt.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t irq_trigger_level_set(struct irq_ctrl_desc *desc, uint32_t irq_id,
|
||||
enum irq_trig_level trig)
|
||||
{
|
||||
if(desc->platform_ops->trigger_level_set)
|
||||
return desc->platform_ops->trigger_level_set(desc, irq_id, trig);
|
||||
else
|
||||
return ENOSYS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable specific interrupt.
|
||||
* @param desc - The IRQ controller descriptor.
|
||||
* @param irq_id - Interrupt identifier.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t irq_enable(struct irq_ctrl_desc *desc, uint32_t irq_id)
|
||||
{
|
||||
return desc->platform_ops->enable(desc, irq_id);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable specific interrupt.
|
||||
* @param desc - The IRQ controller descriptor.
|
||||
* @param irq_id - Interrupt identifier.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t irq_disable(struct irq_ctrl_desc *desc, uint32_t irq_id)
|
||||
{
|
||||
return desc->platform_ops->disable(desc, irq_id);
|
||||
}
|
||||
+144
@@ -0,0 +1,144 @@
|
||||
/***************************************************************************//**
|
||||
* @file spi.c
|
||||
* @brief Implementation of the SPI Interface
|
||||
* @author Antoniu Miclaus ([email protected])
|
||||
********************************************************************************
|
||||
* Copyright 2020(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
#include <inttypes.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include "../../include/spi.h"
|
||||
#include "../../include/error.h"
|
||||
|
||||
/**
|
||||
* @brief Initialize the SPI communication peripheral.
|
||||
* @param desc - The SPI descriptor.
|
||||
* @param param - The structure that contains the SPI parameters.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t spi_init(struct spi_desc **desc,
|
||||
const struct spi_init_param *param)
|
||||
{
|
||||
if (!param)
|
||||
return FAILURE;
|
||||
|
||||
if ((param->platform_ops->init(desc, param)))
|
||||
return FAILURE;
|
||||
|
||||
(*desc)->platform_ops = param->platform_ops;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Free the resources allocated by spi_init().
|
||||
* @param desc - The SPI descriptor.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t spi_remove(struct spi_desc *desc)
|
||||
{
|
||||
return desc->platform_ops->remove(desc);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write and read data to/from SPI.
|
||||
* @param desc - The SPI descriptor.
|
||||
* @param data - The buffer with the transmitted/received data.
|
||||
* @param bytes_number - Number of bytes to write/read.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t spi_write_and_read(struct spi_desc *desc,
|
||||
uint8_t *data,
|
||||
uint16_t bytes_number)
|
||||
{
|
||||
return desc->platform_ops->write_and_read(desc, data, bytes_number);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write and read data to/from SPI in 3 wire mode.
|
||||
* @param desc - The SPI descriptor.
|
||||
* @param write_data - The buffer with the transmitted data.
|
||||
* @param read_data - The buffer with the received data.
|
||||
* @param write_bytes_number - Number of bytes to write.
|
||||
* @param read_bytes_number - Number of bytes to read.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t spi_write_and_read_3wire(struct spi_desc *desc,
|
||||
uint8_t *write_data,
|
||||
uint8_t *read_data,
|
||||
uint16_t write_bytes_number,
|
||||
uint16_t read_bytes_number)
|
||||
{
|
||||
int ret;
|
||||
if(desc->platform_ops->write_and_read_3wire != NULL){
|
||||
return desc->platform_ops->write_and_read_3wire(desc, write_data, read_data,
|
||||
write_bytes_number, read_bytes_number);
|
||||
}
|
||||
else{
|
||||
return FAILURE;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Iterate over head list and send all spi messages
|
||||
* @param desc - The SPI descriptor.
|
||||
* @param msgs - Array of messages.
|
||||
* @param len - Number of messages in the array.
|
||||
* @return SUCCESS in case of success, negativ error code otherwise.
|
||||
*/
|
||||
int32_t spi_transfer(struct spi_desc *desc, struct spi_msg *msgs, uint32_t len)
|
||||
{
|
||||
int32_t ret;
|
||||
uint32_t i;
|
||||
|
||||
if (!desc || !desc->platform_ops)
|
||||
return -EINVAL;
|
||||
|
||||
if (desc->platform_ops->transfer)
|
||||
return desc->platform_ops->transfer(desc, msgs, len);
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
if (msgs[i].rx_buff != msgs[i].tx_buff || !msgs[i].tx_buff)
|
||||
return -EINVAL;
|
||||
ret = spi_write_and_read(desc, msgs[i].rx_buff,
|
||||
msgs[i].bytes_number);
|
||||
if (IS_ERR_VALUE(ret))
|
||||
return ret;
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
+328
@@ -0,0 +1,328 @@
|
||||
/***************************************************************************//**
|
||||
* @file axi_dmac.c
|
||||
* @brief Driver for the Analog Devices AXI-DMAC core.
|
||||
* @author DBogdan ([email protected])
|
||||
********************************************************************************
|
||||
* Copyright 2018(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
#include <stdlib.h>
|
||||
#include <stdio.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include "../../../include/axi_io.h"
|
||||
#include "../../../include/error.h"
|
||||
#include "../axi_dmac/axi_dmac.h"
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief dma_isr
|
||||
*******************************************************************************/
|
||||
void axi_dmac_default_isr(void *instance)
|
||||
{
|
||||
struct axi_dmac *dmac = (struct axi_dmac *)instance;
|
||||
uint32_t remaining_size, burst_size;
|
||||
uint32_t reg_val;
|
||||
|
||||
/* Get interrupt sources and clear interrupts. */
|
||||
axi_dmac_read(dmac, AXI_DMAC_REG_IRQ_PENDING, ®_val);
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_PENDING, reg_val);
|
||||
|
||||
if ((reg_val & AXI_DMAC_IRQ_SOT) && (dmac->big_transfer.size != 0)) {
|
||||
remaining_size = dmac->big_transfer.size -
|
||||
dmac->big_transfer.size_done;
|
||||
burst_size = (remaining_size <= dmac->transfer_max_size) ?
|
||||
remaining_size : dmac->transfer_max_size;
|
||||
|
||||
dmac->big_transfer.size_done += burst_size;
|
||||
dmac->big_transfer.address += burst_size;
|
||||
switch (dmac->direction) {
|
||||
case DMA_DEV_TO_MEM:
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS,
|
||||
dmac->big_transfer.address);
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_DEST_STRIDE, 0x0);
|
||||
break;
|
||||
case DMA_MEM_TO_DEV:
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS,
|
||||
dmac->big_transfer.address);
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_SRC_STRIDE, 0x0);
|
||||
break;
|
||||
default:
|
||||
return; // Other directions are not supported yet
|
||||
}
|
||||
/* The current transfer was started and a new one is queued. */
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH,
|
||||
burst_size);
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0);
|
||||
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1);
|
||||
}
|
||||
if (reg_val & AXI_DMAC_IRQ_EOT) {
|
||||
dmac->big_transfer.transfer_done = true;
|
||||
dmac->big_transfer.address = 0;
|
||||
dmac->big_transfer.size = 0;
|
||||
dmac->big_transfer.size_done = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief axi_dmac_read
|
||||
*******************************************************************************/
|
||||
int32_t axi_dmac_read(struct axi_dmac *dmac,
|
||||
uint32_t reg_addr,
|
||||
uint32_t *reg_data)
|
||||
{
|
||||
axi_io_read(dmac->base, reg_addr, reg_data);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief axi_dmac_write
|
||||
*******************************************************************************/
|
||||
int32_t axi_dmac_write(struct axi_dmac *dmac,
|
||||
uint32_t reg_addr,
|
||||
uint32_t reg_data)
|
||||
{
|
||||
axi_io_write(dmac->base, reg_addr, reg_data);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief axi_dmac_transfer_nonblock
|
||||
*******************************************************************************/
|
||||
int32_t axi_dmac_transfer_nonblocking(struct axi_dmac *dmac,
|
||||
uint32_t address, uint32_t size)
|
||||
{
|
||||
uint32_t reg_val;
|
||||
|
||||
if (size == 0)
|
||||
return SUCCESS; /* nothing to do */
|
||||
|
||||
axi_dmac_read(dmac, AXI_DMAC_REG_CTRL, ®_val);
|
||||
if (!(reg_val & AXI_DMAC_CTRL_ENABLE)) {
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, 0x0);
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, AXI_DMAC_CTRL_ENABLE);
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_MASK, 0x0);
|
||||
}
|
||||
|
||||
axi_dmac_read(dmac, AXI_DMAC_REG_START_TRANSFER, ®_val);
|
||||
if (!(reg_val & 1)) {
|
||||
switch (dmac->direction) {
|
||||
case DMA_DEV_TO_MEM:
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS, address);
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_DEST_STRIDE, 0x0);
|
||||
break;
|
||||
case DMA_MEM_TO_DEV:
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS, address);
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_SRC_STRIDE, 0x0);
|
||||
break;
|
||||
default:
|
||||
return FAILURE; // Other directions are not supported yet
|
||||
}
|
||||
if ((size - 1) > dmac->transfer_max_size) {
|
||||
dmac->big_transfer.address = address;
|
||||
dmac->big_transfer.size = size - 1;
|
||||
dmac->big_transfer.size_done = dmac->transfer_max_size;
|
||||
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH,
|
||||
dmac->transfer_max_size);
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0);
|
||||
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, dmac->flags);
|
||||
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1);
|
||||
} else {
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH,
|
||||
size - 1);
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0);
|
||||
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, dmac->flags);
|
||||
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1);
|
||||
}
|
||||
} else {
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief axi_dmac_is_transfer_ready
|
||||
*******************************************************************************/
|
||||
int32_t axi_dmac_is_transfer_ready(struct axi_dmac *dmac, bool *rdy)
|
||||
{
|
||||
*rdy = dmac->big_transfer.transfer_done;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief axi_dmac_transfer
|
||||
*******************************************************************************/
|
||||
int32_t axi_dmac_transfer(struct axi_dmac *dmac,
|
||||
uint32_t address, uint32_t size)
|
||||
{
|
||||
uint32_t transfer_id;
|
||||
uint32_t reg_val;
|
||||
uint32_t timeout = 0;
|
||||
|
||||
if (size == 0)
|
||||
return SUCCESS; /* nothing to do */
|
||||
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, 0x0);
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, AXI_DMAC_CTRL_ENABLE);
|
||||
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_MASK, 0x0);
|
||||
|
||||
axi_dmac_read(dmac, AXI_DMAC_REG_TRANSFER_ID, &transfer_id);
|
||||
axi_dmac_read(dmac, AXI_DMAC_REG_IRQ_PENDING, ®_val);
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_PENDING, reg_val);
|
||||
|
||||
switch (dmac->direction) {
|
||||
case DMA_DEV_TO_MEM:
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS, address);
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_DEST_STRIDE, 0x0);
|
||||
break;
|
||||
case DMA_MEM_TO_DEV:
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS, address);
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_SRC_STRIDE, 0x0);
|
||||
break;
|
||||
default:
|
||||
return FAILURE; // Other directions are not supported yet
|
||||
}
|
||||
|
||||
if ((size - 1) > dmac->transfer_max_size) {
|
||||
dmac->big_transfer.address = address;
|
||||
dmac->big_transfer.size = size - 1;
|
||||
dmac->big_transfer.size_done = dmac->transfer_max_size;
|
||||
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH,
|
||||
dmac->transfer_max_size);
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0);
|
||||
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, dmac->flags);
|
||||
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1);
|
||||
|
||||
while(!dmac->big_transfer.transfer_done) {
|
||||
timeout++;
|
||||
if (timeout == UINT32_MAX)
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
dmac->big_transfer.address = 0;
|
||||
dmac->big_transfer.size = 0;
|
||||
dmac->big_transfer.size_done = 0;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, size - 1);
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0);
|
||||
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, dmac->flags);
|
||||
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1);
|
||||
|
||||
if (dmac->flags & DMA_CYCLIC)
|
||||
return SUCCESS;
|
||||
|
||||
/* Wait until the new transfer is queued. */
|
||||
do {
|
||||
axi_dmac_read(dmac, AXI_DMAC_REG_START_TRANSFER, ®_val);
|
||||
} while(reg_val == 1);
|
||||
|
||||
/* Wait until the current transfer is completed. */
|
||||
do {
|
||||
axi_dmac_read(dmac, AXI_DMAC_REG_IRQ_PENDING, ®_val);
|
||||
if (reg_val == (AXI_DMAC_IRQ_SOT | AXI_DMAC_IRQ_EOT))
|
||||
break;
|
||||
} while(!dmac->big_transfer.transfer_done);
|
||||
if (reg_val != (AXI_DMAC_IRQ_SOT | AXI_DMAC_IRQ_EOT))
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_PENDING, reg_val);
|
||||
|
||||
/* Wait until the transfer with the ID transfer_id is completed. */
|
||||
do {
|
||||
axi_dmac_read(dmac, AXI_DMAC_REG_TRANSFER_DONE, ®_val);
|
||||
} while((reg_val & (1u << transfer_id)) != (1u << transfer_id));
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief axi_dmac_init
|
||||
*******************************************************************************/
|
||||
int32_t axi_dmac_init(struct axi_dmac **dmac_core,
|
||||
const struct axi_dmac_init *init)
|
||||
{
|
||||
struct axi_dmac *dmac;
|
||||
|
||||
dmac = (struct axi_dmac *)malloc(sizeof(*dmac));
|
||||
if (!dmac)
|
||||
return FAILURE;
|
||||
|
||||
dmac->name = init->name;
|
||||
dmac->base = init->base;
|
||||
dmac->direction = init->direction;
|
||||
dmac->flags = init->flags;
|
||||
dmac->transfer_max_size = -1;
|
||||
dmac->big_transfer.address = 0;
|
||||
dmac->big_transfer.size = 0;
|
||||
dmac->big_transfer.size_done = 0;
|
||||
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, dmac->transfer_max_size);
|
||||
axi_dmac_read(dmac, AXI_DMAC_REG_X_LENGTH, &dmac->transfer_max_size);
|
||||
|
||||
*dmac_core = dmac;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief axi_dmac_remove
|
||||
*******************************************************************************/
|
||||
int32_t axi_dmac_remove(struct axi_dmac *dmac)
|
||||
{
|
||||
if(!dmac)
|
||||
return FAILURE;
|
||||
|
||||
free(dmac);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
+124
@@ -0,0 +1,124 @@
|
||||
/***************************************************************************//**
|
||||
* @file axi_dmac.h
|
||||
* @brief Driver for the Analog Devices AXI-DMAC core.
|
||||
* @author DBogdan ([email protected])
|
||||
********************************************************************************
|
||||
* Copyright 2018(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
#ifndef AXI_DMAC_H_
|
||||
#define AXI_DMAC_H_
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
#include <stdint.h>
|
||||
#include "../../../include/util.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/********************** Macros and Constants Definitions **********************/
|
||||
/******************************************************************************/
|
||||
#define AXI_DMAC_REG_IRQ_MASK 0x80
|
||||
#define AXI_DMAC_REG_IRQ_PENDING 0x84
|
||||
#define AXI_DMAC_IRQ_SOT BIT(0)
|
||||
#define AXI_DMAC_IRQ_EOT BIT(1)
|
||||
|
||||
#define AXI_DMAC_REG_CTRL 0x400
|
||||
#define AXI_DMAC_CTRL_ENABLE BIT(0)
|
||||
#define AXI_DMAC_CTRL_PAUSE BIT(1)
|
||||
|
||||
#define AXI_DMAC_REG_TRANSFER_ID 0x404
|
||||
#define AXI_DMAC_REG_START_TRANSFER 0x408
|
||||
#define AXI_DMAC_REG_FLAGS 0x40c
|
||||
#define AXI_DMAC_REG_DEST_ADDRESS 0x410
|
||||
#define AXI_DMAC_REG_SRC_ADDRESS 0x414
|
||||
#define AXI_DMAC_REG_X_LENGTH 0x418
|
||||
#define AXI_DMAC_REG_Y_LENGTH 0x41c
|
||||
#define AXI_DMAC_REG_DEST_STRIDE 0x420
|
||||
#define AXI_DMAC_REG_SRC_STRIDE 0x424
|
||||
#define AXI_DMAC_REG_TRANSFER_DONE 0x428
|
||||
|
||||
/******************************************************************************/
|
||||
/*************************** Types Declarations *******************************/
|
||||
/******************************************************************************/
|
||||
enum dma_direction {
|
||||
DMA_DEV_TO_MEM,
|
||||
DMA_MEM_TO_DEV
|
||||
};
|
||||
|
||||
enum dma_flags {
|
||||
DMA_CYCLIC = 1,
|
||||
DMA_LAST = 2
|
||||
};
|
||||
|
||||
struct axi_dma_transfer {
|
||||
uint32_t size;
|
||||
uint32_t address;
|
||||
uint32_t size_done;
|
||||
volatile bool transfer_done;
|
||||
};
|
||||
|
||||
struct axi_dmac {
|
||||
const char *name;
|
||||
uint32_t base;
|
||||
enum dma_direction direction;
|
||||
uint32_t flags;
|
||||
uint32_t transfer_max_size;
|
||||
volatile struct axi_dma_transfer big_transfer;
|
||||
};
|
||||
|
||||
struct axi_dmac_init {
|
||||
const char *name;
|
||||
uint32_t base;
|
||||
enum dma_direction direction;
|
||||
uint32_t flags;
|
||||
};
|
||||
|
||||
/******************************************************************************/
|
||||
/************************ Functions Declarations ******************************/
|
||||
/******************************************************************************/
|
||||
void axi_dmac_default_isr(void *instance);
|
||||
int32_t axi_dmac_read(struct axi_dmac *dmac, uint32_t reg_addr,
|
||||
uint32_t *reg_data);
|
||||
int32_t axi_dmac_write(struct axi_dmac *dmac, uint32_t reg_addr,
|
||||
uint32_t reg_data);
|
||||
int32_t axi_dmac_transfer_nonblocking(struct axi_dmac *dmac,
|
||||
uint32_t address, uint32_t size);
|
||||
int32_t axi_dmac_is_transfer_ready(struct axi_dmac *dmac, bool *rdy);
|
||||
int32_t axi_dmac_transfer(struct axi_dmac *dmac,
|
||||
uint32_t address, uint32_t size);
|
||||
int32_t axi_dmac_init(struct axi_dmac **adc_core,
|
||||
const struct axi_dmac_init *init);
|
||||
int32_t axi_dmac_remove(struct axi_dmac *dmac);
|
||||
|
||||
#endif
|
||||
+978
@@ -0,0 +1,978 @@
|
||||
/*******************************************************************************
|
||||
* @file spi_engine.c
|
||||
* @brief Core implementation of the SPI Engine Driver.
|
||||
* @author Sergiu Cuciurean ([email protected])
|
||||
********************************************************************************
|
||||
* Copyright 2019(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/* In debug mode the printf function used in displaying the messages is causing
|
||||
significant delays */
|
||||
//#define DEBUG_LEVEL 2
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <sleep.h>
|
||||
#include <inttypes.h>
|
||||
|
||||
#include "spi_engine.h"
|
||||
#include "../axi_dmac/axi_dmac.h"
|
||||
#include "../../../include/axi_io.h"
|
||||
#include "../../../include/error.h"
|
||||
|
||||
/**
|
||||
* @brief Spi engine platform specific SPI platform ops structure
|
||||
*/
|
||||
const struct spi_platform_ops spi_eng_platform_ops = {
|
||||
.init = &spi_engine_init,
|
||||
.write_and_read = &spi_engine_spi_write_and_read,
|
||||
.write_and_read_3wire = &spi_engine_spi_write_and_read_3wire,
|
||||
.remove = &spi_engine_remove
|
||||
};
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Static variables *******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief Static variable used to sync transfers
|
||||
*
|
||||
*/
|
||||
static uint8_t _sync_id = 0x01;
|
||||
|
||||
/******************************************************************************/
|
||||
/************************** Functions Implementation **************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief Write SPI Engine's axi registers
|
||||
*
|
||||
* @param desc Decriptor containing SPI Engine's parameters
|
||||
* @param reg_addr The address of the SPI Engine's axi register where the data
|
||||
* will be written
|
||||
* @param reg_data Data that will be written
|
||||
* @return int32_t This function allways returns SUCCESS
|
||||
*/
|
||||
int32_t spi_engine_write(struct spi_engine_desc *desc,
|
||||
uint32_t reg_addr,
|
||||
uint32_t reg_data)
|
||||
{
|
||||
axi_io_write(desc->spi_engine_baseaddr, reg_addr, reg_data);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read SPI Engine's axi registers
|
||||
*
|
||||
* @param desc Decriptor containing SPI Engine's parameters
|
||||
* @param reg_addr The address of the SPI Engine's axi register from where the
|
||||
* data where the data will be read
|
||||
* @param reg_data Pointer where the read that will be stored
|
||||
* @return int32_t This function allways returns SUCCESS
|
||||
*/
|
||||
int32_t spi_engine_read(struct spi_engine_desc *desc,
|
||||
uint32_t reg_addr,
|
||||
uint32_t *reg_data)
|
||||
{
|
||||
axi_io_read(desc->spi_engine_baseaddr, reg_addr, reg_data);
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set width of the transferred word over SPI
|
||||
*
|
||||
* @param desc Decriptor containing SPI interface parameters
|
||||
* @param data_width The desired data width
|
||||
* The supported values are:
|
||||
* - 8
|
||||
* - 16
|
||||
* - 24
|
||||
* - 32
|
||||
*/
|
||||
int32_t spi_engine_set_transfer_width(struct spi_desc *desc,
|
||||
uint8_t data_width)
|
||||
{
|
||||
struct spi_engine_desc *desc_extra;
|
||||
|
||||
desc_extra = desc->extra;
|
||||
|
||||
if (data_width > desc_extra->max_data_width)
|
||||
desc_extra->data_width = desc_extra->max_data_width;
|
||||
else
|
||||
desc_extra->data_width = data_width;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set SPI engine clock frequency
|
||||
*
|
||||
* @param desc Decriptor containing SPI Engine's parameters
|
||||
* @param speed_hz SPI engine transfer speed
|
||||
*/
|
||||
void spi_engine_set_speed(struct spi_desc *desc,
|
||||
uint32_t speed_hz)
|
||||
{
|
||||
struct spi_engine_desc *desc_extra;
|
||||
|
||||
desc_extra = desc->extra;
|
||||
|
||||
desc_extra->clk_div = desc_extra->ref_clk_hz /
|
||||
(2 * speed_hz) - 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the number of words transferred in a single transaction
|
||||
*
|
||||
* @param desc Decriptor containing SPI Engine's parameters
|
||||
* @param bytes_number The number of bytes to be converted
|
||||
* @return uint8_t A number of words in which bytes_number can be grouped
|
||||
*/
|
||||
static uint8_t spi_get_words_number(struct spi_engine_desc *desc,
|
||||
uint8_t bytes_number)
|
||||
{
|
||||
uint8_t xfer_word_len;
|
||||
uint8_t words_number;
|
||||
|
||||
xfer_word_len = desc->data_width / 8;
|
||||
words_number = bytes_number / xfer_word_len;
|
||||
|
||||
if ((bytes_number % xfer_word_len) != 0)
|
||||
words_number++;
|
||||
|
||||
return words_number;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the word length in bytes
|
||||
*
|
||||
* @param desc Decriptor containing SPI Engine's parameters
|
||||
* @return uint8_t Number of bytes that fit in one word
|
||||
*/
|
||||
static uint8_t spi_get_word_length(struct spi_engine_desc *desc)
|
||||
{
|
||||
uint8_t word_length;
|
||||
|
||||
word_length = desc->data_width / 8;
|
||||
|
||||
return word_length;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Compute the prescaler used to set the sleep period.
|
||||
*
|
||||
* @param desc Decriptor containing SPI interface parameters
|
||||
* @param sleep_time_ns The amount of time where the transfer hangs
|
||||
* @param sleep_div Clock prescaler
|
||||
* @return int32_t This function allways returns SUCCESS
|
||||
*/
|
||||
static int32_t spi_get_sleep_div(struct spi_desc *desc,
|
||||
uint32_t sleep_time_ns,
|
||||
uint32_t *sleep_div)
|
||||
{
|
||||
struct spi_engine_desc *eng_desc;
|
||||
|
||||
eng_desc = desc->extra;
|
||||
|
||||
/*
|
||||
* Engine Wiki:
|
||||
*
|
||||
* The frequency of the SCLK signal is derived from the
|
||||
* module clock frequency using the following formula:
|
||||
* f_sclk = f_clk / ((div + 1) * 2)
|
||||
*/
|
||||
|
||||
*sleep_div = (desc->max_speed_hz / 1000000 * sleep_time_ns / 1000) /
|
||||
((eng_desc->clk_div + 1) * 2) - 1;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Create a new commands queue used in a spi transfer
|
||||
*
|
||||
* @param fifo Command buffer, usually used in fifo mode
|
||||
* @param cmd Command with witch the buffer will be initiated
|
||||
* @return int32_t Failure if the memory allocation failed
|
||||
*/
|
||||
static int32_t spi_engine_queue_new_cmd(struct spi_engine_cmd_queue **fifo,
|
||||
uint32_t cmd)
|
||||
{
|
||||
struct spi_engine_cmd_queue *local_fifo;
|
||||
|
||||
local_fifo = (spi_engine_cmd_queue*)malloc(sizeof(*local_fifo));
|
||||
|
||||
if(!local_fifo)
|
||||
return FAILURE;
|
||||
|
||||
local_fifo->cmd = cmd;
|
||||
local_fifo->next = NULL;
|
||||
*fifo = local_fifo;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Add a command at the end of an existing queue
|
||||
*
|
||||
* @param fifo Command buffer, usually used in fifo mode
|
||||
* @param cmd Command to be added
|
||||
*/
|
||||
static void spi_engine_queue_add_cmd(struct spi_engine_cmd_queue **fifo,
|
||||
uint32_t cmd)
|
||||
{
|
||||
struct spi_engine_cmd_queue *to_add = NULL;
|
||||
struct spi_engine_cmd_queue *local_fifo;
|
||||
|
||||
local_fifo = *fifo;
|
||||
while (local_fifo->next != NULL) {
|
||||
// Get the last element
|
||||
local_fifo = local_fifo->next;
|
||||
}
|
||||
|
||||
// Create a new element
|
||||
spi_engine_queue_new_cmd(&to_add, cmd);
|
||||
// Add as the next element
|
||||
local_fifo->next = to_add;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Add a command at the beginning of an existing queue
|
||||
*
|
||||
* @param fifo Command buffer, usually used in fifo mode
|
||||
* @param cmd Command to be added
|
||||
*/
|
||||
static void spi_engine_queue_append_cmd(struct spi_engine_cmd_queue **fifo,
|
||||
uint32_t cmd)
|
||||
{
|
||||
struct spi_engine_cmd_queue *to_add = NULL;
|
||||
|
||||
// Create a new element
|
||||
spi_engine_queue_new_cmd(&to_add, cmd);
|
||||
// Interchange the addresses
|
||||
to_add->next = *fifo;
|
||||
*fifo = to_add;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get the command from the beginning of the queue
|
||||
*
|
||||
* @param fifo Command buffer, usually used in fifo mode
|
||||
* @param cmd Value of the command that was extracted
|
||||
* @return int32_t Return FAILURE if the queue is empty
|
||||
*/
|
||||
static int32_t spi_engine_queue_get_cmd(struct spi_engine_cmd_queue **fifo,
|
||||
uint32_t *cmd)
|
||||
{
|
||||
struct spi_engine_cmd_queue *local_fifo;
|
||||
|
||||
if (!*fifo)
|
||||
return FAILURE;
|
||||
|
||||
local_fifo = *fifo;
|
||||
*cmd = local_fifo->cmd;
|
||||
if ((*fifo)->next) {
|
||||
*fifo = local_fifo->next;
|
||||
free(local_fifo);
|
||||
} else {
|
||||
free(*fifo);
|
||||
*fifo = NULL;
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Free the memory allocated by a queue
|
||||
*
|
||||
* @param fifo The queue that needs it's memory freed
|
||||
* @return int32_t This function allways return SUCCESS
|
||||
*/
|
||||
static int32_t spi_engine_queue_free(struct spi_engine_cmd_queue **fifo)
|
||||
{
|
||||
if(*fifo && (*fifo)->next)
|
||||
spi_engine_queue_free(&(*fifo)->next);
|
||||
if((*fifo) != NULL) {
|
||||
free(*fifo);
|
||||
*fifo = NULL;
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write the SPI engine's command fifo
|
||||
*
|
||||
* @param desc Decriptor containing SPI Engine's parameters
|
||||
* @param cmd The command that will be written
|
||||
* @return int32_t Returns FAILURE if the the axi transfer failed
|
||||
*/
|
||||
static int32_t spi_engine_write_cmd_reg(struct spi_engine_desc *desc,
|
||||
uint32_t cmd)
|
||||
{
|
||||
int32_t ret;
|
||||
|
||||
/* Check if offload is enabled */
|
||||
if(desc->offload_config & (OFFLOAD_TX_EN | OFFLOAD_RX_EN)) {
|
||||
ret = spi_engine_write(desc,
|
||||
SPI_ENGINE_REG_OFFLOAD_CMD_MEM(0),
|
||||
cmd);
|
||||
|
||||
} else {
|
||||
ret = spi_engine_write(desc,
|
||||
SPI_ENGINE_REG_CMD_FIFO,
|
||||
cmd);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write a transfer command to the SPI engine's command fifo
|
||||
*
|
||||
* @param desc Decriptor containing SPI Engine's parameters
|
||||
* @param read_write Read/Write operation flag
|
||||
* @param bytes_number Number of bytes to transfer
|
||||
* @return int32_t This function allways returns SUCCESS
|
||||
*/
|
||||
static int32_t spi_engine_transfer(struct spi_engine_desc *desc,
|
||||
uint8_t read_write,
|
||||
uint8_t bytes_number)
|
||||
{
|
||||
uint8_t words_number;
|
||||
|
||||
words_number = spi_get_words_number(desc, bytes_number);
|
||||
|
||||
desc->offload_tx_len += words_number;
|
||||
|
||||
/*
|
||||
* Engine Wiki:
|
||||
*
|
||||
* https://wiki.analog.com/resources/fpga/peripherals/spi_engine
|
||||
*
|
||||
* The words number is zero based
|
||||
*/
|
||||
|
||||
spi_engine_write_cmd_reg(desc,
|
||||
SPI_ENGINE_CMD_TRANSFER(read_write,
|
||||
words_number - 1));
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Change the state of the chip select port
|
||||
*
|
||||
* @param desc Decriptor containing SPI interface parameters
|
||||
* @param assert Chip select state.
|
||||
* The supported values are :
|
||||
* -true (HIGH)
|
||||
* -false (LOW)
|
||||
*/
|
||||
static void spi_engine_set_cs(struct spi_desc *desc,
|
||||
bool assert)
|
||||
{
|
||||
uint8_t mask;
|
||||
struct spi_engine_desc *eng_desc;
|
||||
|
||||
eng_desc = desc->extra;
|
||||
|
||||
mask = 0xFF;
|
||||
/* Switch the state only of the selected chip select */
|
||||
if (!assert)
|
||||
mask ^= BIT(desc->chip_select);
|
||||
|
||||
spi_engine_write_cmd_reg(eng_desc,
|
||||
SPI_ENGINE_CMD_ASSERT(eng_desc->cs_delay,
|
||||
mask));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Add a delay between the engine commands
|
||||
*
|
||||
* @param desc Decriptor containing SPI interface parameters
|
||||
* @param sleep_time_ns Number of nanoseconds to sleep between commands
|
||||
*/
|
||||
static void spi_gen_sleep_ns(struct spi_desc *desc,
|
||||
uint32_t sleep_time_ns)
|
||||
{
|
||||
uint32_t sleep_div;
|
||||
struct spi_engine_desc *eng_desc;
|
||||
|
||||
eng_desc = desc->extra;
|
||||
|
||||
spi_get_sleep_div(desc, sleep_time_ns, &sleep_div);
|
||||
|
||||
spi_engine_write_cmd_reg(eng_desc, SPI_ENGINE_CMD_SLEEP(sleep_div));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Spi engine command interpreter
|
||||
*
|
||||
* @param desc Decriptor containing SPI interface parameters
|
||||
* @param cmd Command to send to the engine
|
||||
* @return int32_t - SUCCESS if the command is transferred
|
||||
* - FAILURE if the command format is invalid
|
||||
*/
|
||||
static int32_t spi_engine_write_cmd(struct spi_desc *desc,
|
||||
uint32_t cmd)
|
||||
{
|
||||
uint8_t engine_command;
|
||||
uint8_t parameter;
|
||||
uint8_t modifier;
|
||||
struct spi_engine_desc *desc_extra;
|
||||
|
||||
desc_extra = desc->extra;
|
||||
|
||||
engine_command = (cmd >> 12) & 0x0F;
|
||||
modifier = (cmd >> 8) & 0x0F;
|
||||
parameter = cmd & 0xFF;
|
||||
|
||||
switch(engine_command) {
|
||||
case SPI_ENGINE_INST_TRANSFER:
|
||||
spi_engine_transfer(desc_extra, modifier, parameter);
|
||||
break;
|
||||
|
||||
case SPI_ENGINE_INST_ASSERT:
|
||||
if(parameter == 0xFF) {
|
||||
/* Set the CS HIGH */
|
||||
spi_engine_set_cs(desc, true);
|
||||
} else if(parameter == 0x00) {
|
||||
/* Set the CS LOW */
|
||||
spi_engine_set_cs(desc, false);
|
||||
}
|
||||
break;
|
||||
|
||||
/* The SYNC and SLEEP commands got the same value but different
|
||||
modifier */
|
||||
case SPI_ENGINE_INST_SYNC_SLEEP:
|
||||
/* SYNC instruction */
|
||||
if(modifier == 0x00) {
|
||||
spi_engine_write_cmd_reg(desc_extra, cmd);
|
||||
} else if(modifier == 0x01) {
|
||||
spi_gen_sleep_ns(desc, parameter);
|
||||
}
|
||||
break;
|
||||
case SPI_ENGINE_INST_CONFIG:
|
||||
spi_engine_write_cmd_reg(desc_extra, cmd);
|
||||
|
||||
break;
|
||||
|
||||
default:
|
||||
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Prepare the command queue before sending it to the engine
|
||||
*
|
||||
* @param desc Decriptor containing SPI interface parameters
|
||||
* @param msg Structure used to store the transfer messages
|
||||
* @return int32_t This function allways returns SUCCESS
|
||||
*/
|
||||
static int32_t spi_engine_compile_message(struct spi_desc *desc,
|
||||
struct spi_engine_msg *msg)
|
||||
{
|
||||
struct spi_engine_desc *desc_extra;
|
||||
|
||||
desc_extra = desc->extra;
|
||||
|
||||
/* Configure the prescaler */
|
||||
spi_engine_queue_append_cmd(&msg->cmds,
|
||||
SPI_ENGINE_CMD_CONFIG(
|
||||
SPI_ENGINE_CMD_REG_CLK_DIV,
|
||||
desc_extra->clk_div));
|
||||
|
||||
/* Set the data transfer length */
|
||||
spi_engine_queue_append_cmd(&msg->cmds,
|
||||
SPI_ENGINE_CMD_CONFIG(
|
||||
SPI_ENGINE_CMD_DATA_TRANSFER_LEN,
|
||||
desc_extra->data_width));
|
||||
/*
|
||||
* Configure the spi mode :
|
||||
* - 3 wire
|
||||
* - CPOL
|
||||
* - CPHA
|
||||
*/
|
||||
spi_engine_queue_append_cmd(&msg->cmds,
|
||||
SPI_ENGINE_CMD_CONFIG(
|
||||
SPI_ENGINE_CMD_REG_CONFIG,
|
||||
desc->mode));
|
||||
|
||||
/* Add a sync command to signal that the transfer has finished */
|
||||
spi_engine_queue_add_cmd(&msg->cmds, SPI_ENGINE_CMD_SYNC(_sync_id));
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initiate a spi transfer (Blocking)
|
||||
*
|
||||
* @param desc Decriptor containing SPI interface parameters
|
||||
* @param msg Structure used to store the transfer messages
|
||||
* @return int32_t - SUCCESS if the transfer finished
|
||||
* - FAILURE if the memory allocation failed
|
||||
*/
|
||||
static int32_t spi_engine_transfer_message(struct spi_desc *desc,
|
||||
struct spi_engine_msg *msg)
|
||||
{
|
||||
uint32_t i;
|
||||
uint32_t data;
|
||||
uint32_t sync_id;
|
||||
bool offload_en;
|
||||
struct spi_engine_desc *desc_extra;
|
||||
|
||||
desc_extra = desc->extra;
|
||||
|
||||
spi_engine_compile_message(desc, msg);
|
||||
|
||||
offload_en = (desc_extra->offload_config & OFFLOAD_TX_EN) |
|
||||
(desc_extra->offload_config & OFFLOAD_RX_EN);
|
||||
|
||||
/* Write the command fifo buffer */
|
||||
while(msg->cmds != NULL) {
|
||||
spi_engine_queue_get_cmd(&msg->cmds, &data);
|
||||
spi_engine_write_cmd(desc, data);
|
||||
}
|
||||
|
||||
/* Write a number of tx_length WORDS on the SDO line */
|
||||
if(offload_en) {
|
||||
for(i = 0; i < desc_extra->offload_tx_len; i++)
|
||||
spi_engine_write(desc_extra,
|
||||
SPI_ENGINE_REG_OFFLOAD_SDO_MEM(0),
|
||||
msg->tx_buf[i]);
|
||||
|
||||
} else {
|
||||
if(msg->tx_buf != NULL){
|
||||
for(i = 0; i < msg->tx_length; i++)
|
||||
spi_engine_write(desc_extra,
|
||||
SPI_ENGINE_REG_SDO_DATA_FIFO,
|
||||
msg->tx_buf[i]);
|
||||
}
|
||||
do {
|
||||
spi_engine_read(desc_extra,
|
||||
SPI_ENGINE_REG_SYNC_ID,
|
||||
&sync_id);
|
||||
}
|
||||
/* Wait for the end sync signal */
|
||||
while(sync_id != _sync_id);
|
||||
_sync_id++;
|
||||
|
||||
/* Read a number of rx_length WORDS from the SDI line and store
|
||||
them */
|
||||
for(i = 0; i < msg->rx_length; i++) {
|
||||
spi_engine_read(desc_extra,
|
||||
SPI_ENGINE_REG_SDI_DATA_FIFO,
|
||||
&data);
|
||||
/* Store the rx data if rx buffer valid, flush sdi_fifo if
|
||||
rx buffer is invalid.*/
|
||||
if(msg->rx_buf != NULL){
|
||||
msg->rx_buf[i] = data;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the spi engine
|
||||
*
|
||||
* @param desc Decriptor containing SPI interface parameters
|
||||
* @param param Structure containing the spi init parameters
|
||||
* @return int32_t - SUCCESS if the transfer finished
|
||||
* - FAILURE if the memory allocation failed
|
||||
*/
|
||||
int32_t spi_engine_init(struct spi_desc **desc,
|
||||
const struct spi_init_param *param)
|
||||
{
|
||||
uint32_t data_width = 0;
|
||||
uint32_t spi_engine_version = 0;
|
||||
struct spi_engine_desc *eng_desc;
|
||||
struct spi_engine_init_param *spi_engine_init;
|
||||
|
||||
if (!param) {
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
*desc = malloc(sizeof(**desc));
|
||||
if(! *desc) {
|
||||
free(*desc);
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
eng_desc = (struct spi_engine_desc*)malloc(sizeof(*eng_desc));
|
||||
|
||||
if (!eng_desc)
|
||||
return FAILURE;
|
||||
|
||||
spi_engine_init = param->extra;
|
||||
|
||||
(*desc)->max_speed_hz = param->max_speed_hz;
|
||||
(*desc)->chip_select = param->chip_select;
|
||||
(*desc)->mode = param->mode;
|
||||
(*desc)->extra = eng_desc;
|
||||
|
||||
eng_desc->offload_config = OFFLOAD_DISABLED;
|
||||
eng_desc->spi_engine_baseaddr = spi_engine_init->spi_engine_baseaddr;
|
||||
eng_desc->type = spi_engine_init->type;
|
||||
eng_desc->cs_delay = spi_engine_init->cs_delay;
|
||||
eng_desc->ref_clk_hz = spi_engine_init->ref_clk_hz;
|
||||
eng_desc->clk_div = eng_desc->ref_clk_hz /
|
||||
(2 * param->max_speed_hz) - 1;
|
||||
|
||||
/* Perform a reset */
|
||||
spi_engine_write(eng_desc, SPI_ENGINE_REG_RESET, 0x01);
|
||||
usleep(1000);
|
||||
spi_engine_write(eng_desc, SPI_ENGINE_REG_RESET, 0x00);
|
||||
|
||||
/* Get current data width */
|
||||
spi_engine_read(eng_desc, SPI_ENGINE_REG_DATA_WIDTH, &data_width);
|
||||
eng_desc->max_data_width = data_width;
|
||||
|
||||
spi_engine_set_transfer_width(*desc, spi_engine_init->data_width);
|
||||
|
||||
/* Get spi engine version */
|
||||
spi_engine_read(eng_desc, SPI_ENGINE_REG_VERSION, &spi_engine_version);
|
||||
|
||||
printf("Spi engine v%"PRIu32".%"PRIu32".%"PRIu32" successfully initialized.\n",
|
||||
(spi_engine_version >> 16),
|
||||
((spi_engine_version >> 8) & 0xFF),
|
||||
(spi_engine_version & 0xFF));
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write and read on the spi interface in 4-wire mode (full-duplex)
|
||||
*
|
||||
* @param desc Decriptor containing SPI interface parameters
|
||||
* @param data Pointer to data buffer
|
||||
* @param bytes_number Number of bytes to transfer
|
||||
* @return int32_t - SUCCESS if the transfer finished
|
||||
* - FAILURE if the memory allocation or transfer failed
|
||||
*/
|
||||
int32_t spi_engine_spi_write_and_read(struct spi_desc *desc,
|
||||
uint8_t *data,
|
||||
uint16_t bytes_number)
|
||||
{
|
||||
uint8_t word_len;
|
||||
uint8_t words_number;
|
||||
int32_t ret;
|
||||
struct spi_engine_msg msg;
|
||||
struct spi_engine_desc *desc_extra;
|
||||
|
||||
desc_extra = desc->extra;
|
||||
|
||||
/* If we want to access SPI interface and SPI engine offload module was
|
||||
* activated, we need to disable it
|
||||
* This is set in spi_engine_offload_init() */
|
||||
desc_extra->offload_config = OFFLOAD_DISABLED;
|
||||
/* This is set in spi_engine_offload_transfer() */
|
||||
spi_engine_write(desc_extra, SPI_ENGINE_REG_OFFLOAD_CTRL(0), 0);
|
||||
|
||||
words_number = spi_get_words_number(desc_extra, bytes_number);
|
||||
|
||||
msg.cmds = (spi_engine_cmd_queue*)malloc(sizeof(*msg.cmds));
|
||||
if (!msg.cmds)
|
||||
return FAILURE;
|
||||
|
||||
msg.tx_buf =(uint32_t*)calloc(words_number, sizeof(msg.tx_buf[0]));
|
||||
msg.rx_buf =(uint32_t*)calloc(words_number, sizeof(msg.rx_buf[0]));
|
||||
msg.tx_length = words_number;
|
||||
msg.rx_length = words_number;
|
||||
|
||||
/* Get the length of transferred word */
|
||||
word_len = spi_get_word_length(desc_extra);
|
||||
|
||||
/* Make sure the CS is HIGH before starting a transaction */
|
||||
msg.cmds->next = NULL;
|
||||
msg.cmds->cmd = CS_HIGH;
|
||||
// Assert select.
|
||||
spi_engine_queue_add_cmd(&msg.cmds, CS_LOW);
|
||||
// add read/write command
|
||||
spi_engine_queue_add_cmd(&msg.cmds, WRITE_READ(bytes_number));
|
||||
// Disable select.
|
||||
spi_engine_queue_add_cmd(&msg.cmds, CS_HIGH);
|
||||
|
||||
/* Pack the bytes into engine WORDS */
|
||||
for (int i = 0; i < bytes_number; i++)
|
||||
msg.tx_buf[i / word_len] |= data[i] << (desc_extra->data_width-
|
||||
(i % word_len + 1) * 8);
|
||||
|
||||
ret = spi_engine_transfer_message(desc, &msg);
|
||||
|
||||
for (int i = 0; i < bytes_number; i++)
|
||||
data[i] = msg.rx_buf[(i) / word_len] >>
|
||||
(desc_extra->data_width -
|
||||
((i) % word_len + 1) * 8);
|
||||
|
||||
spi_engine_queue_free(&msg.cmds);
|
||||
free(msg.tx_buf);
|
||||
free(msg.rx_buf);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write and read on the spi interface in 3-wire mode (half-duplex)
|
||||
*
|
||||
* @param desc Decriptor containing SPI interface parameters
|
||||
* @param data Pointer to data buffer
|
||||
* @param bytes_number Number of bytes to transfer
|
||||
* @return int32_t - SUCCESS if the transfer finished
|
||||
* - FAILURE if the memory allocation or transfer failed
|
||||
*/
|
||||
int32_t spi_engine_spi_write_and_read_3wire(struct spi_desc *desc,
|
||||
uint8_t *write_data,
|
||||
uint8_t *read_data,
|
||||
uint16_t write_bytes_number,
|
||||
uint16_t read_bytes_number)
|
||||
{
|
||||
uint8_t word_len;
|
||||
uint8_t wr_words_number;
|
||||
uint8_t rd_words_number;
|
||||
int32_t ret;
|
||||
struct spi_engine_msg msg;
|
||||
struct spi_engine_desc *desc_extra;
|
||||
|
||||
desc_extra = desc->extra;
|
||||
|
||||
/* If we want to access SPI interface and SPI engine offload module was
|
||||
* activated, we need to disable it
|
||||
* This is set in spi_engine_offload_init() */
|
||||
desc_extra->offload_config = OFFLOAD_DISABLED;
|
||||
/* This is set in spi_engine_offload_transfer() */
|
||||
spi_engine_write(desc_extra, SPI_ENGINE_REG_OFFLOAD_CTRL(0), 0);
|
||||
|
||||
wr_words_number = spi_get_words_number(desc_extra, write_bytes_number);
|
||||
rd_words_number = spi_get_words_number(desc_extra, read_bytes_number);
|
||||
|
||||
msg.cmds = (spi_engine_cmd_queue*)malloc(sizeof(*msg.cmds));
|
||||
if (!msg.cmds)
|
||||
return FAILURE;
|
||||
|
||||
msg.tx_buf =(wr_words_number>0)?(uint32_t*)calloc(wr_words_number, sizeof(msg.tx_buf[0])):NULL;
|
||||
msg.rx_buf =(rd_words_number>0)?(uint32_t*)calloc(rd_words_number, sizeof(msg.rx_buf[0])):NULL;
|
||||
msg.tx_length = wr_words_number;
|
||||
msg.rx_length = rd_words_number;
|
||||
|
||||
/* Get the length of transferred word */
|
||||
word_len = spi_get_word_length(desc_extra);
|
||||
|
||||
/* Make sure the CS is HIGH before starting a transaction */
|
||||
msg.cmds->next = NULL;
|
||||
msg.cmds->cmd = CS_HIGH;
|
||||
|
||||
// Assert select.
|
||||
spi_engine_queue_add_cmd(&msg.cmds, CS_LOW);
|
||||
|
||||
// add read/write command
|
||||
if(write_bytes_number > 0)
|
||||
spi_engine_queue_add_cmd(&msg.cmds, WRITE(write_bytes_number));
|
||||
if(read_bytes_number > 0)
|
||||
spi_engine_queue_add_cmd(&msg.cmds, READ(read_bytes_number));
|
||||
|
||||
// Disable select.
|
||||
spi_engine_queue_add_cmd(&msg.cmds, CS_HIGH);
|
||||
|
||||
/* Pack the bytes into engine WORDS */
|
||||
for (int i = 0; i < write_bytes_number; i++)
|
||||
msg.tx_buf[i / word_len] |= write_data[i] << (desc_extra->data_width-
|
||||
(i % word_len + 1) * 8);
|
||||
|
||||
ret = spi_engine_transfer_message(desc, &msg);
|
||||
|
||||
for (int i = 0; i < read_bytes_number; i++)
|
||||
read_data[i] = msg.rx_buf[(i) / word_len] >>
|
||||
(desc_extra->data_width -
|
||||
((i) % word_len + 1) * 8);
|
||||
|
||||
spi_engine_queue_free(&msg.cmds);
|
||||
free(msg.tx_buf);
|
||||
free(msg.rx_buf);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the SPI engine's offload module
|
||||
*
|
||||
* @param desc Decriptor containing SPI interface parameters
|
||||
* @param param Structure containing the offload init parameters
|
||||
* @return int32_t This function allways returns SUCCESS
|
||||
*/
|
||||
int32_t spi_engine_offload_init(struct spi_desc *desc,
|
||||
const struct spi_engine_offload_init_param *param)
|
||||
{
|
||||
struct spi_engine_desc *eng_desc;
|
||||
struct axi_dmac_init dmac_init;
|
||||
uint32_t dma_flags;
|
||||
|
||||
eng_desc = desc->extra;
|
||||
|
||||
eng_desc->offload_config = param->offload_config;
|
||||
|
||||
if(!(param->dma_flags))
|
||||
dma_flags = DMA_CYCLIC;
|
||||
else
|
||||
dma_flags = *(param->dma_flags);
|
||||
|
||||
if(param->offload_config & OFFLOAD_TX_EN) {
|
||||
dmac_init.name = "DAC DMAC";
|
||||
dmac_init.base = param->tx_dma_baseaddr;
|
||||
dmac_init.direction = DMA_MEM_TO_DEV;
|
||||
dmac_init.flags = dma_flags;
|
||||
axi_dmac_init(&eng_desc->offload_tx_dma, &dmac_init);
|
||||
if(!eng_desc->offload_tx_dma)
|
||||
return FAILURE;
|
||||
}
|
||||
if(param->offload_config & OFFLOAD_RX_EN) {
|
||||
dmac_init.name = "ADC DMAC";
|
||||
dmac_init.base = param->rx_dma_baseaddr;
|
||||
dmac_init.direction = DMA_DEV_TO_MEM;
|
||||
dmac_init.flags = dma_flags;
|
||||
axi_dmac_init(&eng_desc->offload_rx_dma, &dmac_init);
|
||||
if(!eng_desc->offload_rx_dma)
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initiate a SPI transfer in offload mode
|
||||
*
|
||||
* @param desc Decriptor containing SPI interface parameters
|
||||
* @param msg Offload message that get's to be transferred
|
||||
* @param no_samples Number of time the messages will be transferred
|
||||
* @return int32_t This function allways returns SUCCESS
|
||||
*/
|
||||
int32_t spi_engine_offload_transfer(struct spi_desc *desc,
|
||||
struct spi_engine_offload_message msg,
|
||||
uint32_t no_samples)
|
||||
{
|
||||
struct spi_engine_msg transfer;
|
||||
struct spi_engine_desc *eng_desc;
|
||||
uint32_t i;
|
||||
uint8_t word_length;
|
||||
|
||||
eng_desc = desc->extra;
|
||||
|
||||
/* Check if offload is disabled */
|
||||
if(!((eng_desc->offload_config & OFFLOAD_TX_EN) |
|
||||
(eng_desc->offload_config & OFFLOAD_RX_EN)))
|
||||
return FAILURE;
|
||||
|
||||
spi_engine_write(eng_desc, SPI_ENGINE_REG_OFFLOAD_RESET(0), 1);
|
||||
spi_engine_write(eng_desc, SPI_ENGINE_REG_OFFLOAD_RESET(0), 0);
|
||||
|
||||
eng_desc->offload_tx_len = 0;
|
||||
eng_desc->offload_rx_len = 0;
|
||||
|
||||
transfer.cmds = (spi_engine_cmd_queue*)malloc(sizeof(*transfer.cmds));
|
||||
|
||||
if (!transfer.cmds)
|
||||
return FAILURE;
|
||||
|
||||
transfer.tx_buf = msg.commands_data;
|
||||
|
||||
/* Load the commands into the message */
|
||||
transfer.cmds->next = NULL;
|
||||
transfer.cmds->cmd = msg.commands[0];
|
||||
i = 1;
|
||||
while(i < msg.no_commands) {
|
||||
spi_engine_queue_add_cmd(&transfer.cmds, msg.commands[i++]);
|
||||
|
||||
}
|
||||
|
||||
spi_engine_transfer_message(desc, &transfer);
|
||||
|
||||
/* Start transfer */
|
||||
spi_engine_write(eng_desc, SPI_ENGINE_REG_OFFLOAD_CTRL(0), 0x0001);
|
||||
|
||||
word_length = spi_get_word_length(eng_desc);
|
||||
if(eng_desc->offload_config & OFFLOAD_TX_EN) {
|
||||
axi_dmac_transfer(eng_desc->offload_tx_dma,
|
||||
msg.tx_addr,
|
||||
word_length * eng_desc->offload_tx_len *
|
||||
no_samples);
|
||||
}
|
||||
|
||||
if(eng_desc->offload_config & OFFLOAD_RX_EN) {
|
||||
axi_dmac_transfer(eng_desc->offload_rx_dma,
|
||||
msg.rx_addr,
|
||||
word_length * eng_desc->offload_tx_len *
|
||||
no_samples);
|
||||
}
|
||||
|
||||
usleep(1000);
|
||||
|
||||
spi_engine_queue_free(&transfer.cmds);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Free the resources allocated by spi_init().
|
||||
*
|
||||
* @param desc Decriptor containing SPI interface parameters
|
||||
* @return int32_t This function allways returns SUCCESS
|
||||
*/
|
||||
int32_t spi_engine_remove(struct spi_desc *desc)
|
||||
{
|
||||
struct spi_engine_desc *eng_desc;
|
||||
|
||||
eng_desc = desc->extra;
|
||||
|
||||
if(eng_desc->offload_config & OFFLOAD_TX_EN)
|
||||
axi_dmac_remove(eng_desc->offload_tx_dma);
|
||||
if(eng_desc->offload_config & OFFLOAD_RX_EN)
|
||||
axi_dmac_remove(eng_desc->offload_rx_dma);
|
||||
free(desc->extra);
|
||||
free(desc);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
+231
@@ -0,0 +1,231 @@
|
||||
/*******************************************************************************
|
||||
* @file spi_engine.h
|
||||
* @brief Header file of SPI Engine core features.
|
||||
* @author Sergiu Cuciurean ([email protected])
|
||||
********************************************************************************
|
||||
* Copyright 2019(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef SPI_ENGINE_H
|
||||
#define SPI_ENGINE_H
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include "spi_engine_private.h"
|
||||
#include "../../platform/spi_extra.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/********************** Macros and Constants Definitions **********************/
|
||||
/******************************************************************************/
|
||||
|
||||
#define OFFLOAD_DISABLED 0x00
|
||||
#define OFFLOAD_TX_EN BIT(0)
|
||||
#define OFFLOAD_RX_EN BIT(1)
|
||||
#define OFFLOAD_TX_RX_EN OFFLOAD_TX_EN | OFFLOAD_RX_EN
|
||||
|
||||
#define SPI_ENGINE_MSG_QUEUE_END 0xFFFFFFFF
|
||||
|
||||
/* Spi engine commands */
|
||||
#define WRITE_OR_READ(mode, no_bytes) ((SPI_ENGINE_INST_TRANSFER << 12) |\
|
||||
((mode) << 8) | (no_bytes))
|
||||
|
||||
#define WRITE(no_bytes) ((SPI_ENGINE_INST_TRANSFER << 12) |\
|
||||
(SPI_ENGINE_INSTRUCTION_TRANSFER_W << 8) | (no_bytes))
|
||||
|
||||
#define READ(no_bytes) ((SPI_ENGINE_INST_TRANSFER << 12) |\
|
||||
(SPI_ENGINE_INSTRUCTION_TRANSFER_R << 8) | (no_bytes))
|
||||
|
||||
#define WRITE_READ(no_bytes) ((SPI_ENGINE_INST_TRANSFER << 12) |\
|
||||
(SPI_ENGINE_INSTRUCTION_TRANSFER_RW << 8) | (no_bytes))
|
||||
|
||||
|
||||
|
||||
#define SLEEP(time) SPI_ENGINE_CMD_SLEEP(time & 0xF)
|
||||
|
||||
/* The delay and chip select parmeters are passed over the engine descriptor
|
||||
and will be used inside the function call */
|
||||
#define CS_HIGH SPI_ENGINE_CMD_ASSERT(0x00, 0xFF)
|
||||
#define CS_LOW SPI_ENGINE_CMD_ASSERT(0x00, 0x00)
|
||||
|
||||
/******************************************************************************/
|
||||
/*************************** Types Declarations *******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @struct spi_engine_init_param
|
||||
* @brief Structure containing the init parameters needed by the SPI engine
|
||||
*/
|
||||
struct spi_engine_init_param {
|
||||
/** SPI engine reference clock */
|
||||
uint32_t ref_clk_hz;
|
||||
/** Type of implementation */
|
||||
enum xil_spi_type type;
|
||||
/** Base address where the HDL core is situated */
|
||||
uint32_t spi_engine_baseaddr;
|
||||
/** Delay between the CS toggle and the start of SCLK */
|
||||
uint32_t cs_delay;
|
||||
/** Data with of one SPI transfer ( in bits ) */
|
||||
uint8_t data_width;
|
||||
};
|
||||
|
||||
|
||||
/**
|
||||
* @struct spi_engine_desc
|
||||
* @brief Structure representing an SPI engine device
|
||||
*/
|
||||
struct spi_engine_desc {
|
||||
/** SPI engine reference clock */
|
||||
uint32_t ref_clk_hz;
|
||||
/** Type of implementation */
|
||||
enum xil_spi_type type;
|
||||
/** Pointer to a DMAC used in transmission */
|
||||
struct axi_dmac *offload_tx_dma;
|
||||
/** Pointer to a DMAC used in reception */
|
||||
struct axi_dmac *offload_rx_dma;
|
||||
/** Offload's module transfer direction : TX, RX or both */
|
||||
uint8_t offload_config;
|
||||
/** Number of words that the module has to send */
|
||||
uint8_t offload_tx_len;
|
||||
/** Number of words that the module has to receive */
|
||||
uint8_t offload_rx_len;
|
||||
/** Base address where the HDL core is situated */
|
||||
uint32_t spi_engine_baseaddr;
|
||||
/** Base address where the RX DMAC core is situated */
|
||||
uint32_t rx_dma_baseaddr;
|
||||
/** Base address where the TX DMAC core is situated */
|
||||
uint32_t tx_dma_baseaddr;
|
||||
/** Delay between the CS toggle and the start of SCLK */
|
||||
uint8_t cs_delay;
|
||||
/** Clock divider used in transmission delays */
|
||||
uint32_t clk_div;
|
||||
/** Data with of one SPI transfer ( in bits ) */
|
||||
uint8_t data_width;
|
||||
/** The maximum data width supported by the engine */
|
||||
uint8_t max_data_width;
|
||||
};
|
||||
|
||||
|
||||
/**
|
||||
* @struct spi_engine_offload_init_param
|
||||
* @brief Structure containing the init parameters needed by the offload module
|
||||
*/
|
||||
struct spi_engine_offload_init_param {
|
||||
/** Base address where the RX DMAC core is situated */
|
||||
uint32_t rx_dma_baseaddr;
|
||||
/** Base address where the TX DMAC core is situated */
|
||||
uint32_t tx_dma_baseaddr;
|
||||
/** DMAC flags - if not initialized, the default value is DMA_CYCLIC */
|
||||
uint32_t *dma_flags;
|
||||
/** Offload's module transfer direction : TX, RX or both */
|
||||
uint8_t offload_config;
|
||||
};
|
||||
|
||||
/**
|
||||
* @struct spi_engine_offload_message
|
||||
* @brief Structure representing an offload message
|
||||
*/
|
||||
struct spi_engine_offload_message {
|
||||
/** Pointer to the SPI engine commands buffer that will be sent.
|
||||
* The available commands can be found at:
|
||||
* https://wiki.analog.com/resources/fpga/peripherals/spi_engine/
|
||||
*/
|
||||
uint32_t *commands;
|
||||
/** Length of the SPI engine commands buffer */
|
||||
uint32_t no_commands;
|
||||
/** Pointer of the data that will be sent over spi */
|
||||
uint32_t *commands_data;
|
||||
/** The address where the data that will be transmitted is situated */
|
||||
uint32_t tx_addr;
|
||||
/** The address where the data that will be received is situated */
|
||||
uint32_t rx_addr;
|
||||
};
|
||||
|
||||
/******************************************************************************/
|
||||
/************************ Functions Declarations ******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief Spi engine platform specific SPI platform ops structure
|
||||
*/
|
||||
extern const struct spi_platform_ops xil_spi_ops;
|
||||
|
||||
/* Write SPI Engine's axi registers */
|
||||
int32_t spi_engine_write(struct spi_engine_desc *desc,
|
||||
uint32_t reg_addr,
|
||||
uint32_t reg_data);
|
||||
|
||||
/* Read SPI Engine's axi registers */
|
||||
int32_t spi_engine_read(struct spi_engine_desc *desc,
|
||||
uint32_t reg_addr,
|
||||
uint32_t *reg_data);
|
||||
/* Initialize the SPI engine device */
|
||||
int32_t spi_engine_init(struct spi_desc **desc,
|
||||
const struct spi_init_param *param);
|
||||
|
||||
/* Write and read data over SPI using the SPI engine */
|
||||
int32_t spi_engine_spi_write_and_read(struct spi_desc *desc,
|
||||
uint8_t *data,
|
||||
uint16_t bytes_number);
|
||||
|
||||
/* Write and read data over SPI using the SPI engine in 3-wire mode */
|
||||
int32_t spi_engine_spi_write_and_read_3wire(struct spi_desc *desc,
|
||||
uint8_t *write_data,
|
||||
uint8_t *read_data,
|
||||
uint16_t write_bytes_number,
|
||||
uint16_t read_bytes_number);
|
||||
/* Free the resources used by the SPI engine device */
|
||||
int32_t spi_engine_remove(struct spi_desc *desc);
|
||||
|
||||
/* Initialize the SPI engine offload module */
|
||||
int32_t spi_engine_offload_init(struct spi_desc *desc,
|
||||
const struct spi_engine_offload_init_param *param);
|
||||
|
||||
/* Write and read data over SPI using the offload module */
|
||||
int32_t spi_engine_offload_transfer(struct spi_desc *desc,
|
||||
struct spi_engine_offload_message msg,
|
||||
uint32_t no_samples);
|
||||
|
||||
/* Set SPI transfer width */
|
||||
int32_t spi_engine_set_transfer_width(struct spi_desc *desc,
|
||||
uint8_t data_wdith);
|
||||
|
||||
/* Set SPI transfer speed */
|
||||
void spi_engine_set_speed(struct spi_desc *desc,
|
||||
uint32_t speed_hz);
|
||||
|
||||
#endif // SPI_ENGINE_H
|
||||
+154
@@ -0,0 +1,154 @@
|
||||
/*******************************************************************************
|
||||
* @file spi_engine_private.h
|
||||
* @brief Private definitions of the SPI Engine
|
||||
* @author Sergiu Cuciurean ([email protected])
|
||||
********************************************************************************
|
||||
* Copyright 2019(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef SPI_ENGINE_PRIVATE_H
|
||||
#define SPI_ENGINE_PRIVATE_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "../../../include/spi.h"
|
||||
#include "../../../include/util.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/*************************** Spi Engine registers *****************************/
|
||||
/******************************************************************************/
|
||||
|
||||
#define SPI_ENGINE_REG_VERSION 0x00
|
||||
#define SPI_ENGINE_REG_DATA_WIDTH 0x0C
|
||||
#define SPI_ENGINE_REG_RESET 0x40
|
||||
#define SPI_ENGINE_REG_INT_ENABLE 0x80
|
||||
#define SPI_ENGINE_REG_INT_PENDING 0x84
|
||||
#define SPI_ENGINE_REG_INT_SOURCE 0x88
|
||||
#define SPI_ENGINE_REG_SYNC_ID 0xC0
|
||||
#define SPI_ENGINE_REG_CMD_FIFO_ROOM 0xD0
|
||||
#define SPI_ENGINE_REG_SDO_FIFO_ROOM 0xD4
|
||||
#define SPI_ENGINE_REG_SDI_FIFO_LEVEL 0xD8
|
||||
#define SPI_ENGINE_REG_CMD_FIFO 0xE0
|
||||
#define SPI_ENGINE_REG_SDO_DATA_FIFO 0xE4
|
||||
#define SPI_ENGINE_REG_SDI_DATA_FIFO 0xE8
|
||||
#define SPI_ENGINE_REG_SDI_DATA_FIFO_PEEK 0xEC
|
||||
|
||||
/******************************************************************************/
|
||||
/************************ Spi Engine register parameters **********************/
|
||||
/******************************************************************************/
|
||||
|
||||
#define SPI_ENGINE_INST_TRANSFER 0x00
|
||||
#define SPI_ENGINE_INST_ASSERT 0x01
|
||||
#define SPI_ENGINE_INST_CONFIG 0x02
|
||||
#define SPI_ENGINE_INST_SYNC_SLEEP 0x03
|
||||
#define SPI_ENGINE_INST_MISC 0x03
|
||||
#define SPI_ENGINE_CMD_REG_CLK_DIV 0x00
|
||||
#define SPI_ENGINE_CMD_REG_CONFIG 0x01
|
||||
#define SPI_ENGINE_CMD_DATA_TRANSFER_LEN 0x02
|
||||
#define SPI_ENGINE_MISC_SYNC 0x00
|
||||
#define SPI_ENGINE_MISC_SLEEP 0x01
|
||||
#define SPI_ENGINE_SYNC_TRANSFER_BEGIN BIT(1)
|
||||
#define SPI_ENGINE_SYNC_TRANSFER_END BIT(2)
|
||||
#define SPI_ENGINE_INT_CMD_ALMOST_EMPTY BIT(0)
|
||||
#define SPI_ENGINE_INT_SDO_ALMOST_EMPTY BIT(1)
|
||||
#define SPI_ENGINE_INT_SDI_ALMOST_FULL BIT(2)
|
||||
#define SPI_ENGINE_INT_SYNC BIT(3)
|
||||
#define SPI_ENGINE_OFFLOAD_CTRL_ENABLE BIT(0)
|
||||
#define SPI_ENGINE_OFFLOAD_STATUS_ENABLED BIT(0)
|
||||
#define SPI_ENGINE_CONFIG_CPHA BIT(0)
|
||||
#define SPI_ENGINE_CONFIG_CPOL BIT(1)
|
||||
#define SPI_ENGINE_CONFIG_3WIRE BIT(2)
|
||||
#define SPI_ENGINE_VERSION_MAJOR(x) ((x >> 16) & 0xff)
|
||||
#define SPI_ENGINE_VERSION_MINOR(x) ((x >> 8) & 0xff)
|
||||
#define SPI_ENGINE_VERSION_PATCH(x) (x & 0xff)
|
||||
|
||||
/******************************************************************************/
|
||||
/**************************** Spi Engine commands *****************************/
|
||||
/******************************************************************************/
|
||||
|
||||
#define SPI_ENGINE_INSTRUCTION_TRANSFER_W 0x01
|
||||
#define SPI_ENGINE_INSTRUCTION_TRANSFER_R 0x02
|
||||
#define SPI_ENGINE_INSTRUCTION_TRANSFER_RW 0x03
|
||||
|
||||
#define SPI_ENGINE_REG_OFFLOAD_CTRL(x) (0x100 + (0x20 * x))
|
||||
#define SPI_ENGINE_REG_OFFLOAD_STATUS(x) (0x104 + (0x20 * x))
|
||||
#define SPI_ENGINE_REG_OFFLOAD_RESET(x) (0x108 + (0x20 * x))
|
||||
#define SPI_ENGINE_REG_OFFLOAD_CMD_MEM(x) (0x110 + (0x20 * x))
|
||||
#define SPI_ENGINE_REG_OFFLOAD_SDO_MEM(x) (0x114 + (0x20 * x))
|
||||
|
||||
#define SPI_ENGINE_CMD(inst, arg1, arg2) \
|
||||
(((inst & 0x03) << 12) | \
|
||||
((arg1 & 0x03) << 8) | arg2 )
|
||||
|
||||
#define SPI_ENGINE_CMD_TRANSFER(readwrite, n) \
|
||||
SPI_ENGINE_CMD(SPI_ENGINE_INST_TRANSFER, \
|
||||
(readwrite), (n))
|
||||
|
||||
#define SPI_ENGINE_CMD_ASSERT(delay, cs) \
|
||||
SPI_ENGINE_CMD(SPI_ENGINE_INST_ASSERT, \
|
||||
(delay), (cs))
|
||||
|
||||
#define SPI_ENGINE_CMD_CONFIG(reg, val) \
|
||||
SPI_ENGINE_CMD(SPI_ENGINE_INST_CONFIG, \
|
||||
(reg), (val))
|
||||
|
||||
#define SPI_ENGINE_CMD_SLEEP(delay) \
|
||||
SPI_ENGINE_CMD(SPI_ENGINE_INST_MISC, \
|
||||
SPI_ENGINE_MISC_SLEEP, \
|
||||
(delay))
|
||||
|
||||
#define SPI_ENGINE_CMD_SYNC(id) \
|
||||
SPI_ENGINE_CMD(SPI_ENGINE_INST_MISC, \
|
||||
SPI_ENGINE_MISC_SYNC, \
|
||||
(id))
|
||||
|
||||
/******************************************************************************/
|
||||
/*************************** Types Declarations *******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
typedef struct spi_engine_cmd_queue {
|
||||
uint32_t cmd;
|
||||
struct spi_engine_cmd_queue *next;
|
||||
} spi_engine_cmd_queue;
|
||||
|
||||
typedef struct spi_engine_msg {
|
||||
uint32_t *tx_buf;
|
||||
uint32_t *rx_buf;
|
||||
uint32_t tx_length;
|
||||
uint32_t rx_length;
|
||||
struct spi_engine_cmd_queue *cmds;
|
||||
} spi_engine_msg;
|
||||
|
||||
#endif // SPI_ENGINE_PRIVATE_H
|
||||
+928
@@ -0,0 +1,928 @@
|
||||
/***************************************************************************//**
|
||||
* @file hmc7044.c
|
||||
* @brief Implementation of HMC7044, HMC7043 Driver.
|
||||
* @author DBogdan ([email protected])
|
||||
********************************************************************************
|
||||
* Copyright 2018-2020(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
#include <stdlib.h>
|
||||
#include <stdio.h>
|
||||
#include "hmc7044.h"
|
||||
#include "../../../include/error.h"
|
||||
#include "../../../include/util.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/********************** Macros and Constants Definitions **********************/
|
||||
/******************************************************************************/
|
||||
#define HMC7044_WRITE (0 << 15)
|
||||
#define HMC7044_READ (1 << 15)
|
||||
#define HMC7044_CNT(x) (((x) - 1) << 13)
|
||||
#define HMC7044_ADDR(x) ((x) & 0xFFF)
|
||||
|
||||
/* Global Control */
|
||||
#define HMC7044_REG_SOFT_RESET 0x0000
|
||||
#define HMC7044_SOFT_RESET BIT(0)
|
||||
|
||||
#define HMC7044_REG_REQ_MODE_0 0x0001
|
||||
#define HMC7044_RESEED_REQ BIT(7)
|
||||
#define HMC7044_HIGH_PERF_DISTRIB_PATH BIT(6)
|
||||
#define HMC7044_HIGH_PERF_PLL_VCO BIT(5)
|
||||
#define HMC7044_FORCE_HOLDOVER BIT(4)
|
||||
#define HMC7044_MUTE_OUT_DIV BIT(3)
|
||||
#define HMC7044_PULSE_GEN_REQ BIT(2)
|
||||
#define HMC7044_RESTART_DIV_FSM BIT(1)
|
||||
#define HMC7044_SLEEP_MODE BIT(0)
|
||||
|
||||
#define HMC7044_REG_REQ_MODE_1 0x0002
|
||||
#define HMC7044_PLL2_AUTOTUNE_TRIG BIT(2)
|
||||
#define HMC7044_SLIP_REQ BIT(1)
|
||||
|
||||
#define HMC7044_REG_EN_CTRL_0 0x0003
|
||||
#define HMC7044_RF_RESEEDER_EN BIT(5)
|
||||
#define HMC7044_VCO_SEL(x) (((x) & 0x3) << 3)
|
||||
#define HMC7044_VCO_EXT 0
|
||||
#define HMC7044_VCO_HIGH 1
|
||||
#define HMC7044_VCO_LOW 2
|
||||
#define HMC7044_SYSREF_TIMER_EN BIT(2)
|
||||
#define HMC7044_PLL2_EN BIT(1)
|
||||
#define HMC7044_PLL1_EN BIT(0)
|
||||
|
||||
#define HMC7044_REG_EN_CTRL_1 0x0004
|
||||
#define HMC7044_SEVEN_PAIRS(x) ((x) & 0x7f)
|
||||
|
||||
#define HMC7044_REG_GLOB_MODE 0x0005
|
||||
#define HMC7044_REF_PATH_EN(x) ((x) & 0xf)
|
||||
#define HMC7044_RFSYNC_EN BIT(4)
|
||||
#define HMC7044_VCOIN_MODE_EN BIT(5)
|
||||
#define HMC7044_SYNC_PIN_MODE(x) (((x) & 0x3) << 6)
|
||||
|
||||
/* PLL1 */
|
||||
#define HMC7044_REG_CLKIN0_BUF_CTRL 0x000A
|
||||
#define HMC7044_REG_CLKIN1_BUF_CTRL 0x000B
|
||||
#define HMC7044_REG_CLKIN2_BUF_CTRL 0x000C
|
||||
#define HMC7044_REG_CLKIN3_BUF_CTRL 0x000D
|
||||
#define HMC7044_REG_OSCIN_BUF_CTRL 0x000E
|
||||
|
||||
#define HMC7044_REG_PLL1_REF_PRIO_CTRL 0x0014
|
||||
|
||||
#define HMC7044_HIGH_Z_EN BIT(4)
|
||||
#define HMC7044_LVPECL_EN BIT(3)
|
||||
#define HMC7044_AC_COUPLING_EN BIT(2)
|
||||
#define HMC7044_100_OHM_EN BIT(1)
|
||||
#define HMC7044_BUF_EN BIT(0)
|
||||
|
||||
#define HMC7044_REG_CLKIN_PRESCALER(x) (0x001C + (x))
|
||||
#define HMC7044_REG_OSCIN_PRESCALER 0x0020
|
||||
|
||||
#define HMC7044_REG_PLL1_R_LSB 0x0021
|
||||
#define HMC7044_R1_LSB(x) ((x) & 0xff)
|
||||
|
||||
#define HMC7044_REG_PLL1_R_MSB 0x0022
|
||||
#define HMC7044_R1_MSB(x) (((x) & 0xff00) >> 8)
|
||||
|
||||
#define HMC7044_REG_PLL1_N_LSB 0x0026
|
||||
#define HMC7044_N1_LSB(x) ((x) & 0xff)
|
||||
|
||||
#define HMC7044_REG_PLL1_N_MSB 0x0027
|
||||
#define HMC7044_N1_MSB(x) (((x) & 0xff00) >> 8)
|
||||
|
||||
#define HMC7044_REG_PLL1_LOCK_DETECT 0x0028
|
||||
#define HMC7044_LOCK_DETECT_SLIP BIT(5)
|
||||
#define HMC7044_LOCK_DETECT_TIMER(x) ((x) & 0x1f)
|
||||
|
||||
/* PLL2 */
|
||||
#define HMC7044_REG_PLL2_FREQ_DOUBLER 0x0032
|
||||
#define HMC7044_PLL2_FREQ_DOUBLER_DIS BIT(0)
|
||||
|
||||
#define HMC7044_REG_PLL2_R_LSB 0x0033
|
||||
#define HMC7044_R2_LSB(x) ((x) & 0xff)
|
||||
|
||||
#define HMC7044_REG_PLL2_R_MSB 0x0034
|
||||
#define HMC7044_R2_MSB(x) (((x) & 0xf00) >> 8)
|
||||
|
||||
#define HMC7044_REG_PLL2_N_LSB 0x0035
|
||||
#define HMC7044_N2_LSB(x) ((x) & 0xff)
|
||||
|
||||
#define HMC7044_REG_PLL2_N_MSB 0x0036
|
||||
#define HMC7044_N2_MSB(x) (((x) & 0xff00) >> 8)
|
||||
|
||||
#define HMC7044_REG_OSCOUT_PATH 0x0039
|
||||
#define HMC7044_REG_OSCOUT_DRIVER_0 0x003A
|
||||
#define HMC7044_REG_OSCOUT_DRIVER_1 0x003B
|
||||
|
||||
/* GPIO/SDATA Control */
|
||||
#define HMC7044_REG_GPI_CTRL(x) (0x0046 + (x))
|
||||
#define HMC7044_REG_GPI_SEL(x) ((x) & 0xf)
|
||||
|
||||
#define HMC7044_REG_GPO_CTRL(x) (0x0050 + (x))
|
||||
#define HMC7044_GPO_SEL(x) (((x) & 0x3f) << 2)
|
||||
#define HMC7044_GPO_MODE BIT(1)
|
||||
#define HMC7044_GPO_EN BIT(0)
|
||||
|
||||
/* SYSREF/SYNC Control */
|
||||
#define HMC7044_REG_PULSE_GEN 0x005A
|
||||
#define HMC7044_PULSE_GEN_MODE(x) ((x) & 0x7)
|
||||
|
||||
#define HMC7044_REG_SYNC 0x005B
|
||||
#define HMC7044_SYNC_RETIME BIT(2)
|
||||
#define HMC7044_SYNC_THROUGH_PLL2 BIT(1)
|
||||
#define HMC7044_SYNC_POLARITY BIT(0)
|
||||
|
||||
#define HMC7044_REG_SYSREF_TIMER_LSB 0x005C
|
||||
#define HMC7044_SYSREF_TIMER_LSB(x) ((x) & 0xff)
|
||||
|
||||
#define HMC7044_REG_SYSREF_TIMER_MSB 0x005D
|
||||
#define HMC7044_SYSREF_TIMER_MSB(x) (((x) & 0xf00) >> 8)
|
||||
|
||||
#define HMC7044_CLK_INPUT_CTRL 0x0064
|
||||
#define HMC7044_LOW_FREQ_INPUT_MODE BIT(0)
|
||||
#define HMC7044_DIV_2_INPUT_MODE BIT(1)
|
||||
|
||||
/* Status and Alarm readback */
|
||||
#define HMC7044_REG_ALARM_READBACK 0x007D
|
||||
#define HMC7044_REG_PLL1_STATUS 0x0082
|
||||
|
||||
#define HMC7044_PLL1_FSM_STATE(x) ((x) & 0x7)
|
||||
#define HMC7044_PLL1_ACTIVE_CLKIN(x) (((x) >> 3) & 0x3)
|
||||
|
||||
#define HMC7044_PLL2_LOCK_DETECT(x) ((x) & 0x1)
|
||||
#define HMC7044_SYSREF_SYNC_STAT(x) ((x) & 0x2)
|
||||
#define HMC7044_CLK_OUT_PH_STATUS(x) ((x) & 0x4)
|
||||
#define HMC7044_PLL1_PLL2_LOCK_STAT(x) ((x) & 0x8)
|
||||
#define HMC7044_SYNC_REQ_STATUS(x) ((x) & 0x10)
|
||||
|
||||
/* Other Controls */
|
||||
#define HMC7044_REG_CLK_OUT_DRV_LOW_PW 0x009F
|
||||
#define HMC7044_REG_CLK_OUT_DRV_HIGH_PW 0x00A0
|
||||
#define HMC7044_REG_PLL1_DELAY 0x00A5
|
||||
#define HMC7044_REG_PLL1_HOLDOVER 0x00A8
|
||||
#define HMC7044_REG_VTUNE_PRESET 0x00B0
|
||||
|
||||
/* Clock Distribution */
|
||||
#define HMC7044_REG_CH_OUT_CRTL_0(ch) (0x00C8 + 0xA * (ch))
|
||||
#define HMC7044_HI_PERF_MODE BIT(7)
|
||||
#define HMC7044_SYNC_EN BIT(6)
|
||||
#define HMC7044_CH_EN BIT(0)
|
||||
#define HMC7044_START_UP_MODE_DYN_EN (BIT(3) | BIT(2))
|
||||
|
||||
#define HMC7044_REG_CH_OUT_CRTL_1(ch) (0x00C9 + 0xA * (ch))
|
||||
#define HMC7044_DIV_LSB(x) ((x) & 0xFF)
|
||||
|
||||
#define HMC7044_REG_CH_OUT_CRTL_2(ch) (0x00CA + 0xA * (ch))
|
||||
#define HMC7044_DIV_MSB(x) (((x) >> 8) & 0xFF)
|
||||
|
||||
#define HMC7044_REG_CH_OUT_CRTL_3(ch) (0x00CB + 0xA * (ch))
|
||||
#define HMC7044_REG_CH_OUT_CRTL_4(ch) (0x00CC + 0xA * (ch))
|
||||
#define HMC7044_REG_CH_OUT_CRTL_5(ch) (0x00CD + 0xA * (ch))
|
||||
#define HMC7044_REG_CH_OUT_CRTL_6(ch) (0x00CE + 0xA * (ch))
|
||||
#define HMC7044_REG_CH_OUT_CRTL_7(ch) (0x00CF + 0xA * (ch))
|
||||
|
||||
#define HMC7044_REG_CH_OUT_CRTL_8(ch) (0x00D0 + 0xA * (ch))
|
||||
#define HMC7044_DRIVER_MODE(x) (((x) & 0x3) << 3)
|
||||
#define HMC7044_DRIVER_Z_MODE(x) (((x) & 0x3) << 0)
|
||||
#define HMC7044_DYN_DRIVER_EN BIT(5)
|
||||
#define HMC7044_FORCE_MUTE_EN BIT(7)
|
||||
|
||||
#define HMC7044_NUM_CHAN 14
|
||||
|
||||
#define HMC7044_LOW_VCO_MIN 2150000
|
||||
#define HMC7044_LOW_VCO_MAX 2880000
|
||||
#define HMC7044_HIGH_VCO_MIN 2650000
|
||||
#define HMC7044_HIGH_VCO_MAX 3200000
|
||||
|
||||
#define HMC7044_RECOMM_LCM_MIN 30000
|
||||
#define HMC7044_RECOMM_LCM_MAX 70000
|
||||
#define HMC7044_RECOMM_FPD1 10000
|
||||
|
||||
#define HMC7044_R1_MAX 65535
|
||||
#define HMC7044_N1_MAX 65535
|
||||
|
||||
#define HMC7044_R2_MIN 1
|
||||
#define HMC7044_R2_MAX 4095
|
||||
#define HMC7044_N2_MIN 8
|
||||
#define HMC7044_N2_MAX 65535
|
||||
|
||||
#define HMC7044_OUT_DIV_MIN 1
|
||||
#define HMC7044_OUT_DIV_MAX 4094
|
||||
|
||||
/******************************************************************************/
|
||||
/************************** Functions Implementation **************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* SPI register write to device.
|
||||
* @param dev - The device structure.
|
||||
* @param reg - The register address.
|
||||
* @param val - The register data.
|
||||
* @return SUCCESS in case of success, negative error code otherwise.
|
||||
*/
|
||||
int32_t hmc7044_write(struct hmc7044_dev *dev,
|
||||
uint16_t reg,
|
||||
uint8_t val)
|
||||
{
|
||||
uint8_t buf[3];
|
||||
uint16_t cmd;
|
||||
|
||||
cmd = HMC7044_WRITE | HMC7044_CNT(1) | HMC7044_ADDR(reg);
|
||||
buf[0] = cmd >> 8;
|
||||
buf[1] = cmd & 0xFF;
|
||||
buf[2] = val;
|
||||
return spi_write_and_read_3wire(dev->spi_desc, buf, NULL,
|
||||
ARRAY_SIZE(buf), 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* SPI register read from device.
|
||||
* @param dev - The device structure.
|
||||
* @param reg - The register address.
|
||||
* @param val - The register data.
|
||||
* @return SUCCESS in case of success, negative error code otherwise.
|
||||
*/
|
||||
|
||||
int32_t hmc7044_read(struct hmc7044_dev *dev, uint16_t reg, uint8_t *val)
|
||||
{
|
||||
uint8_t wr_buf[2];
|
||||
uint8_t rd_data[1];
|
||||
uint16_t cmd;
|
||||
int ret;
|
||||
|
||||
cmd = HMC7044_READ | HMC7044_CNT(1) | HMC7044_ADDR(reg);
|
||||
wr_buf[0] = cmd >> 8;
|
||||
wr_buf[1] = cmd & 0xFF;
|
||||
|
||||
ret = spi_write_and_read_3wire(dev->spi_desc, wr_buf, rd_data,
|
||||
ARRAY_SIZE(wr_buf), ARRAY_SIZE(rd_data));
|
||||
if (ret != SUCCESS)
|
||||
return ret;
|
||||
|
||||
*val = rd_data[0];
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* Calculate the output channel divider.
|
||||
* @param rate - The desired rate.
|
||||
* @param parent_rate - The parent rate.
|
||||
* @return The output divider.
|
||||
*/
|
||||
uint32_t hmc7044_calc_out_div(uint32_t rate,
|
||||
uint32_t parent_rate)
|
||||
{
|
||||
uint32_t div;
|
||||
|
||||
div = DIV_ROUND_CLOSEST(parent_rate, rate);
|
||||
|
||||
/* Supported odd divide ratios are 1, 3, and 5 */
|
||||
if ((div != 1) && (div != 3) && (div != 5) && (div % 2))
|
||||
div = DIV_ROUND_CLOSEST(parent_rate, rate * 2) * 2;
|
||||
|
||||
div = clamp_t(unsigned int,
|
||||
div,
|
||||
HMC7044_OUT_DIV_MIN,
|
||||
HMC7044_OUT_DIV_MAX);
|
||||
|
||||
return div;
|
||||
}
|
||||
|
||||
/**
|
||||
* Recalculate rate corresponding to a channel.
|
||||
* @param dev - The device structure.
|
||||
* @param chan_num - Channel number.
|
||||
* @param rate - Channel rate.
|
||||
* @return SUCCESS in case of success, negative error code otherwise.
|
||||
*/
|
||||
int32_t hmc7044_clk_recalc_rate(struct hmc7044_dev *dev, uint32_t chan_num,
|
||||
uint64_t *rate)
|
||||
{
|
||||
int i;
|
||||
struct hmc7044_chan_spec *chan = NULL;
|
||||
|
||||
/* Find the reqested channel number */
|
||||
for (i = 0; i < dev->num_channels; i++) {
|
||||
if (dev->channels[i].num == chan_num) {
|
||||
chan = &dev->channels[i];
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (chan == NULL )
|
||||
return FAILURE;
|
||||
|
||||
*rate = dev->pll2_freq / chan->divider;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* Calculate closest possible rate
|
||||
* @param dev - The device structure
|
||||
* @param rate - The desired rate.
|
||||
* @param rounded_rate - The closest possible rate of desired rate.
|
||||
* @return SUCCESS in case of success, negative error code otherwise.
|
||||
*/
|
||||
int32_t hmc7044_clk_round_rate(struct hmc7044_dev *dev, uint32_t rate,
|
||||
uint64_t *rounded_rate)
|
||||
{
|
||||
uint32_t div = hmc7044_calc_out_div(rate, dev->pll2_freq);
|
||||
|
||||
*rounded_rate = DIV_ROUND_CLOSEST(dev->pll2_freq, div);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set channel rate.
|
||||
* @param dev - The device structure.
|
||||
* @param chan_num - Channel number.
|
||||
* @param rate - Channel rate.
|
||||
* @return SUCCESS in case of success, negative error code otherwise.
|
||||
*/
|
||||
int32_t hmc7044_clk_set_rate(struct hmc7044_dev *dev, uint32_t chan_num,
|
||||
uint64_t rate)
|
||||
{
|
||||
uint32_t div;
|
||||
int32_t ret;
|
||||
int i;
|
||||
struct hmc7044_chan_spec *chan = NULL;
|
||||
|
||||
/* Find the reqested channel number */
|
||||
for (i = 0; i < dev->num_channels; i++) {
|
||||
if (dev->channels[i].num == chan_num) {
|
||||
chan = &dev->channels[i];
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (chan == NULL )
|
||||
return FAILURE;
|
||||
|
||||
div = hmc7044_calc_out_div(rate, dev->pll2_freq);
|
||||
chan->divider = div;
|
||||
|
||||
ret = hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_1(chan->num),
|
||||
HMC7044_DIV_LSB(div));
|
||||
if(ret < 0)
|
||||
return ret;
|
||||
|
||||
return hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_2(chan->num),
|
||||
HMC7044_DIV_MSB(div));
|
||||
}
|
||||
|
||||
/**
|
||||
* Setup the device.
|
||||
* @param dev - The device structure.
|
||||
* @return SUCCESS in case of success, negative error code otherwise.
|
||||
*/
|
||||
static int32_t hmc7044_setup(struct hmc7044_dev *dev)
|
||||
{
|
||||
struct hmc7044_chan_spec *chan;
|
||||
bool high_vco_en;
|
||||
bool pll2_freq_doubler_en;
|
||||
uint32_t vcxo_freq, pll2_freq;
|
||||
uint32_t clkin_freq[4];
|
||||
uint32_t lcm_freq;
|
||||
uint32_t in_prescaler[5];
|
||||
uint32_t pll1_lock_detect;
|
||||
uint32_t n1, r1;
|
||||
uint32_t pfd1_freq;
|
||||
uint32_t vco_limit;
|
||||
uint32_t n2[2], r2[2];
|
||||
uint32_t i, ref_en = 0;
|
||||
|
||||
vcxo_freq = dev->vcxo_freq / 1000;
|
||||
pll2_freq = dev->pll2_freq / 1000;
|
||||
|
||||
lcm_freq = vcxo_freq;
|
||||
for (i = 0; i < ARRAY_SIZE(clkin_freq); i++) {
|
||||
if (dev->clkin_freq_ccf[i])
|
||||
clkin_freq[i] = dev->clkin_freq_ccf[i] / 1000;
|
||||
else
|
||||
clkin_freq[i] = dev->clkin_freq[i] / 1000;
|
||||
|
||||
if (clkin_freq[i]) {
|
||||
lcm_freq = greatest_common_divisor(clkin_freq[i], lcm_freq);
|
||||
ref_en |= BIT(i);
|
||||
}
|
||||
}
|
||||
|
||||
while (lcm_freq > HMC7044_RECOMM_LCM_MAX)
|
||||
lcm_freq /= 2;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clkin_freq); i++) {
|
||||
if (clkin_freq[i])
|
||||
in_prescaler[i] = clkin_freq[i] / lcm_freq;
|
||||
else
|
||||
in_prescaler[i] = 1;
|
||||
}
|
||||
in_prescaler[4] = vcxo_freq / lcm_freq;
|
||||
|
||||
pll1_lock_detect = log_base_2((lcm_freq * 4000) / dev->pll1_loop_bw);
|
||||
|
||||
/* fVCXO / N1 = fLCM / R1 */
|
||||
rational_best_approximation(vcxo_freq, lcm_freq,
|
||||
HMC7044_N1_MAX, HMC7044_R1_MAX,
|
||||
&n1, &r1);
|
||||
|
||||
pfd1_freq = vcxo_freq / n1;
|
||||
while ((pfd1_freq > HMC7044_RECOMM_FPD1) &&
|
||||
(n1 <= HMC7044_N1_MAX / 2) &&
|
||||
(r1 <= HMC7044_R1_MAX / 2)) {
|
||||
pfd1_freq /= 2;
|
||||
n1 *= 2;
|
||||
r1 *= 2;
|
||||
}
|
||||
|
||||
dev->pll1_pfd = pfd1_freq;
|
||||
|
||||
if (pll2_freq < HMC7044_LOW_VCO_MIN ||
|
||||
pll2_freq > HMC7044_HIGH_VCO_MAX)
|
||||
return FAILURE;
|
||||
|
||||
vco_limit = (HMC7044_LOW_VCO_MAX + HMC7044_HIGH_VCO_MIN) / 2;
|
||||
if (pll2_freq >= vco_limit)
|
||||
high_vco_en = true;
|
||||
else
|
||||
high_vco_en = false;
|
||||
|
||||
/* fVCO / N2 = fVCXO * doubler / R2 */
|
||||
pll2_freq_doubler_en = true;
|
||||
rational_best_approximation(pll2_freq, vcxo_freq * 2,
|
||||
HMC7044_N2_MAX, HMC7044_R2_MAX,
|
||||
&n2[0], &r2[0]);
|
||||
|
||||
if (pll2_freq != vcxo_freq * n2[0] / r2[0]) {
|
||||
rational_best_approximation(pll2_freq, vcxo_freq,
|
||||
HMC7044_N2_MAX, HMC7044_R2_MAX,
|
||||
&n2[1], &r2[1]);
|
||||
|
||||
if (abs((int)pll2_freq - (int)(vcxo_freq * 2 * n2[0] / r2[0])) >
|
||||
abs((int)pll2_freq - (int)(vcxo_freq * n2[1] / r2[1]))) {
|
||||
n2[0] = n2[1];
|
||||
r2[0] = r2[1];
|
||||
pll2_freq_doubler_en = false;
|
||||
}
|
||||
}
|
||||
|
||||
while ((n2[0] < HMC7044_N2_MIN) && (r2[0] <= HMC7044_R2_MAX / 2)) {
|
||||
n2[0] *= 2;
|
||||
r2[0] *= 2;
|
||||
}
|
||||
if (n2[0] < HMC7044_N2_MIN)
|
||||
return -FAILURE;
|
||||
|
||||
/* Resets all registers to default values */
|
||||
hmc7044_write(dev, HMC7044_REG_SOFT_RESET, HMC7044_SOFT_RESET);
|
||||
mdelay(10);
|
||||
hmc7044_write(dev, HMC7044_REG_SOFT_RESET, 0);
|
||||
mdelay(10);
|
||||
|
||||
/* Disable all channels */
|
||||
for (i = 0; i < HMC7044_NUM_CHAN; i++)
|
||||
hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_0(i), 0);
|
||||
|
||||
/* Load the configuration updates (provided by Analog Devices) */
|
||||
hmc7044_write(dev, HMC7044_REG_CLK_OUT_DRV_LOW_PW, 0x4d);
|
||||
hmc7044_write(dev, HMC7044_REG_CLK_OUT_DRV_HIGH_PW, 0xdf);
|
||||
hmc7044_write(dev, HMC7044_REG_PLL1_DELAY, 0x06);
|
||||
hmc7044_write(dev, HMC7044_REG_PLL1_HOLDOVER, 0x06);
|
||||
hmc7044_write(dev, HMC7044_REG_VTUNE_PRESET, 0x04);
|
||||
|
||||
uint8_t rd_back;
|
||||
hmc7044_read(dev, HMC7044_REG_CLK_OUT_DRV_LOW_PW, &rd_back);
|
||||
hmc7044_read(dev, HMC7044_REG_CLK_OUT_DRV_HIGH_PW, &rd_back);
|
||||
hmc7044_read(dev, HMC7044_REG_PLL1_DELAY, &rd_back);
|
||||
hmc7044_read(dev, HMC7044_REG_PLL1_HOLDOVER, &rd_back);
|
||||
hmc7044_read(dev, HMC7044_REG_VTUNE_PRESET, &rd_back);
|
||||
|
||||
|
||||
hmc7044_write(dev, HMC7044_REG_GLOB_MODE,
|
||||
HMC7044_SYNC_PIN_MODE(dev->sync_pin_mode) |
|
||||
(dev->clkin0_rfsync_en ? HMC7044_RFSYNC_EN : 0) |
|
||||
(dev->clkin1_vcoin_en ? HMC7044_VCOIN_MODE_EN : 0) |
|
||||
HMC7044_REF_PATH_EN(ref_en));
|
||||
|
||||
/* Program PLL2 */
|
||||
|
||||
/* Select the VCO range */
|
||||
hmc7044_write(dev, HMC7044_REG_EN_CTRL_0,
|
||||
(dev->rf_reseeder_en ? HMC7044_RF_RESEEDER_EN : 0) |
|
||||
HMC7044_VCO_SEL(high_vco_en ?
|
||||
HMC7044_VCO_HIGH :
|
||||
HMC7044_VCO_LOW) |
|
||||
HMC7044_SYSREF_TIMER_EN | HMC7044_PLL2_EN |
|
||||
HMC7044_PLL1_EN);
|
||||
|
||||
/* Program the dividers */
|
||||
hmc7044_write(dev, HMC7044_REG_PLL2_R_LSB,
|
||||
HMC7044_R2_LSB(r2[0]));
|
||||
hmc7044_write(dev, HMC7044_REG_PLL2_R_MSB,
|
||||
HMC7044_R2_MSB(r2[0]));
|
||||
hmc7044_write(dev, HMC7044_REG_PLL2_N_LSB,
|
||||
HMC7044_N2_LSB(n2[0]));
|
||||
hmc7044_write(dev, HMC7044_REG_PLL2_N_MSB,
|
||||
HMC7044_N2_MSB(n2[0]));
|
||||
|
||||
/* Program the reference doubler */
|
||||
hmc7044_write(dev, HMC7044_REG_PLL2_FREQ_DOUBLER,
|
||||
pll2_freq_doubler_en ? 0 : HMC7044_PLL2_FREQ_DOUBLER_DIS);
|
||||
|
||||
/* Program PLL1 */
|
||||
|
||||
/* Set the lock detect timer threshold */
|
||||
hmc7044_write(dev, HMC7044_REG_PLL1_LOCK_DETECT,
|
||||
HMC7044_LOCK_DETECT_TIMER(pll1_lock_detect));
|
||||
|
||||
/* Set the LCM */
|
||||
for (i = 0; i < ARRAY_SIZE(clkin_freq); i++) {
|
||||
hmc7044_write(dev, HMC7044_REG_CLKIN_PRESCALER(i),
|
||||
in_prescaler[i]);
|
||||
}
|
||||
hmc7044_write(dev, HMC7044_REG_OSCIN_PRESCALER,
|
||||
in_prescaler[4]);
|
||||
|
||||
/* Program the dividers */
|
||||
hmc7044_write(dev, HMC7044_REG_PLL1_R_LSB,
|
||||
HMC7044_R2_LSB(r1));
|
||||
hmc7044_write(dev, HMC7044_REG_PLL1_R_MSB,
|
||||
HMC7044_R2_MSB(r1));
|
||||
hmc7044_write(dev, HMC7044_REG_PLL1_N_LSB,
|
||||
HMC7044_N2_LSB(n1));
|
||||
hmc7044_write(dev, HMC7044_REG_PLL1_N_MSB,
|
||||
HMC7044_N2_MSB(n1));
|
||||
|
||||
hmc7044_write(dev, HMC7044_REG_PLL1_REF_PRIO_CTRL,
|
||||
dev->pll1_ref_prio_ctrl);
|
||||
|
||||
/* Program the SYSREF timer */
|
||||
|
||||
/* Set the divide ratio */
|
||||
hmc7044_write(dev, HMC7044_REG_SYSREF_TIMER_LSB,
|
||||
HMC7044_SYSREF_TIMER_LSB(dev->sysref_timer_div));
|
||||
hmc7044_write(dev, HMC7044_REG_SYSREF_TIMER_MSB,
|
||||
HMC7044_SYSREF_TIMER_MSB(dev->sysref_timer_div));
|
||||
|
||||
/* Set the pulse generator mode configuration */
|
||||
hmc7044_write(dev, HMC7044_REG_PULSE_GEN,
|
||||
HMC7044_PULSE_GEN_MODE(dev->pulse_gen_mode));
|
||||
|
||||
/* Enable the input buffers */
|
||||
hmc7044_write(dev, HMC7044_REG_CLKIN0_BUF_CTRL,
|
||||
dev->in_buf_mode[0]);
|
||||
hmc7044_write(dev, HMC7044_REG_CLKIN1_BUF_CTRL,
|
||||
dev->in_buf_mode[1]);
|
||||
hmc7044_write(dev, HMC7044_REG_CLKIN2_BUF_CTRL,
|
||||
dev->in_buf_mode[2]);
|
||||
hmc7044_write(dev, HMC7044_REG_CLKIN3_BUF_CTRL,
|
||||
dev->in_buf_mode[3]);
|
||||
hmc7044_write(dev, HMC7044_REG_OSCIN_BUF_CTRL,
|
||||
dev->in_buf_mode[4]);
|
||||
|
||||
/* Set GPIOs */
|
||||
for (i = 0; i < ARRAY_SIZE(dev->gpi_ctrl); i++) {
|
||||
hmc7044_write(dev, HMC7044_REG_GPI_CTRL(i),
|
||||
dev->gpi_ctrl[i]);
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(dev->gpo_ctrl); i++) {
|
||||
hmc7044_write(dev, HMC7044_REG_GPO_CTRL(i),
|
||||
dev->gpo_ctrl[i]);
|
||||
}
|
||||
|
||||
mdelay(10);
|
||||
|
||||
/* Program the output channels */
|
||||
for (i = 0; i < dev->num_channels; i++) {
|
||||
chan = &dev->channels[i];
|
||||
if (chan->num >= HMC7044_NUM_CHAN || chan->disable)
|
||||
continue;
|
||||
|
||||
hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_1(chan->num),
|
||||
HMC7044_DIV_LSB(chan->divider));
|
||||
hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_2(chan->num),
|
||||
HMC7044_DIV_MSB(chan->divider));
|
||||
hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_8(chan->num),
|
||||
HMC7044_DRIVER_MODE(chan->driver_mode) |
|
||||
HMC7044_DRIVER_Z_MODE(chan->driver_impedance) |
|
||||
(chan->dynamic_driver_enable ?
|
||||
HMC7044_DYN_DRIVER_EN : 0) |
|
||||
(chan->force_mute_enable ?
|
||||
HMC7044_FORCE_MUTE_EN : 0));
|
||||
|
||||
hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_3(chan->num),
|
||||
chan->fine_delay & 0x1F);
|
||||
hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_4(chan->num),
|
||||
chan->coarse_delay & 0x1F);
|
||||
hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_7(chan->num),
|
||||
chan->out_mux_mode & 0x3);
|
||||
|
||||
hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_0(chan->num),
|
||||
(chan->start_up_mode_dynamic_enable ?
|
||||
HMC7044_START_UP_MODE_DYN_EN : 0) |
|
||||
(chan->output_control0_rb4_enable ? BIT(4) : 0) |
|
||||
(chan->high_performance_mode_dis ?
|
||||
0 : HMC7044_HI_PERF_MODE) | HMC7044_SYNC_EN |
|
||||
HMC7044_CH_EN);
|
||||
}
|
||||
mdelay(10);
|
||||
|
||||
/* Do a restart to reset the system and initiate calibration */
|
||||
hmc7044_write(dev, HMC7044_REG_REQ_MODE_0,
|
||||
HMC7044_RESTART_DIV_FSM);
|
||||
mdelay(1);
|
||||
hmc7044_write(dev, HMC7044_REG_REQ_MODE_0,
|
||||
(dev->high_performance_mode_clock_dist_en ?
|
||||
HMC7044_HIGH_PERF_DISTRIB_PATH : 0));
|
||||
mdelay(1);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* Setup the device.
|
||||
* @param dev - The device structure.
|
||||
* @return SUCCESS in case of success, negative error code otherwise.
|
||||
*/
|
||||
static int32_t hmc7043_setup(struct hmc7044_dev *dev)
|
||||
{
|
||||
struct hmc7044_chan_spec *chan;
|
||||
uint32_t i;
|
||||
|
||||
if (dev->clkin_freq_ccf[0])
|
||||
dev->pll2_freq = dev->clkin_freq_ccf[0];
|
||||
else
|
||||
dev->pll2_freq = dev->clkin_freq[0];
|
||||
|
||||
if (!dev->pll2_freq) {
|
||||
printf("%s: Failed to get valid parent rate\n", __func__);
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
/* Resets all registers to default values */
|
||||
hmc7044_write(dev, HMC7044_REG_SOFT_RESET, HMC7044_SOFT_RESET);
|
||||
mdelay(10);
|
||||
hmc7044_write(dev, HMC7044_REG_SOFT_RESET, 0);
|
||||
mdelay(10);
|
||||
|
||||
/* Load the configuration updates (provided by Analog Devices) */
|
||||
hmc7044_write(dev, HMC7044_REG_CLK_OUT_DRV_LOW_PW, 0x4d);
|
||||
hmc7044_write(dev, HMC7044_REG_CLK_OUT_DRV_HIGH_PW, 0xdf);
|
||||
|
||||
/* Disable all channels */
|
||||
for (i = 0; i < HMC7044_NUM_CHAN; i++)
|
||||
hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_0(i), 0);
|
||||
|
||||
if (dev->pll2_freq < 1000000000U)
|
||||
hmc7044_write(dev, HMC7044_CLK_INPUT_CTRL,
|
||||
HMC7044_LOW_FREQ_INPUT_MODE);
|
||||
|
||||
hmc7044_write(dev, HMC7044_REG_EN_CTRL_0,
|
||||
(dev->rf_reseeder_en ? HMC7044_RF_RESEEDER_EN : 0) |
|
||||
HMC7044_SYSREF_TIMER_EN);
|
||||
|
||||
/* Program the SYSREF timer */
|
||||
|
||||
/* Set the divide ratio */
|
||||
hmc7044_write(dev, HMC7044_REG_SYSREF_TIMER_LSB,
|
||||
HMC7044_SYSREF_TIMER_LSB(dev->sysref_timer_div));
|
||||
hmc7044_write(dev, HMC7044_REG_SYSREF_TIMER_MSB,
|
||||
HMC7044_SYSREF_TIMER_MSB(dev->sysref_timer_div));
|
||||
|
||||
/* Set the pulse generator mode configuration */
|
||||
hmc7044_write(dev, HMC7044_REG_PULSE_GEN,
|
||||
HMC7044_PULSE_GEN_MODE(dev->pulse_gen_mode));
|
||||
|
||||
/* Enable the input buffers */
|
||||
hmc7044_write(dev, HMC7044_REG_CLKIN0_BUF_CTRL,
|
||||
dev->in_buf_mode[0]);
|
||||
hmc7044_write(dev, HMC7044_REG_CLKIN1_BUF_CTRL,
|
||||
dev->in_buf_mode[1]);
|
||||
|
||||
/* Set GPIOs */
|
||||
hmc7044_write(dev, HMC7044_REG_GPI_CTRL(0),
|
||||
dev->gpi_ctrl[0]);
|
||||
|
||||
hmc7044_write(dev, HMC7044_REG_GPO_CTRL(0),
|
||||
dev->gpo_ctrl[0]);
|
||||
|
||||
/* Program the output channels */
|
||||
for (i = 0; i < dev->num_channels; i++) {
|
||||
chan = &dev->channels[i];
|
||||
|
||||
if (chan->num >= HMC7044_NUM_CHAN || chan->disable)
|
||||
continue;
|
||||
|
||||
hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_1(chan->num),
|
||||
HMC7044_DIV_LSB(chan->divider));
|
||||
hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_2(chan->num),
|
||||
HMC7044_DIV_MSB(chan->divider));
|
||||
hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_8(chan->num),
|
||||
HMC7044_DRIVER_MODE(chan->driver_mode) |
|
||||
HMC7044_DRIVER_Z_MODE(chan->driver_impedance) |
|
||||
(chan->dynamic_driver_enable ?
|
||||
HMC7044_DYN_DRIVER_EN : 0) |
|
||||
(chan->force_mute_enable ?
|
||||
HMC7044_FORCE_MUTE_EN : 0));
|
||||
|
||||
hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_3(chan->num),
|
||||
chan->fine_delay & 0x1F);
|
||||
hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_4(chan->num),
|
||||
chan->coarse_delay & 0x1F);
|
||||
hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_7(chan->num),
|
||||
chan->out_mux_mode & 0x3);
|
||||
|
||||
hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_0(chan->num),
|
||||
(chan->start_up_mode_dynamic_enable ?
|
||||
HMC7044_START_UP_MODE_DYN_EN : 0) |
|
||||
(chan->output_control0_rb4_enable ? BIT(4) : 0) |
|
||||
(chan->high_performance_mode_dis ?
|
||||
0 : HMC7044_HI_PERF_MODE) | HMC7044_SYNC_EN |
|
||||
HMC7044_CH_EN);
|
||||
}
|
||||
mdelay(10);
|
||||
|
||||
|
||||
/* Do a restart to reset the system and initiate calibration */
|
||||
hmc7044_write(dev, HMC7044_REG_REQ_MODE_0,
|
||||
HMC7044_RESTART_DIV_FSM);
|
||||
mdelay(1);
|
||||
hmc7044_write(dev, HMC7044_REG_REQ_MODE_0,
|
||||
(dev->high_performance_mode_clock_dist_en ?
|
||||
HMC7044_HIGH_PERF_DISTRIB_PATH : 0));
|
||||
mdelay(1);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief hmc7044_reg_init
|
||||
*******************************************************************************/
|
||||
int32_t hmc7044_reg_init(struct hmc7044_dev **device,
|
||||
const struct hmc7044_init_param *init_param)
|
||||
{
|
||||
int ret = SUCCESS;
|
||||
struct hmc7044_dev *dev;
|
||||
|
||||
dev = (struct hmc7044_dev *)malloc(sizeof(*dev));
|
||||
if (!dev)
|
||||
return FAILURE;
|
||||
|
||||
/* SPI */
|
||||
ret = spi_init(&dev->spi_desc, init_param->spi_init);
|
||||
|
||||
*device = dev;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize the device.
|
||||
* @param device - The device structure.
|
||||
* @param init_param - The structure that contains the device initial
|
||||
* parameters.
|
||||
* @return SUCCESS in case of success, negative error code otherwise.
|
||||
*/
|
||||
int32_t hmc7044_init(struct hmc7044_dev **device,
|
||||
const struct hmc7044_init_param *init_param)
|
||||
{
|
||||
struct hmc7044_dev *dev;
|
||||
int32_t ret;
|
||||
unsigned int i;
|
||||
|
||||
dev = (struct hmc7044_dev *)malloc(sizeof(*dev));
|
||||
if (!dev)
|
||||
return FAILURE;
|
||||
|
||||
ret = spi_init(&dev->spi_desc, init_param->spi_init);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
dev->is_hmc7043 = init_param->is_hmc7043;
|
||||
|
||||
dev->clkin_freq[0] = init_param->clkin_freq[0];
|
||||
dev->clkin_freq[1] = init_param->clkin_freq[1];
|
||||
dev->clkin_freq[2] = init_param->clkin_freq[2];
|
||||
dev->clkin_freq[3] = init_param->clkin_freq[3];
|
||||
|
||||
dev->clkin_freq_ccf[0] = init_param->clkin_freq_ccf[0];
|
||||
dev->clkin_freq_ccf[1] = init_param->clkin_freq_ccf[1];
|
||||
dev->clkin_freq_ccf[2] = init_param->clkin_freq_ccf[2];
|
||||
dev->clkin_freq_ccf[3] = init_param->clkin_freq_ccf[3];
|
||||
|
||||
dev->vcxo_freq = init_param->vcxo_freq;
|
||||
dev->pll1_pfd = init_param->pll1_pfd;
|
||||
dev->pll2_freq = init_param->pll2_freq;
|
||||
dev->pll1_loop_bw = init_param->pll1_loop_bw;
|
||||
|
||||
dev->sysref_timer_div = init_param->sysref_timer_div;
|
||||
dev->pll1_ref_prio_ctrl = init_param->pll1_ref_prio_ctrl;
|
||||
dev->clkin0_rfsync_en = init_param->clkin0_rfsync_en;
|
||||
dev->clkin1_vcoin_en = init_param->clkin1_vcoin_en;
|
||||
dev->high_performance_mode_clock_dist_en =
|
||||
init_param->high_performance_mode_clock_dist_en;
|
||||
dev->rf_reseeder_en = !init_param->rf_reseeder_disable;
|
||||
dev->sync_pin_mode = init_param->sync_pin_mode;
|
||||
dev->pulse_gen_mode = init_param->pulse_gen_mode;
|
||||
|
||||
dev->in_buf_mode[0] = init_param->in_buf_mode[0];
|
||||
dev->in_buf_mode[1] = init_param->in_buf_mode[1];
|
||||
dev->in_buf_mode[2] = init_param->in_buf_mode[2];
|
||||
dev->in_buf_mode[3] = init_param->in_buf_mode[3];
|
||||
dev->in_buf_mode[4] = init_param->in_buf_mode[4];
|
||||
|
||||
dev->gpi_ctrl[0] = init_param->gpi_ctrl[0];
|
||||
dev->gpi_ctrl[1] = init_param->gpi_ctrl[1];
|
||||
dev->gpi_ctrl[2] = init_param->gpi_ctrl[2];
|
||||
dev->gpi_ctrl[3] = init_param->gpi_ctrl[3];
|
||||
|
||||
dev->gpo_ctrl[0] = init_param->gpo_ctrl[0];
|
||||
dev->gpo_ctrl[1] = init_param->gpo_ctrl[1];
|
||||
dev->gpo_ctrl[2] = init_param->gpo_ctrl[2];
|
||||
dev->gpo_ctrl[3] = init_param->gpo_ctrl[3];
|
||||
|
||||
dev->num_channels = init_param->num_channels;
|
||||
dev->channels = (struct hmc7044_chan_spec *)
|
||||
malloc(sizeof(*dev->channels) * dev->num_channels);
|
||||
|
||||
for (i = 0; i < dev->num_channels; i++) {
|
||||
dev->channels[i].num = init_param->channels[i].num;
|
||||
dev->channels[i].disable = init_param->channels[i].disable;
|
||||
dev->channels[i].divider = init_param->channels[i].divider;
|
||||
dev->channels[i].driver_mode =
|
||||
init_param->channels[i].driver_mode;
|
||||
dev->channels[i].high_performance_mode_dis =
|
||||
init_param->channels[i].high_performance_mode_dis;
|
||||
dev->channels[i].start_up_mode_dynamic_enable =
|
||||
init_param->channels[i].start_up_mode_dynamic_enable;
|
||||
dev->channels[i].dynamic_driver_enable =
|
||||
init_param->channels[i].dynamic_driver_enable;
|
||||
dev->channels[i].output_control0_rb4_enable =
|
||||
init_param->channels[i].output_control0_rb4_enable;
|
||||
dev->channels[i].force_mute_enable =
|
||||
init_param->channels[i].force_mute_enable;
|
||||
dev->channels[i].driver_impedance =
|
||||
init_param->channels[i].driver_impedance;
|
||||
dev->channels[i].coarse_delay =
|
||||
init_param->channels[i].coarse_delay;
|
||||
dev->channels[i].fine_delay =
|
||||
init_param->channels[i].fine_delay;
|
||||
dev->channels[i].out_mux_mode =
|
||||
init_param->channels[i].out_mux_mode;
|
||||
}
|
||||
|
||||
*device = dev;
|
||||
|
||||
if (!dev->is_hmc7043)
|
||||
return hmc7044_setup(dev);
|
||||
else
|
||||
return hmc7043_setup(dev);
|
||||
}
|
||||
|
||||
/**
|
||||
* Remove the device - release resources.
|
||||
* @param device - The device structure.
|
||||
* @return SUCCESS in case of success, negative error code otherwise.
|
||||
*/
|
||||
int32_t hmc7044_remove(struct hmc7044_dev *device)
|
||||
{
|
||||
int32_t ret;
|
||||
|
||||
ret = spi_remove(device->spi_desc);
|
||||
free(device->channels);
|
||||
free(device);
|
||||
|
||||
return ret;
|
||||
}
|
||||
+276
@@ -0,0 +1,276 @@
|
||||
/***************************************************************************//**
|
||||
* @file hmc7044.h
|
||||
* @brief Header file of HMC7044, HMC7043 Driver.
|
||||
* @author DBogdan ([email protected])
|
||||
********************************************************************************
|
||||
* Copyright 2018-2020(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
#ifndef HMC7044_H_
|
||||
#define HMC7044_H_
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include "../../../include/delay.h"
|
||||
#include "../../../include/spi.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/*************************** Types Declarations *******************************/
|
||||
/******************************************************************************/
|
||||
// Enum to select SYNC pin configuration with respect to PLL2 (0x0005)
|
||||
typedef enum
|
||||
{
|
||||
SYNC_DISABLED = 0,
|
||||
SYNC_MULTICHIP = 1,
|
||||
SYNC_PULSE_GEN = 2,
|
||||
SYNC_ALARM = 3
|
||||
} hmc7044SyncPinModeSelect_t;
|
||||
|
||||
// Enum to select input buffer mode (0x000A, 0x000B, 0x000C, 0x000D, 0x000E)
|
||||
typedef enum
|
||||
{
|
||||
BUFFER_ENABLE = (1) << 0,
|
||||
BUFFER_DISABLE = (0) << 0,
|
||||
ENABLE_INTERNAL_TERM = (1) << 1,
|
||||
ENABLE_AC_COUPLE = (1) << 2,
|
||||
ENABLE_LVPECL = (1) << 3,
|
||||
ENABLE_HIGH_Z = (1) << 4
|
||||
} hmc7044InputBufferMode_t;
|
||||
|
||||
// Enum to select output driver mode (0x003A, 0x003B, 0x00D0, 0x00DA, 0x00E4,
|
||||
// 0x00EE, 0x00F8, 0x0102, 0x010C, 0x0116, 0x0120, 0x012A, 0x0134, 0x013E,
|
||||
// 0x0148, 0x0152)
|
||||
typedef enum
|
||||
{
|
||||
CML = 0,
|
||||
LVPECL = 1,
|
||||
LVDS = 2,
|
||||
CMOS = 3
|
||||
} hmc7044DriverMode_t;
|
||||
|
||||
// Enum to select the GPIx functionality. (0x0046, 0x0047, 0x0048, 0x0049)
|
||||
typedef enum
|
||||
{
|
||||
GPI_ENABLE = (1) << 0,
|
||||
GPI_DISABLE = (0) << 0,
|
||||
FORCE_PLL1_HOLDOVER = (0x01) << 1 | GPI_ENABLE,
|
||||
SELECT_PLL1_REF_BIT1 = (0x02) << 1 | GPI_ENABLE,
|
||||
SELECT_PLL1_REF_BIT2 = (0x03) << 1 | GPI_ENABLE,
|
||||
CHIP_SLEEP_MODE = (0x04) << 1 | GPI_ENABLE,
|
||||
MUTE_REQUSET = (0x05) << 1 | GPI_ENABLE,
|
||||
SELECT_INTERNAL_VCO_TYPE = (0x06) << 1 | GPI_ENABLE,
|
||||
SELECT_HI_PERF_MODE = (0x07) << 1 | GPI_ENABLE,
|
||||
PULSE_GEN_REQUSET = (0x08) << 1 | GPI_ENABLE,
|
||||
RESEED_REQUEST = (0x09) << 1 | GPI_ENABLE,
|
||||
RESTART_REQUSET = (0x0A) << 1 | GPI_ENABLE,
|
||||
FORCE_FANOUT_MODE = (0x0B) << 1 | GPI_ENABLE,
|
||||
SLIP_REQUEST = (0x0D) << 1 | GPI_ENABLE,
|
||||
} hmc7044GPIControl_t;
|
||||
|
||||
// Enum to select the GPOx functionality. (0x0050, 0x0051, 0x0052, 0x0053)
|
||||
typedef enum
|
||||
{
|
||||
GPO_ENABLE = (1) << 0,
|
||||
GPO_DISABLE = (0) << 0,
|
||||
GPO_CMOS_MODE = (1) << 1,
|
||||
GPO_OPEN_DRAIN_MODE = (0) << 1,
|
||||
ALARM_SIGNAL = (0x00) << 3 | GPO_ENABLE,
|
||||
SPI_SDATA = (0x01) << 3 | GPO_ENABLE,
|
||||
CLKIN3_SIGNAL_LOSS = (0x02) << 3 | GPO_ENABLE,
|
||||
CLKIN2_SIGNAL_LOSS = (0x03) << 3 | GPO_ENABLE,
|
||||
CLKIN1_SIGNAL_LOSS = (0x04) << 3 | GPO_ENABLE,
|
||||
CLKIN0_SIGNAL_LOSS = (0x05) << 3 | GPO_ENABLE,
|
||||
PLL1_HOLDOVER_ENABLE = (0x06) << 3 | GPO_ENABLE,
|
||||
PLL1_LOCK_DETECT = (0x07) << 3 | GPO_ENABLE,
|
||||
PLL1_ACQUIRING_LOCK = (0x08) << 3 | GPO_ENABLE,
|
||||
PLL1_NEAR_CLOCK_ACQ_STAT = (0x09) << 3 | GPO_ENABLE,
|
||||
PLL2_LOCK_DETECT = (0x0A) << 3 | GPO_ENABLE,
|
||||
PLL2_SYSREF_SYNC = (0x0B) << 3 | GPO_ENABLE,
|
||||
CLOCK_OUTPUT_PHASE_STAT = (0x0C) << 3 | GPO_ENABLE,
|
||||
PLL1_PLL2_LOCKED = (0x0D) << 3 | GPO_ENABLE,
|
||||
SYNC_REQUSRT_STAT = (0x0E) << 3 | GPO_ENABLE,
|
||||
PLL1_ACTIVE_CLKIN0 = (0x0F) << 3 | GPO_ENABLE,
|
||||
PLL1_ACTIVE_CLKIN1 = (0x10) << 3 | GPO_ENABLE,
|
||||
PLL1_HOLDOVER_IN_RANGE_STAT = (0x11) << 3 | GPO_ENABLE,
|
||||
PLL1_HOLDOVER_IN_STAT = (0x12) << 3 | GPO_ENABLE,
|
||||
PLL1_VCXO_STAT = (0x13) << 3 | GPO_ENABLE,
|
||||
PLL1_ACTIVE_CLKINx_STAT = (0x14) << 3 | GPO_ENABLE,
|
||||
PLL1_FSM_BIT0 = (0x15) << 3 | GPO_ENABLE,
|
||||
PLL1_FSM_BIT1 = (0x16) << 3 | GPO_ENABLE,
|
||||
PLL1_FSM_BIT2 = (0x17) << 3 | GPO_ENABLE,
|
||||
PLL1_HOLDOVER_EXIT_PHASE_BIT0 = (0x18) << 3 | GPO_ENABLE,
|
||||
PLL1_HOLDOVER_EXIT_PHASE_BIT1 = (0x19) << 3 | GPO_ENABLE,
|
||||
CHANNEL_OUTPUT_FSM_BUSY = (0x1A) << 3 | GPO_ENABLE,
|
||||
SYSREF_FSM_STAT_BIT0 = (0x1B) << 3 | GPO_ENABLE,
|
||||
SYSREF_FSM_STAT_BIT1 = (0x1C) << 3 | GPO_ENABLE,
|
||||
SYSREF_FSM_STAT_BIT2 = (0x1D) << 3 | GPO_ENABLE,
|
||||
SYSREF_FSM_STAT_BIT3 = (0x1E) << 3 | GPO_ENABLE,
|
||||
FORCE_LOGIC_1 = (0x1F) << 3 | GPO_ENABLE,
|
||||
FORCE_LOGIC_0 = (0x20) << 3 | GPO_ENABLE,
|
||||
PLL1_HOLDOVER_AVG_VALUE_BIT0 = (0x27) << 3 | GPO_ENABLE,
|
||||
PLL1_HOLDOVER_AVG_VALUE_BIT1 = (0x28) << 3 | GPO_ENABLE,
|
||||
PLL1_HOLDOVER_AVG_VALUE_BIT2 = (0x29) << 3 | GPO_ENABLE,
|
||||
PLL1_HOLDOVER_AVG_VALUE_BIT3 = (0x2A) << 3 | GPO_ENABLE,
|
||||
PLL1_HOLDOVER_CURR_VALUE_BIT0 = (0x2B) << 3 | GPO_ENABLE,
|
||||
PLL1_HOLDOVER_CURR_VALUE_BIT1 = (0x2C) << 3 | GPO_ENABLE,
|
||||
PLL1_HOLDOVER_CURR_VALUE_BIT2 = (0x2D) << 3 | GPO_ENABLE,
|
||||
PLL1_HOLDOVER_CURR_VALUE_BIT3 = (0x2E) << 3 | GPO_ENABLE
|
||||
} hmc7044GPOControl_t;
|
||||
|
||||
// Enum to select output channel (0x00CF, 0x00D9, 0x00E3, 0x00ED, 0x00F7,
|
||||
// 0x0101, 0x010B, 0x0115, 0x011F, 0x0129, 0x0133, 0x013D, 0x0147, 0x0151
|
||||
typedef enum
|
||||
{
|
||||
CHANNEL_DIV = 0,
|
||||
ANALOG_DELAY = 1,
|
||||
OTHER_CHANNEL = 2,
|
||||
VCO_CLOCK = 3
|
||||
} hmc7044OutputMuxSelect_t;
|
||||
|
||||
// Enum to select output driver impedance selection for CML mode (0x00D0,
|
||||
// 0x00DA, 0x00E4, 0x00EE, 0x00F8, 0x0102, 0x010C, 0x0116, 0x0120, 0x012A,
|
||||
// 0x0134, 0x013E, 0x0148, 0x0152)
|
||||
typedef enum
|
||||
{
|
||||
INTERNAL_RES_DISABLE = 0,
|
||||
INTERNAL_100OHM_PER_PIN = 1,
|
||||
// INTERNAL_RES_RESERVED = 2,
|
||||
INTERNAL_50OHM_PER_PIN = 3
|
||||
} hmc7044DriverImpedance_t;
|
||||
|
||||
// Enum to select pulse generator mode (0x005A)
|
||||
typedef enum
|
||||
{
|
||||
PULSE_LEVEL_SENSITIVE = 0,
|
||||
PULSE_ONE = 1,
|
||||
PULSE_TWO = 2,
|
||||
PULSE_FOUR = 3,
|
||||
PULSE_EIGHT = 4,
|
||||
PULSE_SIXTEEN = 5,
|
||||
// PULSE_SIXTEEN = 6,
|
||||
PULSE_CONTINOUS = 7
|
||||
} hmc7044SyncPulseGenControl_t;
|
||||
|
||||
struct hmc7044_chan_spec {
|
||||
unsigned int num;
|
||||
bool disable;
|
||||
bool high_performance_mode_dis;
|
||||
bool start_up_mode_dynamic_enable;
|
||||
bool dynamic_driver_enable;
|
||||
bool output_control0_rb4_enable;
|
||||
bool force_mute_enable;
|
||||
unsigned int divider;
|
||||
unsigned int coarse_delay;
|
||||
unsigned int fine_delay;
|
||||
hmc7044DriverMode_t driver_mode;
|
||||
hmc7044DriverImpedance_t driver_impedance;
|
||||
hmc7044OutputMuxSelect_t out_mux_mode;
|
||||
};
|
||||
|
||||
struct hmc7044_config {
|
||||
uint16_t addr;
|
||||
uint8_t value;
|
||||
};
|
||||
|
||||
struct hmc7044_dev {
|
||||
spi_desc *spi_desc;
|
||||
bool is_hmc7043;
|
||||
uint32_t clkin_freq[4];
|
||||
uint32_t clkin_freq_ccf[4];
|
||||
uint32_t vcxo_freq;
|
||||
uint32_t pll1_pfd;
|
||||
uint32_t pll2_freq;
|
||||
uint32_t pll1_loop_bw;
|
||||
uint32_t sysref_timer_div;
|
||||
unsigned int pll1_ref_prio_ctrl;
|
||||
bool clkin0_rfsync_en;
|
||||
bool clkin1_vcoin_en;
|
||||
bool high_performance_mode_clock_dist_en;
|
||||
bool rf_reseeder_en;
|
||||
hmc7044SyncPinModeSelect_t sync_pin_mode;
|
||||
hmc7044SyncPulseGenControl_t pulse_gen_mode;
|
||||
uint32_t in_buf_mode[5];
|
||||
uint32_t gpi_ctrl[4];
|
||||
uint32_t gpo_ctrl[4];
|
||||
uint32_t num_channels;
|
||||
struct hmc7044_chan_spec *channels;
|
||||
};
|
||||
|
||||
struct hmc7044_init_param {
|
||||
spi_init_param *spi_init;
|
||||
bool is_hmc7043;
|
||||
uint32_t clkin_freq[4];
|
||||
uint32_t clkin_freq_ccf[4];
|
||||
uint32_t vcxo_freq;
|
||||
uint32_t pll1_pfd;
|
||||
uint32_t pll2_freq;
|
||||
uint32_t pll1_loop_bw;
|
||||
uint32_t sysref_timer_div;
|
||||
unsigned int pll1_ref_prio_ctrl;
|
||||
bool clkin0_rfsync_en;
|
||||
bool clkin1_vcoin_en;
|
||||
bool high_performance_mode_clock_dist_en;
|
||||
bool rf_reseeder_disable;
|
||||
hmc7044SyncPinModeSelect_t sync_pin_mode;
|
||||
hmc7044SyncPulseGenControl_t pulse_gen_mode;
|
||||
uint32_t in_buf_mode[5];
|
||||
uint32_t gpi_ctrl[4];
|
||||
uint32_t gpo_ctrl[4];
|
||||
uint32_t num_channels;
|
||||
struct hmc7044_chan_spec *channels;
|
||||
};
|
||||
|
||||
/******************************************************************************/
|
||||
/************************ Functions Declarations ******************************/
|
||||
/******************************************************************************/
|
||||
/* Initialize the device. */
|
||||
int32_t hmc7044_reg_init(struct hmc7044_dev **device,
|
||||
const struct hmc7044_init_param *init_param);
|
||||
int32_t hmc7044_init(struct hmc7044_dev **device,
|
||||
const struct hmc7044_init_param *init_param);
|
||||
/* Remove the device. */
|
||||
int32_t hmc7044_remove(struct hmc7044_dev *device);
|
||||
int32_t hmc7044_write(struct hmc7044_dev *dev,
|
||||
uint16_t reg, uint8_t val);
|
||||
int32_t hmc7044_read(struct hmc7044_dev *dev, uint16_t reg, uint8_t *val);
|
||||
int32_t hmc7044_clk_recalc_rate(struct hmc7044_dev *dev, uint32_t chan_num,
|
||||
uint64_t *rate);
|
||||
int32_t hmc7044_clk_round_rate(struct hmc7044_dev *dev, uint32_t rate,
|
||||
uint64_t *rounded_rate);
|
||||
int32_t hmc7044_clk_set_rate(struct hmc7044_dev *dev, uint32_t chan_num,
|
||||
uint64_t rate);
|
||||
|
||||
#endif // HMC7044_H_
|
||||
+79
@@ -0,0 +1,79 @@
|
||||
/***************************************************************************//**
|
||||
* @file xilinx/axi_io.c
|
||||
* @brief Implementation of Xilinx AXI IO.
|
||||
* @author Antoniu Miclaus ([email protected])
|
||||
********************************************************************************
|
||||
* Copyright 2019(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
|
||||
#include <xil_io.h>
|
||||
#include "../../include/error.h"
|
||||
#include "../../include/axi_io.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/************************ Functions Definitions *******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief AXI IO Xilinx specific read function.
|
||||
* @param base - Base address
|
||||
* @param offset - Address offset
|
||||
* @param data - variable where returned data is stored
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t axi_io_read(uint32_t base, uint32_t offset, uint32_t *data)
|
||||
{
|
||||
*data = Xil_In32(base + offset);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief AXI IO Xilinx specific write function.
|
||||
* @param base - Base address
|
||||
* @param offset - Address offset
|
||||
* @param data - data to be written.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t axi_io_write(uint32_t base, uint32_t offset, uint32_t data)
|
||||
{
|
||||
Xil_Out32(base + offset, data);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
+77
@@ -0,0 +1,77 @@
|
||||
/***************************************************************************//**
|
||||
* @file xilinx/delay.c
|
||||
* @brief Implementation of Xilinx Delay Functions.
|
||||
* @author Antoniu Miclaus ([email protected])
|
||||
********************************************************************************
|
||||
* Copyright 2019(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
|
||||
#include "../../include/delay.h"
|
||||
#include <sleep.h>
|
||||
|
||||
/******************************************************************************/
|
||||
/************************ Functions Definitions *******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief Generate microseconds delay.
|
||||
* @param usecs - Delay in microseconds.
|
||||
* @return None.
|
||||
*/
|
||||
void udelay(uint32_t usecs)
|
||||
{
|
||||
#ifdef _XPARAMETERS_PS_H_
|
||||
usleep(usecs);
|
||||
#else
|
||||
usleep(usecs / 20); // FIXME
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Generate miliseconds delay.
|
||||
* @param msecs - Delay in miliseconds.
|
||||
* @return None.
|
||||
*/
|
||||
void mdelay(uint32_t msecs)
|
||||
{
|
||||
#ifdef _XPARAMETERS_PS_H_
|
||||
usleep(msecs * 1000);
|
||||
#else
|
||||
usleep(msecs * 50); // FIXME
|
||||
#endif
|
||||
}
|
||||
+95
@@ -0,0 +1,95 @@
|
||||
/*******************************************************************************
|
||||
* @file xilinx/gpio_extra.h
|
||||
* @brief Header containing extra types used in the gpio driver
|
||||
* @author scuciurean ([email protected])
|
||||
********************************************************************************
|
||||
* Copyright 2019(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef GPIO_EXTRA_H_
|
||||
#define GPIO_EXTRA_H_
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
/******************************************************************************/
|
||||
/*************************** Types Declarations *******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @enum xil_gpio_type
|
||||
* @brief Xilinx platform architecture sections
|
||||
*/
|
||||
typedef enum xil_gpio_type {
|
||||
/** Programmable Logic */
|
||||
GPIO_PL,
|
||||
/** Processing System */
|
||||
GPIO_PS
|
||||
} xil_gpio_type;
|
||||
|
||||
/**
|
||||
* @struct xil_gpio_init_param
|
||||
* @brief Structure holding the initialization parameters for Xilinx platform
|
||||
* specific GPIO parameters.
|
||||
*/
|
||||
typedef struct xil_gpio_init_param {
|
||||
/** Xilinx architecture */
|
||||
enum xil_gpio_type type;
|
||||
/** Device ID */
|
||||
uint32_t device_id;
|
||||
} xil_gpio_init_param;
|
||||
|
||||
/**
|
||||
* @struct xil_gpio_desc
|
||||
* @brief Xilinx platform specific GPIO descriptor
|
||||
*/
|
||||
typedef struct xil_gpio_desc {
|
||||
/** Xilinx architecture */
|
||||
enum xil_gpio_type type;
|
||||
/** Xilinx GPIO configuration */
|
||||
void *config;
|
||||
/** Xilinx GPIO Instance */
|
||||
void *instance;
|
||||
} xil_gpio_desc;
|
||||
|
||||
/**
|
||||
* @brief Xilinx platform specific gpio platform ops structure
|
||||
*/
|
||||
extern const struct gpio_platform_ops xil_gpio_ops;
|
||||
|
||||
#endif
|
||||
+91
@@ -0,0 +1,91 @@
|
||||
/*******************************************************************************
|
||||
* @file irq_extra.h
|
||||
* @brief Header containing types used in the irq driver.
|
||||
* @author Cristian Pop ([email protected])
|
||||
********************************************************************************
|
||||
* Copyright 2019(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef IRQ_EXTRA_H_
|
||||
#define IRQ_EXTRA_H_
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "../../include/irq.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/*************************** Types Declarations *******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @enum xil_irq_type
|
||||
* @brief Xilinx platform architecture sections
|
||||
*/
|
||||
enum xil_irq_type {
|
||||
/** Programmable Logic */
|
||||
IRQ_PL,
|
||||
/** Processing System */
|
||||
IRQ_PS
|
||||
};
|
||||
|
||||
/**
|
||||
* @struct xil_irq_init_param
|
||||
* @brief Structure holding the initialization parameters for Xilinx platform
|
||||
* specific IRQ parameters.
|
||||
*/
|
||||
struct xil_irq_init_param {
|
||||
/** Xilinx architecture */
|
||||
enum xil_irq_type type;
|
||||
};
|
||||
|
||||
/**
|
||||
* @struct xil_irq_desc
|
||||
* @brief Xilinx platform specific IRQ descriptor
|
||||
*/
|
||||
struct xil_irq_desc {
|
||||
/** Xilinx architecture */
|
||||
enum xil_irq_type type;
|
||||
/** Xilinx IRQ Instance */
|
||||
void *instance;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Xilinx specific IRQ platform ops structure
|
||||
*/
|
||||
extern const struct irq_platform_ops xil_irq_ops;
|
||||
|
||||
#endif
|
||||
+115
@@ -0,0 +1,115 @@
|
||||
/*******************************************************************************
|
||||
* @file xilinx/spi_extra.h
|
||||
* @brief Header containing extra types used in the spi driver.
|
||||
* @author scuciurean ([email protected])
|
||||
********************************************************************************
|
||||
* Copyright 2019(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
#ifndef SPI_EXTRA_H_
|
||||
#define SPI_EXTRA_H_
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "../../include/spi.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/********************** Macros and Constants Definitions **********************/
|
||||
/******************************************************************************/
|
||||
|
||||
#define SPI_CS_DECODE 0x01
|
||||
#define SPI_DEASSERT_CURRENT_SS 0x0F
|
||||
|
||||
/******************************************************************************/
|
||||
/*************************** Types Declarations *******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @enum xil_spi_type
|
||||
* @brief Xilinx platform architecture sections
|
||||
*/
|
||||
enum xil_spi_type {
|
||||
/** Programmable Logic */
|
||||
SPI_PL,
|
||||
/** Processing System */
|
||||
SPI_PS,
|
||||
/** SPI Engine */
|
||||
SPI_ENGINE
|
||||
};
|
||||
|
||||
/**
|
||||
* @struct xil_spi_init_param
|
||||
* @brief Structure holding the initialization parameters for Xilinx platform
|
||||
* specific SPI parameters when using xil_spi_ops.
|
||||
*/
|
||||
typedef struct xil_spi_init_param {
|
||||
/** Xilinx architecture */
|
||||
enum xil_spi_type type;
|
||||
/** SPI flags */
|
||||
uint32_t flags;
|
||||
} xil_spi_init_param;
|
||||
|
||||
/**
|
||||
* @struct xil_spi_desc
|
||||
* @brief Xilinx platform specific SPI descriptor
|
||||
*/
|
||||
typedef struct xil_spi_desc {
|
||||
/** Xilinx architecture */
|
||||
enum xil_spi_type type;
|
||||
/** SPI flags */
|
||||
uint32_t flags;
|
||||
/** SPI configuration */
|
||||
void *config;
|
||||
/** SPI instance */
|
||||
void *instance;
|
||||
} xil_spi_desc;
|
||||
|
||||
/**
|
||||
* @brief SPI engine platform ops structure
|
||||
*/
|
||||
extern const struct spi_platform_ops spi_eng_platform_ops;
|
||||
|
||||
/**
|
||||
* @brief Xilinx specific SPI platform ops structure
|
||||
*/
|
||||
extern const struct spi_platform_ops xil_spi_ops;
|
||||
|
||||
/**
|
||||
* @brief Xilinx SPI PS register functions. No extra param needed
|
||||
*/
|
||||
extern const struct spi_platform_ops xil_spi_reg_ops_pl;
|
||||
|
||||
#endif // SPI_EXTRA_H_
|
||||
+107
@@ -0,0 +1,107 @@
|
||||
/*******************************************************************************
|
||||
* @file xilinx/uart_extra.h
|
||||
* @brief Header containing types used in the uart driver.
|
||||
* @author Cristian Pop ([email protected])
|
||||
********************************************************************************
|
||||
* Copyright 2019(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef UART_EXTRA_H_
|
||||
#define UART_EXTRA_H_
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/********************** Macros and Constants Definitions **********************/
|
||||
/******************************************************************************/
|
||||
|
||||
#define UART_BUFF_LENGTH 256
|
||||
|
||||
/******************************************************************************/
|
||||
/*************************** Types Declarations *******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @enum xil_uart_type
|
||||
* @brief Xilinx platform architecture sections
|
||||
*/
|
||||
enum xil_uart_type {
|
||||
/** Programmable Logic */
|
||||
UART_PL,
|
||||
/** Processing System */
|
||||
UART_PS
|
||||
};
|
||||
|
||||
/**
|
||||
* @struct xil_uart_init_param
|
||||
* @brief Structure holding the initialization parameters for Xilinx platform
|
||||
* specific UART parameters.
|
||||
*/
|
||||
struct xil_uart_init_param {
|
||||
/** Xilinx architecture */
|
||||
enum xil_uart_type type;
|
||||
/** Interrupt Request ID */
|
||||
uint32_t irq_id;
|
||||
/** Interrupt Request Descriptor */
|
||||
struct irq_ctrl_desc *irq_desc;
|
||||
};
|
||||
|
||||
/**
|
||||
* @struct xil_uart_desc
|
||||
* @brief Xilinx platform specific UART descriptor
|
||||
*/
|
||||
struct xil_uart_desc {
|
||||
/** Xilinx architecture */
|
||||
enum xil_uart_type type;
|
||||
/** Interrupt Request ID */
|
||||
uint32_t irq_id;
|
||||
/** Interrupt Request Descriptor */
|
||||
struct irq_ctrl_desc *irq_desc;
|
||||
/** FIFO */
|
||||
struct fifo_element *fifo;
|
||||
/** FIFO read offset */
|
||||
uint32_t fifo_read_offset;
|
||||
/** UART Buffer */
|
||||
char buff[UART_BUFF_LENGTH];
|
||||
/** Number of bytes received */
|
||||
uint32_t bytes_received;
|
||||
/** Total number of errors */
|
||||
uint32_t total_error_count;
|
||||
/** UART Instance */
|
||||
void *instance;
|
||||
};
|
||||
|
||||
#endif
|
||||
+464
@@ -0,0 +1,464 @@
|
||||
/***************************************************************************//**
|
||||
* @file xilinx/xilinx_gpio.c
|
||||
* @brief Implementation of Xilinx GPIO Generic Driver.
|
||||
* @author Antoniu Miclaus ([email protected])
|
||||
********************************************************************************
|
||||
* Copyright 2019(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
|
||||
#include <stdlib.h>
|
||||
|
||||
#include <xparameters.h>
|
||||
#ifdef XPAR_XGPIO_NUM_INSTANCES
|
||||
#include <xgpio.h>
|
||||
#endif
|
||||
#ifdef XPAR_XGPIOPS_NUM_INSTANCES
|
||||
#include <xgpiops.h>
|
||||
#endif
|
||||
|
||||
#include "gpio_extra.h"
|
||||
#include "../../include/error.h"
|
||||
#include "../../include/gpio.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/************************ Functions Definitions *******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief Prepare the GPIO decriptor.
|
||||
* @param desc - The GPIO descriptor.
|
||||
* @param param - The structure that contains the GPIO parameters.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t _gpio_init(struct gpio_desc *desc,
|
||||
const struct gpio_init_param *param)
|
||||
{
|
||||
int32_t ret;
|
||||
struct xil_gpio_desc *xdesc;
|
||||
struct xil_gpio_init_param *xinit;
|
||||
|
||||
ret = FAILURE;
|
||||
|
||||
xdesc = desc->extra;
|
||||
xinit = param->extra;
|
||||
|
||||
xdesc->type = xinit->type;
|
||||
desc->number = param->number;
|
||||
|
||||
switch (xinit->type) {
|
||||
case GPIO_PL:
|
||||
#ifdef XGPIO_H
|
||||
xdesc->instance = (XGpio *)malloc(sizeof(XGpio));
|
||||
if(!xdesc->instance)
|
||||
goto pl_error;
|
||||
|
||||
xdesc->config = XGpio_LookupConfig(xinit->device_id);
|
||||
if(xdesc->config == NULL)
|
||||
goto pl_error;
|
||||
|
||||
ret = XGpio_CfgInitialize(xdesc->instance,
|
||||
xdesc->config,
|
||||
((XGpio_Config*)xdesc->config)
|
||||
->BaseAddress);
|
||||
if(ret < 0)
|
||||
goto pl_error;
|
||||
|
||||
break;
|
||||
pl_error:
|
||||
free(xdesc->instance);
|
||||
#endif
|
||||
goto error;
|
||||
case GPIO_PS:
|
||||
#ifdef XGPIOPS_H
|
||||
xdesc->instance = (XGpioPs *)malloc(sizeof(XGpioPs));
|
||||
if(!xdesc->instance)
|
||||
goto ps_error;
|
||||
|
||||
xdesc->config = XGpioPs_LookupConfig(xinit->device_id);
|
||||
if(xdesc->config == NULL)
|
||||
goto ps_error;
|
||||
|
||||
ret = XGpioPs_CfgInitialize(xdesc->instance,
|
||||
xdesc->config,
|
||||
((XGpioPs_Config*)xdesc->config)->BaseAddr);
|
||||
if(ret < 0)
|
||||
goto ps_error;
|
||||
break;
|
||||
ps_error:
|
||||
free(xdesc->instance);
|
||||
#endif
|
||||
goto error;
|
||||
error:
|
||||
default:
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Obtain the GPIO decriptor.
|
||||
* @param desc - The GPIO descriptor.
|
||||
* @param param - GPIO initialization parameters
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t xil_gpio_get(struct gpio_desc **desc,
|
||||
const struct gpio_init_param *param)
|
||||
{
|
||||
struct gpio_desc *descriptor;
|
||||
struct xil_gpio_desc *extra;
|
||||
int32_t ret;
|
||||
|
||||
descriptor = (struct gpio_desc *)malloc(sizeof(*descriptor));
|
||||
extra = (struct xil_gpio_desc*)malloc(sizeof(*extra));
|
||||
|
||||
if (!descriptor || !extra)
|
||||
return FAILURE;
|
||||
|
||||
descriptor->extra = extra;
|
||||
ret = _gpio_init(descriptor, param);
|
||||
|
||||
if(ret != SUCCESS)
|
||||
goto error;
|
||||
|
||||
*desc = descriptor;
|
||||
|
||||
return SUCCESS;
|
||||
error:
|
||||
free(extra);
|
||||
free(descriptor);
|
||||
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the value of an optional GPIO.
|
||||
* @param desc - The GPIO descriptor.
|
||||
* @param param - GPIO Initialization parameters.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t xil_gpio_get_optional(struct gpio_desc **desc,
|
||||
const struct gpio_init_param *param)
|
||||
{
|
||||
if(param == NULL) {
|
||||
*desc = NULL;
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
return xil_gpio_get(desc, param);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Free the resources allocated by gpio_get().
|
||||
* @param desc - The GPIO descriptor.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t xil_gpio_remove(struct gpio_desc *desc)
|
||||
{
|
||||
if (desc != NULL) {
|
||||
free(((xil_gpio_desc *)(desc->extra))->instance);
|
||||
free(desc->extra);
|
||||
free(desc);
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the input direction of the specified GPIO.
|
||||
* @param desc - The GPIO descriptor.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t xil_gpio_direction_input(struct gpio_desc *desc)
|
||||
{
|
||||
struct xil_gpio_desc *extra;
|
||||
#ifdef XGPIO_H
|
||||
uint8_t pin = desc->number;
|
||||
uint32_t channel = 1;
|
||||
uint32_t config = 0;
|
||||
#endif
|
||||
extra = desc->extra;
|
||||
|
||||
switch (extra->type) {
|
||||
case GPIO_PL:
|
||||
#ifdef XGPIO_H
|
||||
/* We assume that pin 32 is the first pin from channel 2 */
|
||||
if (pin >= 32) {
|
||||
channel = 2;
|
||||
pin -= 32;
|
||||
}
|
||||
|
||||
config = XGpio_GetDataDirection((XGpio *)extra->instance,
|
||||
channel);
|
||||
config |= (1 << pin);
|
||||
XGpio_SetDataDirection((XGpio *)extra->instance,
|
||||
channel,
|
||||
config);
|
||||
#endif
|
||||
break;
|
||||
case GPIO_PS:
|
||||
#ifdef XGPIOPS_H
|
||||
XGpioPs_SetDirectionPin(extra->instance,
|
||||
desc->number,
|
||||
GPIO_IN);
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the output direction of the specified GPIO.
|
||||
* @param desc - The GPIO descriptor.
|
||||
* @param value - The value.
|
||||
* Example: GPIO_HIGH
|
||||
* GPIO_LOW
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t xil_gpio_direction_output(struct gpio_desc *desc,
|
||||
uint8_t value)
|
||||
{
|
||||
struct xil_gpio_desc *extra;
|
||||
#ifdef XGPIO_H
|
||||
uint8_t pin = desc->number;
|
||||
uint8_t channel;
|
||||
uint32_t reg_val;
|
||||
#endif
|
||||
extra = desc->extra;
|
||||
|
||||
switch (extra->type) {
|
||||
case GPIO_PL:
|
||||
#ifdef XGPIO_H
|
||||
if (pin >= 32) {
|
||||
channel = 2;
|
||||
pin -= 32;
|
||||
} else
|
||||
channel = 1;
|
||||
|
||||
reg_val = XGpio_GetDataDirection(extra->instance,
|
||||
channel);
|
||||
reg_val &= ~(1 << pin);
|
||||
XGpio_SetDataDirection(extra->instance,
|
||||
channel,
|
||||
reg_val);
|
||||
reg_val = XGpio_DiscreteRead(extra->instance,
|
||||
channel);
|
||||
if(value)
|
||||
reg_val |= (1 << pin);
|
||||
else
|
||||
reg_val &= ~(1 << pin);
|
||||
XGpio_DiscreteWrite(extra->instance,
|
||||
channel,
|
||||
reg_val);
|
||||
#endif
|
||||
break;
|
||||
case GPIO_PS:
|
||||
#ifdef XGPIOPS_H
|
||||
XGpioPs_SetDirectionPin(extra->instance,
|
||||
desc->number,
|
||||
GPIO_OUT);
|
||||
XGpioPs_SetOutputEnablePin(extra->instance,
|
||||
desc->number,
|
||||
GPIO_OUT);
|
||||
XGpioPs_WritePin(extra->instance,
|
||||
desc->number,
|
||||
value);
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the direction of the specified GPIO.
|
||||
* @param desc - The GPIO descriptor.
|
||||
* @param direction - The direction.
|
||||
* Example: GPIO_OUT
|
||||
* GPIO_IN
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t xil_gpio_get_direction(struct gpio_desc *desc,
|
||||
uint8_t *direction)
|
||||
{
|
||||
if (!desc)
|
||||
return FAILURE;
|
||||
|
||||
struct xil_gpio_desc *extra;
|
||||
uint8_t pin = desc->number;
|
||||
|
||||
#ifdef XGPIO_H
|
||||
uint8_t channel;
|
||||
#endif
|
||||
extra = desc->extra;
|
||||
|
||||
switch (extra->type) {
|
||||
case GPIO_PL:
|
||||
#ifdef XGPIO_H
|
||||
if (pin >= 32) {
|
||||
channel = 2;
|
||||
pin -= 32;
|
||||
} else
|
||||
channel = 1;
|
||||
*direction = ((XGpio_GetDataDirection(extra->instance,
|
||||
channel) >> pin) & 0x1) ^ 0x1;
|
||||
#endif
|
||||
break;
|
||||
case GPIO_PS:
|
||||
#ifdef XGPIOPS_H
|
||||
*direction = XGpioPs_GetDirectionPin(extra->instance, pin);
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the value of the specified GPIO.
|
||||
* @param desc - The GPIO descriptor.
|
||||
* @param value - The value.
|
||||
* Example: GPIO_HIGH
|
||||
* GPIO_LOW
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t xil_gpio_set_value(struct gpio_desc *desc,
|
||||
uint8_t value)
|
||||
{
|
||||
struct xil_gpio_desc *extra;
|
||||
#ifdef XGPIO_H
|
||||
uint8_t pin = desc->number;
|
||||
uint8_t channel;
|
||||
uint32_t reg_val;
|
||||
#endif
|
||||
extra = desc->extra;
|
||||
|
||||
switch (extra->type) {
|
||||
case GPIO_PL:
|
||||
#ifdef XGPIO_H
|
||||
if (pin >= 32) {
|
||||
channel = 2;
|
||||
pin -= 32;
|
||||
} else
|
||||
channel = 1;
|
||||
|
||||
reg_val = XGpio_DiscreteRead(extra->instance, channel);
|
||||
if(value)
|
||||
reg_val |= (1 << pin);
|
||||
else
|
||||
reg_val &= ~(1 << pin);
|
||||
XGpio_DiscreteWrite(extra->instance, channel, reg_val);
|
||||
#endif
|
||||
break;
|
||||
case GPIO_PS:
|
||||
#ifdef XGPIOPS_H
|
||||
XGpioPs_WritePin(extra->instance, desc->number, value);
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the value of the specified GPIO.
|
||||
* @param desc - The GPIO descriptor.
|
||||
* @param value - The value.
|
||||
* Example: GPIO_HIGH
|
||||
* GPIO_LOW
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t xil_gpio_get_value(struct gpio_desc *desc,
|
||||
uint8_t *value)
|
||||
{
|
||||
if (!desc)
|
||||
return FAILURE;
|
||||
|
||||
struct xil_gpio_desc *extra;
|
||||
uint8_t pin = desc->number;
|
||||
|
||||
#ifdef XGPIO_H
|
||||
uint8_t channel;
|
||||
#endif
|
||||
extra = desc->extra;
|
||||
|
||||
switch (extra->type) {
|
||||
case GPIO_PL:
|
||||
#ifdef XGPIO_H
|
||||
if (pin >= 32) {
|
||||
channel = 2;
|
||||
pin -= 32;
|
||||
} else
|
||||
channel = 1;
|
||||
*value = (XGpio_DiscreteRead(extra->instance, channel) >> pin) & 0x01;
|
||||
#endif
|
||||
break;
|
||||
case GPIO_PS:
|
||||
#ifdef XGPIOPS_H
|
||||
*value = XGpioPs_ReadPin(extra->instance, pin);
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Xilinx platform specific GPIO platform ops structure
|
||||
*/
|
||||
const struct gpio_platform_ops xil_gpio_ops = {
|
||||
.gpio_ops_get = &xil_gpio_get,
|
||||
.gpio_ops_get_optional = &xil_gpio_get_optional,
|
||||
.gpio_ops_remove = &xil_gpio_remove,
|
||||
.gpio_ops_direction_input = &xil_gpio_direction_input,
|
||||
.gpio_ops_direction_output = &xil_gpio_direction_output,
|
||||
.gpio_ops_get_direction = &xil_gpio_get_direction,
|
||||
.gpio_ops_set_value = &xil_gpio_set_value,
|
||||
.gpio_ops_get_value = &xil_gpio_get_value,
|
||||
};
|
||||
+384
@@ -0,0 +1,384 @@
|
||||
/***************************************************************************//**
|
||||
* @file xilinx/xilinx_irq.c
|
||||
* @brief Implementation of Xilinx IRQ Generic Driver.
|
||||
* @author Cristian Pop ([email protected])
|
||||
********************************************************************************
|
||||
* Copyright 2019(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
|
||||
#include <xparameters.h>
|
||||
#include <stdlib.h>
|
||||
#include "irq_extra.h"
|
||||
#include "../../include/irq.h"
|
||||
#include "../../include/error.h"
|
||||
#ifdef XPAR_XSCUGIC_NUM_INSTANCES
|
||||
#include <xscugic.h>
|
||||
#endif
|
||||
#ifdef XPAR_XINTC_NUM_INSTANCES
|
||||
#include <xintc.h>
|
||||
#endif
|
||||
#ifdef XPAR_XTMRCTR_NUM_INSTANCES
|
||||
#include <xtmrctr.h>
|
||||
#endif
|
||||
|
||||
/******************************************************************************/
|
||||
/************************ Functions Definitions *******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief Initialize the IRQ interrupts.
|
||||
* @param desc - The IRQ controller descriptor.
|
||||
* @param param - The structure that contains the IRQ parameters.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t xil_irq_ctrl_init(struct irq_ctrl_desc **desc,
|
||||
const struct irq_init_param *param)
|
||||
{
|
||||
int32_t status;
|
||||
struct irq_ctrl_desc *descriptor;
|
||||
struct xil_irq_desc *xil_dev;
|
||||
#ifdef XSCUGIC_H
|
||||
void *config;
|
||||
#endif
|
||||
|
||||
descriptor = (struct irq_ctrl_desc *)calloc(1, sizeof *descriptor);
|
||||
if(!descriptor)
|
||||
return FAILURE;
|
||||
xil_dev = (struct xil_irq_desc *)calloc(1, sizeof *xil_dev);
|
||||
if(!xil_dev) {
|
||||
free(descriptor);
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
Xil_ExceptionInit();
|
||||
|
||||
descriptor->irq_ctrl_id = param->irq_ctrl_id;
|
||||
descriptor->extra = xil_dev;
|
||||
xil_dev->type = ((struct xil_irq_init_param *)param->extra)->type;
|
||||
|
||||
switch(xil_dev->type) {
|
||||
case IRQ_PS:
|
||||
#ifdef XSCUGIC_H
|
||||
xil_dev->instance = calloc(1, sizeof(XScuGic));
|
||||
if(!xil_dev->instance)
|
||||
goto error;
|
||||
|
||||
config = XScuGic_LookupConfig(descriptor->irq_ctrl_id);
|
||||
if(!config)
|
||||
goto ps_error;
|
||||
|
||||
status = XScuGic_CfgInitialize(xil_dev->instance, config,
|
||||
((XScuGic_Config *)config)->CpuBaseAddress);
|
||||
if (status != SUCCESS)
|
||||
goto ps_error;
|
||||
|
||||
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
|
||||
(Xil_ExceptionHandler)XScuGic_InterruptHandler,
|
||||
xil_dev->instance);
|
||||
|
||||
break;
|
||||
ps_error:
|
||||
free(xil_dev->instance);
|
||||
#endif
|
||||
goto error;
|
||||
case IRQ_PL:
|
||||
#ifdef XINTC_H
|
||||
xil_dev->instance = calloc(1, sizeof(XIntc));
|
||||
if(!xil_dev->instance)
|
||||
goto error;
|
||||
|
||||
status = XIntc_Initialize(xil_dev->instance, descriptor->irq_ctrl_id);
|
||||
if(status != SUCCESS)
|
||||
goto pl_error;
|
||||
|
||||
status = XIntc_Start(xil_dev->instance, XIN_REAL_MODE);
|
||||
if(status != SUCCESS)
|
||||
goto pl_error;
|
||||
|
||||
break;
|
||||
pl_error:
|
||||
free(xil_dev->instance);
|
||||
#endif
|
||||
goto error;
|
||||
default:
|
||||
goto error;
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
*desc = descriptor;
|
||||
|
||||
return SUCCESS;
|
||||
|
||||
error:
|
||||
free(xil_dev);
|
||||
free(descriptor);
|
||||
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable global interrupts.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t xil_irq_global_enable(struct irq_ctrl_desc *desc)
|
||||
{
|
||||
/* Enable interrupts */
|
||||
Xil_ExceptionEnable();
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable global interrupts.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t xil_irq_global_disable(struct irq_ctrl_desc *desc)
|
||||
{
|
||||
/* Disable interrupts */
|
||||
Xil_ExceptionDisable();
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable specific interrupt.
|
||||
* @param desc - The IRQ controller descriptor.
|
||||
* @param irq_id - Interrupt identifier.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t xil_irq_enable(struct irq_ctrl_desc *desc, uint32_t irq_id)
|
||||
{
|
||||
struct xil_irq_desc *xil_dev = desc->extra;
|
||||
|
||||
switch(xil_dev->type) {
|
||||
case IRQ_PS:
|
||||
#ifdef XSCUGIC_H
|
||||
XScuGic_Enable(xil_dev->instance, irq_id);
|
||||
#endif
|
||||
break;
|
||||
case IRQ_PL:
|
||||
#ifdef XINTC_H
|
||||
XIntc_Enable(xil_dev->instance, irq_id);
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable specific interrupt.
|
||||
* @param desc - The IRQ controller descriptor.
|
||||
* @param irq_id - Interrupt identifier.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t xil_irq_disable(struct irq_ctrl_desc *desc, uint32_t irq_id)
|
||||
{
|
||||
struct xil_irq_desc *xil_dev = desc->extra;
|
||||
|
||||
switch(xil_dev->type) {
|
||||
case IRQ_PS:
|
||||
#ifdef XSCUGIC_H
|
||||
XScuGic_Disable(xil_dev->instance, irq_id);
|
||||
#endif
|
||||
break;
|
||||
case IRQ_PL:
|
||||
#ifdef XINTC_H
|
||||
XIntc_Disable(xil_dev->instance, irq_id);
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Register a callback to handle the irq events.
|
||||
* @param desc - The IRQ controller descriptor.
|
||||
* @param irq_id - Interrupt identifier.
|
||||
* @param callback_desc - Callback descriptor
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t xil_irq_register_callback(struct irq_ctrl_desc *desc, uint32_t irq_id,
|
||||
struct callback_desc *callback_desc)
|
||||
{
|
||||
struct xil_irq_desc *xil_dev = desc->extra;
|
||||
|
||||
switch(xil_dev->type) {
|
||||
case IRQ_PS:
|
||||
#ifdef XSCUGIC_H
|
||||
return XScuGic_Connect(xil_dev->instance, irq_id,
|
||||
(Xil_InterruptHandler) callback_desc->callback,
|
||||
callback_desc->ctx);
|
||||
#endif
|
||||
break;
|
||||
case IRQ_PL:
|
||||
#ifdef XINTC_H
|
||||
if (irq_id == XPAR_AXI_INTC_AXI_TIMER_INTERRUPT_INTR) {
|
||||
int32_t ret;
|
||||
|
||||
ret = XIntc_Connect(xil_dev->instance, irq_id,
|
||||
XTmrCtr_InterruptHandler, callback_desc->config);
|
||||
if (IS_ERR_VALUE(ret))
|
||||
return FAILURE;
|
||||
XTmrCtr_SetHandler(callback_desc->config,
|
||||
(XTmrCtr_Handler)callback_desc->callback,
|
||||
callback_desc->ctx);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
return XIntc_Connect(xil_dev->instance, irq_id,
|
||||
(XInterruptHandler) callback_desc->callback,
|
||||
callback_desc->ctx);
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set interrupt trigger level.
|
||||
* @param desc - The IRQ controller descriptor.
|
||||
* @param irq_id - Interrupt identifier.
|
||||
* @param trig - New trigger level for the interrupt.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t xil_irq_trigger_level_set(struct irq_ctrl_desc *desc, uint32_t irq_id,
|
||||
enum irq_trig_level trig)
|
||||
{
|
||||
struct xil_irq_desc *xil_dev = desc->extra;
|
||||
|
||||
if(trig == IRQ_EDGE_BOTH)
|
||||
return -EINVAL;
|
||||
|
||||
switch(xil_dev->type) {
|
||||
case IRQ_PS:
|
||||
#ifdef XSCUGIC_H
|
||||
;
|
||||
uint8_t priority, trigger;
|
||||
|
||||
XScuGic_GetPriorityTriggerType(xil_dev->instance, irq_id, &priority,
|
||||
&trigger);
|
||||
trigger = trig;
|
||||
XScuGic_SetPriorityTriggerType(xil_dev->instance, irq_id, priority,
|
||||
trigger);
|
||||
|
||||
return SUCCESS;
|
||||
#endif
|
||||
break;
|
||||
case IRQ_PL:
|
||||
#ifdef XINTC_H
|
||||
/* Interrupt trigger determined in hardware. TODO: verify */
|
||||
return SUCCESS;
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Unregisters a generic IRQ handling function.
|
||||
* @param desc - The IRQ controller descriptor.
|
||||
* @param irq_id - Interrupt identifier.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t xil_irq_unregister(struct irq_ctrl_desc *desc, uint32_t irq_id)
|
||||
{
|
||||
struct xil_irq_desc *xil_dev = desc->extra;
|
||||
|
||||
switch(xil_dev->type) {
|
||||
case IRQ_PS:
|
||||
#ifdef XSCUGIC_H
|
||||
XScuGic_Disconnect(xil_dev->instance, irq_id);
|
||||
#endif
|
||||
break;
|
||||
case IRQ_PL:
|
||||
#ifdef XINTC_H
|
||||
XIntc_Disconnect(xil_dev->instance, irq_id);
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Free the resources allocated by irq_ctrl_init().
|
||||
* @param desc - The IRQ control descriptor.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t xil_irq_ctrl_remove(struct irq_ctrl_desc *desc)
|
||||
{
|
||||
struct xil_irq_desc *xil_dev = desc->extra;
|
||||
free(xil_dev->instance);
|
||||
free(desc->extra);
|
||||
free(desc);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Xilinx platform specific IRQ platform ops structure
|
||||
*/
|
||||
const struct irq_platform_ops xil_irq_ops = {
|
||||
.init = &xil_irq_ctrl_init,
|
||||
.register_callback = &xil_irq_register_callback,
|
||||
.unregister = &xil_irq_unregister,
|
||||
.global_enable = &xil_irq_global_enable,
|
||||
.global_disable = &xil_irq_global_disable,
|
||||
.trigger_level_set = &xil_irq_trigger_level_set,
|
||||
.enable = &xil_irq_enable,
|
||||
.disable = &xil_irq_disable,
|
||||
.remove = &xil_irq_ctrl_remove
|
||||
};
|
||||
+461
@@ -0,0 +1,461 @@
|
||||
/***************************************************************************//**
|
||||
* @file xilinx/xilinx_spi.c
|
||||
* @brief Implementation of Xilinx SPI Generic Driver.
|
||||
* @author Antoniu Miclaus ([email protected])
|
||||
********************************************************************************
|
||||
* Copyright 2019(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
|
||||
#include <stdlib.h>
|
||||
|
||||
#include <xparameters.h>
|
||||
#ifdef XPAR_XSPI_NUM_INSTANCES
|
||||
#include <xspi.h>
|
||||
#endif
|
||||
#ifdef XPAR_XSPIPS_NUM_INSTANCES
|
||||
#include <xspips.h>
|
||||
#endif
|
||||
|
||||
#include "../../include/error.h"
|
||||
#include "../../include/spi.h"
|
||||
#include "spi_extra.h"
|
||||
|
||||
#if defined(PLATFORM_ZYNQ)
|
||||
#define SPI_CLK_FREQ_HZ(dev) (XPAR_PS7_SPI_ ## dev ## _SPI_CLK_FREQ_HZ)
|
||||
#define SPI_NUM_INSTANCES XPAR_XSPIPS_NUM_INSTANCES
|
||||
#elif defined(PLATFORM_ZYNQMP)
|
||||
#define SPI_CLK_FREQ_HZ(dev) (XPAR_PSU_SPI_ ## dev ## _SPI_CLK_FREQ_HZ)
|
||||
#define SPI_NUM_INSTANCES XPAR_XSPIPS_NUM_INSTANCES
|
||||
#else
|
||||
#define SPI_NUM_INSTANCES 0
|
||||
#endif
|
||||
|
||||
/******************************************************************************/
|
||||
/************************ Functions Definitions *******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief Initialize the hardware SPI peripherial
|
||||
*
|
||||
* @param xdesc Platform specific SPI descriptor
|
||||
* @param xinit Platform specific SPI init param
|
||||
* @return int32_t FAILURE if the device couldn't be found or configured
|
||||
*/
|
||||
static int32_t spi_init_pl(struct spi_desc *desc,
|
||||
const struct spi_init_param *param)
|
||||
{
|
||||
#ifdef XSPI_H
|
||||
int32_t ret;
|
||||
struct xil_spi_desc *xdesc;
|
||||
struct xil_spi_init_param *xinit;
|
||||
|
||||
xdesc = (xil_spi_desc*)malloc(sizeof(xil_spi_desc));
|
||||
if(!xdesc) {
|
||||
free(xdesc);
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
desc->extra = xdesc;
|
||||
xinit = param->extra;
|
||||
xdesc->type = xinit->type;
|
||||
xdesc->flags = xinit->flags;
|
||||
|
||||
xdesc->instance = (XSpi*)calloc(1, sizeof(XSpi));
|
||||
if(!xdesc->instance)
|
||||
goto pl_error;
|
||||
|
||||
xdesc->config = XSpi_LookupConfig(param->device_id);
|
||||
if(xdesc->config == NULL)
|
||||
goto pl_error;
|
||||
|
||||
ret = XSpi_CfgInitialize(xdesc->instance,
|
||||
xdesc->config,
|
||||
((XSpi_Config*)xdesc->config)
|
||||
->BaseAddress);
|
||||
if(ret != SUCCESS)
|
||||
goto pl_error;
|
||||
|
||||
ret = XSpi_Initialize(xdesc->instance, param->device_id);
|
||||
if (ret != SUCCESS)
|
||||
goto pl_error;
|
||||
|
||||
ret = XSpi_SetOptions(xdesc->instance,
|
||||
XSP_MASTER_OPTION |
|
||||
((desc->mode & SPI_CPOL) ?
|
||||
XSP_CLK_ACTIVE_LOW_OPTION : 0) |
|
||||
((desc->mode & SPI_CPHA) ?
|
||||
XSP_CLK_PHASE_1_OPTION : 0));
|
||||
if (ret != SUCCESS)
|
||||
goto pl_error;
|
||||
|
||||
ret = XSpi_Start(xdesc->instance);
|
||||
if (ret != SUCCESS)
|
||||
goto pl_error;
|
||||
|
||||
XSpi_IntrGlobalDisable((XSpi *)(xdesc->instance));
|
||||
|
||||
return SUCCESS;
|
||||
|
||||
pl_error:
|
||||
free(xdesc->instance);
|
||||
free(xdesc);
|
||||
#endif
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the hardware SPI peripherial
|
||||
*
|
||||
* @param xdesc Platform specific SPI descriptor
|
||||
* @param xinit Platform specific SPI init param
|
||||
* @return int32_t FAILURE if the device couldn't be found or configured
|
||||
*/
|
||||
static int32_t spi_init_ps(struct spi_desc *desc,
|
||||
const struct spi_init_param *param)
|
||||
{
|
||||
#ifdef XSPIPS_H
|
||||
int32_t ret;
|
||||
struct xil_spi_desc *xdesc;
|
||||
struct xil_spi_init_param *xinit;
|
||||
const uint32_t prescaler_default = XSPIPS_CLK_PRESCALE_64;
|
||||
const uint32_t prescaler_min = XSPIPS_CLK_PRESCALE_4;
|
||||
const uint32_t prescaler_max = XSPIPS_CLK_PRESCALE_256;
|
||||
uint32_t prescaler = 0u;
|
||||
uint32_t input_clock = 0u;
|
||||
|
||||
xdesc = (xil_spi_desc*)malloc(sizeof(xil_spi_desc));
|
||||
if(!xdesc) {
|
||||
free(xdesc);
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
desc->extra = xdesc;
|
||||
xinit = param->extra;
|
||||
xdesc->type = xinit->type;
|
||||
xdesc->flags = xinit->flags;
|
||||
|
||||
xdesc->instance = (XSpiPs*)malloc(sizeof(XSpiPs));
|
||||
if(!xdesc->instance)
|
||||
goto ps_error;
|
||||
|
||||
xdesc->config = XSpiPs_LookupConfig(param->device_id);
|
||||
if(xdesc->config == NULL)
|
||||
goto ps_error;
|
||||
|
||||
ret = XSpiPs_CfgInitialize(xdesc->instance,
|
||||
xdesc->config,
|
||||
((XSpiPs_Config*)xdesc->config)
|
||||
->BaseAddress);
|
||||
if(ret != SUCCESS)
|
||||
goto ps_error;
|
||||
|
||||
switch (param->device_id) {
|
||||
#if (SPI_NUM_INSTANCES >= 1)
|
||||
case 0:
|
||||
input_clock = SPI_CLK_FREQ_HZ(0);
|
||||
break;
|
||||
#endif
|
||||
#if (SPI_NUM_INSTANCES >= 2)
|
||||
case 1:
|
||||
input_clock = SPI_CLK_FREQ_HZ(1);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
goto ps_error;
|
||||
};
|
||||
|
||||
if (desc->max_speed_hz != 0u) {
|
||||
uint32_t div = input_clock / desc->max_speed_hz;
|
||||
uint32_t rem = input_clock % desc->max_speed_hz;
|
||||
uint32_t po2 = !(div & (div - 1)) && !rem;
|
||||
|
||||
// find the power of two just higher than div and
|
||||
// store the exponent in prescaler
|
||||
while(div) {
|
||||
prescaler += 1;
|
||||
div >>= 1u;
|
||||
}
|
||||
|
||||
// this exponent - 1 is needed because of the way
|
||||
// xilinx stores it into registers
|
||||
if (prescaler)
|
||||
prescaler -= 1;
|
||||
|
||||
// this exponent - 1 is needed when initial div was
|
||||
// precisely a power of two
|
||||
if (prescaler && po2)
|
||||
prescaler -= 1;
|
||||
|
||||
if (prescaler < prescaler_min)
|
||||
prescaler = prescaler_min;
|
||||
|
||||
if (prescaler > prescaler_max)
|
||||
prescaler = prescaler_max;
|
||||
} else
|
||||
prescaler = prescaler_default;
|
||||
|
||||
ret = XSpiPs_SetClkPrescaler(xdesc->instance, prescaler);
|
||||
|
||||
if(ret != SUCCESS)
|
||||
goto ps_error;
|
||||
|
||||
return SUCCESS;
|
||||
|
||||
ps_error:
|
||||
free(xdesc->instance);
|
||||
free(xdesc);
|
||||
#endif
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the SPI communication peripheral.
|
||||
* @param desc - The SPI descriptor.
|
||||
* @param param - The structure that contains the SPI parameters.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t xil_spi_init(struct spi_desc **desc,
|
||||
const struct spi_init_param *param)
|
||||
{
|
||||
int32_t ret;
|
||||
enum xil_spi_type *spi_type;
|
||||
|
||||
if (!param) {
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
*desc = malloc(sizeof(**desc));
|
||||
if(! *desc) {
|
||||
free(*desc);
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
spi_type = param->extra;
|
||||
|
||||
if(!spi_type)
|
||||
goto init_error;
|
||||
|
||||
(*desc)->max_speed_hz = param->max_speed_hz;
|
||||
(*desc)->mode = param->mode;
|
||||
(*desc)->bit_order = param->bit_order;
|
||||
(*desc)->chip_select = param->chip_select;
|
||||
|
||||
switch (*spi_type) {
|
||||
case SPI_PL:
|
||||
ret = spi_init_pl(*desc, param);
|
||||
break;
|
||||
case SPI_PS:
|
||||
ret = spi_init_ps(*desc, param);
|
||||
break;
|
||||
|
||||
default:
|
||||
goto init_error;
|
||||
break;
|
||||
}
|
||||
|
||||
if (ret != SUCCESS) {
|
||||
init_error:
|
||||
free(*desc);
|
||||
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Free the resources allocated by spi_init().
|
||||
* @param desc - The SPI descriptor.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t xil_spi_remove(struct spi_desc *desc)
|
||||
{
|
||||
#ifdef XSPI_H
|
||||
int32_t ret;
|
||||
#endif
|
||||
struct xil_spi_desc *xdesc = NULL;
|
||||
enum xil_spi_type *spi_type;
|
||||
|
||||
spi_type = desc->extra;
|
||||
|
||||
if(!spi_type)
|
||||
return FAILURE;
|
||||
|
||||
switch (*spi_type ) {
|
||||
case SPI_PL:
|
||||
#ifdef XSPI_H
|
||||
xdesc = desc->extra;
|
||||
|
||||
if(!xdesc)
|
||||
return FAILURE;
|
||||
|
||||
ret = XSpi_Stop((XSpi *)(xdesc->instance));
|
||||
if(ret != SUCCESS)
|
||||
goto error;
|
||||
#endif
|
||||
break;
|
||||
case SPI_PS:
|
||||
#ifdef XSPIPS_H
|
||||
xdesc = desc->extra;
|
||||
|
||||
if(!xdesc)
|
||||
return FAILURE;
|
||||
#endif
|
||||
break;
|
||||
|
||||
/* Intended fallthrough */
|
||||
#ifdef XSPI_H
|
||||
error:
|
||||
#endif
|
||||
default:
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
if(xdesc)
|
||||
free(xdesc->instance);
|
||||
free(desc->extra);
|
||||
free(desc);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write and read data to/from SPI.
|
||||
* @param desc - The SPI descriptor.
|
||||
* @param data - The buffer with the transmitted/received data.
|
||||
* @param bytes_number - Number of bytes to write/read.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t xil_spi_write_and_read(struct spi_desc *desc,
|
||||
uint8_t *data,
|
||||
uint16_t bytes_number)
|
||||
{
|
||||
int32_t ret;
|
||||
#ifdef XSPI_H
|
||||
uint32_t ctrl_reg;
|
||||
#endif
|
||||
struct xil_spi_desc *xdesc;
|
||||
enum xil_spi_type *spi_type;
|
||||
|
||||
ret = FAILURE;
|
||||
|
||||
spi_type = desc->extra;
|
||||
|
||||
if(!spi_type)
|
||||
return FAILURE;
|
||||
|
||||
xdesc = desc->extra;
|
||||
|
||||
switch (*spi_type) {
|
||||
case SPI_PL:
|
||||
#ifdef XSPI_H
|
||||
ret = XSpi_SetOptions(xdesc->instance,
|
||||
XSP_MASTER_OPTION |
|
||||
((desc->mode & SPI_CPOL) ?
|
||||
XSP_CLK_ACTIVE_LOW_OPTION : 0) |
|
||||
((desc->mode & SPI_CPHA) ?
|
||||
XSP_CLK_PHASE_1_OPTION : 0));
|
||||
if (ret != SUCCESS)
|
||||
goto error;
|
||||
|
||||
ctrl_reg = XSpi_GetControlReg(((XSpi*)xdesc->instance));
|
||||
if (desc->bit_order == SPI_BIT_ORDER_LSB_FIRST)
|
||||
ctrl_reg |= XSP_CR_LSB_MSB_FIRST_MASK;
|
||||
else
|
||||
ctrl_reg &= ~ XSP_CR_LSB_MSB_FIRST_MASK;
|
||||
XSpi_SetControlReg(((XSpi*)xdesc->instance), ctrl_reg);
|
||||
|
||||
ret = XSpi_SetSlaveSelect(xdesc->instance,
|
||||
0x01 << desc->chip_select);
|
||||
if (ret != SUCCESS)
|
||||
goto error;
|
||||
|
||||
ret = XSpi_Transfer(xdesc->instance,
|
||||
data,
|
||||
data,
|
||||
bytes_number);
|
||||
if (ret != SUCCESS)
|
||||
goto error;
|
||||
#endif
|
||||
break;
|
||||
case SPI_PS:
|
||||
#ifdef XSPIPS_H
|
||||
ret = XSpiPs_SetOptions(xdesc->instance,
|
||||
XSPIPS_MASTER_OPTION |
|
||||
((xdesc->flags & SPI_CS_DECODE) ?
|
||||
XSPIPS_DECODE_SSELECT_OPTION : 0) |
|
||||
XSPIPS_FORCE_SSELECT_OPTION |
|
||||
((desc->mode & SPI_CPOL) ?
|
||||
XSPIPS_CLK_ACTIVE_LOW_OPTION : 0) |
|
||||
((desc->mode & SPI_CPHA) ?
|
||||
XSPIPS_CLK_PHASE_1_OPTION : 0));
|
||||
if (ret != SUCCESS)
|
||||
goto error;
|
||||
|
||||
ret = XSpiPs_SetSlaveSelect(xdesc->instance,
|
||||
desc->chip_select);
|
||||
if (ret != SUCCESS)
|
||||
goto error;
|
||||
ret = XSpiPs_PolledTransfer(xdesc->instance,
|
||||
data,
|
||||
data,
|
||||
bytes_number);
|
||||
if (ret != SUCCESS)
|
||||
goto error;
|
||||
ret = XSpiPs_SetSlaveSelect(xdesc->instance, SPI_DEASSERT_CURRENT_SS);
|
||||
if (ret != SUCCESS)
|
||||
goto error;
|
||||
#endif
|
||||
break;
|
||||
error:
|
||||
default:
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Xilinx platform specific SPI platform ops structure
|
||||
*/
|
||||
const struct spi_platform_ops xil_spi_ops = {
|
||||
.init = &xil_spi_init,
|
||||
.write_and_read = &xil_spi_write_and_read,
|
||||
.write_and_read_3wire = NULL, // Not support.
|
||||
.remove = &xil_spi_remove
|
||||
};
|
||||
+531
@@ -0,0 +1,531 @@
|
||||
/*******************************************************************************
|
||||
* @file xilinx/xilinx_spi_pl.c
|
||||
* @brief Driver for spi pl device using registers
|
||||
* @author Mihail Chindris ([email protected])
|
||||
********************************************************************************
|
||||
* Copyright 2021(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
#include <xparameters.h>
|
||||
|
||||
#ifdef XPAR_XSPI_NUM_INSTANCES
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
|
||||
#include <xspi.h>
|
||||
#include <stdlib.h>
|
||||
#include <stdbool.h>
|
||||
#include "spi.h"
|
||||
#include "error.h"
|
||||
#include "delay.h"
|
||||
#include "util.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/********************** Macros and Constants Definitions **********************/
|
||||
/******************************************************************************/
|
||||
|
||||
#define XPS_TYPE_WRITE 0x1
|
||||
#define XPS_TYPE_READ 0x2
|
||||
#define XSP_DEFAULT_SR_VALUE 0x25
|
||||
#define XSP_DUMMY_DATA 0xFF
|
||||
|
||||
/*
|
||||
* Used to store current spi device configuration in order to not update it for
|
||||
* each spi transaction if not needed.
|
||||
*/
|
||||
static struct spi_desc g_spi_desc[XPAR_XSPI_NUM_INSTANCES];
|
||||
|
||||
/******************************************************************************/
|
||||
/*************************** Types Declarations *******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/* Xilinx PL spi specific data */
|
||||
struct xspi_desc {
|
||||
uint32_t base_addr;
|
||||
uint32_t disable_slaves_mask;
|
||||
uint32_t fifo_depth;
|
||||
uint8_t cs_asserted;
|
||||
};
|
||||
|
||||
/* Structure used to iterate over SPI messages */
|
||||
struct msg_iter {
|
||||
struct spi_msg *msgs;
|
||||
uint32_t len;
|
||||
uint32_t i;
|
||||
uint32_t buff_i;
|
||||
uint8_t is_wr;
|
||||
};
|
||||
|
||||
/******************************************************************************/
|
||||
/************************ Functions Definitions *******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/* Read device register */
|
||||
static inline uint32_t _read(struct xspi_desc *xdesc, uint32_t reg)
|
||||
{
|
||||
return Xil_In32(xdesc->base_addr + reg);
|
||||
}
|
||||
|
||||
/* Write device register */
|
||||
static inline void _write(struct xspi_desc *xdesc, uint32_t reg, uint32_t val)
|
||||
{
|
||||
Xil_Out32(xdesc->base_addr + reg, val);
|
||||
}
|
||||
|
||||
/* Update device register. Only bits set to 1 in mask will be modified */
|
||||
static inline void _wr_mask(struct xspi_desc *xdesc, uint32_t reg,
|
||||
uint32_t val, uint32_t mask)
|
||||
{
|
||||
uint32_t tmp;
|
||||
|
||||
tmp = _read(xdesc, reg);
|
||||
tmp &= ~mask;
|
||||
tmp |= val & mask;
|
||||
_write(xdesc, reg, tmp);
|
||||
}
|
||||
|
||||
/* Update spi device configuration if needed */
|
||||
static void _update_mode(struct spi_desc *desc)
|
||||
{
|
||||
uint32_t val;
|
||||
uint32_t mask;
|
||||
|
||||
if (desc->mode == g_spi_desc[desc->device_id].mode &&
|
||||
desc->bit_order == g_spi_desc[desc->device_id].bit_order)
|
||||
return ;
|
||||
|
||||
/* Update mode */
|
||||
val = desc->mode | SPI_CPOL ? XSP_CR_CLK_POLARITY_MASK : 0;
|
||||
val |= desc->mode | SPI_CPHA ? XSP_CR_CLK_PHASE_MASK : 0;
|
||||
mask = XSP_CR_CLK_POLARITY_MASK | XSP_CR_CLK_PHASE_MASK;
|
||||
|
||||
val |= desc->bit_order == SPI_BIT_ORDER_LSB_FIRST ?
|
||||
XSP_CR_LSB_MSB_FIRST_MASK : 0;
|
||||
mask |= XSP_CR_LSB_MSB_FIRST_MASK;
|
||||
|
||||
_wr_mask(desc->extra, XSP_CR_OFFSET, val, mask);
|
||||
g_spi_desc[desc->device_id] = *desc;
|
||||
}
|
||||
|
||||
/* Configure SPI PL device */
|
||||
static int32_t _xil_spi_init_dev(struct xspi_desc *xdesc)
|
||||
{
|
||||
uint32_t val;
|
||||
|
||||
/* Software reset */
|
||||
_write(xdesc, XSP_SRR_OFFSET, XSP_SRR_RESET_MASK);
|
||||
mdelay(1);
|
||||
|
||||
/* Check if success reset */
|
||||
val = _read(xdesc, XSP_SR_OFFSET);
|
||||
if (val != XSP_DEFAULT_SR_VALUE)
|
||||
return -ENODEV;
|
||||
|
||||
/* Disable interrupts. Drivers only works with pooled mode */
|
||||
_write(xdesc, XSP_IIER_OFFSET, 0);
|
||||
|
||||
/* Deasert chip selects */
|
||||
_write(xdesc, XSP_SSR_OFFSET, 0xFFFFFFFF);
|
||||
|
||||
/* Get fifo depth */
|
||||
while (!(_read(xdesc, XSP_SR_OFFSET) & XSP_SR_TX_FULL_MASK))
|
||||
_write(xdesc, XSP_DTR_OFFSET, XSP_DUMMY_DATA);
|
||||
xdesc->fifo_depth = _read(xdesc, XSP_TFO_OFFSET) + 1;
|
||||
|
||||
/* Configure spi device */
|
||||
val = XSP_CR_ENABLE_MASK |
|
||||
XSP_CR_MANUAL_SS_MASK |
|
||||
XSP_CR_TXFIFO_RESET_MASK |
|
||||
XSP_CR_RXFIFO_RESET_MASK |
|
||||
XSP_CR_MASTER_MODE_MASK |
|
||||
XSP_CR_TRANS_INHIBIT_MASK;
|
||||
|
||||
_write(xdesc, XSP_CR_OFFSET, val);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/* Initialize spi_desc structure and device */
|
||||
static int32_t xil_spi_init_pl(struct spi_desc **desc,
|
||||
const struct spi_init_param *param)
|
||||
{
|
||||
struct spi_desc *ldesc;
|
||||
struct xspi_desc *xdesc;
|
||||
int32_t err;
|
||||
XSpi_Config *cfg;
|
||||
|
||||
if (!desc || !param || param->device_id >= XPAR_XSPI_NUM_INSTANCES)
|
||||
return -EINVAL;
|
||||
|
||||
cfg = XSpi_LookupConfig(param->device_id);
|
||||
if (!cfg)
|
||||
return -EINVAL;
|
||||
|
||||
if (param->chip_select > cfg->NumSlaveBits)
|
||||
return -EINVAL;
|
||||
|
||||
ldesc = (struct spi_desc *)calloc(1, sizeof(*ldesc));
|
||||
if (!ldesc)
|
||||
return -ENOMEM;
|
||||
|
||||
xdesc = (struct xspi_desc *)calloc(1, sizeof(*xdesc));
|
||||
if (!xdesc) {
|
||||
err = -ENOMEM;
|
||||
goto error;
|
||||
}
|
||||
|
||||
ldesc->bit_order = param->bit_order;
|
||||
ldesc->chip_select = param->chip_select;
|
||||
ldesc->mode = param->mode;
|
||||
xdesc->base_addr = cfg->BaseAddress;
|
||||
xdesc->disable_slaves_mask = (1 << cfg->NumSlaveBits) - 1;
|
||||
xdesc->cs_asserted = 0;
|
||||
|
||||
err = _xil_spi_init_dev(xdesc);
|
||||
if (IS_ERR_VALUE(err))
|
||||
goto error;
|
||||
|
||||
ldesc->extra = xdesc;
|
||||
*desc = ldesc;
|
||||
|
||||
return SUCCESS;
|
||||
|
||||
error:
|
||||
free(xdesc);
|
||||
free(ldesc);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
/* Remove allocated resources */
|
||||
static int32_t xil_spi_remove_pl(struct spi_desc *desc)
|
||||
{
|
||||
if (!desc)
|
||||
return -EINVAL;
|
||||
|
||||
free(desc->extra);
|
||||
free(desc);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/*
|
||||
* Fill fifo until fifo is full or no more data available.
|
||||
* Return the number of written bytes.
|
||||
*/
|
||||
static uint32_t _wr_fifo(struct xspi_desc *xdesc, uint8_t *data,
|
||||
uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
uint32_t to_write;
|
||||
uint32_t tx_available;
|
||||
|
||||
tx_available = xdesc->fifo_depth - _read(xdesc, XSP_TFO_OFFSET);
|
||||
to_write = min(tx_available, len);
|
||||
for (i = 0; i < to_write; ++i)
|
||||
if (data)
|
||||
_write(xdesc, XSP_DTR_OFFSET, data[i]);
|
||||
else
|
||||
_write(xdesc, XSP_DTR_OFFSET, XSP_DUMMY_DATA);
|
||||
|
||||
return to_write;
|
||||
}
|
||||
|
||||
/*
|
||||
* Read fifo until fifo is empty or no more buffer available to read into
|
||||
* Returns the number of read bytes
|
||||
*/
|
||||
static uint32_t _rd_fifo(struct xspi_desc *xdesc, uint8_t *data,
|
||||
uint32_t len)
|
||||
{
|
||||
uint32_t rx_available;
|
||||
uint32_t to_read;
|
||||
uint32_t tmp;
|
||||
uint32_t i;
|
||||
|
||||
tmp = _read(xdesc, XSP_SR_OFFSET);
|
||||
if (tmp & XSP_SR_RX_EMPTY_MASK)
|
||||
return 0;
|
||||
|
||||
rx_available = _read(xdesc, XSP_RFO_OFFSET) + 1;
|
||||
to_read = min(rx_available, len);
|
||||
for (i = 0; i < to_read; ++i) {
|
||||
tmp = _read(xdesc, XSP_DRR_OFFSET);
|
||||
if (data)
|
||||
data[i] = tmp;
|
||||
}
|
||||
|
||||
return to_read;
|
||||
}
|
||||
|
||||
/* If start is 0 stop transfer, else start it.
|
||||
* CS will be asserted if needed. If different CS othere than the one needed
|
||||
* is asserted. Deassert it and assert correct one */
|
||||
static void _xil_spi_start_transfer(struct spi_desc *desc, uint8_t start)
|
||||
{
|
||||
struct xspi_desc *xdesc;
|
||||
|
||||
xdesc = desc->extra;
|
||||
if (start) {
|
||||
if (xdesc->cs_asserted) {
|
||||
if (desc->chip_select ==
|
||||
g_spi_desc[desc->device_id].chip_select)
|
||||
return ;
|
||||
else
|
||||
/* Stop transfer to start again with new CS */
|
||||
_xil_spi_start_transfer(desc, 0);
|
||||
}
|
||||
_write(xdesc, XSP_SSR_OFFSET, ~(1 << desc->chip_select));
|
||||
_wr_mask(xdesc, XSP_CR_OFFSET, 0, XSP_CR_TRANS_INHIBIT_MASK);
|
||||
} else {
|
||||
_wr_mask(xdesc, XSP_CR_OFFSET, XSP_CR_TRANS_INHIBIT_MASK,
|
||||
XSP_CR_TRANS_INHIBIT_MASK);
|
||||
_write(xdesc, XSP_SSR_OFFSET, xdesc->disable_slaves_mask);
|
||||
}
|
||||
xdesc->cs_asserted = start;
|
||||
}
|
||||
|
||||
|
||||
/* SPI polled transfer */
|
||||
static int32_t xil_spi_write_and_read_pl(struct spi_desc *desc, uint8_t *data,
|
||||
uint16_t bytes_number)
|
||||
{
|
||||
struct xspi_desc *xdesc;
|
||||
uint32_t rx;
|
||||
uint32_t tx;
|
||||
|
||||
if (!desc || !desc->extra)
|
||||
return -EINVAL;
|
||||
|
||||
xdesc = desc->extra;
|
||||
_update_mode(desc);
|
||||
|
||||
_xil_spi_start_transfer(desc, 1);
|
||||
rx = 0;
|
||||
tx = 0;
|
||||
while (rx < bytes_number) {
|
||||
if (tx < bytes_number)
|
||||
tx += _wr_fifo(xdesc, data + tx, bytes_number - tx);
|
||||
rx += _rd_fifo(xdesc, data + rx, bytes_number - rx);
|
||||
}
|
||||
_xil_spi_start_transfer(desc, 0);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/* Get type of message. It can be READ, WRITE or both */
|
||||
static uint32_t _get_msg_type(struct spi_msg *msg)
|
||||
{
|
||||
uint32_t type;
|
||||
|
||||
type = 0;
|
||||
if (msg->tx_buff)
|
||||
type |= XPS_TYPE_WRITE;
|
||||
if (msg->rx_buff)
|
||||
type |= XPS_TYPE_READ;
|
||||
|
||||
return type;
|
||||
}
|
||||
|
||||
/* Get information based on current iterator position */
|
||||
static void _get_data(struct msg_iter *it, uint8_t **buff, uint32_t *len,
|
||||
uint32_t *type)
|
||||
{
|
||||
struct spi_msg *msg;
|
||||
|
||||
if (it->i == it->len) {
|
||||
*len = 0;
|
||||
return ;
|
||||
}
|
||||
|
||||
msg = it->msgs + it->i;
|
||||
if (it->is_wr)
|
||||
*buff = msg->tx_buff;
|
||||
else
|
||||
*buff = msg->rx_buff;
|
||||
|
||||
if (*buff)
|
||||
*buff += it->buff_i;
|
||||
|
||||
*len = msg->bytes_number - it->buff_i;
|
||||
if (type)
|
||||
*type = _get_msg_type(msg);
|
||||
}
|
||||
|
||||
/*
|
||||
* Increment iterator position with desired length.
|
||||
* If the new position has a different message type, new_type will be set to 1
|
||||
* If a CS change is needed, cs_change is set
|
||||
*/
|
||||
static void _increment_iter(struct msg_iter *it, uint32_t len,
|
||||
uint8_t *cs_change, uint8_t *new_type)
|
||||
{
|
||||
struct spi_msg *msg;
|
||||
uint32_t type;
|
||||
uint32_t extra_len;
|
||||
|
||||
if (!len)
|
||||
return ;
|
||||
|
||||
*cs_change = 0;
|
||||
*new_type = 0;
|
||||
msg = it->msgs + it->i;
|
||||
if (it->buff_i + len > msg->bytes_number)
|
||||
extra_len = it->buff_i + len - msg->bytes_number;
|
||||
else
|
||||
extra_len = 0;
|
||||
len -= extra_len;
|
||||
it->buff_i += len;
|
||||
if (it->buff_i == msg->bytes_number) {
|
||||
type = _get_msg_type(msg);
|
||||
++it->i;
|
||||
it->buff_i = 0;
|
||||
if (cs_change && msg->cs_change)
|
||||
*cs_change = 1;
|
||||
if (new_type)
|
||||
if (it->i == it->len ||
|
||||
type != _get_msg_type(it->msgs + it->i))
|
||||
*new_type = 1;
|
||||
}
|
||||
if (extra_len)
|
||||
_increment_iter(it, extra_len, cs_change, new_type);
|
||||
}
|
||||
|
||||
/*
|
||||
* SPI polling transfer of multiple messages.
|
||||
*/
|
||||
static int32_t xil_spi_transfer_pl(struct spi_desc *desc, struct spi_msg *msgs,
|
||||
uint32_t len)
|
||||
|
||||
{
|
||||
struct xspi_desc *xdesc;
|
||||
uint8_t cs_change;
|
||||
uint8_t new_type;
|
||||
struct msg_iter rx = {.msgs = msgs, .len = len, .is_wr = 0};
|
||||
struct msg_iter tx = {.msgs = msgs, .len = len, .is_wr = 1};
|
||||
uint8_t *buff;
|
||||
uint32_t bytes;
|
||||
uint32_t type;
|
||||
/* Bytes to increment rx when only a write transaction is executed */
|
||||
uint32_t to_inc_rx;
|
||||
/* Difference between rx and tx iterators in bytes */
|
||||
uint32_t tx_advance;
|
||||
/* Save bytes sent during a write loop */
|
||||
uint32_t tx_sent;
|
||||
/* Used to loop if need to empty the RX FIFO */
|
||||
uint32_t loop;
|
||||
|
||||
if (!desc || !desc->extra)
|
||||
return -EINVAL;
|
||||
|
||||
xdesc = desc->extra;
|
||||
_update_mode(desc);
|
||||
|
||||
tx_advance = 0;
|
||||
to_inc_rx = 0;
|
||||
buff = NULL;
|
||||
type = 0;
|
||||
do {
|
||||
_xil_spi_start_transfer(desc, 1);
|
||||
|
||||
tx_sent = 0;
|
||||
/* Writing loop */
|
||||
do {
|
||||
_get_data(&tx, &buff, &bytes, &type);
|
||||
if (type & XPS_TYPE_READ)
|
||||
/*
|
||||
* Do not write more bytes than fifo_depth if
|
||||
* they haven't been read.
|
||||
*/
|
||||
bytes = min(bytes,
|
||||
xdesc->fifo_depth - tx_advance);
|
||||
bytes = _wr_fifo(xdesc, buff, bytes);
|
||||
tx_sent += bytes;
|
||||
_increment_iter(&tx, bytes, &cs_change, &new_type);
|
||||
tx_advance += bytes;
|
||||
} while (!cs_change && !new_type && bytes);
|
||||
|
||||
if (type & XPS_TYPE_READ) {
|
||||
loop = 1;
|
||||
/*
|
||||
* Loop only when no more data to write otherwise read
|
||||
* only available data.
|
||||
*/
|
||||
while (loop) {
|
||||
if (!new_type)
|
||||
loop = 0;
|
||||
_get_data(&rx, &buff, &bytes, NULL);
|
||||
bytes = _rd_fifo(xdesc, buff, bytes);
|
||||
_increment_iter(&rx, bytes, &cs_change, &new_type);
|
||||
tx_advance -= bytes;
|
||||
if (loop && new_type)
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
/* Clean RX FIFO if it was only a WRITE message */
|
||||
to_inc_rx += tx_sent;
|
||||
if (new_type) {
|
||||
/* Wait for TX to be sent */
|
||||
while (!(_read(xdesc, XSP_SR_OFFSET) &
|
||||
XSP_SR_TX_EMPTY_MASK))
|
||||
;
|
||||
/* Reset fifo. Only write was performed */
|
||||
_wr_mask(xdesc, XSP_CR_OFFSET,
|
||||
XSP_CR_RXFIFO_RESET_MASK,
|
||||
XSP_CR_RXFIFO_RESET_MASK);
|
||||
|
||||
_increment_iter(&rx, to_inc_rx, NULL, NULL);
|
||||
tx_advance -= to_inc_rx;
|
||||
to_inc_rx = 0;
|
||||
}
|
||||
}
|
||||
|
||||
if ((cs_change && rx.i != len) || (!cs_change && rx.i == len))
|
||||
_xil_spi_start_transfer(desc, 0);
|
||||
} while (rx.i < len);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
const struct spi_platform_ops xil_spi_reg_ops_pl = {
|
||||
.init = xil_spi_init_pl,
|
||||
.remove = xil_spi_remove_pl,
|
||||
.write_and_read = xil_spi_write_and_read_pl,
|
||||
.write_and_read_3wire = NULL, // Not support.
|
||||
.transfer = xil_spi_transfer_pl
|
||||
};
|
||||
|
||||
#endif // XPAR_XSPI_NUM_INSTANCES
|
||||
+7475
File diff suppressed because it is too large
Load Diff
+3568
File diff suppressed because it is too large
Load Diff
+2157
File diff suppressed because it is too large
Load Diff
+552
@@ -0,0 +1,552 @@
|
||||
/***************************************************************************//**
|
||||
* @file ad9361_api.h
|
||||
* @brief Header file of AD9361 API Driver.
|
||||
* @author DBogdan (dragos.bogdan@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2013(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
#ifndef AD9361_API_H_
|
||||
#define AD9361_API_H_
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
#include "ad9361_util.h"
|
||||
#include "../../../include/gpio.h"
|
||||
#include "../../../include/spi.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/*************************** Types Declarations *******************************/
|
||||
/******************************************************************************/
|
||||
typedef struct {
|
||||
/* Device selection */
|
||||
enum dev_id dev_sel;
|
||||
/* Reference Clock */
|
||||
uint32_t reference_clk_rate;
|
||||
/* Base Configuration */
|
||||
uint8_t two_rx_two_tx_mode_enable; /* adi,2rx-2tx-mode-enable */
|
||||
uint8_t one_rx_one_tx_mode_use_rx_num; /* adi,1rx-1tx-mode-use-rx-num */
|
||||
uint8_t one_rx_one_tx_mode_use_tx_num; /* adi,1rx-1tx-mode-use-tx-num */
|
||||
uint8_t frequency_division_duplex_mode_enable; /* adi,frequency-division-duplex-mode-enable */
|
||||
uint8_t frequency_division_duplex_independent_mode_enable; /* adi,frequency-division-duplex-independent-mode-enable */
|
||||
uint8_t tdd_use_dual_synth_mode_enable; /* adi,tdd-use-dual-synth-mode-enable */
|
||||
uint8_t tdd_skip_vco_cal_enable; /* adi,tdd-skip-vco-cal-enable */
|
||||
uint32_t tx_fastlock_delay_ns; /* adi,tx-fastlock-delay-ns */
|
||||
uint32_t rx_fastlock_delay_ns; /* adi,rx-fastlock-delay-ns */
|
||||
uint8_t rx_fastlock_pincontrol_enable; /* adi,rx-fastlock-pincontrol-enable */
|
||||
uint8_t tx_fastlock_pincontrol_enable; /* adi,tx-fastlock-pincontrol-enable */
|
||||
uint8_t external_rx_lo_enable; /* adi,external-rx-lo-enable */
|
||||
uint8_t external_tx_lo_enable; /* adi,external-tx-lo-enable */
|
||||
uint8_t dc_offset_tracking_update_event_mask; /* adi,dc-offset-tracking-update-event-mask */
|
||||
uint8_t dc_offset_attenuation_high_range; /* adi,dc-offset-attenuation-high-range */
|
||||
uint8_t dc_offset_attenuation_low_range; /* adi,dc-offset-attenuation-low-range */
|
||||
uint8_t dc_offset_count_high_range; /* adi,dc-offset-count-high-range */
|
||||
uint8_t dc_offset_count_low_range; /* adi,dc-offset-count-low-range */
|
||||
uint8_t split_gain_table_mode_enable; /* adi,split-gain-table-mode-enable */
|
||||
uint32_t trx_synthesizer_target_fref_overwrite_hz; /* adi,trx-synthesizer-target-fref-overwrite-hz */
|
||||
uint8_t qec_tracking_slow_mode_enable; /* adi,qec-tracking-slow-mode-enable */
|
||||
/* ENSM Control */
|
||||
uint8_t ensm_enable_pin_pulse_mode_enable; /* adi,ensm-enable-pin-pulse-mode-enable */
|
||||
uint8_t ensm_enable_txnrx_control_enable; /* adi,ensm-enable-txnrx-control-enable */
|
||||
/* LO Control */
|
||||
uint64_t rx_synthesizer_frequency_hz; /* adi,rx-synthesizer-frequency-hz */
|
||||
uint64_t tx_synthesizer_frequency_hz; /* adi,tx-synthesizer-frequency-hz */
|
||||
uint8_t tx_lo_powerdown_managed_enable; /* adi,tx-lo-powerdown-managed-enable */
|
||||
/* Rate & BW Control */
|
||||
uint32_t rx_path_clock_frequencies[6]; /* adi,rx-path-clock-frequencies */
|
||||
uint32_t tx_path_clock_frequencies[6]; /* adi,tx-path-clock-frequencies */
|
||||
uint32_t rf_rx_bandwidth_hz; /* adi,rf-rx-bandwidth-hz */
|
||||
uint32_t rf_tx_bandwidth_hz; /* adi,rf-tx-bandwidth-hz */
|
||||
/* RF Port Control */
|
||||
uint32_t rx_rf_port_input_select; /* adi,rx-rf-port-input-select */
|
||||
uint32_t tx_rf_port_input_select; /* adi,tx-rf-port-input-select */
|
||||
/* TX Attenuation Control */
|
||||
int32_t tx_attenuation_mdB; /* adi,tx-attenuation-mdB */
|
||||
uint8_t update_tx_gain_in_alert_enable; /* adi,update-tx-gain-in-alert-enable */
|
||||
/* Reference Clock Control */
|
||||
uint8_t xo_disable_use_ext_refclk_enable; /* adi,xo-disable-use-ext-refclk-enable */
|
||||
uint32_t dcxo_coarse_and_fine_tune[2]; /* adi,dcxo-coarse-and-fine-tune */
|
||||
uint32_t clk_output_mode_select; /* adi,clk-output-mode-select */
|
||||
/* Gain Control */
|
||||
uint8_t gc_rx1_mode; /* adi,gc-rx1-mode */
|
||||
uint8_t gc_rx2_mode; /* adi,gc-rx2-mode */
|
||||
uint8_t gc_adc_large_overload_thresh; /* adi,gc-adc-large-overload-thresh */
|
||||
uint8_t gc_adc_ovr_sample_size; /* adi,gc-adc-ovr-sample-size */
|
||||
uint8_t gc_adc_small_overload_thresh; /* adi,gc-adc-small-overload-thresh */
|
||||
uint16_t gc_dec_pow_measurement_duration; /* adi,gc-dec-pow-measurement-duration */
|
||||
uint8_t gc_dig_gain_enable; /* adi,gc-dig-gain-enable */
|
||||
uint16_t gc_lmt_overload_high_thresh; /* adi,gc-lmt-overload-high-thresh */
|
||||
uint16_t gc_lmt_overload_low_thresh; /* adi,gc-lmt-overload-low-thresh */
|
||||
uint8_t gc_low_power_thresh; /* adi,gc-low-power-thresh */
|
||||
uint8_t gc_max_dig_gain; /* adi,gc-max-dig-gain */
|
||||
uint8_t gc_use_rx_fir_out_for_dec_pwr_meas_enable; /* adi,gc-use-rx-fir-out-for-dec-pwr-meas-enable */
|
||||
/* Gain MGC Control */
|
||||
uint8_t mgc_dec_gain_step; /* adi,mgc-dec-gain-step */
|
||||
uint8_t mgc_inc_gain_step; /* adi,mgc-inc-gain-step */
|
||||
uint8_t mgc_rx1_ctrl_inp_enable; /* adi,mgc-rx1-ctrl-inp-enable */
|
||||
uint8_t mgc_rx2_ctrl_inp_enable; /* adi,mgc-rx2-ctrl-inp-enable */
|
||||
uint8_t mgc_split_table_ctrl_inp_gain_mode; /* adi,mgc-split-table-ctrl-inp-gain-mode */
|
||||
/* Gain AGC Control */
|
||||
uint8_t agc_adc_large_overload_exceed_counter; /* adi,agc-adc-large-overload-exceed-counter */
|
||||
uint8_t agc_adc_large_overload_inc_steps; /* adi,agc-adc-large-overload-inc-steps - Name is misleading should be dec-steps*/
|
||||
uint8_t agc_adc_lmt_small_overload_prevent_gain_inc_enable; /* adi,agc-adc-lmt-small-overload-prevent-gain-inc-enable */
|
||||
uint8_t agc_adc_small_overload_exceed_counter; /* adi,agc-adc-small-overload-exceed-counter */
|
||||
uint8_t agc_dig_gain_step_size; /* adi,agc-dig-gain-step-size */
|
||||
uint8_t agc_dig_saturation_exceed_counter; /* adi,agc-dig-saturation-exceed-counter */
|
||||
uint32_t agc_gain_update_interval_us; /* adi,agc-gain-update-interval-us */
|
||||
uint8_t agc_immed_gain_change_if_large_adc_overload_enable; /* adi,agc-immed-gain-change-if-large-adc-overload-enable */
|
||||
uint8_t agc_immed_gain_change_if_large_lmt_overload_enable; /* adi,agc-immed-gain-change-if-large-lmt-overload-enable */
|
||||
uint8_t agc_inner_thresh_high; /* adi,agc-inner-thresh-high */
|
||||
uint8_t agc_inner_thresh_high_dec_steps; /* adi,agc-inner-thresh-high-dec-steps */
|
||||
uint8_t agc_inner_thresh_low; /* adi,agc-inner-thresh-low */
|
||||
uint8_t agc_inner_thresh_low_inc_steps; /* adi,agc-inner-thresh-low-inc-steps */
|
||||
uint8_t agc_lmt_overload_large_exceed_counter; /* adi,agc-lmt-overload-large-exceed-counter */
|
||||
uint8_t agc_lmt_overload_large_inc_steps; /* adi,agc-lmt-overload-large-inc-steps */
|
||||
uint8_t agc_lmt_overload_small_exceed_counter; /* adi,agc-lmt-overload-small-exceed-counter */
|
||||
uint8_t agc_outer_thresh_high; /* adi,agc-outer-thresh-high */
|
||||
uint8_t agc_outer_thresh_high_dec_steps; /* adi,agc-outer-thresh-high-dec-steps */
|
||||
uint8_t agc_outer_thresh_low; /* adi,agc-outer-thresh-low */
|
||||
uint8_t agc_outer_thresh_low_inc_steps; /* adi,agc-outer-thresh-low-inc-steps */
|
||||
uint32_t agc_attack_delay_extra_margin_us; /* adi,agc-attack-delay-extra-margin-us */
|
||||
uint8_t agc_sync_for_gain_counter_enable; /* adi,agc-sync-for-gain-counter-enable */
|
||||
/* Fast AGC */
|
||||
uint32_t fagc_dec_pow_measuremnt_duration; /* adi,fagc-dec-pow-measurement-duration */
|
||||
uint32_t fagc_state_wait_time_ns; /* adi,fagc-state-wait-time-ns */
|
||||
/* Fast AGC - Low Power */
|
||||
uint8_t fagc_allow_agc_gain_increase; /* adi,fagc-allow-agc-gain-increase-enable */
|
||||
uint32_t fagc_lp_thresh_increment_time; /* adi,fagc-lp-thresh-increment-time */
|
||||
uint32_t fagc_lp_thresh_increment_steps; /* adi,fagc-lp-thresh-increment-steps */
|
||||
/* Fast AGC - Lock Level (Lock Level is set via slow AGC inner high threshold) */
|
||||
uint8_t fagc_lock_level_lmt_gain_increase_en; /* adi,fagc-lock-level-lmt-gain-increase-enable */
|
||||
uint32_t fagc_lock_level_gain_increase_upper_limit; /* adi,fagc-lock-level-gain-increase-upper-limit */
|
||||
/* Fast AGC - Peak Detectors and Final Settling */
|
||||
uint32_t fagc_lpf_final_settling_steps; /* adi,fagc-lpf-final-settling-steps */
|
||||
uint32_t fagc_lmt_final_settling_steps; /* adi,fagc-lmt-final-settling-steps */
|
||||
uint32_t fagc_final_overrange_count; /* adi,fagc-final-overrange-count */
|
||||
/* Fast AGC - Final Power Test */
|
||||
uint8_t fagc_gain_increase_after_gain_lock_en; /* adi,fagc-gain-increase-after-gain-lock-enable */
|
||||
/* Fast AGC - Unlocking the Gain */
|
||||
uint32_t fagc_gain_index_type_after_exit_rx_mode; /* adi,fagc-gain-index-type-after-exit-rx-mode */
|
||||
uint8_t fagc_use_last_lock_level_for_set_gain_en; /* adi,fagc-use-last-lock-level-for-set-gain-enable */
|
||||
uint8_t fagc_rst_gla_stronger_sig_thresh_exceeded_en; /* adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable */
|
||||
uint32_t fagc_optimized_gain_offset; /* adi,fagc-optimized-gain-offset */
|
||||
uint32_t fagc_rst_gla_stronger_sig_thresh_above_ll; /* adi,fagc-rst-gla-stronger-sig-thresh-above-ll */
|
||||
uint8_t fagc_rst_gla_engergy_lost_sig_thresh_exceeded_en; /* adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable */
|
||||
uint8_t fagc_rst_gla_engergy_lost_goto_optim_gain_en; /* adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable */
|
||||
uint32_t fagc_rst_gla_engergy_lost_sig_thresh_below_ll; /* adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll */
|
||||
uint32_t fagc_energy_lost_stronger_sig_gain_lock_exit_cnt; /* adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt */
|
||||
uint8_t fagc_rst_gla_large_adc_overload_en; /* adi,fagc-rst-gla-large-adc-overload-enable */
|
||||
uint8_t fagc_rst_gla_large_lmt_overload_en; /* adi,fagc-rst-gla-large-lmt-overload-enable */
|
||||
uint8_t fagc_rst_gla_en_agc_pulled_high_en; /* adi,fagc-rst-gla-en-agc-pulled-high-enable */
|
||||
uint32_t fagc_rst_gla_if_en_agc_pulled_high_mode; /* adi,fagc-rst-gla-if-en-agc-pulled-high-mode */
|
||||
uint32_t fagc_power_measurement_duration_in_state5; /* adi,fagc-power-measurement-duration-in-state5 */
|
||||
uint32_t fagc_large_overload_inc_steps; /* adi,fagc-adc-large-overload-inc-steps - Name is misleading should be dec-steps */
|
||||
/* RSSI Control */
|
||||
uint32_t rssi_delay; /* adi,rssi-delay */
|
||||
uint32_t rssi_duration; /* adi,rssi-duration */
|
||||
uint8_t rssi_restart_mode; /* adi,rssi-restart-mode */
|
||||
uint8_t rssi_unit_is_rx_samples_enable; /* adi,rssi-unit-is-rx-samples-enable */
|
||||
uint32_t rssi_wait; /* adi,rssi-wait */
|
||||
/* Aux ADC Control */
|
||||
uint32_t aux_adc_decimation; /* adi,aux-adc-decimation */
|
||||
uint32_t aux_adc_rate; /* adi,aux-adc-rate */
|
||||
/* AuxDAC Control */
|
||||
uint8_t aux_dac_manual_mode_enable; /* adi,aux-dac-manual-mode-enable */
|
||||
uint32_t aux_dac1_default_value_mV; /* adi,aux-dac1-default-value-mV */
|
||||
uint8_t aux_dac1_active_in_rx_enable; /* adi,aux-dac1-active-in-rx-enable */
|
||||
uint8_t aux_dac1_active_in_tx_enable; /* adi,aux-dac1-active-in-tx-enable */
|
||||
uint8_t aux_dac1_active_in_alert_enable; /* adi,aux-dac1-active-in-alert-enable */
|
||||
uint32_t aux_dac1_rx_delay_us; /* adi,aux-dac1-rx-delay-us */
|
||||
uint32_t aux_dac1_tx_delay_us; /* adi,aux-dac1-tx-delay-us */
|
||||
uint32_t aux_dac2_default_value_mV; /* adi,aux-dac2-default-value-mV */
|
||||
uint8_t aux_dac2_active_in_rx_enable; /* adi,aux-dac2-active-in-rx-enable */
|
||||
uint8_t aux_dac2_active_in_tx_enable; /* adi,aux-dac2-active-in-tx-enable */
|
||||
uint8_t aux_dac2_active_in_alert_enable; /* adi,aux-dac2-active-in-alert-enable */
|
||||
uint32_t aux_dac2_rx_delay_us; /* adi,aux-dac2-rx-delay-us */
|
||||
uint32_t aux_dac2_tx_delay_us; /* adi,aux-dac2-tx-delay-us */
|
||||
/* Temperature Sensor Control */
|
||||
uint32_t temp_sense_decimation; /* adi,temp-sense-decimation */
|
||||
uint16_t temp_sense_measurement_interval_ms; /* adi,temp-sense-measurement-interval-ms */
|
||||
int8_t temp_sense_offset_signed; /* adi,temp-sense-offset-signed */
|
||||
uint8_t temp_sense_periodic_measurement_enable; /* adi,temp-sense-periodic-measurement-enable */
|
||||
/* Control Out Setup */
|
||||
uint8_t ctrl_outs_enable_mask; /* adi,ctrl-outs-enable-mask */
|
||||
uint8_t ctrl_outs_index; /* adi,ctrl-outs-index */
|
||||
/* External LNA Control */
|
||||
uint32_t elna_settling_delay_ns; /* adi,elna-settling-delay-ns */
|
||||
uint32_t elna_gain_mdB; /* adi,elna-gain-mdB */
|
||||
uint32_t elna_bypass_loss_mdB; /* adi,elna-bypass-loss-mdB */
|
||||
uint8_t elna_rx1_gpo0_control_enable; /* adi,elna-rx1-gpo0-control-enable */
|
||||
uint8_t elna_rx2_gpo1_control_enable; /* adi,elna-rx2-gpo1-control-enable */
|
||||
uint8_t elna_gaintable_all_index_enable; /* adi,elna-gaintable-all-index-enable */
|
||||
/* Digital Interface Control */
|
||||
uint8_t digital_interface_tune_skip_mode; /* adi,digital-interface-tune-skip-mode */
|
||||
uint8_t digital_interface_tune_fir_disable; /* adi,digital-interface-tune-fir-disable */
|
||||
uint8_t pp_tx_swap_enable; /* adi,pp-tx-swap-enable */
|
||||
uint8_t pp_rx_swap_enable; /* adi,pp-rx-swap-enable */
|
||||
uint8_t tx_channel_swap_enable; /* adi,tx-channel-swap-enable */
|
||||
uint8_t rx_channel_swap_enable; /* adi,rx-channel-swap-enable */
|
||||
uint8_t rx_frame_pulse_mode_enable; /* adi,rx-frame-pulse-mode-enable */
|
||||
uint8_t two_t_two_r_timing_enable; /* adi,2t2r-timing-enable */
|
||||
uint8_t invert_data_bus_enable; /* adi,invert-data-bus-enable */
|
||||
uint8_t invert_data_clk_enable; /* adi,invert-data-clk-enable */
|
||||
uint8_t fdd_alt_word_order_enable; /* adi,fdd-alt-word-order-enable */
|
||||
uint8_t invert_rx_frame_enable; /* adi,invert-rx-frame-enable */
|
||||
uint8_t fdd_rx_rate_2tx_enable; /* adi,fdd-rx-rate-2tx-enable */
|
||||
uint8_t swap_ports_enable; /* adi,swap-ports-enable */
|
||||
uint8_t single_data_rate_enable; /* adi,single-data-rate-enable */
|
||||
uint8_t lvds_mode_enable; /* adi,lvds-mode-enable */
|
||||
uint8_t half_duplex_mode_enable; /* adi,half-duplex-mode-enable */
|
||||
uint8_t single_port_mode_enable; /* adi,single-port-mode-enable */
|
||||
uint8_t full_port_enable; /* adi,full-port-enable */
|
||||
uint8_t full_duplex_swap_bits_enable; /* adi,full-duplex-swap-bits-enable */
|
||||
uint32_t delay_rx_data; /* adi,delay-rx-data */
|
||||
uint32_t rx_data_clock_delay; /* adi,rx-data-clock-delay */
|
||||
uint32_t rx_data_delay; /* adi,rx-data-delay */
|
||||
uint32_t tx_fb_clock_delay; /* adi,tx-fb-clock-delay */
|
||||
uint32_t tx_data_delay; /* adi,tx-data-delay */
|
||||
uint32_t lvds_bias_mV; /* adi,lvds-bias-mV */
|
||||
uint8_t lvds_rx_onchip_termination_enable; /* adi,lvds-rx-onchip-termination-enable */
|
||||
uint8_t rx1rx2_phase_inversion_en; /* adi,rx1-rx2-phase-inversion-enable */
|
||||
uint8_t lvds_invert1_control; /* adi,lvds-invert1-control */
|
||||
uint8_t lvds_invert2_control; /* adi,lvds-invert2-control */
|
||||
/* GPO Control */
|
||||
uint8_t gpo_manual_mode_enable; /* adi,gpo-manual-mode-enable */
|
||||
uint32_t gpo_manual_mode_enable_mask; /* adi,gpo-manual-mode-enable-mask */
|
||||
uint8_t gpo0_inactive_state_high_enable; /* adi,gpo0-inactive-state-high-enable */
|
||||
uint8_t gpo1_inactive_state_high_enable; /* adi,gpo1-inactive-state-high-enable */
|
||||
uint8_t gpo2_inactive_state_high_enable; /* adi,gpo2-inactive-state-high-enable */
|
||||
uint8_t gpo3_inactive_state_high_enable; /* adi,gpo3-inactive-state-high-enable */
|
||||
uint8_t gpo0_slave_rx_enable; /* adi,gpo0-slave-rx-enable */
|
||||
uint8_t gpo0_slave_tx_enable; /* adi,gpo0-slave-tx-enable */
|
||||
uint8_t gpo1_slave_rx_enable; /* adi,gpo1-slave-rx-enable */
|
||||
uint8_t gpo1_slave_tx_enable; /* adi,gpo1-slave-tx-enable */
|
||||
uint8_t gpo2_slave_rx_enable; /* adi,gpo2-slave-rx-enable */
|
||||
uint8_t gpo2_slave_tx_enable; /* adi,gpo2-slave-tx-enable */
|
||||
uint8_t gpo3_slave_rx_enable; /* adi,gpo3-slave-rx-enable */
|
||||
uint8_t gpo3_slave_tx_enable; /* adi,gpo3-slave-tx-enable */
|
||||
uint8_t gpo0_rx_delay_us; /* adi,gpo0-rx-delay-us */
|
||||
uint8_t gpo0_tx_delay_us; /* adi,gpo0-tx-delay-us */
|
||||
uint8_t gpo1_rx_delay_us; /* adi,gpo1-rx-delay-us */
|
||||
uint8_t gpo1_tx_delay_us; /* adi,gpo1-tx-delay-us */
|
||||
uint8_t gpo2_rx_delay_us; /* adi,gpo2-rx-delay-us */
|
||||
uint8_t gpo2_tx_delay_us; /* adi,gpo2-tx-delay-us */
|
||||
uint8_t gpo3_rx_delay_us; /* adi,gpo3-rx-delay-us */
|
||||
uint8_t gpo3_tx_delay_us; /* adi,gpo3-tx-delay-us */
|
||||
/* Tx Monitor Control */
|
||||
uint32_t low_high_gain_threshold_mdB; /* adi,txmon-low-high-thresh */
|
||||
uint32_t low_gain_dB; /* adi,txmon-low-gain */
|
||||
uint32_t high_gain_dB; /* adi,txmon-high-gain */
|
||||
uint8_t tx_mon_track_en; /* adi,txmon-dc-tracking-enable */
|
||||
uint8_t one_shot_mode_en; /* adi,txmon-one-shot-mode-enable */
|
||||
uint32_t tx_mon_delay; /* adi,txmon-delay */
|
||||
uint32_t tx_mon_duration; /* adi,txmon-duration */
|
||||
uint32_t tx1_mon_front_end_gain; /* adi,txmon-1-front-end-gain */
|
||||
uint32_t tx2_mon_front_end_gain; /* adi,txmon-2-front-end-gain */
|
||||
uint32_t tx1_mon_lo_cm; /* adi,txmon-1-lo-cm */
|
||||
uint32_t tx2_mon_lo_cm; /* adi,txmon-2-lo-cm */
|
||||
/* GPIO definitions */
|
||||
struct gpio_init_param gpio_resetb; /* reset-gpios */
|
||||
/* MCS Sync */
|
||||
struct gpio_init_param gpio_sync; /* sync-gpios */
|
||||
struct gpio_init_param gpio_cal_sw1; /* cal-sw1-gpios */
|
||||
struct gpio_init_param gpio_cal_sw2; /* cal-sw2-gpios */
|
||||
|
||||
struct spi_init_param spi_param;
|
||||
|
||||
/* External LO clocks */
|
||||
uint32_t (*ad9361_rfpll_ext_recalc_rate)(struct refclk_scale *clk_priv);
|
||||
int32_t (*ad9361_rfpll_ext_round_rate)(struct refclk_scale *clk_priv,
|
||||
uint32_t rate);
|
||||
int32_t (*ad9361_rfpll_ext_set_rate)(struct refclk_scale *clk_priv,
|
||||
uint32_t rate);
|
||||
|
||||
} AD9361_InitParam;
|
||||
|
||||
typedef struct {
|
||||
uint32_t rx; /* 1, 2, 3(both) */
|
||||
int32_t rx_gain; /* -12, -6, 0, 6 */
|
||||
uint32_t rx_dec; /* 1, 2, 4 */
|
||||
int16_t rx_coef[128];
|
||||
uint8_t rx_coef_size;
|
||||
uint32_t rx_path_clks[6];
|
||||
uint32_t rx_bandwidth;
|
||||
} AD9361_RXFIRConfig;
|
||||
|
||||
typedef struct {
|
||||
uint32_t tx; /* 1, 2, 3(both) */
|
||||
int32_t tx_gain; /* -6, 0 */
|
||||
uint32_t tx_int; /* 1, 2, 4 */
|
||||
int16_t tx_coef[128];
|
||||
uint8_t tx_coef_size;
|
||||
uint32_t tx_path_clks[6];
|
||||
uint32_t tx_bandwidth;
|
||||
} AD9361_TXFIRConfig;
|
||||
|
||||
enum ad9361_ensm_mode {
|
||||
ENSM_MODE_TX,
|
||||
ENSM_MODE_RX,
|
||||
ENSM_MODE_ALERT,
|
||||
ENSM_MODE_FDD,
|
||||
ENSM_MODE_WAIT,
|
||||
ENSM_MODE_SLEEP,
|
||||
ENSM_MODE_PINCTRL,
|
||||
ENSM_MODE_PINCTRL_FDD_INDEP,
|
||||
};
|
||||
|
||||
#define ENABLE 1
|
||||
#define DISABLE 0
|
||||
|
||||
#define RX1 0
|
||||
#define RX2 1
|
||||
|
||||
#define TX1 0
|
||||
#define TX2 1
|
||||
|
||||
#define A_BALANCED 0
|
||||
#define B_BALANCED 1
|
||||
#define C_BALANCED 2
|
||||
#define A_N 3
|
||||
#define A_P 4
|
||||
#define B_N 5
|
||||
#define B_P 6
|
||||
#define C_N 7
|
||||
#define C_P 8
|
||||
#define TX_MON1 9
|
||||
#define TX_MON2 10
|
||||
#define TX_MON1_2 11
|
||||
|
||||
#define TXA 0
|
||||
#define TXB 1
|
||||
|
||||
#define MODE_1x1 1
|
||||
#define MODE_2x2 2
|
||||
|
||||
#define HIGHEST_OSR 0
|
||||
#define NOMINAL_OSR 1
|
||||
|
||||
#define INT_LO 0
|
||||
#define EXT_LO 1
|
||||
|
||||
#define ON 0
|
||||
#define OFF 1
|
||||
|
||||
/******************************************************************************/
|
||||
/************************ Functions Declarations ******************************/
|
||||
/******************************************************************************/
|
||||
/* Initialize the AD9361 part. */
|
||||
int32_t ad9361_init (struct ad9361_rf_phy **ad9361_phy,
|
||||
AD9361_InitParam *init_param);
|
||||
/* Free the allocated resources. */
|
||||
int32_t ad9361_remove(struct ad9361_rf_phy *phy);
|
||||
/* Set the Enable State Machine (ENSM) mode. */
|
||||
int32_t ad9361_set_en_state_machine_mode (struct ad9361_rf_phy *phy,
|
||||
uint32_t mode);
|
||||
/* Get the Enable State Machine (ENSM) mode. */
|
||||
int32_t ad9361_get_en_state_machine_mode (struct ad9361_rf_phy *phy,
|
||||
uint32_t *mode);
|
||||
/* Set the receive RF gain for the selected channel. */
|
||||
int32_t ad9361_set_rx_rf_gain (struct ad9361_rf_phy *phy, uint8_t ch,
|
||||
int32_t gain_db);
|
||||
/* Get current receive RF gain for the selected channel. */
|
||||
int32_t ad9361_get_rx_rf_gain (struct ad9361_rf_phy *phy, uint8_t ch,
|
||||
int32_t *gain_db);
|
||||
/* Set the RX RF bandwidth. */
|
||||
int32_t ad9361_set_rx_rf_bandwidth (struct ad9361_rf_phy *phy,
|
||||
uint32_t bandwidth_hz);
|
||||
/* Get the RX RF bandwidth. */
|
||||
int32_t ad9361_get_rx_rf_bandwidth (struct ad9361_rf_phy *phy,
|
||||
uint32_t *bandwidth_hz);
|
||||
/* Set the RX sampling frequency. */
|
||||
int32_t ad9361_set_rx_sampling_freq (struct ad9361_rf_phy *phy,
|
||||
uint32_t sampling_freq_hz);
|
||||
/* Get current RX sampling frequency. */
|
||||
int32_t ad9361_get_rx_sampling_freq (struct ad9361_rf_phy *phy,
|
||||
uint32_t *sampling_freq_hz);
|
||||
/* Set the RX LO frequency. */
|
||||
int32_t ad9361_set_rx_lo_freq (struct ad9361_rf_phy *phy, uint64_t lo_freq_hz);
|
||||
/* Get current RX LO frequency. */
|
||||
int32_t ad9361_get_rx_lo_freq (struct ad9361_rf_phy *phy, uint64_t *lo_freq_hz);
|
||||
/* Switch between internal and external LO. */
|
||||
int32_t ad9361_set_rx_lo_int_ext(struct ad9361_rf_phy *phy, uint8_t int_ext);
|
||||
/* Get the RSSI for the selected channel. */
|
||||
int32_t ad9361_get_rx_rssi (struct ad9361_rf_phy *phy, uint8_t ch,
|
||||
struct rf_rssi *rssi);
|
||||
/* Set the gain control mode for the selected channel. */
|
||||
int32_t ad9361_set_rx_gain_control_mode (struct ad9361_rf_phy *phy, uint8_t ch,
|
||||
uint8_t gc_mode);
|
||||
/* Get the gain control mode for the selected channel. */
|
||||
int32_t ad9361_get_rx_gain_control_mode (struct ad9361_rf_phy *phy, uint8_t ch,
|
||||
uint8_t *gc_mode);
|
||||
/* Set the RX FIR filter configuration. */
|
||||
int32_t ad9361_set_rx_fir_config (struct ad9361_rf_phy *phy,
|
||||
AD9361_RXFIRConfig fir_cfg);
|
||||
/* Get the RX FIR filter configuration. */
|
||||
int32_t ad9361_get_rx_fir_config(struct ad9361_rf_phy *phy, uint8_t rx_ch,
|
||||
AD9361_RXFIRConfig *fir_cfg);
|
||||
/* Enable/disable the RX FIR filter. */
|
||||
int32_t ad9361_set_rx_fir_en_dis (struct ad9361_rf_phy *phy, uint8_t en_dis);
|
||||
/* Get the status of the RX FIR filter. */
|
||||
int32_t ad9361_get_rx_fir_en_dis (struct ad9361_rf_phy *phy, uint8_t *en_dis);
|
||||
/* Enable/disable the RX RFDC Tracking. */
|
||||
int32_t ad9361_set_rx_rfdc_track_en_dis (struct ad9361_rf_phy *phy,
|
||||
uint8_t en_dis);
|
||||
/* Get the status of the RX RFDC Tracking. */
|
||||
int32_t ad9361_get_rx_rfdc_track_en_dis (struct ad9361_rf_phy *phy,
|
||||
uint8_t *en_dis);
|
||||
/* Enable/disable the RX BasebandDC Tracking. */
|
||||
int32_t ad9361_set_rx_bbdc_track_en_dis (struct ad9361_rf_phy *phy,
|
||||
uint8_t en_dis);
|
||||
/* Get the status of the RX BasebandDC Tracking. */
|
||||
int32_t ad9361_get_rx_bbdc_track_en_dis (struct ad9361_rf_phy *phy,
|
||||
uint8_t *en_dis);
|
||||
/* Enable/disable the RX Quadrature Tracking. */
|
||||
int32_t ad9361_set_rx_quad_track_en_dis (struct ad9361_rf_phy *phy,
|
||||
uint8_t en_dis);
|
||||
/* Get the status of the RX Quadrature Tracking. */
|
||||
int32_t ad9361_get_rx_quad_track_en_dis (struct ad9361_rf_phy *phy,
|
||||
uint8_t *en_dis);
|
||||
/* Set the RX RF input port. */
|
||||
int32_t ad9361_set_rx_rf_port_input (struct ad9361_rf_phy *phy, uint32_t mode);
|
||||
/* Get the selected RX RF input port. */
|
||||
int32_t ad9361_get_rx_rf_port_input (struct ad9361_rf_phy *phy, uint32_t *mode);
|
||||
/* Store RX fastlock profile. */
|
||||
int32_t ad9361_rx_fastlock_store(struct ad9361_rf_phy *phy, uint32_t profile);
|
||||
/* Recall RX fastlock profile. */
|
||||
int32_t ad9361_rx_fastlock_recall(struct ad9361_rf_phy *phy, uint32_t profile);
|
||||
/* Load RX fastlock profile. */
|
||||
int32_t ad9361_rx_fastlock_load(struct ad9361_rf_phy *phy, uint32_t profile,
|
||||
uint8_t *values);
|
||||
/* Save RX fastlock profile. */
|
||||
int32_t ad9361_rx_fastlock_save(struct ad9361_rf_phy *phy, uint32_t profile,
|
||||
uint8_t *values);
|
||||
/* Power down the RX Local Oscillator. */
|
||||
int32_t ad9361_rx_lo_powerdown(struct ad9361_rf_phy *phy, uint8_t option);
|
||||
/* Get the RX Local Oscillator power status. */
|
||||
int32_t ad9361_get_rx_lo_power(struct ad9361_rf_phy *phy, uint8_t *option);
|
||||
/* Set the transmit attenuation for the selected channel. */
|
||||
int32_t ad9361_set_tx_attenuation (struct ad9361_rf_phy *phy, uint8_t ch,
|
||||
uint32_t attenuation_mdb);
|
||||
/* Get current transmit attenuation for the selected channel. */
|
||||
int32_t ad9361_get_tx_attenuation (struct ad9361_rf_phy *phy, uint8_t ch,
|
||||
uint32_t *attenuation_mdb);
|
||||
/* Set the TX RF bandwidth. */
|
||||
int32_t ad9361_set_tx_rf_bandwidth (struct ad9361_rf_phy *phy,
|
||||
uint32_t bandwidth_hz);
|
||||
/* Get the TX RF bandwidth. */
|
||||
int32_t ad9361_get_tx_rf_bandwidth (struct ad9361_rf_phy *phy,
|
||||
uint32_t *bandwidth_hz);
|
||||
/* Set the TX sampling frequency. */
|
||||
int32_t ad9361_set_tx_sampling_freq (struct ad9361_rf_phy *phy,
|
||||
uint32_t sampling_freq_hz);
|
||||
/* Get current TX sampling frequency. */
|
||||
int32_t ad9361_get_tx_sampling_freq (struct ad9361_rf_phy *phy,
|
||||
uint32_t *sampling_freq_hz);
|
||||
/* Set the TX LO frequency. */
|
||||
int32_t ad9361_set_tx_lo_freq (struct ad9361_rf_phy *phy, uint64_t lo_freq_hz);
|
||||
/* Get current TX LO frequency. */
|
||||
int32_t ad9361_get_tx_lo_freq (struct ad9361_rf_phy *phy, uint64_t *lo_freq_hz);
|
||||
/* Switch between internal and external LO. */
|
||||
int32_t ad9361_set_tx_lo_int_ext(struct ad9361_rf_phy *phy, uint8_t int_ext);
|
||||
/* Set the TX FIR filter configuration. */
|
||||
int32_t ad9361_set_tx_fir_config (struct ad9361_rf_phy *phy,
|
||||
AD9361_TXFIRConfig fir_cfg);
|
||||
/* Get the TX FIR filter configuration. */
|
||||
int32_t ad9361_get_tx_fir_config(struct ad9361_rf_phy *phy, uint8_t tx_ch,
|
||||
AD9361_TXFIRConfig *fir_cfg);
|
||||
/* Enable/disable the TX FIR filter. */
|
||||
int32_t ad9361_set_tx_fir_en_dis (struct ad9361_rf_phy *phy, uint8_t en_dis);
|
||||
/* Get the status of the TX FIR filter. */
|
||||
int32_t ad9361_get_tx_fir_en_dis (struct ad9361_rf_phy *phy, uint8_t *en_dis);
|
||||
/* Get the TX RSSI for the selected channel. */
|
||||
int32_t ad9361_get_tx_rssi (struct ad9361_rf_phy *phy, uint8_t ch,
|
||||
uint32_t *rssi_db_x_1000);
|
||||
/* Set the TX RF output port. */
|
||||
int32_t ad9361_set_tx_rf_port_output (struct ad9361_rf_phy *phy, uint32_t mode);
|
||||
/* Get the selected TX RF output port. */
|
||||
int32_t ad9361_get_tx_rf_port_output (struct ad9361_rf_phy *phy,
|
||||
uint32_t *mode);
|
||||
/* Enable/disable the auto calibration. */
|
||||
int32_t ad9361_set_tx_auto_cal_en_dis (struct ad9361_rf_phy *phy,
|
||||
uint8_t en_dis);
|
||||
/* Get the status of the auto calibration flag. */
|
||||
int32_t ad9361_get_tx_auto_cal_en_dis (struct ad9361_rf_phy *phy,
|
||||
uint8_t *en_dis);
|
||||
/* Store TX fastlock profile. */
|
||||
int32_t ad9361_tx_fastlock_store(struct ad9361_rf_phy *phy, uint32_t profile);
|
||||
/* Recall TX fastlock profile. */
|
||||
int32_t ad9361_tx_fastlock_recall(struct ad9361_rf_phy *phy, uint32_t profile);
|
||||
/* Load TX fastlock profile. */
|
||||
int32_t ad9361_tx_fastlock_load(struct ad9361_rf_phy *phy, uint32_t profile,
|
||||
uint8_t *values);
|
||||
/* Save TX fastlock profile. */
|
||||
int32_t ad9361_tx_fastlock_save(struct ad9361_rf_phy *phy, uint32_t profile,
|
||||
uint8_t *values);
|
||||
/* Power down the TX Local Oscillator. */
|
||||
int32_t ad9361_tx_lo_powerdown(struct ad9361_rf_phy *phy, uint8_t option);
|
||||
/* Get the TX Local Oscillator power status. */
|
||||
int32_t ad9361_get_tx_lo_power(struct ad9361_rf_phy *phy, uint8_t *option);
|
||||
/* Set the RX and TX path rates. */
|
||||
int32_t ad9361_set_trx_path_clks(struct ad9361_rf_phy *phy,
|
||||
uint32_t *rx_path_clks, uint32_t *tx_path_clks);
|
||||
/* Get the RX and TX path rates. */
|
||||
int32_t ad9361_get_trx_path_clks(struct ad9361_rf_phy *phy,
|
||||
uint32_t *rx_path_clks, uint32_t *tx_path_clks);
|
||||
/* Set the number of channels mode. */
|
||||
int32_t ad9361_set_no_ch_mode(struct ad9361_rf_phy *phy, uint8_t no_ch_mode);
|
||||
/* Do multi chip synchronization. */
|
||||
int32_t ad9361_do_mcs(struct ad9361_rf_phy *phy_master,
|
||||
struct ad9361_rf_phy *phy_slave);
|
||||
/* Enable/disable the TRX FIR filters. */
|
||||
int32_t ad9361_set_trx_fir_en_dis (struct ad9361_rf_phy *phy, uint8_t en_dis);
|
||||
/* Set the OSR rate governor. */
|
||||
int32_t ad9361_set_trx_rate_gov (struct ad9361_rf_phy *phy, uint32_t rate_gov);
|
||||
/* Get the OSR rate governor. */
|
||||
int32_t ad9361_get_trx_rate_gov (struct ad9361_rf_phy *phy, uint32_t *rate_gov);
|
||||
/* Perform the selected calibration. */
|
||||
int32_t ad9361_do_calib(struct ad9361_rf_phy *phy, uint32_t cal, int32_t arg);
|
||||
/* Load and enable TRX FIR filters configurations. */
|
||||
int32_t ad9361_trx_load_enable_fir(struct ad9361_rf_phy *phy,
|
||||
AD9361_RXFIRConfig rx_fir_cfg,
|
||||
AD9361_TXFIRConfig tx_fir_cfg);
|
||||
/* Do DCXO coarse tuning. */
|
||||
int32_t ad9361_do_dcxo_tune_coarse(struct ad9361_rf_phy *phy,
|
||||
uint32_t coarse);
|
||||
/* Do DCXO fine tuning. */
|
||||
int32_t ad9361_do_dcxo_tune_fine(struct ad9361_rf_phy *phy,
|
||||
uint32_t fine);
|
||||
/* Get the temperature. */
|
||||
int32_t ad9361_get_temperature(struct ad9361_rf_phy *phy,
|
||||
int32_t *temp);
|
||||
#endif
|
||||
+86
@@ -0,0 +1,86 @@
|
||||
|
||||
/***************************************************************************//**
|
||||
* @file ad9361_conv.c
|
||||
* @brief Implementation of AD9361 Conv Driver.
|
||||
********************************************************************************
|
||||
* Copyright 2014-2015(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
#include <inttypes.h>
|
||||
#include <string.h>
|
||||
#include "ad9361.h"
|
||||
#include "ad9361_util.h"
|
||||
#include "../../../../app_config.h"
|
||||
#include "../../../include/delay.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/********************** Macros and Constants Definitions **********************/
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* HDL loopback enable/disable.
|
||||
* @param phy The AD9361 state structure.
|
||||
* @param enable Enable/disable option.
|
||||
* @return 0 in case of success, negative error code otherwise.
|
||||
*/
|
||||
int32_t ad9361_hdl_loopback(struct ad9361_rf_phy *phy, bool enable)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/**
|
||||
* Digital tune.
|
||||
* @param phy The AD9361 state structure.
|
||||
* @param max_freq Maximum frequency.
|
||||
* @param flags Flags: BE_VERBOSE, BE_MOREVERBOSE, DO_IDELAY, DO_ODELAY.
|
||||
* @return 0 in case of success, negative error code otherwise.
|
||||
*/
|
||||
int32_t ad9361_dig_tune(struct ad9361_rf_phy *phy, uint32_t max_freq,
|
||||
enum dig_tune_flags flags)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Setup the AD9361 device.
|
||||
* @param phy The AD9361 state structure.
|
||||
* @return 0 in case of success, negative error code otherwise.
|
||||
*/
|
||||
int32_t ad9361_post_setup(struct ad9361_rf_phy *phy)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
+335
@@ -0,0 +1,335 @@
|
||||
/***************************************************************************//**
|
||||
* @file ad9361_util.c
|
||||
* @brief AD9361 Implementation of Util Driver.
|
||||
* @author DBogdan (dragos.bogdan@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2013(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
#include <string.h>
|
||||
#include "ad9361_util.h"
|
||||
#include "../../../include/delay.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/*************************** Macros Definitions *******************************/
|
||||
/******************************************************************************/
|
||||
#define BITS_PER_LONG 32
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief clk_prepare_enable
|
||||
*******************************************************************************/
|
||||
int32_t clk_prepare_enable(struct clk *clk)
|
||||
{
|
||||
if (clk) {
|
||||
// Unused variable - fix compiler warning
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief clk_get_rate
|
||||
*******************************************************************************/
|
||||
uint32_t clk_get_rate(struct ad9361_rf_phy *phy,
|
||||
struct refclk_scale *clk_priv)
|
||||
{
|
||||
uint32_t rate = 0;
|
||||
uint32_t source;
|
||||
|
||||
source = clk_priv->source;
|
||||
|
||||
switch (source) {
|
||||
case TX_REFCLK:
|
||||
case RX_REFCLK:
|
||||
case BB_REFCLK:
|
||||
rate = ad9361_clk_factor_recalc_rate(clk_priv,
|
||||
phy->clk_refin->rate);
|
||||
break;
|
||||
case TX_RFPLL_INT:
|
||||
case RX_RFPLL_INT:
|
||||
rate = ad9361_rfpll_int_recalc_rate(clk_priv,
|
||||
phy->clks[clk_priv->parent_source]->rate);
|
||||
break;
|
||||
case RX_RFPLL_DUMMY:
|
||||
case TX_RFPLL_DUMMY:
|
||||
rate = ad9361_rfpll_dummy_recalc_rate(clk_priv);
|
||||
break;
|
||||
case TX_RFPLL:
|
||||
case RX_RFPLL:
|
||||
rate = ad9361_rfpll_recalc_rate(clk_priv);
|
||||
break;
|
||||
case BBPLL_CLK:
|
||||
rate = ad9361_bbpll_recalc_rate(clk_priv,
|
||||
phy->clks[clk_priv->parent_source]->rate);
|
||||
break;
|
||||
case ADC_CLK:
|
||||
case R2_CLK:
|
||||
case R1_CLK:
|
||||
case CLKRF_CLK:
|
||||
case RX_SAMPL_CLK:
|
||||
case DAC_CLK:
|
||||
case T2_CLK:
|
||||
case T1_CLK:
|
||||
case CLKTF_CLK:
|
||||
case TX_SAMPL_CLK:
|
||||
rate = ad9361_clk_factor_recalc_rate(clk_priv,
|
||||
phy->clks[clk_priv->parent_source]->rate);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return rate;
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief clk_set_rate
|
||||
*******************************************************************************/
|
||||
int32_t clk_set_rate(struct ad9361_rf_phy *phy,
|
||||
struct refclk_scale *clk_priv,
|
||||
uint32_t rate)
|
||||
{
|
||||
uint32_t source;
|
||||
int32_t i;
|
||||
uint32_t round_rate;
|
||||
|
||||
source = clk_priv->source;
|
||||
if(phy->clks[source]->rate != rate)
|
||||
{
|
||||
switch (source) {
|
||||
case TX_REFCLK:
|
||||
case RX_REFCLK:
|
||||
case BB_REFCLK:
|
||||
round_rate = ad9361_clk_factor_round_rate(clk_priv, rate,
|
||||
&phy->clk_refin->rate);
|
||||
ad9361_clk_factor_set_rate(clk_priv, round_rate,
|
||||
phy->clk_refin->rate);
|
||||
phy->clks[source]->rate = ad9361_clk_factor_recalc_rate(clk_priv,
|
||||
phy->clk_refin->rate);
|
||||
break;
|
||||
case TX_RFPLL_INT:
|
||||
case RX_RFPLL_INT:
|
||||
round_rate = ad9361_rfpll_int_round_rate(clk_priv, rate,
|
||||
&phy->clks[clk_priv->parent_source]->rate);
|
||||
ad9361_rfpll_int_set_rate(clk_priv, round_rate,
|
||||
phy->clks[clk_priv->parent_source]->rate);
|
||||
phy->clks[source]->rate = ad9361_rfpll_int_recalc_rate(clk_priv,
|
||||
phy->clks[clk_priv->parent_source]->rate);
|
||||
break;
|
||||
case RX_RFPLL_DUMMY:
|
||||
case TX_RFPLL_DUMMY:
|
||||
ad9361_rfpll_dummy_set_rate(clk_priv, rate);
|
||||
break;
|
||||
case TX_RFPLL:
|
||||
case RX_RFPLL:
|
||||
round_rate = ad9361_rfpll_round_rate(clk_priv, rate);
|
||||
ad9361_rfpll_set_rate(clk_priv, round_rate);
|
||||
phy->clks[source]->rate = ad9361_rfpll_recalc_rate(clk_priv);
|
||||
break;
|
||||
case BBPLL_CLK:
|
||||
round_rate = ad9361_bbpll_round_rate(clk_priv, rate,
|
||||
&phy->clks[clk_priv->parent_source]->rate);
|
||||
ad9361_bbpll_set_rate(clk_priv, round_rate,
|
||||
phy->clks[clk_priv->parent_source]->rate);
|
||||
phy->clks[source]->rate = ad9361_bbpll_recalc_rate(clk_priv,
|
||||
phy->clks[clk_priv->parent_source]->rate);
|
||||
phy->bbpll_initialized = true;
|
||||
break;
|
||||
case ADC_CLK:
|
||||
case R2_CLK:
|
||||
case R1_CLK:
|
||||
case CLKRF_CLK:
|
||||
case RX_SAMPL_CLK:
|
||||
case DAC_CLK:
|
||||
case T2_CLK:
|
||||
case T1_CLK:
|
||||
case CLKTF_CLK:
|
||||
case TX_SAMPL_CLK:
|
||||
round_rate = ad9361_clk_factor_round_rate(clk_priv, rate,
|
||||
&phy->clks[clk_priv->parent_source]->rate);
|
||||
ad9361_clk_factor_set_rate(clk_priv, round_rate,
|
||||
phy->clks[clk_priv->parent_source]->rate);
|
||||
phy->clks[source]->rate = ad9361_clk_factor_recalc_rate(clk_priv,
|
||||
phy->clks[clk_priv->parent_source]->rate);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
for(i = BB_REFCLK; i < BBPLL_CLK; i++)
|
||||
{
|
||||
phy->clks[i]->rate = ad9361_clk_factor_recalc_rate(phy->ref_clk_scale[i],
|
||||
phy->clk_refin->rate);
|
||||
}
|
||||
phy->clks[BBPLL_CLK]->rate = ad9361_bbpll_recalc_rate(phy->ref_clk_scale[BBPLL_CLK],
|
||||
phy->clks[phy->ref_clk_scale[BBPLL_CLK]->parent_source]->rate);
|
||||
for(i = ADC_CLK; i < RX_RFPLL_INT; i++)
|
||||
{
|
||||
phy->clks[i]->rate = ad9361_clk_factor_recalc_rate(phy->ref_clk_scale[i],
|
||||
phy->clks[phy->ref_clk_scale[i]->parent_source]->rate);
|
||||
}
|
||||
for(i = RX_RFPLL_INT; i < RX_RFPLL_DUMMY; i++)
|
||||
{
|
||||
phy->clks[i]->rate = ad9361_rfpll_int_recalc_rate(phy->ref_clk_scale[i],
|
||||
phy->clks[phy->ref_clk_scale[i]->parent_source]->rate);
|
||||
}
|
||||
for(i = RX_RFPLL_DUMMY; i < RX_RFPLL; i++)
|
||||
{
|
||||
phy->clks[i]->rate = ad9361_rfpll_dummy_recalc_rate(phy->ref_clk_scale[i]);
|
||||
}
|
||||
for(i = RX_RFPLL; i < NUM_AD9361_CLKS; i++)
|
||||
{
|
||||
phy->clks[i]->rate = ad9361_rfpll_recalc_rate(phy->ref_clk_scale[i]);
|
||||
}
|
||||
} else {
|
||||
if ((source == BBPLL_CLK) && !phy->bbpll_initialized) {
|
||||
round_rate = ad9361_bbpll_round_rate(clk_priv, rate,
|
||||
&phy->clks[clk_priv->parent_source]->rate);
|
||||
ad9361_bbpll_set_rate(clk_priv, round_rate,
|
||||
phy->clks[clk_priv->parent_source]->rate);
|
||||
phy->clks[source]->rate = ad9361_bbpll_recalc_rate(clk_priv,
|
||||
phy->clks[clk_priv->parent_source]->rate);
|
||||
phy->bbpll_initialized = true;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief int_sqrt
|
||||
*******************************************************************************/
|
||||
uint32_t int_sqrt(uint32_t x)
|
||||
{
|
||||
uint32_t b, m, y = 0;
|
||||
|
||||
if (x <= 1)
|
||||
return x;
|
||||
|
||||
m = 1UL << (BITS_PER_LONG - 2);
|
||||
while (m != 0) {
|
||||
b = y + m;
|
||||
y >>= 1;
|
||||
|
||||
if (x >= b) {
|
||||
x -= b;
|
||||
y += m;
|
||||
}
|
||||
m >>= 2;
|
||||
}
|
||||
|
||||
return y;
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief ilog2
|
||||
*******************************************************************************/
|
||||
int32_t ilog2(int32_t x)
|
||||
{
|
||||
int32_t A = !(!(x >> 16));
|
||||
int32_t count = 0;
|
||||
int32_t x_copy = x;
|
||||
|
||||
count = count + (A << 4);
|
||||
|
||||
x_copy = (((~A + 1) & (x >> 16)) + (~(~A + 1) & x));
|
||||
|
||||
A = !(!(x_copy >> 8));
|
||||
count = count + (A << 3);
|
||||
x_copy = (((~A + 1) & (x_copy >> 8)) + (~(~A + 1) & x_copy));
|
||||
|
||||
A = !(!(x_copy >> 4));
|
||||
count = count + (A << 2);
|
||||
x_copy = (((~A + 1) & (x_copy >> 4)) + (~(~A + 1) & x_copy));
|
||||
|
||||
A = !(!(x_copy >> 2));
|
||||
count = count + (A << 1);
|
||||
x_copy = (((~A + 1) & (x_copy >> 2)) + (~(~A + 1) & x_copy));
|
||||
|
||||
A = !(!(x_copy >> 1));
|
||||
count = count + A;
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief find_first_bit
|
||||
*******************************************************************************/
|
||||
uint32_t find_first_bit(uint32_t word)
|
||||
{
|
||||
int32_t num = 0;
|
||||
|
||||
if ((word & 0xffff) == 0) {
|
||||
num += 16;
|
||||
word >>= 16;
|
||||
}
|
||||
if ((word & 0xff) == 0) {
|
||||
num += 8;
|
||||
word >>= 8;
|
||||
}
|
||||
if ((word & 0xf) == 0) {
|
||||
num += 4;
|
||||
word >>= 4;
|
||||
}
|
||||
if ((word & 0x3) == 0) {
|
||||
num += 2;
|
||||
word >>= 2;
|
||||
}
|
||||
if ((word & 0x1) == 0)
|
||||
num += 1;
|
||||
return num;
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief ERR_PTR
|
||||
*******************************************************************************/
|
||||
void * ERR_PTR(long error)
|
||||
{
|
||||
return (void *) error;
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief zmalloc
|
||||
*******************************************************************************/
|
||||
void *zmalloc(size_t size)
|
||||
{
|
||||
void *ptr = malloc(size);
|
||||
if (ptr)
|
||||
memset(ptr, 0, size);
|
||||
mdelay(1);
|
||||
|
||||
return ptr;
|
||||
}
|
||||
+121
@@ -0,0 +1,121 @@
|
||||
/***************************************************************************//**
|
||||
* @file ad9361_util.h
|
||||
* @brief AD9361 Header file of Util driver.
|
||||
* @author DBogdan (dragos.bogdan@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2013(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
#ifndef __AD9361_UTIL_H__
|
||||
#define __AD9361_UTIL_H__
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
#include <limits.h>
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include "ad9361.h"
|
||||
#include "common.h"
|
||||
#include "../../../../app_config.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/********************** Macros and Constants Definitions **********************/
|
||||
/******************************************************************************/
|
||||
#define CLK_IGNORE_UNUSED BIT(3)
|
||||
#define CLK_GET_RATE_NOCACHE BIT(6)
|
||||
|
||||
#if defined(HAVE_VERBOSE_MESSAGES)
|
||||
#define dev_err(dev, format, ...) ({printf(format, ## __VA_ARGS__);printf("\n"); })
|
||||
#define dev_warn(dev, format, ...) ({printf(format, ## __VA_ARGS__);printf("\n"); })
|
||||
#if defined(HAVE_DEBUG_MESSAGES)
|
||||
#define dev_dbg(dev, format, ...) ({printf(format, ## __VA_ARGS__);printf("\n"); })
|
||||
#else
|
||||
#define dev_dbg(dev, format, ...) ({ if (0) printf(format, ## __VA_ARGS__); })
|
||||
#endif
|
||||
#define printk(format, ...) printf(format, ## __VA_ARGS__)
|
||||
#else
|
||||
#define dev_err(dev, format, ...) ({ if (0) printf(format, ## __VA_ARGS__); })
|
||||
#define dev_warn(dev, format, ...) ({ if (0) printf(format, ## __VA_ARGS__); })
|
||||
#define dev_dbg(dev, format, ...) ({ if (0) printf(format, ## __VA_ARGS__); })
|
||||
#define printk(format, ...) ({ if (0) printf(format, ## __VA_ARGS__); })
|
||||
#endif
|
||||
|
||||
struct device {
|
||||
};
|
||||
|
||||
struct spi_device {
|
||||
struct device dev;
|
||||
uint8_t id_no;
|
||||
};
|
||||
|
||||
struct axiadc_state {
|
||||
struct ad9361_rf_phy *phy;
|
||||
uint32_t pcore_version;
|
||||
};
|
||||
|
||||
struct axiadc_chip_info {
|
||||
char *name;
|
||||
int32_t num_channels;
|
||||
};
|
||||
|
||||
struct axiadc_converter {
|
||||
struct axiadc_chip_info *chip_info;
|
||||
uint32_t scratch_reg[16];
|
||||
};
|
||||
|
||||
#ifdef WIN32
|
||||
#include "basetsd.h"
|
||||
typedef SSIZE_T ssize_t;
|
||||
#define strsep(s, ct) 0
|
||||
#define snprintf(s, n, format, ...) 0
|
||||
#define __func__ __FUNCTION__
|
||||
#endif
|
||||
|
||||
/******************************************************************************/
|
||||
/************************ Functions Declarations ******************************/
|
||||
/******************************************************************************/
|
||||
int32_t clk_prepare_enable(struct clk *clk);
|
||||
uint32_t clk_get_rate(struct ad9361_rf_phy *phy,
|
||||
struct refclk_scale *clk_priv);
|
||||
int32_t clk_set_rate(struct ad9361_rf_phy *phy,
|
||||
struct refclk_scale *clk_priv,
|
||||
uint32_t rate);
|
||||
uint32_t int_sqrt(uint32_t x);
|
||||
int32_t ilog2(int32_t x);
|
||||
uint32_t find_first_bit(uint32_t word);
|
||||
void * ERR_PTR(long error);
|
||||
void *zmalloc(size_t size);
|
||||
|
||||
#endif
|
||||
+66
@@ -0,0 +1,66 @@
|
||||
/***************************************************************************//**
|
||||
* @file common.h
|
||||
* @brief Header file of Common Driver.
|
||||
* @author DBogdan (dragos.bogdan@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2013(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
#ifndef COMMON_H_
|
||||
#define COMMON_H_
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
#include <stdint.h>
|
||||
#include "../../../include/error.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/*************************** Types Declarations *******************************/
|
||||
/******************************************************************************/
|
||||
#if defined (__STDC__) && (__STDC_VERSION__ >= 199901L)
|
||||
#include <stdbool.h>
|
||||
#else
|
||||
typedef enum { false, true } bool;
|
||||
#endif
|
||||
|
||||
struct clk {
|
||||
const char *name;
|
||||
uint32_t rate;
|
||||
};
|
||||
|
||||
struct clk_hw {
|
||||
struct clk *clk;
|
||||
};
|
||||
|
||||
#endif
|
||||
+151
@@ -0,0 +1,151 @@
|
||||
/***************************************************************************//**
|
||||
* @file ad9361_reg.c
|
||||
* @brief Implementation of AD9680 Driver.
|
||||
* @author DBogdan (dragos.bogdan@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2014-2016(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
#include "ad9361_reg.h"
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <stdio.h>
|
||||
#include "../../../include/error.h"
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief ad9361_reg_read
|
||||
*******************************************************************************/
|
||||
int32_t ad9361_reg_read(struct ad9361_reg_dev *dev,
|
||||
uint16_t reg_addr,
|
||||
uint8_t *reg_data)
|
||||
{
|
||||
uint8_t tx_buf[2];
|
||||
uint8_t rx_buf[1];
|
||||
int32_t ret;
|
||||
|
||||
tx_buf[0] = reg_addr >> 8;
|
||||
tx_buf[1] = reg_addr & 0xFF;
|
||||
|
||||
|
||||
ret = spi_write_and_read_3wire(dev->spi_desc,
|
||||
tx_buf, rx_buf, 2, 1);
|
||||
|
||||
*reg_data = rx_buf[0];
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief ad9361_reg_write
|
||||
*******************************************************************************/
|
||||
int32_t ad9361_reg_write(struct ad9361_reg_dev *dev,
|
||||
uint16_t reg_addr,
|
||||
uint8_t reg_data)
|
||||
{
|
||||
uint8_t buf[3];
|
||||
|
||||
int32_t ret;
|
||||
|
||||
buf[0] = 0x80 | reg_addr >> 8;
|
||||
buf[1] = reg_addr & 0xFF;
|
||||
buf[2] = reg_data;
|
||||
|
||||
ret = spi_write_and_read_3wire(dev->spi_desc,
|
||||
buf, NULL, 3, 0);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief ad9361_reg_init
|
||||
*******************************************************************************/
|
||||
int32_t ad9361_reg_init(struct ad9361_reg_dev **device,
|
||||
const struct ad9361_reg_init_param *init_param)
|
||||
{
|
||||
int ret = SUCCESS;
|
||||
struct ad9361_reg_dev *dev;
|
||||
|
||||
dev = (struct ad9361_reg_dev *)malloc(sizeof(*dev));
|
||||
if (!dev)
|
||||
return FAILURE;
|
||||
|
||||
/* SPI */
|
||||
ret = spi_init(&dev->spi_desc, init_param->spi_init);
|
||||
ret |= gpio_get(&dev->gpio_desc_resetb, init_param->gpio_resetb);
|
||||
|
||||
gpio_direction_output(dev->gpio_desc_resetb, 0);
|
||||
|
||||
ad9361_reg_reset(dev);
|
||||
|
||||
*device = dev;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* AD9361 Device Reset
|
||||
* @param phy The AD9361 state structure.
|
||||
* @return 0 in case of success, negative error code otherwise.
|
||||
*/
|
||||
int32_t ad9361_reg_reset(struct ad9361_reg_dev *dev)
|
||||
{
|
||||
if (dev->gpio_desc_resetb) {
|
||||
gpio_set_value(dev->gpio_desc_resetb, 0);
|
||||
mdelay(10);
|
||||
gpio_set_value(dev->gpio_desc_resetb, 1);
|
||||
mdelay(10);
|
||||
return 0;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief Free the resources allocated by ad9361_reg_setup().
|
||||
*
|
||||
* @param dev - The device structure.
|
||||
*
|
||||
* @return SUCCESS in case of success, negative error code otherwise.
|
||||
*******************************************************************************/
|
||||
int32_t ad9361_reg_remove(struct ad9361_reg_dev *dev)
|
||||
{
|
||||
int32_t ret;
|
||||
|
||||
ret = spi_remove(dev->spi_desc);
|
||||
|
||||
free(dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
+104
@@ -0,0 +1,104 @@
|
||||
/***************************************************************************//**
|
||||
* @file ad9361_reg.h
|
||||
* @brief Header file of ad9361_reg Driver.
|
||||
* @author DBogdan (dragos.bogdan@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2014-2016(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
#ifndef ad9361_reg_H_
|
||||
#define ad9361_reg_H_
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
#include <stdint.h>
|
||||
#include "../../../include/delay.h"
|
||||
#include "../../../include/spi.h"
|
||||
#include "../../../include/gpio.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/********************** Macros and Constants Definitions **********************/
|
||||
/******************************************************************************/
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/*************************** Types Declarations *******************************/
|
||||
/******************************************************************************/
|
||||
struct ad9361_reg_dev {
|
||||
/* SPI */
|
||||
spi_desc *spi_desc;
|
||||
gpio_desc *gpio_desc_resetb;
|
||||
};
|
||||
|
||||
struct ad9361_reg_init_param {
|
||||
/* SPI */
|
||||
spi_init_param *spi_init;
|
||||
gpio_init_param *gpio_resetb;
|
||||
};
|
||||
|
||||
enum Operation_Type{
|
||||
AD9361_WRITE,
|
||||
AD9361_READ,
|
||||
AD9361_WAIT,
|
||||
AD9361_WHEN
|
||||
};
|
||||
|
||||
struct ad9361_reg_config {
|
||||
int operation;
|
||||
uint16_t val1;
|
||||
uint16_t val2;
|
||||
};
|
||||
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/************************ Functions Declarations ******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
int32_t ad9361_reg_read(struct ad9361_reg_dev *dev,
|
||||
uint16_t reg_addr,
|
||||
uint8_t *reg_data);
|
||||
|
||||
int32_t ad9361_reg_write(struct ad9361_reg_dev *dev,
|
||||
uint16_t reg_addr,
|
||||
uint8_t reg_data);
|
||||
|
||||
int32_t ad9361_reg_init(struct ad9361_reg_dev **device,
|
||||
const struct ad9361_reg_init_param *init_param);
|
||||
|
||||
int32_t ad9361_reg_reset(struct ad9361_reg_dev *dev);
|
||||
|
||||
int32_t ad9361_reg_remove(struct ad9361_reg_dev *dev);
|
||||
|
||||
#endif
|
||||
+59
@@ -0,0 +1,59 @@
|
||||
/***************************************************************************//**
|
||||
* @file axi_io.h
|
||||
* @brief Header file of AXI IO.
|
||||
* @author Antoniu Miclaus (antoniu.miclaus@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2019(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef AXI_IO_H_
|
||||
#define AXI_IO_H_
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/******************************************************************************/
|
||||
/************************ Functions Declarations ******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/* AXI IO Read data */
|
||||
int32_t axi_io_read(uint32_t base, uint32_t offset, uint32_t *data);
|
||||
|
||||
/* AXI IO Write data */
|
||||
int32_t axi_io_write(uint32_t base, uint32_t offset, uint32_t data);
|
||||
|
||||
#endif // AXI_IO_H_
|
||||
+59
@@ -0,0 +1,59 @@
|
||||
/***************************************************************************//**
|
||||
* @file delay.h
|
||||
* @brief Header file of Delay functions
|
||||
* @author DBogdan (dragos.bogdan@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2019(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef DELAY_H_
|
||||
#define DELAY_H_
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/******************************************************************************/
|
||||
/************************ Functions Declarations ******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/* Generate microseconds delay. */
|
||||
void udelay(uint32_t usecs);
|
||||
|
||||
/* Generate miliseconds delay. */
|
||||
void mdelay(uint32_t msecs);
|
||||
|
||||
#endif // DELAY_H_
|
||||
+67
@@ -0,0 +1,67 @@
|
||||
/***************************************************************************//**
|
||||
* @file error.h
|
||||
* @brief Error codes definition
|
||||
* @author DBogdan (dragos.bogdan@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2019(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef ERROR_H_
|
||||
#define ERROR_H_
|
||||
|
||||
#include <errno.h>
|
||||
|
||||
/******************************************************************************/
|
||||
/********************** Macros and Constants Definitions **********************/
|
||||
/******************************************************************************/
|
||||
|
||||
#ifdef SUCCESS
|
||||
#undef SUCCESS
|
||||
#endif
|
||||
#define SUCCESS 0
|
||||
#ifdef FAILURE
|
||||
#undef FAILURE
|
||||
#endif
|
||||
#define FAILURE -1
|
||||
|
||||
#ifndef __ELASTERROR
|
||||
#define __ELASTERROR 2000
|
||||
#endif
|
||||
|
||||
#define EOVERRUN (__ELASTERROR + 1) /* Circular buffer overrun */
|
||||
|
||||
|
||||
#define IS_ERR_VALUE(x) ((x) < 0)
|
||||
|
||||
#endif // ERROR_H_
|
||||
+165
@@ -0,0 +1,165 @@
|
||||
/***************************************************************************//**
|
||||
* @file gpio.h
|
||||
* @brief Header file of GPIO Interface
|
||||
* @author DBogdan (dragos.bogdan@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2019(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef GPIO_H_
|
||||
#define GPIO_H_
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/******************************************************************************/
|
||||
/********************** Macros and Constants Definitions **********************/
|
||||
/******************************************************************************/
|
||||
|
||||
#define GPIO_OUT 0x01
|
||||
#define GPIO_IN 0x00
|
||||
|
||||
/******************************************************************************/
|
||||
/*************************** Types Declarations *******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @struct gpio_platform_ops
|
||||
* @brief Structure holding gpio function pointers that point to the platform
|
||||
* specific function
|
||||
*/
|
||||
struct gpio_platform_ops ;
|
||||
|
||||
/**
|
||||
* @struct gpio_init_param
|
||||
* @brief Structure holding the parameters for GPIO initialization.
|
||||
*/
|
||||
typedef struct gpio_init_param {
|
||||
/** GPIO number */
|
||||
int32_t number;
|
||||
/** GPIO platform specific functions */
|
||||
const struct gpio_platform_ops *platform_ops;
|
||||
/** GPIO extra parameters (device specific) */
|
||||
void *extra;
|
||||
} gpio_init_param;
|
||||
|
||||
/**
|
||||
* @struct gpio_desc
|
||||
* @brief Structure holding the GPIO descriptor.
|
||||
*/
|
||||
typedef struct gpio_desc {
|
||||
/** GPIO number */
|
||||
int32_t number;
|
||||
/** GPIO platform specific functions */
|
||||
const struct gpio_platform_ops *platform_ops;
|
||||
/** GPIO extra parameters (device specific) */
|
||||
void *extra;
|
||||
} gpio_desc;
|
||||
|
||||
/**
|
||||
* @enum gpio_values
|
||||
* @brief Enum that holds the possible output states of a GPIO.
|
||||
*/
|
||||
enum gpio_values {
|
||||
/** GPIO logic low */
|
||||
GPIO_LOW,
|
||||
/** GPIO logic high */
|
||||
GPIO_HIGH,
|
||||
/** GPIO high impedance */
|
||||
GPIO_HIGH_Z
|
||||
};
|
||||
|
||||
/**
|
||||
* @struct gpio_platform_ops
|
||||
* @brief Structure holding gpio function pointers that point to the platform
|
||||
* specific function
|
||||
*/
|
||||
struct gpio_platform_ops {
|
||||
/** gpio initialization function pointer */
|
||||
int32_t (*gpio_ops_get)(struct gpio_desc **, const struct gpio_init_param *);
|
||||
/** gpio optional descriptor function pointer */
|
||||
int32_t (*gpio_ops_get_optional)(struct gpio_desc **,
|
||||
const struct gpio_init_param *);
|
||||
/** gpio remove function pointer */
|
||||
int32_t (*gpio_ops_remove)(struct gpio_desc *);
|
||||
/** gpio direction input function pointer */
|
||||
int32_t (*gpio_ops_direction_input)(struct gpio_desc *);
|
||||
/** gpio direction output function pointer */
|
||||
int32_t (*gpio_ops_direction_output)(struct gpio_desc *, uint8_t);
|
||||
/** gpio get direction function pointer */
|
||||
int32_t (*gpio_ops_get_direction)(struct gpio_desc *, uint8_t *);
|
||||
/** gpio set value function pointer */
|
||||
int32_t (*gpio_ops_set_value)(struct gpio_desc *, uint8_t);
|
||||
/** gpio get value function pointer */
|
||||
int32_t (*gpio_ops_get_value)(struct gpio_desc *, uint8_t *);
|
||||
};
|
||||
|
||||
/******************************************************************************/
|
||||
/************************ Functions Declarations ******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/* Obtain the GPIO decriptor. */
|
||||
int32_t gpio_get(struct gpio_desc **desc,
|
||||
const struct gpio_init_param *param);
|
||||
|
||||
/* Obtain optional GPIO descriptor. */
|
||||
int32_t gpio_get_optional(struct gpio_desc **desc,
|
||||
const struct gpio_init_param *param);
|
||||
|
||||
/* Free the resources allocated by gpio_get() */
|
||||
int32_t gpio_remove(struct gpio_desc *desc);
|
||||
|
||||
/* Enable the input direction of the specified GPIO. */
|
||||
int32_t gpio_direction_input(struct gpio_desc *desc);
|
||||
|
||||
/* Enable the output direction of the specified GPIO. */
|
||||
int32_t gpio_direction_output(struct gpio_desc *desc,
|
||||
uint8_t value);
|
||||
|
||||
/* Get the direction of the specified GPIO. */
|
||||
int32_t gpio_get_direction(struct gpio_desc *desc,
|
||||
uint8_t *direction);
|
||||
|
||||
/* Set the value of the specified GPIO. */
|
||||
int32_t gpio_set_value(struct gpio_desc *desc,
|
||||
uint8_t value);
|
||||
|
||||
/* Get the value of the specified GPIO. */
|
||||
int32_t gpio_get_value(struct gpio_desc *desc,
|
||||
uint8_t *value);
|
||||
|
||||
#endif // GPIO_H_
|
||||
+188
@@ -0,0 +1,188 @@
|
||||
/***************************************************************************//**
|
||||
* @file irq.h
|
||||
* @brief Header file of IRQ interface.
|
||||
* @author Cristian Pop (cristian.pop@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2019(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef IRQ_H_
|
||||
#define IRQ_H_
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/******************************************************************************/
|
||||
/*************************** Types Declarations *******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @enum irq_uart_event_e
|
||||
* @brief Possible events for uart interrupt
|
||||
*/
|
||||
enum irq_uart_event_e {
|
||||
/** Write operation finalized */
|
||||
IRQ_WRITE_DONE,
|
||||
/** Read operation finalized */
|
||||
IRQ_READ_DONE,
|
||||
/** An error occurred */
|
||||
IRQ_ERROR
|
||||
};
|
||||
|
||||
enum irq_trig_level {
|
||||
IRQ_LEVEL_LOW,
|
||||
IRQ_LEVEL_HIGH,
|
||||
IRQ_EDGE_FALLING,
|
||||
IRQ_EDGE_RISING,
|
||||
IRQ_EDGE_BOTH
|
||||
};
|
||||
|
||||
/**
|
||||
* @struct irq_platform_ops
|
||||
* @brief Structure holding IRQ function pointers that point to the platform
|
||||
* specific function
|
||||
*/
|
||||
struct irq_platform_ops ;
|
||||
|
||||
/**
|
||||
* @struct irq_init_param
|
||||
* @brief Structure holding the initial parameters for Interrupt Request.
|
||||
*/
|
||||
struct irq_init_param {
|
||||
/** Interrupt request controller ID. */
|
||||
uint32_t irq_ctrl_id;
|
||||
/** Platform specific IRQ platform ops structure. */
|
||||
const struct irq_platform_ops *platform_ops;
|
||||
/** IRQ extra parameters (device specific) */
|
||||
void *extra;
|
||||
};
|
||||
|
||||
/**
|
||||
* @struct irq_desc
|
||||
* @brief Structure for Interrupt Request descriptor.
|
||||
*/
|
||||
struct irq_ctrl_desc {
|
||||
/** Interrupt request controller ID. */
|
||||
uint32_t irq_ctrl_id;
|
||||
/** Platform specific IRQ platform ops structure. */
|
||||
const struct irq_platform_ops *platform_ops;
|
||||
/** IRQ extra parameters (device specific) */
|
||||
void *extra;
|
||||
};
|
||||
|
||||
/**
|
||||
* @struct callback_desc
|
||||
* @brief Structure describing a callback to be registered
|
||||
*/
|
||||
struct callback_desc {
|
||||
/**
|
||||
* Callback to be called when the event an event occurs
|
||||
* @param ctx - Same as \ref callback_desc.ctx
|
||||
* @param event - Event that generated the callback
|
||||
* @param extra - Platform specific data
|
||||
*/
|
||||
void (*callback)(void *ctx, uint32_t event, void *extra);
|
||||
/** Parameter to be passed when the callback is called */
|
||||
void *ctx;
|
||||
/** Platform specific configuration for a callback */
|
||||
void *config;
|
||||
};
|
||||
|
||||
/**
|
||||
* @struct irq_platform_ops
|
||||
* @brief Structure holding IRQ function pointers that point to the platform
|
||||
* specific function
|
||||
*/
|
||||
struct irq_platform_ops {
|
||||
/** Initialize a interrupt controller peripheral. */
|
||||
int32_t (*init)(struct irq_ctrl_desc **desc,
|
||||
const struct irq_init_param *param);
|
||||
/** Register a callback to handle the irq events */
|
||||
int32_t (*register_callback)(struct irq_ctrl_desc *desc, uint32_t irq_id,
|
||||
struct callback_desc *callback_desc);
|
||||
/** Unregisters a generic IRQ handling function */
|
||||
int32_t (*unregister)(struct irq_ctrl_desc *desc, uint32_t irq_id);
|
||||
/** Global interrupt enable */
|
||||
int32_t (*global_enable)(struct irq_ctrl_desc *desc);
|
||||
/** Global interrupt disable */
|
||||
int32_t (*global_disable)(struct irq_ctrl_desc *desc);
|
||||
/** Set interrupt trigger level. */
|
||||
int32_t (*trigger_level_set)(struct irq_ctrl_desc *desc, uint32_t irq_id,
|
||||
enum irq_trig_level trig);
|
||||
/** Enable specific interrupt */
|
||||
int32_t (*enable)(struct irq_ctrl_desc *desc, uint32_t irq_id);
|
||||
/** Disable specific interrupt */
|
||||
int32_t (*disable)(struct irq_ctrl_desc *desc, uint32_t irq_id);
|
||||
/** IRQ remove function pointer */
|
||||
int32_t (*remove)(struct irq_ctrl_desc *desc);
|
||||
};
|
||||
|
||||
/******************************************************************************/
|
||||
/************************ Functions Declarations ******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/* Initialize a interrupt controller peripheral. */
|
||||
int32_t irq_ctrl_init(struct irq_ctrl_desc **desc,
|
||||
const struct irq_init_param *param);
|
||||
|
||||
/* Free the resources allocated by irq_ctrl_init(). */
|
||||
int32_t irq_ctrl_remove(struct irq_ctrl_desc *desc);
|
||||
|
||||
/* Register a callback to handle the irq events */
|
||||
int32_t irq_register_callback(struct irq_ctrl_desc *desc, uint32_t irq_id,
|
||||
struct callback_desc *callback_desc);
|
||||
|
||||
/* Unregisters a generic IRQ handling function */
|
||||
int32_t irq_unregister(struct irq_ctrl_desc *desc, uint32_t irq_id);
|
||||
|
||||
/* Global interrupt enable */
|
||||
int32_t irq_global_enable(struct irq_ctrl_desc *desc);
|
||||
|
||||
/* Global interrupt disable */
|
||||
int32_t irq_global_disable(struct irq_ctrl_desc *desc);
|
||||
|
||||
/* Set interrupt trigger level. */
|
||||
int32_t irq_trigger_level_set(struct irq_ctrl_desc *desc, uint32_t irq_id,
|
||||
enum irq_trig_level trig);
|
||||
|
||||
/* Enable specific interrupt */
|
||||
int32_t irq_enable(struct irq_ctrl_desc *desc, uint32_t irq_id);
|
||||
|
||||
/* Disable specific interrupt */
|
||||
int32_t irq_disable(struct irq_ctrl_desc *desc, uint32_t irq_id);
|
||||
|
||||
#endif // IRQ_H_
|
||||
+194
@@ -0,0 +1,194 @@
|
||||
/***************************************************************************//**
|
||||
* @file spi.h
|
||||
* @brief Header file of SPI Interface
|
||||
* @author DBogdan (dragos.bogdan@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2019(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef SPI_H_
|
||||
#define SPI_H_
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/******************************************************************************/
|
||||
/********************** Macros and Constants Definitions **********************/
|
||||
/******************************************************************************/
|
||||
|
||||
#define SPI_CPHA 0x01
|
||||
#define SPI_CPOL 0x02
|
||||
#define SPI_3WIRE 0x04
|
||||
|
||||
/******************************************************************************/
|
||||
/*************************** Types Declarations *******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @enum spi_mode
|
||||
* @brief SPI configuration for clock phase and polarity.
|
||||
*/
|
||||
typedef enum spi_mode {
|
||||
/** Data on rising, shift out on falling */
|
||||
SPI_MODE_0 = (0 | 0),
|
||||
/** Data on falling, shift out on rising */
|
||||
SPI_MODE_1 = (0 | SPI_CPHA),
|
||||
/** Data on falling, shift out on rising */
|
||||
SPI_MODE_2 = (SPI_CPOL | 0),
|
||||
/** Data on rising, shift out on falling */
|
||||
SPI_MODE_3 = (SPI_CPOL | SPI_CPHA),
|
||||
/** Data on rising, shift out on falling */
|
||||
SPI_MODE_4 = SPI_3WIRE
|
||||
} spi_mode;
|
||||
|
||||
/**
|
||||
* @enum spi_bit_order
|
||||
* @brief SPI configuration for bit order (MSB/LSB).
|
||||
*/
|
||||
typedef enum spi_bit_order {
|
||||
/** Most-significant bit (MSB) first */
|
||||
SPI_BIT_ORDER_MSB_FIRST = 0,
|
||||
/** Least-significant bit (LSB) first */
|
||||
SPI_BIT_ORDER_LSB_FIRST = 1,
|
||||
} spi_bit_order;
|
||||
|
||||
/**
|
||||
* @struct spi_msg_list
|
||||
* @brief List item describing a SPI transfer
|
||||
*/
|
||||
struct spi_msg {
|
||||
/** Buffer with data to send. If NULL, 0x00 will be sent */
|
||||
uint8_t *tx_buff;
|
||||
/** Buffer where to store data. If NULL, incoming data won't be saved */
|
||||
uint8_t *rx_buff;
|
||||
/** Length of buffers. Must have equal size. */
|
||||
uint32_t bytes_number;
|
||||
/** If set, CS will be deasserted after the transfer */
|
||||
uint8_t cs_change;
|
||||
};
|
||||
|
||||
/**
|
||||
* @struct spi_platform_ops
|
||||
* @brief Structure holding SPI function pointers that point to the platform
|
||||
* specific function
|
||||
*/
|
||||
struct spi_platform_ops ;
|
||||
|
||||
/**
|
||||
* @struct spi_init_param
|
||||
* @brief Structure holding the parameters for SPI initialization
|
||||
*/
|
||||
typedef struct spi_init_param {
|
||||
/** Device ID */
|
||||
uint32_t device_id;
|
||||
/** maximum transfer speed */
|
||||
uint32_t max_speed_hz;
|
||||
/** SPI chip select */
|
||||
uint8_t chip_select;
|
||||
/** SPI mode */
|
||||
enum spi_mode mode;
|
||||
/** SPI bit order */
|
||||
enum spi_bit_order bit_order;
|
||||
const struct spi_platform_ops *platform_ops;
|
||||
/** SPI extra parameters (device specific) */
|
||||
void *extra;
|
||||
} spi_init_param;
|
||||
|
||||
/**
|
||||
* @struct spi_desc
|
||||
* @brief Structure holding SPI descriptor.
|
||||
*/
|
||||
typedef struct spi_desc {
|
||||
/** Device ID */
|
||||
uint32_t device_id;
|
||||
/** maximum transfer speed */
|
||||
uint32_t max_speed_hz;
|
||||
/** SPI chip select */
|
||||
uint8_t chip_select;
|
||||
/** SPI mode */
|
||||
enum spi_mode mode;
|
||||
/** SPI bit order */
|
||||
enum spi_bit_order bit_order;
|
||||
const struct spi_platform_ops *platform_ops;
|
||||
/** SPI extra parameters (device specific) */
|
||||
void *extra;
|
||||
} spi_desc;
|
||||
|
||||
/**
|
||||
* @struct spi_platform_ops
|
||||
* @brief Structure holding SPI function pointers that point to the platform
|
||||
* specific function
|
||||
*/
|
||||
struct spi_platform_ops {
|
||||
/** SPI initialization function pointer */
|
||||
int32_t (*init)(struct spi_desc **, const struct spi_init_param *);
|
||||
/** SPI write/read function pointer */
|
||||
int32_t (*write_and_read)(struct spi_desc *, uint8_t *, uint16_t);
|
||||
/** SPI write function pointer */
|
||||
int32_t (*write_and_read_3wire)(struct spi_desc *, uint8_t *,uint8_t *,uint16_t, uint16_t);
|
||||
/** Iterate over the spi_msg array and send all messages at once */
|
||||
int32_t (*transfer)(struct spi_desc *, struct spi_msg *, uint32_t);
|
||||
/** SPI remove function pointer */
|
||||
int32_t (*remove)(struct spi_desc *);
|
||||
};
|
||||
|
||||
/******************************************************************************/
|
||||
/************************ Functions Declarations ******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/* Initialize the SPI communication peripheral. */
|
||||
int32_t spi_init(struct spi_desc **desc,
|
||||
const struct spi_init_param *param);
|
||||
|
||||
/* Free the resources allocated by spi_init(). */
|
||||
int32_t spi_remove(struct spi_desc *desc);
|
||||
|
||||
/* Write and read data to/from SPI. */
|
||||
int32_t spi_write_and_read(struct spi_desc *desc,
|
||||
uint8_t *data,
|
||||
uint16_t bytes_number);
|
||||
int32_t spi_write_and_read_3wire(struct spi_desc *desc,
|
||||
uint8_t *write_data,
|
||||
uint8_t *read_data,
|
||||
uint16_t write_bytes_number,
|
||||
uint16_t read_bytes_number);
|
||||
|
||||
/* Iterate over the spi_msg array and send all messages at once */
|
||||
int32_t spi_transfer(struct spi_desc *desc, struct spi_msg *msgs, uint32_t len);
|
||||
|
||||
|
||||
#endif // SPI_H_
|
||||
+165
@@ -0,0 +1,165 @@
|
||||
/***************************************************************************//**
|
||||
* @file util.h
|
||||
* @brief Implementation of utility functions.
|
||||
* @author DBogdan (dragos.bogdan@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2018(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
#ifndef UTIL_H_
|
||||
#define UTIL_H_
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include <stdbool.h>
|
||||
/******************************************************************************/
|
||||
/********************** Macros and Constants Definitions **********************/
|
||||
/******************************************************************************/
|
||||
#define BIT(x) (1 << (x))
|
||||
|
||||
#define ARRAY_SIZE(x) \
|
||||
(sizeof(x) / sizeof((x)[0]))
|
||||
|
||||
#define DIV_ROUND_UP(x,y) \
|
||||
(((x) + (y) - 1) / (y))
|
||||
#define DIV_ROUND_CLOSEST(x, y) \
|
||||
(((x) + (y) / 2) / (y))
|
||||
#define DIV_ROUND_CLOSEST_ULL(x, y) \
|
||||
DIV_ROUND_CLOSEST(x, y)
|
||||
|
||||
#define min(x, y) \
|
||||
(((x) < (y)) ? (x) : (y))
|
||||
#define min_t(type, x, y) \
|
||||
(type)min((type)(x), (type)(y))
|
||||
|
||||
#define max(x, y) \
|
||||
(((x) > (y)) ? (x) : (y))
|
||||
#define max_t(type, x, y) \
|
||||
(type)max((type)(x), (type)(y))
|
||||
|
||||
#define clamp(val, min_val, max_val) \
|
||||
(max(min((val), (max_val)), (min_val)))
|
||||
#define clamp_t(type, val, min_val, max_val) \
|
||||
(type)clamp((type)(val), (type)(min_val), (type)(max_val))
|
||||
|
||||
#define swap(x, y) \
|
||||
{typeof(x) _tmp_ = (x); (x) = (y); (y) = _tmp_;}
|
||||
|
||||
#define round_up(x,y) \
|
||||
(((x)+(y)-1)/(y))
|
||||
|
||||
#define BITS_PER_LONG 32
|
||||
|
||||
#define GENMASK(h, l) ({ \
|
||||
uint32_t t = (uint32_t)(~0UL); \
|
||||
t = t << (BITS_PER_LONG - (h - l + 1)); \
|
||||
t = t >> (BITS_PER_LONG - (h + 1)); \
|
||||
t; \
|
||||
})
|
||||
|
||||
#define bswap_constant_32(x) \
|
||||
((((x) & 0xff000000) >> 24) | (((x) & 0x00ff0000) >> 8) | \
|
||||
(((x) & 0x0000ff00) << 8) | (((x) & 0x000000ff) << 24))
|
||||
|
||||
#define bswap_constant_16(x) ((((x) & (uint16_t)0xff00) >> 8) | \
|
||||
(((x) & (uint16_t)0x00ff) << 8))
|
||||
|
||||
#define bit_swap_constant_8(x) \
|
||||
((((x) & 0x80) >> 7) | \
|
||||
(((x) & 0x40) >> 5) | \
|
||||
(((x) & 0x20) >> 3) | \
|
||||
(((x) & 0x10) >> 1) | \
|
||||
(((x) & 0x08) << 1) | \
|
||||
(((x) & 0x04) << 3) | \
|
||||
(((x) & 0x02) << 5) | \
|
||||
(((x) & 0x01) << 7))
|
||||
|
||||
#define U16_MAX ((uint16_t)~0U)
|
||||
#define S16_MAX ((int16_t)(U16_MAX>>1))
|
||||
|
||||
#define DIV_U64(x, y) (x / y)
|
||||
|
||||
#define UNUSED_PARAM(x) ((void)x)
|
||||
|
||||
#define shift_right(x, s) ((x) < 0 ? -(-(x) >> (s)) : (x) >> (s))
|
||||
|
||||
/******************************************************************************/
|
||||
/************************ Functions Declarations ******************************/
|
||||
/******************************************************************************/
|
||||
/* Find first set bit in word. */
|
||||
uint32_t find_first_set_bit(uint32_t word);
|
||||
/* Find last set bit in word. */
|
||||
uint32_t find_last_set_bit(uint32_t word);
|
||||
/* Locate the closest element in an array. */
|
||||
uint32_t find_closest(int32_t val,
|
||||
const int32_t *array,
|
||||
uint32_t size);
|
||||
/* Shift the value and apply the specified mask. */
|
||||
uint32_t field_prep(uint32_t mask, uint32_t val);
|
||||
/* Get a field specified by a mask from a word. */
|
||||
uint32_t field_get(uint32_t mask, uint32_t word);
|
||||
/* Log base 2 of the given number. */
|
||||
int32_t log_base_2(uint32_t x);
|
||||
/* Find greatest common divisor of the given two numbers. */
|
||||
uint32_t greatest_common_divisor(uint32_t a,
|
||||
uint32_t b);
|
||||
/* Calculate best rational approximation for a given fraction. */
|
||||
void rational_best_approximation(uint32_t given_numerator,
|
||||
uint32_t given_denominator,
|
||||
uint32_t max_numerator,
|
||||
uint32_t max_denominator,
|
||||
uint32_t *best_numerator,
|
||||
uint32_t *best_denominator);
|
||||
/* Calculate the number of set bits. */
|
||||
uint32_t hweight8(uint32_t word);
|
||||
/* Calculate the quotient and the remainder of an integer division. */
|
||||
uint64_t do_div(uint64_t* n,
|
||||
uint64_t base);
|
||||
/* Unsigned 64bit divide with 64bit divisor and remainder */
|
||||
uint64_t div64_u64_rem(uint64_t dividend, uint64_t divisor,
|
||||
uint64_t *remainder);
|
||||
/* Unsigned 64bit divide with 32bit divisor with remainder */
|
||||
uint64_t div_u64_rem(uint64_t dividend, uint32_t divisor, uint32_t *remainder);
|
||||
int64_t div_s64_rem(int64_t dividend, int32_t divisor, int32_t *remainder);
|
||||
/* Unsigned 64bit divide with 32bit divisor */
|
||||
uint64_t div_u64(uint64_t dividend, uint32_t divisor);
|
||||
int64_t div_s64(int64_t dividend, int32_t divisor);
|
||||
/* Converts from string to int32_t */
|
||||
int32_t str_to_int32(const char *str);
|
||||
/* Converts from string to uint32_t */
|
||||
uint32_t srt_to_uint32(const char *str);
|
||||
#endif // UTIL_H_
|
||||
|
||||
+283
@@ -0,0 +1,283 @@
|
||||
/***************************************************************************//**
|
||||
* @file util.c
|
||||
* @brief Implementation of utility functions.
|
||||
* @author DBogdan (dragos.bogdan@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2018(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
#include <string.h>
|
||||
#include <stdlib.h>
|
||||
#include "errno.h"
|
||||
#include "../include/util.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/************************** Functions Implementation **************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* Find first set bit in word.
|
||||
*/
|
||||
uint32_t find_first_set_bit(uint32_t word)
|
||||
{
|
||||
uint32_t first_set_bit = 0;
|
||||
|
||||
while (word) {
|
||||
if (word & 0x1)
|
||||
return first_set_bit;
|
||||
word >>= 1;
|
||||
first_set_bit ++;
|
||||
}
|
||||
|
||||
return 32;
|
||||
}
|
||||
|
||||
/**
|
||||
* Find last set bit in word.
|
||||
*/
|
||||
uint32_t find_last_set_bit(uint32_t word)
|
||||
{
|
||||
uint32_t bit = 0;
|
||||
uint32_t last_set_bit = 32;
|
||||
|
||||
while (word) {
|
||||
if (word & 0x1)
|
||||
last_set_bit = bit;
|
||||
word >>= 1;
|
||||
bit ++;
|
||||
}
|
||||
|
||||
return last_set_bit;
|
||||
}
|
||||
|
||||
/**
|
||||
* Locate the closest element in an array.
|
||||
*/
|
||||
uint32_t find_closest(int32_t val,
|
||||
const int32_t *array,
|
||||
uint32_t size)
|
||||
{
|
||||
int32_t diff = abs(array[0] - val);
|
||||
uint32_t ret = 0;
|
||||
uint32_t i;
|
||||
|
||||
for (i = 1; i < size; i++) {
|
||||
if (abs(array[i] - val) < diff) {
|
||||
diff = abs(array[i] - val);
|
||||
ret = i;
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* Shift the value and apply the specified mask.
|
||||
*/
|
||||
uint32_t field_prep(uint32_t mask, uint32_t val)
|
||||
{
|
||||
return (val << find_first_set_bit(mask)) & mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* Get a field specified by a mask from a word.
|
||||
*/
|
||||
uint32_t field_get(uint32_t mask, uint32_t word)
|
||||
{
|
||||
return (word & mask) >> find_first_set_bit(mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* Log base 2 of the given number.
|
||||
*/
|
||||
int32_t log_base_2(uint32_t x)
|
||||
{
|
||||
return find_last_set_bit(x);
|
||||
}
|
||||
|
||||
/**
|
||||
* Find greatest common divisor of the given two numbers.
|
||||
*/
|
||||
uint32_t greatest_common_divisor(uint32_t a,
|
||||
uint32_t b)
|
||||
{
|
||||
uint32_t div;
|
||||
uint32_t common_div = 1;
|
||||
|
||||
if ((a == 0) || (b == 0))
|
||||
return max(a, b);
|
||||
|
||||
for (div = 1; (div <= a) && (div <= b); div++)
|
||||
if (!(a % div) && !(b % div))
|
||||
common_div = div;
|
||||
|
||||
return common_div;
|
||||
}
|
||||
|
||||
/**
|
||||
* Calculate best rational approximation for a given fraction.
|
||||
*/
|
||||
void rational_best_approximation(uint32_t given_numerator,
|
||||
uint32_t given_denominator,
|
||||
uint32_t max_numerator,
|
||||
uint32_t max_denominator,
|
||||
uint32_t *best_numerator,
|
||||
uint32_t *best_denominator)
|
||||
{
|
||||
uint32_t gcd;
|
||||
|
||||
gcd = greatest_common_divisor(given_numerator, given_denominator);
|
||||
|
||||
*best_numerator = given_numerator / gcd;
|
||||
*best_denominator = given_denominator / gcd;
|
||||
|
||||
if ((*best_numerator > max_numerator) ||
|
||||
(*best_denominator > max_denominator)) {
|
||||
*best_numerator = 0;
|
||||
*best_denominator = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Calculate the number of set bits.
|
||||
*/
|
||||
uint32_t hweight8(uint32_t word)
|
||||
{
|
||||
uint32_t count = 0;
|
||||
|
||||
while (word) {
|
||||
if (word & 0x1)
|
||||
count++;
|
||||
word >>= 1;
|
||||
}
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
/**
|
||||
* Calculate the quotient and the remainder of an integer division.
|
||||
*/
|
||||
uint64_t do_div(uint64_t* n,
|
||||
uint64_t base)
|
||||
{
|
||||
uint64_t mod = 0;
|
||||
|
||||
mod = *n % base;
|
||||
*n = *n / base;
|
||||
|
||||
return mod;
|
||||
}
|
||||
|
||||
/**
|
||||
* Unsigned 64bit divide with 64bit divisor and remainder
|
||||
*/
|
||||
uint64_t div64_u64_rem(uint64_t dividend, uint64_t divisor, uint64_t *remainder)
|
||||
{
|
||||
*remainder = dividend % divisor;
|
||||
|
||||
return dividend / divisor;
|
||||
}
|
||||
|
||||
/**
|
||||
* Unsigned 64bit divide with 32bit divisor with remainder
|
||||
*/
|
||||
uint64_t div_u64_rem(uint64_t dividend, uint32_t divisor, uint32_t *remainder)
|
||||
{
|
||||
*remainder = do_div(÷nd, divisor);
|
||||
|
||||
return dividend;
|
||||
}
|
||||
|
||||
/**
|
||||
* Signed 64bit divide with 32bit divisor with remainder
|
||||
*/
|
||||
int64_t div_s64_rem(int64_t dividend, int32_t divisor, int32_t *remainder)
|
||||
{
|
||||
*remainder = dividend % divisor;
|
||||
return dividend / divisor;
|
||||
}
|
||||
|
||||
/**
|
||||
* Unsigned 64bit divide with 32bit divisor
|
||||
*/
|
||||
uint64_t div_u64(uint64_t dividend, uint32_t divisor)
|
||||
{
|
||||
uint32_t remainder;
|
||||
|
||||
return div_u64_rem(dividend, divisor, &remainder);
|
||||
}
|
||||
|
||||
/**
|
||||
* Signed 64bit divide with 32bit divisor
|
||||
*/
|
||||
int64_t div_s64(int64_t dividend, int32_t divisor)
|
||||
{
|
||||
int32_t remainder;
|
||||
return div_s64_rem(dividend, divisor, &remainder);
|
||||
}
|
||||
|
||||
/**
|
||||
* Converts from string to int32_t
|
||||
* @param *str
|
||||
* @return int32_t
|
||||
*/
|
||||
int32_t str_to_int32(const char *str)
|
||||
{
|
||||
char *end;
|
||||
int32_t value = strtol(str, &end, 0);
|
||||
|
||||
if (end == str)
|
||||
return -EINVAL;
|
||||
else
|
||||
return value;
|
||||
}
|
||||
|
||||
/**
|
||||
* Converts from string to uint32_t
|
||||
* @param *str
|
||||
* @return uint32_t
|
||||
*/
|
||||
uint32_t srt_to_uint32(const char *str)
|
||||
{
|
||||
char *end;
|
||||
uint32_t value = strtoul(str, &end, 0);
|
||||
|
||||
if (end == str)
|
||||
return -EINVAL;
|
||||
else
|
||||
return value;
|
||||
}
|
||||
@@ -1,103 +1,55 @@
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* Description: Global configurations.
|
||||
/***************************************************************************//**
|
||||
* @file app_config.h
|
||||
* @brief Config file of AD9361/API Driver.
|
||||
* @author DBogdan (dragos.bogdan@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2015(c) Analog Devices, Inc.
|
||||
*
|
||||
* Date: 2021-04-28 13:19
|
||||
* Last Edit Time: 2022-05-23 20:32
|
||||
* All rights reserved.
|
||||
*
|
||||
* Revisions: Rev 0.0
|
||||
* History:
|
||||
* [2021-04-28]: Initial edition.
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* Copyright(c) 2021 Beijing Institute of Technology.
|
||||
* Lab of Communication and Networking
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
#ifndef CONFIG_H_
|
||||
#define CONFIG_H_
|
||||
|
||||
#define XILINX_PLATFORM
|
||||
#define SPI_INTERFACE_SPI_ENGINE
|
||||
|
||||
#include "xparameters.h"
|
||||
#include "xparameters_ps.h"
|
||||
#define HAVE_SPLIT_GAIN_TABLE 1 /* only set to 0 in case split_gain_table_mode_enable = 0*/
|
||||
#define HAVE_TDD_SYNTH_TABLE 1 /* only set to 0 in case split_gain_table_mode_enable = 0*/
|
||||
|
||||
|
||||
/********* Zynq Platform Configs **********/
|
||||
#define AD9361_DEVICE 1 /* set it 1 if AD9361 device is used, 0 otherwise */
|
||||
#define AD9364_DEVICE 0 /* set it 1 if AD9364 device is used, 0 otherwise */
|
||||
#define AD9363A_DEVICE 0 /* set it 1 if AD9363A device is used, 0 otherwise */
|
||||
|
||||
#define HAVE_VERBOSE_MESSAGES /* Recommended during development prints errors and warnings */
|
||||
//#define HAVE_DEBUG_MESSAGES /* For Debug purposes only */
|
||||
|
||||
// interrupt controller
|
||||
#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
|
||||
|
||||
// gpio
|
||||
#define GPIO_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
|
||||
#define GPIO_INTR_ID XPS_GPIO_INT_ID
|
||||
#define GPIO_OFFSET 54
|
||||
#define GPIO_INPUT 0
|
||||
#define GPIO_OUTPUT 1
|
||||
#define GPIO_DISABLE 0
|
||||
#define GPIO_ENABLE 1
|
||||
|
||||
// spi
|
||||
#define SPI_DEVICE_ID XPAR_PS7_SPI_0_DEVICE_ID
|
||||
#define SPI_INTR_ID XPS_SPI0_INT_ID
|
||||
|
||||
// hmc7044
|
||||
#define HMC7044_RESET GPIO_OFFSET+0
|
||||
#define HMC7044_SYNC GPIO_OFFSET+1
|
||||
#define HMC7044_GPIO_0 GPIO_OFFSET+2
|
||||
#define HMC7044_GPIO_1 GPIO_OFFSET+3
|
||||
#define HMC7044_GPIO_2 GPIO_OFFSET+4
|
||||
#define HMC7044_GPIO_3 GPIO_OFFSET+5
|
||||
// ad9361-1
|
||||
#define AD9361_1_TXNRX GPIO_OFFSET+6
|
||||
#define AD9361_1_ENABLE GPIO_OFFSET+7
|
||||
#define AD9361_1_EN_AGC GPIO_OFFSET+8
|
||||
#define AD9361_1_RESET_B GPIO_OFFSET+9
|
||||
#define AD9361_1_CTRL_OUT0 GPIO_OFFSET+10
|
||||
#define AD9361_1_CTRL_OUT1 GPIO_OFFSET+11
|
||||
#define AD9361_1_CTRL_OUT2 GPIO_OFFSET+12
|
||||
#define AD9361_1_CTRL_OUT3 GPIO_OFFSET+13
|
||||
#define AD9361_1_CTRL_OUT4 GPIO_OFFSET+14
|
||||
#define AD9361_1_CTRL_OUT5 GPIO_OFFSET+15
|
||||
#define AD9361_1_CTRL_OUT6 GPIO_OFFSET+16
|
||||
#define AD9361_1_CTRL_OUT7 GPIO_OFFSET+17
|
||||
#define AD9361_1_CTRL_IN0 GPIO_OFFSET+18
|
||||
#define AD9361_1_CTRL_IN1 GPIO_OFFSET+19
|
||||
#define AD9361_1_CTRL_IN2 GPIO_OFFSET+20
|
||||
#define AD9361_1_CTRL_IN3 GPIO_OFFSET+21
|
||||
// ad9361-2
|
||||
#define AD9361_2_TXNRX GPIO_OFFSET+22
|
||||
#define AD9361_2_ENABLE GPIO_OFFSET+23
|
||||
#define AD9361_2_EN_AGC GPIO_OFFSET+24
|
||||
#define AD9361_2_RESET_B GPIO_OFFSET+25
|
||||
#define AD9361_2_CTRL_OUT0 GPIO_OFFSET+26
|
||||
#define AD9361_2_CTRL_OUT1 GPIO_OFFSET+27
|
||||
#define AD9361_2_CTRL_OUT2 GPIO_OFFSET+28
|
||||
#define AD9361_2_CTRL_OUT3 GPIO_OFFSET+29
|
||||
#define AD9361_2_CTRL_OUT4 GPIO_OFFSET+30
|
||||
#define AD9361_2_CTRL_OUT5 GPIO_OFFSET+31
|
||||
#define AD9361_2_CTRL_OUT6 GPIO_OFFSET+32
|
||||
#define AD9361_2_CTRL_OUT7 GPIO_OFFSET+33
|
||||
#define AD9361_2_CTRL_IN0 GPIO_OFFSET+34
|
||||
#define AD9361_2_CTRL_IN1 GPIO_OFFSET+35
|
||||
#define AD9361_2_CTRL_IN2 GPIO_OFFSET+36
|
||||
#define AD9361_2_CTRL_IN3 GPIO_OFFSET+37
|
||||
|
||||
#define AD9361_SYNC GPIO_OFFSET+38
|
||||
#define AD9361_RX_FIFO_RST GPIO_OFFSET+39
|
||||
#define AD9361_1_CAL_START GPIO_OFFSET+40
|
||||
#define AD9361_2_CAL_START GPIO_OFFSET+41
|
||||
#define AD9361_RECAL GPIO_OFFSET+42
|
||||
#define AD9361_TX_SWITCH GPIO_OFFSET+44
|
||||
#define AD9361_1_CAL_DONE GPIO_OFFSET+44
|
||||
#define AD9361_2_CAL_DONE GPIO_OFFSET+45
|
||||
#define AD9361_CAL_RESULT GPIO_OFFSET+46
|
||||
|
||||
#define SPI_CS_HMC7044 0x00
|
||||
#define SPI_CS_AD9361_1 0x01
|
||||
#define SPI_CS_AD9361_2 0x02
|
||||
|
||||
#endif
|
||||
|
||||
+325
@@ -0,0 +1,325 @@
|
||||
#include "dev_profile.h"
|
||||
#include "../app_config.h"
|
||||
#include "../adi_noos/drivers/rf-transceiver/ad9361/ad9361_api.h"
|
||||
|
||||
AD9361_InitParam ad9361_default_init_param = {
|
||||
/* Device selection */
|
||||
ID_AD9361, // dev_sel
|
||||
/* Reference Clock */
|
||||
48000000UL, //reference_clk_rate
|
||||
/* Base Configuration */
|
||||
1, //two_rx_two_tx_mode_enable *** adi,2rx-2tx-mode-enable
|
||||
1, //one_rx_one_tx_mode_use_rx_num *** adi,1rx-1tx-mode-use-rx-num
|
||||
1, //one_rx_one_tx_mode_use_tx_num *** adi,1rx-1tx-mode-use-tx-num
|
||||
1, //frequency_division_duplex_mode_enable *** adi,frequency-division-duplex-mode-enable
|
||||
0, //frequency_division_duplex_independent_mode_enable *** adi,frequency-division-duplex-independent-mode-enable
|
||||
0, //tdd_use_dual_synth_mode_enable *** adi,tdd-use-dual-synth-mode-enable
|
||||
0, //tdd_skip_vco_cal_enable *** adi,tdd-skip-vco-cal-enable
|
||||
0, //tx_fastlock_delay_ns *** adi,tx-fastlock-delay-ns
|
||||
0, //rx_fastlock_delay_ns *** adi,rx-fastlock-delay-ns
|
||||
0, //rx_fastlock_pincontrol_enable *** adi,rx-fastlock-pincontrol-enable
|
||||
0, //tx_fastlock_pincontrol_enable *** adi,tx-fastlock-pincontrol-enable
|
||||
0, //external_rx_lo_enable *** adi,external-rx-lo-enable
|
||||
0, //external_tx_lo_enable *** adi,external-tx-lo-enable
|
||||
5, //dc_offset_tracking_update_event_mask *** adi,dc-offset-tracking-update-event-mask
|
||||
6, //dc_offset_attenuation_high_range *** adi,dc-offset-attenuation-high-range
|
||||
5, //dc_offset_attenuation_low_range *** adi,dc-offset-attenuation-low-range
|
||||
0x28, //dc_offset_count_high_range *** adi,dc-offset-count-high-range
|
||||
0x32, //dc_offset_count_low_range *** adi,dc-offset-count-low-range
|
||||
0, //split_gain_table_mode_enable *** adi,split-gain-table-mode-enable
|
||||
MAX_SYNTH_FREF, //trx_synthesizer_target_fref_overwrite_hz *** adi,trx-synthesizer-target-fref-overwrite-hz
|
||||
0, // qec_tracking_slow_mode_enable *** adi,qec-tracking-slow-mode-enable
|
||||
/* ENSM Control */
|
||||
0, //ensm_enable_pin_pulse_mode_enable *** adi,ensm-enable-pin-pulse-mode-enable
|
||||
0, //ensm_enable_txnrx_control_enable *** adi,ensm-enable-txnrx-control-enable
|
||||
/* LO Control */
|
||||
4125000000UL, //rx_synthesizer_frequency_hz *** adi,rx-synthesizer-frequency-hz
|
||||
4126000000UL, //tx_synthesizer_frequency_hz *** adi,tx-synthesizer-frequency-hz
|
||||
1, //tx_lo_powerdown_managed_enable *** adi,tx-lo-powerdown-managed-enable
|
||||
/* Rate & BW Control */
|
||||
{768000000, 192000000, 96000000, 48000000, 24000000, 24000000},// rx_path_clock_frequencies[6] *** adi,rx-path-clock-frequencies
|
||||
{768000000, 192000000, 96000000, 48000000, 24000000, 24000000},// tx_path_clock_frequencies[6] *** adi,tx-path-clock-frequencies
|
||||
18000000,//rf_rx_bandwidth_hz *** adi,rf-rx-bandwidth-hz
|
||||
18000000,//rf_tx_bandwidth_hz *** adi,rf-tx-bandwidth-hz
|
||||
/* RF Port Control */
|
||||
0, //rx_rf_port_input_select *** adi,rx-rf-port-input-select
|
||||
0, //tx_rf_port_input_select *** adi,tx-rf-port-input-select
|
||||
/* TX Attenuation Control */
|
||||
10000, //tx_attenuation_mdB *** adi,tx-attenuation-mdB
|
||||
0, //update_tx_gain_in_alert_enable *** adi,update-tx-gain-in-alert-enable
|
||||
/* Reference Clock Control */
|
||||
0, //xo_disable_use_ext_refclk_enable *** adi,xo-disable-use-ext-refclk-enable
|
||||
{8, 5920}, //dcxo_coarse_and_fine_tune[2] *** adi,dcxo-coarse-and-fine-tune
|
||||
CLKOUT_DISABLE, //clk_output_mode_select *** adi,clk-output-mode-select
|
||||
/* Gain Control */
|
||||
2, //gc_rx1_mode *** adi,gc-rx1-mode
|
||||
2, //gc_rx2_mode *** adi,gc-rx2-mode
|
||||
58, //gc_adc_large_overload_thresh *** adi,gc-adc-large-overload-thresh
|
||||
4, //gc_adc_ovr_sample_size *** adi,gc-adc-ovr-sample-size
|
||||
47, //gc_adc_small_overload_thresh *** adi,gc-adc-small-overload-thresh
|
||||
8192, //gc_dec_pow_measurement_duration *** adi,gc-dec-pow-measurement-duration
|
||||
0, //gc_dig_gain_enable *** adi,gc-dig-gain-enable
|
||||
800, //gc_lmt_overload_high_thresh *** adi,gc-lmt-overload-high-thresh
|
||||
704, //gc_lmt_overload_low_thresh *** adi,gc-lmt-overload-low-thresh
|
||||
24, //gc_low_power_thresh *** adi,gc-low-power-thresh
|
||||
15, //gc_max_dig_gain *** adi,gc-max-dig-gain
|
||||
0, //gc_use_rx_fir_out_for_dec_pwr_meas_enable *** adi,gc-use-rx-fir-out-for-dec-pwr-meas-enable
|
||||
/* Gain MGC Control */
|
||||
2, //mgc_dec_gain_step *** adi,mgc-dec-gain-step
|
||||
2, //mgc_inc_gain_step *** adi,mgc-inc-gain-step
|
||||
0, //mgc_rx1_ctrl_inp_enable *** adi,mgc-rx1-ctrl-inp-enable
|
||||
0, //mgc_rx2_ctrl_inp_enable *** adi,mgc-rx2-ctrl-inp-enable
|
||||
0, //mgc_split_table_ctrl_inp_gain_mode *** adi,mgc-split-table-ctrl-inp-gain-mode
|
||||
/* Gain AGC Control */
|
||||
10, //agc_adc_large_overload_exceed_counter *** adi,agc-adc-large-overload-exceed-counter
|
||||
2, //agc_adc_large_overload_inc_steps *** adi,agc-adc-large-overload-inc-steps
|
||||
0, //agc_adc_lmt_small_overload_prevent_gain_inc_enable *** adi,agc-adc-lmt-small-overload-prevent-gain-inc-enable
|
||||
10, //agc_adc_small_overload_exceed_counter *** adi,agc-adc-small-overload-exceed-counter
|
||||
4, //agc_dig_gain_step_size *** adi,agc-dig-gain-step-size
|
||||
3, //agc_dig_saturation_exceed_counter *** adi,agc-dig-saturation-exceed-counter
|
||||
1000, // agc_gain_update_interval_us *** adi,agc-gain-update-interval-us
|
||||
0, //agc_immed_gain_change_if_large_adc_overload_enable *** adi,agc-immed-gain-change-if-large-adc-overload-enable
|
||||
0, //agc_immed_gain_change_if_large_lmt_overload_enable *** adi,agc-immed-gain-change-if-large-lmt-overload-enable
|
||||
10, //agc_inner_thresh_high *** adi,agc-inner-thresh-high
|
||||
1, //agc_inner_thresh_high_dec_steps *** adi,agc-inner-thresh-high-dec-steps
|
||||
12, //agc_inner_thresh_low *** adi,agc-inner-thresh-low
|
||||
1, //agc_inner_thresh_low_inc_steps *** adi,agc-inner-thresh-low-inc-steps
|
||||
10, //agc_lmt_overload_large_exceed_counter *** adi,agc-lmt-overload-large-exceed-counter
|
||||
2, //agc_lmt_overload_large_inc_steps *** adi,agc-lmt-overload-large-inc-steps
|
||||
10, //agc_lmt_overload_small_exceed_counter *** adi,agc-lmt-overload-small-exceed-counter
|
||||
5, //agc_outer_thresh_high *** adi,agc-outer-thresh-high
|
||||
2, //agc_outer_thresh_high_dec_steps *** adi,agc-outer-thresh-high-dec-steps
|
||||
18, //agc_outer_thresh_low *** adi,agc-outer-thresh-low
|
||||
2, //agc_outer_thresh_low_inc_steps *** adi,agc-outer-thresh-low-inc-steps
|
||||
1, //agc_attack_delay_extra_margin_us; *** adi,agc-attack-delay-extra-margin-us
|
||||
0, //agc_sync_for_gain_counter_enable *** adi,agc-sync-for-gain-counter-enable
|
||||
/* Fast AGC */
|
||||
64, //fagc_dec_pow_measuremnt_duration *** adi,fagc-dec-pow-measurement-duration
|
||||
260, //fagc_state_wait_time_ns *** adi,fagc-state-wait-time-ns
|
||||
/* Fast AGC - Low Power */
|
||||
0, //fagc_allow_agc_gain_increase *** adi,fagc-allow-agc-gain-increase-enable
|
||||
5, //fagc_lp_thresh_increment_time *** adi,fagc-lp-thresh-increment-time
|
||||
1, //fagc_lp_thresh_increment_steps *** adi,fagc-lp-thresh-increment-steps
|
||||
/* Fast AGC - Lock Level (Lock Level is set via slow AGC inner high threshold) */
|
||||
1, //fagc_lock_level_lmt_gain_increase_en *** adi,fagc-lock-level-lmt-gain-increase-enable
|
||||
5, //fagc_lock_level_gain_increase_upper_limit *** adi,fagc-lock-level-gain-increase-upper-limit
|
||||
/* Fast AGC - Peak Detectors and Final Settling */
|
||||
1, //fagc_lpf_final_settling_steps *** adi,fagc-lpf-final-settling-steps
|
||||
1, //fagc_lmt_final_settling_steps *** adi,fagc-lmt-final-settling-steps
|
||||
3, //fagc_final_overrange_count *** adi,fagc-final-overrange-count
|
||||
/* Fast AGC - Final Power Test */
|
||||
0, //fagc_gain_increase_after_gain_lock_en *** adi,fagc-gain-increase-after-gain-lock-enable
|
||||
/* Fast AGC - Unlocking the Gain */
|
||||
0, //fagc_gain_index_type_after_exit_rx_mode *** adi,fagc-gain-index-type-after-exit-rx-mode
|
||||
1, //fagc_use_last_lock_level_for_set_gain_en *** adi,fagc-use-last-lock-level-for-set-gain-enable
|
||||
1, //fagc_rst_gla_stronger_sig_thresh_exceeded_en *** adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable
|
||||
5, //fagc_optimized_gain_offset *** adi,fagc-optimized-gain-offset
|
||||
10, //fagc_rst_gla_stronger_sig_thresh_above_ll *** adi,fagc-rst-gla-stronger-sig-thresh-above-ll
|
||||
1, //fagc_rst_gla_engergy_lost_sig_thresh_exceeded_en *** adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable
|
||||
1, //fagc_rst_gla_engergy_lost_goto_optim_gain_en *** adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable
|
||||
10, //fagc_rst_gla_engergy_lost_sig_thresh_below_ll *** adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll
|
||||
8, //fagc_energy_lost_stronger_sig_gain_lock_exit_cnt *** adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt
|
||||
1, //fagc_rst_gla_large_adc_overload_en *** adi,fagc-rst-gla-large-adc-overload-enable
|
||||
1, //fagc_rst_gla_large_lmt_overload_en *** adi,fagc-rst-gla-large-lmt-overload-enable
|
||||
0, //fagc_rst_gla_en_agc_pulled_high_en *** adi,fagc-rst-gla-en-agc-pulled-high-enable
|
||||
0, //fagc_rst_gla_if_en_agc_pulled_high_mode *** adi,fagc-rst-gla-if-en-agc-pulled-high-mode
|
||||
64, //fagc_power_measurement_duration_in_state5 *** adi,fagc-power-measurement-duration-in-state5
|
||||
2, //fagc_large_overload_inc_steps *** adi,fagc-adc-large-overload-inc-steps
|
||||
/* RSSI Control */
|
||||
1, //rssi_delay *** adi,rssi-delay
|
||||
1000, //rssi_duration *** adi,rssi-duration
|
||||
3, //rssi_restart_mode *** adi,rssi-restart-mode
|
||||
0, //rssi_unit_is_rx_samples_enable *** adi,rssi-unit-is-rx-samples-enable
|
||||
1, //rssi_wait *** adi,rssi-wait
|
||||
/* Aux ADC Control */
|
||||
256, //aux_adc_decimation *** adi,aux-adc-decimation
|
||||
48000000UL, //aux_adc_rate *** adi,aux-adc-rate
|
||||
/* AuxDAC Control */
|
||||
1, //aux_dac_manual_mode_enable *** adi,aux-dac-manual-mode-enable
|
||||
0, //aux_dac1_default_value_mV *** adi,aux-dac1-default-value-mV
|
||||
0, //aux_dac1_active_in_rx_enable *** adi,aux-dac1-active-in-rx-enable
|
||||
0, //aux_dac1_active_in_tx_enable *** adi,aux-dac1-active-in-tx-enable
|
||||
0, //aux_dac1_active_in_alert_enable *** adi,aux-dac1-active-in-alert-enable
|
||||
0, //aux_dac1_rx_delay_us *** adi,aux-dac1-rx-delay-us
|
||||
0, //aux_dac1_tx_delay_us *** adi,aux-dac1-tx-delay-us
|
||||
0, //aux_dac2_default_value_mV *** adi,aux-dac2-default-value-mV
|
||||
0, //aux_dac2_active_in_rx_enable *** adi,aux-dac2-active-in-rx-enable
|
||||
0, //aux_dac2_active_in_tx_enable *** adi,aux-dac2-active-in-tx-enable
|
||||
0, //aux_dac2_active_in_alert_enable *** adi,aux-dac2-active-in-alert-enable
|
||||
0, //aux_dac2_rx_delay_us *** adi,aux-dac2-rx-delay-us
|
||||
0, //aux_dac2_tx_delay_us *** adi,aux-dac2-tx-delay-us
|
||||
/* Temperature Sensor Control */
|
||||
256, //temp_sense_decimation *** adi,temp-sense-decimation
|
||||
1000, //temp_sense_measurement_interval_ms *** adi,temp-sense-measurement-interval-ms
|
||||
0xCE, //temp_sense_offset_signed *** adi,temp-sense-offset-signed
|
||||
1, //temp_sense_periodic_measurement_enable *** adi,temp-sense-periodic-measurement-enable
|
||||
/* Control Out Setup */
|
||||
0xFF, //ctrl_outs_enable_mask *** adi,ctrl-outs-enable-mask
|
||||
0, //ctrl_outs_index *** adi,ctrl-outs-index
|
||||
/* External LNA Control */
|
||||
0, //elna_settling_delay_ns *** adi,elna-settling-delay-ns
|
||||
0, //elna_gain_mdB *** adi,elna-gain-mdB
|
||||
0, //elna_bypass_loss_mdB *** adi,elna-bypass-loss-mdB
|
||||
0, //elna_rx1_gpo0_control_enable *** adi,elna-rx1-gpo0-control-enable
|
||||
0, //elna_rx2_gpo1_control_enable *** adi,elna-rx2-gpo1-control-enable
|
||||
0, //elna_gaintable_all_index_enable *** adi,elna-gaintable-all-index-enable
|
||||
/* Digital Interface Control */
|
||||
0, //digital_interface_tune_skip_mode *** adi,digital-interface-tune-skip-mode
|
||||
0, //digital_interface_tune_fir_disable *** adi,digital-interface-tune-fir-disable
|
||||
1, //pp_tx_swap_enable *** adi,pp-tx-swap-enable
|
||||
1, //pp_rx_swap_enable *** adi,pp-rx-swap-enable
|
||||
0, //tx_channel_swap_enable *** adi,tx-channel-swap-enable
|
||||
0, //rx_channel_swap_enable *** adi,rx-channel-swap-enable
|
||||
1, //rx_frame_pulse_mode_enable *** adi,rx-frame-pulse-mode-enable
|
||||
0, //two_t_two_r_timing_enable *** adi,2t2r-timing-enable
|
||||
0, //invert_data_bus_enable *** adi,invert-data-bus-enable
|
||||
0, //invert_data_clk_enable *** adi,invert-data-clk-enable
|
||||
0, //fdd_alt_word_order_enable *** adi,fdd-alt-word-order-enable
|
||||
0, //invert_rx_frame_enable *** adi,invert-rx-frame-enable
|
||||
0, //fdd_rx_rate_2tx_enable *** adi,fdd-rx-rate-2tx-enable
|
||||
0, //swap_ports_enable *** adi,swap-ports-enable
|
||||
0, //single_data_rate_enable *** adi,single-data-rate-enable
|
||||
1, //lvds_mode_enable *** adi,lvds-mode-enable
|
||||
0, //half_duplex_mode_enable *** adi,half-duplex-mode-enable
|
||||
0, //single_port_mode_enable *** adi,single-port-mode-enable
|
||||
0, //full_port_enable *** adi,full-port-enable
|
||||
0, //full_duplex_swap_bits_enable *** adi,full-duplex-swap-bits-enable
|
||||
0, //delay_rx_data *** adi,delay-rx-data
|
||||
0, //rx_data_clock_delay *** adi,rx-data-clock-delay
|
||||
4, //rx_data_delay *** adi,rx-data-delay
|
||||
7, //tx_fb_clock_delay *** adi,tx-fb-clock-delay
|
||||
0, //tx_data_delay *** adi,tx-data-delay
|
||||
150, //lvds_bias_mV *** adi,lvds-bias-mV
|
||||
1, //lvds_rx_onchip_termination_enable *** adi,lvds-rx-onchip-termination-enable
|
||||
0, //rx1rx2_phase_inversion_en *** adi,rx1-rx2-phase-inversion-enable
|
||||
0xFF, //lvds_invert1_control *** adi,lvds-invert1-control
|
||||
0x0F, //lvds_invert2_control *** adi,lvds-invert2-control
|
||||
/* GPO Control */
|
||||
0, //gpo_manual_mode_enable *** adi,gpo-manual-mode-enable
|
||||
0, //gpo_manual_mode_enable_mask *** adi,gpo-manual-mode-enable-mask
|
||||
0, //gpo0_inactive_state_high_enable *** adi,gpo0-inactive-state-high-enable
|
||||
0, //gpo1_inactive_state_high_enable *** adi,gpo1-inactive-state-high-enable
|
||||
0, //gpo2_inactive_state_high_enable *** adi,gpo2-inactive-state-high-enable
|
||||
0, //gpo3_inactive_state_high_enable *** adi,gpo3-inactive-state-high-enable
|
||||
0, //gpo0_slave_rx_enable *** adi,gpo0-slave-rx-enable
|
||||
0, //gpo0_slave_tx_enable *** adi,gpo0-slave-tx-enable
|
||||
0, //gpo1_slave_rx_enable *** adi,gpo1-slave-rx-enable
|
||||
0, //gpo1_slave_tx_enable *** adi,gpo1-slave-tx-enable
|
||||
0, //gpo2_slave_rx_enable *** adi,gpo2-slave-rx-enable
|
||||
0, //gpo2_slave_tx_enable *** adi,gpo2-slave-tx-enable
|
||||
0, //gpo3_slave_rx_enable *** adi,gpo3-slave-rx-enable
|
||||
0, //gpo3_slave_tx_enable *** adi,gpo3-slave-tx-enable
|
||||
0, //gpo0_rx_delay_us *** adi,gpo0-rx-delay-us
|
||||
0, //gpo0_tx_delay_us *** adi,gpo0-tx-delay-us
|
||||
0, //gpo1_rx_delay_us *** adi,gpo1-rx-delay-us
|
||||
0, //gpo1_tx_delay_us *** adi,gpo1-tx-delay-us
|
||||
0, //gpo2_rx_delay_us *** adi,gpo2-rx-delay-us
|
||||
0, //gpo2_tx_delay_us *** adi,gpo2-tx-delay-us
|
||||
0, //gpo3_rx_delay_us *** adi,gpo3-rx-delay-us
|
||||
0, //gpo3_tx_delay_us *** adi,gpo3-tx-delay-us
|
||||
/* Tx Monitor Control */
|
||||
37000, //low_high_gain_threshold_mdB *** adi,txmon-low-high-thresh
|
||||
0, //low_gain_dB *** adi,txmon-low-gain
|
||||
24, //high_gain_dB *** adi,txmon-high-gain
|
||||
0, //tx_mon_track_en *** adi,txmon-dc-tracking-enable
|
||||
0, //one_shot_mode_en *** adi,txmon-one-shot-mode-enable
|
||||
511, //tx_mon_delay *** adi,txmon-delay
|
||||
8192, //tx_mon_duration *** adi,txmon-duration
|
||||
2, //tx1_mon_front_end_gain *** adi,txmon-1-front-end-gain
|
||||
2, //tx2_mon_front_end_gain *** adi,txmon-2-front-end-gain
|
||||
48, //tx1_mon_lo_cm *** adi,txmon-1-lo-cm
|
||||
48, //tx2_mon_lo_cm *** adi,txmon-2-lo-cm
|
||||
/* GPIO definitions */
|
||||
/* Reset_b */
|
||||
{
|
||||
.number = AD9361_1_RESET_B,
|
||||
.platform_ops = GPIO_OPS,
|
||||
.extra = GPIO_PARAM
|
||||
}, //gpio_resetb *** reset-gpios
|
||||
/* MCS Sync */
|
||||
{
|
||||
.number = -1,
|
||||
.platform_ops = GPIO_OPS,
|
||||
.extra = GPIO_PARAM
|
||||
}, //gpio_sync *** sync-gpios
|
||||
/* Cal-SW1 */
|
||||
{
|
||||
.number = -1,
|
||||
.platform_ops = GPIO_OPS,
|
||||
.extra = GPIO_PARAM
|
||||
}, //gpio_cal_sw1 *** cal-sw1-gpios
|
||||
/* Cal-SW2 */
|
||||
{
|
||||
.number = -1,
|
||||
.platform_ops = GPIO_OPS,
|
||||
.extra = GPIO_PARAM
|
||||
}, //gpio_cal_sw2 *** cal-sw2-gpios
|
||||
|
||||
{
|
||||
.device_id = SPI_DEVICE_ID,
|
||||
.mode = SPI_MODE_1,
|
||||
.chip_select = SPI_CS_AD9361_1,
|
||||
.platform_ops = SPI_OPS,
|
||||
.extra = SPI_PARAM
|
||||
},
|
||||
|
||||
/* External LO clocks */
|
||||
NULL, //(*ad9361_rfpll_ext_recalc_rate)()
|
||||
NULL, //(*ad9361_rfpll_ext_round_rate)()
|
||||
NULL, //(*ad9361_rfpll_ext_set_rate)()
|
||||
};
|
||||
|
||||
AD9361_RXFIRConfig rx_fir_config = { // BPF PASSBAND 3/20 fs to 1/4 fs
|
||||
3, // rx
|
||||
0, // rx_gain
|
||||
1, // rx_dec
|
||||
{
|
||||
-4, -6, -37, 35, 186, 86, -284, -315,
|
||||
107, 219, -4, 271, 558, -307, -1182, -356,
|
||||
658, 157, 207, 1648, 790, -2525, -2553, 748,
|
||||
865, -476, 3737, 6560, -3583, -14731, -5278, 14819,
|
||||
14819, -5278, -14731, -3583, 6560, 3737, -476, 865,
|
||||
748, -2553, -2525, 790, 1648, 207, 157, 658,
|
||||
-356, -1182, -307, 558, 271, -4, 219, 107,
|
||||
-315, -284, 86, 186, 35, -37, -6, -4,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0
|
||||
}, // rx_coef[128]
|
||||
64, // rx_coef_size
|
||||
{0, 0, 0, 0, 0, 0}, //rx_path_clks[6]
|
||||
0 // rx_bandwidth
|
||||
};
|
||||
|
||||
AD9361_TXFIRConfig tx_fir_config = { // BPF PASSBAND 3/20 fs to 1/4 fs
|
||||
3, // tx
|
||||
-6, // tx_gain
|
||||
1, // tx_int
|
||||
{
|
||||
-4, -6, -37, 35, 186, 86, -284, -315,
|
||||
107, 219, -4, 271, 558, -307, -1182, -356,
|
||||
658, 157, 207, 1648, 790, -2525, -2553, 748,
|
||||
865, -476, 3737, 6560, -3583, -14731, -5278, 14819,
|
||||
14819, -5278, -14731, -3583, 6560, 3737, -476, 865,
|
||||
748, -2553, -2525, 790, 1648, 207, 157, 658,
|
||||
-356, -1182, -307, 558, 271, -4, 219, 107,
|
||||
-315, -284, 86, 186, 35, -37, -6, -4,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0
|
||||
}, // tx_coef[128]
|
||||
64, // tx_coef_size
|
||||
{0, 0, 0, 0, 0, 0}, // tx_path_clks[6]
|
||||
0 // tx_bandwidth
|
||||
};
|
||||
|
||||
+1237
File diff suppressed because it is too large
Load Diff
+45
@@ -0,0 +1,45 @@
|
||||
#ifndef DEV_PROFILE_H_
|
||||
#define DEV_PROFILE_H_
|
||||
|
||||
#include <inttypes.h>
|
||||
#include "../app_config.h"
|
||||
#include "../parameters.h"
|
||||
#include "../adi_noos/include/spi.h"
|
||||
#include "../adi_noos/include/gpio.h"
|
||||
#include "../adi_noos/include/delay.h"
|
||||
#include "../adi_noos/include/irq.h"
|
||||
#include "../adi_noos/include/error.h"
|
||||
#include "../adi_noos/drivers/rf-transceiver/ad9361/ad9361_api.h"
|
||||
#include "../adi_noos/drivers/rf-transceiver/ad9361_reg/ad9361_reg.h"
|
||||
#include "../adi_noos/drivers/frequency/hmc7044/hmc7044.h"
|
||||
#include "../adi_noos/drivers/adc/ad9694/ad9694.h"
|
||||
|
||||
// Platform includes
|
||||
#include "../adi_noos/drivers/platform/spi_extra.h"
|
||||
#include "../adi_noos/drivers/platform/gpio_extra.h"
|
||||
#include "../adi_noos/drivers/platform/irq_extra.h"
|
||||
|
||||
// AXI-Cores includes
|
||||
#include "../adi_noos/drivers/axi_core/spi_engine/spi_engine.h"
|
||||
|
||||
// Declare in mian.c
|
||||
extern struct spi_engine_init_param spi_engine_param;
|
||||
extern struct xil_gpio_init_param xil_gpio_param;
|
||||
|
||||
#define GPIO_PARAM &xil_gpio_param
|
||||
#define SPI_PARAM &spi_engine_param
|
||||
#define GPIO_OPS &xil_gpio_ops
|
||||
#define SPI_OPS &spi_eng_platform_ops
|
||||
|
||||
extern struct hmc7044_init_param hmc7044_default_init_param;
|
||||
|
||||
extern AD9361_InitParam ad9361_default_init_param;
|
||||
extern AD9361_RXFIRConfig rx_fir_config;
|
||||
extern AD9361_TXFIRConfig tx_fir_config;
|
||||
|
||||
extern struct ad9361_reg_init_param ad9361_1_reg_default_init_param;
|
||||
extern struct ad9361_reg_init_param ad9361_2_reg_default_init_param;
|
||||
|
||||
uint32_t ad9361_reg_config(struct ad9361_reg_dev *dev);
|
||||
|
||||
#endif /* SRC_DEV_PROFILE_H_ */
|
||||
+100
@@ -0,0 +1,100 @@
|
||||
#include "dev_profile.h"
|
||||
#include "../app_config.h"
|
||||
#include "../adi_noos/drivers/frequency/hmc7044/hmc7044.h"
|
||||
|
||||
// hmc7044 spi settings
|
||||
static spi_init_param hmc7044_spi_init_param = {
|
||||
.device_id = SPI_DEVICE_ID,
|
||||
.max_speed_hz = SPI_ENGINE_MAX_SPEED,
|
||||
.mode = SPI_MODE_4,
|
||||
.chip_select = SPI_CS_HMC7044,
|
||||
.platform_ops = SPI_OPS,
|
||||
.extra = SPI_PARAM
|
||||
};
|
||||
|
||||
// hmc7044 channel specifications
|
||||
struct hmc7044_chan_spec hmc7044_chan_spec[3] = {
|
||||
/* AD9361_XTAL */
|
||||
{
|
||||
.disable = 0,
|
||||
.num = 3,
|
||||
.divider = 100,
|
||||
.coarse_delay = 0,
|
||||
.fine_delay = 0,
|
||||
.high_performance_mode_dis = true,
|
||||
.start_up_mode_dynamic_enable = false,
|
||||
.dynamic_driver_enable = false,
|
||||
.output_control0_rb4_enable = true,
|
||||
.force_mute_enable = false,
|
||||
.driver_mode = CML,
|
||||
.driver_impedance = INTERNAL_100OHM_PER_PIN,
|
||||
.out_mux_mode = CHANNEL_DIV
|
||||
},
|
||||
/* FPGA_DAC_LOGIC_CLK */
|
||||
{
|
||||
.disable = 0,
|
||||
.num = 4,
|
||||
.divider = 10,
|
||||
.coarse_delay = 0,
|
||||
.fine_delay = 0,
|
||||
.high_performance_mode_dis = true,
|
||||
.start_up_mode_dynamic_enable = false,
|
||||
.dynamic_driver_enable = false,
|
||||
.output_control0_rb4_enable = true,
|
||||
.force_mute_enable = false,
|
||||
.driver_mode = CML,
|
||||
.driver_impedance = INTERNAL_100OHM_PER_PIN,
|
||||
.out_mux_mode = CHANNEL_DIV
|
||||
},
|
||||
/* B_AD9361_XTAL */
|
||||
{
|
||||
.disable = 0,
|
||||
.num = 12,
|
||||
.divider = 100,
|
||||
.coarse_delay = 0,
|
||||
.fine_delay = 0,
|
||||
.high_performance_mode_dis = false,
|
||||
.start_up_mode_dynamic_enable = false,
|
||||
.dynamic_driver_enable = false,
|
||||
.output_control0_rb4_enable = true,
|
||||
.force_mute_enable = false,
|
||||
.driver_mode = CML,
|
||||
.driver_impedance = INTERNAL_100OHM_PER_PIN,
|
||||
.out_mux_mode = CHANNEL_DIV
|
||||
},
|
||||
};
|
||||
|
||||
// hmc7044 default configurations
|
||||
struct hmc7044_init_param hmc7044_default_init_param = {
|
||||
.spi_init = &hmc7044_spi_init_param,
|
||||
.clkin_freq = {0, 100000000, 0, 0},
|
||||
.vcxo_freq = 100000000,
|
||||
.pll2_freq = 2500000000,
|
||||
.pll1_loop_bw = 200,
|
||||
.sysref_timer_div = 1536,
|
||||
.in_buf_mode = {
|
||||
BUFFER_DISABLE,
|
||||
ENABLE_AC_COUPLE | ENABLE_INTERNAL_TERM | BUFFER_ENABLE,
|
||||
BUFFER_DISABLE,
|
||||
BUFFER_DISABLE,
|
||||
ENABLE_AC_COUPLE | ENABLE_INTERNAL_TERM | BUFFER_ENABLE
|
||||
},
|
||||
.gpi_ctrl = {
|
||||
GPI_DISABLE,
|
||||
GPI_DISABLE,
|
||||
CHIP_SLEEP_MODE,
|
||||
PULSE_GEN_REQUSET
|
||||
},
|
||||
.gpo_ctrl = {
|
||||
PLL1_LOCK_DETECT | GPO_CMOS_MODE,
|
||||
PLL2_LOCK_DETECT | GPO_CMOS_MODE,
|
||||
GPO_DISABLE,
|
||||
GPO_DISABLE
|
||||
},
|
||||
.num_channels = 3,
|
||||
.pll1_ref_prio_ctrl = 0xE4,
|
||||
.sync_pin_mode = SYNC_MULTICHIP,
|
||||
.high_performance_mode_clock_dist_en = false,
|
||||
.pulse_gen_mode = PULSE_ONE,
|
||||
.channels = hmc7044_chan_spec
|
||||
};
|
||||
@@ -1,226 +1,155 @@
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* Description: main.c
|
||||
/***************************************************************************//**
|
||||
* @file ad9361/src/main.c
|
||||
* @brief Implementation of Main Function.
|
||||
* @author DBogdan (dragos.bogdan@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2013(c) Analog Devices, Inc.
|
||||
*
|
||||
* Date: 2024-01-24 21:38
|
||||
* Last Edit Time: [2024-01-24 21:38]
|
||||
* All rights reserved.
|
||||
*
|
||||
* Revisions: Rev 0.0
|
||||
* History:
|
||||
* [2024-01-24]: Initial edition.
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* Copyright(c) 2024 Beijing Institute of Technology.
|
||||
* Lab of Communication and Networking
|
||||
*
|
||||
******************************************************************************/
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/******************************* Include Files ********************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
|
||||
// Standard
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
|
||||
// Xilinx
|
||||
#include "xscugic.h" // The generic interrupt controller driver component
|
||||
#include "xil_exception.h" // ARM Cortex A9 specific exception related APIs
|
||||
#include "sleep.h"
|
||||
// Platform includes
|
||||
#include <inttypes.h>
|
||||
#include <xparameters.h>
|
||||
#include <xil_mmu.h>
|
||||
#include "xgpiops.h"
|
||||
#include "xspips.h"
|
||||
|
||||
// User
|
||||
// ADI Drivers
|
||||
#include "app_config.h"
|
||||
#include "dev_profile/dev_profile.h"
|
||||
#include "adi_noos/drivers/rf-transceiver/ad9361/ad9361_api.h"
|
||||
#include "adi_noos/drivers/axi_core/spi_engine/spi_engine.h"
|
||||
// AXI-Cores includes
|
||||
#include "adi_noos/drivers/axi_core/spi_engine/spi_engine.h"
|
||||
#include "adi_noos/drivers/platform/gpio_extra.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/**************************** Function Prototypes *****************************/
|
||||
/************************ Variables Definitions *******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
int SetupInterruptSystem(XScuGic* GicInstPtr, u32 IntcDevId);
|
||||
int SetupGpioPs(XGpioPs* GpioPsInstPtr, u32 GpioPsDevId);
|
||||
int SetupSpiPs(XSpiPs* SpiPsInstPtr, u32 SpiPsDevId);
|
||||
struct spi_engine_init_param spi_engine_param = {
|
||||
.ref_clk_hz = SPI_ENGINE_REF_CLK,
|
||||
.type = SPI_ENGINE,
|
||||
.spi_engine_baseaddr = SPI_ENGINE_BASEADDR,
|
||||
.cs_delay = SPI_ENGINE_CS_DELAY,
|
||||
.data_width = SPI_ENGINE_DATA_WIDTH
|
||||
};
|
||||
|
||||
/******************************************************************************/
|
||||
/**************************** Constant Definitions ****************************/
|
||||
/******************************************************************************/
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/************************ Driver Instance Definitions *************************/
|
||||
/******************************************************************************/
|
||||
|
||||
static XScuGic Intc; // General interrupt controller instance
|
||||
static XGpioPs GpioPs;
|
||||
static XSpiPs SpiPs;
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* @brief This function initializes the SCUGIC instance. It looks for the
|
||||
* device configuration based on the unique device ID, initializes a
|
||||
* SCUGIC and enables system interrupts.
|
||||
*
|
||||
* @param GicInstPtr is a reference to the XScuGic driver Instance.
|
||||
* @param IntcDevId is the XPAR_<SCUGIC_instance>_DEVICE_ID value from
|
||||
* "xparameters.h".
|
||||
*
|
||||
* @return SUCCESS if initialization succeed.
|
||||
* XST_FAILURE if initialization failed.
|
||||
*
|
||||
*****************************************************************************/
|
||||
int SetupInterruptSystem(XScuGic* GicInstPtr, u32 IntcDevId){
|
||||
|
||||
int Status;
|
||||
|
||||
XScuGic_Config* IntcConfigPtr; /* Instance of the interrupt controller */
|
||||
|
||||
Xil_ExceptionInit();
|
||||
|
||||
/*
|
||||
* Initialize the interrupt controller driver so that it is ready to
|
||||
* use.
|
||||
*/
|
||||
IntcConfigPtr = XScuGic_LookupConfig(IntcDevId);
|
||||
if (NULL == IntcConfigPtr) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
Status = XScuGic_CfgInitialize(GicInstPtr, IntcConfigPtr,
|
||||
IntcConfigPtr->CpuBaseAddress);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
/*
|
||||
* Connect the interrupt controller interrupt handler to the hardware
|
||||
* interrupt handling logic in the processor.
|
||||
*/
|
||||
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
|
||||
(Xil_ExceptionHandler)XScuGic_InterruptHandler,
|
||||
GicInstPtr);
|
||||
|
||||
/* Enable interrupts in the Processor. */
|
||||
Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ);
|
||||
|
||||
return XST_SUCCESS;
|
||||
} // SetupInterruptSystem
|
||||
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* @brief This function initializes the PS GPIO instance. It looks for the
|
||||
* device configuration based on the unique device ID and initializes a
|
||||
* GpioPs instance.
|
||||
*
|
||||
* @param GpioPsInstPtr is a reference to the XGpioPs driver Instance.
|
||||
* @param GpioPsDevId is the XPAR_<GPIO_instance>_DEVICE_ID value from
|
||||
* "xparameters.h".
|
||||
*
|
||||
* @return SUCCESS if initialize successful.
|
||||
* XST_FAILURE if initialization failed.
|
||||
*
|
||||
*****************************************************************************/
|
||||
int SetupGpioPs(XGpioPs* GpioPsInstPtr, u32 GpioPsDevId){
|
||||
|
||||
int Status;
|
||||
|
||||
XGpioPs_Config *GpioConfigPtr;
|
||||
|
||||
/* Initialize the Gpio driver. */
|
||||
GpioConfigPtr = XGpioPs_LookupConfig(GpioPsDevId);
|
||||
if (GpioConfigPtr == NULL) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
Status = XGpioPs_CfgInitialize(GpioPsInstPtr, GpioConfigPtr,
|
||||
GpioConfigPtr->BaseAddr);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
/* Run a self-test on the GPIO device. */
|
||||
Status = XGpioPs_SelfTest(GpioPsInstPtr);
|
||||
|
||||
return Status;
|
||||
} // SetupGpioPs
|
||||
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* @brief This function initializes the PS SPI instance. It looks for the
|
||||
* device configuration based on the unique device ID and initializes a
|
||||
* SpiPs instance.
|
||||
*
|
||||
* @param SpiPsInstPtr is a reference to the XSpiPs driver Instance.
|
||||
* @param SpiPsDevId is the XPAR_<SPI_instance>_DEVICE_ID value from
|
||||
* "xparameters.h".
|
||||
*
|
||||
* @return SUCCESS if initialize successful.
|
||||
* XST_FAILURE if initialization failed.
|
||||
*
|
||||
*****************************************************************************/
|
||||
int SetupSpiPs(XSpiPs* SpiPsInstPtr, u32 SpiPsDevId){
|
||||
|
||||
int Status;
|
||||
|
||||
XSpiPs_Config *SpiPsConfigPtr;
|
||||
|
||||
/* Initialize spi driver. */
|
||||
SpiPsConfigPtr = XSpiPs_LookupConfig(SpiPsDevId);
|
||||
if (SpiPsConfigPtr == NULL) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
Status = XSpiPs_CfgInitialize(SpiPsInstPtr, SpiPsConfigPtr,
|
||||
SpiPsConfigPtr->BaseAddress);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
// Perform a self-test to check hardware build
|
||||
Status = XSpiPs_SelfTest(SpiPsInstPtr);
|
||||
|
||||
|
||||
// Set the Spi device as a master, force chip select
|
||||
XSpiPs_SetOptions(SpiInstancePtr, XSPIPS_MASTER_OPTION |
|
||||
XSPIPS_FORCE_SSELECT_OPTION);
|
||||
|
||||
XSpiPs_SetClkPrescaler(SpiInstancePtr, XSPIPS_CLK_PRESCALE_64);
|
||||
|
||||
return Status;
|
||||
} // SetupSpiPs
|
||||
struct xil_gpio_init_param xil_gpio_param = {
|
||||
.type = GPIO_PS,
|
||||
.device_id = GPIO_DEVICE_ID
|
||||
};
|
||||
|
||||
struct hmc7044_dev *hmc7044_inst;
|
||||
struct ad9361_reg_dev *ad9361_1_reg_inst;
|
||||
struct ad9361_reg_dev *ad9361_2_reg_inst;
|
||||
struct ad9361_rf_phy *ad9361_phy;
|
||||
struct ad9361_rf_phy *ad9361_2_phy;
|
||||
|
||||
XGpioPs Gpio;
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief main
|
||||
*******************************************************************************/
|
||||
int main(void) {
|
||||
int main(void)
|
||||
{
|
||||
int32_t Status;
|
||||
XGpioPs_Config *ConfigPtr;
|
||||
ConfigPtr = XGpioPs_LookupConfig(GPIO_DEVICE_ID);
|
||||
Status = XGpioPs_CfgInitialize(&Gpio, ConfigPtr, ConfigPtr->BaseAddr);
|
||||
if (Status != XST_SUCCESS)
|
||||
{
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
int32_t Status;
|
||||
/**********************************************************/
|
||||
/****************** HMC7044 Configuration *****************/
|
||||
/**********************************************************/
|
||||
Status = hmc7044_init(&hmc7044_inst, &hmc7044_default_init_param);
|
||||
if (Status != SUCCESS) {
|
||||
printf("hmc7044_init() error: %d\n", Status);
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
/**********************************************************/
|
||||
/***************** Xilinx Initialization ******************/
|
||||
/**********************************************************/
|
||||
// gic
|
||||
Status = SetupInterruptSystem(&Intc, INTC_DEVICE_ID);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
/**********************************************************/
|
||||
/***************** AD9361-1 Configuration *****************/
|
||||
/**********************************************************/
|
||||
XGpioPs_SetDirectionPin(&Gpio, AD9361_1_TXNRX, GPIO_OUTPUT);
|
||||
XGpioPs_SetDirectionPin(&Gpio, AD9361_1_ENABLE, GPIO_OUTPUT);
|
||||
XGpioPs_SetDirectionPin(&Gpio, AD9361_1_EN_AGC, GPIO_OUTPUT);
|
||||
XGpioPs_SetDirectionPin(&Gpio, AD9361_1_RESET_B, GPIO_OUTPUT);
|
||||
|
||||
// gpio
|
||||
Status = SetupGpioPs(&GpioPs, GPIO_DEVICE_ID);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
ad9361_reg_init(&ad9361_1_reg_inst, &ad9361_1_reg_default_init_param);
|
||||
XGpioPs_WritePin(&Gpio, AD9361_1_ENABLE, 0);
|
||||
ad9361_reg_config(ad9361_1_reg_inst);
|
||||
XGpioPs_WritePin(&Gpio, AD9361_1_ENABLE, 1);
|
||||
|
||||
// spi
|
||||
Status = SetupSpiPs(&SpiPs, SPI_DEVICE_ID);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
// Status = ad9361_init(&ad9361_phy, &ad9361_default_init_param);
|
||||
// if (Status != XST_SUCCESS){
|
||||
// return XST_FAILURE;
|
||||
// }else{
|
||||
// printf("Configurate AD9361 Completely!\n");
|
||||
// }
|
||||
// ad9361_set_tx_fir_config(ad9361_phy, tx_fir_config);
|
||||
// ad9361_set_rx_fir_config(ad9361_phy, rx_fir_config);
|
||||
|
||||
/**********************************************************/
|
||||
/***************** AD9361-2 Configuration *****************/
|
||||
/**********************************************************/
|
||||
XGpioPs_SetDirectionPin(&Gpio, AD9361_2_TXNRX, GPIO_OUTPUT);
|
||||
XGpioPs_SetDirectionPin(&Gpio, AD9361_2_ENABLE, GPIO_OUTPUT);
|
||||
XGpioPs_SetDirectionPin(&Gpio, AD9361_2_EN_AGC, GPIO_OUTPUT);
|
||||
XGpioPs_SetDirectionPin(&Gpio, AD9361_2_RESET_B, GPIO_OUTPUT);
|
||||
|
||||
ad9361_reg_init(&ad9361_2_reg_inst, &ad9361_2_reg_default_init_param);
|
||||
XGpioPs_WritePin(&Gpio, AD9361_2_ENABLE, 0);
|
||||
ad9361_reg_config(ad9361_2_reg_inst);
|
||||
XGpioPs_WritePin(&Gpio, AD9361_2_ENABLE, 1);
|
||||
|
||||
// reset rx fifo
|
||||
XGpioPs_SetDirectionPin(&Gpio, AD9361_RX_FIFO_RESET, GPIO_OUTPUT);
|
||||
XGpioPs_WritePin(&Gpio, AD9361_RX_FIFO_RESET, 1);
|
||||
mdelay(200);
|
||||
XGpioPs_WritePin(&Gpio, AD9361_RX_FIFO_RESET, 0);
|
||||
|
||||
|
||||
// uint8_t rd_back;
|
||||
// Status = ad9361_reg_read(ad9361_1_reg_inst, 0x0002, &rd_back);
|
||||
// Status = ad9361_reg_read(ad9361_2_reg_inst, 0x0002, &rd_back);
|
||||
|
||||
return XST_SUCCESS;
|
||||
printf("Done.\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@@ -0,0 +1,120 @@
|
||||
/***************************************************************************//**
|
||||
* @file ad9361/src/parameters.h
|
||||
* @brief Parameters Definitions.
|
||||
* @author DBogdan (dragos.bogdan@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2013(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
#ifndef __PARAMETERS_H__
|
||||
#define __PARAMETERS_H__
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
#include <xparameters.h>
|
||||
#include "app_config.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/********************** Macros and Constants Definitions **********************/
|
||||
/******************************************************************************/
|
||||
#ifdef XILINX_PLATFORM
|
||||
|
||||
#define FCLK_CLK0_HZ 50000000
|
||||
|
||||
#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
|
||||
|
||||
#define GPIO_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
|
||||
#define GPIO_OFFSET 54
|
||||
#define GPIO_INPUT 0
|
||||
#define GPIO_OUTPUT 1
|
||||
#define GPIO_DISABLE 0
|
||||
#define GPIO_ENABLE 1
|
||||
|
||||
// hmc7044
|
||||
#define HMC7044_RESET GPIO_OFFSET+0
|
||||
#define HMC7044_SYNC GPIO_OFFSET+1
|
||||
#define HMC7044_GPIO_0 GPIO_OFFSET+2
|
||||
#define HMC7044_GPIO_1 GPIO_OFFSET+3
|
||||
#define HMC7044_GPIO_2 GPIO_OFFSET+4
|
||||
#define HMC7044_GPIO_3 GPIO_OFFSET+5
|
||||
// ad9361-1
|
||||
#define AD9361_1_TXNRX GPIO_OFFSET+6
|
||||
#define AD9361_1_ENABLE GPIO_OFFSET+7
|
||||
#define AD9361_1_EN_AGC GPIO_OFFSET+8
|
||||
#define AD9361_1_RESET_B GPIO_OFFSET+9
|
||||
#define AD9361_1_CTRL_OUT1 GPIO_OFFSET+10
|
||||
#define AD9361_1_CTRL_OUT2 GPIO_OFFSET+11
|
||||
#define AD9361_1_CTRL_OUT3 GPIO_OFFSET+12
|
||||
#define AD9361_1_CTRL_OUT4 GPIO_OFFSET+13
|
||||
#define AD9361_1_CTRL_OUT5 GPIO_OFFSET+14
|
||||
#define AD9361_1_CTRL_OUT6 GPIO_OFFSET+15
|
||||
#define AD9361_1_CTRL_OUT7 GPIO_OFFSET+16
|
||||
#define AD9361_1_CTRL_OUT8 GPIO_OFFSET+17
|
||||
#define AD9361_1_CTRL_IN1 GPIO_OFFSET+18
|
||||
#define AD9361_1_CTRL_IN2 GPIO_OFFSET+19
|
||||
#define AD9361_1_CTRL_IN3 GPIO_OFFSET+20
|
||||
#define AD9361_1_CTRL_IN4 GPIO_OFFSET+21
|
||||
// ad9361-2
|
||||
#define AD9361_2_TXNRX GPIO_OFFSET+22
|
||||
#define AD9361_2_ENABLE GPIO_OFFSET+23
|
||||
#define AD9361_2_EN_AGC GPIO_OFFSET+24
|
||||
#define AD9361_2_RESET_B GPIO_OFFSET+25
|
||||
#define AD9361_2_CTRL_OUT1 GPIO_OFFSET+26
|
||||
#define AD9361_2_CTRL_OUT2 GPIO_OFFSET+27
|
||||
#define AD9361_2_CTRL_OUT3 GPIO_OFFSET+28
|
||||
#define AD9361_2_CTRL_OUT4 GPIO_OFFSET+29
|
||||
#define AD9361_2_CTRL_OUT5 GPIO_OFFSET+30
|
||||
#define AD9361_2_CTRL_OUT6 GPIO_OFFSET+31
|
||||
#define AD9361_2_CTRL_OUT7 GPIO_OFFSET+32
|
||||
#define AD9361_2_CTRL_OUT8 GPIO_OFFSET+33
|
||||
#define AD9361_2_CTRL_IN1 GPIO_OFFSET+34
|
||||
#define AD9361_2_CTRL_IN2 GPIO_OFFSET+35
|
||||
#define AD9361_2_CTRL_IN3 GPIO_OFFSET+36
|
||||
#define AD9361_2_CTRL_IN4 GPIO_OFFSET+37
|
||||
|
||||
#define AD9361_RX_FIFO_RESET GPIO_OFFSET+38
|
||||
|
||||
#define SPI_DEVICE_ID 0
|
||||
#define SPI_ENGINE_REF_CLK FCLK_CLK0_HZ
|
||||
#define SPI_ENGINE_MAX_SPEED 5000000
|
||||
#define SPI_ENGINE_BASEADDR XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR
|
||||
#define SPI_ENGINE_DATA_WIDTH 8
|
||||
#define SPI_ENGINE_CS_DELAY 3
|
||||
#define SPI_CS_HMC7044 0x00
|
||||
#define SPI_CS_AD9361_1 0x01
|
||||
#define SPI_CS_AD9361_2 0x02
|
||||
|
||||
#endif
|
||||
|
||||
#endif // __PARAMETERS_H__
|
||||
@@ -3,9 +3,9 @@
|
||||
|
||||
<storageModule moduleId="org.eclipse.cdt.core.settings">
|
||||
|
||||
<cconfiguration id="com.xilinx.sdx.system.managedbuilder.debugConfiguration.746031487">
|
||||
<cconfiguration id="com.xilinx.sdx.system.managedbuilder.debugConfiguration.162511159">
|
||||
|
||||
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.xilinx.sdx.system.managedbuilder.debugConfiguration.746031487" moduleId="org.eclipse.cdt.core.settings" name="Debug">
|
||||
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.xilinx.sdx.system.managedbuilder.debugConfiguration.162511159" moduleId="org.eclipse.cdt.core.settings" name="Debug">
|
||||
|
||||
<externalSettings/>
|
||||
|
||||
@@ -21,17 +21,17 @@
|
||||
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
|
||||
<configuration artifactName="${ProjName}" buildProperties="" description="" id="com.xilinx.sdx.system.managedbuilder.debugConfiguration.746031487" name="Debug" parent="com.xilinx.sdx.system.managedbuilder.debugConfiguration">
|
||||
<configuration artifactName="${ProjName}" buildProperties="" description="" id="com.xilinx.sdx.system.managedbuilder.debugConfiguration.162511159" name="Debug" parent="com.xilinx.sdx.system.managedbuilder.debugConfiguration">
|
||||
|
||||
<folderInfo id="com.xilinx.sdx.system.managedbuilder.debugConfiguration.746031487." name="/" resourcePath="">
|
||||
<folderInfo id="com.xilinx.sdx.system.managedbuilder.debugConfiguration.162511159." name="/" resourcePath="">
|
||||
|
||||
<toolChain id="com.xilinx.sdx.system.managedbuilder.debug.toolChain.1029529057" name="System Toolchain" superClass="com.xilinx.sdx.system.managedbuilder.debug.toolChain">
|
||||
<toolChain id="com.xilinx.sdx.system.managedbuilder.debug.toolChain.1485390188" name="System Toolchain" superClass="com.xilinx.sdx.system.managedbuilder.debug.toolChain">
|
||||
|
||||
<targetPlatform id="com.xilinx.sdx.system.managedbuilder.debugConfiguration.746031487..1666728986" name=""/>
|
||||
<targetPlatform id="com.xilinx.sdx.system.managedbuilder.debugConfiguration.162511159..509348882" name=""/>
|
||||
|
||||
<builder buildPath="${workspace_loc:/duifei_cmos_system}/Debug" enableAutoBuild="true" id="com.xilinx.sdx.system.managedbuilder.systemBuilder.767028753" managedBuildOn="true" name="System Project Builder.Debug" superClass="com.xilinx.sdx.system.managedbuilder.systemBuilder"/>
|
||||
<builder buildPath="${workspace_loc:/duifei_cmos_system}/Debug" enableAutoBuild="true" id="com.xilinx.sdx.system.managedbuilder.systemBuilder.299732850" managedBuildOn="true" name="System Project Builder.Debug" superClass="com.xilinx.sdx.system.managedbuilder.systemBuilder"/>
|
||||
|
||||
<tool id="com.xilinx.sdx.system.managedbuilder.toolchain.cfjoinTool.2082969895" name="System Builder" superClass="com.xilinx.sdx.system.managedbuilder.toolchain.cfjoinTool"/>
|
||||
<tool id="com.xilinx.sdx.system.managedbuilder.toolchain.cfjoinTool.751958576" name="System Builder" superClass="com.xilinx.sdx.system.managedbuilder.toolchain.cfjoinTool"/>
|
||||
|
||||
</toolChain>
|
||||
|
||||
@@ -45,9 +45,9 @@
|
||||
|
||||
</cconfiguration>
|
||||
|
||||
<cconfiguration id="com.xilinx.sdx.system.managedbuilder.releaseConfiguration.945258846">
|
||||
<cconfiguration id="com.xilinx.sdx.system.managedbuilder.releaseConfiguration.1931912227">
|
||||
|
||||
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.xilinx.sdx.system.managedbuilder.releaseConfiguration.945258846" moduleId="org.eclipse.cdt.core.settings" name="Release">
|
||||
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.xilinx.sdx.system.managedbuilder.releaseConfiguration.1931912227" moduleId="org.eclipse.cdt.core.settings" name="Release">
|
||||
|
||||
<externalSettings/>
|
||||
|
||||
@@ -63,17 +63,17 @@
|
||||
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
|
||||
<configuration artifactName="${ProjName}" buildProperties="" description="" id="com.xilinx.sdx.system.managedbuilder.releaseConfiguration.945258846" name="Release" parent="com.xilinx.sdx.system.managedbuilder.releaseConfiguration">
|
||||
<configuration artifactName="${ProjName}" buildProperties="" description="" id="com.xilinx.sdx.system.managedbuilder.releaseConfiguration.1931912227" name="Release" parent="com.xilinx.sdx.system.managedbuilder.releaseConfiguration">
|
||||
|
||||
<folderInfo id="com.xilinx.sdx.system.managedbuilder.releaseConfiguration.945258846." name="/" resourcePath="">
|
||||
<folderInfo id="com.xilinx.sdx.system.managedbuilder.releaseConfiguration.1931912227." name="/" resourcePath="">
|
||||
|
||||
<toolChain id="com.xilinx.sdx.system.managedbuilder.release.toolChain.704219540" name="System Toolchain" superClass="com.xilinx.sdx.system.managedbuilder.release.toolChain">
|
||||
<toolChain id="com.xilinx.sdx.system.managedbuilder.release.toolChain.174824923" name="System Toolchain" superClass="com.xilinx.sdx.system.managedbuilder.release.toolChain">
|
||||
|
||||
<targetPlatform id="com.xilinx.sdx.system.managedbuilder.releaseConfiguration.945258846..881202403" name=""/>
|
||||
<targetPlatform id="com.xilinx.sdx.system.managedbuilder.releaseConfiguration.1931912227..1469837457" name=""/>
|
||||
|
||||
<builder buildPath="${workspace_loc:/duifei_cmos_system}/Release" enableAutoBuild="true" id="com.xilinx.sdx.system.managedbuilder.systemBuilder.2099545225" managedBuildOn="true" name="System Project Builder.Release" superClass="com.xilinx.sdx.system.managedbuilder.systemBuilder"/>
|
||||
<builder buildPath="${workspace_loc:/duifei_cmos_system}/Release" enableAutoBuild="true" id="com.xilinx.sdx.system.managedbuilder.systemBuilder.1470513713" managedBuildOn="true" name="System Project Builder.Release" superClass="com.xilinx.sdx.system.managedbuilder.systemBuilder"/>
|
||||
|
||||
<tool id="com.xilinx.sdx.system.managedbuilder.toolchain.cfjoinTool.1054026661" name="System Builder" superClass="com.xilinx.sdx.system.managedbuilder.toolchain.cfjoinTool"/>
|
||||
<tool id="com.xilinx.sdx.system.managedbuilder.toolchain.cfjoinTool.490945215" name="System Builder" superClass="com.xilinx.sdx.system.managedbuilder.toolchain.cfjoinTool"/>
|
||||
|
||||
</toolChain>
|
||||
|
||||
@@ -93,7 +93,7 @@
|
||||
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
|
||||
<project id="duifei_cmos_system.com.xilinx.sdx.system.managedbuilder.projectType.673474257" name="Vitis Embedded System Project" projectType="com.xilinx.sdx.system.managedbuilder.projectType"/>
|
||||
<project id="duifei_cmos_system.com.xilinx.sdx.system.managedbuilder.projectType.861883093" name="Vitis Embedded System Project" projectType="com.xilinx.sdx.system.managedbuilder.projectType"/>
|
||||
|
||||
</storageModule>
|
||||
|
||||
@@ -102,7 +102,5 @@
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="refreshScope"/>
|
||||
|
||||
</cproject>
|
||||
|
||||
+2
-6
@@ -1,16 +1,12 @@
|
||||
<?xml version="1.0" encoding="ASCII"?>
|
||||
<systemproject:SystemProject xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:sdsproject="http://www.xilinx.com/sdsproject" xmlns:systemproject="http://www.xilinx.com/systemproject" name="duifei_cmos_system" platform="/home/josh/Workspace/vivado/vivado_pvt/projects/duifei/duifei_cmos_1t2r/vitis/duifei_platform/export/duifei_platform/duifei_platform.xpfm" platformUID="xilinx:::0.0(custom)" sysConfig="duifei_platform" runtime="C/C++" rootFSLocation="" linuxImage="" sysroot="">
|
||||
<configuration name="Debug" id="com.xilinx.sdx.system.managedbuilder.debugConfiguration.746031487">
|
||||
<configuration name="Debug" id="com.xilinx.sdx.system.managedbuilder.debugConfiguration.162511159">
|
||||
<configBuildOptions xsi:type="systemproject:SystemOptions">
|
||||
<applications name="duifei_cmos" domainName="standalone_domain" domainPrettyName="standalone_domain" appBuildConfig="Debug"/>
|
||||
<options xsi:type="sdsproject:Option" gensdcard="true" dmclkid="0"/>
|
||||
</configBuildOptions>
|
||||
<lastBuildOptions xsi:type="systemproject:SystemOptions">
|
||||
<applications name="duifei_cmos" domainName="standalone_domain" domainPrettyName="standalone_domain" appBuildConfig="Debug"/>
|
||||
<options xsi:type="sdsproject:Option" gensdcard="true" dmclkid="0"/>
|
||||
</lastBuildOptions>
|
||||
</configuration>
|
||||
<configuration name="Release" id="com.xilinx.sdx.system.managedbuilder.releaseConfiguration.945258846">
|
||||
<configuration name="Release" id="com.xilinx.sdx.system.managedbuilder.releaseConfiguration.1931912227">
|
||||
<configBuildOptions xsi:type="systemproject:SystemOptions">
|
||||
<applications name="duifei_cmos" domainName="standalone_domain" domainPrettyName="standalone_domain" appBuildConfig="Release"/>
|
||||
<options xsi:type="sdsproject:Option" gensdcard="true" dmclkid="0"/>
|
||||
|
||||
@@ -3,9 +3,9 @@
|
||||
|
||||
<storageModule moduleId="org.eclipse.cdt.core.settings">
|
||||
|
||||
<cconfiguration id="org.eclipse.cdt.core.default.config.1776907321">
|
||||
<cconfiguration id="org.eclipse.cdt.core.default.config.697523103">
|
||||
|
||||
<storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.1776907321" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
|
||||
<storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.697523103" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
|
||||
|
||||
<externalSettings/>
|
||||
|
||||
|
||||
@@ -172,23 +172,23 @@ unsigned long ps7_pll_init_data_3_0[] = {
|
||||
EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
|
||||
// .. .. FINISH: DDR PLL INIT
|
||||
// .. .. START: IO PLL INIT
|
||||
// .. .. PLL_RES = 0xc
|
||||
// .. .. ==> 0XF8000118[7:4] = 0x0000000CU
|
||||
// .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
|
||||
// .. .. PLL_RES = 0x4
|
||||
// .. .. ==> 0XF8000118[7:4] = 0x00000004U
|
||||
// .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U
|
||||
// .. .. PLL_CP = 0x2
|
||||
// .. .. ==> 0XF8000118[11:8] = 0x00000002U
|
||||
// .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
|
||||
// .. .. LOCK_CNT = 0x145
|
||||
// .. .. ==> 0XF8000118[21:12] = 0x00000145U
|
||||
// .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
|
||||
// .. .. LOCK_CNT = 0xfa
|
||||
// .. .. ==> 0XF8000118[21:12] = 0x000000FAU
|
||||
// .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
|
||||
// .. ..
|
||||
EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
|
||||
EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U),
|
||||
// .. .. .. START: UPDATE FB_DIV
|
||||
// .. .. .. PLL_FDIV = 0x1e
|
||||
// .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
|
||||
// .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
|
||||
// .. .. .. PLL_FDIV = 0x36
|
||||
// .. .. .. ==> 0XF8000108[18:12] = 0x00000036U
|
||||
// .. .. .. ==> MASK : 0x0007F000U VAL : 0x00036000U
|
||||
// .. .. ..
|
||||
EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x00036000U),
|
||||
// .. .. .. FINISH: UPDATE FB_DIV
|
||||
// .. .. .. START: BY PASS PLL
|
||||
// .. .. .. PLL_BYPASS_FORCE = 1
|
||||
@@ -268,25 +268,11 @@ unsigned long ps7_clock_init_data_3_0[] = {
|
||||
// .. SRCSEL = 0x0
|
||||
// .. ==> 0XF800014C[5:4] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000030U VAL : 0x00000000U
|
||||
// .. DIVISOR = 0x5
|
||||
// .. ==> 0XF800014C[13:8] = 0x00000005U
|
||||
// .. ==> MASK : 0x00003F00U VAL : 0x00000500U
|
||||
// .. DIVISOR = 0x9
|
||||
// .. ==> 0XF800014C[13:8] = 0x00000009U
|
||||
// .. ==> MASK : 0x00003F00U VAL : 0x00000900U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
|
||||
// .. CLKACT0 = 0x1
|
||||
// .. ==> 0XF8000158[0:0] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
|
||||
// .. CLKACT1 = 0x0
|
||||
// .. ==> 0XF8000158[1:1] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000002U VAL : 0x00000000U
|
||||
// .. SRCSEL = 0x0
|
||||
// .. ==> 0XF8000158[5:4] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000030U VAL : 0x00000000U
|
||||
// .. DIVISOR = 0x6
|
||||
// .. ==> 0XF8000158[13:8] = 0x00000006U
|
||||
// .. ==> MASK : 0x00003F00U VAL : 0x00000600U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000601U),
|
||||
EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000901U),
|
||||
// .. .. START: TRACE CLOCK
|
||||
// .. .. FINISH: TRACE CLOCK
|
||||
// .. .. CLKACT = 0x1
|
||||
@@ -295,22 +281,22 @@ unsigned long ps7_clock_init_data_3_0[] = {
|
||||
// .. .. SRCSEL = 0x0
|
||||
// .. .. ==> 0XF8000168[5:4] = 0x00000000U
|
||||
// .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
|
||||
// .. .. DIVISOR = 0x5
|
||||
// .. .. ==> 0XF8000168[13:8] = 0x00000005U
|
||||
// .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
|
||||
// .. .. DIVISOR = 0x9
|
||||
// .. .. ==> 0XF8000168[13:8] = 0x00000009U
|
||||
// .. .. ==> MASK : 0x00003F00U VAL : 0x00000900U
|
||||
// .. ..
|
||||
EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
|
||||
EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000901U),
|
||||
// .. .. SRCSEL = 0x0
|
||||
// .. .. ==> 0XF8000170[5:4] = 0x00000000U
|
||||
// .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
|
||||
// .. .. DIVISOR0 = 0x5
|
||||
// .. .. ==> 0XF8000170[13:8] = 0x00000005U
|
||||
// .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
|
||||
// .. .. DIVISOR1 = 0x2
|
||||
// .. .. ==> 0XF8000170[25:20] = 0x00000002U
|
||||
// .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
|
||||
// .. .. DIVISOR0 = 0x6
|
||||
// .. .. ==> 0XF8000170[13:8] = 0x00000006U
|
||||
// .. .. ==> MASK : 0x00003F00U VAL : 0x00000600U
|
||||
// .. .. DIVISOR1 = 0x3
|
||||
// .. .. ==> 0XF8000170[25:20] = 0x00000003U
|
||||
// .. .. ==> MASK : 0x03F00000U VAL : 0x00300000U
|
||||
// .. ..
|
||||
EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U),
|
||||
EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00300600U),
|
||||
// .. .. CLK_621_TRUE = 0x1
|
||||
// .. .. ==> 0XF80001C4[0:0] = 0x00000001U
|
||||
// .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
|
||||
@@ -337,9 +323,9 @@ unsigned long ps7_clock_init_data_3_0[] = {
|
||||
// .. .. SDI1_CPU_1XCLKACT = 0x0
|
||||
// .. .. ==> 0XF800012C[11:11] = 0x00000000U
|
||||
// .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
|
||||
// .. .. SPI0_CPU_1XCLKACT = 0x1
|
||||
// .. .. ==> 0XF800012C[14:14] = 0x00000001U
|
||||
// .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
|
||||
// .. .. SPI0_CPU_1XCLKACT = 0x0
|
||||
// .. .. ==> 0XF800012C[14:14] = 0x00000000U
|
||||
// .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
|
||||
// .. .. SPI1_CPU_1XCLKACT = 0x0
|
||||
// .. .. ==> 0XF800012C[15:15] = 0x00000000U
|
||||
// .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
|
||||
@@ -371,7 +357,7 @@ unsigned long ps7_clock_init_data_3_0[] = {
|
||||
// .. .. ==> 0XF800012C[24:24] = 0x00000001U
|
||||
// .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
|
||||
// .. ..
|
||||
EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01CC400DU),
|
||||
EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01CC000DU),
|
||||
// .. FINISH: CLOCK CONTROL SLCR REGISTERS
|
||||
// .. START: THIS SHOULD BE BLANK
|
||||
// .. FINISH: THIS SHOULD BE BLANK
|
||||
@@ -2546,23 +2532,23 @@ unsigned long ps7_pll_init_data_2_0[] = {
|
||||
EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
|
||||
// .. .. FINISH: DDR PLL INIT
|
||||
// .. .. START: IO PLL INIT
|
||||
// .. .. PLL_RES = 0xc
|
||||
// .. .. ==> 0XF8000118[7:4] = 0x0000000CU
|
||||
// .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
|
||||
// .. .. PLL_RES = 0x4
|
||||
// .. .. ==> 0XF8000118[7:4] = 0x00000004U
|
||||
// .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U
|
||||
// .. .. PLL_CP = 0x2
|
||||
// .. .. ==> 0XF8000118[11:8] = 0x00000002U
|
||||
// .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
|
||||
// .. .. LOCK_CNT = 0x145
|
||||
// .. .. ==> 0XF8000118[21:12] = 0x00000145U
|
||||
// .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
|
||||
// .. .. LOCK_CNT = 0xfa
|
||||
// .. .. ==> 0XF8000118[21:12] = 0x000000FAU
|
||||
// .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
|
||||
// .. ..
|
||||
EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
|
||||
EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U),
|
||||
// .. .. .. START: UPDATE FB_DIV
|
||||
// .. .. .. PLL_FDIV = 0x1e
|
||||
// .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
|
||||
// .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
|
||||
// .. .. .. PLL_FDIV = 0x36
|
||||
// .. .. .. ==> 0XF8000108[18:12] = 0x00000036U
|
||||
// .. .. .. ==> MASK : 0x0007F000U VAL : 0x00036000U
|
||||
// .. .. ..
|
||||
EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x00036000U),
|
||||
// .. .. .. FINISH: UPDATE FB_DIV
|
||||
// .. .. .. START: BY PASS PLL
|
||||
// .. .. .. PLL_BYPASS_FORCE = 1
|
||||
@@ -2642,25 +2628,11 @@ unsigned long ps7_clock_init_data_2_0[] = {
|
||||
// .. SRCSEL = 0x0
|
||||
// .. ==> 0XF800014C[5:4] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000030U VAL : 0x00000000U
|
||||
// .. DIVISOR = 0x5
|
||||
// .. ==> 0XF800014C[13:8] = 0x00000005U
|
||||
// .. ==> MASK : 0x00003F00U VAL : 0x00000500U
|
||||
// .. DIVISOR = 0x9
|
||||
// .. ==> 0XF800014C[13:8] = 0x00000009U
|
||||
// .. ==> MASK : 0x00003F00U VAL : 0x00000900U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
|
||||
// .. CLKACT0 = 0x1
|
||||
// .. ==> 0XF8000158[0:0] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
|
||||
// .. CLKACT1 = 0x0
|
||||
// .. ==> 0XF8000158[1:1] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000002U VAL : 0x00000000U
|
||||
// .. SRCSEL = 0x0
|
||||
// .. ==> 0XF8000158[5:4] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000030U VAL : 0x00000000U
|
||||
// .. DIVISOR = 0x6
|
||||
// .. ==> 0XF8000158[13:8] = 0x00000006U
|
||||
// .. ==> MASK : 0x00003F00U VAL : 0x00000600U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000601U),
|
||||
EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000901U),
|
||||
// .. .. START: TRACE CLOCK
|
||||
// .. .. FINISH: TRACE CLOCK
|
||||
// .. .. CLKACT = 0x1
|
||||
@@ -2669,22 +2641,22 @@ unsigned long ps7_clock_init_data_2_0[] = {
|
||||
// .. .. SRCSEL = 0x0
|
||||
// .. .. ==> 0XF8000168[5:4] = 0x00000000U
|
||||
// .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
|
||||
// .. .. DIVISOR = 0x5
|
||||
// .. .. ==> 0XF8000168[13:8] = 0x00000005U
|
||||
// .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
|
||||
// .. .. DIVISOR = 0x9
|
||||
// .. .. ==> 0XF8000168[13:8] = 0x00000009U
|
||||
// .. .. ==> MASK : 0x00003F00U VAL : 0x00000900U
|
||||
// .. ..
|
||||
EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
|
||||
EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000901U),
|
||||
// .. .. SRCSEL = 0x0
|
||||
// .. .. ==> 0XF8000170[5:4] = 0x00000000U
|
||||
// .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
|
||||
// .. .. DIVISOR0 = 0x5
|
||||
// .. .. ==> 0XF8000170[13:8] = 0x00000005U
|
||||
// .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
|
||||
// .. .. DIVISOR1 = 0x2
|
||||
// .. .. ==> 0XF8000170[25:20] = 0x00000002U
|
||||
// .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
|
||||
// .. .. DIVISOR0 = 0x6
|
||||
// .. .. ==> 0XF8000170[13:8] = 0x00000006U
|
||||
// .. .. ==> MASK : 0x00003F00U VAL : 0x00000600U
|
||||
// .. .. DIVISOR1 = 0x3
|
||||
// .. .. ==> 0XF8000170[25:20] = 0x00000003U
|
||||
// .. .. ==> MASK : 0x03F00000U VAL : 0x00300000U
|
||||
// .. ..
|
||||
EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U),
|
||||
EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00300600U),
|
||||
// .. .. CLK_621_TRUE = 0x1
|
||||
// .. .. ==> 0XF80001C4[0:0] = 0x00000001U
|
||||
// .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
|
||||
@@ -2711,9 +2683,9 @@ unsigned long ps7_clock_init_data_2_0[] = {
|
||||
// .. .. SDI1_CPU_1XCLKACT = 0x0
|
||||
// .. .. ==> 0XF800012C[11:11] = 0x00000000U
|
||||
// .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
|
||||
// .. .. SPI0_CPU_1XCLKACT = 0x1
|
||||
// .. .. ==> 0XF800012C[14:14] = 0x00000001U
|
||||
// .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
|
||||
// .. .. SPI0_CPU_1XCLKACT = 0x0
|
||||
// .. .. ==> 0XF800012C[14:14] = 0x00000000U
|
||||
// .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
|
||||
// .. .. SPI1_CPU_1XCLKACT = 0x0
|
||||
// .. .. ==> 0XF800012C[15:15] = 0x00000000U
|
||||
// .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
|
||||
@@ -2745,7 +2717,7 @@ unsigned long ps7_clock_init_data_2_0[] = {
|
||||
// .. .. ==> 0XF800012C[24:24] = 0x00000001U
|
||||
// .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
|
||||
// .. ..
|
||||
EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01CC400DU),
|
||||
EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01CC000DU),
|
||||
// .. FINISH: CLOCK CONTROL SLCR REGISTERS
|
||||
// .. START: THIS SHOULD BE BLANK
|
||||
// .. FINISH: THIS SHOULD BE BLANK
|
||||
@@ -5067,23 +5039,23 @@ unsigned long ps7_pll_init_data_1_0[] = {
|
||||
EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
|
||||
// .. .. FINISH: DDR PLL INIT
|
||||
// .. .. START: IO PLL INIT
|
||||
// .. .. PLL_RES = 0xc
|
||||
// .. .. ==> 0XF8000118[7:4] = 0x0000000CU
|
||||
// .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
|
||||
// .. .. PLL_RES = 0x4
|
||||
// .. .. ==> 0XF8000118[7:4] = 0x00000004U
|
||||
// .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U
|
||||
// .. .. PLL_CP = 0x2
|
||||
// .. .. ==> 0XF8000118[11:8] = 0x00000002U
|
||||
// .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
|
||||
// .. .. LOCK_CNT = 0x145
|
||||
// .. .. ==> 0XF8000118[21:12] = 0x00000145U
|
||||
// .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
|
||||
// .. .. LOCK_CNT = 0xfa
|
||||
// .. .. ==> 0XF8000118[21:12] = 0x000000FAU
|
||||
// .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
|
||||
// .. ..
|
||||
EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
|
||||
EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U),
|
||||
// .. .. .. START: UPDATE FB_DIV
|
||||
// .. .. .. PLL_FDIV = 0x1e
|
||||
// .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
|
||||
// .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
|
||||
// .. .. .. PLL_FDIV = 0x36
|
||||
// .. .. .. ==> 0XF8000108[18:12] = 0x00000036U
|
||||
// .. .. .. ==> MASK : 0x0007F000U VAL : 0x00036000U
|
||||
// .. .. ..
|
||||
EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x00036000U),
|
||||
// .. .. .. FINISH: UPDATE FB_DIV
|
||||
// .. .. .. START: BY PASS PLL
|
||||
// .. .. .. PLL_BYPASS_FORCE = 1
|
||||
@@ -5163,25 +5135,11 @@ unsigned long ps7_clock_init_data_1_0[] = {
|
||||
// .. SRCSEL = 0x0
|
||||
// .. ==> 0XF800014C[5:4] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000030U VAL : 0x00000000U
|
||||
// .. DIVISOR = 0x5
|
||||
// .. ==> 0XF800014C[13:8] = 0x00000005U
|
||||
// .. ==> MASK : 0x00003F00U VAL : 0x00000500U
|
||||
// .. DIVISOR = 0x9
|
||||
// .. ==> 0XF800014C[13:8] = 0x00000009U
|
||||
// .. ==> MASK : 0x00003F00U VAL : 0x00000900U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
|
||||
// .. CLKACT0 = 0x1
|
||||
// .. ==> 0XF8000158[0:0] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
|
||||
// .. CLKACT1 = 0x0
|
||||
// .. ==> 0XF8000158[1:1] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000002U VAL : 0x00000000U
|
||||
// .. SRCSEL = 0x0
|
||||
// .. ==> 0XF8000158[5:4] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000030U VAL : 0x00000000U
|
||||
// .. DIVISOR = 0x6
|
||||
// .. ==> 0XF8000158[13:8] = 0x00000006U
|
||||
// .. ==> MASK : 0x00003F00U VAL : 0x00000600U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000601U),
|
||||
EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000901U),
|
||||
// .. .. START: TRACE CLOCK
|
||||
// .. .. FINISH: TRACE CLOCK
|
||||
// .. .. CLKACT = 0x1
|
||||
@@ -5190,22 +5148,22 @@ unsigned long ps7_clock_init_data_1_0[] = {
|
||||
// .. .. SRCSEL = 0x0
|
||||
// .. .. ==> 0XF8000168[5:4] = 0x00000000U
|
||||
// .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
|
||||
// .. .. DIVISOR = 0x5
|
||||
// .. .. ==> 0XF8000168[13:8] = 0x00000005U
|
||||
// .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
|
||||
// .. .. DIVISOR = 0x9
|
||||
// .. .. ==> 0XF8000168[13:8] = 0x00000009U
|
||||
// .. .. ==> MASK : 0x00003F00U VAL : 0x00000900U
|
||||
// .. ..
|
||||
EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
|
||||
EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000901U),
|
||||
// .. .. SRCSEL = 0x0
|
||||
// .. .. ==> 0XF8000170[5:4] = 0x00000000U
|
||||
// .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
|
||||
// .. .. DIVISOR0 = 0x5
|
||||
// .. .. ==> 0XF8000170[13:8] = 0x00000005U
|
||||
// .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
|
||||
// .. .. DIVISOR1 = 0x2
|
||||
// .. .. ==> 0XF8000170[25:20] = 0x00000002U
|
||||
// .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
|
||||
// .. .. DIVISOR0 = 0x6
|
||||
// .. .. ==> 0XF8000170[13:8] = 0x00000006U
|
||||
// .. .. ==> MASK : 0x00003F00U VAL : 0x00000600U
|
||||
// .. .. DIVISOR1 = 0x3
|
||||
// .. .. ==> 0XF8000170[25:20] = 0x00000003U
|
||||
// .. .. ==> MASK : 0x03F00000U VAL : 0x00300000U
|
||||
// .. ..
|
||||
EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U),
|
||||
EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00300600U),
|
||||
// .. .. CLK_621_TRUE = 0x1
|
||||
// .. .. ==> 0XF80001C4[0:0] = 0x00000001U
|
||||
// .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
|
||||
@@ -5232,9 +5190,9 @@ unsigned long ps7_clock_init_data_1_0[] = {
|
||||
// .. .. SDI1_CPU_1XCLKACT = 0x0
|
||||
// .. .. ==> 0XF800012C[11:11] = 0x00000000U
|
||||
// .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
|
||||
// .. .. SPI0_CPU_1XCLKACT = 0x1
|
||||
// .. .. ==> 0XF800012C[14:14] = 0x00000001U
|
||||
// .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
|
||||
// .. .. SPI0_CPU_1XCLKACT = 0x0
|
||||
// .. .. ==> 0XF800012C[14:14] = 0x00000000U
|
||||
// .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
|
||||
// .. .. SPI1_CPU_1XCLKACT = 0x0
|
||||
// .. .. ==> 0XF800012C[15:15] = 0x00000000U
|
||||
// .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
|
||||
@@ -5266,7 +5224,7 @@ unsigned long ps7_clock_init_data_1_0[] = {
|
||||
// .. .. ==> 0XF800012C[24:24] = 0x00000001U
|
||||
// .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
|
||||
// .. ..
|
||||
EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01CC400DU),
|
||||
EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01CC000DU),
|
||||
// .. FINISH: CLOCK CONTROL SLCR REGISTERS
|
||||
// .. START: THIS SHOULD BE BLANK
|
||||
// .. FINISH: THIS SHOULD BE BLANK
|
||||
|
||||
@@ -81,7 +81,7 @@ extern unsigned long * ps7_peripherals_init_data;
|
||||
#define USB1_FREQ 60000000
|
||||
#define SDIO_FREQ 10000000
|
||||
#define UART_FREQ 10000000
|
||||
#define SPI_FREQ 166666672
|
||||
#define SPI_FREQ 10000000
|
||||
#define I2C_FREQ 111111115
|
||||
#define WDT_FREQ 111111115
|
||||
#define TTC_FREQ 50000000
|
||||
|
||||
+66
-644
File diff suppressed because it is too large
Load Diff
@@ -16,8 +16,8 @@ proc ps7_pll_init_data_3_0 {} {
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x001452C0
|
||||
mask_write 0XF8000108 0x0007F000 0x0001E000
|
||||
mask_write 0XF8000118 0x003FFFF0 0x000FA240
|
||||
mask_write 0XF8000108 0x0007F000 0x00036000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
@@ -28,12 +28,11 @@ proc ps7_pll_init_data_3_0 {} {
|
||||
proc ps7_clock_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||
mask_write 0XF800014C 0x00003F31 0x00000501
|
||||
mask_write 0XF8000158 0x00003F33 0x00000601
|
||||
mask_write 0XF8000168 0x00003F31 0x00000501
|
||||
mask_write 0XF8000170 0x03F03F30 0x00200500
|
||||
mask_write 0XF800014C 0x00003F31 0x00000901
|
||||
mask_write 0XF8000168 0x00003F31 0x00000901
|
||||
mask_write 0XF8000170 0x03F03F30 0x00300600
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01CC400D
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01CC000D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_3_0 {} {
|
||||
@@ -184,8 +183,8 @@ proc ps7_pll_init_data_2_0 {} {
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x001452C0
|
||||
mask_write 0XF8000108 0x0007F000 0x0001E000
|
||||
mask_write 0XF8000118 0x003FFFF0 0x000FA240
|
||||
mask_write 0XF8000108 0x0007F000 0x00036000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
@@ -196,12 +195,11 @@ proc ps7_pll_init_data_2_0 {} {
|
||||
proc ps7_clock_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||
mask_write 0XF800014C 0x00003F31 0x00000501
|
||||
mask_write 0XF8000158 0x00003F33 0x00000601
|
||||
mask_write 0XF8000168 0x00003F31 0x00000501
|
||||
mask_write 0XF8000170 0x03F03F30 0x00200500
|
||||
mask_write 0XF800014C 0x00003F31 0x00000901
|
||||
mask_write 0XF8000168 0x00003F31 0x00000901
|
||||
mask_write 0XF8000170 0x03F03F30 0x00300600
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01CC400D
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01CC000D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_2_0 {} {
|
||||
@@ -353,8 +351,8 @@ proc ps7_pll_init_data_1_0 {} {
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x001452C0
|
||||
mask_write 0XF8000108 0x0007F000 0x0001E000
|
||||
mask_write 0XF8000118 0x003FFFF0 0x000FA240
|
||||
mask_write 0XF8000108 0x0007F000 0x00036000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
@@ -365,12 +363,11 @@ proc ps7_pll_init_data_1_0 {} {
|
||||
proc ps7_clock_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||
mask_write 0XF800014C 0x00003F31 0x00000501
|
||||
mask_write 0XF8000158 0x00003F33 0x00000601
|
||||
mask_write 0XF8000168 0x00003F31 0x00000501
|
||||
mask_write 0XF8000170 0x03F03F30 0x00200500
|
||||
mask_write 0XF800014C 0x00003F31 0x00000901
|
||||
mask_write 0XF8000168 0x00003F31 0x00000901
|
||||
mask_write 0XF8000170 0x03F03F30 0x00300600
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01CC400D
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01CC000D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_1_0 {} {
|
||||
|
||||
+90
-132
@@ -185,23 +185,23 @@ unsigned long ps7_pll_init_data_3_0[] = {
|
||||
EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
|
||||
// .. .. FINISH: DDR PLL INIT
|
||||
// .. .. START: IO PLL INIT
|
||||
// .. .. PLL_RES = 0xc
|
||||
// .. .. ==> 0XF8000118[7:4] = 0x0000000CU
|
||||
// .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
|
||||
// .. .. PLL_RES = 0x4
|
||||
// .. .. ==> 0XF8000118[7:4] = 0x00000004U
|
||||
// .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U
|
||||
// .. .. PLL_CP = 0x2
|
||||
// .. .. ==> 0XF8000118[11:8] = 0x00000002U
|
||||
// .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
|
||||
// .. .. LOCK_CNT = 0x145
|
||||
// .. .. ==> 0XF8000118[21:12] = 0x00000145U
|
||||
// .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
|
||||
// .. .. LOCK_CNT = 0xfa
|
||||
// .. .. ==> 0XF8000118[21:12] = 0x000000FAU
|
||||
// .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
|
||||
// .. ..
|
||||
EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
|
||||
EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U),
|
||||
// .. .. .. START: UPDATE FB_DIV
|
||||
// .. .. .. PLL_FDIV = 0x1e
|
||||
// .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
|
||||
// .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
|
||||
// .. .. .. PLL_FDIV = 0x36
|
||||
// .. .. .. ==> 0XF8000108[18:12] = 0x00000036U
|
||||
// .. .. .. ==> MASK : 0x0007F000U VAL : 0x00036000U
|
||||
// .. .. ..
|
||||
EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x00036000U),
|
||||
// .. .. .. FINISH: UPDATE FB_DIV
|
||||
// .. .. .. START: BY PASS PLL
|
||||
// .. .. .. PLL_BYPASS_FORCE = 1
|
||||
@@ -281,25 +281,11 @@ unsigned long ps7_clock_init_data_3_0[] = {
|
||||
// .. SRCSEL = 0x0
|
||||
// .. ==> 0XF800014C[5:4] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000030U VAL : 0x00000000U
|
||||
// .. DIVISOR = 0x5
|
||||
// .. ==> 0XF800014C[13:8] = 0x00000005U
|
||||
// .. ==> MASK : 0x00003F00U VAL : 0x00000500U
|
||||
// .. DIVISOR = 0x9
|
||||
// .. ==> 0XF800014C[13:8] = 0x00000009U
|
||||
// .. ==> MASK : 0x00003F00U VAL : 0x00000900U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
|
||||
// .. CLKACT0 = 0x1
|
||||
// .. ==> 0XF8000158[0:0] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
|
||||
// .. CLKACT1 = 0x0
|
||||
// .. ==> 0XF8000158[1:1] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000002U VAL : 0x00000000U
|
||||
// .. SRCSEL = 0x0
|
||||
// .. ==> 0XF8000158[5:4] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000030U VAL : 0x00000000U
|
||||
// .. DIVISOR = 0x6
|
||||
// .. ==> 0XF8000158[13:8] = 0x00000006U
|
||||
// .. ==> MASK : 0x00003F00U VAL : 0x00000600U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000601U),
|
||||
EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000901U),
|
||||
// .. .. START: TRACE CLOCK
|
||||
// .. .. FINISH: TRACE CLOCK
|
||||
// .. .. CLKACT = 0x1
|
||||
@@ -308,22 +294,22 @@ unsigned long ps7_clock_init_data_3_0[] = {
|
||||
// .. .. SRCSEL = 0x0
|
||||
// .. .. ==> 0XF8000168[5:4] = 0x00000000U
|
||||
// .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
|
||||
// .. .. DIVISOR = 0x5
|
||||
// .. .. ==> 0XF8000168[13:8] = 0x00000005U
|
||||
// .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
|
||||
// .. .. DIVISOR = 0x9
|
||||
// .. .. ==> 0XF8000168[13:8] = 0x00000009U
|
||||
// .. .. ==> MASK : 0x00003F00U VAL : 0x00000900U
|
||||
// .. ..
|
||||
EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
|
||||
EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000901U),
|
||||
// .. .. SRCSEL = 0x0
|
||||
// .. .. ==> 0XF8000170[5:4] = 0x00000000U
|
||||
// .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
|
||||
// .. .. DIVISOR0 = 0x5
|
||||
// .. .. ==> 0XF8000170[13:8] = 0x00000005U
|
||||
// .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
|
||||
// .. .. DIVISOR1 = 0x2
|
||||
// .. .. ==> 0XF8000170[25:20] = 0x00000002U
|
||||
// .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
|
||||
// .. .. DIVISOR0 = 0x6
|
||||
// .. .. ==> 0XF8000170[13:8] = 0x00000006U
|
||||
// .. .. ==> MASK : 0x00003F00U VAL : 0x00000600U
|
||||
// .. .. DIVISOR1 = 0x3
|
||||
// .. .. ==> 0XF8000170[25:20] = 0x00000003U
|
||||
// .. .. ==> MASK : 0x03F00000U VAL : 0x00300000U
|
||||
// .. ..
|
||||
EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U),
|
||||
EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00300600U),
|
||||
// .. .. CLK_621_TRUE = 0x1
|
||||
// .. .. ==> 0XF80001C4[0:0] = 0x00000001U
|
||||
// .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
|
||||
@@ -350,9 +336,9 @@ unsigned long ps7_clock_init_data_3_0[] = {
|
||||
// .. .. SDI1_CPU_1XCLKACT = 0x0
|
||||
// .. .. ==> 0XF800012C[11:11] = 0x00000000U
|
||||
// .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
|
||||
// .. .. SPI0_CPU_1XCLKACT = 0x1
|
||||
// .. .. ==> 0XF800012C[14:14] = 0x00000001U
|
||||
// .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
|
||||
// .. .. SPI0_CPU_1XCLKACT = 0x0
|
||||
// .. .. ==> 0XF800012C[14:14] = 0x00000000U
|
||||
// .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
|
||||
// .. .. SPI1_CPU_1XCLKACT = 0x0
|
||||
// .. .. ==> 0XF800012C[15:15] = 0x00000000U
|
||||
// .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
|
||||
@@ -384,7 +370,7 @@ unsigned long ps7_clock_init_data_3_0[] = {
|
||||
// .. .. ==> 0XF800012C[24:24] = 0x00000001U
|
||||
// .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
|
||||
// .. ..
|
||||
EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01CC400DU),
|
||||
EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01CC000DU),
|
||||
// .. FINISH: CLOCK CONTROL SLCR REGISTERS
|
||||
// .. START: THIS SHOULD BE BLANK
|
||||
// .. FINISH: THIS SHOULD BE BLANK
|
||||
@@ -2559,23 +2545,23 @@ unsigned long ps7_pll_init_data_2_0[] = {
|
||||
EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
|
||||
// .. .. FINISH: DDR PLL INIT
|
||||
// .. .. START: IO PLL INIT
|
||||
// .. .. PLL_RES = 0xc
|
||||
// .. .. ==> 0XF8000118[7:4] = 0x0000000CU
|
||||
// .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
|
||||
// .. .. PLL_RES = 0x4
|
||||
// .. .. ==> 0XF8000118[7:4] = 0x00000004U
|
||||
// .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U
|
||||
// .. .. PLL_CP = 0x2
|
||||
// .. .. ==> 0XF8000118[11:8] = 0x00000002U
|
||||
// .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
|
||||
// .. .. LOCK_CNT = 0x145
|
||||
// .. .. ==> 0XF8000118[21:12] = 0x00000145U
|
||||
// .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
|
||||
// .. .. LOCK_CNT = 0xfa
|
||||
// .. .. ==> 0XF8000118[21:12] = 0x000000FAU
|
||||
// .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
|
||||
// .. ..
|
||||
EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
|
||||
EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U),
|
||||
// .. .. .. START: UPDATE FB_DIV
|
||||
// .. .. .. PLL_FDIV = 0x1e
|
||||
// .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
|
||||
// .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
|
||||
// .. .. .. PLL_FDIV = 0x36
|
||||
// .. .. .. ==> 0XF8000108[18:12] = 0x00000036U
|
||||
// .. .. .. ==> MASK : 0x0007F000U VAL : 0x00036000U
|
||||
// .. .. ..
|
||||
EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x00036000U),
|
||||
// .. .. .. FINISH: UPDATE FB_DIV
|
||||
// .. .. .. START: BY PASS PLL
|
||||
// .. .. .. PLL_BYPASS_FORCE = 1
|
||||
@@ -2655,25 +2641,11 @@ unsigned long ps7_clock_init_data_2_0[] = {
|
||||
// .. SRCSEL = 0x0
|
||||
// .. ==> 0XF800014C[5:4] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000030U VAL : 0x00000000U
|
||||
// .. DIVISOR = 0x5
|
||||
// .. ==> 0XF800014C[13:8] = 0x00000005U
|
||||
// .. ==> MASK : 0x00003F00U VAL : 0x00000500U
|
||||
// .. DIVISOR = 0x9
|
||||
// .. ==> 0XF800014C[13:8] = 0x00000009U
|
||||
// .. ==> MASK : 0x00003F00U VAL : 0x00000900U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
|
||||
// .. CLKACT0 = 0x1
|
||||
// .. ==> 0XF8000158[0:0] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
|
||||
// .. CLKACT1 = 0x0
|
||||
// .. ==> 0XF8000158[1:1] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000002U VAL : 0x00000000U
|
||||
// .. SRCSEL = 0x0
|
||||
// .. ==> 0XF8000158[5:4] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000030U VAL : 0x00000000U
|
||||
// .. DIVISOR = 0x6
|
||||
// .. ==> 0XF8000158[13:8] = 0x00000006U
|
||||
// .. ==> MASK : 0x00003F00U VAL : 0x00000600U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000601U),
|
||||
EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000901U),
|
||||
// .. .. START: TRACE CLOCK
|
||||
// .. .. FINISH: TRACE CLOCK
|
||||
// .. .. CLKACT = 0x1
|
||||
@@ -2682,22 +2654,22 @@ unsigned long ps7_clock_init_data_2_0[] = {
|
||||
// .. .. SRCSEL = 0x0
|
||||
// .. .. ==> 0XF8000168[5:4] = 0x00000000U
|
||||
// .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
|
||||
// .. .. DIVISOR = 0x5
|
||||
// .. .. ==> 0XF8000168[13:8] = 0x00000005U
|
||||
// .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
|
||||
// .. .. DIVISOR = 0x9
|
||||
// .. .. ==> 0XF8000168[13:8] = 0x00000009U
|
||||
// .. .. ==> MASK : 0x00003F00U VAL : 0x00000900U
|
||||
// .. ..
|
||||
EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
|
||||
EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000901U),
|
||||
// .. .. SRCSEL = 0x0
|
||||
// .. .. ==> 0XF8000170[5:4] = 0x00000000U
|
||||
// .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
|
||||
// .. .. DIVISOR0 = 0x5
|
||||
// .. .. ==> 0XF8000170[13:8] = 0x00000005U
|
||||
// .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
|
||||
// .. .. DIVISOR1 = 0x2
|
||||
// .. .. ==> 0XF8000170[25:20] = 0x00000002U
|
||||
// .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
|
||||
// .. .. DIVISOR0 = 0x6
|
||||
// .. .. ==> 0XF8000170[13:8] = 0x00000006U
|
||||
// .. .. ==> MASK : 0x00003F00U VAL : 0x00000600U
|
||||
// .. .. DIVISOR1 = 0x3
|
||||
// .. .. ==> 0XF8000170[25:20] = 0x00000003U
|
||||
// .. .. ==> MASK : 0x03F00000U VAL : 0x00300000U
|
||||
// .. ..
|
||||
EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U),
|
||||
EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00300600U),
|
||||
// .. .. CLK_621_TRUE = 0x1
|
||||
// .. .. ==> 0XF80001C4[0:0] = 0x00000001U
|
||||
// .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
|
||||
@@ -2724,9 +2696,9 @@ unsigned long ps7_clock_init_data_2_0[] = {
|
||||
// .. .. SDI1_CPU_1XCLKACT = 0x0
|
||||
// .. .. ==> 0XF800012C[11:11] = 0x00000000U
|
||||
// .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
|
||||
// .. .. SPI0_CPU_1XCLKACT = 0x1
|
||||
// .. .. ==> 0XF800012C[14:14] = 0x00000001U
|
||||
// .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
|
||||
// .. .. SPI0_CPU_1XCLKACT = 0x0
|
||||
// .. .. ==> 0XF800012C[14:14] = 0x00000000U
|
||||
// .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
|
||||
// .. .. SPI1_CPU_1XCLKACT = 0x0
|
||||
// .. .. ==> 0XF800012C[15:15] = 0x00000000U
|
||||
// .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
|
||||
@@ -2758,7 +2730,7 @@ unsigned long ps7_clock_init_data_2_0[] = {
|
||||
// .. .. ==> 0XF800012C[24:24] = 0x00000001U
|
||||
// .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
|
||||
// .. ..
|
||||
EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01CC400DU),
|
||||
EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01CC000DU),
|
||||
// .. FINISH: CLOCK CONTROL SLCR REGISTERS
|
||||
// .. START: THIS SHOULD BE BLANK
|
||||
// .. FINISH: THIS SHOULD BE BLANK
|
||||
@@ -5080,23 +5052,23 @@ unsigned long ps7_pll_init_data_1_0[] = {
|
||||
EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
|
||||
// .. .. FINISH: DDR PLL INIT
|
||||
// .. .. START: IO PLL INIT
|
||||
// .. .. PLL_RES = 0xc
|
||||
// .. .. ==> 0XF8000118[7:4] = 0x0000000CU
|
||||
// .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U
|
||||
// .. .. PLL_RES = 0x4
|
||||
// .. .. ==> 0XF8000118[7:4] = 0x00000004U
|
||||
// .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U
|
||||
// .. .. PLL_CP = 0x2
|
||||
// .. .. ==> 0XF8000118[11:8] = 0x00000002U
|
||||
// .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U
|
||||
// .. .. LOCK_CNT = 0x145
|
||||
// .. .. ==> 0XF8000118[21:12] = 0x00000145U
|
||||
// .. .. ==> MASK : 0x003FF000U VAL : 0x00145000U
|
||||
// .. .. LOCK_CNT = 0xfa
|
||||
// .. .. ==> 0XF8000118[21:12] = 0x000000FAU
|
||||
// .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U
|
||||
// .. ..
|
||||
EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001452C0U),
|
||||
EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U),
|
||||
// .. .. .. START: UPDATE FB_DIV
|
||||
// .. .. .. PLL_FDIV = 0x1e
|
||||
// .. .. .. ==> 0XF8000108[18:12] = 0x0000001EU
|
||||
// .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001E000U
|
||||
// .. .. .. PLL_FDIV = 0x36
|
||||
// .. .. .. ==> 0XF8000108[18:12] = 0x00000036U
|
||||
// .. .. .. ==> MASK : 0x0007F000U VAL : 0x00036000U
|
||||
// .. .. ..
|
||||
EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x0001E000U),
|
||||
EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x00036000U),
|
||||
// .. .. .. FINISH: UPDATE FB_DIV
|
||||
// .. .. .. START: BY PASS PLL
|
||||
// .. .. .. PLL_BYPASS_FORCE = 1
|
||||
@@ -5176,25 +5148,11 @@ unsigned long ps7_clock_init_data_1_0[] = {
|
||||
// .. SRCSEL = 0x0
|
||||
// .. ==> 0XF800014C[5:4] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000030U VAL : 0x00000000U
|
||||
// .. DIVISOR = 0x5
|
||||
// .. ==> 0XF800014C[13:8] = 0x00000005U
|
||||
// .. ==> MASK : 0x00003F00U VAL : 0x00000500U
|
||||
// .. DIVISOR = 0x9
|
||||
// .. ==> 0XF800014C[13:8] = 0x00000009U
|
||||
// .. ==> MASK : 0x00003F00U VAL : 0x00000900U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000501U),
|
||||
// .. CLKACT0 = 0x1
|
||||
// .. ==> 0XF8000158[0:0] = 0x00000001U
|
||||
// .. ==> MASK : 0x00000001U VAL : 0x00000001U
|
||||
// .. CLKACT1 = 0x0
|
||||
// .. ==> 0XF8000158[1:1] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000002U VAL : 0x00000000U
|
||||
// .. SRCSEL = 0x0
|
||||
// .. ==> 0XF8000158[5:4] = 0x00000000U
|
||||
// .. ==> MASK : 0x00000030U VAL : 0x00000000U
|
||||
// .. DIVISOR = 0x6
|
||||
// .. ==> 0XF8000158[13:8] = 0x00000006U
|
||||
// .. ==> MASK : 0x00003F00U VAL : 0x00000600U
|
||||
// ..
|
||||
EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00000601U),
|
||||
EMIT_MASKWRITE(0XF800014C, 0x00003F31U ,0x00000901U),
|
||||
// .. .. START: TRACE CLOCK
|
||||
// .. .. FINISH: TRACE CLOCK
|
||||
// .. .. CLKACT = 0x1
|
||||
@@ -5203,22 +5161,22 @@ unsigned long ps7_clock_init_data_1_0[] = {
|
||||
// .. .. SRCSEL = 0x0
|
||||
// .. .. ==> 0XF8000168[5:4] = 0x00000000U
|
||||
// .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
|
||||
// .. .. DIVISOR = 0x5
|
||||
// .. .. ==> 0XF8000168[13:8] = 0x00000005U
|
||||
// .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
|
||||
// .. .. DIVISOR = 0x9
|
||||
// .. .. ==> 0XF8000168[13:8] = 0x00000009U
|
||||
// .. .. ==> MASK : 0x00003F00U VAL : 0x00000900U
|
||||
// .. ..
|
||||
EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000501U),
|
||||
EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000901U),
|
||||
// .. .. SRCSEL = 0x0
|
||||
// .. .. ==> 0XF8000170[5:4] = 0x00000000U
|
||||
// .. .. ==> MASK : 0x00000030U VAL : 0x00000000U
|
||||
// .. .. DIVISOR0 = 0x5
|
||||
// .. .. ==> 0XF8000170[13:8] = 0x00000005U
|
||||
// .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U
|
||||
// .. .. DIVISOR1 = 0x2
|
||||
// .. .. ==> 0XF8000170[25:20] = 0x00000002U
|
||||
// .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U
|
||||
// .. .. DIVISOR0 = 0x6
|
||||
// .. .. ==> 0XF8000170[13:8] = 0x00000006U
|
||||
// .. .. ==> MASK : 0x00003F00U VAL : 0x00000600U
|
||||
// .. .. DIVISOR1 = 0x3
|
||||
// .. .. ==> 0XF8000170[25:20] = 0x00000003U
|
||||
// .. .. ==> MASK : 0x03F00000U VAL : 0x00300000U
|
||||
// .. ..
|
||||
EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00200500U),
|
||||
EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00300600U),
|
||||
// .. .. CLK_621_TRUE = 0x1
|
||||
// .. .. ==> 0XF80001C4[0:0] = 0x00000001U
|
||||
// .. .. ==> MASK : 0x00000001U VAL : 0x00000001U
|
||||
@@ -5245,9 +5203,9 @@ unsigned long ps7_clock_init_data_1_0[] = {
|
||||
// .. .. SDI1_CPU_1XCLKACT = 0x0
|
||||
// .. .. ==> 0XF800012C[11:11] = 0x00000000U
|
||||
// .. .. ==> MASK : 0x00000800U VAL : 0x00000000U
|
||||
// .. .. SPI0_CPU_1XCLKACT = 0x1
|
||||
// .. .. ==> 0XF800012C[14:14] = 0x00000001U
|
||||
// .. .. ==> MASK : 0x00004000U VAL : 0x00004000U
|
||||
// .. .. SPI0_CPU_1XCLKACT = 0x0
|
||||
// .. .. ==> 0XF800012C[14:14] = 0x00000000U
|
||||
// .. .. ==> MASK : 0x00004000U VAL : 0x00000000U
|
||||
// .. .. SPI1_CPU_1XCLKACT = 0x0
|
||||
// .. .. ==> 0XF800012C[15:15] = 0x00000000U
|
||||
// .. .. ==> MASK : 0x00008000U VAL : 0x00000000U
|
||||
@@ -5279,7 +5237,7 @@ unsigned long ps7_clock_init_data_1_0[] = {
|
||||
// .. .. ==> 0XF800012C[24:24] = 0x00000001U
|
||||
// .. .. ==> MASK : 0x01000000U VAL : 0x01000000U
|
||||
// .. ..
|
||||
EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01CC400DU),
|
||||
EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01CC000DU),
|
||||
// .. FINISH: CLOCK CONTROL SLCR REGISTERS
|
||||
// .. START: THIS SHOULD BE BLANK
|
||||
// .. FINISH: THIS SHOULD BE BLANK
|
||||
|
||||
@@ -95,7 +95,7 @@ extern unsigned long * ps7_peripherals_init_data;
|
||||
#define USB1_FREQ 60000000
|
||||
#define SDIO_FREQ 10000000
|
||||
#define UART_FREQ 10000000
|
||||
#define SPI_FREQ 166666672
|
||||
#define SPI_FREQ 10000000
|
||||
#define I2C_FREQ 111111115
|
||||
#define WDT_FREQ 111111115
|
||||
#define TTC_FREQ 50000000
|
||||
|
||||
BIN
Binary file not shown.
BIN
Binary file not shown.
@@ -1 +1 @@
|
||||
{"platformName":"duifei_platform","sprVersion":"2.0","mode":"gui","dsaType":"Fixed","platformDesc":"duifei_platform","platHandOff":"/home/josh/Workspace/vivado/vivado_pvt/projects/duifei/duifei_cmos_1t2r/system_top.xsa","platIntHandOff":"<platformDir>/hw/system_top.xsa","deviceType":"zynq","platIsPrebuiltAutogen":"false","platIsNoBootBsp":"false","hasFsblMakeHasChanges":"false","hasPmufwMakeHasChanges":"false","fsblExtraCompilerFlags":"-MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard ","platPreBuiltFlag":false,"platformSamplesDir":"","platActiveSys":"duifei_platform","systems":[{"systemName":"duifei_platform","systemDesc":"duifei_platform","sysIsBootAutoGen":"true","systemDispName":"duifei_platform","sysActiveDom":"standalone_domain","sysDefaultDom":"standalone_domain","domains":[{"domainName":"zynq_fsbl","domainDispName":"zynq_fsbl","domainDesc":"FSBL Application BSP - Auto Generated.","processors":"ps7_cortexa9_0","os":"standalone","sdxOs":"standalone","debugEnable":"","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"9.0","mssFile":"","md5Digest":"a5dd9b2b99a4e80a35dcc5f15d411c7a","compatibleApp":"zynq_fsbl","domType":"bootDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["xilffs:5.1","xilrsa:1.7"],"libOptions":{"libsContainingOptions":[]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}},{"domainName":"standalone_domain","domainDispName":"standalone on ps7_cortexa9_0","domainDesc":"standalone_domain","processors":"ps7_cortexa9_0","os":"standalone","sdxOs":"standalone","qemuArgs":"<platformDir>/resources/duifei_platform/standalone_domain/qemu_args.txt","qemuData":"<platformDir>/resources/duifei_platform/standalone_domain/qemu","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"9.0","mssFile":"","md5Digest":"ee1795cc5622622c05a83e5a3cf480b4","compatibleApp":"","domType":"mssDomain","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":[],"libOptions":{"libsContainingOptions":[]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}}]}]}
|
||||
{"platformName":"duifei_platform","sprVersion":"2.0","mode":"gui","dsaType":"Fixed","platformDesc":"duifei_platform","platHandOff":"/home/josh/Workspace/vivado/vivado_pvt/projects/duifei/duifei_cmos_1t2r/system_top.xsa","platIntHandOff":"<platformDir>/hw/system_top.xsa","deviceType":"zynq","platIsPrebuiltAutogen":"false","platIsNoBootBsp":"false","hasFsblMakeHasChanges":"false","hasPmufwMakeHasChanges":"false","fsblExtraCompilerFlags":"-MMD -MP -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard ","platPreBuiltFlag":false,"platformSamplesDir":"","platActiveSys":"duifei_platform","systems":[{"systemName":"duifei_platform","systemDesc":"duifei_platform","sysIsBootAutoGen":"true","systemDispName":"duifei_platform","sysActiveDom":"standalone_domain","sysDefaultDom":"standalone_domain","domains":[{"domainName":"zynq_fsbl","domainDispName":"zynq_fsbl","domainDesc":"FSBL Application BSP - Auto Generated.","processors":"ps7_cortexa9_0","os":"standalone","sdxOs":"standalone","debugEnable":"","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"9.0","mssFile":"","md5Digest":"a8e323f0dbcd513982a224aa8903ae1d","compatibleApp":"zynq_fsbl","domType":"bootDomain","arch":"32-bit","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":["xilffs:5.1","xilrsa:1.7"],"libOptions":{"libsContainingOptions":[]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}},{"domainName":"standalone_domain","domainDispName":"standalone on ps7_cortexa9_0","domainDesc":"standalone_domain","processors":"ps7_cortexa9_0","os":"standalone","sdxOs":"standalone","qemuArgs":"<platformDir>/resources/duifei_platform/standalone_domain/qemu_args.txt","qemuData":"<platformDir>/resources/duifei_platform/standalone_domain/qemu","debugEnable":"False","domRuntimes":["cpp"],"swRepo":"","mssOsVer":"9.0","mssFile":"","md5Digest":"470b52687b1ae65fd346d81bbd926113","compatibleApp":"","domType":"mssDomain","appSettings":{"appCompilerFlags":"","appLinkerFlags":""},"addedLibs":[],"libOptions":{"libsContainingOptions":[]},"prebuiltLibs":{"prebuiltIncPath":[],"prebuiltLibPath":[]},"isolation":{}}]}]}
|
||||
|
||||
@@ -16,6 +16,3 @@ platform write
|
||||
platform generate -domains
|
||||
platform active {duifei_platform}
|
||||
platform generate
|
||||
platform active {duifei_platform}
|
||||
platform generate
|
||||
bsp reload
|
||||
|
||||
+10
-21
@@ -89,6 +89,11 @@
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
/* Peripheral Definitions for peripheral AXI_SPI_ENGINE_AXI_SPI_ENGINE */
|
||||
#define XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR 0x43C00000
|
||||
#define XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_HIGHADDR 0x43C0FFFF
|
||||
|
||||
|
||||
/* Peripheral Definitions for peripheral PS7_AFI_0 */
|
||||
#define XPAR_PS7_AFI_0_S_AXI_BASEADDR 0xF8008000
|
||||
#define XPAR_PS7_AFI_0_S_AXI_HIGHADDR 0xF8008FFF
|
||||
@@ -184,6 +189,11 @@
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
/* Canonical Definitions for peripheral AXI_SPI_ENGINE_AXI_SPI_ENGINE */
|
||||
#define XPAR_AXI_SPI_ENGINE_0_BASEADDR 0x43C00000
|
||||
#define XPAR_AXI_SPI_ENGINE_0_HIGHADDR 0x43C0FFFF
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -323,27 +333,6 @@
|
||||
#define XPAR_SCUWDT_0_HIGHADDR 0xF8F006FF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver SPIPS */
|
||||
#define XPAR_XSPIPS_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral PS7_SPI_0 */
|
||||
#define XPAR_PS7_SPI_0_DEVICE_ID 0
|
||||
#define XPAR_PS7_SPI_0_BASEADDR 0xE0006000
|
||||
#define XPAR_PS7_SPI_0_HIGHADDR 0xE0006FFF
|
||||
#define XPAR_PS7_SPI_0_SPI_CLK_FREQ_HZ 166666672
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral PS7_SPI_0 */
|
||||
#define XPAR_XSPIPS_0_DEVICE_ID XPAR_PS7_SPI_0_DEVICE_ID
|
||||
#define XPAR_XSPIPS_0_BASEADDR 0xE0006000
|
||||
#define XPAR_XSPIPS_0_HIGHADDR 0xE0006FFF
|
||||
#define XPAR_XSPIPS_0_SPI_CLK_FREQ_HZ 166666672
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver XADCPS */
|
||||
|
||||
-703
@@ -1,703 +0,0 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2017 - 2022 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xspips.h
|
||||
* @addtogroup spips Overview
|
||||
* @{
|
||||
* @details
|
||||
*
|
||||
* This file contains the implementation of the XSpiPs driver. It works for
|
||||
* both the master and slave mode. User documentation for the driver functions
|
||||
* is contained in this file in the form of comment blocks at the front of each
|
||||
* function.
|
||||
*
|
||||
* An SPI device connects to an SPI bus through a 4-wire serial interface.
|
||||
* The SPI bus is a full-duplex, synchronous bus that facilitates communication
|
||||
* between one master and one slave. The device is always full-duplex,
|
||||
* which means that for every byte sent, one is received, and vice-versa.
|
||||
* The master controls the clock, so it can regulate when it wants to
|
||||
* send or receive data. The slave is under control of the master, it must
|
||||
* respond quickly since it has no control of the clock and must send/receive
|
||||
* data as fast or as slow as the master does.
|
||||
*
|
||||
* <b>Initialization & Configuration</b>
|
||||
*
|
||||
* The XSpiPs_Config structure is used by the driver to configure itself. This
|
||||
* configuration structure is typically created by the tool-chain based on HW
|
||||
* build properties.
|
||||
*
|
||||
* To support multiple runtime loading and initialization strategies employed by
|
||||
* various operating systems, the driver instance can be initialized in the
|
||||
* following way:
|
||||
* - XSpiPs_LookupConfig(DeviceId) - Use the divide identifier to find the
|
||||
* static configuration structure defined in xspips_g.c. This is setup by
|
||||
* the tools. For some operating systems the config structure will be
|
||||
* initialized by the software and this call is not needed.
|
||||
* - XSpiPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
|
||||
* configuration structure provided by the caller. If running in a system
|
||||
* with address translation, the provided virtual memory base address
|
||||
* replaces the physical address present in the configuration structure.
|
||||
*
|
||||
* <b>Multiple Masters</b>
|
||||
*
|
||||
* More than one master can exist, but arbitration is the responsibility of
|
||||
* the higher layer software. The device driver does not perform any type of
|
||||
* arbitration.
|
||||
*
|
||||
* <b>Multiple Slaves</b>
|
||||
*
|
||||
* Contention between multiple masters is detected by the hardware, in which
|
||||
* case a mode fault occurs on the device. The device is disabled immediately
|
||||
* by hardware, and the current word transfer is stopped. The Aborted word
|
||||
* transfer due to the mode fault is resumed once the devie is enabled again.
|
||||
*
|
||||
* <b>Modes of Operation</b>
|
||||
*
|
||||
* There are four modes to perform a data transfer and the selection of a mode
|
||||
* is based on Chip Select(CS) and Start. These two options individually, can
|
||||
* be controlled either by software(Manual) or hardware(Auto).
|
||||
* - Auto CS: Chip select is automatically asserted as soon as the first word
|
||||
* is written into the TXFIFO and deasserted when the TXFIFO becomes
|
||||
* empty
|
||||
* - Manual CS: Software must assert and deassert CS.
|
||||
* - Auto Start: Data transmission starts as soon as there is data in the
|
||||
* TXFIFO and stalls when the TXFIFO is empty
|
||||
* - Manual Start: Software must start data transmission at the beginning of
|
||||
* the transaction or whenever the TXFIFO has become empty
|
||||
*
|
||||
* The preferred combination is Manual CS and Auto Start.
|
||||
* In this combination, the software asserts CS before loading any data into
|
||||
* TXFIFO. In Auto Start mode, whenever data is in TXFIFO, controller sends it
|
||||
* out until TXFIFO becomes empty. The software reads the RXFIFO whenever the
|
||||
* data is available. If no further data, software disables CS.
|
||||
*
|
||||
* Risks/challenges of other combinations:
|
||||
* - Manual CS and Manual Start: Manual Start bit should be set after each
|
||||
* TXFIFO write otherwise there could be a race condition where the TXFIFO
|
||||
* becomes empty before the new word is written. In that case the
|
||||
* transmission stops.
|
||||
* - Auto CS with Manual or Auto Start: It is very difficult for software to
|
||||
* keep the TXFIFO filled. Whenever the TXFIFO runs empty, CS is deasserted.
|
||||
* This results in a single transaction to be split into multiple pieces each
|
||||
* with its own chip select. This will result in garbage data to be sent.
|
||||
*
|
||||
* <b>Interrupts</b>
|
||||
*
|
||||
* The user must connect the interrupt handler of the driver,
|
||||
* XSpiPs_InterruptHandler, to an interrupt system such that it will be
|
||||
* called when an interrupt occurs. This function does not save and restore
|
||||
* the processor context such that the user must provide this processing.
|
||||
*
|
||||
* The driver handles the following interrupts:
|
||||
* - Data Transmit Register/FIFO Underflow
|
||||
* - Data Receive Register/FIFO Full
|
||||
* - Data Receive Register/FIFO Not Empty
|
||||
* - Data Transmit Register/FIFO Full
|
||||
* - Data Transmit Register/FIFO Overwater
|
||||
* - Mode Fault Error
|
||||
* - Data Receive Register/FIFO Overrun
|
||||
*
|
||||
* The Data Transmit Register/FIFO Overwater interrupt -- indicates that the
|
||||
* SPI device has transmitted the data available to transmit, and now its data
|
||||
* register and FIFO is ready to accept more data. The driver uses this
|
||||
* interrupt to indicate progress while sending data. The driver may have
|
||||
* more data to send, in which case the data transmit register and FIFO is
|
||||
* filled for subsequent transmission. When this interrupt arrives and all
|
||||
* the data has been sent, the driver invokes the status callback with a
|
||||
* value of XST_SPI_TRANSFER_DONE to inform the upper layer software that
|
||||
* all data has been sent.
|
||||
*
|
||||
* The Data Transmit Register/FIFO Underflow interrupt -- indicates that,
|
||||
* as slave, the SPI device was required to transmit but there was no data
|
||||
* available to transmit in the transmit register (or FIFO). This may not
|
||||
* be an error if the master is not expecting data. But in the case where
|
||||
* the master is expecting data, this serves as a notification of such a
|
||||
* condition. The driver reports this condition to the upper layer
|
||||
* software through the status handler.
|
||||
*
|
||||
* The Data Receive Register/FIFO Overrun interrupt -- indicates that the SPI
|
||||
* device received data and subsequently dropped the data because the data
|
||||
* receive register and FIFO was full. The interrupt applies to both master
|
||||
* and slave operation. The driver reports this condition to the upper layer
|
||||
* software through the status handler. This likely indicates a problem with
|
||||
* the higher layer protocol, or a problem with the slave performance.
|
||||
*
|
||||
* The Mode Fault Error interrupt -- indicates that while configured as a
|
||||
* master, the device was selected as a slave by another master. This can be
|
||||
* used by the application for arbitration in a multimaster environment or to
|
||||
* indicate a problem with arbitration. When this interrupt occurs, the
|
||||
* driver invokes the status callback with a status value of
|
||||
* XST_SPI_MODE_FAULT. It is up to the application to resolve the conflict.
|
||||
* When configured as a slave, Mode Fault Error interrupt indicates that a slave
|
||||
* device was selected as a slave by a master, but the slave device was
|
||||
* disabled. When configured as a master, Mode Fault Error interrupt indicates
|
||||
* that another SPI device is acting as a master on the bus.
|
||||
*
|
||||
*
|
||||
* <b>Polled Operation</b>
|
||||
*
|
||||
* Transfer in polled mode is supported through a separate interface function
|
||||
* XSpiPs_PolledTransfer(). Unlike the transfer function in the interrupt mode,
|
||||
* this function blocks until all data has been sent/received.
|
||||
*
|
||||
* <b>Device Busy</b>
|
||||
*
|
||||
* Some operations are disallowed when the device is busy. The driver tracks
|
||||
* whether a device is busy. The device is considered busy when a data transfer
|
||||
* request is outstanding, and is considered not busy only when that transfer
|
||||
* completes (or is aborted with a mode fault error). This applies to both
|
||||
* master and slave devices.
|
||||
*
|
||||
* <b>Device Configuration</b>
|
||||
*
|
||||
* The device can be configured in various ways during the FPGA implementation
|
||||
* process. Configuration parameters are stored in the xspips_g.c file or
|
||||
* passed in via XSpiPs_CfgInitialize(). A table is defined where each entry
|
||||
* contains configuration information for an SPI device, including the base
|
||||
* address for the device.
|
||||
*
|
||||
* <b>RTOS Independence</b>
|
||||
*
|
||||
* This driver is intended to be RTOS and processor independent. It works with
|
||||
* physical addresses only. Any needs for dynamic memory management, threads or
|
||||
* thread mutual exclusion, virtual memory, or cache control must be satisfied
|
||||
* by the layer above this driver.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ------ -------- -----------------------------------------------
|
||||
* 1.00 drg/jz 01/25/10 First release
|
||||
* 1.00 sdm 10/25/11 Removed the Divide by 2 in the SPI Clock Prescaler
|
||||
* options as this is not supported in the device.
|
||||
* 1.01 sg 03/07/12 Updated the code to always clear the relevant bits
|
||||
* before writing to config register.
|
||||
* Always clear the slave select bits before write and
|
||||
* clear the bits to no slave at the end of transfer
|
||||
* Modified the Polled transfer transmit/receive logic.
|
||||
* Tx should wait on TXOW Interrupt and Rx on RXNEMTY.
|
||||
* 1.02 sg 05/31/12 Updated XSPIPS_FIFO_DEPTH to 128 from 32 to match HW
|
||||
* for CR 658289
|
||||
* 1.03 sg 09/21/12 Added memory barrier dmb in polled transfer and
|
||||
* interrupt handler to overcome the clock domain
|
||||
* crossing issue in the controller. For CR #679252.
|
||||
* 1.04a sg 01/30/13 Created XSPIPS_MANUAL_START_OPTION. Created macros
|
||||
* XSpiPs_IsMaster, XSpiPs_IsManualStart and
|
||||
* XSpiPs_IsManualChipSelect. Changed SPI
|
||||
* Enable/Disable macro argument from BaseAddress to
|
||||
* Instance Pointer. Added DelayNss argument to SetDelays
|
||||
* and GetDelays API's. Added macros to set/get the
|
||||
* RX Watermark value.Created macros XSpiPs_IsMaster,
|
||||
* XSpiPs_IsManualStart and XSpiPs_IsManualChipSelect.
|
||||
* Changed SPI transfer logic for polled and interrupt
|
||||
* modes to be based on filled tx fifo count and receive
|
||||
* based on it. RXNEMPTY interrupt is not used.
|
||||
* SetSlaveSelect API logic is modified to drive the bit
|
||||
* position low based on the slave select value
|
||||
* requested. GetSlaveSelect API will return the value
|
||||
* based on bit position that is low.
|
||||
* Created XSPIPS_CR_MODF_GEN_EN_MASK macro and added it
|
||||
* to XSPIPS_CR_RESET_STATE. Created
|
||||
* XSPIPS_IXR_WR_TO_CLR_MASK for interrupts which need
|
||||
* write-to-clear. Added shift and mask macros for d_nss
|
||||
* parameter. Added Rx Watermark mask.
|
||||
* 1.05a hk 26/04/13 Added disable and enable in XSpiPs_SetOptions when
|
||||
* CPOL/CPHA bits are set/reset. Fix for CR#707669.
|
||||
* 1.06a hk 08/22/13 Changed GetSlaveSelect function. CR# 727866.
|
||||
* Added masking ConfigReg before writing in SetSlaveSel
|
||||
* Added extended slave select support - CR#722569.
|
||||
* Added prototypes of reset API and related constant
|
||||
* definitions.
|
||||
* Added check for MODF in polled transfer function.
|
||||
* 3.0 vm 12/09/14 Modified driver source code for MISRA-C:2012 compliance.
|
||||
* Support for Zynq Ultrascale Mp added.
|
||||
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
|
||||
* generation.
|
||||
* ms 04/05/17 Modified Comment lines in functions of spips
|
||||
* examples to recognize it as documentation block
|
||||
* for doxygen generation and also modified filename tag
|
||||
* in eeprom interrupt, eeprom polled and flash polled
|
||||
* files to include them in doxygen examples.
|
||||
* 3.1 tjs 04/12/18 InputClockHz parameter copied in instance for use in
|
||||
* application. CR#998910
|
||||
* 3.2 aru 01/20/19 Fixes violations according to MISRAC-2012
|
||||
* in safety mode and done changes such as
|
||||
* Declared the pointer param as Pointer to const.
|
||||
* 3.2 nsk 03/26/19 Add support for versal - CR #1025583.
|
||||
* 3.3 mus 04/05/19 Replaced XPLAT_versal macro with XPLAT_VERSAL, to be in
|
||||
* sync with standalone BSP
|
||||
* 3.3 akm 08/06/19 Initialized DeviceID in XSpiPs_CfgInitialize function.
|
||||
* 3.5 akm 09/02/20 Updated the Makefile to support parallel make execution.
|
||||
* 3.6 sg 02/05/21 Added polled mode example for TPM device.
|
||||
* 3.7 asa 04/01/22 Updated version to 3.7. Fixed issue in selftest
|
||||
* example.
|
||||
* 3.9 sb 07/05/23 Added support for system device-tree flow.
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef XSPIPS_H /* prevent circular inclusions */
|
||||
#define XSPIPS_H /* by using protection macros */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xstatus.h"
|
||||
#include "xspips_hw.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/** @name Configuration options
|
||||
*
|
||||
* The following options are supported to enable/disable certain features of
|
||||
* an SPI device. Each of the options is a bit mask, so more than one may be
|
||||
* specified.
|
||||
*
|
||||
* <b>The Master option</b> configures the SPI device as a master.
|
||||
* By default, the device is a slave.
|
||||
*
|
||||
* The <b>Active Low Clock option</b> configures the device's clock polarity.
|
||||
* Setting this option means the clock is active low and the SCK signal idles
|
||||
* high. By default, the clock is active high and SCK idles low.
|
||||
*
|
||||
* The <b>Clock Phase option</b> configures the SPI device for one of two
|
||||
* transfer formats. A clock phase of 0, the default, means data is valid on
|
||||
* the first SCK edge (rising or falling) after the slave select (SS) signal
|
||||
* has been asserted. A clock phase of 1 means data is valid on the second SCK
|
||||
* edge (rising or falling) after SS has been asserted.
|
||||
*
|
||||
* The <b>Slave Select Decode Enable option</b> selects how the SPI_SS_outN are
|
||||
* controlled by the SPI Slave Select Decode bits.
|
||||
* 0: Use this setting for the standard configuration of up to three slave
|
||||
* select outputs. Only one of the three slave select outputs will be low.
|
||||
* (Default)
|
||||
* 1: Use this setting for the optional configuration of an additional decoder
|
||||
* to support 8 slave select outputs. SPI_SS_outN reflects the value in the
|
||||
* register.
|
||||
*
|
||||
* The <b>SPI Force Slave Select option</b> is used to enable manual control of
|
||||
* the signals SPI_SS_outN.
|
||||
* 0: The SPI_SS_outN signals are controlled by the SPI controller during
|
||||
* transfers. (Default)
|
||||
* 1: The SPI_SS_outN signal indicated by the Slave Select Control bit is
|
||||
* forced active (driven low) regardless of any transfers in progress.
|
||||
*
|
||||
* NOTE: The driver will handle setting and clearing the Slave Select when
|
||||
* the user sets the "FORCE_SSELECT_OPTION". Using this option will allow the
|
||||
* SPI clock to be set to a faster speed. If the SPI clock is too fast, the
|
||||
* processor cannot empty and refill the FIFOs before the TX FIFO is empty
|
||||
* When the SPI hardware is controlling the Slave Select signals, this
|
||||
* will cause slave to be de-selected and terminate the transfer.
|
||||
*
|
||||
* The <b>Manual Start option</b> is used to enable manual control of
|
||||
* the Start command to perform data transfer.
|
||||
* 0: The Start command is controlled by the SPI controller during
|
||||
* transfers(Default). Data transmission starts as soon as there is data in
|
||||
* the TXFIFO and stalls when the TXFIFO is empty
|
||||
* 1: The Start command must be issued by software to perform data transfer.
|
||||
* Bit 15 of Configuration register is used to issue Start command. This bit
|
||||
* must be set whenever TXFIFO is filled with new data.
|
||||
*
|
||||
* NOTE: The driver will set the Manual Start Enable bit in Configuration
|
||||
* Register, if Manual Start option is selected. Software will issue
|
||||
* Manual Start command whenever TXFIFO is filled with data. When there is
|
||||
* no further data, driver will clear the Manual Start Enable bit.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
#define XSPIPS_MASTER_OPTION 0x00000001U /**< Master mode option */
|
||||
#define XSPIPS_CLK_ACTIVE_LOW_OPTION 0x00000002U /**< Active Low Clock option */
|
||||
#define XSPIPS_CLK_PHASE_1_OPTION 0x00000004U /**< Clock Phase one option */
|
||||
#define XSPIPS_DECODE_SSELECT_OPTION 0x00000008U /**< Select 16 slaves Option */
|
||||
#define XSPIPS_FORCE_SSELECT_OPTION 0x00000010U /**< Force Slave Select */
|
||||
#define XSPIPS_MANUAL_START_OPTION 0x00000020U /**< Manual Start mode option */
|
||||
/*@}*/
|
||||
|
||||
|
||||
/** @name SPI Clock Prescaler options
|
||||
* The SPI Clock Prescaler Configuration bits are used to program master mode
|
||||
* bit rate. The bit rate can be programmed in divide-by-two decrements from
|
||||
* pclk/4 to pclk/256.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define XSPIPS_CLK_PRESCALE_4 0x01U /**< PCLK/4 Prescaler */
|
||||
#define XSPIPS_CLK_PRESCALE_8 0x02U /**< PCLK/8 Prescaler */
|
||||
#define XSPIPS_CLK_PRESCALE_16 0x03U /**< PCLK/16 Prescaler */
|
||||
#define XSPIPS_CLK_PRESCALE_32 0x04U /**< PCLK/32 Prescaler */
|
||||
#define XSPIPS_CLK_PRESCALE_64 0x05U /**< PCLK/64 Prescaler */
|
||||
#define XSPIPS_CLK_PRESCALE_128 0x06U /**< PCLK/128 Prescaler */
|
||||
#define XSPIPS_CLK_PRESCALE_256 0x07U /**< PCLK/256 Prescaler */
|
||||
/*@}*/
|
||||
|
||||
|
||||
/** @name Callback events
|
||||
*
|
||||
* These constants specify the handler events that are passed to
|
||||
* a handler from the driver. These constants are not bit masks such that
|
||||
* only one will be passed at a time to the handler.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
#define XSPIPS_EVENT_MODE_FAULT 1U /**< Mode fault error */
|
||||
#define XSPIPS_EVENT_TRANSFER_DONE 2U /**< Transfer done */
|
||||
#define XSPIPS_EVENT_TRANSMIT_UNDERRUN 3U /**< TX FIFO empty */
|
||||
#define XSPIPS_EVENT_RECEIVE_OVERRUN 4U /**< Receive data loss because
|
||||
RX FIFO full */
|
||||
/*@}*/
|
||||
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
/**
|
||||
* The handler data type allows the user to define a callback function to
|
||||
* handle the asynchronous processing for the SPI device. The application
|
||||
* using this driver is expected to define a handler of this type to support
|
||||
* interrupt driven mode. The handler executes in an interrupt context, so
|
||||
* only minimal processing should be performed.
|
||||
*
|
||||
* @param CallBackRef is the callback reference passed in by the upper
|
||||
* layer when setting the callback functions, and passed back to
|
||||
* the upper layer when the callback is invoked. Its type is
|
||||
* not important to the driver, so it is a void pointer.
|
||||
* @param StatusEvent holds one or more status events that have occurred.
|
||||
* See the XSpiPs_SetStatusHandler() for details on the status
|
||||
* events that can be passed in the callback.
|
||||
* @param ByteCount indicates how many bytes of data were successfully
|
||||
* transferred. This may be less than the number of bytes
|
||||
* requested if the status event indicates an error.
|
||||
*/
|
||||
typedef void (*XSpiPs_StatusHandler) (const void *CallBackRef, u32 StatusEvent,
|
||||
u32 ByteCount);
|
||||
|
||||
/**
|
||||
* This typedef contains configuration information for the device.
|
||||
*/
|
||||
typedef struct {
|
||||
#ifndef SDT
|
||||
u16 DeviceId; /**< Unique ID of device */
|
||||
#else
|
||||
char *Name;
|
||||
#endif
|
||||
u32 BaseAddress; /**< Base address of the device */
|
||||
u32 InputClockHz; /**< Input clock frequency */
|
||||
u16 IntrId; /**< Bits[11:0] Interrupt-id Bits[15:12]
|
||||
* trigger type and level flags */
|
||||
UINTPTR IntrParent; /**< Bit[0] Interrupt parent type Bit[64/32:1]
|
||||
* Parent base address */
|
||||
} XSpiPs_Config;
|
||||
|
||||
/**
|
||||
* The XSpiPs driver instance data. The user is required to allocate a
|
||||
* variable of this type for every SPI device in the system. A pointer
|
||||
* to a variable of this type is then passed to the driver API functions.
|
||||
*/
|
||||
typedef struct {
|
||||
XSpiPs_Config Config; /**< Configuration structure */
|
||||
u32 IsReady; /**< Device is initialized and ready */
|
||||
|
||||
u8 *SendBufferPtr; /**< Buffer to send (state) */
|
||||
u8 *RecvBufferPtr; /**< Buffer to receive (state) */
|
||||
u32 RequestedBytes; /**< Number of bytes to transfer (state) */
|
||||
u32 RemainingBytes; /**< Number of bytes left to transfer(state) */
|
||||
u32 IsBusy; /**< A transfer is in progress (state) */
|
||||
u32 SlaveSelect; /**< The slave select value when
|
||||
XSPIPS_FORCE_SSELECT_OPTION is set */
|
||||
|
||||
XSpiPs_StatusHandler StatusHandler;
|
||||
void *StatusRef; /**< Callback reference for status handler */
|
||||
|
||||
} XSpiPs;
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
/****************************************************************************/
|
||||
/*
|
||||
*
|
||||
* Check in OptionsTable if Manual Start Option is enabled or disabled.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XSpiPs instance.
|
||||
*
|
||||
* @return
|
||||
* - TRUE if option is set
|
||||
* - FALSE if option is not set
|
||||
*
|
||||
* @note C-Style signature:
|
||||
* u8 XSpiPs_IsManualStart(XSpiPs *InstancePtr)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XSpiPs_IsManualStart(InstancePtr) \
|
||||
(((XSpiPs_GetOptions(InstancePtr) & \
|
||||
XSPIPS_MANUAL_START_OPTION) != (u32)0U) ? TRUE : FALSE)
|
||||
|
||||
/****************************************************************************/
|
||||
/*
|
||||
*
|
||||
* Check in OptionsTable if Manual Chip Select Option is enabled or disabled.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XSpiPs instance.
|
||||
*
|
||||
* @return
|
||||
* - TRUE if option is set
|
||||
* - FALSE if option is not set
|
||||
*
|
||||
* @note C-Style signature:
|
||||
* u8 XSpiPs_IsManualChipSelect(XSpiPs *InstancePtr)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XSpiPs_IsManualChipSelect(InstancePtr) \
|
||||
(((XSpiPs_GetOptions(InstancePtr) & \
|
||||
XSPIPS_FORCE_SSELECT_OPTION) != (u32)0U) ? TRUE : FALSE)
|
||||
|
||||
/****************************************************************************/
|
||||
/*
|
||||
*
|
||||
* Check in OptionsTable if Decode Slave Select option is enabled or disabled.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XSpiPs instance.
|
||||
*
|
||||
* @return
|
||||
* - TRUE if option is set
|
||||
* - FALSE if option is not set
|
||||
*
|
||||
* @note C-Style signature:
|
||||
* u8 XSpiPs_IsDecodeSSelect(XSpiPs *InstancePtr)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XSpiPs_IsDecodeSSelect(InstancePtr) \
|
||||
(((XSpiPs_GetOptions(InstancePtr) & \
|
||||
XSPIPS_DECODE_SSELECT_OPTION) != (u32)0U) ? TRUE : FALSE)
|
||||
|
||||
/****************************************************************************/
|
||||
/*
|
||||
*
|
||||
* Check in OptionsTable if Master Option is enabled or disabled.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XSpiPs instance.
|
||||
*
|
||||
* @return
|
||||
* - TRUE if option is set
|
||||
* - FALSE if option is not set
|
||||
*
|
||||
* @note C-Style signature:
|
||||
* u8 XSpiPs_IsMaster(XSpiPs *InstancePtr)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XSpiPs_IsMaster(InstancePtr) \
|
||||
(((XSpiPs_GetOptions(InstancePtr) & \
|
||||
XSPIPS_MASTER_OPTION) != (u32)0U) ? TRUE : FALSE)
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Set the contents of the slave idle count register.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XSpiPs instance.
|
||||
* @param RegisterValue is the value to be written, valid values are
|
||||
* 0-255.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @note
|
||||
* C-Style signature:
|
||||
* void XSpiPs_SetSlaveIdle(XSpiPs *InstancePtr, u32 RegisterValue)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XSpiPs_SetSlaveIdle(InstancePtr, RegisterValue) \
|
||||
XSpiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
|
||||
XSPIPS_SICR_OFFSET, (RegisterValue))
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Get the contents of the slave idle count register. Use the XSPIPS_SICR_*
|
||||
* constants defined in xspips_hw.h to interpret the bit-mask returned.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XSpiPs instance.
|
||||
*
|
||||
* @return 8-bit value representing the contents of the SIC register.
|
||||
*
|
||||
* @note C-Style signature:
|
||||
* u32 XSpiPs_GetSlaveIdle(XSpiPs *InstancePtr)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XSpiPs_GetSlaveIdle(InstancePtr) \
|
||||
XSpiPs_In32(((InstancePtr)->Config.BaseAddress) + \
|
||||
XSPIPS_SICR_OFFSET)
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Set the contents of the transmit FIFO watermark register.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XSpiPs instance.
|
||||
* @param RegisterValue is the value to be written, valid values
|
||||
* are 1-128.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note
|
||||
* C-Style signature:
|
||||
* void XSpiPs_SetTXWatermark(XSpiPs *InstancePtr, u32 RegisterValue)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XSpiPs_SetTXWatermark(InstancePtr, RegisterValue) \
|
||||
XSpiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
|
||||
XSPIPS_TXWR_OFFSET, (RegisterValue))
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Get the contents of the transmit FIFO watermark register.
|
||||
* Use the XSPIPS_TXWR_* constants defined xspips_hw.h to interpret
|
||||
* the bit-mask returned.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XSpiPs instance.
|
||||
*
|
||||
* @return 8-bit value representing the contents of the TXWR register.
|
||||
*
|
||||
* @note C-Style signature:
|
||||
* u32 XSpiPs_GetTXWatermark(u32 *InstancePtr)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XSpiPs_GetTXWatermark(InstancePtr) \
|
||||
XSpiPs_In32(((InstancePtr)->Config.BaseAddress) + XSPIPS_TXWR_OFFSET)
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Set the contents of the receive FIFO watermark register.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XSpiPs instance.
|
||||
* @param RegisterValue is the value to be written, valid values
|
||||
* are 1-128.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note
|
||||
* C-Style signature:
|
||||
* void XSpiPs_SetRXWatermark(XSpiPs *InstancePtr, u32 RegisterValue)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XSpiPs_SetRXWatermark(InstancePtr, RegisterValue) \
|
||||
XSpiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
|
||||
XSPIPS_RXWR_OFFSET, (RegisterValue))
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Get the contents of the receive FIFO watermark register.
|
||||
* Use the XSPIPS_RXWR_* constants defined xspips_hw.h to interpret
|
||||
* the bit-mask returned.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XSpiPs instance.
|
||||
*
|
||||
* @return A 8-bit value representing the contents of the RXWR register.
|
||||
*
|
||||
* @note C-Style signature:
|
||||
* u32 XSpiPs_GetRXWatermark(u32 *InstancePtr)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XSpiPs_GetRXWatermark(InstancePtr) \
|
||||
XSpiPs_In32(((InstancePtr)->Config.BaseAddress) + XSPIPS_RXWR_OFFSET)
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Enable the device and uninhibit master transactions.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XSpiPs instance.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note C-Style signature:
|
||||
* void XSpiPs_Enable(u32 *InstancePtr)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XSpiPs_Enable(InstancePtr) \
|
||||
XSpiPs_Out32(((InstancePtr)->Config.BaseAddress) + XSPIPS_ER_OFFSET, \
|
||||
XSPIPS_ER_ENABLE_MASK)
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Disable the device.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XSpiPs instance.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note C-Style signature:
|
||||
* void XSpiPs_Disable(u32 *InstancePtr)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XSpiPs_Disable(InstancePtr) \
|
||||
XSpiPs_Out32(((InstancePtr)->Config.BaseAddress) + XSPIPS_ER_OFFSET, 0U)
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
/*
|
||||
* Initialization function, implemented in xspips_sinit.c
|
||||
*/
|
||||
#ifndef SDT
|
||||
XSpiPs_Config *XSpiPs_LookupConfig(u16 DeviceId);
|
||||
#else
|
||||
XSpiPs_Config *XSpiPs_LookupConfig(u32 BaseAddress);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Functions implemented in xspips.c
|
||||
*/
|
||||
s32 XSpiPs_CfgInitialize(XSpiPs *InstancePtr, const XSpiPs_Config *ConfigPtr,
|
||||
u32 EffectiveAddr);
|
||||
|
||||
void XSpiPs_Reset(XSpiPs *InstancePtr);
|
||||
|
||||
s32 XSpiPs_Transfer(XSpiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
|
||||
u32 ByteCount);
|
||||
|
||||
s32 XSpiPs_PolledTransfer(XSpiPs *InstancePtr, u8 *SendBufPtr,
|
||||
u8 *RecvBufPtr, u32 ByteCount);
|
||||
|
||||
void XSpiPs_SetStatusHandler(XSpiPs *InstancePtr, void *CallBackRef,
|
||||
XSpiPs_StatusHandler FunctionPtr);
|
||||
void XSpiPs_InterruptHandler(XSpiPs *InstancePtr);
|
||||
|
||||
void XSpiPs_Abort(XSpiPs *InstancePtr);
|
||||
|
||||
s32 XSpiPs_SetSlaveSelect(XSpiPs *InstancePtr, u8 SlaveSel);
|
||||
u8 XSpiPs_GetSlaveSelect(const XSpiPs *InstancePtr);
|
||||
|
||||
/*
|
||||
* Functions for selftest, in xspips_selftest.c
|
||||
*/
|
||||
s32 XSpiPs_SelfTest(XSpiPs *InstancePtr);
|
||||
|
||||
/*
|
||||
* Functions for options, in xspips_options.c
|
||||
*/
|
||||
s32 XSpiPs_SetOptions(const XSpiPs *InstancePtr, u32 Options);
|
||||
u32 XSpiPs_GetOptions(const XSpiPs *InstancePtr);
|
||||
|
||||
s32 XSpiPs_SetClkPrescaler(const XSpiPs *InstancePtr, u8 Prescaler);
|
||||
u8 XSpiPs_GetClkPrescaler(const XSpiPs *InstancePtr);
|
||||
|
||||
s32 XSpiPs_SetDelays(const XSpiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
|
||||
u8 DelayAfter, u8 DelayInit);
|
||||
void XSpiPs_GetDelays(const XSpiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
|
||||
u8 *DelayAfter, u8 *DelayInit);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* end of protection macro */
|
||||
/** @} */
|
||||
-287
@@ -1,287 +0,0 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xspips_hw.h
|
||||
* @addtogroup spips Overview
|
||||
* @{
|
||||
*
|
||||
* This header file contains the identifiers and basic driver functions (or
|
||||
* macros) that can be used to access the device. Other driver functions
|
||||
* are defined in xspips.h.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ------ -------- -----------------------------------------------
|
||||
* 1.00 drg/jz 01/25/10 First release
|
||||
* 1.02a sg 05/31/12 Updated XSPIPS_FIFO_DEPTH to 128 from 32 to match HW
|
||||
* for CR 658289
|
||||
* 1.04a sg 01/30/13 Created XSPIPS_CR_MODF_GEN_EN_MASK macro and added it
|
||||
* to XSPIPS_CR_RESET_STATE. Created
|
||||
* XSPIPS_IXR_WR_TO_CLR_MASK for interrupts which need
|
||||
* write-to-clear. Added shift and mask macros for d_nss
|
||||
* parameter. Added Rx Watermark mask.
|
||||
* 1.06a hk 08/22/13 Added prototypes of reset API and related constant
|
||||
* definitions.
|
||||
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef XSPIPS_HW_H /* prevent circular inclusions */
|
||||
#define XSPIPS_HW_H /* by using protection macros */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xil_types.h"
|
||||
#include "xil_assert.h"
|
||||
#include "xil_io.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/** @name Register Map
|
||||
*
|
||||
* Register offsets from the base address of an SPI device.
|
||||
* @{
|
||||
*/
|
||||
#define XSPIPS_CR_OFFSET 0x00U /**< Configuration */
|
||||
#define XSPIPS_SR_OFFSET 0x04U /**< Interrupt Status */
|
||||
#define XSPIPS_IER_OFFSET 0x08U /**< Interrupt Enable */
|
||||
#define XSPIPS_IDR_OFFSET 0x0CU /**< Interrupt Disable */
|
||||
#define XSPIPS_IMR_OFFSET 0x10U /**< Interrupt Enabled Mask */
|
||||
#define XSPIPS_ER_OFFSET 0x14U /**< Enable/Disable Register */
|
||||
#define XSPIPS_DR_OFFSET 0x18U /**< Delay Register */
|
||||
#define XSPIPS_TXD_OFFSET 0x1CU /**< Data Transmit Register */
|
||||
#define XSPIPS_RXD_OFFSET 0x20U /**< Data Receive Register */
|
||||
#define XSPIPS_SICR_OFFSET 0x24U /**< Slave Idle Count */
|
||||
#define XSPIPS_TXWR_OFFSET 0x28U /**< Transmit FIFO Watermark */
|
||||
#define XSPIPS_RXWR_OFFSET 0x2CU /**< Receive FIFO Watermark */
|
||||
/* @} */
|
||||
|
||||
/** @name Configuration Register
|
||||
*
|
||||
* This register contains various control bits that
|
||||
* affects the operation of an SPI device. Read/Write.
|
||||
* @{
|
||||
*/
|
||||
#define XSPIPS_CR_MODF_GEN_EN_MASK 0x00020000U /**< Modefail Generation
|
||||
Enable */
|
||||
#define XSPIPS_CR_MANSTRT_MASK 0x00010000U /**< Manual Transmission Start */
|
||||
#define XSPIPS_CR_MANSTRTEN_MASK 0x00008000U /**< Manual Transmission Start
|
||||
Enable */
|
||||
#define XSPIPS_CR_SSFORCE_MASK 0x00004000U /**< Force Slave Select */
|
||||
#define XSPIPS_CR_SSCTRL_MASK 0x00003C00U /**< Slave Select Decode */
|
||||
#define XSPIPS_CR_SSCTRL_SHIFT 10U /**< Slave Select Decode shift */
|
||||
#define XSPIPS_CR_SSCTRL_MAXIMUM 0xFU /**< Slave Select maximum value */
|
||||
#define XSPIPS_CR_SSDECEN_MASK 0x00000200U /**< Slave Select Decode Enable */
|
||||
|
||||
#define XSPIPS_CR_PRESC_MASK 0x00000038U /**< Prescaler Setting */
|
||||
#define XSPIPS_CR_PRESC_SHIFT 3U /**< Prescaler shift */
|
||||
#define XSPIPS_CR_PRESC_MAXIMUM 0x07U /**< Prescaler maximum value */
|
||||
|
||||
#define XSPIPS_CR_CPHA_MASK 0x00000004U /**< Phase Configuration */
|
||||
#define XSPIPS_CR_CPOL_MASK 0x00000002U /**< Polarity Configuration */
|
||||
|
||||
#define XSPIPS_CR_MSTREN_MASK 0x00000001U /**< Master Mode Enable */
|
||||
#define XSPIPS_CR_RESET_STATE 0x00020000U /**< Mode Fail Generation Enable */
|
||||
/* @} */
|
||||
|
||||
|
||||
/** @name SPI Interrupt Registers
|
||||
*
|
||||
* <b>SPI Status Register</b>
|
||||
*
|
||||
* This register holds the interrupt status flags for an SPI device. Some
|
||||
* of the flags are level triggered, which means that they are set as long
|
||||
* as the interrupt condition exists. Other flags are edge triggered,
|
||||
* which means they are set once the interrupt condition occurs and remain
|
||||
* set until they are cleared by software. The interrupts are cleared by
|
||||
* writing a '1' to the interrupt bit position in the Status Register.
|
||||
* Read/Write.
|
||||
*
|
||||
* <b>SPI Interrupt Enable Register</b>
|
||||
*
|
||||
* This register is used to enable chosen interrupts for an SPI device.
|
||||
* Writing a '1' to a bit in this register sets the corresponding bit in the
|
||||
* SPI Interrupt Mask register. Write only.
|
||||
*
|
||||
* <b>SPI Interrupt Disable Register </b>
|
||||
*
|
||||
* This register is used to disable chosen interrupts for an SPI device.
|
||||
* Writing a '1' to a bit in this register clears the corresponding bit in the
|
||||
* SPI Interrupt Mask register. Write only.
|
||||
*
|
||||
* <b>SPI Interrupt Mask Register</b>
|
||||
*
|
||||
* This register shows the enabled/disabled interrupts of an SPI device.
|
||||
* Read only.
|
||||
*
|
||||
* All four registers have the same bit definitions. They are only defined once
|
||||
* for each of the Interrupt Enable Register, Interrupt Disable Register,
|
||||
* Interrupt Mask Register, and Channel Interrupt Status Register
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define XSPIPS_IXR_TXUF_MASK 0x00000040U /**< Tx FIFO Underflow */
|
||||
#define XSPIPS_IXR_RXFULL_MASK 0x00000020U /**< Rx FIFO Full */
|
||||
#define XSPIPS_IXR_RXNEMPTY_MASK 0x00000010U /**< Rx FIFO Not Empty */
|
||||
#define XSPIPS_IXR_TXFULL_MASK 0x00000008U /**< Tx FIFO Full */
|
||||
#define XSPIPS_IXR_TXOW_MASK 0x00000004U /**< Tx FIFO Overwater */
|
||||
#define XSPIPS_IXR_MODF_MASK 0x00000002U /**< Mode Fault */
|
||||
#define XSPIPS_IXR_RXOVR_MASK 0x00000001U /**< Rx FIFO Overrun */
|
||||
#define XSPIPS_IXR_DFLT_MASK 0x00000027U /**< Default interrupts
|
||||
mask */
|
||||
#define XSPIPS_IXR_WR_TO_CLR_MASK 0x00000043U /**< Interrupts which
|
||||
need write to clear */
|
||||
#define XSPIPS_ISR_RESET_STATE 0x04U /**< Default to tx/rx
|
||||
* reg empty */
|
||||
#define XSPIPS_IXR_DISABLE_ALL_MASK 0x00000043U /**< Disable all
|
||||
* interrupts */
|
||||
/* @} */
|
||||
|
||||
|
||||
/** @name Enable Register
|
||||
*
|
||||
* This register is used to enable or disable an SPI device.
|
||||
* Read/Write
|
||||
* @{
|
||||
*/
|
||||
#define XSPIPS_ER_ENABLE_MASK 0x00000001U /**< SPI Enable Bit Mask */
|
||||
/* @} */
|
||||
|
||||
|
||||
/** @name Delay Register
|
||||
*
|
||||
* This register is used to program timing delays in
|
||||
* slave mode. Read/Write
|
||||
* @{
|
||||
*/
|
||||
#define XSPIPS_DR_NSS_MASK 0xFF000000U /**< Delay for slave select
|
||||
* de-assertion between
|
||||
* word transfers mask */
|
||||
#define XSPIPS_DR_NSS_SHIFT 24U /**< Delay for slave select
|
||||
* de-assertion between
|
||||
* word transfers shift */
|
||||
#define XSPIPS_DR_BTWN_MASK 0x00FF0000U /**< Delay Between Transfers mask */
|
||||
#define XSPIPS_DR_BTWN_SHIFT 16U /**< Delay Between Transfers shift */
|
||||
#define XSPIPS_DR_AFTER_MASK 0x0000FF00U /**< Delay After Transfers mask */
|
||||
#define XSPIPS_DR_AFTER_SHIFT 8U /**< Delay After Transfers shift */
|
||||
#define XSPIPS_DR_INIT_MASK 0x000000FFU /**< Delay Initially mask */
|
||||
/* @} */
|
||||
|
||||
|
||||
/** @name Slave Idle Count Registers
|
||||
*
|
||||
* This register defines the number of pclk cycles the slave waits for a the
|
||||
* SPI clock to become stable in quiescent state before it can detect the start
|
||||
* of the next transfer in CPHA = 1 mode.
|
||||
* Read/Write
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
#define XSPIPS_SICR_MASK 0x000000FFU /**< Slave Idle Count Mask */
|
||||
/* @} */
|
||||
|
||||
|
||||
|
||||
/** @name Transmit FIFO Watermark Register
|
||||
*
|
||||
* This register defines the watermark setting for the Transmit FIFO. The
|
||||
* transmit FIFO is 128 bytes deep, so the register is 7 bits. Valid values
|
||||
* are 1 to 128.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
#define XSPIPS_TXWR_MASK 0x0000007FU /**< Transmit Watermark Mask */
|
||||
#define XSPIPS_TXWR_RESET_VALUE 0x00000001U /**< Transmit Watermark
|
||||
* register reset value */
|
||||
/* @} */
|
||||
|
||||
/** @name Receive FIFO Watermark Register
|
||||
*
|
||||
* This register defines the watermark setting for the Receive FIFO. The
|
||||
* receive FIFO is 128 bytes deep, so the register is 7 bits. Valid values
|
||||
* are 1 to 128.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
#define XSPIPS_RXWR_MASK 0x0000007FU /**< Receive Watermark Mask */
|
||||
#define XSPIPS_RXWR_RESET_VALUE 0x00000001U /**< Receive Watermark
|
||||
* register reset value */
|
||||
/* @} */
|
||||
|
||||
/** @name FIFO Depth
|
||||
*
|
||||
* This macro provides the depth of transmit FIFO and receive FIFO.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
#define XSPIPS_FIFO_DEPTH 128U /**< FIFO depth of Tx and Rx */
|
||||
/* @} */
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
#define XSpiPs_In32 Xil_In32
|
||||
#define XSpiPs_Out32 Xil_Out32
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Read a register.
|
||||
*
|
||||
* @param BaseAddress contains the base address of the device.
|
||||
* @param RegOffset contains the offset from the 1st register of the
|
||||
* device to the target register.
|
||||
*
|
||||
* @return The value read from the register.
|
||||
*
|
||||
* @note C-Style signature:
|
||||
* u32 XSpiPs_ReadReg(u32 BaseAddress. int RegOffset)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XSpiPs_ReadReg(BaseAddress, RegOffset) \
|
||||
XSpiPs_In32((BaseAddress) + (RegOffset))
|
||||
|
||||
/***************************************************************************/
|
||||
/**
|
||||
* Write to a register.
|
||||
*
|
||||
* @param BaseAddress contains the base address of the device.
|
||||
* @param RegOffset contains the offset from the 1st register of the
|
||||
* device to target register.
|
||||
* @param RegisterValue is the value to be written to the register.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note C-Style signature:
|
||||
* void XSpiPs_WriteReg(u32 BaseAddress, int RegOffset,
|
||||
* u32 RegisterValue)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XSpiPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
|
||||
XSpiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
void XSpiPs_ResetHw(u32 BaseAddress);
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* end of protection macro */
|
||||
/** @} */
|
||||
-22
@@ -1,22 +0,0 @@
|
||||
# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
# SPDX-License-Identifier: MIT
|
||||
cmake_minimum_required(VERSION 3.15)
|
||||
project(spips)
|
||||
|
||||
find_package(common)
|
||||
collector_create (PROJECT_LIB_HEADERS "${CMAKE_CURRENT_SOURCE_DIR}")
|
||||
collector_create (PROJECT_LIB_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}")
|
||||
include_directories(${CMAKE_BINARY_DIR}/include)
|
||||
collect (PROJECT_LIB_SOURCES xspips.c)
|
||||
collect (PROJECT_LIB_HEADERS xspips.h)
|
||||
collect (PROJECT_LIB_SOURCES xspips_g.c)
|
||||
collect (PROJECT_LIB_SOURCES xspips_hw.c)
|
||||
collect (PROJECT_LIB_HEADERS xspips_hw.h)
|
||||
collect (PROJECT_LIB_SOURCES xspips_options.c)
|
||||
collect (PROJECT_LIB_SOURCES xspips_selftest.c)
|
||||
collect (PROJECT_LIB_SOURCES xspips_sinit.c)
|
||||
collector_list (_sources PROJECT_LIB_SOURCES)
|
||||
collector_list (_headers PROJECT_LIB_HEADERS)
|
||||
file(COPY ${_headers} DESTINATION ${CMAKE_BINARY_DIR}/include)
|
||||
add_library(spips STATIC ${_sources})
|
||||
set_target_properties(spips PROPERTIES LINKER_LANGUAGE C)
|
||||
-39
@@ -1,39 +0,0 @@
|
||||
DRIVER_LIB_VERSION = 1.0
|
||||
COMPILER=
|
||||
ARCHIVER=
|
||||
CP=cp
|
||||
COMPILER_FLAGS=
|
||||
EXTRA_COMPILER_FLAGS=
|
||||
LIB=libxil.a
|
||||
|
||||
CC_FLAGS = $(COMPILER_FLAGS)
|
||||
ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
|
||||
|
||||
RELEASEDIR=../../../lib/
|
||||
INCLUDEDIR=../../../include/
|
||||
INCLUDES=-I./. -I$(INCLUDEDIR)
|
||||
|
||||
SRCFILES:=$(wildcard *.c)
|
||||
|
||||
OBJECTS = $(addprefix $(RELEASEDIR), $(addsuffix .o, $(basename $(wildcard *.c))))
|
||||
|
||||
libs: $(OBJECTS)
|
||||
|
||||
DEPFILES := $(SRCFILES:%.c=$(RELEASEDIR)%.d)
|
||||
|
||||
include $(wildcard $(DEPFILES))
|
||||
|
||||
include $(wildcard ../../../../dep.mk)
|
||||
|
||||
$(RELEASEDIR)%.o: %.c
|
||||
${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(DEPENDENCY_FLAGS) $< -o $@
|
||||
|
||||
.PHONY: include
|
||||
include: $(addprefix $(INCLUDEDIR),$(wildcard *.h))
|
||||
|
||||
$(INCLUDEDIR)%.h: %.h
|
||||
$(CP) $< $@
|
||||
|
||||
clean:
|
||||
rm -rf ${OBJECTS}
|
||||
rm -rf $(DEPFILES)
|
||||
-1146
File diff suppressed because it is too large
Load Diff
-703
@@ -1,703 +0,0 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2017 - 2022 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xspips.h
|
||||
* @addtogroup spips Overview
|
||||
* @{
|
||||
* @details
|
||||
*
|
||||
* This file contains the implementation of the XSpiPs driver. It works for
|
||||
* both the master and slave mode. User documentation for the driver functions
|
||||
* is contained in this file in the form of comment blocks at the front of each
|
||||
* function.
|
||||
*
|
||||
* An SPI device connects to an SPI bus through a 4-wire serial interface.
|
||||
* The SPI bus is a full-duplex, synchronous bus that facilitates communication
|
||||
* between one master and one slave. The device is always full-duplex,
|
||||
* which means that for every byte sent, one is received, and vice-versa.
|
||||
* The master controls the clock, so it can regulate when it wants to
|
||||
* send or receive data. The slave is under control of the master, it must
|
||||
* respond quickly since it has no control of the clock and must send/receive
|
||||
* data as fast or as slow as the master does.
|
||||
*
|
||||
* <b>Initialization & Configuration</b>
|
||||
*
|
||||
* The XSpiPs_Config structure is used by the driver to configure itself. This
|
||||
* configuration structure is typically created by the tool-chain based on HW
|
||||
* build properties.
|
||||
*
|
||||
* To support multiple runtime loading and initialization strategies employed by
|
||||
* various operating systems, the driver instance can be initialized in the
|
||||
* following way:
|
||||
* - XSpiPs_LookupConfig(DeviceId) - Use the divide identifier to find the
|
||||
* static configuration structure defined in xspips_g.c. This is setup by
|
||||
* the tools. For some operating systems the config structure will be
|
||||
* initialized by the software and this call is not needed.
|
||||
* - XSpiPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
|
||||
* configuration structure provided by the caller. If running in a system
|
||||
* with address translation, the provided virtual memory base address
|
||||
* replaces the physical address present in the configuration structure.
|
||||
*
|
||||
* <b>Multiple Masters</b>
|
||||
*
|
||||
* More than one master can exist, but arbitration is the responsibility of
|
||||
* the higher layer software. The device driver does not perform any type of
|
||||
* arbitration.
|
||||
*
|
||||
* <b>Multiple Slaves</b>
|
||||
*
|
||||
* Contention between multiple masters is detected by the hardware, in which
|
||||
* case a mode fault occurs on the device. The device is disabled immediately
|
||||
* by hardware, and the current word transfer is stopped. The Aborted word
|
||||
* transfer due to the mode fault is resumed once the devie is enabled again.
|
||||
*
|
||||
* <b>Modes of Operation</b>
|
||||
*
|
||||
* There are four modes to perform a data transfer and the selection of a mode
|
||||
* is based on Chip Select(CS) and Start. These two options individually, can
|
||||
* be controlled either by software(Manual) or hardware(Auto).
|
||||
* - Auto CS: Chip select is automatically asserted as soon as the first word
|
||||
* is written into the TXFIFO and deasserted when the TXFIFO becomes
|
||||
* empty
|
||||
* - Manual CS: Software must assert and deassert CS.
|
||||
* - Auto Start: Data transmission starts as soon as there is data in the
|
||||
* TXFIFO and stalls when the TXFIFO is empty
|
||||
* - Manual Start: Software must start data transmission at the beginning of
|
||||
* the transaction or whenever the TXFIFO has become empty
|
||||
*
|
||||
* The preferred combination is Manual CS and Auto Start.
|
||||
* In this combination, the software asserts CS before loading any data into
|
||||
* TXFIFO. In Auto Start mode, whenever data is in TXFIFO, controller sends it
|
||||
* out until TXFIFO becomes empty. The software reads the RXFIFO whenever the
|
||||
* data is available. If no further data, software disables CS.
|
||||
*
|
||||
* Risks/challenges of other combinations:
|
||||
* - Manual CS and Manual Start: Manual Start bit should be set after each
|
||||
* TXFIFO write otherwise there could be a race condition where the TXFIFO
|
||||
* becomes empty before the new word is written. In that case the
|
||||
* transmission stops.
|
||||
* - Auto CS with Manual or Auto Start: It is very difficult for software to
|
||||
* keep the TXFIFO filled. Whenever the TXFIFO runs empty, CS is deasserted.
|
||||
* This results in a single transaction to be split into multiple pieces each
|
||||
* with its own chip select. This will result in garbage data to be sent.
|
||||
*
|
||||
* <b>Interrupts</b>
|
||||
*
|
||||
* The user must connect the interrupt handler of the driver,
|
||||
* XSpiPs_InterruptHandler, to an interrupt system such that it will be
|
||||
* called when an interrupt occurs. This function does not save and restore
|
||||
* the processor context such that the user must provide this processing.
|
||||
*
|
||||
* The driver handles the following interrupts:
|
||||
* - Data Transmit Register/FIFO Underflow
|
||||
* - Data Receive Register/FIFO Full
|
||||
* - Data Receive Register/FIFO Not Empty
|
||||
* - Data Transmit Register/FIFO Full
|
||||
* - Data Transmit Register/FIFO Overwater
|
||||
* - Mode Fault Error
|
||||
* - Data Receive Register/FIFO Overrun
|
||||
*
|
||||
* The Data Transmit Register/FIFO Overwater interrupt -- indicates that the
|
||||
* SPI device has transmitted the data available to transmit, and now its data
|
||||
* register and FIFO is ready to accept more data. The driver uses this
|
||||
* interrupt to indicate progress while sending data. The driver may have
|
||||
* more data to send, in which case the data transmit register and FIFO is
|
||||
* filled for subsequent transmission. When this interrupt arrives and all
|
||||
* the data has been sent, the driver invokes the status callback with a
|
||||
* value of XST_SPI_TRANSFER_DONE to inform the upper layer software that
|
||||
* all data has been sent.
|
||||
*
|
||||
* The Data Transmit Register/FIFO Underflow interrupt -- indicates that,
|
||||
* as slave, the SPI device was required to transmit but there was no data
|
||||
* available to transmit in the transmit register (or FIFO). This may not
|
||||
* be an error if the master is not expecting data. But in the case where
|
||||
* the master is expecting data, this serves as a notification of such a
|
||||
* condition. The driver reports this condition to the upper layer
|
||||
* software through the status handler.
|
||||
*
|
||||
* The Data Receive Register/FIFO Overrun interrupt -- indicates that the SPI
|
||||
* device received data and subsequently dropped the data because the data
|
||||
* receive register and FIFO was full. The interrupt applies to both master
|
||||
* and slave operation. The driver reports this condition to the upper layer
|
||||
* software through the status handler. This likely indicates a problem with
|
||||
* the higher layer protocol, or a problem with the slave performance.
|
||||
*
|
||||
* The Mode Fault Error interrupt -- indicates that while configured as a
|
||||
* master, the device was selected as a slave by another master. This can be
|
||||
* used by the application for arbitration in a multimaster environment or to
|
||||
* indicate a problem with arbitration. When this interrupt occurs, the
|
||||
* driver invokes the status callback with a status value of
|
||||
* XST_SPI_MODE_FAULT. It is up to the application to resolve the conflict.
|
||||
* When configured as a slave, Mode Fault Error interrupt indicates that a slave
|
||||
* device was selected as a slave by a master, but the slave device was
|
||||
* disabled. When configured as a master, Mode Fault Error interrupt indicates
|
||||
* that another SPI device is acting as a master on the bus.
|
||||
*
|
||||
*
|
||||
* <b>Polled Operation</b>
|
||||
*
|
||||
* Transfer in polled mode is supported through a separate interface function
|
||||
* XSpiPs_PolledTransfer(). Unlike the transfer function in the interrupt mode,
|
||||
* this function blocks until all data has been sent/received.
|
||||
*
|
||||
* <b>Device Busy</b>
|
||||
*
|
||||
* Some operations are disallowed when the device is busy. The driver tracks
|
||||
* whether a device is busy. The device is considered busy when a data transfer
|
||||
* request is outstanding, and is considered not busy only when that transfer
|
||||
* completes (or is aborted with a mode fault error). This applies to both
|
||||
* master and slave devices.
|
||||
*
|
||||
* <b>Device Configuration</b>
|
||||
*
|
||||
* The device can be configured in various ways during the FPGA implementation
|
||||
* process. Configuration parameters are stored in the xspips_g.c file or
|
||||
* passed in via XSpiPs_CfgInitialize(). A table is defined where each entry
|
||||
* contains configuration information for an SPI device, including the base
|
||||
* address for the device.
|
||||
*
|
||||
* <b>RTOS Independence</b>
|
||||
*
|
||||
* This driver is intended to be RTOS and processor independent. It works with
|
||||
* physical addresses only. Any needs for dynamic memory management, threads or
|
||||
* thread mutual exclusion, virtual memory, or cache control must be satisfied
|
||||
* by the layer above this driver.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ------ -------- -----------------------------------------------
|
||||
* 1.00 drg/jz 01/25/10 First release
|
||||
* 1.00 sdm 10/25/11 Removed the Divide by 2 in the SPI Clock Prescaler
|
||||
* options as this is not supported in the device.
|
||||
* 1.01 sg 03/07/12 Updated the code to always clear the relevant bits
|
||||
* before writing to config register.
|
||||
* Always clear the slave select bits before write and
|
||||
* clear the bits to no slave at the end of transfer
|
||||
* Modified the Polled transfer transmit/receive logic.
|
||||
* Tx should wait on TXOW Interrupt and Rx on RXNEMTY.
|
||||
* 1.02 sg 05/31/12 Updated XSPIPS_FIFO_DEPTH to 128 from 32 to match HW
|
||||
* for CR 658289
|
||||
* 1.03 sg 09/21/12 Added memory barrier dmb in polled transfer and
|
||||
* interrupt handler to overcome the clock domain
|
||||
* crossing issue in the controller. For CR #679252.
|
||||
* 1.04a sg 01/30/13 Created XSPIPS_MANUAL_START_OPTION. Created macros
|
||||
* XSpiPs_IsMaster, XSpiPs_IsManualStart and
|
||||
* XSpiPs_IsManualChipSelect. Changed SPI
|
||||
* Enable/Disable macro argument from BaseAddress to
|
||||
* Instance Pointer. Added DelayNss argument to SetDelays
|
||||
* and GetDelays API's. Added macros to set/get the
|
||||
* RX Watermark value.Created macros XSpiPs_IsMaster,
|
||||
* XSpiPs_IsManualStart and XSpiPs_IsManualChipSelect.
|
||||
* Changed SPI transfer logic for polled and interrupt
|
||||
* modes to be based on filled tx fifo count and receive
|
||||
* based on it. RXNEMPTY interrupt is not used.
|
||||
* SetSlaveSelect API logic is modified to drive the bit
|
||||
* position low based on the slave select value
|
||||
* requested. GetSlaveSelect API will return the value
|
||||
* based on bit position that is low.
|
||||
* Created XSPIPS_CR_MODF_GEN_EN_MASK macro and added it
|
||||
* to XSPIPS_CR_RESET_STATE. Created
|
||||
* XSPIPS_IXR_WR_TO_CLR_MASK for interrupts which need
|
||||
* write-to-clear. Added shift and mask macros for d_nss
|
||||
* parameter. Added Rx Watermark mask.
|
||||
* 1.05a hk 26/04/13 Added disable and enable in XSpiPs_SetOptions when
|
||||
* CPOL/CPHA bits are set/reset. Fix for CR#707669.
|
||||
* 1.06a hk 08/22/13 Changed GetSlaveSelect function. CR# 727866.
|
||||
* Added masking ConfigReg before writing in SetSlaveSel
|
||||
* Added extended slave select support - CR#722569.
|
||||
* Added prototypes of reset API and related constant
|
||||
* definitions.
|
||||
* Added check for MODF in polled transfer function.
|
||||
* 3.0 vm 12/09/14 Modified driver source code for MISRA-C:2012 compliance.
|
||||
* Support for Zynq Ultrascale Mp added.
|
||||
* ms 03/17/17 Added readme.txt file in examples folder for doxygen
|
||||
* generation.
|
||||
* ms 04/05/17 Modified Comment lines in functions of spips
|
||||
* examples to recognize it as documentation block
|
||||
* for doxygen generation and also modified filename tag
|
||||
* in eeprom interrupt, eeprom polled and flash polled
|
||||
* files to include them in doxygen examples.
|
||||
* 3.1 tjs 04/12/18 InputClockHz parameter copied in instance for use in
|
||||
* application. CR#998910
|
||||
* 3.2 aru 01/20/19 Fixes violations according to MISRAC-2012
|
||||
* in safety mode and done changes such as
|
||||
* Declared the pointer param as Pointer to const.
|
||||
* 3.2 nsk 03/26/19 Add support for versal - CR #1025583.
|
||||
* 3.3 mus 04/05/19 Replaced XPLAT_versal macro with XPLAT_VERSAL, to be in
|
||||
* sync with standalone BSP
|
||||
* 3.3 akm 08/06/19 Initialized DeviceID in XSpiPs_CfgInitialize function.
|
||||
* 3.5 akm 09/02/20 Updated the Makefile to support parallel make execution.
|
||||
* 3.6 sg 02/05/21 Added polled mode example for TPM device.
|
||||
* 3.7 asa 04/01/22 Updated version to 3.7. Fixed issue in selftest
|
||||
* example.
|
||||
* 3.9 sb 07/05/23 Added support for system device-tree flow.
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef XSPIPS_H /* prevent circular inclusions */
|
||||
#define XSPIPS_H /* by using protection macros */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xstatus.h"
|
||||
#include "xspips_hw.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/** @name Configuration options
|
||||
*
|
||||
* The following options are supported to enable/disable certain features of
|
||||
* an SPI device. Each of the options is a bit mask, so more than one may be
|
||||
* specified.
|
||||
*
|
||||
* <b>The Master option</b> configures the SPI device as a master.
|
||||
* By default, the device is a slave.
|
||||
*
|
||||
* The <b>Active Low Clock option</b> configures the device's clock polarity.
|
||||
* Setting this option means the clock is active low and the SCK signal idles
|
||||
* high. By default, the clock is active high and SCK idles low.
|
||||
*
|
||||
* The <b>Clock Phase option</b> configures the SPI device for one of two
|
||||
* transfer formats. A clock phase of 0, the default, means data is valid on
|
||||
* the first SCK edge (rising or falling) after the slave select (SS) signal
|
||||
* has been asserted. A clock phase of 1 means data is valid on the second SCK
|
||||
* edge (rising or falling) after SS has been asserted.
|
||||
*
|
||||
* The <b>Slave Select Decode Enable option</b> selects how the SPI_SS_outN are
|
||||
* controlled by the SPI Slave Select Decode bits.
|
||||
* 0: Use this setting for the standard configuration of up to three slave
|
||||
* select outputs. Only one of the three slave select outputs will be low.
|
||||
* (Default)
|
||||
* 1: Use this setting for the optional configuration of an additional decoder
|
||||
* to support 8 slave select outputs. SPI_SS_outN reflects the value in the
|
||||
* register.
|
||||
*
|
||||
* The <b>SPI Force Slave Select option</b> is used to enable manual control of
|
||||
* the signals SPI_SS_outN.
|
||||
* 0: The SPI_SS_outN signals are controlled by the SPI controller during
|
||||
* transfers. (Default)
|
||||
* 1: The SPI_SS_outN signal indicated by the Slave Select Control bit is
|
||||
* forced active (driven low) regardless of any transfers in progress.
|
||||
*
|
||||
* NOTE: The driver will handle setting and clearing the Slave Select when
|
||||
* the user sets the "FORCE_SSELECT_OPTION". Using this option will allow the
|
||||
* SPI clock to be set to a faster speed. If the SPI clock is too fast, the
|
||||
* processor cannot empty and refill the FIFOs before the TX FIFO is empty
|
||||
* When the SPI hardware is controlling the Slave Select signals, this
|
||||
* will cause slave to be de-selected and terminate the transfer.
|
||||
*
|
||||
* The <b>Manual Start option</b> is used to enable manual control of
|
||||
* the Start command to perform data transfer.
|
||||
* 0: The Start command is controlled by the SPI controller during
|
||||
* transfers(Default). Data transmission starts as soon as there is data in
|
||||
* the TXFIFO and stalls when the TXFIFO is empty
|
||||
* 1: The Start command must be issued by software to perform data transfer.
|
||||
* Bit 15 of Configuration register is used to issue Start command. This bit
|
||||
* must be set whenever TXFIFO is filled with new data.
|
||||
*
|
||||
* NOTE: The driver will set the Manual Start Enable bit in Configuration
|
||||
* Register, if Manual Start option is selected. Software will issue
|
||||
* Manual Start command whenever TXFIFO is filled with data. When there is
|
||||
* no further data, driver will clear the Manual Start Enable bit.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
#define XSPIPS_MASTER_OPTION 0x00000001U /**< Master mode option */
|
||||
#define XSPIPS_CLK_ACTIVE_LOW_OPTION 0x00000002U /**< Active Low Clock option */
|
||||
#define XSPIPS_CLK_PHASE_1_OPTION 0x00000004U /**< Clock Phase one option */
|
||||
#define XSPIPS_DECODE_SSELECT_OPTION 0x00000008U /**< Select 16 slaves Option */
|
||||
#define XSPIPS_FORCE_SSELECT_OPTION 0x00000010U /**< Force Slave Select */
|
||||
#define XSPIPS_MANUAL_START_OPTION 0x00000020U /**< Manual Start mode option */
|
||||
/*@}*/
|
||||
|
||||
|
||||
/** @name SPI Clock Prescaler options
|
||||
* The SPI Clock Prescaler Configuration bits are used to program master mode
|
||||
* bit rate. The bit rate can be programmed in divide-by-two decrements from
|
||||
* pclk/4 to pclk/256.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define XSPIPS_CLK_PRESCALE_4 0x01U /**< PCLK/4 Prescaler */
|
||||
#define XSPIPS_CLK_PRESCALE_8 0x02U /**< PCLK/8 Prescaler */
|
||||
#define XSPIPS_CLK_PRESCALE_16 0x03U /**< PCLK/16 Prescaler */
|
||||
#define XSPIPS_CLK_PRESCALE_32 0x04U /**< PCLK/32 Prescaler */
|
||||
#define XSPIPS_CLK_PRESCALE_64 0x05U /**< PCLK/64 Prescaler */
|
||||
#define XSPIPS_CLK_PRESCALE_128 0x06U /**< PCLK/128 Prescaler */
|
||||
#define XSPIPS_CLK_PRESCALE_256 0x07U /**< PCLK/256 Prescaler */
|
||||
/*@}*/
|
||||
|
||||
|
||||
/** @name Callback events
|
||||
*
|
||||
* These constants specify the handler events that are passed to
|
||||
* a handler from the driver. These constants are not bit masks such that
|
||||
* only one will be passed at a time to the handler.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
#define XSPIPS_EVENT_MODE_FAULT 1U /**< Mode fault error */
|
||||
#define XSPIPS_EVENT_TRANSFER_DONE 2U /**< Transfer done */
|
||||
#define XSPIPS_EVENT_TRANSMIT_UNDERRUN 3U /**< TX FIFO empty */
|
||||
#define XSPIPS_EVENT_RECEIVE_OVERRUN 4U /**< Receive data loss because
|
||||
RX FIFO full */
|
||||
/*@}*/
|
||||
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
/**
|
||||
* The handler data type allows the user to define a callback function to
|
||||
* handle the asynchronous processing for the SPI device. The application
|
||||
* using this driver is expected to define a handler of this type to support
|
||||
* interrupt driven mode. The handler executes in an interrupt context, so
|
||||
* only minimal processing should be performed.
|
||||
*
|
||||
* @param CallBackRef is the callback reference passed in by the upper
|
||||
* layer when setting the callback functions, and passed back to
|
||||
* the upper layer when the callback is invoked. Its type is
|
||||
* not important to the driver, so it is a void pointer.
|
||||
* @param StatusEvent holds one or more status events that have occurred.
|
||||
* See the XSpiPs_SetStatusHandler() for details on the status
|
||||
* events that can be passed in the callback.
|
||||
* @param ByteCount indicates how many bytes of data were successfully
|
||||
* transferred. This may be less than the number of bytes
|
||||
* requested if the status event indicates an error.
|
||||
*/
|
||||
typedef void (*XSpiPs_StatusHandler) (const void *CallBackRef, u32 StatusEvent,
|
||||
u32 ByteCount);
|
||||
|
||||
/**
|
||||
* This typedef contains configuration information for the device.
|
||||
*/
|
||||
typedef struct {
|
||||
#ifndef SDT
|
||||
u16 DeviceId; /**< Unique ID of device */
|
||||
#else
|
||||
char *Name;
|
||||
#endif
|
||||
u32 BaseAddress; /**< Base address of the device */
|
||||
u32 InputClockHz; /**< Input clock frequency */
|
||||
u16 IntrId; /**< Bits[11:0] Interrupt-id Bits[15:12]
|
||||
* trigger type and level flags */
|
||||
UINTPTR IntrParent; /**< Bit[0] Interrupt parent type Bit[64/32:1]
|
||||
* Parent base address */
|
||||
} XSpiPs_Config;
|
||||
|
||||
/**
|
||||
* The XSpiPs driver instance data. The user is required to allocate a
|
||||
* variable of this type for every SPI device in the system. A pointer
|
||||
* to a variable of this type is then passed to the driver API functions.
|
||||
*/
|
||||
typedef struct {
|
||||
XSpiPs_Config Config; /**< Configuration structure */
|
||||
u32 IsReady; /**< Device is initialized and ready */
|
||||
|
||||
u8 *SendBufferPtr; /**< Buffer to send (state) */
|
||||
u8 *RecvBufferPtr; /**< Buffer to receive (state) */
|
||||
u32 RequestedBytes; /**< Number of bytes to transfer (state) */
|
||||
u32 RemainingBytes; /**< Number of bytes left to transfer(state) */
|
||||
u32 IsBusy; /**< A transfer is in progress (state) */
|
||||
u32 SlaveSelect; /**< The slave select value when
|
||||
XSPIPS_FORCE_SSELECT_OPTION is set */
|
||||
|
||||
XSpiPs_StatusHandler StatusHandler;
|
||||
void *StatusRef; /**< Callback reference for status handler */
|
||||
|
||||
} XSpiPs;
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
/****************************************************************************/
|
||||
/*
|
||||
*
|
||||
* Check in OptionsTable if Manual Start Option is enabled or disabled.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XSpiPs instance.
|
||||
*
|
||||
* @return
|
||||
* - TRUE if option is set
|
||||
* - FALSE if option is not set
|
||||
*
|
||||
* @note C-Style signature:
|
||||
* u8 XSpiPs_IsManualStart(XSpiPs *InstancePtr)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XSpiPs_IsManualStart(InstancePtr) \
|
||||
(((XSpiPs_GetOptions(InstancePtr) & \
|
||||
XSPIPS_MANUAL_START_OPTION) != (u32)0U) ? TRUE : FALSE)
|
||||
|
||||
/****************************************************************************/
|
||||
/*
|
||||
*
|
||||
* Check in OptionsTable if Manual Chip Select Option is enabled or disabled.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XSpiPs instance.
|
||||
*
|
||||
* @return
|
||||
* - TRUE if option is set
|
||||
* - FALSE if option is not set
|
||||
*
|
||||
* @note C-Style signature:
|
||||
* u8 XSpiPs_IsManualChipSelect(XSpiPs *InstancePtr)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XSpiPs_IsManualChipSelect(InstancePtr) \
|
||||
(((XSpiPs_GetOptions(InstancePtr) & \
|
||||
XSPIPS_FORCE_SSELECT_OPTION) != (u32)0U) ? TRUE : FALSE)
|
||||
|
||||
/****************************************************************************/
|
||||
/*
|
||||
*
|
||||
* Check in OptionsTable if Decode Slave Select option is enabled or disabled.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XSpiPs instance.
|
||||
*
|
||||
* @return
|
||||
* - TRUE if option is set
|
||||
* - FALSE if option is not set
|
||||
*
|
||||
* @note C-Style signature:
|
||||
* u8 XSpiPs_IsDecodeSSelect(XSpiPs *InstancePtr)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XSpiPs_IsDecodeSSelect(InstancePtr) \
|
||||
(((XSpiPs_GetOptions(InstancePtr) & \
|
||||
XSPIPS_DECODE_SSELECT_OPTION) != (u32)0U) ? TRUE : FALSE)
|
||||
|
||||
/****************************************************************************/
|
||||
/*
|
||||
*
|
||||
* Check in OptionsTable if Master Option is enabled or disabled.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XSpiPs instance.
|
||||
*
|
||||
* @return
|
||||
* - TRUE if option is set
|
||||
* - FALSE if option is not set
|
||||
*
|
||||
* @note C-Style signature:
|
||||
* u8 XSpiPs_IsMaster(XSpiPs *InstancePtr)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XSpiPs_IsMaster(InstancePtr) \
|
||||
(((XSpiPs_GetOptions(InstancePtr) & \
|
||||
XSPIPS_MASTER_OPTION) != (u32)0U) ? TRUE : FALSE)
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Set the contents of the slave idle count register.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XSpiPs instance.
|
||||
* @param RegisterValue is the value to be written, valid values are
|
||||
* 0-255.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @note
|
||||
* C-Style signature:
|
||||
* void XSpiPs_SetSlaveIdle(XSpiPs *InstancePtr, u32 RegisterValue)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XSpiPs_SetSlaveIdle(InstancePtr, RegisterValue) \
|
||||
XSpiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
|
||||
XSPIPS_SICR_OFFSET, (RegisterValue))
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Get the contents of the slave idle count register. Use the XSPIPS_SICR_*
|
||||
* constants defined in xspips_hw.h to interpret the bit-mask returned.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XSpiPs instance.
|
||||
*
|
||||
* @return 8-bit value representing the contents of the SIC register.
|
||||
*
|
||||
* @note C-Style signature:
|
||||
* u32 XSpiPs_GetSlaveIdle(XSpiPs *InstancePtr)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XSpiPs_GetSlaveIdle(InstancePtr) \
|
||||
XSpiPs_In32(((InstancePtr)->Config.BaseAddress) + \
|
||||
XSPIPS_SICR_OFFSET)
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Set the contents of the transmit FIFO watermark register.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XSpiPs instance.
|
||||
* @param RegisterValue is the value to be written, valid values
|
||||
* are 1-128.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note
|
||||
* C-Style signature:
|
||||
* void XSpiPs_SetTXWatermark(XSpiPs *InstancePtr, u32 RegisterValue)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XSpiPs_SetTXWatermark(InstancePtr, RegisterValue) \
|
||||
XSpiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
|
||||
XSPIPS_TXWR_OFFSET, (RegisterValue))
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Get the contents of the transmit FIFO watermark register.
|
||||
* Use the XSPIPS_TXWR_* constants defined xspips_hw.h to interpret
|
||||
* the bit-mask returned.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XSpiPs instance.
|
||||
*
|
||||
* @return 8-bit value representing the contents of the TXWR register.
|
||||
*
|
||||
* @note C-Style signature:
|
||||
* u32 XSpiPs_GetTXWatermark(u32 *InstancePtr)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XSpiPs_GetTXWatermark(InstancePtr) \
|
||||
XSpiPs_In32(((InstancePtr)->Config.BaseAddress) + XSPIPS_TXWR_OFFSET)
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Set the contents of the receive FIFO watermark register.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XSpiPs instance.
|
||||
* @param RegisterValue is the value to be written, valid values
|
||||
* are 1-128.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note
|
||||
* C-Style signature:
|
||||
* void XSpiPs_SetRXWatermark(XSpiPs *InstancePtr, u32 RegisterValue)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XSpiPs_SetRXWatermark(InstancePtr, RegisterValue) \
|
||||
XSpiPs_Out32(((InstancePtr)->Config.BaseAddress) + \
|
||||
XSPIPS_RXWR_OFFSET, (RegisterValue))
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Get the contents of the receive FIFO watermark register.
|
||||
* Use the XSPIPS_RXWR_* constants defined xspips_hw.h to interpret
|
||||
* the bit-mask returned.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XSpiPs instance.
|
||||
*
|
||||
* @return A 8-bit value representing the contents of the RXWR register.
|
||||
*
|
||||
* @note C-Style signature:
|
||||
* u32 XSpiPs_GetRXWatermark(u32 *InstancePtr)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XSpiPs_GetRXWatermark(InstancePtr) \
|
||||
XSpiPs_In32(((InstancePtr)->Config.BaseAddress) + XSPIPS_RXWR_OFFSET)
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Enable the device and uninhibit master transactions.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XSpiPs instance.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note C-Style signature:
|
||||
* void XSpiPs_Enable(u32 *InstancePtr)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XSpiPs_Enable(InstancePtr) \
|
||||
XSpiPs_Out32(((InstancePtr)->Config.BaseAddress) + XSPIPS_ER_OFFSET, \
|
||||
XSPIPS_ER_ENABLE_MASK)
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Disable the device.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XSpiPs instance.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note C-Style signature:
|
||||
* void XSpiPs_Disable(u32 *InstancePtr)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XSpiPs_Disable(InstancePtr) \
|
||||
XSpiPs_Out32(((InstancePtr)->Config.BaseAddress) + XSPIPS_ER_OFFSET, 0U)
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
/*
|
||||
* Initialization function, implemented in xspips_sinit.c
|
||||
*/
|
||||
#ifndef SDT
|
||||
XSpiPs_Config *XSpiPs_LookupConfig(u16 DeviceId);
|
||||
#else
|
||||
XSpiPs_Config *XSpiPs_LookupConfig(u32 BaseAddress);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Functions implemented in xspips.c
|
||||
*/
|
||||
s32 XSpiPs_CfgInitialize(XSpiPs *InstancePtr, const XSpiPs_Config *ConfigPtr,
|
||||
u32 EffectiveAddr);
|
||||
|
||||
void XSpiPs_Reset(XSpiPs *InstancePtr);
|
||||
|
||||
s32 XSpiPs_Transfer(XSpiPs *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr,
|
||||
u32 ByteCount);
|
||||
|
||||
s32 XSpiPs_PolledTransfer(XSpiPs *InstancePtr, u8 *SendBufPtr,
|
||||
u8 *RecvBufPtr, u32 ByteCount);
|
||||
|
||||
void XSpiPs_SetStatusHandler(XSpiPs *InstancePtr, void *CallBackRef,
|
||||
XSpiPs_StatusHandler FunctionPtr);
|
||||
void XSpiPs_InterruptHandler(XSpiPs *InstancePtr);
|
||||
|
||||
void XSpiPs_Abort(XSpiPs *InstancePtr);
|
||||
|
||||
s32 XSpiPs_SetSlaveSelect(XSpiPs *InstancePtr, u8 SlaveSel);
|
||||
u8 XSpiPs_GetSlaveSelect(const XSpiPs *InstancePtr);
|
||||
|
||||
/*
|
||||
* Functions for selftest, in xspips_selftest.c
|
||||
*/
|
||||
s32 XSpiPs_SelfTest(XSpiPs *InstancePtr);
|
||||
|
||||
/*
|
||||
* Functions for options, in xspips_options.c
|
||||
*/
|
||||
s32 XSpiPs_SetOptions(const XSpiPs *InstancePtr, u32 Options);
|
||||
u32 XSpiPs_GetOptions(const XSpiPs *InstancePtr);
|
||||
|
||||
s32 XSpiPs_SetClkPrescaler(const XSpiPs *InstancePtr, u8 Prescaler);
|
||||
u8 XSpiPs_GetClkPrescaler(const XSpiPs *InstancePtr);
|
||||
|
||||
s32 XSpiPs_SetDelays(const XSpiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
|
||||
u8 DelayAfter, u8 DelayInit);
|
||||
void XSpiPs_GetDelays(const XSpiPs *InstancePtr, u8 *DelayNss, u8 *DelayBtwn,
|
||||
u8 *DelayAfter, u8 *DelayInit);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* end of protection macro */
|
||||
/** @} */
|
||||
-32
@@ -1,32 +0,0 @@
|
||||
|
||||
/*******************************************************************
|
||||
*
|
||||
* CAUTION: This file is automatically generated by HSI.
|
||||
* Version: 2023.2.1
|
||||
* DO NOT EDIT.
|
||||
*
|
||||
* Copyright (C) 2010-2024 Xilinx, Inc. All Rights Reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
|
||||
*
|
||||
* Description: Driver configuration
|
||||
*
|
||||
*******************************************************************/
|
||||
|
||||
#include "xparameters.h"
|
||||
#include "xspips.h"
|
||||
|
||||
/*
|
||||
* The configuration table for devices
|
||||
*/
|
||||
|
||||
XSpiPs_Config XSpiPs_ConfigTable[XPAR_XSPIPS_NUM_INSTANCES] =
|
||||
{
|
||||
{
|
||||
XPAR_PS7_SPI_0_DEVICE_ID,
|
||||
XPAR_PS7_SPI_0_BASEADDR,
|
||||
XPAR_PS7_SPI_0_SPI_CLK_FREQ_HZ
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
-121
@@ -1,121 +0,0 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2013 - 2022 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xspips_hw.c
|
||||
* @addtogroup spips Overview
|
||||
* @{
|
||||
*
|
||||
* Contains the reset and post boot rom state initialization.
|
||||
* Function prototypes in xspips_hw.h
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ------ -------- -----------------------------------------------
|
||||
* 1.06a hk 08/22/13 First release.
|
||||
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
|
||||
* 3.02 raw 11/23/15 Updated XSpiPs_ResetHw() to read all RXFIFO
|
||||
* entries. This change is to tackle CR#910231.
|
||||
* 3.1 tjs 11/23/18 Added a check for A72 and R5 processor to
|
||||
* avoid changes made for the workaround DT#842463.
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xspips_hw.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Resets the spi module
|
||||
*
|
||||
* @param BaseAddress is the base address of the device.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void XSpiPs_ResetHw(u32 BaseAddress)
|
||||
{
|
||||
u32 Check;
|
||||
#if !defined(versal)
|
||||
u32 Count;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Disable Interrupts
|
||||
*/
|
||||
XSpiPs_WriteReg(BaseAddress, XSPIPS_IDR_OFFSET,
|
||||
XSPIPS_IXR_DISABLE_ALL_MASK);
|
||||
|
||||
/*
|
||||
* Disable device
|
||||
*/
|
||||
XSpiPs_WriteReg(BaseAddress, XSPIPS_ER_OFFSET,
|
||||
0U);
|
||||
/*
|
||||
* Write default value to RX and TX threshold registers
|
||||
* RX threshold should be set to 1 here as the corresponding
|
||||
* status bit is used to clear the FIFO next
|
||||
*/
|
||||
XSpiPs_WriteReg(BaseAddress, XSPIPS_TXWR_OFFSET,
|
||||
(XSPIPS_TXWR_RESET_VALUE & XSPIPS_TXWR_MASK));
|
||||
XSpiPs_WriteReg(BaseAddress, XSPIPS_RXWR_OFFSET,
|
||||
(XSPIPS_RXWR_RESET_VALUE & XSPIPS_RXWR_MASK));
|
||||
|
||||
/*
|
||||
* Clear RXFIFO
|
||||
*/
|
||||
Check = (XSpiPs_ReadReg(BaseAddress,XSPIPS_SR_OFFSET) &
|
||||
XSPIPS_IXR_RXNEMPTY_MASK);
|
||||
while (Check != 0U) {
|
||||
(void)XSpiPs_ReadReg(BaseAddress, XSPIPS_RXD_OFFSET);
|
||||
Check = (XSpiPs_ReadReg(BaseAddress,XSPIPS_SR_OFFSET) &
|
||||
XSPIPS_IXR_RXNEMPTY_MASK);
|
||||
}
|
||||
|
||||
/*
|
||||
* Read all RXFIFO entries
|
||||
*/
|
||||
#if !defined(versal)
|
||||
for (Count = 0U; Count < XSPIPS_FIFO_DEPTH; Count++) {
|
||||
(void)XSpiPs_ReadReg(BaseAddress, XSPIPS_RXD_OFFSET);
|
||||
}
|
||||
#endif
|
||||
/*
|
||||
* Clear status register by writing 1 to the write to clear bits
|
||||
*/
|
||||
XSpiPs_WriteReg(BaseAddress, XSPIPS_SR_OFFSET,
|
||||
XSPIPS_IXR_WR_TO_CLR_MASK);
|
||||
|
||||
/*
|
||||
* Write default value to configuration register
|
||||
* De-select all slaves
|
||||
*/
|
||||
XSpiPs_WriteReg(BaseAddress, XSPIPS_CR_OFFSET,
|
||||
XSPIPS_CR_RESET_STATE |
|
||||
XSPIPS_CR_SSCTRL_MASK);
|
||||
|
||||
}
|
||||
/** @} */
|
||||
-287
@@ -1,287 +0,0 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xspips_hw.h
|
||||
* @addtogroup spips Overview
|
||||
* @{
|
||||
*
|
||||
* This header file contains the identifiers and basic driver functions (or
|
||||
* macros) that can be used to access the device. Other driver functions
|
||||
* are defined in xspips.h.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ------ -------- -----------------------------------------------
|
||||
* 1.00 drg/jz 01/25/10 First release
|
||||
* 1.02a sg 05/31/12 Updated XSPIPS_FIFO_DEPTH to 128 from 32 to match HW
|
||||
* for CR 658289
|
||||
* 1.04a sg 01/30/13 Created XSPIPS_CR_MODF_GEN_EN_MASK macro and added it
|
||||
* to XSPIPS_CR_RESET_STATE. Created
|
||||
* XSPIPS_IXR_WR_TO_CLR_MASK for interrupts which need
|
||||
* write-to-clear. Added shift and mask macros for d_nss
|
||||
* parameter. Added Rx Watermark mask.
|
||||
* 1.06a hk 08/22/13 Added prototypes of reset API and related constant
|
||||
* definitions.
|
||||
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef XSPIPS_HW_H /* prevent circular inclusions */
|
||||
#define XSPIPS_HW_H /* by using protection macros */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xil_types.h"
|
||||
#include "xil_assert.h"
|
||||
#include "xil_io.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/** @name Register Map
|
||||
*
|
||||
* Register offsets from the base address of an SPI device.
|
||||
* @{
|
||||
*/
|
||||
#define XSPIPS_CR_OFFSET 0x00U /**< Configuration */
|
||||
#define XSPIPS_SR_OFFSET 0x04U /**< Interrupt Status */
|
||||
#define XSPIPS_IER_OFFSET 0x08U /**< Interrupt Enable */
|
||||
#define XSPIPS_IDR_OFFSET 0x0CU /**< Interrupt Disable */
|
||||
#define XSPIPS_IMR_OFFSET 0x10U /**< Interrupt Enabled Mask */
|
||||
#define XSPIPS_ER_OFFSET 0x14U /**< Enable/Disable Register */
|
||||
#define XSPIPS_DR_OFFSET 0x18U /**< Delay Register */
|
||||
#define XSPIPS_TXD_OFFSET 0x1CU /**< Data Transmit Register */
|
||||
#define XSPIPS_RXD_OFFSET 0x20U /**< Data Receive Register */
|
||||
#define XSPIPS_SICR_OFFSET 0x24U /**< Slave Idle Count */
|
||||
#define XSPIPS_TXWR_OFFSET 0x28U /**< Transmit FIFO Watermark */
|
||||
#define XSPIPS_RXWR_OFFSET 0x2CU /**< Receive FIFO Watermark */
|
||||
/* @} */
|
||||
|
||||
/** @name Configuration Register
|
||||
*
|
||||
* This register contains various control bits that
|
||||
* affects the operation of an SPI device. Read/Write.
|
||||
* @{
|
||||
*/
|
||||
#define XSPIPS_CR_MODF_GEN_EN_MASK 0x00020000U /**< Modefail Generation
|
||||
Enable */
|
||||
#define XSPIPS_CR_MANSTRT_MASK 0x00010000U /**< Manual Transmission Start */
|
||||
#define XSPIPS_CR_MANSTRTEN_MASK 0x00008000U /**< Manual Transmission Start
|
||||
Enable */
|
||||
#define XSPIPS_CR_SSFORCE_MASK 0x00004000U /**< Force Slave Select */
|
||||
#define XSPIPS_CR_SSCTRL_MASK 0x00003C00U /**< Slave Select Decode */
|
||||
#define XSPIPS_CR_SSCTRL_SHIFT 10U /**< Slave Select Decode shift */
|
||||
#define XSPIPS_CR_SSCTRL_MAXIMUM 0xFU /**< Slave Select maximum value */
|
||||
#define XSPIPS_CR_SSDECEN_MASK 0x00000200U /**< Slave Select Decode Enable */
|
||||
|
||||
#define XSPIPS_CR_PRESC_MASK 0x00000038U /**< Prescaler Setting */
|
||||
#define XSPIPS_CR_PRESC_SHIFT 3U /**< Prescaler shift */
|
||||
#define XSPIPS_CR_PRESC_MAXIMUM 0x07U /**< Prescaler maximum value */
|
||||
|
||||
#define XSPIPS_CR_CPHA_MASK 0x00000004U /**< Phase Configuration */
|
||||
#define XSPIPS_CR_CPOL_MASK 0x00000002U /**< Polarity Configuration */
|
||||
|
||||
#define XSPIPS_CR_MSTREN_MASK 0x00000001U /**< Master Mode Enable */
|
||||
#define XSPIPS_CR_RESET_STATE 0x00020000U /**< Mode Fail Generation Enable */
|
||||
/* @} */
|
||||
|
||||
|
||||
/** @name SPI Interrupt Registers
|
||||
*
|
||||
* <b>SPI Status Register</b>
|
||||
*
|
||||
* This register holds the interrupt status flags for an SPI device. Some
|
||||
* of the flags are level triggered, which means that they are set as long
|
||||
* as the interrupt condition exists. Other flags are edge triggered,
|
||||
* which means they are set once the interrupt condition occurs and remain
|
||||
* set until they are cleared by software. The interrupts are cleared by
|
||||
* writing a '1' to the interrupt bit position in the Status Register.
|
||||
* Read/Write.
|
||||
*
|
||||
* <b>SPI Interrupt Enable Register</b>
|
||||
*
|
||||
* This register is used to enable chosen interrupts for an SPI device.
|
||||
* Writing a '1' to a bit in this register sets the corresponding bit in the
|
||||
* SPI Interrupt Mask register. Write only.
|
||||
*
|
||||
* <b>SPI Interrupt Disable Register </b>
|
||||
*
|
||||
* This register is used to disable chosen interrupts for an SPI device.
|
||||
* Writing a '1' to a bit in this register clears the corresponding bit in the
|
||||
* SPI Interrupt Mask register. Write only.
|
||||
*
|
||||
* <b>SPI Interrupt Mask Register</b>
|
||||
*
|
||||
* This register shows the enabled/disabled interrupts of an SPI device.
|
||||
* Read only.
|
||||
*
|
||||
* All four registers have the same bit definitions. They are only defined once
|
||||
* for each of the Interrupt Enable Register, Interrupt Disable Register,
|
||||
* Interrupt Mask Register, and Channel Interrupt Status Register
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define XSPIPS_IXR_TXUF_MASK 0x00000040U /**< Tx FIFO Underflow */
|
||||
#define XSPIPS_IXR_RXFULL_MASK 0x00000020U /**< Rx FIFO Full */
|
||||
#define XSPIPS_IXR_RXNEMPTY_MASK 0x00000010U /**< Rx FIFO Not Empty */
|
||||
#define XSPIPS_IXR_TXFULL_MASK 0x00000008U /**< Tx FIFO Full */
|
||||
#define XSPIPS_IXR_TXOW_MASK 0x00000004U /**< Tx FIFO Overwater */
|
||||
#define XSPIPS_IXR_MODF_MASK 0x00000002U /**< Mode Fault */
|
||||
#define XSPIPS_IXR_RXOVR_MASK 0x00000001U /**< Rx FIFO Overrun */
|
||||
#define XSPIPS_IXR_DFLT_MASK 0x00000027U /**< Default interrupts
|
||||
mask */
|
||||
#define XSPIPS_IXR_WR_TO_CLR_MASK 0x00000043U /**< Interrupts which
|
||||
need write to clear */
|
||||
#define XSPIPS_ISR_RESET_STATE 0x04U /**< Default to tx/rx
|
||||
* reg empty */
|
||||
#define XSPIPS_IXR_DISABLE_ALL_MASK 0x00000043U /**< Disable all
|
||||
* interrupts */
|
||||
/* @} */
|
||||
|
||||
|
||||
/** @name Enable Register
|
||||
*
|
||||
* This register is used to enable or disable an SPI device.
|
||||
* Read/Write
|
||||
* @{
|
||||
*/
|
||||
#define XSPIPS_ER_ENABLE_MASK 0x00000001U /**< SPI Enable Bit Mask */
|
||||
/* @} */
|
||||
|
||||
|
||||
/** @name Delay Register
|
||||
*
|
||||
* This register is used to program timing delays in
|
||||
* slave mode. Read/Write
|
||||
* @{
|
||||
*/
|
||||
#define XSPIPS_DR_NSS_MASK 0xFF000000U /**< Delay for slave select
|
||||
* de-assertion between
|
||||
* word transfers mask */
|
||||
#define XSPIPS_DR_NSS_SHIFT 24U /**< Delay for slave select
|
||||
* de-assertion between
|
||||
* word transfers shift */
|
||||
#define XSPIPS_DR_BTWN_MASK 0x00FF0000U /**< Delay Between Transfers mask */
|
||||
#define XSPIPS_DR_BTWN_SHIFT 16U /**< Delay Between Transfers shift */
|
||||
#define XSPIPS_DR_AFTER_MASK 0x0000FF00U /**< Delay After Transfers mask */
|
||||
#define XSPIPS_DR_AFTER_SHIFT 8U /**< Delay After Transfers shift */
|
||||
#define XSPIPS_DR_INIT_MASK 0x000000FFU /**< Delay Initially mask */
|
||||
/* @} */
|
||||
|
||||
|
||||
/** @name Slave Idle Count Registers
|
||||
*
|
||||
* This register defines the number of pclk cycles the slave waits for a the
|
||||
* SPI clock to become stable in quiescent state before it can detect the start
|
||||
* of the next transfer in CPHA = 1 mode.
|
||||
* Read/Write
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
#define XSPIPS_SICR_MASK 0x000000FFU /**< Slave Idle Count Mask */
|
||||
/* @} */
|
||||
|
||||
|
||||
|
||||
/** @name Transmit FIFO Watermark Register
|
||||
*
|
||||
* This register defines the watermark setting for the Transmit FIFO. The
|
||||
* transmit FIFO is 128 bytes deep, so the register is 7 bits. Valid values
|
||||
* are 1 to 128.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
#define XSPIPS_TXWR_MASK 0x0000007FU /**< Transmit Watermark Mask */
|
||||
#define XSPIPS_TXWR_RESET_VALUE 0x00000001U /**< Transmit Watermark
|
||||
* register reset value */
|
||||
/* @} */
|
||||
|
||||
/** @name Receive FIFO Watermark Register
|
||||
*
|
||||
* This register defines the watermark setting for the Receive FIFO. The
|
||||
* receive FIFO is 128 bytes deep, so the register is 7 bits. Valid values
|
||||
* are 1 to 128.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
#define XSPIPS_RXWR_MASK 0x0000007FU /**< Receive Watermark Mask */
|
||||
#define XSPIPS_RXWR_RESET_VALUE 0x00000001U /**< Receive Watermark
|
||||
* register reset value */
|
||||
/* @} */
|
||||
|
||||
/** @name FIFO Depth
|
||||
*
|
||||
* This macro provides the depth of transmit FIFO and receive FIFO.
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
#define XSPIPS_FIFO_DEPTH 128U /**< FIFO depth of Tx and Rx */
|
||||
/* @} */
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
#define XSpiPs_In32 Xil_In32
|
||||
#define XSpiPs_Out32 Xil_Out32
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
* Read a register.
|
||||
*
|
||||
* @param BaseAddress contains the base address of the device.
|
||||
* @param RegOffset contains the offset from the 1st register of the
|
||||
* device to the target register.
|
||||
*
|
||||
* @return The value read from the register.
|
||||
*
|
||||
* @note C-Style signature:
|
||||
* u32 XSpiPs_ReadReg(u32 BaseAddress. int RegOffset)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XSpiPs_ReadReg(BaseAddress, RegOffset) \
|
||||
XSpiPs_In32((BaseAddress) + (RegOffset))
|
||||
|
||||
/***************************************************************************/
|
||||
/**
|
||||
* Write to a register.
|
||||
*
|
||||
* @param BaseAddress contains the base address of the device.
|
||||
* @param RegOffset contains the offset from the 1st register of the
|
||||
* device to target register.
|
||||
* @param RegisterValue is the value to be written to the register.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note C-Style signature:
|
||||
* void XSpiPs_WriteReg(u32 BaseAddress, int RegOffset,
|
||||
* u32 RegisterValue)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XSpiPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
|
||||
XSpiPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
void XSpiPs_ResetHw(u32 BaseAddress);
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* end of protection macro */
|
||||
/** @} */
|
||||
-409
@@ -1,409 +0,0 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xspips_options.c
|
||||
* @addtogroup spips Overview
|
||||
* @{
|
||||
*
|
||||
* Contains functions for the configuration of the XSpiPs driver.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ------ -------- -----------------------------------------------
|
||||
* 1.00 drg/jz 01/25/10 First release
|
||||
* 1.00 sdm 10/25/11 Removed the Divide by 2 in the SPI Clock Prescaler
|
||||
* options as this is not supported in the device
|
||||
* 1.04a sg 01/30/13 Added XSPIPS_MANUAL_START_OPTION. SetDelays and
|
||||
* GetDelays API's include DelayNss parameter.
|
||||
* 1.05a hk 26/04/13 Added disable and enable in XSpiPs_SetOptions when
|
||||
* CPOL/CPHA bits are set/reset. Fix for CR#707669.
|
||||
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
|
||||
* 3.2 aru 01/20/19 Fixes violations according to MISRAC-2012
|
||||
* in safety mode and done changes such as
|
||||
* Declared the pointer param as Pointer to const
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xspips.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
/*
|
||||
* Create the table of options which are processed to get/set the device
|
||||
* options. These options are table driven to allow easy maintenance and
|
||||
* expansion of the options.
|
||||
*/
|
||||
typedef struct {
|
||||
u32 Option;
|
||||
u32 Mask;
|
||||
} OptionsMap;
|
||||
|
||||
static OptionsMap OptionsTable[] = {
|
||||
{XSPIPS_MASTER_OPTION, XSPIPS_CR_MSTREN_MASK},
|
||||
{XSPIPS_CLK_ACTIVE_LOW_OPTION, XSPIPS_CR_CPOL_MASK},
|
||||
{XSPIPS_CLK_PHASE_1_OPTION, XSPIPS_CR_CPHA_MASK},
|
||||
{XSPIPS_DECODE_SSELECT_OPTION, XSPIPS_CR_SSDECEN_MASK},
|
||||
{XSPIPS_FORCE_SSELECT_OPTION, XSPIPS_CR_SSFORCE_MASK},
|
||||
{XSPIPS_MANUAL_START_OPTION, XSPIPS_CR_MANSTRTEN_MASK}
|
||||
};
|
||||
|
||||
#define XSPIPS_NUM_OPTIONS (sizeof(OptionsTable) / sizeof(OptionsMap))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function sets the options for the SPI device driver. The options control
|
||||
* how the device behaves relative to the SPI bus. The device must be idle
|
||||
* rather than busy transferring data before setting these device options.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XSpiPs instance.
|
||||
* @param Options contains the specified options to be set. This is a bit
|
||||
* mask where a 1 means to turn the option on, and a 0 means to
|
||||
* turn the option off. One or more bit values may be contained in
|
||||
* the mask. See the bit definitions named XSPIPS_*_OPTIONS in the
|
||||
* file xspips.h.
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if options are successfully set.
|
||||
* - XST_DEVICE_BUSY if the device is currently transferring data.
|
||||
* The transfer must complete or be aborted before setting options.
|
||||
*
|
||||
* @note
|
||||
* This function is not thread-safe.
|
||||
*
|
||||
******************************************************************************/
|
||||
s32 XSpiPs_SetOptions(const XSpiPs *InstancePtr, u32 Options)
|
||||
{
|
||||
u32 ConfigReg;
|
||||
u32 Index;
|
||||
u32 CurrentConfigReg;
|
||||
s32 Status;
|
||||
|
||||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
|
||||
/*
|
||||
* Do not allow the slave select to change while a transfer is in
|
||||
* progress. Not thread-safe.
|
||||
*/
|
||||
if (InstancePtr->IsBusy == TRUE) {
|
||||
Status = (s32)XST_DEVICE_BUSY;
|
||||
} else {
|
||||
|
||||
ConfigReg = XSpiPs_ReadReg(InstancePtr->Config.BaseAddress,
|
||||
XSPIPS_CR_OFFSET);
|
||||
|
||||
CurrentConfigReg = ConfigReg;
|
||||
|
||||
/*
|
||||
* Loop through the options table, turning the option on or off
|
||||
* depending on whether the bit is set in the incoming options flag.
|
||||
*/
|
||||
for (Index = 0U; Index < XSPIPS_NUM_OPTIONS; Index++) {
|
||||
if ((Options & OptionsTable[Index].Option) != (u32)0U) {
|
||||
/* Turn it on */
|
||||
ConfigReg |= OptionsTable[Index].Mask;
|
||||
}
|
||||
else {
|
||||
/* Turn it off */
|
||||
ConfigReg &= ~(OptionsTable[Index].Mask);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* If CPOL-CPHA bits are toggled from previous state,
|
||||
* disable before writing the configuration register and then enable.
|
||||
*/
|
||||
if( ((CurrentConfigReg & XSPIPS_CR_CPOL_MASK) !=
|
||||
(ConfigReg & XSPIPS_CR_CPOL_MASK)) ||
|
||||
((CurrentConfigReg & XSPIPS_CR_CPHA_MASK) !=
|
||||
(ConfigReg & XSPIPS_CR_CPHA_MASK)) ) {
|
||||
XSpiPs_Disable(InstancePtr);
|
||||
}
|
||||
|
||||
/*
|
||||
* Now write the Config register. Leave it to the upper layers
|
||||
* to restart the device.
|
||||
*/
|
||||
XSpiPs_WriteReg(InstancePtr->Config.BaseAddress,
|
||||
XSPIPS_CR_OFFSET, ConfigReg);
|
||||
|
||||
/*
|
||||
* Enable
|
||||
*/
|
||||
if( ((CurrentConfigReg & XSPIPS_CR_CPOL_MASK) !=
|
||||
(ConfigReg & XSPIPS_CR_CPOL_MASK)) ||
|
||||
((CurrentConfigReg & XSPIPS_CR_CPHA_MASK) !=
|
||||
(ConfigReg & XSPIPS_CR_CPHA_MASK)) ) {
|
||||
XSpiPs_Enable(InstancePtr);
|
||||
}
|
||||
|
||||
Status = (s32)XST_SUCCESS;
|
||||
}
|
||||
return Status;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function gets the options for the SPI device. The options control how
|
||||
* the device behaves relative to the SPI bus.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XSpiPs instance.
|
||||
*
|
||||
* @return
|
||||
*
|
||||
* Options contains the specified options currently set. This is a bit value
|
||||
* where a 1 means the option is on, and a 0 means the option is off.
|
||||
* See the bit definitions named XSPIPS_*_OPTIONS in file xspips.h.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
u32 XSpiPs_GetOptions(const XSpiPs *InstancePtr)
|
||||
{
|
||||
u32 OptionsFlag = 0U;
|
||||
u32 ConfigReg;
|
||||
u32 Index;
|
||||
|
||||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
|
||||
/*
|
||||
* Get the current options
|
||||
*/
|
||||
ConfigReg =
|
||||
XSpiPs_ReadReg(InstancePtr->Config.BaseAddress,
|
||||
XSPIPS_CR_OFFSET);
|
||||
|
||||
/*
|
||||
* Loop through the options table to grab options
|
||||
*/
|
||||
for (Index = 0U; Index < XSPIPS_NUM_OPTIONS; Index++) {
|
||||
if ((ConfigReg & OptionsTable[Index].Mask) != FALSE) {
|
||||
OptionsFlag |= OptionsTable[Index].Option;
|
||||
}
|
||||
}
|
||||
|
||||
return OptionsFlag;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function sets the clock prescaler for an SPI device. The device
|
||||
* must be idle rather than busy transferring data before setting these device
|
||||
* options.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XSpiPs instance.
|
||||
* @param Prescaler is the value that determine how much the clock should
|
||||
* be divided by. Use the XSPIPS_CLK_PRESCALE_* constants defined
|
||||
* in xspips.h for this setting.
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if options are successfully set.
|
||||
* - XST_DEVICE_BUSY if the device is currently transferring data.
|
||||
* The transfer must complete or be aborted before setting options.
|
||||
*
|
||||
* @note
|
||||
* This function is not thread-safe.
|
||||
*
|
||||
******************************************************************************/
|
||||
s32 XSpiPs_SetClkPrescaler(const XSpiPs *InstancePtr, u8 Prescaler)
|
||||
{
|
||||
u32 ConfigReg;
|
||||
s32 Status;
|
||||
|
||||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
Xil_AssertNonvoid((Prescaler > 0U) && (Prescaler <= XSPIPS_CR_PRESC_MAXIMUM));
|
||||
|
||||
/*
|
||||
* Do not allow the prescaler to be changed while a transfer is in
|
||||
* progress. Not thread-safe.
|
||||
*/
|
||||
if (InstancePtr->IsBusy == TRUE) {
|
||||
Status = (s32)XST_DEVICE_BUSY;
|
||||
} else {
|
||||
|
||||
/*
|
||||
* Read the Config register, mask out the interesting bits, and set
|
||||
* them with the shifted value passed into the function. Write the
|
||||
* results back to the Config register.
|
||||
*/
|
||||
ConfigReg = XSpiPs_ReadReg(InstancePtr->Config.BaseAddress,
|
||||
XSPIPS_CR_OFFSET);
|
||||
|
||||
ConfigReg &= (u32)(~XSPIPS_CR_PRESC_MASK);
|
||||
ConfigReg |= (u32) ((u32)Prescaler & (u32)XSPIPS_CR_PRESC_MAXIMUM) <<
|
||||
XSPIPS_CR_PRESC_SHIFT;
|
||||
|
||||
XSpiPs_WriteReg(InstancePtr->Config.BaseAddress,
|
||||
XSPIPS_CR_OFFSET,
|
||||
ConfigReg);
|
||||
|
||||
Status = (s32)XST_SUCCESS;
|
||||
}
|
||||
return Status;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function gets the clock prescaler of an SPI device.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XSpiPs instance.
|
||||
*
|
||||
* @return The prescaler value.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
u8 XSpiPs_GetClkPrescaler(const XSpiPs *InstancePtr)
|
||||
{
|
||||
u32 ConfigReg;
|
||||
|
||||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
|
||||
ConfigReg = XSpiPs_ReadReg(InstancePtr->Config.BaseAddress,
|
||||
XSPIPS_CR_OFFSET);
|
||||
|
||||
ConfigReg &= XSPIPS_CR_PRESC_MASK;
|
||||
|
||||
return (u8)(ConfigReg >> XSPIPS_CR_PRESC_SHIFT);
|
||||
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function sets the delay register for the SPI device driver.
|
||||
* The delay register controls the Delay Between Transfers, Delay After
|
||||
* Transfers, and the Delay Initially. The default value is 0x0. The range of
|
||||
* each delay value is 0-255.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XSpiPs instance.
|
||||
* @param DelayNss is the delay for which the chip select outputs will
|
||||
* be de-asserted between words when CPHA=0.
|
||||
* @param DelayBtwn is the delay between one Slave Select being
|
||||
* de-activated and the activation of another slave. The delay is
|
||||
* the number of master clock periods given by DelayBtwn + 2.
|
||||
* @param DelayAfter define the delay between the last bit of the current
|
||||
* byte transfer and the first bit of the next byte transfer.
|
||||
* The delay in number of master clock periods is given as:
|
||||
* CPHA=0:DelayInit+DelayAfter+3
|
||||
* CPHA=1:DelayAfter+1
|
||||
* @param DelayInit is the delay between asserting the slave select signal
|
||||
* and the first bit transfer. The delay int number of master clock
|
||||
* periods is DelayInit+1.
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if delays are successfully set.
|
||||
* - XST_DEVICE_BUSY if the device is currently transferring data.
|
||||
* The transfer must complete or be aborted before setting options.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
s32 XSpiPs_SetDelays(const XSpiPs *InstancePtr, u8 DelayNss, u8 DelayBtwn,
|
||||
u8 DelayAfter, u8 DelayInit)
|
||||
{
|
||||
u32 DelayRegister;
|
||||
s32 Status;
|
||||
|
||||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
|
||||
/*
|
||||
* Do not allow the delays to change while a transfer is in
|
||||
* progress. Not thread-safe.
|
||||
*/
|
||||
if (InstancePtr->IsBusy == TRUE) {
|
||||
Status = (s32)XST_DEVICE_BUSY;
|
||||
} else {
|
||||
|
||||
/* Shift, Mask and OR the values to build the register settings */
|
||||
DelayRegister = (u32) DelayNss << XSPIPS_DR_NSS_SHIFT;
|
||||
DelayRegister |= (u32) DelayBtwn << XSPIPS_DR_BTWN_SHIFT;
|
||||
DelayRegister |= (u32) DelayAfter << XSPIPS_DR_AFTER_SHIFT;
|
||||
DelayRegister |= (u32) DelayInit;
|
||||
|
||||
XSpiPs_WriteReg(InstancePtr->Config.BaseAddress,
|
||||
XSPIPS_DR_OFFSET, DelayRegister);
|
||||
|
||||
Status = (s32)XST_SUCCESS;
|
||||
}
|
||||
return Status;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function gets the delay settings for an SPI device.
|
||||
* The delay register controls the Delay Between Transfers, Delay After
|
||||
* Transfers, and the Delay Initially. The default value is 0x0.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XSpiPs instance.
|
||||
* @param DelayNss is a pointer to the delay for which the chip select
|
||||
* outputs will be de-asserted between words when CPHA=0.
|
||||
* @param DelayBtwn is a pointer to the Delay Between transfers value.
|
||||
* This is a return parameter.
|
||||
* @param DelayAfter is a pointer to the Delay After transfer value.
|
||||
* This is a return parameter.
|
||||
* @param DelayInit is a pointer to the Delay Initially value. This is
|
||||
* a return parameter.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
void XSpiPs_GetDelays(const XSpiPs *InstancePtr,u8 *DelayNss, u8 *DelayBtwn,
|
||||
u8 *DelayAfter, u8 *DelayInit)
|
||||
{
|
||||
u32 DelayRegister;
|
||||
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
|
||||
DelayRegister = XSpiPs_ReadReg(InstancePtr->Config.BaseAddress,
|
||||
XSPIPS_DR_OFFSET);
|
||||
|
||||
*DelayInit = (u8)(DelayRegister & XSPIPS_DR_INIT_MASK);
|
||||
|
||||
*DelayAfter = (u8)((DelayRegister & XSPIPS_DR_AFTER_MASK) >>
|
||||
XSPIPS_DR_AFTER_SHIFT);
|
||||
|
||||
*DelayBtwn = (u8)((DelayRegister & XSPIPS_DR_BTWN_MASK) >>
|
||||
XSPIPS_DR_BTWN_SHIFT);
|
||||
|
||||
*DelayNss = (u8)((DelayRegister & XSPIPS_DR_NSS_MASK) >>
|
||||
XSPIPS_DR_NSS_SHIFT);
|
||||
|
||||
}
|
||||
/** @} */
|
||||
-141
@@ -1,141 +0,0 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xspips_selftest.c
|
||||
* @addtogroup spips Overview
|
||||
* @{
|
||||
*
|
||||
* This component contains the implementation of selftest functions for an SPI
|
||||
* device.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ------ -------- ----------------------------------------------
|
||||
* 1.00 drg/jz 01/25/10 First release
|
||||
* 1.04a sg 01/30/13 SetDelays test includes DelayTestNss parameter.
|
||||
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
|
||||
* 3.2 aru 01/20/19 Fixes violations according to MISRAC-2012
|
||||
* in safety mode and done changes such as
|
||||
* Added goto statements.
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xspips.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Runs a self-test on the driver/device. The self-test is destructive in that
|
||||
* a reset of the device is performed in order to check the reset values of
|
||||
* the registers and to get the device into a known state.
|
||||
*
|
||||
* Upon successful return from the self-test, the device is reset.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the XSpiPs instance.
|
||||
*
|
||||
* @return
|
||||
* - XST_SUCCESS if successful
|
||||
* - XST_REGISTER_ERROR indicates a register did not read or write
|
||||
* correctly.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
s32 XSpiPs_SelfTest(XSpiPs *InstancePtr)
|
||||
{
|
||||
s32 Status;
|
||||
u32 Register;
|
||||
u8 DelayTestNss;
|
||||
u8 DelayTestBtwn;
|
||||
u8 DelayTestAfter;
|
||||
u8 DelayTestInit;
|
||||
|
||||
Xil_AssertNonvoid(InstancePtr != NULL);
|
||||
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||
|
||||
/*
|
||||
* Reset the SPI device to leave it in a known good state
|
||||
*/
|
||||
XSpiPs_Reset(InstancePtr);
|
||||
|
||||
/*
|
||||
* All the SPI registers should be in their default state right now.
|
||||
*/
|
||||
Register = XSpiPs_ReadReg(InstancePtr->Config.BaseAddress,
|
||||
XSPIPS_CR_OFFSET);
|
||||
if (Register != XSPIPS_CR_RESET_STATE) {
|
||||
Status = (s32)XST_REGISTER_ERROR;
|
||||
goto END;
|
||||
}
|
||||
|
||||
Register = XSpiPs_ReadReg(InstancePtr->Config.BaseAddress,
|
||||
XSPIPS_SR_OFFSET);
|
||||
if (Register != XSPIPS_ISR_RESET_STATE) {
|
||||
Status = (s32)XST_REGISTER_ERROR;
|
||||
goto END;;
|
||||
}
|
||||
|
||||
DelayTestNss = 0x5AU;
|
||||
DelayTestBtwn = 0xA5U;
|
||||
DelayTestAfter = 0xAAU;
|
||||
DelayTestInit = 0x55U;
|
||||
|
||||
/*
|
||||
* Write and read the delay register, just to be sure there is some
|
||||
* hardware out there.
|
||||
*/
|
||||
Status = XSpiPs_SetDelays(InstancePtr, DelayTestNss, DelayTestBtwn,
|
||||
DelayTestAfter, DelayTestInit);
|
||||
if (Status != (s32)XST_SUCCESS) {
|
||||
goto END;
|
||||
}
|
||||
|
||||
XSpiPs_GetDelays(InstancePtr, &DelayTestNss, &DelayTestBtwn,
|
||||
&DelayTestAfter, &DelayTestInit);
|
||||
if ((0x5AU != DelayTestNss) || (0xA5U != DelayTestBtwn) ||
|
||||
(0xAAU != DelayTestAfter) || (0x55U != DelayTestInit)) {
|
||||
Status = (s32)XST_REGISTER_ERROR;
|
||||
goto END;
|
||||
}
|
||||
|
||||
Status = XSpiPs_SetDelays(InstancePtr, 0U, 0U, 0U, 0U);
|
||||
if (Status != (s32)XST_SUCCESS) {
|
||||
goto END;
|
||||
}
|
||||
|
||||
/*
|
||||
* Reset the SPI device to leave it in a known good state
|
||||
*/
|
||||
XSpiPs_Reset(InstancePtr);
|
||||
|
||||
Status = (s32)XST_SUCCESS;
|
||||
|
||||
END:
|
||||
return Status;
|
||||
}
|
||||
/** @} */
|
||||
-98
@@ -1,98 +0,0 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2010 - 2022 Xilinx, Inc. All rights reserved.
|
||||
* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
******************************************************************************/
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xspips_sinit.c
|
||||
* @addtogroup spips Overview
|
||||
* @{
|
||||
*
|
||||
* The implementation of the XSpiPs driver's static initialization
|
||||
* functionality.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ------ -------- -----------------------------------------------
|
||||
* 1.00 drg/jz 01/25/10 First release
|
||||
* 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
|
||||
* 3.9 sb 07/05/23 Added support for system device-tree flow.
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xstatus.h"
|
||||
#include "xspips.h"
|
||||
#include "xparameters.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
#ifndef SDT
|
||||
extern XSpiPs_Config XSpiPs_ConfigTable[XPAR_XSPIPS_NUM_INSTANCES];
|
||||
#else
|
||||
extern XSpiPs_Config XSpiPs_ConfigTable[];
|
||||
#endif
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Looks up the device configuration based on the unique device ID. A table
|
||||
* contains the configuration info for each device in the system.
|
||||
*
|
||||
* @param DeviceId contains the ID of the device to look up the
|
||||
* configuration for.
|
||||
*
|
||||
* @return
|
||||
*
|
||||
* A pointer to the configuration found or NULL if the specified device ID was
|
||||
* not found. See xspips.h for the definition of XSpiPs_Config.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef SDT
|
||||
XSpiPs_Config *XSpiPs_LookupConfig(u16 DeviceId)
|
||||
{
|
||||
XSpiPs_Config *CfgPtr = NULL;
|
||||
u32 Index;
|
||||
|
||||
for (Index = 0U; Index < (u32)XPAR_XSPIPS_NUM_INSTANCES; Index++) {
|
||||
if (XSpiPs_ConfigTable[Index].DeviceId == DeviceId) {
|
||||
CfgPtr = &XSpiPs_ConfigTable[Index];
|
||||
break;
|
||||
}
|
||||
}
|
||||
return (XSpiPs_Config *)CfgPtr;
|
||||
}
|
||||
#else
|
||||
XSpiPs_Config *XSpiPs_LookupConfig(u32 BaseAddress)
|
||||
{
|
||||
XSpiPs_Config *CfgPtr = NULL;
|
||||
u32 Index;
|
||||
|
||||
for (Index = (u32)0x0; XSpiPs_ConfigTable[Index].Name != NULL; Index++) {
|
||||
if ((XSpiPs_ConfigTable[Index].BaseAddress == BaseAddress) ||
|
||||
!BaseAddress) {
|
||||
CfgPtr = &XSpiPs_ConfigTable[Index];
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return (XSpiPs_Config *)CfgPtr;
|
||||
}
|
||||
#endif
|
||||
/** @} */
|
||||
+6
-6
@@ -18,6 +18,12 @@ BEGIN PROCESSOR
|
||||
END
|
||||
|
||||
|
||||
BEGIN DRIVER
|
||||
PARAMETER DRIVER_NAME = generic
|
||||
PARAMETER DRIVER_VER = 3.1
|
||||
PARAMETER HW_INSTANCE = axi_spi_engine_axi_spi_engine
|
||||
END
|
||||
|
||||
BEGIN DRIVER
|
||||
PARAMETER DRIVER_NAME = generic
|
||||
PARAMETER DRIVER_VER = 3.1
|
||||
@@ -186,12 +192,6 @@ BEGIN DRIVER
|
||||
PARAMETER HW_INSTANCE = ps7_slcr_0
|
||||
END
|
||||
|
||||
BEGIN DRIVER
|
||||
PARAMETER DRIVER_NAME = spips
|
||||
PARAMETER DRIVER_VER = 3.9
|
||||
PARAMETER HW_INSTANCE = ps7_spi_0
|
||||
END
|
||||
|
||||
BEGIN DRIVER
|
||||
PARAMETER DRIVER_NAME = xadcps
|
||||
PARAMETER DRIVER_VER = 2.7
|
||||
|
||||
Binary file not shown.
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user