add ps src of prj dl814_k7_cal_coarse

happy new year! microblaze memory is enlarged to 256k

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.runs/impl_1/system_top.bit

@@ -1,3 +1,3 @@
 version https://git-lfs.github.com/spec/v1
-oid sha256:63d4884933926a9c7a02349a9d1d6fd6445d07a2d4f5d5feec675abd0071b814
+oid sha256:c9cea2b093495440187776aa3b2f6ed204eb52d690e7500081f94955d5722d63
 size 9326271

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xci

@@ -2,7 +2,7 @@
   "schema": "xilinx.com:schema:json_instance:1.0",
   "ip_inst": {
     "xci_name": "system_bd_axi_spi_engine_0_0",
-    "cell_name": "axi_spi_engine",
+    "cell_name": "axi_spi_engine/axi_spi_engine",
     "component_reference": "analog.com:user:axi_spi_engine:1.0",
     "ip_revision": "1",
     "gen_directory": "../../../../../../dl814_k7_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0",
@@ -115,25 +115,25 @@
           "memory_map_ref": "s_axi",
           "parameters": {
             "DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
             "FREQ_HZ": [ { "value": "25000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "ADDR_WIDTH": [ { "value": "16", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "HAS_RRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0.xci

@@ -9,7 +9,7 @@
     "parameters": {
       "component_parameters": {
         "C_BASEADDR": [ { "value": "0x0000000000000000", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
-        "C_HIGHADDR": [ { "value": "0x0000000000003FFF", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
+        "C_HIGHADDR": [ { "value": "0x000000000003FFFF", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "C_MASK": [ { "value": "0x0000000000000000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
         "C_MASK1": [ { "value": "0x0000000000800000", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
         "C_MASK2": [ { "value": "0x0000000000800000", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
@@ -41,7 +41,7 @@
       },
       "model_parameters": {
         "C_FAMILY": [ { "value": "kintex7", "resolve_type": "generated", "usage": "all" } ],
-        "C_HIGHADDR": [ { "value": "0x0000000000003FFF", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "C_HIGHADDR": [ { "value": "0x000000000003FFFF", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
         "C_BASEADDR": [ { "value": "0x0000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
         "C_NUM_LMB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_MASK": [ { "value": "0x0000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
@@ -148,7 +148,7 @@
           "abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
           "mode": "master",
           "parameters": {
-            "MEM_SIZE": [ { "value": "16384", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "usage": "all" } ],
+            "MEM_SIZE": [ { "value": "262144", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "usage": "all" } ],
             "MASTER_TYPE": [ { "value": "BRAM_CTRL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
             "MEM_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "MEM_ECC": [ { "value": "NONE", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0.xci

@@ -253,7 +253,7 @@
           "abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
           "mode": "slave",
           "parameters": {
-            "MEM_SIZE": [ { "value": "16384", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MEM_SIZE": [ { "value": "262144", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "MEM_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
             "MEM_ECC": [ { "value": "NONE", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
             "MASTER_TYPE": [ { "value": "BRAM_CTRL", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_0/system_bd_spi_engine_execution_0_0.xci

@@ -2,7 +2,7 @@
   "schema": "xilinx.com:schema:json_instance:1.0",
   "ip_inst": {
     "xci_name": "system_bd_spi_engine_execution_0_0",
-    "cell_name": "spi_engine_execution",
+    "cell_name": "axi_spi_engine/spi_engine_execution",
     "component_reference": "analog.com:user:spi_engine_execution:1.0",
     "ip_revision": "1",
     "gen_directory": "../../../../../../dl814_k7_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_0",

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ip/system_bd_xbar_0/system_bd_xbar_0.xci

@@ -1315,7 +1315,7 @@
           "parameters": {
             "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
             "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
-            "TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+            "TYPE": [ { "value": "INTERCONNECT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
           },
           "port_maps": {
             "RST": [ { "physical_name": "aresetn" } ]

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/system_bd.bd

@@ -1046,7 +1046,7 @@
               "SEG_ilmb_bram_if_cntlr_Mem": {
                 "address_block": "/microblaze_ps_local_memory/ilmb_bram_if_cntlr/SLMB/Mem",
                 "offset": "0x00000000",
-                "range": "16K",
+                "range": "256K",
                 "offset_high_param": "C_HIGHADDR"
               }
             }

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/system_bd.bda

@@ -189,24 +189,6 @@
                 "TU": "active"
             },
             "V3": {
-                "VT": "AC",
-                "BA": "0x00000000",
-                "HA": "0x00003FFF",
-                "BP": "C_BASEADDR",
-                "HP": "C_HIGHADDR",
-                "MA": "Instruction",
-                "MX": "/microblaze_ps",
-                "MI": "ILMB",
-                "MS": "SEG_ilmb_bram_if_cntlr_Mem",
-                "MV": "xilinx.com:ip:microblaze:11.0",
-                "SX": "/microblaze_ps_local_memory/ilmb_bram_if_cntlr",
-                "SI": "SLMB",
-                "SS": "Mem",
-                "SV": "xilinx.com:ip:lmb_bram_if_cntlr:4.0",
-                "TM": "instruction",
-                "TU": "memory"
-            },
-            "V4": {
                 "VT": "AC",
                 "BA": "0x00000000",
                 "HA": "0x0003FFFF",
@@ -224,6 +206,24 @@
                 "TM": "data",
                 "TU": "memory"
             },
+            "V4": {
+                "VT": "AC",
+                "BA": "0x00000000",
+                "HA": "0x0003FFFF",
+                "BP": "C_BASEADDR",
+                "HP": "C_HIGHADDR",
+                "MA": "Instruction",
+                "MX": "/microblaze_ps",
+                "MI": "ILMB",
+                "MS": "SEG_ilmb_bram_if_cntlr_Mem",
+                "MV": "xilinx.com:ip:microblaze:11.0",
+                "SX": "/microblaze_ps_local_memory/ilmb_bram_if_cntlr",
+                "SI": "SLMB",
+                "SS": "Mem",
+                "SV": "xilinx.com:ip:lmb_bram_if_cntlr:4.0",
+                "TM": "instruction",
+                "TU": "memory"
+            },
             "V5": {
                 "VT": "AC",
                 "BA": "0x40000000",

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ui/bd_c6d0cb12.ui

@@ -18,23 +18,23 @@ preplace inst rst_clk_wiz_25M -pg 1 -lvl 2 -x 790 -y 760 -defaultsOSRD
 preplace inst axi_spi_engine -pg 1 -lvl 2 -x 790 -y 320 -defaultsOSRD
 preplace inst microblaze_ps_axi_periph -pg 1 -lvl 1 -x 310 -y 300 -defaultsOSRD
 preplace inst axi_gpio -pg 1 -lvl 1 -x 310 -y 90 -defaultsOSRD
-preplace netloc microblaze_ps_Clk 1 0 2 40 870 580
-preplace netloc clk_wiz_1_locked 1 1 1 590 660n
-preplace netloc rst_clk_wiz_1_100M_mb_reset 1 0 3 20 890 N 890 980
-preplace netloc rst_clk_wiz_1_100M_bus_struct_reset 1 1 2 610 660 970J
-preplace netloc mdm_1_debug_sys_rst 1 1 1 N 780
-preplace netloc clk_in1_0_1 1 0 1 N 650
-preplace netloc axi_spi_engine_active_0 1 2 1 N 320
-preplace netloc rst_clk_wiz_25M_peripheral_aresetn 1 0 3 30 880 600 860 970
 preplace netloc axi_gpio_gpio_io_o 1 1 2 NJ 80 NJ
+preplace netloc axi_spi_engine_active_0 1 2 1 N 320
+preplace netloc clk_in1_0_1 1 0 1 N 650
+preplace netloc clk_wiz_1_locked 1 1 1 590 660n
 preplace netloc gpio2_io_i_0_1 1 1 2 N 120 N
-preplace netloc microblaze_ps_dlmb_1 1 1 1 N 490
+preplace netloc mdm_1_debug_sys_rst 1 1 1 N 780
-preplace netloc microblaze_ps_ilmb_1 1 1 1 N 510
+preplace netloc microblaze_ps_Clk 1 0 2 40 870 580
-preplace netloc microblaze_ps_debug 1 0 2 50 860 560J
+preplace netloc rst_clk_wiz_1_100M_bus_struct_reset 1 1 2 610 660 970J
+preplace netloc rst_clk_wiz_1_100M_mb_reset 1 0 3 20 890 N 890 980
+preplace netloc rst_clk_wiz_25M_peripheral_aresetn 1 0 3 30 880 600 860 970
 preplace netloc axi_spi_engine_spi_0 1 2 1 N 300
 preplace netloc microblaze_ps_M_AXI_DP 1 0 2 70 840 550J
 preplace netloc microblaze_ps_axi_periph_M00_AXI 1 1 1 N 290
 preplace netloc microblaze_ps_axi_periph_M01_AXI 1 0 2 60 850 570
+preplace netloc microblaze_ps_debug 1 0 2 50 860 560J
+preplace netloc microblaze_ps_dlmb_1 1 1 1 N 490
+preplace netloc microblaze_ps_ilmb_1 1 1 1 N 510
 levelinfo -pg 1 0 310 790 1010
 pagesize -pg 1 -db -bbox -sgen -130 0 1150 900
 "

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/utils_1/imports/synth_1/system_top.dcp

@@ -1,3 +1,3 @@
 version https://git-lfs.github.com/spec/v1
-oid sha256:f63248cdfe87ae1bcc80fefc7124fc82cadaa18aa95dc95716f062570e337a99
+oid sha256:a883b54d40b098c782833e5548b4abb193d32d987c42af86622454101023cbfc
-size 2345346
+size 2345994

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.xpr

@@ -562,6 +562,7 @@
       </Config>
     </FileSet>
     <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+      <Filter Type="Srcs"/>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
         <Option Name="TopModule" Val="system_top"/>
@@ -1010,9 +1011,7 @@
   <Runs Version="1" Minor="21">
     <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7k410tffg900-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/system_top.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -1022,9 +1021,7 @@
     </Run>
     <Run Id="fifo_AntCtrl_synth_1" Type="Ft3:Synth" SrcSet="fifo_AntCtrl" Part="xc7k410tffg900-2" ConstrsSet="fifo_AntCtrl" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/fifo_AntCtrl_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/fifo_AntCtrl_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/fifo_AntCtrl_synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -1034,9 +1031,7 @@
     </Run>
     <Run Id="rotate_16b_synth_1" Type="Ft3:Synth" SrcSet="rotate_16b" Part="xc7k410tffg900-2" ConstrsSet="rotate_16b" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/rotate_16b_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/rotate_16b_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/rotate_16b_synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -1046,9 +1041,7 @@
     </Run>
     <Run Id="ram_hop_data_synth_1" Type="Ft3:Synth" SrcSet="ram_hop_data" Part="xc7k410tffg900-2" ConstrsSet="ram_hop_data" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ram_hop_data_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ram_hop_data_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ram_hop_data_synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -1058,9 +1051,7 @@
     </Run>
     <Run Id="cmpy_12x12_synth_1" Type="Ft3:Synth" SrcSet="cmpy_12x12" Part="xc7k410tffg900-2" ConstrsSet="cmpy_12x12" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/cmpy_12x12_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/cmpy_12x12_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/cmpy_12x12_synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -1070,9 +1061,7 @@
     </Run>
     <Run Id="fifo_accor_cdc_synth_1" Type="Ft3:Synth" SrcSet="fifo_accor_cdc" Part="xc7k410tffg900-2" ConstrsSet="fifo_accor_cdc" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/fifo_accor_cdc_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/fifo_accor_cdc_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/fifo_accor_cdc_synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -1082,9 +1071,7 @@
     </Run>
     <Run Id="cmpy_16x12_synth_1" Type="Ft3:Synth" SrcSet="cmpy_16x12" Part="xc7k410tffg900-2" ConstrsSet="cmpy_16x12" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/cmpy_16x12_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/cmpy_16x12_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/cmpy_16x12_synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -1094,9 +1081,7 @@
     </Run>
     <Run Id="fifo_weight_cdc_synth_1" Type="Ft3:Synth" SrcSet="fifo_weight_cdc" Part="xc7k410tffg900-2" ConstrsSet="fifo_weight_cdc" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/fifo_weight_cdc_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/fifo_weight_cdc_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/fifo_weight_cdc_synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -1106,9 +1091,7 @@
     </Run>
     <Run Id="rom_hop_data_synth_1" Type="Ft3:Synth" SrcSet="rom_hop_data" Part="xc7k410tffg900-2" ConstrsSet="rom_hop_data" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/rom_hop_data_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/rom_hop_data_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/rom_hop_data_synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -1118,9 +1101,7 @@
     </Run>
     <Run Id="vio_rfcontrl_synth_1" Type="Ft3:Synth" SrcSet="vio_rfcontrl" Part="xc7k410tffg900-2" ConstrsSet="vio_rfcontrl" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/vio_rfcontrl_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_rfcontrl_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_rfcontrl_synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -1130,9 +1111,7 @@
     </Run>
     <Run Id="vio_ant_test_synth_1" Type="Ft3:Synth" SrcSet="vio_ant_test" Part="xc7k410tffg900-2" ConstrsSet="vio_ant_test" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/vio_ant_test_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_ant_test_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_ant_test_synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -1142,9 +1121,7 @@
     </Run>
     <Run Id="vio_rf_rd_synth_1" Type="Ft3:Synth" SrcSet="vio_rf_rd" Part="xc7k410tffg900-2" ConstrsSet="vio_rf_rd" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/vio_rf_rd_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_rf_rd_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_rf_rd_synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -1154,9 +1131,7 @@
     </Run>
     <Run Id="vio_manual_ctrl_synth_1" Type="Ft3:Synth" SrcSet="vio_manual_ctrl" Part="xc7k410tffg900-2" ConstrsSet="vio_manual_ctrl" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/vio_manual_ctrl_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_manual_ctrl_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_manual_ctrl_synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -1166,9 +1141,7 @@
     </Run>
     <Run Id="vio_phase_comp_synth_1" Type="Ft3:Synth" SrcSet="vio_phase_comp" Part="xc7k410tffg900-2" ConstrsSet="vio_phase_comp" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/vio_phase_comp_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_phase_comp_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_phase_comp_synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -1178,9 +1151,7 @@
     </Run>
     <Run Id="atan2_16b_synth_1" Type="Ft3:Synth" SrcSet="atan2_16b" Part="xc7k410tffg900-2" ConstrsSet="atan2_16b" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/atan2_16b_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/atan2_16b_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/atan2_16b_synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -1190,9 +1161,7 @@
     </Run>
     <Run Id="ila_rfcontrl_synth_1" Type="Ft3:Synth" SrcSet="ila_rfcontrl" Part="xc7k410tffg900-2" ConstrsSet="ila_rfcontrl" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ila_rfcontrl_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_rfcontrl_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_rfcontrl_synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -1202,9 +1171,7 @@
     </Run>
     <Run Id="ila_AntCtrl_synth_1" Type="Ft3:Synth" SrcSet="ila_AntCtrl" Part="xc7k410tffg900-2" ConstrsSet="ila_AntCtrl" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ila_AntCtrl_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_AntCtrl_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_AntCtrl_synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -1214,9 +1181,7 @@
     </Run>
     <Run Id="ila_2x12x1024_synth_1" Type="Ft3:Synth" SrcSet="ila_2x12x1024" Part="xc7k410tffg900-2" ConstrsSet="ila_2x12x1024" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ila_2x12x1024_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_2x12x1024_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_2x12x1024_synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -1226,9 +1191,7 @@
     </Run>
     <Run Id="ila_8x12_2x30_131072_synth_1" Type="Ft3:Synth" SrcSet="ila_8x12_2x30_131072" Part="xc7k410tffg900-2" ConstrsSet="ila_8x12_2x30_131072" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ila_8x12_2x30_131072_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_8x12_2x30_131072_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_8x12_2x30_131072_synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -1238,9 +1201,7 @@
     </Run>
     <Run Id="ila_cal_synth_1" Type="Ft3:Synth" SrcSet="ila_cal" Part="xc7k410tffg900-2" ConstrsSet="ila_cal" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ila_cal_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_cal_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_cal_synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -1250,9 +1211,7 @@
     </Run>
     <Run Id="ila_rx_pre_sys_synth_1" Type="Ft3:Synth" SrcSet="ila_rx_pre_sys" Part="xc7k410tffg900-2" ConstrsSet="ila_rx_pre_sys" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ila_rx_pre_sys_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_rx_pre_sys_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_rx_pre_sys_synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -1262,9 +1221,7 @@
     </Run>
     <Run Id="ila_rx_pre_ant_synth_1" Type="Ft3:Synth" SrcSet="ila_rx_pre_ant" Part="xc7k410tffg900-2" ConstrsSet="ila_rx_pre_ant" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/ila_rx_pre_ant_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_rx_pre_ant_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_rx_pre_ant_synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -1274,9 +1231,7 @@
     </Run>
     <Run Id="vio_ant_rd_synth_1" Type="Ft3:Synth" SrcSet="vio_ant_rd" Part="xc7k410tffg900-2" ConstrsSet="vio_ant_rd" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/vio_ant_rd_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_ant_rd_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_ant_rd_synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -1286,9 +1241,7 @@
     </Run>
     <Run Id="vio_cal_synth_1" Type="Ft3:Synth" SrcSet="vio_cal" Part="xc7k410tffg900-2" ConstrsSet="vio_cal" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/vio_cal_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_cal_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_cal_synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -1298,9 +1251,7 @@
     </Run>
     <Run Id="vio_clk_ld_rd_synth_1" Type="Ft3:Synth" SrcSet="vio_clk_ld_rd" Part="xc7k410tffg900-2" ConstrsSet="vio_clk_ld_rd" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/vio_clk_ld_rd_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_clk_ld_rd_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_clk_ld_rd_synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -1310,9 +1261,7 @@
     </Run>
     <Run Id="system_bd_spi_engine_execution_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_spi_engine_execution_0_0" Part="xc7k410tffg900-2" ConstrsSet="system_bd_spi_engine_execution_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_spi_engine_execution_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_spi_engine_execution_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_spi_engine_execution_0_0_synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -1322,9 +1271,7 @@
     </Run>
     <Run Id="system_bd_axi_gpio_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_axi_gpio_0_0" Part="xc7k410tffg900-2" ConstrsSet="system_bd_axi_gpio_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_axi_gpio_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_axi_gpio_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_axi_gpio_0_0_synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -1334,9 +1281,7 @@
     </Run>
     <Run Id="system_bd_ilmb_bram_if_cntlr_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_ilmb_bram_if_cntlr_0" Part="xc7k410tffg900-2" ConstrsSet="system_bd_ilmb_bram_if_cntlr_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_ilmb_bram_if_cntlr_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_ilmb_bram_if_cntlr_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_ilmb_bram_if_cntlr_0_synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -1346,9 +1291,7 @@
     </Run>
     <Run Id="system_bd_clk_wiz_1_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_clk_wiz_1_0" Part="xc7k410tffg900-2" ConstrsSet="system_bd_clk_wiz_1_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_clk_wiz_1_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_clk_wiz_1_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_clk_wiz_1_0_synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -1358,9 +1301,7 @@
     </Run>
     <Run Id="system_bd_lmb_bram_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_lmb_bram_0" Part="xc7k410tffg900-2" ConstrsSet="system_bd_lmb_bram_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_lmb_bram_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_lmb_bram_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_lmb_bram_0_synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -1370,9 +1311,7 @@
     </Run>
     <Run Id="system_bd_microblaze_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_microblaze_0_0" Part="xc7k410tffg900-2" ConstrsSet="system_bd_microblaze_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_microblaze_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_microblaze_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_microblaze_0_0_synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -1382,9 +1321,7 @@
     </Run>
     <Run Id="system_bd_dlmb_bram_if_cntlr_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_dlmb_bram_if_cntlr_0" Part="xc7k410tffg900-2" ConstrsSet="system_bd_dlmb_bram_if_cntlr_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_dlmb_bram_if_cntlr_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_dlmb_bram_if_cntlr_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_dlmb_bram_if_cntlr_0_synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -1394,9 +1331,7 @@
     </Run>
     <Run Id="system_bd_ilmb_v10_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_ilmb_v10_0" Part="xc7k410tffg900-2" ConstrsSet="system_bd_ilmb_v10_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_ilmb_v10_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_ilmb_v10_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_ilmb_v10_0_synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -1406,9 +1341,7 @@
     </Run>
     <Run Id="system_bd_dlmb_v10_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_dlmb_v10_0" Part="xc7k410tffg900-2" ConstrsSet="system_bd_dlmb_v10_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_dlmb_v10_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_dlmb_v10_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_dlmb_v10_0_synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -1418,9 +1351,7 @@
     </Run>
     <Run Id="system_bd_mdm_1_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_mdm_1_0" Part="xc7k410tffg900-2" ConstrsSet="system_bd_mdm_1_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_mdm_1_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_mdm_1_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_mdm_1_0_synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -1430,9 +1361,7 @@
     </Run>
     <Run Id="system_bd_axi_spi_engine_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_axi_spi_engine_0_0" Part="xc7k410tffg900-2" ConstrsSet="system_bd_axi_spi_engine_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_axi_spi_engine_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_axi_spi_engine_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_axi_spi_engine_0_0_synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -1442,9 +1371,7 @@
     </Run>
     <Run Id="system_bd_rst_clk_wiz_1_100M_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_rst_clk_wiz_1_100M_0" Part="xc7k410tffg900-2" ConstrsSet="system_bd_rst_clk_wiz_1_100M_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_rst_clk_wiz_1_100M_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_rst_clk_wiz_1_100M_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_rst_clk_wiz_1_100M_0_synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -1454,9 +1381,7 @@
     </Run>
     <Run Id="system_bd_xbar_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_xbar_0" Part="xc7k410tffg900-2" ConstrsSet="system_bd_xbar_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_xbar_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_xbar_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_xbar_0_synth_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -1466,9 +1391,7 @@
     </Run>
     <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 18 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -1486,9 +1409,7 @@
     </Run>
     <Run Id="fifo_AntCtrl_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="fifo_AntCtrl" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="fifo_AntCtrl_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/fifo_AntCtrl_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/fifo_AntCtrl_impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -1505,9 +1426,7 @@
     </Run>
     <Run Id="rotate_16b_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="rotate_16b" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="rotate_16b_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/rotate_16b_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/rotate_16b_impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -1524,9 +1443,7 @@
     </Run>
     <Run Id="ram_hop_data_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="ram_hop_data" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ram_hop_data_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ram_hop_data_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ram_hop_data_impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -1543,9 +1460,7 @@
     </Run>
     <Run Id="cmpy_12x12_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="cmpy_12x12" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="cmpy_12x12_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/cmpy_12x12_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/cmpy_12x12_impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -1562,9 +1477,7 @@
     </Run>
     <Run Id="fifo_accor_cdc_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="fifo_accor_cdc" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="fifo_accor_cdc_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/fifo_accor_cdc_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/fifo_accor_cdc_impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -1581,9 +1494,7 @@
     </Run>
     <Run Id="cmpy_16x12_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="cmpy_16x12" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="cmpy_16x12_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/cmpy_16x12_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/cmpy_16x12_impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -1600,9 +1511,7 @@
     </Run>
     <Run Id="fifo_weight_cdc_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="fifo_weight_cdc" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="fifo_weight_cdc_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/fifo_weight_cdc_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/fifo_weight_cdc_impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -1619,9 +1528,7 @@
     </Run>
     <Run Id="rom_hop_data_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="rom_hop_data" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="rom_hop_data_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/rom_hop_data_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/rom_hop_data_impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -1638,9 +1545,7 @@
     </Run>
     <Run Id="vio_rfcontrl_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="vio_rfcontrl" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="vio_rfcontrl_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_rfcontrl_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_rfcontrl_impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -1657,9 +1562,7 @@
     </Run>
     <Run Id="vio_ant_test_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="vio_ant_test" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="vio_ant_test_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_ant_test_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_ant_test_impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -1676,9 +1579,7 @@
     </Run>
     <Run Id="vio_rf_rd_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="vio_rf_rd" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="vio_rf_rd_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_rf_rd_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_rf_rd_impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -1695,9 +1596,7 @@
     </Run>
     <Run Id="vio_manual_ctrl_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="vio_manual_ctrl" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="vio_manual_ctrl_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_manual_ctrl_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_manual_ctrl_impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -1714,9 +1613,7 @@
     </Run>
     <Run Id="vio_phase_comp_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="vio_phase_comp" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="vio_phase_comp_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_phase_comp_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_phase_comp_impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -1733,9 +1630,7 @@
     </Run>
     <Run Id="atan2_16b_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="atan2_16b" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="atan2_16b_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/atan2_16b_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/atan2_16b_impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -1752,9 +1647,7 @@
     </Run>
     <Run Id="ila_rfcontrl_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="ila_rfcontrl" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ila_rfcontrl_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_rfcontrl_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_rfcontrl_impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -1771,9 +1664,7 @@
     </Run>
     <Run Id="ila_AntCtrl_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="ila_AntCtrl" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ila_AntCtrl_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_AntCtrl_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_AntCtrl_impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -1790,9 +1681,7 @@
     </Run>
     <Run Id="ila_2x12x1024_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="ila_2x12x1024" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ila_2x12x1024_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_2x12x1024_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_2x12x1024_impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -1809,9 +1698,7 @@
     </Run>
     <Run Id="ila_8x12_2x30_131072_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="ila_8x12_2x30_131072" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ila_8x12_2x30_131072_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_8x12_2x30_131072_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_8x12_2x30_131072_impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -1828,9 +1715,7 @@
     </Run>
     <Run Id="ila_cal_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="ila_cal" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ila_cal_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_cal_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_cal_impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -1847,9 +1732,7 @@
     </Run>
     <Run Id="ila_rx_pre_sys_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="ila_rx_pre_sys" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ila_rx_pre_sys_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_rx_pre_sys_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_rx_pre_sys_impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -1866,9 +1749,7 @@
     </Run>
     <Run Id="ila_rx_pre_ant_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="ila_rx_pre_ant" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="ila_rx_pre_ant_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/ila_rx_pre_ant_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/ila_rx_pre_ant_impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -1885,9 +1766,7 @@
     </Run>
     <Run Id="vio_ant_rd_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="vio_ant_rd" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="vio_ant_rd_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_ant_rd_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_ant_rd_impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -1904,9 +1783,7 @@
     </Run>
     <Run Id="vio_cal_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="vio_cal" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="vio_cal_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_cal_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_cal_impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -1923,9 +1800,7 @@
     </Run>
     <Run Id="vio_clk_ld_rd_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="vio_clk_ld_rd" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="vio_clk_ld_rd_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/vio_clk_ld_rd_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/vio_clk_ld_rd_impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -1942,9 +1817,7 @@
     </Run>
     <Run Id="system_bd_spi_engine_execution_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="system_bd_spi_engine_execution_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_spi_engine_execution_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_spi_engine_execution_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_spi_engine_execution_0_0_impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -1961,9 +1834,7 @@
     </Run>
     <Run Id="system_bd_axi_gpio_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="system_bd_axi_gpio_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_axi_gpio_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_axi_gpio_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_axi_gpio_0_0_impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -1980,9 +1851,7 @@
     </Run>
     <Run Id="system_bd_ilmb_bram_if_cntlr_0_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="system_bd_ilmb_bram_if_cntlr_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_ilmb_bram_if_cntlr_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_ilmb_bram_if_cntlr_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_ilmb_bram_if_cntlr_0_impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -1999,9 +1868,7 @@
     </Run>
     <Run Id="system_bd_clk_wiz_1_0_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="system_bd_clk_wiz_1_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_clk_wiz_1_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_clk_wiz_1_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_clk_wiz_1_0_impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -2018,9 +1885,7 @@
     </Run>
     <Run Id="system_bd_lmb_bram_0_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="system_bd_lmb_bram_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_lmb_bram_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_lmb_bram_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_lmb_bram_0_impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -2037,9 +1902,7 @@
     </Run>
     <Run Id="system_bd_microblaze_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="system_bd_microblaze_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_microblaze_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_microblaze_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_microblaze_0_0_impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -2056,9 +1919,7 @@
     </Run>
     <Run Id="system_bd_dlmb_bram_if_cntlr_0_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="system_bd_dlmb_bram_if_cntlr_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_dlmb_bram_if_cntlr_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_dlmb_bram_if_cntlr_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_dlmb_bram_if_cntlr_0_impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -2075,9 +1936,7 @@
     </Run>
     <Run Id="system_bd_ilmb_v10_0_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="system_bd_ilmb_v10_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_ilmb_v10_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_ilmb_v10_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_ilmb_v10_0_impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -2094,9 +1953,7 @@
     </Run>
     <Run Id="system_bd_dlmb_v10_0_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="system_bd_dlmb_v10_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_dlmb_v10_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_dlmb_v10_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_dlmb_v10_0_impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -2113,9 +1970,7 @@
     </Run>
     <Run Id="system_bd_mdm_1_0_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="system_bd_mdm_1_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_mdm_1_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_mdm_1_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_mdm_1_0_impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -2132,9 +1987,7 @@
     </Run>
     <Run Id="system_bd_axi_spi_engine_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="system_bd_axi_spi_engine_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_axi_spi_engine_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_axi_spi_engine_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_axi_spi_engine_0_0_impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -2151,9 +2004,7 @@
     </Run>
     <Run Id="system_bd_rst_clk_wiz_1_100M_0_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="system_bd_rst_clk_wiz_1_100M_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_rst_clk_wiz_1_100M_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_rst_clk_wiz_1_100M_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_rst_clk_wiz_1_100M_0_impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -2170,9 +2021,7 @@
     </Run>
     <Run Id="system_bd_xbar_0_impl_1" Type="Ft2:EntireDesign" Part="xc7k410tffg900-2" ConstrsSet="system_bd_xbar_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_xbar_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_xbar_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_xbar_0_impl_1">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/system_top.xsa

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+oid sha256:ff38e5b6d614299ccd049e5bca72a986b84c8209c589be7c31b453217cbc10ec
-size 2300905
+size 2300879

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/.cproject

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vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/.gitignore

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+<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- SW Build 4081461 on Thu Dec 14 12:22:04 MST 2023                  -->
+<!--                                                                         -->
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+<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Dec 14 2023                                                             -->
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+            <AddressRange Begin="32768" End="65535"/>
+            <BitLayout pattern=""/>
+            <Parity ON="false" NumBits="0"/>
+          </BitLane>
+          <BitLane MemType="RAMB36" Placement="X4Y63" Read_Width="0" SLR_INDEX="-1">
+            <DataWidth MSB="18" LSB="18"/>
+            <AddressRange Begin="32768" End="65535"/>
+            <BitLayout pattern=""/>
+            <Parity ON="false" NumBits="0"/>
+          </BitLane>
+          <BitLane MemType="RAMB36" Placement="X1Y67" Read_Width="0" SLR_INDEX="-1">
+            <DataWidth MSB="17" LSB="17"/>
+            <AddressRange Begin="32768" End="65535"/>
+            <BitLayout pattern=""/>
+            <Parity ON="false" NumBits="0"/>
+          </BitLane>
+          <BitLane MemType="RAMB36" Placement="X2Y67" Read_Width="0" SLR_INDEX="-1">
+            <DataWidth MSB="16" LSB="16"/>
+            <AddressRange Begin="32768" End="65535"/>
+            <BitLayout pattern=""/>
+            <Parity ON="false" NumBits="0"/>
+          </BitLane>
+          <BitLane MemType="RAMB36" Placement="X1Y51" Read_Width="0" SLR_INDEX="-1">
+            <DataWidth MSB="31" LSB="31"/>
+            <AddressRange Begin="32768" End="65535"/>
+            <BitLayout pattern=""/>
+            <Parity ON="false" NumBits="0"/>
+          </BitLane>
+          <BitLane MemType="RAMB36" Placement="X0Y49" Read_Width="0" SLR_INDEX="-1">
+            <DataWidth MSB="30" LSB="30"/>
+            <AddressRange Begin="32768" End="65535"/>
+            <BitLayout pattern=""/>
+            <Parity ON="false" NumBits="0"/>
+          </BitLane>
+          <BitLane MemType="RAMB36" Placement="X3Y56" Read_Width="0" SLR_INDEX="-1">
+            <DataWidth MSB="29" LSB="29"/>
+            <AddressRange Begin="32768" End="65535"/>
+            <BitLayout pattern=""/>
+            <Parity ON="false" NumBits="0"/>
+          </BitLane>
+          <BitLane MemType="RAMB36" Placement="X0Y53" Read_Width="0" SLR_INDEX="-1">
+            <DataWidth MSB="28" LSB="28"/>
+            <AddressRange Begin="32768" End="65535"/>
+            <BitLayout pattern=""/>
+            <Parity ON="false" NumBits="0"/>
+          </BitLane>
+          <BitLane MemType="RAMB36" Placement="X2Y54" Read_Width="0" SLR_INDEX="-1">
+            <DataWidth MSB="27" LSB="27"/>
+            <AddressRange Begin="32768" End="65535"/>
+            <BitLayout pattern=""/>
+            <Parity ON="false" NumBits="0"/>
+          </BitLane>
+          <BitLane MemType="RAMB36" Placement="X0Y45" Read_Width="0" SLR_INDEX="-1">
+            <DataWidth MSB="26" LSB="26"/>
+            <AddressRange Begin="32768" End="65535"/>
+            <BitLayout pattern=""/>
+            <Parity ON="false" NumBits="0"/>
+          </BitLane>
+          <BitLane MemType="RAMB36" Placement="X2Y48" Read_Width="0" SLR_INDEX="-1">
+            <DataWidth MSB="25" LSB="25"/>
+            <AddressRange Begin="32768" End="65535"/>
+            <BitLayout pattern=""/>
+            <Parity ON="false" NumBits="0"/>
+          </BitLane>
+          <BitLane MemType="RAMB36" Placement="X0Y51" Read_Width="0" SLR_INDEX="-1">
+            <DataWidth MSB="24" LSB="24"/>
+            <AddressRange Begin="32768" End="65535"/>
+            <BitLayout pattern=""/>
+            <Parity ON="false" NumBits="0"/>
+          </BitLane>
+        </BusBlock>
+      </AddressSpaceRange>
+    </AddressSpace>
+  </Processor>
+  <Config>
+    <Option Name="Part" Val="xc7k410tffg900-2"/>
+  </Config>
+  <DRC>
+    <Rule Name="RDADDRCHANGE" Val="false"/>
+  </DRC>
+</MemInfo>

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/_ide/hwspec.checksum

@@ -0,0 +1 @@
+1679918884

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/dl814_k7_48m.prj

@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="ASCII"?>
+<sdkproject:SdkProject xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:sdkproject="http://www.xilinx.com/sdkproject" name="dl814_k7_48m" location="/home/josh/Workspace/vivado/vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m" platform="/home/josh/Workspace/vivado/vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/export/dl814_k7_platform/dl814_k7_platform.xpfm" platformUID="xilinx:::0.0(custom)" systemProject="dl814_k7_48m_system" sysConfig="dl814_k7_platform" runtime="C/C++" cpu="standalone_domain" cpuInstance="microblaze_ps" os="standalone" mssSignature="bb143150eab354ba66e0eedf8ebdf8ea">
+  <configuration name="Debug" id="xilinx.gnu.mb.exe.debug.697452522">
+    <configBuildOptions xsi:type="sdkproject:SdkOptions"/>
+    <lastBuildOptions xsi:type="sdkproject:SdkOptions"/>
+  </configuration>
+  <configuration name="Release" id="xilinx.gnu.mb.exe.release.834811624" dirty="true">
+    <configBuildOptions xsi:type="sdkproject:SdkOptions"/>
+  </configuration>
+  <template appTemplateName="empty_application"/>
+</sdkproject:SdkProject>

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/src/README.txt

@@ -0,0 +1 @@
+Empty application. Add your own sources.

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/src/adi_noos/drivers/api/gpio.c

@@ -0,0 +1,184 @@
+/***************************************************************************//**
+ *   @file   gpio.c
+ *   @brief  Implementation of the GPIO Interface
+ *   @author Antoniu Miclaus ([email protected])
+********************************************************************************
+ * Copyright 2020(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#include <inttypes.h>
+#include <stdlib.h>
+#include "../../include/gpio.h"
+#include "../../include/error.h"
+
+/******************************************************************************/
+/************************ Functions Definitions *******************************/
+/******************************************************************************/
+
+/**
+ * @brief Obtain the GPIO decriptor.
+ * @param desc - The GPIO descriptor.
+ * @param param - GPIO Initialization parameters.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_get(struct gpio_desc **desc,
+		 const struct gpio_init_param *param)
+{
+	if (!param)
+		return FAILURE;
+
+	if ((param->platform_ops->gpio_ops_get(desc, param)))
+		return FAILURE;
+
+	(*desc)->platform_ops = param->platform_ops;
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Get the value of an optional GPIO.
+ * @param desc - The GPIO descriptor.
+ * @param param - GPIO Initialization parameters.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_get_optional(struct gpio_desc **desc,
+			  const struct gpio_init_param *param)
+{
+	if (!param || (param->number == -1)) {
+		*desc = NULL;
+		return SUCCESS;
+	}
+
+	if ((param->platform_ops->gpio_ops_get_optional(desc, param)))
+		return FAILURE;
+
+	(*desc)->platform_ops = param->platform_ops;
+
+	return SUCCESS;
+}
+/**
+ * @brief Free the resources allocated by gpio_get().
+ * @param desc - The GPIO descriptor.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_remove(struct gpio_desc *desc)
+{
+	if (desc)
+		return desc->platform_ops->gpio_ops_remove(desc);
+	else
+		return SUCCESS;
+}
+
+/**
+ * @brief Enable the input direction of the specified GPIO.
+ * @param desc - The GPIO descriptor.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_direction_input(struct gpio_desc *desc)
+{
+	if (desc)
+		return desc->platform_ops->gpio_ops_direction_input(desc);
+	else
+		return SUCCESS;
+}
+
+/**
+ * @brief Enable the output direction of the specified GPIO.
+ * @param desc - The GPIO descriptor.
+ * @param value - The value.
+ *                Example: GPIO_HIGH
+ *                         GPIO_LOW
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_direction_output(struct gpio_desc *desc,
+			      uint8_t value)
+{
+	if (desc)
+		return desc->platform_ops->
+		       gpio_ops_direction_output(desc, value);
+	else
+		return SUCCESS;
+}
+
+/**
+ * @brief Get the direction of the specified GPIO.
+ * @param desc - The GPIO descriptor.
+ * @param direction - The direction.
+ *                    Example: GPIO_OUT
+ *                             GPIO_IN
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_get_direction(struct gpio_desc *desc,
+			   uint8_t *direction)
+{
+	if (desc)
+		return desc->platform_ops->
+		       gpio_ops_get_direction(desc, direction);
+	else
+		return SUCCESS;
+}
+
+/**
+ * @brief Set the value of the specified GPIO.
+ * @param desc - The GPIO descriptor.
+ * @param value - The value.
+ *                Example: GPIO_HIGH
+ *                         GPIO_LOW
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_set_value(struct gpio_desc *desc,
+		       uint8_t value)
+{
+	if (desc)
+		return desc->platform_ops->gpio_ops_set_value(desc, value);
+	else
+		return SUCCESS;
+}
+
+/**
+ * @brief Get the value of the specified GPIO.
+ * @param desc - The GPIO descriptor.
+ * @param value - The value.
+ *                Example: GPIO_HIGH
+ *                         GPIO_LOW
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t gpio_get_value(struct gpio_desc *desc,
+		       uint8_t *value)
+{
+	if (desc)
+		return desc->platform_ops->gpio_ops_get_value(desc, value);
+	else
+		return SUCCESS;
+}

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/src/adi_noos/drivers/api/irq.c

@@ -0,0 +1,153 @@
+/***************************************************************************//**
+ *   @file   irq.c
+ *   @brief  Implementation of the IRQ Interface
+ *   @author Andrei Porumb ([email protected])
+********************************************************************************
+ * Copyright 2021(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#include <inttypes.h>
+#include <stdlib.h>
+#include "../../include/irq.h"
+#include "../../include/error.h"
+
+/**
+ * @brief Initialize the IRQ interrupts.
+ * @param desc - The IRQ descriptor.
+ * @param param - The structure that contains the IRQ parameters.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t irq_ctrl_init(struct irq_ctrl_desc **desc,
+		      const struct irq_init_param *param)
+{
+	if (!param)
+		return FAILURE;
+
+	if ((param->platform_ops->init(desc, param)))
+		return FAILURE;
+
+	(*desc)->platform_ops = param->platform_ops;
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Free the resources allocated by irq_ctrl_init().
+ * @param desc - The SPI descriptor.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t irq_ctrl_remove(struct irq_ctrl_desc *desc)
+{
+	return desc->platform_ops->remove(desc);
+}
+
+/**
+ * @brief Register a callback to handle the irq events.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @param callback_desc - Callback descriptor
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t irq_register_callback(struct irq_ctrl_desc *desc, uint32_t irq_id,
+			      struct callback_desc *callback_desc)
+{
+	return desc->platform_ops->register_callback(desc, irq_id, callback_desc);
+}
+
+/**
+ * @brief Unregisters a generic IRQ handling function.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t irq_unregister(struct irq_ctrl_desc *desc, uint32_t irq_id)
+{
+	return desc->platform_ops->unregister(desc, irq_id);
+}
+
+/**
+ * @brief Enable global interrupts.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t irq_global_enable(struct irq_ctrl_desc *desc)
+{
+	return desc->platform_ops->global_enable(desc);
+}
+
+/**
+ * @brief Disable global interrupts.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t irq_global_disable(struct irq_ctrl_desc *desc)
+{
+	return desc->platform_ops->global_disable(desc);
+}
+
+/**
+ * @brief Set interrupt trigger level.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @param trig - New trigger level for the interrupt.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t irq_trigger_level_set(struct irq_ctrl_desc *desc, uint32_t irq_id,
+			      enum irq_trig_level trig)
+{
+	if(desc->platform_ops->trigger_level_set)
+		return desc->platform_ops->trigger_level_set(desc, irq_id, trig);
+	else
+		return ENOSYS;
+}
+
+/**
+ * @brief Enable specific interrupt.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t irq_enable(struct irq_ctrl_desc *desc, uint32_t irq_id)
+{
+	return desc->platform_ops->enable(desc, irq_id);
+}
+
+/**
+ * @brief Disable specific interrupt.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t irq_disable(struct irq_ctrl_desc *desc, uint32_t irq_id)
+{
+	return desc->platform_ops->disable(desc, irq_id);
+}

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/src/adi_noos/drivers/api/spi.c

@@ -0,0 +1,144 @@
+/***************************************************************************//**
+ *   @file   spi.c
+ *   @brief  Implementation of the SPI Interface
+ *   @author Antoniu Miclaus ([email protected])
+********************************************************************************
+ * Copyright 2020(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#include <inttypes.h>
+#include <stdlib.h>
+#include <string.h>
+#include "../../include/spi.h"
+#include "../../include/error.h"
+
+/**
+ * @brief Initialize the SPI communication peripheral.
+ * @param desc - The SPI descriptor.
+ * @param param - The structure that contains the SPI parameters.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t spi_init(struct spi_desc **desc,
+		 const struct spi_init_param *param)
+{
+	if (!param)
+		return FAILURE;
+
+	if ((param->platform_ops->init(desc, param)))
+		return FAILURE;
+
+	(*desc)->platform_ops = param->platform_ops;
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Free the resources allocated by spi_init().
+ * @param desc - The SPI descriptor.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t spi_remove(struct spi_desc *desc)
+{
+	return desc->platform_ops->remove(desc);
+}
+
+/**
+ * @brief Write and read data to/from SPI.
+ * @param desc - The SPI descriptor.
+ * @param data - The buffer with the transmitted/received data.
+ * @param bytes_number - Number of bytes to write/read.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t spi_write_and_read(struct spi_desc *desc,
+			   uint8_t *data,
+			   uint16_t bytes_number)
+{
+	return desc->platform_ops->write_and_read(desc, data, bytes_number);
+}
+
+/**
+ * @brief Write and read data to/from SPI in 3 wire mode.
+ * @param desc - The SPI descriptor.
+ * @param write_data - The buffer with the transmitted data.
+ * @param read_data - The buffer with the received data.
+ * @param write_bytes_number - Number of bytes to write.
+ * @param read_bytes_number - Number of bytes to read.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t spi_write_and_read_3wire(struct spi_desc *desc,
+			   uint8_t *write_data,
+			   uint8_t *read_data,
+			   uint16_t write_bytes_number,
+			   uint16_t read_bytes_number)
+{
+	int ret;
+	if(desc->platform_ops->write_and_read_3wire != NULL){
+		return desc->platform_ops->write_and_read_3wire(desc, write_data, read_data,
+			write_bytes_number, read_bytes_number);
+	}
+	else{
+		return FAILURE;
+	}
+}
+
+
+/**
+ * @brief  Iterate over head list and send all spi messages
+ * @param desc - The SPI descriptor.
+ * @param msgs - Array of messages.
+ * @param len - Number of messages in the array.
+ * @return SUCCESS in case of success, negativ error code otherwise.
+ */
+int32_t spi_transfer(struct spi_desc *desc, struct spi_msg *msgs, uint32_t len)
+{
+	int32_t  ret;
+	uint32_t i;
+
+	if (!desc || !desc->platform_ops)
+		return -EINVAL;
+
+	if (desc->platform_ops->transfer)
+		return desc->platform_ops->transfer(desc, msgs, len);
+
+	for (i = 0; i < len; i++) {
+		if (msgs[i].rx_buff != msgs[i].tx_buff || !msgs[i].tx_buff)
+			return -EINVAL;
+		ret = spi_write_and_read(desc, msgs[i].rx_buff,
+					 msgs[i].bytes_number);
+		if (IS_ERR_VALUE(ret))
+			return ret;
+	}
+
+	return SUCCESS;
+}

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/src/adi_noos/drivers/axi_core/axi_dmac/axi_dmac.c

@@ -0,0 +1,328 @@
+/***************************************************************************//**
+ *   @file   axi_dmac.c
+ *   @brief  Driver for the Analog Devices AXI-DMAC core.
+ *   @author DBogdan ([email protected])
+********************************************************************************
+ * Copyright 2018(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+#include <stdlib.h>
+#include <stdio.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include "../../../include/axi_io.h"
+#include "../../../include/error.h"
+#include "../axi_dmac/axi_dmac.h"
+
+/***************************************************************************//**
+ * @brief dma_isr
+*******************************************************************************/
+void axi_dmac_default_isr(void *instance)
+{
+	struct axi_dmac *dmac = (struct axi_dmac *)instance;
+	uint32_t remaining_size, burst_size;
+	uint32_t reg_val;
+
+	/* Get interrupt sources and clear interrupts. */
+	axi_dmac_read(dmac, AXI_DMAC_REG_IRQ_PENDING, &reg_val);
+	axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_PENDING, reg_val);
+
+	if ((reg_val & AXI_DMAC_IRQ_SOT) && (dmac->big_transfer.size != 0)) {
+		remaining_size = dmac->big_transfer.size -
+				 dmac->big_transfer.size_done;
+		burst_size = (remaining_size <= dmac->transfer_max_size) ?
+			     remaining_size : dmac->transfer_max_size;
+
+		dmac->big_transfer.size_done += burst_size;
+		dmac->big_transfer.address += burst_size;
+		switch (dmac->direction) {
+		case DMA_DEV_TO_MEM:
+			axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS,
+				       dmac->big_transfer.address);
+			axi_dmac_write(dmac, AXI_DMAC_REG_DEST_STRIDE, 0x0);
+			break;
+		case DMA_MEM_TO_DEV:
+			axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS,
+				       dmac->big_transfer.address);
+			axi_dmac_write(dmac, AXI_DMAC_REG_SRC_STRIDE, 0x0);
+			break;
+		default:
+			return; // Other directions are not supported yet
+		}
+		/* The current transfer was started and a new one is queued. */
+		axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH,
+			       burst_size);
+		axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0);
+
+		axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1);
+	}
+	if (reg_val & AXI_DMAC_IRQ_EOT) {
+		dmac->big_transfer.transfer_done = true;
+		dmac->big_transfer.address = 0;
+		dmac->big_transfer.size = 0;
+		dmac->big_transfer.size_done = 0;
+	}
+}
+
+/***************************************************************************//**
+ * @brief axi_dmac_read
+ *******************************************************************************/
+int32_t axi_dmac_read(struct axi_dmac *dmac,
+		      uint32_t reg_addr,
+		      uint32_t *reg_data)
+{
+	axi_io_read(dmac->base, reg_addr, reg_data);
+
+	return SUCCESS;
+}
+
+/***************************************************************************//**
+ * @brief axi_dmac_write
+ *******************************************************************************/
+int32_t axi_dmac_write(struct axi_dmac *dmac,
+		       uint32_t reg_addr,
+		       uint32_t reg_data)
+{
+	axi_io_write(dmac->base, reg_addr, reg_data);
+
+	return SUCCESS;
+}
+
+/***************************************************************************//**
+ * @brief axi_dmac_transfer_nonblock
+ *******************************************************************************/
+int32_t axi_dmac_transfer_nonblocking(struct axi_dmac *dmac,
+				      uint32_t address, uint32_t size)
+{
+	uint32_t reg_val;
+
+	if (size == 0)
+		return SUCCESS; /* nothing to do */
+
+	axi_dmac_read(dmac, AXI_DMAC_REG_CTRL, &reg_val);
+	if (!(reg_val & AXI_DMAC_CTRL_ENABLE)) {
+		axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, 0x0);
+		axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, AXI_DMAC_CTRL_ENABLE);
+		axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_MASK, 0x0);
+	}
+
+	axi_dmac_read(dmac, AXI_DMAC_REG_START_TRANSFER, &reg_val);
+	if (!(reg_val & 1)) {
+		switch (dmac->direction) {
+		case DMA_DEV_TO_MEM:
+			axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS, address);
+			axi_dmac_write(dmac, AXI_DMAC_REG_DEST_STRIDE, 0x0);
+			break;
+		case DMA_MEM_TO_DEV:
+			axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS, address);
+			axi_dmac_write(dmac, AXI_DMAC_REG_SRC_STRIDE, 0x0);
+			break;
+		default:
+			return FAILURE; // Other directions are not supported yet
+		}
+		if ((size - 1) > dmac->transfer_max_size) {
+			dmac->big_transfer.address = address;
+			dmac->big_transfer.size = size - 1;
+			dmac->big_transfer.size_done = dmac->transfer_max_size;
+
+			axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH,
+				       dmac->transfer_max_size);
+			axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0);
+
+			axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, dmac->flags);
+
+			axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1);
+		} else {
+			axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH,
+				       size - 1);
+			axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0);
+
+			axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, dmac->flags);
+
+			axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1);
+		}
+	} else {
+		return FAILURE;
+	}
+
+	return SUCCESS;
+}
+
+/***************************************************************************//**
+ * @brief axi_dmac_is_transfer_ready
+ *******************************************************************************/
+int32_t axi_dmac_is_transfer_ready(struct axi_dmac *dmac, bool *rdy)
+{
+	*rdy = dmac->big_transfer.transfer_done;
+
+	return SUCCESS;
+}
+
+/***************************************************************************//**
+ * @brief axi_dmac_transfer
+ *******************************************************************************/
+int32_t axi_dmac_transfer(struct axi_dmac *dmac,
+			  uint32_t address, uint32_t size)
+{
+	uint32_t transfer_id;
+	uint32_t reg_val;
+	uint32_t timeout = 0;
+
+	if (size == 0)
+		return SUCCESS; /* nothing to do */
+
+	axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, 0x0);
+	axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, AXI_DMAC_CTRL_ENABLE);
+
+	axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_MASK, 0x0);
+
+	axi_dmac_read(dmac, AXI_DMAC_REG_TRANSFER_ID, &transfer_id);
+	axi_dmac_read(dmac, AXI_DMAC_REG_IRQ_PENDING, &reg_val);
+	axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_PENDING, reg_val);
+
+	switch (dmac->direction) {
+	case DMA_DEV_TO_MEM:
+		axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS, address);
+		axi_dmac_write(dmac, AXI_DMAC_REG_DEST_STRIDE, 0x0);
+		break;
+	case DMA_MEM_TO_DEV:
+		axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS, address);
+		axi_dmac_write(dmac, AXI_DMAC_REG_SRC_STRIDE, 0x0);
+		break;
+	default:
+		return FAILURE; // Other directions are not supported yet
+	}
+
+	if ((size - 1) > dmac->transfer_max_size) {
+		dmac->big_transfer.address = address;
+		dmac->big_transfer.size = size - 1;
+		dmac->big_transfer.size_done = dmac->transfer_max_size;
+
+		axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH,
+			       dmac->transfer_max_size);
+		axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0);
+
+		axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, dmac->flags);
+
+		axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1);
+
+		while(!dmac->big_transfer.transfer_done) {
+			timeout++;
+			if (timeout == UINT32_MAX)
+				return FAILURE;
+		}
+
+		dmac->big_transfer.address = 0;
+		dmac->big_transfer.size = 0;
+		dmac->big_transfer.size_done = 0;
+
+		return SUCCESS;
+	}
+
+	axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, size - 1);
+	axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0);
+
+	axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, dmac->flags);
+
+	axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1);
+
+	if (dmac->flags & DMA_CYCLIC)
+		return SUCCESS;
+
+	/* Wait until the new transfer is queued. */
+	do {
+		axi_dmac_read(dmac, AXI_DMAC_REG_START_TRANSFER, &reg_val);
+	} while(reg_val == 1);
+
+	/* Wait until the current transfer is completed. */
+	do {
+		axi_dmac_read(dmac, AXI_DMAC_REG_IRQ_PENDING, &reg_val);
+		if (reg_val == (AXI_DMAC_IRQ_SOT | AXI_DMAC_IRQ_EOT))
+			break;
+	} while(!dmac->big_transfer.transfer_done);
+	if (reg_val != (AXI_DMAC_IRQ_SOT | AXI_DMAC_IRQ_EOT))
+		axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_PENDING, reg_val);
+
+	/* Wait until the transfer with the ID transfer_id is completed. */
+	do {
+		axi_dmac_read(dmac, AXI_DMAC_REG_TRANSFER_DONE, &reg_val);
+	} while((reg_val & (1u << transfer_id)) != (1u << transfer_id));
+
+	return SUCCESS;
+}
+
+/***************************************************************************//**
+ * @brief axi_dmac_init
+ *******************************************************************************/
+int32_t axi_dmac_init(struct axi_dmac **dmac_core,
+		      const struct axi_dmac_init *init)
+{
+	struct axi_dmac *dmac;
+
+	dmac = (struct axi_dmac *)malloc(sizeof(*dmac));
+	if (!dmac)
+		return FAILURE;
+
+	dmac->name = init->name;
+	dmac->base = init->base;
+	dmac->direction = init->direction;
+	dmac->flags = init->flags;
+	dmac->transfer_max_size = -1;
+	dmac->big_transfer.address = 0;
+	dmac->big_transfer.size = 0;
+	dmac->big_transfer.size_done = 0;
+
+	axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, dmac->transfer_max_size);
+	axi_dmac_read(dmac, AXI_DMAC_REG_X_LENGTH, &dmac->transfer_max_size);
+
+	*dmac_core = dmac;
+
+	return SUCCESS;
+}
+
+/***************************************************************************//**
+ * @brief axi_dmac_remove
+ *******************************************************************************/
+int32_t axi_dmac_remove(struct axi_dmac *dmac)
+{
+	if(!dmac)
+		return FAILURE;
+
+	free(dmac);
+
+	return SUCCESS;
+}

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/src/adi_noos/drivers/axi_core/axi_dmac/axi_dmac.h

@@ -0,0 +1,124 @@
+/***************************************************************************//**
+ *   @file   axi_dmac.h
+ *   @brief  Driver for the Analog Devices AXI-DMAC core.
+ *   @author DBogdan ([email protected])
+********************************************************************************
+ * Copyright 2018(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+#ifndef AXI_DMAC_H_
+#define AXI_DMAC_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+#include <stdint.h>
+#include "../../../include/util.h"
+
+/******************************************************************************/
+/********************** Macros and Constants Definitions **********************/
+/******************************************************************************/
+#define AXI_DMAC_REG_IRQ_MASK		0x80
+#define AXI_DMAC_REG_IRQ_PENDING	0x84
+#define AXI_DMAC_IRQ_SOT			BIT(0)
+#define AXI_DMAC_IRQ_EOT			BIT(1)
+
+#define AXI_DMAC_REG_CTRL			0x400
+#define AXI_DMAC_CTRL_ENABLE		BIT(0)
+#define AXI_DMAC_CTRL_PAUSE			BIT(1)
+
+#define AXI_DMAC_REG_TRANSFER_ID	0x404
+#define AXI_DMAC_REG_START_TRANSFER	0x408
+#define AXI_DMAC_REG_FLAGS			0x40c
+#define AXI_DMAC_REG_DEST_ADDRESS	0x410
+#define AXI_DMAC_REG_SRC_ADDRESS	0x414
+#define AXI_DMAC_REG_X_LENGTH		0x418
+#define AXI_DMAC_REG_Y_LENGTH		0x41c
+#define AXI_DMAC_REG_DEST_STRIDE	0x420
+#define AXI_DMAC_REG_SRC_STRIDE		0x424
+#define AXI_DMAC_REG_TRANSFER_DONE	0x428
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+enum dma_direction {
+	DMA_DEV_TO_MEM,
+	DMA_MEM_TO_DEV
+};
+
+enum dma_flags {
+	DMA_CYCLIC = 1,
+	DMA_LAST = 2
+};
+
+struct axi_dma_transfer {
+	uint32_t size;
+	uint32_t address;
+	uint32_t size_done;
+	volatile bool transfer_done;
+};
+
+struct axi_dmac {
+	const char *name;
+	uint32_t base;
+	enum dma_direction direction;
+	uint32_t flags;
+	uint32_t transfer_max_size;
+	volatile struct axi_dma_transfer big_transfer;
+};
+
+struct axi_dmac_init {
+	const char *name;
+	uint32_t base;
+	enum dma_direction direction;
+	uint32_t flags;
+};
+
+/******************************************************************************/
+/************************ Functions Declarations ******************************/
+/******************************************************************************/
+void axi_dmac_default_isr(void *instance);
+int32_t axi_dmac_read(struct axi_dmac *dmac, uint32_t reg_addr,
+		      uint32_t *reg_data);
+int32_t axi_dmac_write(struct axi_dmac *dmac, uint32_t reg_addr,
+		       uint32_t reg_data);
+int32_t axi_dmac_transfer_nonblocking(struct axi_dmac *dmac,
+				      uint32_t address, uint32_t size);
+int32_t axi_dmac_is_transfer_ready(struct axi_dmac *dmac, bool *rdy);
+int32_t axi_dmac_transfer(struct axi_dmac *dmac,
+			  uint32_t address, uint32_t size);
+int32_t axi_dmac_init(struct axi_dmac **adc_core,
+		      const struct axi_dmac_init *init);
+int32_t axi_dmac_remove(struct axi_dmac *dmac);
+
+#endif

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/src/adi_noos/drivers/axi_core/spi_engine/spi_engine.c

@@ -0,0 +1,978 @@
+/*******************************************************************************
+ *   @file   spi_engine.c
+ *   @brief  Core implementation of the SPI Engine Driver.
+ *   @author Sergiu Cuciurean ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************/
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+/* In debug mode the printf function used in displaying the messages is causing
+significant delays */
+//#define DEBUG_LEVEL 2
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <sleep.h>
+#include <inttypes.h>
+
+#include "spi_engine.h"
+#include "../axi_dmac/axi_dmac.h"
+#include "../../../include/axi_io.h"
+#include "../../../include/error.h"
+
+/**
+ * @brief Spi engine platform specific SPI platform ops structure
+ */
+const struct spi_platform_ops spi_eng_platform_ops = {
+	.init = &spi_engine_init,
+	.write_and_read = &spi_engine_spi_write_and_read,
+	.write_and_read_3wire = &spi_engine_spi_write_and_read_3wire,
+	.remove = &spi_engine_remove
+};
+
+/******************************************************************************/
+/***************************** Static variables *******************************/
+/******************************************************************************/
+
+/**
+ * @brief Static variable used to sync transfers
+ *
+ */
+static uint8_t _sync_id = 0x01;
+
+/******************************************************************************/
+/************************** Functions Implementation **************************/
+/******************************************************************************/
+
+/**
+ * @brief Write SPI Engine's axi registers
+ *
+ * @param desc Decriptor containing SPI Engine's parameters
+ * @param reg_addr The address of the SPI Engine's axi register where the data
+ * 	will be written
+ * @param reg_data Data that will be written
+ * @return int32_t This function allways returns SUCCESS
+ */
+int32_t spi_engine_write(struct spi_engine_desc *desc,
+			 uint32_t reg_addr,
+			 uint32_t reg_data)
+{
+	axi_io_write(desc->spi_engine_baseaddr, reg_addr, reg_data);
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Read SPI Engine's axi registers
+ *
+ * @param desc Decriptor containing SPI Engine's parameters
+ * @param reg_addr The address of the SPI Engine's axi register from where the
+ * 	data where the data will be read
+ * @param reg_data Pointer where the read that will be stored
+ * @return int32_t This function allways returns SUCCESS
+ */
+int32_t spi_engine_read(struct spi_engine_desc *desc,
+			uint32_t reg_addr,
+			uint32_t *reg_data)
+{
+	axi_io_read(desc->spi_engine_baseaddr, reg_addr, reg_data);
+	return SUCCESS;
+}
+
+/**
+ * @brief Set width of the transferred word over SPI
+ *
+ * @param desc Decriptor containing SPI interface parameters
+ * @param data_width The desired data width
+ * 	The supported values are:
+ * 		- 8
+ * 		- 16
+ * 		- 24
+ * 		- 32
+ */
+int32_t spi_engine_set_transfer_width(struct spi_desc *desc,
+				      uint8_t data_width)
+{
+	struct spi_engine_desc	*desc_extra;
+
+	desc_extra = desc->extra;
+
+	if (data_width > desc_extra->max_data_width)
+		desc_extra->data_width = desc_extra->max_data_width;
+	else
+		desc_extra->data_width = data_width;
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Set SPI engine clock frequency
+ *
+ * @param desc Decriptor containing SPI Engine's parameters
+ * @param speed_hz SPI engine transfer speed
+ */
+void spi_engine_set_speed(struct spi_desc *desc,
+			  uint32_t speed_hz)
+{
+	struct spi_engine_desc	*desc_extra;
+
+	desc_extra = desc->extra;
+
+	desc_extra->clk_div =  desc_extra->ref_clk_hz /
+			       (2 * speed_hz) - 1;
+}
+
+/**
+ * @brief Set the number of words transferred in a single transaction
+ *
+ * @param desc Decriptor containing SPI Engine's parameters
+ * @param bytes_number The number of bytes to be converted
+ * @return uint8_t A number of words in which bytes_number can be grouped
+ */
+static uint8_t spi_get_words_number(struct spi_engine_desc *desc,
+				    uint8_t bytes_number)
+{
+	uint8_t xfer_word_len;
+	uint8_t words_number;
+
+	xfer_word_len = desc->data_width / 8;
+	words_number = bytes_number / xfer_word_len;
+
+	if ((bytes_number % xfer_word_len) != 0)
+		words_number++;
+
+	return words_number;
+}
+
+/**
+ * @brief Get the word length in bytes
+ *
+ * @param desc Decriptor containing SPI Engine's parameters
+ * @return uint8_t Number of bytes that fit in one word
+ */
+static uint8_t spi_get_word_length(struct spi_engine_desc *desc)
+{
+	uint8_t word_length;
+
+	word_length = desc->data_width / 8;
+
+	return word_length;
+}
+
+/**
+ * @brief Compute the prescaler used to set the sleep period.
+ *
+ * @param desc Decriptor containing SPI interface parameters
+ * @param sleep_time_ns The amount of time where the transfer hangs
+ * @param sleep_div Clock prescaler
+ * @return int32_t This function allways returns SUCCESS
+ */
+static int32_t spi_get_sleep_div(struct spi_desc *desc,
+				 uint32_t sleep_time_ns,
+				 uint32_t *sleep_div)
+{
+	struct spi_engine_desc	*eng_desc;
+
+	eng_desc = desc->extra;
+
+	/*
+	 * Engine Wiki:
+	 *
+	 * The frequency of the SCLK signal is derived from the
+	 * module clock frequency using the following formula:
+	 * f_sclk = f_clk / ((div + 1) * 2)
+	 */
+
+	*sleep_div = (desc->max_speed_hz / 1000000 * sleep_time_ns / 1000) /
+		     ((eng_desc->clk_div + 1) * 2) - 1;
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Create a new commands queue used in a spi transfer
+ *
+ * @param fifo Command buffer, usually used in fifo mode
+ * @param cmd Command with witch the buffer will be initiated
+ * @return int32_t Failure if the memory allocation failed
+ */
+static int32_t spi_engine_queue_new_cmd(struct spi_engine_cmd_queue **fifo,
+					uint32_t cmd)
+{
+	struct spi_engine_cmd_queue *local_fifo;
+
+	local_fifo = (spi_engine_cmd_queue*)malloc(sizeof(*local_fifo));
+
+	if(!local_fifo)
+		return FAILURE;
+
+	local_fifo->cmd = cmd;
+	local_fifo->next = NULL;
+	*fifo = local_fifo;
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Add a command at the end of an existing queue
+ *
+ * @param fifo Command buffer, usually used in fifo mode
+ * @param cmd Command to be added
+ */
+static void spi_engine_queue_add_cmd(struct spi_engine_cmd_queue **fifo,
+				     uint32_t cmd)
+{
+	struct spi_engine_cmd_queue *to_add = NULL;
+	struct spi_engine_cmd_queue *local_fifo;
+
+	local_fifo = *fifo;
+	while (local_fifo->next != NULL) {
+		// Get the last element
+		local_fifo = local_fifo->next;
+	}
+
+	// Create a new element
+	spi_engine_queue_new_cmd(&to_add, cmd);
+	// Add as the next element
+	local_fifo->next = to_add;
+}
+
+/**
+ * @brief Add a command at the beginning of an existing queue
+ *
+ * @param fifo Command buffer, usually used in fifo mode
+ * @param cmd Command to be added
+ */
+static void spi_engine_queue_append_cmd(struct spi_engine_cmd_queue **fifo,
+					uint32_t cmd)
+{
+	struct spi_engine_cmd_queue *to_add = NULL;
+
+	// Create a new element
+	spi_engine_queue_new_cmd(&to_add, cmd);
+	// Interchange the addresses
+	to_add->next = *fifo;
+	*fifo = to_add;
+}
+
+
+/**
+ * @brief Get the command from the beginning of the queue
+ *
+ * @param fifo Command buffer, usually used in fifo mode
+ * @param cmd Value of the command that was extracted
+ * @return int32_t Return FAILURE if the queue is empty
+ */
+static int32_t spi_engine_queue_get_cmd(struct spi_engine_cmd_queue **fifo,
+					uint32_t *cmd)
+{
+	struct spi_engine_cmd_queue *local_fifo;
+
+	if (!*fifo)
+		return FAILURE;
+
+	local_fifo = *fifo;
+	*cmd = local_fifo->cmd;
+	if ((*fifo)->next) {
+		*fifo = local_fifo->next;
+		free(local_fifo);
+	} else {
+		free(*fifo);
+		*fifo = NULL;
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Free the memory allocated by a queue
+ *
+ * @param fifo The queue that needs it's memory freed
+ * @return int32_t This function allways return SUCCESS
+ */
+static int32_t spi_engine_queue_free(struct spi_engine_cmd_queue **fifo)
+{
+	if(*fifo && (*fifo)->next)
+		spi_engine_queue_free(&(*fifo)->next);
+	if((*fifo) != NULL) {
+		free(*fifo);
+		*fifo = NULL;
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Write the SPI engine's command fifo
+ *
+ * @param desc Decriptor containing SPI Engine's parameters
+ * @param cmd The command that will be written
+ * @return int32_t Returns FAILURE if the the axi transfer failed
+ */
+static int32_t spi_engine_write_cmd_reg(struct spi_engine_desc *desc,
+					uint32_t cmd)
+{
+	int32_t ret;
+
+	/* Check if offload is enabled */
+	if(desc->offload_config & (OFFLOAD_TX_EN | OFFLOAD_RX_EN)) {
+		ret = spi_engine_write(desc,
+				       SPI_ENGINE_REG_OFFLOAD_CMD_MEM(0),
+				       cmd);
+
+	} else {
+		ret = spi_engine_write(desc,
+				       SPI_ENGINE_REG_CMD_FIFO,
+				       cmd);
+	}
+
+	return ret;
+}
+
+/**
+ * @brief Write a transfer command to the SPI engine's command fifo
+ *
+ * @param desc Decriptor containing SPI Engine's parameters
+ * @param read_write Read/Write operation flag
+ * @param bytes_number Number of bytes to transfer
+ * @return int32_t This function allways returns SUCCESS
+ */
+static int32_t spi_engine_transfer(struct spi_engine_desc *desc,
+				   uint8_t read_write,
+				   uint8_t bytes_number)
+{
+	uint8_t words_number;
+
+	words_number = spi_get_words_number(desc, bytes_number);
+
+	desc->offload_tx_len += words_number;
+
+	/*
+	 * Engine Wiki:
+	 *
+	 * https://wiki.analog.com/resources/fpga/peripherals/spi_engine
+	 *
+	 * The words number is zero based
+	 */
+
+	spi_engine_write_cmd_reg(desc,
+				 SPI_ENGINE_CMD_TRANSFER(read_write,
+						 words_number  - 1));
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Change the state of the chip select port
+ *
+ * @param desc Decriptor containing SPI interface parameters
+ * @param assert Chip select state.
+ * 		 The supported values are :
+ * 			-true (HIGH)
+ * 			-false (LOW)
+ */
+static void spi_engine_set_cs(struct spi_desc *desc,
+			      bool assert)
+{
+	uint8_t			mask;
+	struct spi_engine_desc	*eng_desc;
+
+	eng_desc = desc->extra;
+
+	mask = 0xFF;
+	/* Switch the state only of the selected chip select */
+	if (!assert)
+		mask ^= BIT(desc->chip_select);
+
+	spi_engine_write_cmd_reg(eng_desc,
+				 SPI_ENGINE_CMD_ASSERT(eng_desc->cs_delay,
+						 mask));
+}
+
+/**
+ * @brief Add a delay between the engine commands
+ *
+ * @param desc Decriptor containing SPI interface parameters
+ * @param sleep_time_ns Number of nanoseconds to sleep between commands
+ */
+static void spi_gen_sleep_ns(struct spi_desc *desc,
+			     uint32_t sleep_time_ns)
+{
+	uint32_t 		sleep_div;
+	struct spi_engine_desc	*eng_desc;
+
+	eng_desc = desc->extra;
+
+	spi_get_sleep_div(desc, sleep_time_ns, &sleep_div);
+
+	spi_engine_write_cmd_reg(eng_desc, SPI_ENGINE_CMD_SLEEP(sleep_div));
+}
+
+/**
+ * @brief Spi engine command interpreter
+ *
+ * @param desc Decriptor containing SPI interface parameters
+ * @param cmd Command to send to the engine
+ * @return int32_t - SUCCESS if the command is transferred
+ *		   - FAILURE if the command format is invalid
+ */
+static int32_t spi_engine_write_cmd(struct spi_desc *desc,
+				    uint32_t cmd)
+{
+	uint8_t				engine_command;
+	uint8_t				parameter;
+	uint8_t				modifier;
+	struct spi_engine_desc		*desc_extra;
+
+	desc_extra = desc->extra;
+
+	engine_command = (cmd >> 12) & 0x0F;
+	modifier = (cmd >> 8) & 0x0F;
+	parameter = cmd & 0xFF;
+
+	switch(engine_command) {
+	case SPI_ENGINE_INST_TRANSFER:
+		spi_engine_transfer(desc_extra, modifier, parameter);
+		break;
+
+	case SPI_ENGINE_INST_ASSERT:
+		if(parameter == 0xFF) {
+			/* Set the CS HIGH */
+			spi_engine_set_cs(desc, true);
+		} else if(parameter == 0x00) {
+			/* Set the CS LOW */
+			spi_engine_set_cs(desc, false);
+		}
+		break;
+
+	/* The SYNC and SLEEP commands got the same value but different
+	modifier */
+	case SPI_ENGINE_INST_SYNC_SLEEP:
+		/* SYNC instruction */
+		if(modifier == 0x00) {
+			spi_engine_write_cmd_reg(desc_extra, cmd);
+		} else if(modifier == 0x01) {
+			spi_gen_sleep_ns(desc, parameter);
+		}
+		break;
+	case SPI_ENGINE_INST_CONFIG:
+		spi_engine_write_cmd_reg(desc_extra, cmd);
+
+		break;
+
+	default:
+
+		return FAILURE;
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Prepare the command queue before sending it to the engine
+ *
+ * @param desc Decriptor containing SPI interface parameters
+ * @param msg Structure used to store the transfer messages
+ * @return int32_t This function allways returns SUCCESS
+ */
+static int32_t spi_engine_compile_message(struct spi_desc *desc,
+		struct spi_engine_msg *msg)
+{
+	struct spi_engine_desc	*desc_extra;
+
+	desc_extra = desc->extra;
+
+	/* Configure the prescaler */
+	spi_engine_queue_append_cmd(&msg->cmds,
+				    SPI_ENGINE_CMD_CONFIG(
+					    SPI_ENGINE_CMD_REG_CLK_DIV,
+					    desc_extra->clk_div));
+
+	/* Set the data transfer length */
+	spi_engine_queue_append_cmd(&msg->cmds,
+				    SPI_ENGINE_CMD_CONFIG(
+					    SPI_ENGINE_CMD_DATA_TRANSFER_LEN,
+					    desc_extra->data_width));
+	/*
+	 * Configure the spi mode :
+	 *	- 3 wire
+	 *	- CPOL
+	 *	- CPHA
+	 */
+	spi_engine_queue_append_cmd(&msg->cmds,
+				    SPI_ENGINE_CMD_CONFIG(
+					    SPI_ENGINE_CMD_REG_CONFIG,
+					    desc->mode));
+
+	/* Add a sync command to signal that the transfer has finished */
+	spi_engine_queue_add_cmd(&msg->cmds, SPI_ENGINE_CMD_SYNC(_sync_id));
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Initiate a spi transfer (Blocking)
+ *
+ * @param desc Decriptor containing SPI interface parameters
+ * @param msg Structure used to store the transfer messages
+ * @return int32_t - SUCCESS if the transfer finished
+ *		   - FAILURE if the memory allocation failed
+ */
+static int32_t spi_engine_transfer_message(struct spi_desc *desc,
+		struct spi_engine_msg *msg)
+{
+	uint32_t		i;
+	uint32_t		data;
+	uint32_t		sync_id;
+	bool 			offload_en;
+	struct spi_engine_desc	*desc_extra;
+
+	desc_extra = desc->extra;
+
+	spi_engine_compile_message(desc, msg);
+
+	offload_en = (desc_extra->offload_config & OFFLOAD_TX_EN) |
+		     (desc_extra->offload_config & OFFLOAD_RX_EN);
+
+	/* Write the command fifo buffer */
+	while(msg->cmds != NULL) {
+		spi_engine_queue_get_cmd(&msg->cmds, &data);
+		spi_engine_write_cmd(desc, data);
+	}
+
+	/* Write a number of tx_length WORDS on the SDO line */
+	if(offload_en) {
+		for(i = 0; i < desc_extra->offload_tx_len; i++)
+			spi_engine_write(desc_extra,
+					 SPI_ENGINE_REG_OFFLOAD_SDO_MEM(0),
+					 msg->tx_buf[i]);
+
+	} else {
+		if(msg->tx_buf != NULL){
+			for(i = 0; i < msg->tx_length; i++)
+			spi_engine_write(desc_extra,
+					 SPI_ENGINE_REG_SDO_DATA_FIFO,
+					 msg->tx_buf[i]);
+		}
+		do {
+			spi_engine_read(desc_extra,
+					SPI_ENGINE_REG_SYNC_ID,
+					&sync_id);
+		}
+		/* Wait for the end sync signal */
+		while(sync_id != _sync_id);
+		_sync_id++;
+
+		/* Read a number of rx_length WORDS from the SDI line and store
+		them */
+		for(i = 0; i < msg->rx_length; i++) {
+			spi_engine_read(desc_extra,
+					SPI_ENGINE_REG_SDI_DATA_FIFO,
+					&data);
+			/* Store the rx data if rx buffer valid, flush sdi_fifo if
+			rx buffer is invalid.*/
+			if(msg->rx_buf != NULL){
+				msg->rx_buf[i] = data;
+			}
+		}
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Initialize the spi engine
+ *
+ * @param desc Decriptor containing SPI interface parameters
+ * @param param Structure containing the spi init parameters
+ * @return int32_t - SUCCESS if the transfer finished
+ *		   - FAILURE if the memory allocation failed
+ */
+int32_t spi_engine_init(struct spi_desc **desc,
+			const struct spi_init_param *param)
+{
+	uint32_t			data_width = 0;
+	uint32_t			spi_engine_version = 0;
+	struct spi_engine_desc		*eng_desc;
+	struct spi_engine_init_param	*spi_engine_init;
+
+	if (!param) {
+		return FAILURE;
+	}
+
+	*desc = malloc(sizeof(**desc));
+	if(! *desc) {
+		free(*desc);
+		return FAILURE;
+	}
+
+	eng_desc = (struct spi_engine_desc*)malloc(sizeof(*eng_desc));
+
+	if (!eng_desc)
+		return FAILURE;
+
+	spi_engine_init = param->extra;
+
+	(*desc)->max_speed_hz = param->max_speed_hz;
+	(*desc)->chip_select = param->chip_select;
+	(*desc)->mode = param->mode;
+	(*desc)->extra = eng_desc;
+
+	eng_desc->offload_config = OFFLOAD_DISABLED;
+	eng_desc->spi_engine_baseaddr = spi_engine_init->spi_engine_baseaddr;
+	eng_desc->type = spi_engine_init->type;
+	eng_desc->cs_delay = spi_engine_init->cs_delay;
+	eng_desc->ref_clk_hz = spi_engine_init->ref_clk_hz;
+	eng_desc->clk_div =  eng_desc->ref_clk_hz /
+			     (2 * param->max_speed_hz) - 1;
+
+	/* Perform a reset */
+	spi_engine_write(eng_desc, SPI_ENGINE_REG_RESET, 0x01);
+	usleep(1000);
+	spi_engine_write(eng_desc, SPI_ENGINE_REG_RESET, 0x00);
+
+	/* Get current data width */
+	spi_engine_read(eng_desc, SPI_ENGINE_REG_DATA_WIDTH, &data_width);
+	eng_desc->max_data_width = data_width;
+
+	spi_engine_set_transfer_width(*desc, spi_engine_init->data_width);
+
+	/* Get spi engine version */
+	spi_engine_read(eng_desc, SPI_ENGINE_REG_VERSION, &spi_engine_version);
+
+	printf("Spi engine v%"PRIu32".%"PRIu32".%"PRIu32" successfully initialized.\n",
+	       (spi_engine_version >> 16),
+	       ((spi_engine_version >> 8) & 0xFF),
+	       (spi_engine_version & 0xFF));
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Write and read on the spi interface in 4-wire mode (full-duplex)
+ *
+ * @param desc Decriptor containing SPI interface parameters
+ * @param data Pointer to data buffer
+ * @param bytes_number Number of bytes to transfer
+ * @return int32_t - SUCCESS if the transfer finished
+ *		   - FAILURE if the memory allocation or transfer failed
+ */
+int32_t spi_engine_spi_write_and_read(struct spi_desc *desc,
+				  uint8_t *data,
+				  uint16_t bytes_number)
+{
+	uint8_t 		word_len;
+	uint8_t 		words_number;
+	int32_t 		ret;
+	struct spi_engine_msg	msg;
+	struct spi_engine_desc	*desc_extra;
+
+	desc_extra = desc->extra;
+
+	/* If we want to access SPI interface and SPI engine offload module was
+	 * activated, we need to disable it
+	 * This is set in spi_engine_offload_init() */
+	desc_extra->offload_config = OFFLOAD_DISABLED;
+	/* This is set in spi_engine_offload_transfer() */
+	spi_engine_write(desc_extra, SPI_ENGINE_REG_OFFLOAD_CTRL(0), 0);
+
+	words_number = spi_get_words_number(desc_extra, bytes_number);
+
+	msg.cmds = (spi_engine_cmd_queue*)malloc(sizeof(*msg.cmds));
+	if (!msg.cmds)
+		return FAILURE;
+
+	msg.tx_buf =(uint32_t*)calloc(words_number, sizeof(msg.tx_buf[0]));
+	msg.rx_buf =(uint32_t*)calloc(words_number, sizeof(msg.rx_buf[0]));
+	msg.tx_length = words_number;
+	msg.rx_length = words_number;
+
+	/* Get the length of transferred word */
+	word_len = spi_get_word_length(desc_extra);
+
+	/* Make sure the CS is HIGH before starting a transaction */
+	msg.cmds->next = NULL;
+	msg.cmds->cmd = CS_HIGH;
+	// Assert select.
+	spi_engine_queue_add_cmd(&msg.cmds, CS_LOW);
+	// add read/write command
+	spi_engine_queue_add_cmd(&msg.cmds, WRITE_READ(bytes_number));
+	// Disable select.
+	spi_engine_queue_add_cmd(&msg.cmds, CS_HIGH);
+
+	/* Pack the bytes into engine WORDS */
+	for (int i = 0; i < bytes_number; i++)
+		msg.tx_buf[i / word_len] |= data[i] << (desc_extra->data_width-
+							(i % word_len + 1) * 8);
+
+	ret = spi_engine_transfer_message(desc, &msg);
+
+	for (int i = 0; i < bytes_number; i++)
+	data[i] = msg.rx_buf[(i) / word_len] >>
+		  (desc_extra->data_width -
+		   ((i) % word_len + 1) * 8);
+	
+	spi_engine_queue_free(&msg.cmds);
+	free(msg.tx_buf);
+	free(msg.rx_buf);
+
+	return ret;
+}
+
+/**
+ * @brief Write and read on the spi interface in 3-wire mode (half-duplex)
+ *
+ * @param desc Decriptor containing SPI interface parameters
+ * @param data Pointer to data buffer
+ * @param bytes_number Number of bytes to transfer
+ * @return int32_t - SUCCESS if the transfer finished
+ *		   - FAILURE if the memory allocation or transfer failed
+ */
+int32_t spi_engine_spi_write_and_read_3wire(struct spi_desc *desc,
+		   uint8_t *write_data,
+		   uint8_t *read_data,
+		   uint16_t write_bytes_number,
+		   uint16_t read_bytes_number)
+{
+	uint8_t 		word_len;
+	uint8_t 		wr_words_number;
+	uint8_t 		rd_words_number;
+	int32_t 		ret;
+	struct spi_engine_msg	msg;
+	struct spi_engine_desc	*desc_extra;
+
+	desc_extra = desc->extra;
+
+	/* If we want to access SPI interface and SPI engine offload module was
+	 * activated, we need to disable it
+	 * This is set in spi_engine_offload_init() */
+	desc_extra->offload_config = OFFLOAD_DISABLED;
+	/* This is set in spi_engine_offload_transfer() */
+	spi_engine_write(desc_extra, SPI_ENGINE_REG_OFFLOAD_CTRL(0), 0);
+
+	wr_words_number = spi_get_words_number(desc_extra, write_bytes_number);
+	rd_words_number = spi_get_words_number(desc_extra, read_bytes_number);
+
+	msg.cmds = (spi_engine_cmd_queue*)malloc(sizeof(*msg.cmds));
+	if (!msg.cmds)
+		return FAILURE;
+
+	msg.tx_buf =(wr_words_number>0)?(uint32_t*)calloc(wr_words_number, sizeof(msg.tx_buf[0])):NULL;
+	msg.rx_buf =(rd_words_number>0)?(uint32_t*)calloc(rd_words_number, sizeof(msg.rx_buf[0])):NULL;
+	msg.tx_length = wr_words_number;
+	msg.rx_length = rd_words_number;
+
+	/* Get the length of transferred word */
+	word_len = spi_get_word_length(desc_extra);
+
+	/* Make sure the CS is HIGH before starting a transaction */
+	msg.cmds->next = NULL;
+	msg.cmds->cmd = CS_HIGH;
+
+	// Assert select.
+	spi_engine_queue_add_cmd(&msg.cmds, CS_LOW);
+
+	// add read/write command
+	if(write_bytes_number > 0)
+	spi_engine_queue_add_cmd(&msg.cmds, WRITE(write_bytes_number));
+	if(read_bytes_number > 0)
+	spi_engine_queue_add_cmd(&msg.cmds, READ(read_bytes_number));
+
+	// Disable select.
+	spi_engine_queue_add_cmd(&msg.cmds, CS_HIGH);
+
+	/* Pack the bytes into engine WORDS */
+	for (int i = 0; i < write_bytes_number; i++)
+		msg.tx_buf[i / word_len] |= write_data[i] << (desc_extra->data_width-
+							(i % word_len + 1) * 8);
+
+	ret = spi_engine_transfer_message(desc, &msg);
+
+	for (int i = 0; i < read_bytes_number; i++)
+		read_data[i] = msg.rx_buf[(i) / word_len] >>
+		  (desc_extra->data_width -
+		   ((i) % word_len + 1) * 8);
+
+	spi_engine_queue_free(&msg.cmds);
+	free(msg.tx_buf);
+	free(msg.rx_buf);
+
+	return ret;
+}
+
+/**
+ * @brief Initialize the SPI engine's offload module
+ *
+ * @param desc Decriptor containing SPI interface parameters
+ * @param param Structure containing the offload init parameters
+ * @return int32_t This function allways returns SUCCESS
+ */
+int32_t spi_engine_offload_init(struct spi_desc *desc,
+				const struct spi_engine_offload_init_param *param)
+{
+	struct spi_engine_desc	*eng_desc;
+	struct axi_dmac_init	dmac_init;
+	uint32_t dma_flags;
+
+	eng_desc = desc->extra;
+
+	eng_desc->offload_config = param->offload_config;
+
+	if(!(param->dma_flags))
+		dma_flags = DMA_CYCLIC;
+	else
+		dma_flags = *(param->dma_flags);
+
+	if(param->offload_config & OFFLOAD_TX_EN) {
+		dmac_init.name = "DAC DMAC";
+		dmac_init.base = param->tx_dma_baseaddr;
+		dmac_init.direction = DMA_MEM_TO_DEV;
+		dmac_init.flags = dma_flags;
+		axi_dmac_init(&eng_desc->offload_tx_dma, &dmac_init);
+		if(!eng_desc->offload_tx_dma)
+			return FAILURE;
+	}
+	if(param->offload_config & OFFLOAD_RX_EN) {
+		dmac_init.name = "ADC DMAC";
+		dmac_init.base = param->rx_dma_baseaddr;
+		dmac_init.direction = DMA_DEV_TO_MEM;
+		dmac_init.flags = dma_flags;
+		axi_dmac_init(&eng_desc->offload_rx_dma, &dmac_init);
+		if(!eng_desc->offload_rx_dma)
+			return FAILURE;
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Initiate a SPI transfer in offload mode
+ *
+ * @param desc Decriptor containing SPI interface parameters
+ * @param msg Offload message that get's to be transferred
+ * @param no_samples Number of time the messages will be transferred
+ * @return int32_t This function allways returns SUCCESS
+ */
+int32_t spi_engine_offload_transfer(struct spi_desc *desc,
+				    struct spi_engine_offload_message msg,
+				    uint32_t no_samples)
+{
+	struct spi_engine_msg	transfer;
+	struct spi_engine_desc	*eng_desc;
+	uint32_t 		i;
+	uint8_t 		word_length;
+
+	eng_desc = desc->extra;
+
+	/* Check if offload is disabled */
+	if(!((eng_desc->offload_config & OFFLOAD_TX_EN) |
+	     (eng_desc->offload_config & OFFLOAD_RX_EN)))
+		return FAILURE;
+
+	spi_engine_write(eng_desc, SPI_ENGINE_REG_OFFLOAD_RESET(0), 1);
+	spi_engine_write(eng_desc, SPI_ENGINE_REG_OFFLOAD_RESET(0), 0);
+
+	eng_desc->offload_tx_len = 0;
+	eng_desc->offload_rx_len = 0;
+
+	transfer.cmds = (spi_engine_cmd_queue*)malloc(sizeof(*transfer.cmds));
+
+	if (!transfer.cmds)
+		return FAILURE;
+
+	transfer.tx_buf = msg.commands_data;
+
+	/* Load the commands into the message */
+	transfer.cmds->next = NULL;
+	transfer.cmds->cmd = msg.commands[0];
+	i = 1;
+	while(i < msg.no_commands) {
+		spi_engine_queue_add_cmd(&transfer.cmds, msg.commands[i++]);
+
+	}
+
+	spi_engine_transfer_message(desc, &transfer);
+
+	/* Start transfer */
+	spi_engine_write(eng_desc, SPI_ENGINE_REG_OFFLOAD_CTRL(0), 0x0001);
+
+	word_length = spi_get_word_length(eng_desc);
+	if(eng_desc->offload_config & OFFLOAD_TX_EN) {
+		axi_dmac_transfer(eng_desc->offload_tx_dma,
+				  msg.tx_addr,
+				  word_length * eng_desc->offload_tx_len *
+				  no_samples);
+	}
+
+	if(eng_desc->offload_config & OFFLOAD_RX_EN) {
+		axi_dmac_transfer(eng_desc->offload_rx_dma,
+				  msg.rx_addr,
+				  word_length * eng_desc->offload_tx_len *
+				  no_samples);
+	}
+
+	usleep(1000);
+
+	spi_engine_queue_free(&transfer.cmds);
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Free the resources allocated by spi_init().
+ *
+ * @param desc Decriptor containing SPI interface parameters
+ * @return int32_t This function allways returns SUCCESS
+ */
+int32_t spi_engine_remove(struct spi_desc *desc)
+{
+	struct spi_engine_desc	*eng_desc;
+
+	eng_desc = desc->extra;
+
+	if(eng_desc->offload_config & OFFLOAD_TX_EN)
+		axi_dmac_remove(eng_desc->offload_tx_dma);
+	if(eng_desc->offload_config & OFFLOAD_RX_EN)
+		axi_dmac_remove(eng_desc->offload_rx_dma);
+	free(desc->extra);
+	free(desc);
+
+	return SUCCESS;
+}

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/src/adi_noos/drivers/axi_core/spi_engine/spi_engine.h

@@ -0,0 +1,231 @@
+/*******************************************************************************
+ *   @file   spi_engine.h
+ *   @brief  Header file of SPI Engine core features.
+ *   @author Sergiu Cuciurean ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#ifndef SPI_ENGINE_H
+#define SPI_ENGINE_H
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <stdint.h>
+
+#include "spi_engine_private.h"
+#include "../../platform/spi_extra.h"
+
+/******************************************************************************/
+/********************** Macros and Constants Definitions **********************/
+/******************************************************************************/
+
+#define OFFLOAD_DISABLED		0x00
+#define OFFLOAD_TX_EN			BIT(0)
+#define OFFLOAD_RX_EN			BIT(1)
+#define OFFLOAD_TX_RX_EN		OFFLOAD_TX_EN | OFFLOAD_RX_EN
+
+#define SPI_ENGINE_MSG_QUEUE_END	0xFFFFFFFF
+
+/* Spi engine commands */
+#define	WRITE_OR_READ(mode, no_bytes)	((SPI_ENGINE_INST_TRANSFER << 12) |\
+((mode) << 8) | (no_bytes))
+
+#define	WRITE(no_bytes)			((SPI_ENGINE_INST_TRANSFER << 12) |\
+	(SPI_ENGINE_INSTRUCTION_TRANSFER_W << 8) | (no_bytes))
+
+#define	READ(no_bytes)			((SPI_ENGINE_INST_TRANSFER << 12) |\
+	(SPI_ENGINE_INSTRUCTION_TRANSFER_R << 8) | (no_bytes))
+
+#define	WRITE_READ(no_bytes)		((SPI_ENGINE_INST_TRANSFER << 12) |\
+	(SPI_ENGINE_INSTRUCTION_TRANSFER_RW << 8) | (no_bytes))
+
+
+
+#define SLEEP(time)			SPI_ENGINE_CMD_SLEEP(time & 0xF)
+
+/* The delay and chip select parmeters are passed over the engine descriptor
+and will be used inside the function call */
+#define CS_HIGH			SPI_ENGINE_CMD_ASSERT(0x00, 0xFF)
+#define CS_LOW			SPI_ENGINE_CMD_ASSERT(0x00, 0x00)
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+
+/**
+ * @struct spi_engine_init_param
+ * @brief  Structure containing the init parameters needed by the SPI engine
+ */
+struct spi_engine_init_param {
+	/** SPI engine reference clock */
+	uint32_t	ref_clk_hz;
+	/** Type of implementation */
+	enum xil_spi_type	type;
+	/** Base address where the HDL core is situated */
+	uint32_t 		spi_engine_baseaddr;
+	/** Delay between the CS toggle and the start of SCLK */
+	uint32_t		cs_delay;
+	/** Data with of one SPI transfer ( in bits ) */
+	uint8_t			data_width;
+};
+
+
+/**
+ * @struct spi_engine_desc
+ * @brief  Structure representing an SPI engine device
+ */
+struct spi_engine_desc {
+	/** SPI engine reference clock */
+	uint32_t	ref_clk_hz;
+	/** Type of implementation */
+	enum xil_spi_type	type;
+	/** Pointer to a DMAC used in transmission */
+	struct axi_dmac		*offload_tx_dma;
+	/** Pointer to a DMAC used in reception */
+	struct axi_dmac		*offload_rx_dma;
+	/** Offload's module transfer direction : TX, RX or both */
+	uint8_t			offload_config;
+	/** Number of words that the module has to send */
+	uint8_t			offload_tx_len;
+	/** Number of words that the module has to receive */
+	uint8_t			offload_rx_len;
+	/** Base address where the HDL core is situated */
+	uint32_t		spi_engine_baseaddr;
+	/** Base address where the RX DMAC core is situated */
+	uint32_t		rx_dma_baseaddr;
+	/** Base address where the TX DMAC core is situated */
+	uint32_t		tx_dma_baseaddr;
+	/** Delay between the CS toggle and the start of SCLK */
+	uint8_t			cs_delay;
+	/** Clock divider used in transmission delays */
+	uint32_t		clk_div;
+	/** Data with of one SPI transfer ( in bits ) */
+	uint8_t			data_width;
+	/** The maximum data width supported by the engine */
+	uint8_t 		max_data_width;
+};
+
+
+/**
+ * @struct spi_engine_offload_init_param
+ * @brief  Structure containing the init parameters needed by the offload module
+ */
+struct spi_engine_offload_init_param {
+	/** Base address where the RX DMAC core is situated */
+	uint32_t	rx_dma_baseaddr;
+	/** Base address where the TX DMAC core is situated */
+	uint32_t	tx_dma_baseaddr;
+	/** DMAC flags - if not initialized, the default value is DMA_CYCLIC */
+	uint32_t	*dma_flags;
+	/** Offload's module transfer direction : TX, RX or both */
+	uint8_t		offload_config;
+};
+
+/**
+ * @struct spi_engine_offload_message
+ * @brief  Structure representing an offload message
+ */
+struct spi_engine_offload_message {
+	/** Pointer to the SPI engine commands buffer that will be sent.
+	 * The available commands can be found at:
+	 * https://wiki.analog.com/resources/fpga/peripherals/spi_engine/
+	*/
+	uint32_t *commands;
+	/** Length of the SPI engine commands buffer */
+	uint32_t no_commands;
+	/** Pointer of the data that will be sent over spi */
+	uint32_t *commands_data;
+	/** The address where the data that will be transmitted is situated */
+	uint32_t tx_addr;
+	/** The address where the data that will be received is situated */
+	uint32_t rx_addr;
+};
+
+/******************************************************************************/
+/************************ Functions Declarations ******************************/
+/******************************************************************************/
+
+/**
+ * @brief Spi engine platform specific SPI platform ops structure
+ */
+extern const struct spi_platform_ops xil_spi_ops;
+
+/* Write SPI Engine's axi registers */
+int32_t spi_engine_write(struct spi_engine_desc *desc,
+			 uint32_t reg_addr,
+			 uint32_t reg_data);
+
+/* Read SPI Engine's axi registers */
+int32_t spi_engine_read(struct spi_engine_desc *desc,
+			uint32_t reg_addr,
+			uint32_t *reg_data);
+/* Initialize the SPI engine device */
+int32_t spi_engine_init(struct spi_desc **desc,
+			const struct spi_init_param *param);
+
+/* Write and read data over SPI using the SPI engine */
+int32_t spi_engine_spi_write_and_read(struct spi_desc *desc,
+				  uint8_t *data,
+				  uint16_t bytes_number);
+
+/* Write and read data over SPI using the SPI engine in 3-wire mode */
+int32_t spi_engine_spi_write_and_read_3wire(struct spi_desc *desc,
+		   uint8_t *write_data,
+		   uint8_t *read_data,
+		   uint16_t write_bytes_number,
+		   uint16_t read_bytes_number);
+/* Free the resources used by the SPI engine device */
+int32_t spi_engine_remove(struct spi_desc *desc);
+
+/* Initialize the SPI engine offload module */
+int32_t spi_engine_offload_init(struct spi_desc *desc,
+				const struct spi_engine_offload_init_param *param);
+
+/* Write and read data over SPI using the offload module */
+int32_t spi_engine_offload_transfer(struct spi_desc *desc,
+				    struct spi_engine_offload_message msg,
+				    uint32_t no_samples);
+
+/* Set SPI transfer width */
+int32_t spi_engine_set_transfer_width(struct spi_desc *desc,
+				      uint8_t data_wdith);
+
+/* Set SPI transfer speed */
+void spi_engine_set_speed(struct spi_desc *desc,
+			  uint32_t speed_hz);
+
+#endif // SPI_ENGINE_H

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/src/adi_noos/drivers/axi_core/spi_engine/spi_engine_private.h

@@ -0,0 +1,154 @@
+/*******************************************************************************
+ *   @file   spi_engine_private.h
+ *   @brief  Private definitions of the SPI Engine
+ *   @author Sergiu Cuciurean ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#ifndef SPI_ENGINE_PRIVATE_H
+#define SPI_ENGINE_PRIVATE_H
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "../../../include/spi.h"
+#include "../../../include/util.h"
+
+/******************************************************************************/
+/*************************** Spi Engine registers *****************************/
+/******************************************************************************/
+
+#define SPI_ENGINE_REG_VERSION			0x00
+#define SPI_ENGINE_REG_DATA_WIDTH		0x0C
+#define SPI_ENGINE_REG_RESET			0x40
+#define SPI_ENGINE_REG_INT_ENABLE		0x80
+#define SPI_ENGINE_REG_INT_PENDING		0x84
+#define SPI_ENGINE_REG_INT_SOURCE		0x88
+#define SPI_ENGINE_REG_SYNC_ID			0xC0
+#define SPI_ENGINE_REG_CMD_FIFO_ROOM		0xD0
+#define SPI_ENGINE_REG_SDO_FIFO_ROOM		0xD4
+#define SPI_ENGINE_REG_SDI_FIFO_LEVEL		0xD8
+#define SPI_ENGINE_REG_CMD_FIFO 		0xE0
+#define SPI_ENGINE_REG_SDO_DATA_FIFO		0xE4
+#define SPI_ENGINE_REG_SDI_DATA_FIFO		0xE8
+#define SPI_ENGINE_REG_SDI_DATA_FIFO_PEEK	0xEC
+
+/******************************************************************************/
+/************************ Spi Engine register parameters **********************/
+/******************************************************************************/
+
+#define SPI_ENGINE_INST_TRANSFER		0x00
+#define SPI_ENGINE_INST_ASSERT			0x01
+#define SPI_ENGINE_INST_CONFIG			0x02
+#define SPI_ENGINE_INST_SYNC_SLEEP		0x03
+#define SPI_ENGINE_INST_MISC			0x03
+#define SPI_ENGINE_CMD_REG_CLK_DIV		0x00
+#define SPI_ENGINE_CMD_REG_CONFIG		0x01
+#define SPI_ENGINE_CMD_DATA_TRANSFER_LEN	0x02
+#define SPI_ENGINE_MISC_SYNC			0x00
+#define SPI_ENGINE_MISC_SLEEP			0x01
+#define SPI_ENGINE_SYNC_TRANSFER_BEGIN		BIT(1)
+#define SPI_ENGINE_SYNC_TRANSFER_END		BIT(2)
+#define SPI_ENGINE_INT_CMD_ALMOST_EMPTY		BIT(0)
+#define SPI_ENGINE_INT_SDO_ALMOST_EMPTY		BIT(1)
+#define SPI_ENGINE_INT_SDI_ALMOST_FULL		BIT(2)
+#define SPI_ENGINE_INT_SYNC			BIT(3)
+#define SPI_ENGINE_OFFLOAD_CTRL_ENABLE		BIT(0)
+#define SPI_ENGINE_OFFLOAD_STATUS_ENABLED	BIT(0)
+#define SPI_ENGINE_CONFIG_CPHA			BIT(0)
+#define SPI_ENGINE_CONFIG_CPOL			BIT(1)
+#define SPI_ENGINE_CONFIG_3WIRE			BIT(2)
+#define SPI_ENGINE_VERSION_MAJOR(x) 		((x >> 16) & 0xff)
+#define SPI_ENGINE_VERSION_MINOR(x) 		((x >> 8) & 0xff)
+#define SPI_ENGINE_VERSION_PATCH(x) 		(x & 0xff)
+
+/******************************************************************************/
+/**************************** Spi Engine commands *****************************/
+/******************************************************************************/
+
+#define SPI_ENGINE_INSTRUCTION_TRANSFER_W	0x01
+#define SPI_ENGINE_INSTRUCTION_TRANSFER_R	0x02
+#define SPI_ENGINE_INSTRUCTION_TRANSFER_RW	0x03
+
+#define SPI_ENGINE_REG_OFFLOAD_CTRL(x)		(0x100 + (0x20 * x))
+#define SPI_ENGINE_REG_OFFLOAD_STATUS(x)	(0x104 + (0x20 * x))
+#define SPI_ENGINE_REG_OFFLOAD_RESET(x)		(0x108 + (0x20 * x))
+#define SPI_ENGINE_REG_OFFLOAD_CMD_MEM(x)	(0x110 + (0x20 * x))
+#define SPI_ENGINE_REG_OFFLOAD_SDO_MEM(x)	(0x114 + (0x20 * x))
+
+#define SPI_ENGINE_CMD(inst, arg1, arg2) 				\
+			(((inst & 0x03) << 12) | 			\
+			((arg1 & 0x03) << 8) | arg2 )
+
+#define SPI_ENGINE_CMD_TRANSFER(readwrite, n)				\
+	SPI_ENGINE_CMD(SPI_ENGINE_INST_TRANSFER,			\
+			(readwrite), (n))
+
+#define SPI_ENGINE_CMD_ASSERT(delay, cs) 				\
+	SPI_ENGINE_CMD(SPI_ENGINE_INST_ASSERT,				\
+			(delay), (cs))
+
+#define SPI_ENGINE_CMD_CONFIG(reg, val)					\
+	SPI_ENGINE_CMD(SPI_ENGINE_INST_CONFIG,				\
+			(reg), (val))
+
+#define SPI_ENGINE_CMD_SLEEP(delay) 					\
+	SPI_ENGINE_CMD(SPI_ENGINE_INST_MISC, 				\
+			SPI_ENGINE_MISC_SLEEP, 				\
+			(delay))
+
+#define SPI_ENGINE_CMD_SYNC(id) 					\
+	SPI_ENGINE_CMD(SPI_ENGINE_INST_MISC, 				\
+			SPI_ENGINE_MISC_SYNC, 				\
+			(id))
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+
+typedef struct spi_engine_cmd_queue {
+	uint32_t	cmd;
+	struct		spi_engine_cmd_queue *next;
+} spi_engine_cmd_queue;
+
+typedef struct spi_engine_msg {
+	uint32_t			*tx_buf;
+	uint32_t			*rx_buf;
+	uint32_t			tx_length;
+	uint32_t			rx_length;
+	struct spi_engine_cmd_queue	*cmds;
+} spi_engine_msg;
+
+#endif // SPI_ENGINE_PRIVATE_H

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/src/adi_noos/drivers/frequency/ad9516/ad9516.c

@@ -0,0 +1,129 @@
+/***************************************************************************//**
+ * @file ad9516.c
+ * @brief Implementation of AD9680 Driver.
+ * @author DBogdan ([email protected])
+ ********************************************************************************
+ * Copyright 2014-2016(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * - Neither the name of Analog Devices, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * - The use of this software may or may not infringe the patent rights
+ * of one or more patent holders. This license does not release you
+ * from the requirement that you obtain separate licenses from these
+ * patent holders to use this software.
+ * - Use of the software either in source or binary form, must be run
+ * on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************/
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+#include "ad9516.h"
+
+#include <stdlib.h>
+#include <stdio.h>
+#include "../../../include/error.h"
+
+/***************************************************************************//**
+ * @brief ad9516_read
+ *******************************************************************************/
+int32_t ad9516_read(struct ad9516_dev *dev,
+			uint16_t reg_addr,
+			uint8_t *reg_data)
+{
+	uint8_t tx_buf[2];
+	uint8_t rx_buf[1];
+	int32_t ret;
+
+	tx_buf[0] = 0x80 | (reg_addr >> 8);
+	tx_buf[1] = reg_addr & 0xFF;
+
+
+	ret = spi_write_and_read_3wire(dev->spi_desc,
+			tx_buf, rx_buf, 2, 1);
+
+	*reg_data = rx_buf[0];
+
+	return ret;
+}
+
+/***************************************************************************//**
+ * @brief ad9516_write
+ *******************************************************************************/
+int32_t ad9516_write(struct ad9516_dev *dev,
+			 uint16_t reg_addr,
+			 uint8_t reg_data)
+{
+	uint8_t buf[3];
+
+	int32_t ret;
+
+	buf[0] = reg_addr >> 8;
+	buf[1] = reg_addr & 0xFF;
+	buf[2] = reg_data;
+
+	ret = spi_write_and_read_3wire(dev->spi_desc,
+				 buf, NULL, 3, 0);
+	return ret;
+}
+
+/***************************************************************************//**
+ * @brief ad9516_init
+ *******************************************************************************/
+int32_t ad9516_init(struct ad9516_dev **device,
+		     const struct ad9516_init_param *init_param)
+{
+	int ret = SUCCESS;
+	struct ad9516_dev *dev;
+
+	dev = (struct ad9516_dev *)malloc(sizeof(*dev));
+	if (!dev)
+		return FAILURE;
+
+	/* SPI */
+	ret = spi_init(&dev->spi_desc, init_param->spi_init);
+
+	*device = dev;
+
+	return ret;
+}
+
+/***************************************************************************//**
+ * @brief Free the resources allocated by ad9516_setup().
+ *
+ * @param dev - The device structure.
+ *
+ * @return SUCCESS in case of success, negative error code otherwise.
+*******************************************************************************/
+int32_t ad9516_remove(struct ad9516_dev *dev)
+{
+	int32_t ret;
+
+	ret = spi_remove(dev->spi_desc);
+
+	free(dev);
+
+	return ret;
+}

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/src/adi_noos/drivers/frequency/ad9516/ad9516.h

@@ -0,0 +1,89 @@
+/***************************************************************************//**
+ * @file ad9516.h
+ * @brief Header file of ad9516 Driver.
+ * @author DBogdan ([email protected])
+ ********************************************************************************
+ * Copyright 2014-2016(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * - Neither the name of Analog Devices, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * - The use of this software may or may not infringe the patent rights
+ * of one or more patent holders. This license does not release you
+ * from the requirement that you obtain separate licenses from these
+ * patent holders to use this software.
+ * - Use of the software either in source or binary form, must be run
+ * on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************/
+#ifndef AD9516_H_
+#define AD9516_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+#include <stdint.h>
+#include "../../../include/delay.h"
+#include "../../../include/spi.h"
+
+/******************************************************************************/
+/********************** Macros and Constants Definitions **********************/
+/******************************************************************************/
+
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+struct ad9516_dev {
+	/* SPI */
+	spi_desc	*spi_desc;
+};
+
+struct ad9516_init_param {
+	/* SPI */
+	spi_init_param	*spi_init;
+};
+
+struct ad9516_config {
+	uint16_t addr;
+	uint8_t value;
+};
+
+/******************************************************************************/
+/************************ Functions Declarations ******************************/
+/******************************************************************************/
+
+int32_t ad9516_read(struct ad9516_dev *dev,
+			uint16_t reg_addr,
+			uint8_t *reg_data);
+
+int32_t ad9516_write(struct ad9516_dev *dev,
+			 uint16_t reg_addr,
+			 uint8_t reg_data);
+
+int32_t ad9516_init(struct ad9516_dev **device,
+		     const struct ad9516_init_param *init_param);
+
+int32_t ad9516_remove(struct ad9516_dev *dev);
+
+#endif

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/src/adi_noos/drivers/platform/axi_io.c

@@ -0,0 +1,79 @@
+/***************************************************************************//**
+ *   @file   xilinx/axi_io.c
+ *   @brief  Implementation of Xilinx AXI IO.
+ *   @author Antoniu Miclaus ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <xil_io.h>
+#include "../../include/error.h"
+#include "../../include/axi_io.h"
+
+/******************************************************************************/
+/************************ Functions Definitions *******************************/
+/******************************************************************************/
+
+/**
+ * @brief AXI IO Xilinx specific read function.
+ * @param base - Base address
+ * @param offset - Address offset
+ * @param data - variable where returned data is stored
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t axi_io_read(uint32_t base, uint32_t offset, uint32_t *data)
+{
+	*data = Xil_In32(base + offset);
+
+	return SUCCESS;
+}
+
+/**
+ * @brief AXI IO Xilinx specific write function.
+ * @param base - Base address
+ * @param offset - Address offset
+ * @param data - data to be written.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t axi_io_write(uint32_t base, uint32_t offset, uint32_t data)
+{
+	Xil_Out32(base + offset, data);
+
+	return SUCCESS;
+}
+

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/src/adi_noos/drivers/platform/delay.c

@@ -0,0 +1,77 @@
+/***************************************************************************//**
+ *   @file   xilinx/delay.c
+ *   @brief  Implementation of Xilinx Delay Functions.
+ *   @author Antoniu Miclaus ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include "../../include/delay.h"
+#include <sleep.h>
+
+/******************************************************************************/
+/************************ Functions Definitions *******************************/
+/******************************************************************************/
+
+/**
+ * @brief Generate microseconds delay.
+ * @param usecs - Delay in microseconds.
+ * @return None.
+ */
+void udelay(uint32_t usecs)
+{
+#ifdef _XPARAMETERS_PS_H_
+	usleep(usecs);
+#else
+	usleep(usecs / 20);	// FIXME
+#endif
+}
+
+/**
+ * @brief Generate miliseconds delay.
+ * @param msecs - Delay in miliseconds.
+ * @return None.
+ */
+void mdelay(uint32_t msecs)
+{
+#ifdef _XPARAMETERS_PS_H_
+	usleep(msecs * 1000);
+#else
+	usleep(msecs * 50);	// FIXME
+#endif
+}

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/src/adi_noos/drivers/platform/gpio_extra.h

@@ -0,0 +1,95 @@
+/*******************************************************************************
+ *   @file   xilinx/gpio_extra.h
+ *   @brief  Header containing extra types used in the gpio driver
+ *   @author scuciurean ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#ifndef GPIO_EXTRA_H_
+#define GPIO_EXTRA_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <stdint.h>
+#include <stdbool.h>
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+
+/**
+ * @enum xil_gpio_type
+ * @brief Xilinx platform architecture sections
+ */
+typedef enum xil_gpio_type {
+	/** Programmable Logic */
+	GPIO_PL,
+	/** Processing System */
+	GPIO_PS
+} xil_gpio_type;
+
+/**
+ * @struct xil_gpio_init_param
+ * @brief Structure holding the initialization parameters for Xilinx platform
+ * specific GPIO parameters.
+ */
+typedef struct xil_gpio_init_param {
+	/** Xilinx architecture */
+	enum xil_gpio_type	type;
+	/** Device ID */
+	uint32_t		device_id;
+} xil_gpio_init_param;
+
+/**
+ * @struct xil_gpio_desc
+ * @brief Xilinx platform specific GPIO descriptor
+ */
+typedef struct xil_gpio_desc {
+	/** Xilinx architecture */
+	enum xil_gpio_type	type;
+	/** Xilinx GPIO configuration */
+	void			*config;
+	/** Xilinx GPIO Instance */
+	void			*instance;
+} xil_gpio_desc;
+
+/**
+ * @brief Xilinx platform specific gpio platform ops structure
+ */
+extern const struct gpio_platform_ops xil_gpio_ops;
+
+#endif

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/src/adi_noos/drivers/platform/irq_extra.h

@@ -0,0 +1,91 @@
+/*******************************************************************************
+ *   @file   irq_extra.h
+ *   @brief  Header containing types used in the irq driver.
+ *   @author Cristian Pop ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#ifndef IRQ_EXTRA_H_
+#define IRQ_EXTRA_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <stdint.h>
+#include "../../include/irq.h"
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+
+/**
+ * @enum xil_irq_type
+ * @brief Xilinx platform architecture sections
+ */
+enum xil_irq_type {
+	/** Programmable Logic */
+	IRQ_PL,
+	/** Processing System */
+	IRQ_PS
+};
+
+/**
+ * @struct xil_irq_init_param
+ * @brief Structure holding the initialization parameters for Xilinx platform
+ * specific IRQ parameters.
+ */
+struct xil_irq_init_param {
+	/** Xilinx architecture */
+	enum xil_irq_type	type;
+};
+
+/**
+ * @struct xil_irq_desc
+ * @brief Xilinx platform specific IRQ descriptor
+ */
+struct xil_irq_desc {
+	/** Xilinx architecture */
+	enum xil_irq_type	type;
+	/** Xilinx IRQ Instance */
+	void				*instance;
+};
+
+/**
+ * @brief Xilinx specific IRQ platform ops structure
+ */
+extern const struct irq_platform_ops xil_irq_ops;
+
+#endif

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/src/adi_noos/drivers/platform/spi_extra.h

@@ -0,0 +1,115 @@
+/*******************************************************************************
+ *   @file   xilinx/spi_extra.h
+ *   @brief  Header containing extra types used in the spi driver.
+ *   @author scuciurean ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+#ifndef SPI_EXTRA_H_
+#define SPI_EXTRA_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <stdint.h>
+#include "../../include/spi.h"
+
+/******************************************************************************/
+/********************** Macros and Constants Definitions **********************/
+/******************************************************************************/
+
+#define SPI_CS_DECODE			0x01
+#define SPI_DEASSERT_CURRENT_SS	0x0F
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+
+/**
+ * @enum xil_spi_type
+ * @brief Xilinx platform architecture sections
+ */
+enum xil_spi_type {
+	/** Programmable Logic */
+	SPI_PL,
+	/** Processing System */
+	SPI_PS,
+	/** SPI Engine */
+	SPI_ENGINE
+};
+
+/**
+ * @struct xil_spi_init_param
+ * @brief Structure holding the initialization parameters for Xilinx platform
+ * specific SPI parameters when using xil_spi_ops.
+ */
+typedef struct xil_spi_init_param {
+	/** Xilinx architecture */
+	enum xil_spi_type	type;
+	/** SPI flags */
+	uint32_t		flags;
+} xil_spi_init_param;
+
+/**
+ * @struct xil_spi_desc
+ * @brief Xilinx platform specific SPI descriptor
+ */
+typedef struct xil_spi_desc {
+	/** Xilinx architecture */
+	enum xil_spi_type	type;
+	/** SPI flags */
+	uint32_t		flags;
+	/** SPI configuration */
+	void			*config;
+	/** SPI instance */
+	void			*instance;
+} xil_spi_desc;
+
+/**
+ * @brief SPI engine platform ops structure
+ */
+extern const struct spi_platform_ops spi_eng_platform_ops;
+
+/**
+ * @brief Xilinx specific SPI platform ops structure
+ */
+extern const struct spi_platform_ops xil_spi_ops;
+
+/**
+ * @brief Xilinx SPI PS register functions. No extra param needed
+ */
+extern const struct spi_platform_ops xil_spi_reg_ops_pl;
+
+#endif // SPI_EXTRA_H_

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/src/adi_noos/drivers/platform/uart_extra.h

@@ -0,0 +1,107 @@
+/*******************************************************************************
+ *   @file   xilinx/uart_extra.h
+ *   @brief  Header containing types used in the uart driver.
+ *   @author Cristian Pop ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#ifndef UART_EXTRA_H_
+#define UART_EXTRA_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+/******************************************************************************/
+/********************** Macros and Constants Definitions **********************/
+/******************************************************************************/
+
+#define UART_BUFF_LENGTH 256
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+
+/**
+ * @enum xil_uart_type
+ * @brief Xilinx platform architecture sections
+ */
+enum xil_uart_type {
+	/** Programmable Logic */
+	UART_PL,
+	/** Processing System */
+	UART_PS
+};
+
+/**
+ * @struct xil_uart_init_param
+ * @brief Structure holding the initialization parameters for Xilinx platform
+ * specific UART parameters.
+ */
+struct xil_uart_init_param {
+	/** Xilinx architecture */
+	enum xil_uart_type	type;
+	/** Interrupt Request ID */
+	uint32_t			irq_id;
+	/** Interrupt Request Descriptor */
+	struct irq_ctrl_desc *irq_desc;
+};
+
+/**
+ * @struct xil_uart_desc
+ * @brief Xilinx platform specific UART descriptor
+ */
+struct xil_uart_desc {
+	/** Xilinx architecture */
+	enum xil_uart_type	type;
+	/** Interrupt Request ID */
+	uint32_t			irq_id;
+	/** Interrupt Request Descriptor */
+	struct irq_ctrl_desc *irq_desc;
+	/** FIFO */
+	struct fifo_element	*fifo;
+	/** FIFO read offset */
+	uint32_t 			fifo_read_offset;
+	/** UART Buffer */
+	char 				buff[UART_BUFF_LENGTH];
+	/** Number of bytes received */
+	uint32_t 			bytes_received;
+	/** Total number of errors */
+	uint32_t 			total_error_count;
+	/** UART Instance */
+	void				*instance;
+};
+
+#endif

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/src/adi_noos/drivers/platform/xilinx_gpio.c

@@ -0,0 +1,464 @@
+/***************************************************************************//**
+ *   @file   xilinx/xilinx_gpio.c
+ *   @brief  Implementation of Xilinx GPIO Generic Driver.
+ *   @author Antoniu Miclaus ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <stdlib.h>
+
+#include <xparameters.h>
+#ifdef XPAR_XGPIO_NUM_INSTANCES
+#include <xgpio.h>
+#endif
+#ifdef XPAR_XGPIOPS_NUM_INSTANCES
+#include <xgpiops.h>
+#endif
+
+#include "gpio_extra.h"
+#include "../../include/error.h"
+#include "../../include/gpio.h"
+
+/******************************************************************************/
+/************************ Functions Definitions *******************************/
+/******************************************************************************/
+
+/**
+ * @brief Prepare the GPIO decriptor.
+ * @param desc - The GPIO descriptor.
+ * @param param - The structure that contains the GPIO parameters.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t _gpio_init(struct gpio_desc *desc,
+		   const struct gpio_init_param *param)
+{
+	int32_t				ret;
+	struct xil_gpio_desc		*xdesc;
+	struct xil_gpio_init_param	*xinit;
+
+	ret = FAILURE;
+
+	xdesc = desc->extra;
+	xinit = param->extra;
+
+	xdesc->type = xinit->type;
+	desc->number = param->number;
+
+	switch (xinit->type) {
+	case GPIO_PL:
+#ifdef XGPIO_H
+		xdesc->instance = (XGpio *)malloc(sizeof(XGpio));
+		if(!xdesc->instance)
+			goto pl_error;
+
+		xdesc->config = XGpio_LookupConfig(xinit->device_id);
+		if(xdesc->config == NULL)
+			goto pl_error;
+
+		ret = XGpio_CfgInitialize(xdesc->instance,
+					  xdesc->config,
+					  ((XGpio_Config*)xdesc->config)
+					  ->BaseAddress);
+		if(ret < 0)
+			goto pl_error;
+
+		break;
+pl_error:
+		free(xdesc->instance);
+#endif
+		goto error;
+	case GPIO_PS:
+#ifdef XGPIOPS_H
+		xdesc->instance = (XGpioPs *)malloc(sizeof(XGpioPs));
+		if(!xdesc->instance)
+			goto ps_error;
+
+		xdesc->config = XGpioPs_LookupConfig(xinit->device_id);
+		if(xdesc->config == NULL)
+			goto ps_error;
+
+		ret = XGpioPs_CfgInitialize(xdesc->instance,
+					    xdesc->config,
+					    ((XGpioPs_Config*)xdesc->config)->BaseAddr);
+		if(ret < 0)
+			goto ps_error;
+		break;
+ps_error:
+		free(xdesc->instance);
+#endif
+		goto error;
+error:
+	default:
+		return FAILURE;
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Obtain the GPIO decriptor.
+ * @param desc - The GPIO descriptor.
+ * @param param - GPIO initialization parameters
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t xil_gpio_get(struct gpio_desc **desc,
+		     const struct gpio_init_param *param)
+{
+	struct gpio_desc	*descriptor;
+	struct xil_gpio_desc	*extra;
+	int32_t			ret;
+
+	descriptor = (struct gpio_desc *)malloc(sizeof(*descriptor));
+	extra = (struct xil_gpio_desc*)malloc(sizeof(*extra));
+
+	if (!descriptor || !extra)
+		return FAILURE;
+
+	descriptor->extra = extra;
+	ret = _gpio_init(descriptor, param);
+
+	if(ret != SUCCESS)
+		goto error;
+
+	*desc = descriptor;
+
+	return SUCCESS;
+error:
+	free(extra);
+	free(descriptor);
+
+	return FAILURE;
+}
+
+/**
+ * @brief Get the value of an optional GPIO.
+ * @param desc - The GPIO descriptor.
+ * @param param - GPIO Initialization parameters.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t xil_gpio_get_optional(struct gpio_desc **desc,
+			      const struct gpio_init_param *param)
+{
+	if(param == NULL) {
+		*desc = NULL;
+		return SUCCESS;
+	}
+
+	return xil_gpio_get(desc, param);
+}
+
+/**
+ * @brief Free the resources allocated by gpio_get().
+ * @param desc - The GPIO descriptor.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t xil_gpio_remove(struct gpio_desc *desc)
+{
+	if (desc != NULL) {
+		free(((xil_gpio_desc *)(desc->extra))->instance);
+		free(desc->extra);
+		free(desc);
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Enable the input direction of the specified GPIO.
+ * @param desc - The GPIO descriptor.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t xil_gpio_direction_input(struct gpio_desc *desc)
+{
+	struct xil_gpio_desc	*extra;
+#ifdef XGPIO_H
+	uint8_t pin = desc->number;
+	uint32_t channel = 1;
+	uint32_t config	 = 0;
+#endif
+	extra = desc->extra;
+
+	switch (extra->type) {
+	case GPIO_PL:
+#ifdef XGPIO_H
+		/* We assume that pin 32 is the first pin from channel 2 */
+		if (pin >= 32) {
+			channel = 2;
+			pin -= 32;
+		}
+
+		config = XGpio_GetDataDirection((XGpio *)extra->instance,
+						channel);
+		config |= (1 << pin);
+		XGpio_SetDataDirection((XGpio *)extra->instance,
+				       channel,
+				       config);
+#endif
+		break;
+	case GPIO_PS:
+#ifdef XGPIOPS_H
+		XGpioPs_SetDirectionPin(extra->instance,
+					desc->number,
+					GPIO_IN);
+#endif
+		break;
+	default:
+		return FAILURE;
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Enable the output direction of the specified GPIO.
+ * @param desc - The GPIO descriptor.
+ * @param value - The value.
+ *                Example: GPIO_HIGH
+ *                         GPIO_LOW
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t xil_gpio_direction_output(struct gpio_desc *desc,
+				  uint8_t value)
+{
+	struct xil_gpio_desc	*extra;
+#ifdef XGPIO_H
+	uint8_t pin = desc->number;
+	uint8_t channel;
+	uint32_t reg_val;
+#endif
+	extra = desc->extra;
+
+	switch (extra->type) {
+	case GPIO_PL:
+#ifdef XGPIO_H
+		if (pin >= 32) {
+			channel = 2;
+			pin -= 32;
+		} else
+			channel = 1;
+
+		reg_val = XGpio_GetDataDirection(extra->instance,
+						 channel);
+		reg_val &= ~(1 << pin);
+		XGpio_SetDataDirection(extra->instance,
+				       channel,
+				       reg_val);
+		reg_val = XGpio_DiscreteRead(extra->instance,
+					     channel);
+		if(value)
+			reg_val |= (1 << pin);
+		else
+			reg_val &= ~(1 << pin);
+		XGpio_DiscreteWrite(extra->instance,
+				    channel,
+				    reg_val);
+#endif
+		break;
+	case GPIO_PS:
+#ifdef XGPIOPS_H
+		XGpioPs_SetDirectionPin(extra->instance,
+					desc->number,
+					GPIO_OUT);
+		XGpioPs_SetOutputEnablePin(extra->instance,
+					   desc->number,
+					   GPIO_OUT);
+		XGpioPs_WritePin(extra->instance,
+				 desc->number,
+				 value);
+#endif
+		break;
+	default:
+		return FAILURE;
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Get the direction of the specified GPIO.
+ * @param desc - The GPIO descriptor.
+ * @param direction - The direction.
+ *                    Example: GPIO_OUT
+ *                             GPIO_IN
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t xil_gpio_get_direction(struct gpio_desc *desc,
+			       uint8_t *direction)
+{
+	if (!desc)
+		return FAILURE;
+
+	struct xil_gpio_desc	*extra;
+	uint8_t pin = desc->number;
+
+#ifdef XGPIO_H
+	uint8_t channel;
+#endif
+	extra = desc->extra;
+
+	switch (extra->type) {
+	case GPIO_PL:
+#ifdef XGPIO_H
+		if (pin >= 32) {
+			channel = 2;
+			pin -= 32;
+		} else
+			channel = 1;
+		*direction = ((XGpio_GetDataDirection(extra->instance,
+						      channel) >> pin) & 0x1) ^ 0x1;
+#endif
+		break;
+	case GPIO_PS:
+#ifdef XGPIOPS_H
+		*direction = XGpioPs_GetDirectionPin(extra->instance, pin);
+#endif
+		break;
+	default:
+		return FAILURE;
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Set the value of the specified GPIO.
+ * @param desc - The GPIO descriptor.
+ * @param value - The value.
+ *                Example: GPIO_HIGH
+ *                         GPIO_LOW
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t xil_gpio_set_value(struct gpio_desc *desc,
+			   uint8_t value)
+{
+	struct xil_gpio_desc	*extra;
+#ifdef XGPIO_H
+	uint8_t pin = desc->number;
+	uint8_t channel;
+	uint32_t reg_val;
+#endif
+	extra = desc->extra;
+
+	switch (extra->type) {
+	case GPIO_PL:
+#ifdef XGPIO_H
+		if (pin >= 32) {
+			channel = 2;
+			pin -= 32;
+		} else
+			channel = 1;
+
+		reg_val = XGpio_DiscreteRead(extra->instance, channel);
+		if(value)
+			reg_val |= (1 << pin);
+		else
+			reg_val &= ~(1 << pin);
+		XGpio_DiscreteWrite(extra->instance, channel, reg_val);
+#endif
+		break;
+	case GPIO_PS:
+#ifdef XGPIOPS_H
+		XGpioPs_WritePin(extra->instance, desc->number, value);
+#endif
+		break;
+	default:
+		return FAILURE;
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Get the value of the specified GPIO.
+ * @param desc - The GPIO descriptor.
+ * @param value - The value.
+ *                Example: GPIO_HIGH
+ *                         GPIO_LOW
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t xil_gpio_get_value(struct gpio_desc *desc,
+			   uint8_t *value)
+{
+	if (!desc)
+		return FAILURE;
+
+	struct xil_gpio_desc	*extra;
+	uint8_t pin = desc->number;
+
+#ifdef XGPIO_H
+	uint8_t channel;
+#endif
+	extra = desc->extra;
+
+	switch (extra->type) {
+	case GPIO_PL:
+#ifdef XGPIO_H
+		if (pin >= 32) {
+			channel = 2;
+			pin -= 32;
+		} else
+			channel = 1;
+		*value = (XGpio_DiscreteRead(extra->instance, channel) >> pin) & 0x01;
+#endif
+		break;
+	case GPIO_PS:
+#ifdef XGPIOPS_H
+		*value = XGpioPs_ReadPin(extra->instance, pin);
+#endif
+		break;
+	default:
+		return FAILURE;
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Xilinx platform specific GPIO platform ops structure
+ */
+const struct gpio_platform_ops xil_gpio_ops = {
+	.gpio_ops_get = &xil_gpio_get,
+	.gpio_ops_get_optional = &xil_gpio_get_optional,
+	.gpio_ops_remove = &xil_gpio_remove,
+	.gpio_ops_direction_input = &xil_gpio_direction_input,
+	.gpio_ops_direction_output = &xil_gpio_direction_output,
+	.gpio_ops_get_direction = &xil_gpio_get_direction,
+	.gpio_ops_set_value = &xil_gpio_set_value,
+	.gpio_ops_get_value = &xil_gpio_get_value,
+};

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/src/adi_noos/drivers/platform/xilinx_irq.c

@@ -0,0 +1,384 @@
+/***************************************************************************//**
+ *   @file   xilinx/xilinx_irq.c
+ *   @brief  Implementation of Xilinx IRQ Generic Driver.
+ *   @author Cristian Pop ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <xparameters.h>
+#include <stdlib.h>
+#include "irq_extra.h"
+#include "../../include/irq.h"
+#include "../../include/error.h"
+#ifdef XPAR_XSCUGIC_NUM_INSTANCES
+#include <xscugic.h>
+#endif
+#ifdef XPAR_XINTC_NUM_INSTANCES
+#include <xintc.h>
+#endif
+#ifdef XPAR_XTMRCTR_NUM_INSTANCES
+#include <xtmrctr.h>
+#endif
+
+/******************************************************************************/
+/************************ Functions Definitions *******************************/
+/******************************************************************************/
+
+/**
+ * @brief Initialize the IRQ interrupts.
+ * @param desc - The IRQ controller descriptor.
+ * @param param - The structure that contains the IRQ parameters.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t xil_irq_ctrl_init(struct irq_ctrl_desc **desc,
+			  const struct irq_init_param *param)
+{
+	int32_t status;
+	struct irq_ctrl_desc *descriptor;
+	struct xil_irq_desc *xil_dev;
+#ifdef XSCUGIC_H
+	void *config;
+#endif
+
+	descriptor = (struct irq_ctrl_desc *)calloc(1, sizeof *descriptor);
+	if(!descriptor)
+		return FAILURE;
+	xil_dev = (struct xil_irq_desc *)calloc(1, sizeof *xil_dev);
+	if(!xil_dev) {
+		free(descriptor);
+		return FAILURE;
+	}
+
+	Xil_ExceptionInit();
+
+	descriptor->irq_ctrl_id = param->irq_ctrl_id;
+	descriptor->extra = xil_dev;
+	xil_dev->type = ((struct xil_irq_init_param *)param->extra)->type;
+
+	switch(xil_dev->type) {
+	case IRQ_PS:
+#ifdef XSCUGIC_H
+		xil_dev->instance = calloc(1, sizeof(XScuGic));
+		if(!xil_dev->instance)
+			goto error;
+
+		config = XScuGic_LookupConfig(descriptor->irq_ctrl_id);
+		if(!config)
+			goto ps_error;
+
+		status = XScuGic_CfgInitialize(xil_dev->instance, config,
+					       ((XScuGic_Config *)config)->CpuBaseAddress);
+		if (status != SUCCESS)
+			goto ps_error;
+
+		Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
+					     (Xil_ExceptionHandler)XScuGic_InterruptHandler,
+					     xil_dev->instance);
+
+		break;
+ps_error:
+		free(xil_dev->instance);
+#endif
+		goto error;
+	case IRQ_PL:
+#ifdef XINTC_H
+		xil_dev->instance = calloc(1, sizeof(XIntc));
+		if(!xil_dev->instance)
+			goto error;
+
+		status = XIntc_Initialize(xil_dev->instance, descriptor->irq_ctrl_id);
+		if(status != SUCCESS)
+			goto pl_error;
+
+		status = XIntc_Start(xil_dev->instance, XIN_REAL_MODE);
+		if(status != SUCCESS)
+			goto pl_error;
+
+		break;
+pl_error:
+		free(xil_dev->instance);
+#endif
+		goto error;
+	default:
+		goto error;
+
+		break;
+	}
+
+	*desc = descriptor;
+
+	return SUCCESS;
+
+error:
+	free(xil_dev);
+	free(descriptor);
+
+	return FAILURE;
+}
+
+/**
+ * @brief Enable global interrupts.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t xil_irq_global_enable(struct irq_ctrl_desc *desc)
+{
+	/* Enable interrupts */
+	Xil_ExceptionEnable();
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Disable global interrupts.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t xil_irq_global_disable(struct irq_ctrl_desc *desc)
+{
+	/* Disable interrupts */
+	Xil_ExceptionDisable();
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Enable specific interrupt.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t xil_irq_enable(struct irq_ctrl_desc *desc, uint32_t irq_id)
+{
+	struct xil_irq_desc *xil_dev = desc->extra;
+
+	switch(xil_dev->type) {
+	case IRQ_PS:
+#ifdef XSCUGIC_H
+		XScuGic_Enable(xil_dev->instance, irq_id);
+#endif
+		break;
+	case IRQ_PL:
+#ifdef XINTC_H
+		XIntc_Enable(xil_dev->instance, irq_id);
+#endif
+		break;
+	default:
+
+		return FAILURE;
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Disable specific interrupt.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t xil_irq_disable(struct irq_ctrl_desc *desc, uint32_t irq_id)
+{
+	struct xil_irq_desc *xil_dev = desc->extra;
+
+	switch(xil_dev->type) {
+	case IRQ_PS:
+#ifdef XSCUGIC_H
+		XScuGic_Disable(xil_dev->instance, irq_id);
+#endif
+		break;
+	case IRQ_PL:
+#ifdef XINTC_H
+		XIntc_Disable(xil_dev->instance, irq_id);
+#endif
+		break;
+	default:
+
+		return FAILURE;
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Register a callback to handle the irq events.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @param callback_desc - Callback descriptor
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t xil_irq_register_callback(struct irq_ctrl_desc *desc, uint32_t irq_id,
+				  struct callback_desc *callback_desc)
+{
+	struct xil_irq_desc *xil_dev = desc->extra;
+
+	switch(xil_dev->type) {
+	case IRQ_PS:
+#ifdef XSCUGIC_H
+		return XScuGic_Connect(xil_dev->instance, irq_id,
+				       (Xil_InterruptHandler) callback_desc->callback,
+				       callback_desc->ctx);
+#endif
+		break;
+	case IRQ_PL:
+#ifdef XINTC_H
+		if (irq_id == XPAR_AXI_INTC_AXI_TIMER_INTERRUPT_INTR) {
+			int32_t ret;
+
+			ret = XIntc_Connect(xil_dev->instance, irq_id,
+					    XTmrCtr_InterruptHandler, callback_desc->config);
+			if (IS_ERR_VALUE(ret))
+				return FAILURE;
+			XTmrCtr_SetHandler(callback_desc->config,
+					   (XTmrCtr_Handler)callback_desc->callback,
+					   callback_desc->ctx);
+
+			return SUCCESS;
+		}
+		return XIntc_Connect(xil_dev->instance, irq_id,
+				     (XInterruptHandler) callback_desc->callback,
+				     callback_desc->ctx);
+#endif
+		break;
+	default:
+		break;
+	}
+
+	return FAILURE;
+}
+
+/**
+ * @brief Set interrupt trigger level.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @param trig - New trigger level for the interrupt.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t xil_irq_trigger_level_set(struct irq_ctrl_desc *desc, uint32_t irq_id,
+				  enum irq_trig_level trig)
+{
+	struct xil_irq_desc *xil_dev = desc->extra;
+
+	if(trig == IRQ_EDGE_BOTH)
+		return -EINVAL;
+
+	switch(xil_dev->type) {
+	case IRQ_PS:
+#ifdef XSCUGIC_H
+		;
+		uint8_t priority, trigger;
+
+		XScuGic_GetPriorityTriggerType(xil_dev->instance, irq_id, &priority,
+					       &trigger);
+		trigger = trig;
+		XScuGic_SetPriorityTriggerType(xil_dev->instance, irq_id, priority,
+					       trigger);
+
+		return SUCCESS;
+#endif
+		break;
+	case IRQ_PL:
+#ifdef XINTC_H
+		/* Interrupt trigger determined in hardware. TODO: verify */
+		return SUCCESS;
+#endif
+		break;
+	default:
+		break;
+	}
+
+	return FAILURE;
+}
+
+/**
+ * @brief Unregisters a generic IRQ handling function.
+ * @param desc - The IRQ controller descriptor.
+ * @param irq_id - Interrupt identifier.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t xil_irq_unregister(struct irq_ctrl_desc *desc, uint32_t irq_id)
+{
+	struct xil_irq_desc *xil_dev = desc->extra;
+
+	switch(xil_dev->type) {
+	case IRQ_PS:
+#ifdef XSCUGIC_H
+		XScuGic_Disconnect(xil_dev->instance, irq_id);
+#endif
+		break;
+	case IRQ_PL:
+#ifdef XINTC_H
+		XIntc_Disconnect(xil_dev->instance, irq_id);
+#endif
+		break;
+	default:
+
+		return FAILURE;
+	}
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Free the resources allocated by irq_ctrl_init().
+ * @param desc - The IRQ control descriptor.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t xil_irq_ctrl_remove(struct irq_ctrl_desc *desc)
+{
+	struct xil_irq_desc *xil_dev = desc->extra;
+	free(xil_dev->instance);
+	free(desc->extra);
+	free(desc);
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Xilinx platform specific IRQ platform ops structure
+ */
+const struct irq_platform_ops xil_irq_ops = {
+	.init = &xil_irq_ctrl_init,
+	.register_callback = &xil_irq_register_callback,
+	.unregister = &xil_irq_unregister,
+	.global_enable = &xil_irq_global_enable,
+	.global_disable = &xil_irq_global_disable,
+	.trigger_level_set = &xil_irq_trigger_level_set,
+	.enable = &xil_irq_enable,
+	.disable = &xil_irq_disable,
+	.remove = &xil_irq_ctrl_remove
+};

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/src/adi_noos/drivers/platform/xilinx_spi.c

@@ -0,0 +1,461 @@
+/***************************************************************************//**
+ *   @file   xilinx/xilinx_spi.c
+ *   @brief  Implementation of Xilinx SPI Generic Driver.
+ *   @author Antoniu Miclaus ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <stdlib.h>
+
+#include <xparameters.h>
+#ifdef XPAR_XSPI_NUM_INSTANCES
+#include <xspi.h>
+#endif
+#ifdef XPAR_XSPIPS_NUM_INSTANCES
+#include <xspips.h>
+#endif
+
+#include "../../include/error.h"
+#include "../../include/spi.h"
+#include "spi_extra.h"
+
+#if defined(PLATFORM_ZYNQ)
+#define SPI_CLK_FREQ_HZ(dev)	(XPAR_PS7_SPI_ ## dev ## _SPI_CLK_FREQ_HZ)
+#define SPI_NUM_INSTANCES	XPAR_XSPIPS_NUM_INSTANCES
+#elif defined(PLATFORM_ZYNQMP)
+#define SPI_CLK_FREQ_HZ(dev)	(XPAR_PSU_SPI_ ## dev ## _SPI_CLK_FREQ_HZ)
+#define SPI_NUM_INSTANCES	XPAR_XSPIPS_NUM_INSTANCES
+#else
+#define SPI_NUM_INSTANCES	0
+#endif
+
+/******************************************************************************/
+/************************ Functions Definitions *******************************/
+/******************************************************************************/
+
+/**
+ * @brief Initialize the hardware SPI peripherial
+ *
+ * @param xdesc Platform specific SPI descriptor
+ * @param xinit Platform specific SPI init param
+ * @return int32_t FAILURE if the device couldn't be found or configured
+ */
+static int32_t spi_init_pl(struct spi_desc *desc,
+			   const struct spi_init_param *param)
+{
+#ifdef XSPI_H
+	int32_t				ret;
+	struct xil_spi_desc 		*xdesc;
+	struct xil_spi_init_param	*xinit;
+
+	xdesc = (xil_spi_desc*)malloc(sizeof(xil_spi_desc));
+	if(!xdesc) {
+		free(xdesc);
+		return FAILURE;
+	}
+
+	desc->extra = xdesc;
+	xinit = param->extra;
+	xdesc->type = xinit->type;
+	xdesc->flags = xinit->flags;
+
+	xdesc->instance = (XSpi*)calloc(1, sizeof(XSpi));
+	if(!xdesc->instance)
+		goto pl_error;
+
+	xdesc->config = XSpi_LookupConfig(param->device_id);
+	if(xdesc->config == NULL)
+		goto pl_error;
+
+	ret = XSpi_CfgInitialize(xdesc->instance,
+				 xdesc->config,
+				 ((XSpi_Config*)xdesc->config)
+				 ->BaseAddress);
+	if(ret != SUCCESS)
+		goto pl_error;
+
+	ret = XSpi_Initialize(xdesc->instance, param->device_id);
+	if (ret != SUCCESS)
+		goto pl_error;
+
+	ret = XSpi_SetOptions(xdesc->instance,
+			      XSP_MASTER_OPTION |
+			      ((desc->mode & SPI_CPOL) ?
+			       XSP_CLK_ACTIVE_LOW_OPTION : 0) |
+			      ((desc->mode & SPI_CPHA) ?
+			       XSP_CLK_PHASE_1_OPTION : 0));
+	if (ret != SUCCESS)
+		goto pl_error;
+
+	ret = XSpi_Start(xdesc->instance);
+	if (ret != SUCCESS)
+		goto pl_error;
+
+	XSpi_IntrGlobalDisable((XSpi *)(xdesc->instance));
+
+	return SUCCESS;
+
+pl_error:
+	free(xdesc->instance);
+	free(xdesc);
+#endif
+	return FAILURE;
+}
+
+/**
+ * @brief Initialize the hardware SPI peripherial
+ *
+ * @param xdesc Platform specific SPI descriptor
+ * @param xinit Platform specific SPI init param
+ * @return int32_t FAILURE if the device couldn't be found or configured
+ */
+static int32_t spi_init_ps(struct spi_desc *desc,
+			   const struct spi_init_param *param)
+{
+#ifdef XSPIPS_H
+	int32_t				ret;
+	struct xil_spi_desc 		*xdesc;
+	struct xil_spi_init_param	*xinit;
+	const uint32_t			prescaler_default = XSPIPS_CLK_PRESCALE_64;
+	const uint32_t			prescaler_min = XSPIPS_CLK_PRESCALE_4;
+	const uint32_t			prescaler_max = XSPIPS_CLK_PRESCALE_256;
+	uint32_t			prescaler = 0u;
+	uint32_t			input_clock = 0u;
+
+	xdesc = (xil_spi_desc*)malloc(sizeof(xil_spi_desc));
+	if(!xdesc) {
+		free(xdesc);
+		return FAILURE;
+	}
+
+	desc->extra = xdesc;
+	xinit = param->extra;
+	xdesc->type = xinit->type;
+	xdesc->flags = xinit->flags;
+
+	xdesc->instance = (XSpiPs*)malloc(sizeof(XSpiPs));
+	if(!xdesc->instance)
+		goto ps_error;
+
+	xdesc->config = XSpiPs_LookupConfig(param->device_id);
+	if(xdesc->config == NULL)
+		goto ps_error;
+
+	ret = XSpiPs_CfgInitialize(xdesc->instance,
+				   xdesc->config,
+				   ((XSpiPs_Config*)xdesc->config)
+				   ->BaseAddress);
+	if(ret != SUCCESS)
+		goto ps_error;
+
+	switch (param->device_id) {
+#if (SPI_NUM_INSTANCES >= 1)
+	case 0:
+		input_clock = SPI_CLK_FREQ_HZ(0);
+		break;
+#endif
+#if (SPI_NUM_INSTANCES >= 2)
+	case 1:
+		input_clock = SPI_CLK_FREQ_HZ(1);
+		break;
+#endif
+	default:
+		goto ps_error;
+	};
+
+	if (desc->max_speed_hz != 0u) {
+		uint32_t div = input_clock / desc->max_speed_hz;
+		uint32_t rem = input_clock % desc->max_speed_hz;
+		uint32_t po2 = !(div & (div - 1)) && !rem;
+
+		// find the power of two just higher than div and
+		// store the exponent in prescaler
+		while(div) {
+			prescaler += 1;
+			div >>= 1u;
+		}
+
+		// this exponent - 1 is needed because of the way
+		// xilinx stores it into registers
+		if (prescaler)
+			prescaler -= 1;
+
+		// this exponent - 1 is needed when initial div was
+		// precisely a power of two
+		if (prescaler && po2)
+			prescaler -= 1;
+
+		if (prescaler < prescaler_min)
+			prescaler = prescaler_min;
+
+		if (prescaler > prescaler_max)
+			prescaler = prescaler_max;
+	} else
+		prescaler = prescaler_default;
+
+	ret = XSpiPs_SetClkPrescaler(xdesc->instance, prescaler);
+
+	if(ret != SUCCESS)
+		goto ps_error;
+
+	return SUCCESS;
+
+ps_error:
+	free(xdesc->instance);
+	free(xdesc);
+#endif
+	return FAILURE;
+}
+
+/**
+ * @brief Initialize the SPI communication peripheral.
+ * @param desc - The SPI descriptor.
+ * @param param - The structure that contains the SPI parameters.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t xil_spi_init(struct spi_desc **desc,
+		     const struct spi_init_param *param)
+{
+	int32_t				ret;
+	enum xil_spi_type		*spi_type;
+
+	if (!param) {
+		return FAILURE;
+	}
+
+	*desc = malloc(sizeof(**desc));
+	if(! *desc) {
+		free(*desc);
+		return FAILURE;
+	}
+
+	spi_type = param->extra;
+
+	if(!spi_type)
+		goto init_error;
+
+	(*desc)->max_speed_hz = param->max_speed_hz;
+	(*desc)->mode = param->mode;
+	(*desc)->bit_order = param->bit_order;
+	(*desc)->chip_select = param->chip_select;
+
+	switch (*spi_type) {
+	case SPI_PL:
+		ret = spi_init_pl(*desc, param);
+		break;
+	case SPI_PS:
+		ret = spi_init_ps(*desc, param);
+		break;
+
+	default:
+		goto init_error;
+		break;
+	}
+
+	if (ret != SUCCESS) {
+init_error:
+		free(*desc);
+
+		return FAILURE;
+	}
+
+	return ret;
+}
+
+/**
+ * @brief Free the resources allocated by spi_init().
+ * @param desc - The SPI descriptor.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t xil_spi_remove(struct spi_desc *desc)
+{
+#ifdef XSPI_H
+	int32_t				ret;
+#endif
+	struct xil_spi_desc	*xdesc = NULL;
+	enum xil_spi_type	*spi_type;
+
+	spi_type = desc->extra;
+
+	if(!spi_type)
+		return FAILURE;
+
+	switch (*spi_type ) {
+	case SPI_PL:
+#ifdef XSPI_H
+		xdesc = desc->extra;
+
+		if(!xdesc)
+			return FAILURE;
+
+		ret = XSpi_Stop((XSpi *)(xdesc->instance));
+		if(ret != SUCCESS)
+			goto error;
+#endif
+		break;
+	case SPI_PS:
+#ifdef XSPIPS_H
+		xdesc = desc->extra;
+
+		if(!xdesc)
+			return FAILURE;
+#endif
+		break;
+
+		/* Intended fallthrough */
+#ifdef XSPI_H
+error:
+#endif
+	default:
+		return FAILURE;
+	}
+
+	if(xdesc)
+		free(xdesc->instance);
+	free(desc->extra);
+	free(desc);
+
+	return SUCCESS;
+}
+
+/**
+ * @brief Write and read data to/from SPI.
+ * @param desc - The SPI descriptor.
+ * @param data - The buffer with the transmitted/received data.
+ * @param bytes_number - Number of bytes to write/read.
+ * @return SUCCESS in case of success, FAILURE otherwise.
+ */
+int32_t xil_spi_write_and_read(struct spi_desc *desc,
+			       uint8_t *data,
+			       uint16_t bytes_number)
+{
+	int32_t			ret;
+#ifdef XSPI_H
+	uint32_t		ctrl_reg;
+#endif
+	struct xil_spi_desc	*xdesc;
+	enum xil_spi_type	*spi_type;
+
+	ret = FAILURE;
+
+	spi_type = desc->extra;
+
+	if(!spi_type)
+		return FAILURE;
+
+	xdesc = desc->extra;
+
+	switch (*spi_type) {
+	case SPI_PL:
+#ifdef XSPI_H
+		ret = XSpi_SetOptions(xdesc->instance,
+				      XSP_MASTER_OPTION |
+				      ((desc->mode & SPI_CPOL) ?
+				       XSP_CLK_ACTIVE_LOW_OPTION : 0) |
+				      ((desc->mode & SPI_CPHA) ?
+				       XSP_CLK_PHASE_1_OPTION : 0));
+		if (ret != SUCCESS)
+			goto error;
+
+		ctrl_reg = XSpi_GetControlReg(((XSpi*)xdesc->instance));
+		if (desc->bit_order == SPI_BIT_ORDER_LSB_FIRST)
+			ctrl_reg |= XSP_CR_LSB_MSB_FIRST_MASK;
+		else
+			ctrl_reg &= ~ XSP_CR_LSB_MSB_FIRST_MASK;
+		XSpi_SetControlReg(((XSpi*)xdesc->instance), ctrl_reg);
+
+		ret = XSpi_SetSlaveSelect(xdesc->instance,
+					  0x01 << desc->chip_select);
+		if (ret != SUCCESS)
+			goto error;
+
+		ret = XSpi_Transfer(xdesc->instance,
+				    data,
+				    data,
+				    bytes_number);
+		if (ret != SUCCESS)
+			goto error;
+#endif
+		break;
+	case SPI_PS:
+#ifdef XSPIPS_H
+		ret = XSpiPs_SetOptions(xdesc->instance,
+					XSPIPS_MASTER_OPTION |
+					((xdesc->flags & SPI_CS_DECODE) ?
+					 XSPIPS_DECODE_SSELECT_OPTION : 0) |
+					XSPIPS_FORCE_SSELECT_OPTION |
+					((desc->mode & SPI_CPOL) ?
+					 XSPIPS_CLK_ACTIVE_LOW_OPTION : 0) |
+					((desc->mode & SPI_CPHA) ?
+					 XSPIPS_CLK_PHASE_1_OPTION : 0));
+		if (ret != SUCCESS)
+			goto error;
+
+		ret = XSpiPs_SetSlaveSelect(xdesc->instance,
+					    desc->chip_select);
+		if (ret != SUCCESS)
+			goto error;
+		ret = XSpiPs_PolledTransfer(xdesc->instance,
+					    data,
+					    data,
+					    bytes_number);
+		if (ret != SUCCESS)
+			goto error;
+		ret = XSpiPs_SetSlaveSelect(xdesc->instance, SPI_DEASSERT_CURRENT_SS);
+		if (ret != SUCCESS)
+			goto error;
+#endif
+		break;
+error:
+	default:
+		return FAILURE;
+	}
+
+	return ret;
+}
+
+/**
+ * @brief Xilinx platform specific SPI platform ops structure
+ */
+const struct spi_platform_ops xil_spi_ops = {
+	.init = &xil_spi_init,
+	.write_and_read = &xil_spi_write_and_read,
+	.write_and_read_3wire = NULL, // Not support.
+	.remove = &xil_spi_remove
+};

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/src/adi_noos/drivers/platform/xilinx_spi_pl.c

@@ -0,0 +1,531 @@
+/*******************************************************************************
+ *   @file   xilinx/xilinx_spi_pl.c
+ *   @brief  Driver for spi pl device using registers
+ *   @author Mihail Chindris ([email protected])
+********************************************************************************
+ * Copyright 2021(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#include <xparameters.h>
+
+#ifdef XPAR_XSPI_NUM_INSTANCES
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <xspi.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include "spi.h"
+#include "error.h"
+#include "delay.h"
+#include "util.h"
+
+/******************************************************************************/
+/********************** Macros and Constants Definitions **********************/
+/******************************************************************************/
+
+#define XPS_TYPE_WRITE		0x1
+#define XPS_TYPE_READ		0x2
+#define XSP_DEFAULT_SR_VALUE	0x25
+#define XSP_DUMMY_DATA		0xFF
+
+/*
+ * Used to store current spi device configuration in order to not update it for
+ * each spi transaction if not needed.
+ */
+static struct spi_desc g_spi_desc[XPAR_XSPI_NUM_INSTANCES];
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+
+/* Xilinx PL spi specific data */
+struct xspi_desc {
+	uint32_t base_addr;
+	uint32_t disable_slaves_mask;
+	uint32_t fifo_depth;
+	uint8_t  cs_asserted;
+};
+
+/* Structure used to iterate over SPI messages */
+struct msg_iter {
+	struct spi_msg	*msgs;
+	uint32_t	len;
+	uint32_t	i;
+	uint32_t	buff_i;
+	uint8_t		is_wr;
+};
+
+/******************************************************************************/
+/************************ Functions Definitions *******************************/
+/******************************************************************************/
+
+/* Read device register */
+static inline uint32_t _read(struct xspi_desc *xdesc, uint32_t reg)
+{
+	return Xil_In32(xdesc->base_addr + reg);
+}
+
+/* Write device register */
+static inline void _write(struct xspi_desc *xdesc, uint32_t reg, uint32_t val)
+{
+	Xil_Out32(xdesc->base_addr + reg, val);
+}
+
+/* Update device register. Only bits set to 1 in mask will be modified */
+static inline void _wr_mask(struct xspi_desc *xdesc, uint32_t reg,
+			    uint32_t val, uint32_t mask)
+{
+	uint32_t tmp;
+
+	tmp = _read(xdesc, reg);
+	tmp &= ~mask;
+	tmp |= val & mask;
+	_write(xdesc, reg, tmp);
+}
+
+/* Update spi device configuration if needed */
+static void _update_mode(struct spi_desc *desc)
+{
+	uint32_t		val;
+	uint32_t		mask;
+
+	if (desc->mode == g_spi_desc[desc->device_id].mode &&
+	    desc->bit_order == g_spi_desc[desc->device_id].bit_order)
+		return ;
+
+	/* Update mode */
+	val = desc->mode | SPI_CPOL ? XSP_CR_CLK_POLARITY_MASK : 0;
+	val |= desc->mode | SPI_CPHA ? XSP_CR_CLK_PHASE_MASK : 0;
+	mask = XSP_CR_CLK_POLARITY_MASK | XSP_CR_CLK_PHASE_MASK;
+
+	val |= desc->bit_order == SPI_BIT_ORDER_LSB_FIRST ?
+	       XSP_CR_LSB_MSB_FIRST_MASK : 0;
+	mask |= XSP_CR_LSB_MSB_FIRST_MASK;
+
+	_wr_mask(desc->extra, XSP_CR_OFFSET, val, mask);
+	g_spi_desc[desc->device_id] = *desc;
+}
+
+/* Configure SPI PL device */
+static int32_t _xil_spi_init_dev(struct xspi_desc *xdesc)
+{
+	uint32_t val;
+
+	/* Software reset */
+	_write(xdesc, XSP_SRR_OFFSET, XSP_SRR_RESET_MASK);
+	mdelay(1);
+
+	/* Check if success reset */
+	val = _read(xdesc, XSP_SR_OFFSET);
+	if (val != XSP_DEFAULT_SR_VALUE)
+		return -ENODEV;
+
+	/* Disable interrupts. Drivers only works with pooled mode */
+	_write(xdesc, XSP_IIER_OFFSET, 0);
+
+	/* Deasert chip selects */
+	_write(xdesc, XSP_SSR_OFFSET, 0xFFFFFFFF);
+
+	/* Get fifo depth */
+	while (!(_read(xdesc, XSP_SR_OFFSET) & XSP_SR_TX_FULL_MASK))
+		_write(xdesc, XSP_DTR_OFFSET, XSP_DUMMY_DATA);
+	xdesc->fifo_depth = _read(xdesc, XSP_TFO_OFFSET) + 1;
+
+	/* Configure spi device */
+	val = XSP_CR_ENABLE_MASK |
+	      XSP_CR_MANUAL_SS_MASK |
+	      XSP_CR_TXFIFO_RESET_MASK |
+	      XSP_CR_RXFIFO_RESET_MASK |
+	      XSP_CR_MASTER_MODE_MASK |
+	      XSP_CR_TRANS_INHIBIT_MASK;
+
+	_write(xdesc, XSP_CR_OFFSET, val);
+
+	return SUCCESS;
+}
+
+/* Initialize spi_desc structure and device */
+static int32_t xil_spi_init_pl(struct spi_desc **desc,
+			       const struct spi_init_param *param)
+{
+	struct spi_desc		*ldesc;
+	struct xspi_desc	*xdesc;
+	int32_t			err;
+	XSpi_Config		*cfg;
+
+	if (!desc || !param || param->device_id >= XPAR_XSPI_NUM_INSTANCES)
+		return -EINVAL;
+
+	cfg = XSpi_LookupConfig(param->device_id);
+	if (!cfg)
+		return -EINVAL;
+
+	if (param->chip_select > cfg->NumSlaveBits)
+		return -EINVAL;
+
+	ldesc = (struct spi_desc *)calloc(1, sizeof(*ldesc));
+	if (!ldesc)
+		return -ENOMEM;
+
+	xdesc = (struct xspi_desc *)calloc(1, sizeof(*xdesc));
+	if (!xdesc) {
+		err = -ENOMEM;
+		goto error;
+	}
+
+	ldesc->bit_order = param->bit_order;
+	ldesc->chip_select = param->chip_select;
+	ldesc->mode = param->mode;
+	xdesc->base_addr = cfg->BaseAddress;
+	xdesc->disable_slaves_mask = (1 << cfg->NumSlaveBits) - 1;
+	xdesc->cs_asserted = 0;
+
+	err = _xil_spi_init_dev(xdesc);
+	if (IS_ERR_VALUE(err))
+		goto error;
+
+	ldesc->extra = xdesc;
+	*desc = ldesc;
+
+	return SUCCESS;
+
+error:
+	free(xdesc);
+	free(ldesc);
+
+	return err;
+}
+
+/* Remove allocated resources */
+static int32_t xil_spi_remove_pl(struct spi_desc *desc)
+{
+	if (!desc)
+		return -EINVAL;
+
+	free(desc->extra);
+	free(desc);
+
+	return SUCCESS;
+}
+
+/*
+ * Fill fifo until fifo is full or no more data available.
+ * Return the number of written bytes.
+ */
+static uint32_t _wr_fifo(struct xspi_desc *xdesc, uint8_t *data,
+			 uint32_t len)
+{
+	uint32_t i;
+	uint32_t to_write;
+	uint32_t tx_available;
+
+	tx_available = xdesc->fifo_depth - _read(xdesc, XSP_TFO_OFFSET);
+	to_write = min(tx_available, len);
+	for (i = 0; i < to_write; ++i)
+		if (data)
+			_write(xdesc, XSP_DTR_OFFSET, data[i]);
+		else
+			_write(xdesc, XSP_DTR_OFFSET, XSP_DUMMY_DATA);
+
+	return to_write;
+}
+
+/*
+ * Read fifo until fifo is empty or no more buffer available to read into
+ * Returns the number of read bytes
+ */
+static uint32_t _rd_fifo(struct xspi_desc *xdesc, uint8_t *data,
+			 uint32_t len)
+{
+	uint32_t rx_available;
+	uint32_t to_read;
+	uint32_t tmp;
+	uint32_t i;
+
+	tmp = _read(xdesc, XSP_SR_OFFSET);
+	if (tmp & XSP_SR_RX_EMPTY_MASK)
+		return 0;
+
+	rx_available = _read(xdesc, XSP_RFO_OFFSET) + 1;
+	to_read = min(rx_available, len);
+	for (i = 0; i < to_read; ++i) {
+		tmp = _read(xdesc, XSP_DRR_OFFSET);
+		if (data)
+			data[i] = tmp;
+	}
+
+	return to_read;
+}
+
+/* If start is 0 stop transfer, else start it.
+ * CS will be asserted if needed. If different CS othere than the one needed
+ * is asserted. Deassert it and assert correct one */
+static void _xil_spi_start_transfer(struct spi_desc *desc, uint8_t start)
+{
+	struct xspi_desc	*xdesc;
+
+	xdesc = desc->extra;
+	if (start) {
+		if (xdesc->cs_asserted) {
+			if (desc->chip_select ==
+			    g_spi_desc[desc->device_id].chip_select)
+				return ;
+			else
+				/* Stop transfer to start again with new CS */
+				_xil_spi_start_transfer(desc, 0);
+		}
+		_write(xdesc, XSP_SSR_OFFSET, ~(1 << desc->chip_select));
+		_wr_mask(xdesc, XSP_CR_OFFSET, 0, XSP_CR_TRANS_INHIBIT_MASK);
+	} else {
+		_wr_mask(xdesc, XSP_CR_OFFSET, XSP_CR_TRANS_INHIBIT_MASK,
+			 XSP_CR_TRANS_INHIBIT_MASK);
+		_write(xdesc, XSP_SSR_OFFSET, xdesc->disable_slaves_mask);
+	}
+	xdesc->cs_asserted = start;
+}
+
+
+/* SPI polled transfer */
+static int32_t xil_spi_write_and_read_pl(struct spi_desc *desc, uint8_t *data,
+		uint16_t bytes_number)
+{
+	struct xspi_desc	*xdesc;
+	uint32_t		rx;
+	uint32_t		tx;
+
+	if (!desc || !desc->extra)
+		return -EINVAL;
+
+	xdesc = desc->extra;
+	_update_mode(desc);
+
+	_xil_spi_start_transfer(desc, 1);
+	rx = 0;
+	tx = 0;
+	while (rx < bytes_number) {
+		if (tx < bytes_number)
+			tx += _wr_fifo(xdesc, data + tx, bytes_number - tx);
+		rx += _rd_fifo(xdesc, data + rx, bytes_number - rx);
+	}
+	_xil_spi_start_transfer(desc, 0);
+
+	return SUCCESS;
+}
+
+/* Get type of message. It can be READ, WRITE or both */
+static uint32_t _get_msg_type(struct spi_msg *msg)
+{
+	uint32_t	type;
+
+	type = 0;
+	if (msg->tx_buff)
+		type |= XPS_TYPE_WRITE;
+	if (msg->rx_buff)
+		type |= XPS_TYPE_READ;
+
+	return type;
+}
+
+/* Get information based on current iterator position */
+static void _get_data(struct msg_iter *it, uint8_t **buff, uint32_t *len,
+		      uint32_t *type)
+{
+	struct spi_msg *msg;
+
+	if (it->i == it->len) {
+		*len = 0;
+		return ;
+	}
+
+	msg = it->msgs + it->i;
+	if (it->is_wr)
+		*buff = msg->tx_buff;
+	else
+		*buff = msg->rx_buff;
+
+	if (*buff)
+		*buff += it->buff_i;
+
+	*len = msg->bytes_number - it->buff_i;
+	if (type)
+		*type = _get_msg_type(msg);
+}
+
+/*
+ * Increment iterator position with desired length.
+ * If the new position has a different message type, new_type will be set to 1
+ * If a CS change is needed, cs_change is set
+ */
+static void _increment_iter(struct msg_iter *it, uint32_t len,
+			    uint8_t *cs_change, uint8_t *new_type)
+{
+	struct spi_msg	*msg;
+	uint32_t	type;
+	uint32_t	extra_len;
+
+	if (!len)
+		return ;
+
+	*cs_change = 0;
+	*new_type = 0;
+	msg = it->msgs + it->i;
+	if (it->buff_i + len > msg->bytes_number)
+		extra_len = it->buff_i + len - msg->bytes_number;
+	else
+		extra_len = 0;
+	len -= extra_len;
+	it->buff_i += len;
+	if (it->buff_i == msg->bytes_number) {
+		type = _get_msg_type(msg);
+		++it->i;
+		it->buff_i = 0;
+		if (cs_change && msg->cs_change)
+			*cs_change = 1;
+		if (new_type)
+			if (it->i == it->len ||
+			    type != _get_msg_type(it->msgs + it->i))
+				*new_type = 1;
+	}
+	if (extra_len)
+		_increment_iter(it, extra_len, cs_change, new_type);
+}
+
+/*
+ * SPI polling transfer of multiple messages.
+ */
+static int32_t xil_spi_transfer_pl(struct spi_desc *desc, struct spi_msg *msgs,
+				   uint32_t len)
+
+{
+	struct xspi_desc	*xdesc;
+	uint8_t			cs_change;
+	uint8_t			new_type;
+	struct msg_iter		rx = {.msgs = msgs, .len = len, .is_wr = 0};
+	struct msg_iter		tx = {.msgs = msgs, .len = len, .is_wr = 1};
+	uint8_t			*buff;
+	uint32_t		bytes;
+	uint32_t		type;
+	/* Bytes to increment rx when only a write transaction is executed */
+	uint32_t		to_inc_rx;
+	/* Difference between rx and tx iterators in bytes */
+	uint32_t		tx_advance;
+	/* Save bytes sent during a write loop */
+	uint32_t		tx_sent;
+	/* Used to loop if need to empty the RX FIFO */
+	uint32_t		loop;
+
+	if (!desc || !desc->extra)
+		return -EINVAL;
+
+	xdesc = desc->extra;
+	_update_mode(desc);
+
+	tx_advance = 0;
+	to_inc_rx = 0;
+	buff = NULL;
+	type = 0;
+	do {
+		_xil_spi_start_transfer(desc, 1);
+
+		tx_sent = 0;
+		/* Writing loop */
+		do {
+			_get_data(&tx, &buff, &bytes, &type);
+			if (type & XPS_TYPE_READ)
+				/*
+				 * Do not write more bytes than fifo_depth if
+				 * they haven't been read.
+				 */
+				bytes = min(bytes,
+					    xdesc->fifo_depth - tx_advance);
+			bytes = _wr_fifo(xdesc, buff, bytes);
+			tx_sent += bytes;
+			_increment_iter(&tx, bytes, &cs_change, &new_type);
+			tx_advance += bytes;
+		} while (!cs_change && !new_type && bytes);
+
+		if (type & XPS_TYPE_READ) {
+			loop = 1;
+			/*
+			 * Loop only when no more data to write otherwise read
+			 * only available data.
+			 */
+			while (loop) {
+				if (!new_type)
+					loop = 0;
+				_get_data(&rx, &buff, &bytes, NULL);
+				bytes = _rd_fifo(xdesc, buff, bytes);
+				_increment_iter(&rx, bytes, &cs_change, &new_type);
+				tx_advance -= bytes;
+				if (loop && new_type)
+					break;
+			}
+		} else {
+			/* Clean RX FIFO if it was only a WRITE message */
+			to_inc_rx += tx_sent;
+			if (new_type) {
+				/* Wait for TX to be sent */
+				while (!(_read(xdesc, XSP_SR_OFFSET) &
+					 XSP_SR_TX_EMPTY_MASK))
+					;
+				/* Reset fifo. Only write was performed */
+				_wr_mask(xdesc, XSP_CR_OFFSET,
+					 XSP_CR_RXFIFO_RESET_MASK,
+					 XSP_CR_RXFIFO_RESET_MASK);
+
+				_increment_iter(&rx, to_inc_rx, NULL, NULL);
+				tx_advance -= to_inc_rx;
+				to_inc_rx = 0;
+			}
+		}
+
+		if ((cs_change && rx.i != len) || (!cs_change && rx.i == len))
+			_xil_spi_start_transfer(desc, 0);
+	} while (rx.i < len);
+
+	return SUCCESS;
+}
+
+const struct spi_platform_ops xil_spi_reg_ops_pl = {
+	.init = xil_spi_init_pl,
+	.remove = xil_spi_remove_pl,
+	.write_and_read = xil_spi_write_and_read_pl,
+	.write_and_read_3wire = NULL, // Not support.
+	.transfer = xil_spi_transfer_pl
+};
+
+#endif // XPAR_XSPI_NUM_INSTANCES

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/src/adi_noos/drivers/rf-transceiver/ad9361_reg/ad9361_reg.c

@@ -0,0 +1,151 @@
+/***************************************************************************//**
+ * @file ad9361_reg.c
+ * @brief Implementation of AD9680 Driver.
+ * @author DBogdan ([email protected])
+ ********************************************************************************
+ * Copyright 2014-2016(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * - Neither the name of Analog Devices, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * - The use of this software may or may not infringe the patent rights
+ * of one or more patent holders. This license does not release you
+ * from the requirement that you obtain separate licenses from these
+ * patent holders to use this software.
+ * - Use of the software either in source or binary form, must be run
+ * on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************/
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+#include "ad9361_reg.h"
+
+#include <stdlib.h>
+#include <stdio.h>
+#include "../../../include/error.h"
+
+/***************************************************************************//**
+ * @brief ad9361_reg_read
+ *******************************************************************************/
+int32_t ad9361_reg_read(struct ad9361_reg_dev *dev,
+			uint16_t reg_addr,
+			uint8_t *reg_data)
+{
+	uint8_t tx_buf[2];
+	uint8_t rx_buf[1];
+	int32_t ret;
+
+	tx_buf[0] = reg_addr >> 8;
+	tx_buf[1] = reg_addr & 0xFF;
+	
+
+	ret = spi_write_and_read_3wire(dev->spi_desc,
+			tx_buf, rx_buf, 2, 1);
+
+	*reg_data = rx_buf[0];
+
+	return ret;
+}
+
+/***************************************************************************//**
+ * @brief ad9361_reg_write
+ *******************************************************************************/
+int32_t ad9361_reg_write(struct ad9361_reg_dev *dev,
+			 uint16_t reg_addr,
+			 uint8_t reg_data)
+{
+	uint8_t buf[3];
+
+	int32_t ret;
+
+	buf[0] = 0x80 | reg_addr >> 8;
+	buf[1] = reg_addr & 0xFF;
+	buf[2] = reg_data;
+
+	ret = spi_write_and_read_3wire(dev->spi_desc,
+				 buf, NULL, 3, 0);
+	return ret;
+}
+
+/***************************************************************************//**
+ * @brief ad9361_reg_init
+ *******************************************************************************/
+int32_t ad9361_reg_init(struct ad9361_reg_dev **device,
+		     const struct ad9361_reg_init_param *init_param)
+{
+	int ret = SUCCESS;
+	struct ad9361_reg_dev *dev;
+
+	dev = (struct ad9361_reg_dev *)malloc(sizeof(*dev));
+	if (!dev)
+		return FAILURE;
+
+	/* SPI */
+	ret = spi_init(&dev->spi_desc, init_param->spi_init);
+	ret |= gpio_get(&dev->gpio_desc_resetb, init_param->gpio_resetb);
+
+//	gpio_direction_output(dev->gpio_desc_resetb, 0);
+//
+//	ad9361_reg_reset(dev);
+
+	*device = dev;
+
+	return ret;
+}
+
+/**
+ * AD9361 Device Reset
+ * @param phy The AD9361 state structure.
+ * @return 0 in case of success, negative error code otherwise.
+ */
+int32_t ad9361_reg_reset(struct ad9361_reg_dev *dev)
+{
+	if (dev->gpio_desc_resetb) {
+		gpio_set_value(dev->gpio_desc_resetb, 0);
+		mdelay(10);
+		gpio_set_value(dev->gpio_desc_resetb, 1);
+		mdelay(10);
+		return 0;
+	}
+	return 0;
+}
+
+/***************************************************************************//**
+ * @brief Free the resources allocated by ad9361_reg_setup().
+ *
+ * @param dev - The device structure.
+ *
+ * @return SUCCESS in case of success, negative error code otherwise.
+*******************************************************************************/
+int32_t ad9361_reg_remove(struct ad9361_reg_dev *dev)
+{
+	int32_t ret;
+
+	ret = spi_remove(dev->spi_desc);
+
+	free(dev);
+
+	return ret;
+}

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/src/adi_noos/drivers/rf-transceiver/ad9361_reg/ad9361_reg.h

@@ -0,0 +1,104 @@
+/***************************************************************************//**
+ * @file ad9361_reg.h
+ * @brief Header file of ad9361_reg Driver.
+ * @author DBogdan ([email protected])
+ ********************************************************************************
+ * Copyright 2014-2016(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * - Neither the name of Analog Devices, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * - The use of this software may or may not infringe the patent rights
+ * of one or more patent holders. This license does not release you
+ * from the requirement that you obtain separate licenses from these
+ * patent holders to use this software.
+ * - Use of the software either in source or binary form, must be run
+ * on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************/
+#ifndef ad9361_reg_H_
+#define ad9361_reg_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+#include <stdint.h>
+#include "../../../include/delay.h"
+#include "../../../include/spi.h"
+#include "../../../include/gpio.h"
+
+/******************************************************************************/
+/********************** Macros and Constants Definitions **********************/
+/******************************************************************************/
+
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+struct ad9361_reg_dev {
+	/* SPI */
+	spi_desc	*spi_desc;
+	gpio_desc 	*gpio_desc_resetb;
+};
+
+struct ad9361_reg_init_param {
+	/* SPI */
+	spi_init_param	*spi_init;
+	gpio_init_param	*gpio_resetb;
+};
+
+enum Operation_Type{
+	AD9361_WRITE,
+	AD9361_READ,
+	AD9361_WAIT,
+	AD9361_WHEN
+};
+
+struct ad9361_reg_config {
+	int operation;
+	uint16_t val1;
+	uint16_t val2;
+};
+
+
+
+/******************************************************************************/
+/************************ Functions Declarations ******************************/
+/******************************************************************************/
+
+int32_t ad9361_reg_read(struct ad9361_reg_dev *dev,
+			uint16_t reg_addr,
+			uint8_t *reg_data);
+
+int32_t ad9361_reg_write(struct ad9361_reg_dev *dev,
+			 uint16_t reg_addr,
+			 uint8_t reg_data);
+
+int32_t ad9361_reg_init(struct ad9361_reg_dev **device,
+		     const struct ad9361_reg_init_param *init_param);
+
+int32_t ad9361_reg_reset(struct ad9361_reg_dev *dev);
+
+int32_t ad9361_reg_remove(struct ad9361_reg_dev *dev);
+
+#endif

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/src/adi_noos/include/axi_io.h

@@ -0,0 +1,59 @@
+/***************************************************************************//**
+ *   @file   axi_io.h
+ *   @brief  Header file of AXI IO.
+ *   @author Antoniu Miclaus ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#ifndef AXI_IO_H_
+#define AXI_IO_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <stdint.h>
+
+/******************************************************************************/
+/************************ Functions Declarations ******************************/
+/******************************************************************************/
+
+/* AXI IO Read data */
+int32_t axi_io_read(uint32_t base, uint32_t offset, uint32_t *data);
+
+/* AXI IO Write data */
+int32_t axi_io_write(uint32_t base, uint32_t offset, uint32_t data);
+
+#endif // AXI_IO_H_

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/src/adi_noos/include/delay.h

@@ -0,0 +1,59 @@
+/***************************************************************************//**
+ *   @file   delay.h
+ *   @brief  Header file of Delay functions
+ *   @author DBogdan ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#ifndef DELAY_H_
+#define DELAY_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <stdint.h>
+
+/******************************************************************************/
+/************************ Functions Declarations ******************************/
+/******************************************************************************/
+
+/* Generate microseconds delay. */
+void udelay(uint32_t usecs);
+
+/* Generate miliseconds delay. */
+void mdelay(uint32_t msecs);
+
+#endif // DELAY_H_

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/src/adi_noos/include/error.h

@@ -0,0 +1,67 @@
+/***************************************************************************//**
+ *   @file   error.h
+ *   @brief  Error codes definition
+ *   @author DBogdan ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#ifndef ERROR_H_
+#define ERROR_H_
+
+#include <errno.h>
+
+/******************************************************************************/
+/********************** Macros and Constants Definitions **********************/
+/******************************************************************************/
+
+#ifdef SUCCESS
+#undef SUCCESS
+#endif
+#define SUCCESS		0
+#ifdef FAILURE
+#undef FAILURE
+#endif
+#define FAILURE		-1
+
+#ifndef __ELASTERROR
+#define __ELASTERROR 2000
+#endif
+
+#define EOVERRUN	(__ELASTERROR + 1) /* Circular buffer overrun */
+
+
+#define IS_ERR_VALUE(x)	((x) < 0)
+
+#endif // ERROR_H_

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/src/adi_noos/include/gpio.h

@@ -0,0 +1,165 @@
+/***************************************************************************//**
+ *   @file   gpio.h
+ *   @brief  Header file of GPIO Interface
+ *   @author DBogdan ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#ifndef GPIO_H_
+#define GPIO_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <stdint.h>
+
+/******************************************************************************/
+/********************** Macros and Constants Definitions **********************/
+/******************************************************************************/
+
+#define GPIO_OUT	0x01
+#define GPIO_IN		0x00
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+
+/**
+ * @struct gpio_platform_ops
+ * @brief Structure holding gpio function pointers that point to the platform
+ * specific function
+ */
+struct gpio_platform_ops ;
+
+/**
+ * @struct gpio_init_param
+ * @brief Structure holding the parameters for GPIO initialization.
+ */
+typedef struct gpio_init_param {
+	/** GPIO number */
+	int32_t		number;
+	/** GPIO platform specific functions */
+	const struct gpio_platform_ops *platform_ops;
+	/** GPIO extra parameters (device specific) */
+	void		*extra;
+} gpio_init_param;
+
+/**
+ * @struct gpio_desc
+ * @brief Structure holding the GPIO descriptor.
+ */
+typedef struct gpio_desc {
+	/** GPIO number */
+	int32_t		number;
+	/** GPIO platform specific functions */
+	const struct gpio_platform_ops *platform_ops;
+	/** GPIO extra parameters (device specific) */
+	void		*extra;
+} gpio_desc;
+
+/**
+ * @enum gpio_values
+ * @brief Enum that holds the possible output states of a GPIO.
+ */
+enum gpio_values {
+	/** GPIO logic low */
+	GPIO_LOW,
+	/** GPIO logic high */
+	GPIO_HIGH,
+	/** GPIO high impedance */
+	GPIO_HIGH_Z
+};
+
+/**
+ * @struct gpio_platform_ops
+ * @brief Structure holding gpio function pointers that point to the platform
+ * specific function
+ */
+struct gpio_platform_ops {
+	/** gpio initialization function pointer */
+	int32_t (*gpio_ops_get)(struct gpio_desc **, const struct gpio_init_param *);
+	/** gpio optional descriptor function pointer */
+	int32_t (*gpio_ops_get_optional)(struct gpio_desc **,
+					 const struct gpio_init_param *);
+	/** gpio remove function pointer */
+	int32_t (*gpio_ops_remove)(struct gpio_desc *);
+	/** gpio direction input function pointer */
+	int32_t (*gpio_ops_direction_input)(struct gpio_desc *);
+	/** gpio direction output function pointer */
+	int32_t (*gpio_ops_direction_output)(struct gpio_desc *, uint8_t);
+	/** gpio get direction function pointer */
+	int32_t (*gpio_ops_get_direction)(struct gpio_desc *, uint8_t *);
+	/** gpio set value function pointer */
+	int32_t (*gpio_ops_set_value)(struct gpio_desc *, uint8_t);
+	/** gpio get value function pointer */
+	int32_t (*gpio_ops_get_value)(struct gpio_desc *, uint8_t *);
+};
+
+/******************************************************************************/
+/************************ Functions Declarations ******************************/
+/******************************************************************************/
+
+/* Obtain the GPIO decriptor. */
+int32_t gpio_get(struct gpio_desc **desc,
+		 const struct gpio_init_param *param);
+
+/* Obtain optional GPIO descriptor. */
+int32_t gpio_get_optional(struct gpio_desc **desc,
+			  const struct gpio_init_param *param);
+
+/* Free the resources allocated by gpio_get() */
+int32_t gpio_remove(struct gpio_desc *desc);
+
+/* Enable the input direction of the specified GPIO. */
+int32_t gpio_direction_input(struct gpio_desc *desc);
+
+/* Enable the output direction of the specified GPIO. */
+int32_t gpio_direction_output(struct gpio_desc *desc,
+			      uint8_t value);
+
+/* Get the direction of the specified GPIO. */
+int32_t gpio_get_direction(struct gpio_desc *desc,
+			   uint8_t *direction);
+
+/* Set the value of the specified GPIO. */
+int32_t gpio_set_value(struct gpio_desc *desc,
+		       uint8_t value);
+
+/* Get the value of the specified GPIO. */
+int32_t gpio_get_value(struct gpio_desc *desc,
+		       uint8_t *value);
+
+#endif // GPIO_H_

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/src/adi_noos/include/irq.h

@@ -0,0 +1,188 @@
+/***************************************************************************//**
+ *   @file   irq.h
+ *   @brief  Header file of IRQ interface.
+ *   @author Cristian Pop ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#ifndef IRQ_H_
+#define IRQ_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <stdint.h>
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+
+/**
+ * @enum irq_uart_event_e
+ * @brief Possible events for uart interrupt
+ */
+enum irq_uart_event_e {
+	/** Write operation finalized */
+	IRQ_WRITE_DONE,
+	/** Read operation finalized */
+	IRQ_READ_DONE,
+	/** An error occurred */
+	IRQ_ERROR
+};
+
+enum irq_trig_level {
+	IRQ_LEVEL_LOW,
+	IRQ_LEVEL_HIGH,
+	IRQ_EDGE_FALLING,
+	IRQ_EDGE_RISING,
+	IRQ_EDGE_BOTH
+};
+
+/**
+ * @struct irq_platform_ops
+ * @brief Structure holding IRQ function pointers that point to the platform
+ * specific function
+ */
+struct irq_platform_ops ;
+
+/**
+ * @struct irq_init_param
+ * @brief Structure holding the initial parameters for Interrupt Request.
+ */
+struct irq_init_param {
+	/** Interrupt request controller ID. */
+	uint32_t	irq_ctrl_id;
+	/** Platform specific IRQ platform ops structure. */
+	const struct irq_platform_ops *platform_ops;
+	/** IRQ extra parameters (device specific) */
+	void		*extra;
+};
+
+/**
+ * @struct irq_desc
+ * @brief Structure for Interrupt Request descriptor.
+ */
+struct irq_ctrl_desc {
+	/** Interrupt request controller ID. */
+	uint32_t	irq_ctrl_id;
+	/** Platform specific IRQ platform ops structure. */
+	const struct irq_platform_ops *platform_ops;
+	/** IRQ extra parameters (device specific) */
+	void		*extra;
+};
+
+/**
+ * @struct callback_desc
+ * @brief Structure describing a callback to be registered
+ */
+struct callback_desc {
+	/**
+	 * Callback to be called when the event an event occurs
+	 *  @param ctx - Same as \ref callback_desc.ctx
+	 *  @param event - Event that generated the callback
+	 *  @param extra - Platform specific data
+	 */
+	void (*callback)(void *ctx, uint32_t event, void *extra);
+	/** Parameter to be passed when the callback is called */
+	void *ctx;
+	/** Platform specific configuration for a callback */
+	void *config;
+};
+
+/**
+ * @struct irq_platform_ops
+ * @brief Structure holding IRQ function pointers that point to the platform
+ * specific function
+ */
+struct irq_platform_ops {
+	/** Initialize a interrupt controller peripheral. */
+	int32_t (*init)(struct irq_ctrl_desc **desc,
+			const struct irq_init_param *param);
+	/** Register a callback to handle the irq events */
+	int32_t (*register_callback)(struct irq_ctrl_desc *desc, uint32_t irq_id,
+				     struct callback_desc *callback_desc);
+	/** Unregisters a generic IRQ handling function */
+	int32_t (*unregister)(struct irq_ctrl_desc *desc, uint32_t irq_id);
+	/** Global interrupt enable */
+	int32_t (*global_enable)(struct irq_ctrl_desc *desc);
+	/** Global interrupt disable */
+	int32_t (*global_disable)(struct irq_ctrl_desc *desc);
+	/** Set interrupt trigger level. */
+	int32_t (*trigger_level_set)(struct irq_ctrl_desc *desc, uint32_t irq_id,
+				     enum irq_trig_level trig);
+	/** Enable specific interrupt */
+	int32_t (*enable)(struct irq_ctrl_desc *desc, uint32_t irq_id);
+	/** Disable specific interrupt */
+	int32_t (*disable)(struct irq_ctrl_desc *desc, uint32_t irq_id);
+	/** IRQ remove function pointer */
+	int32_t (*remove)(struct irq_ctrl_desc *desc);
+};
+
+/******************************************************************************/
+/************************ Functions Declarations ******************************/
+/******************************************************************************/
+
+/* Initialize a interrupt controller peripheral. */
+int32_t irq_ctrl_init(struct irq_ctrl_desc **desc,
+		      const struct irq_init_param *param);
+
+/* Free the resources allocated by irq_ctrl_init(). */
+int32_t irq_ctrl_remove(struct irq_ctrl_desc *desc);
+
+/* Register a callback to handle the irq events */
+int32_t irq_register_callback(struct irq_ctrl_desc *desc, uint32_t irq_id,
+			      struct callback_desc *callback_desc);
+
+/* Unregisters a generic IRQ handling function */
+int32_t irq_unregister(struct irq_ctrl_desc *desc, uint32_t irq_id);
+
+/* Global interrupt enable */
+int32_t irq_global_enable(struct irq_ctrl_desc *desc);
+
+/* Global interrupt disable */
+int32_t irq_global_disable(struct irq_ctrl_desc *desc);
+
+/* Set interrupt trigger level. */
+int32_t irq_trigger_level_set(struct irq_ctrl_desc *desc, uint32_t irq_id,
+			      enum irq_trig_level trig);
+
+/* Enable specific interrupt */
+int32_t irq_enable(struct irq_ctrl_desc *desc, uint32_t irq_id);
+
+/* Disable specific interrupt */
+int32_t irq_disable(struct irq_ctrl_desc *desc, uint32_t irq_id);
+
+#endif // IRQ_H_

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/src/adi_noos/include/spi.h

@@ -0,0 +1,194 @@
+/***************************************************************************//**
+ *   @file   spi.h
+ *   @brief  Header file of SPI Interface
+ *   @author DBogdan ([email protected])
+********************************************************************************
+ * Copyright 2019(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+#ifndef SPI_H_
+#define SPI_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+
+#include <stdint.h>
+
+/******************************************************************************/
+/********************** Macros and Constants Definitions **********************/
+/******************************************************************************/
+
+#define	SPI_CPHA	0x01
+#define	SPI_CPOL	0x02
+#define	SPI_3WIRE	0x04
+
+/******************************************************************************/
+/*************************** Types Declarations *******************************/
+/******************************************************************************/
+
+/**
+ * @enum spi_mode
+ * @brief SPI configuration for clock phase and polarity.
+ */
+typedef enum spi_mode {
+	/** Data on rising, shift out on falling */
+	SPI_MODE_0 = (0 | 0),
+	/** Data on falling, shift out on rising */
+	SPI_MODE_1 = (0 | SPI_CPHA),
+	/** Data on falling, shift out on rising */
+	SPI_MODE_2 = (SPI_CPOL | 0),
+	/** Data on rising, shift out on falling */
+	SPI_MODE_3 = (SPI_CPOL | SPI_CPHA),
+	/** Data on rising, shift out on falling */
+	SPI_MODE_4 = SPI_3WIRE
+} spi_mode;
+
+/**
+ * @enum spi_bit_order
+ * @brief SPI configuration for bit order (MSB/LSB).
+ */
+typedef enum spi_bit_order {
+	/** Most-significant bit (MSB) first */
+	SPI_BIT_ORDER_MSB_FIRST = 0,
+	/** Least-significant bit (LSB) first */
+	SPI_BIT_ORDER_LSB_FIRST = 1,
+} spi_bit_order;
+
+/**
+ * @struct spi_msg_list
+ * @brief List item describing a SPI transfer
+ */
+struct spi_msg {
+	/** Buffer with data to send. If NULL, 0x00 will be sent */
+	uint8_t			*tx_buff;
+	/** Buffer where to store data. If NULL, incoming data won't be saved */
+	uint8_t			*rx_buff;
+	/** Length of buffers. Must have equal size. */
+	uint32_t		bytes_number;
+	/** If set, CS will be deasserted after the transfer */
+	uint8_t			cs_change;
+};
+
+/**
+ * @struct spi_platform_ops
+ * @brief Structure holding SPI function pointers that point to the platform
+ * specific function
+ */
+struct spi_platform_ops ;
+
+/**
+ * @struct spi_init_param
+ * @brief Structure holding the parameters for SPI initialization
+ */
+typedef struct spi_init_param {
+	/** Device ID */
+	uint32_t	device_id;
+	/** maximum transfer speed */
+	uint32_t	max_speed_hz;
+	/** SPI chip select */
+	uint8_t		chip_select;
+	/** SPI mode */
+	enum spi_mode	mode;
+	/** SPI bit order */
+	enum spi_bit_order	bit_order;
+	const struct spi_platform_ops *platform_ops;
+	/**  SPI extra parameters (device specific) */
+	void		*extra;
+} spi_init_param;
+
+/**
+ * @struct spi_desc
+ * @brief Structure holding SPI descriptor.
+ */
+typedef struct spi_desc {
+	/** Device ID */
+	uint32_t	device_id;
+	/** maximum transfer speed */
+	uint32_t	max_speed_hz;
+	/** SPI chip select */
+	uint8_t		chip_select;
+	/** SPI mode */
+	enum spi_mode	mode;
+	/** SPI bit order */
+	enum spi_bit_order	bit_order;
+	const struct spi_platform_ops *platform_ops;
+	/**  SPI extra parameters (device specific) */
+	void		*extra;
+} spi_desc;
+
+/**
+ * @struct spi_platform_ops
+ * @brief Structure holding SPI function pointers that point to the platform
+ * specific function
+ */
+struct spi_platform_ops {
+	/** SPI initialization function pointer */
+	int32_t (*init)(struct spi_desc **, const struct spi_init_param *);
+	/** SPI write/read function pointer */
+	int32_t (*write_and_read)(struct spi_desc *, uint8_t *, uint16_t);
+	/** SPI write function pointer */
+	int32_t (*write_and_read_3wire)(struct spi_desc *, uint8_t *,uint8_t *,uint16_t, uint16_t);
+	/** Iterate over the spi_msg array and send all messages at once */
+	int32_t (*transfer)(struct spi_desc *, struct spi_msg *, uint32_t);
+	/** SPI remove function pointer */
+	int32_t (*remove)(struct spi_desc *);
+};
+
+/******************************************************************************/
+/************************ Functions Declarations ******************************/
+/******************************************************************************/
+
+/* Initialize the SPI communication peripheral. */
+int32_t spi_init(struct spi_desc **desc,
+		 const struct spi_init_param *param);
+
+/* Free the resources allocated by spi_init(). */
+int32_t spi_remove(struct spi_desc *desc);
+
+/* Write and read data to/from SPI. */
+int32_t spi_write_and_read(struct spi_desc *desc,
+			   uint8_t *data,
+			   uint16_t bytes_number);
+int32_t spi_write_and_read_3wire(struct spi_desc *desc,
+			   uint8_t *write_data,
+			   uint8_t *read_data,
+			   uint16_t write_bytes_number,
+			   uint16_t read_bytes_number);
+
+/* Iterate over the spi_msg array and send all messages at once */
+int32_t spi_transfer(struct spi_desc *desc, struct spi_msg *msgs, uint32_t len);
+
+
+#endif // SPI_H_

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/src/adi_noos/include/util.h

@@ -0,0 +1,165 @@
+/***************************************************************************//**
+ *   @file   util.h
+ *   @brief  Implementation of utility functions.
+ *   @author DBogdan ([email protected])
+********************************************************************************
+ * Copyright 2018(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+#ifndef UTIL_H_
+#define UTIL_H_
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+#include <stdint.h>
+#include <stdlib.h>
+#include <stdbool.h>
+/******************************************************************************/
+/********************** Macros and Constants Definitions **********************/
+/******************************************************************************/
+#define BIT(x)	(1 << (x))
+
+#define ARRAY_SIZE(x) \
+	(sizeof(x) / sizeof((x)[0]))
+
+#define DIV_ROUND_UP(x,y) \
+	(((x) + (y) - 1) / (y))
+#define DIV_ROUND_CLOSEST(x, y) \
+	(((x) + (y) / 2) / (y))
+#define DIV_ROUND_CLOSEST_ULL(x, y) \
+	DIV_ROUND_CLOSEST(x, y)
+
+#define min(x, y) \
+	(((x) < (y)) ? (x) : (y))
+#define min_t(type, x, y) \
+	(type)min((type)(x), (type)(y))
+
+#define max(x, y) \
+	(((x) > (y)) ? (x) : (y))
+#define max_t(type, x, y) \
+	(type)max((type)(x), (type)(y))
+
+#define clamp(val, min_val, max_val) \
+	(max(min((val), (max_val)), (min_val)))
+#define clamp_t(type, val, min_val, max_val) \
+	(type)clamp((type)(val), (type)(min_val), (type)(max_val))
+
+#define swap(x, y) \
+	{typeof(x) _tmp_ = (x); (x) = (y); (y) = _tmp_;}
+
+#define round_up(x,y) \
+		(((x)+(y)-1)/(y))
+
+#define BITS_PER_LONG 32
+
+#define GENMASK(h, l) ({ 					\
+		uint32_t t = (uint32_t)(~0UL);			\
+		t = t << (BITS_PER_LONG - (h - l + 1));		\
+		t = t >> (BITS_PER_LONG - (h + 1));		\
+		t;						\
+})
+
+#define bswap_constant_32(x) \
+	((((x) & 0xff000000) >> 24) | (((x) & 0x00ff0000) >>  8) | \
+	 (((x) & 0x0000ff00) <<  8) | (((x) & 0x000000ff) << 24))
+
+#define bswap_constant_16(x) ((((x) & (uint16_t)0xff00) >> 8) | \
+				 (((x) & (uint16_t)0x00ff) << 8))
+
+#define bit_swap_constant_8(x) \
+	((((x) & 0x80) >> 7) | \
+	 (((x) & 0x40) >> 5) | \
+	 (((x) & 0x20) >> 3) | \
+	 (((x) & 0x10) >> 1) | \
+	 (((x) & 0x08) << 1) | \
+	 (((x) & 0x04) << 3) | \
+	 (((x) & 0x02) << 5) | \
+	 (((x) & 0x01) << 7))
+
+#define U16_MAX		((uint16_t)~0U)
+#define S16_MAX		((int16_t)(U16_MAX>>1))
+
+#define DIV_U64(x, y) (x / y)
+
+#define UNUSED_PARAM(x) ((void)x)
+
+#define shift_right(x, s) ((x) < 0 ? -(-(x) >> (s)) : (x) >> (s))
+
+/******************************************************************************/
+/************************ Functions Declarations ******************************/
+/******************************************************************************/
+/* Find first set bit in word. */
+uint32_t find_first_set_bit(uint32_t word);
+/* Find last set bit in word. */
+uint32_t find_last_set_bit(uint32_t word);
+/* Locate the closest element in an array. */
+uint32_t find_closest(int32_t val,
+		      const int32_t *array,
+		      uint32_t size);
+/* Shift the value and apply the specified mask. */
+uint32_t field_prep(uint32_t mask, uint32_t val);
+/* Get a field specified by a mask from a word. */
+uint32_t field_get(uint32_t mask, uint32_t word);
+/* Log base 2 of the given number. */
+int32_t log_base_2(uint32_t x);
+/* Find greatest common divisor of the given two numbers. */
+uint32_t greatest_common_divisor(uint32_t a,
+				 uint32_t b);
+/* Calculate best rational approximation for a given fraction. */
+void rational_best_approximation(uint32_t given_numerator,
+				 uint32_t given_denominator,
+				 uint32_t max_numerator,
+				 uint32_t max_denominator,
+				 uint32_t *best_numerator,
+				 uint32_t *best_denominator);
+/* Calculate the number of set bits. */
+uint32_t hweight8(uint32_t word);
+/* Calculate the quotient and the remainder of an integer division. */
+uint64_t do_div(uint64_t* n,
+		uint64_t base);
+/* Unsigned 64bit divide with 64bit divisor and remainder */
+uint64_t div64_u64_rem(uint64_t dividend, uint64_t divisor,
+		       uint64_t *remainder);
+/* Unsigned 64bit divide with 32bit divisor with remainder */
+uint64_t div_u64_rem(uint64_t dividend, uint32_t divisor, uint32_t *remainder);
+int64_t div_s64_rem(int64_t dividend, int32_t divisor, int32_t *remainder);
+/* Unsigned 64bit divide with 32bit divisor */
+uint64_t div_u64(uint64_t dividend, uint32_t divisor);
+int64_t div_s64(int64_t dividend, int32_t divisor);
+/* Converts from string to int32_t */
+int32_t str_to_int32(const char *str);
+/* Converts from string to uint32_t */
+uint32_t srt_to_uint32(const char *str);
+#endif // UTIL_H_
+

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/src/adi_noos/util/util.c

@@ -0,0 +1,283 @@
+/***************************************************************************//**
+ *   @file   util.c
+ *   @brief  Implementation of utility functions.
+ *   @author DBogdan ([email protected])
+********************************************************************************
+ * Copyright 2018(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+#include <string.h>
+#include <stdlib.h>
+#include "errno.h"
+#include "../include/util.h"
+
+/******************************************************************************/
+/************************** Functions Implementation **************************/
+/******************************************************************************/
+
+/**
+ * Find first set bit in word.
+ */
+uint32_t find_first_set_bit(uint32_t word)
+{
+	uint32_t first_set_bit = 0;
+
+	while (word) {
+		if (word & 0x1)
+			return first_set_bit;
+		word >>= 1;
+		first_set_bit ++;
+	}
+
+	return 32;
+}
+
+/**
+ * Find last set bit in word.
+ */
+uint32_t find_last_set_bit(uint32_t word)
+{
+	uint32_t bit = 0;
+	uint32_t last_set_bit = 32;
+
+	while (word) {
+		if (word & 0x1)
+			last_set_bit = bit;
+		word >>= 1;
+		bit ++;
+	}
+
+	return last_set_bit;
+}
+
+/**
+ * Locate the closest element in an array.
+ */
+uint32_t find_closest(int32_t val,
+		      const int32_t *array,
+		      uint32_t size)
+{
+	int32_t diff = abs(array[0] - val);
+	uint32_t ret = 0;
+	uint32_t i;
+
+	for (i = 1; i < size; i++) {
+		if (abs(array[i] - val) < diff) {
+			diff = abs(array[i] - val);
+			ret = i;
+		}
+	}
+
+	return ret;
+}
+
+/**
+ * Shift the value and apply the specified mask.
+ */
+uint32_t field_prep(uint32_t mask, uint32_t val)
+{
+	return (val << find_first_set_bit(mask)) & mask;
+}
+
+/**
+ * Get a field specified by a mask from a word.
+ */
+uint32_t field_get(uint32_t mask, uint32_t word)
+{
+	return (word & mask) >> find_first_set_bit(mask);
+}
+
+/**
+ * Log base 2 of the given number.
+ */
+int32_t log_base_2(uint32_t x)
+{
+	return find_last_set_bit(x);
+}
+
+/**
+ * Find greatest common divisor of the given two numbers.
+ */
+uint32_t greatest_common_divisor(uint32_t a,
+				 uint32_t b)
+{
+	uint32_t div;
+	uint32_t common_div = 1;
+
+	if ((a == 0) || (b == 0))
+		return max(a, b);
+
+	for (div = 1; (div <= a) && (div <= b); div++)
+		if (!(a % div) && !(b % div))
+			common_div = div;
+
+	return common_div;
+}
+
+/**
+ * Calculate best rational approximation for a given fraction.
+ */
+void rational_best_approximation(uint32_t given_numerator,
+				 uint32_t given_denominator,
+				 uint32_t max_numerator,
+				 uint32_t max_denominator,
+				 uint32_t *best_numerator,
+				 uint32_t *best_denominator)
+{
+	uint32_t gcd;
+
+	gcd = greatest_common_divisor(given_numerator, given_denominator);
+
+	*best_numerator = given_numerator / gcd;
+	*best_denominator = given_denominator / gcd;
+
+	if ((*best_numerator > max_numerator) ||
+	    (*best_denominator > max_denominator)) {
+		*best_numerator = 0;
+		*best_denominator = 0;
+	}
+}
+
+/**
+ * Calculate the number of set bits.
+ */
+uint32_t hweight8(uint32_t word)
+{
+	uint32_t count = 0;
+
+	while (word) {
+		if (word & 0x1)
+			count++;
+		word >>= 1;
+	}
+
+	return count;
+}
+
+/**
+ * Calculate the quotient and the remainder of an integer division.
+ */
+uint64_t do_div(uint64_t* n,
+		uint64_t base)
+{
+	uint64_t mod = 0;
+
+	mod = *n % base;
+	*n = *n / base;
+
+	return mod;
+}
+
+/**
+ * Unsigned 64bit divide with 64bit divisor and remainder
+ */
+uint64_t div64_u64_rem(uint64_t dividend, uint64_t divisor, uint64_t *remainder)
+{
+	*remainder = dividend % divisor;
+
+	return dividend / divisor;
+}
+
+/**
+ * Unsigned 64bit divide with 32bit divisor with remainder
+ */
+uint64_t div_u64_rem(uint64_t dividend, uint32_t divisor, uint32_t *remainder)
+{
+	*remainder = do_div(&dividend, divisor);
+
+	return dividend;
+}
+
+/**
+ * Signed 64bit divide with 32bit divisor with remainder
+ */
+int64_t div_s64_rem(int64_t dividend, int32_t divisor, int32_t *remainder)
+{
+	*remainder = dividend % divisor;
+	return dividend / divisor;
+}
+
+/**
+ * Unsigned 64bit divide with 32bit divisor
+ */
+uint64_t div_u64(uint64_t dividend, uint32_t divisor)
+{
+	uint32_t remainder;
+
+	return div_u64_rem(dividend, divisor, &remainder);
+}
+
+/**
+ * Signed 64bit divide with 32bit divisor
+ */
+int64_t div_s64(int64_t dividend, int32_t divisor)
+{
+	int32_t remainder;
+	return div_s64_rem(dividend, divisor, &remainder);
+}
+
+/**
+ * Converts from string to int32_t
+ * @param *str
+ * @return int32_t
+ */
+int32_t str_to_int32(const char *str)
+{
+	char *end;
+	int32_t value = strtol(str, &end, 0);
+
+	if (end == str)
+		return -EINVAL;
+	else
+		return value;
+}
+
+/**
+ * Converts from string to uint32_t
+ * @param *str
+ * @return uint32_t
+ */
+uint32_t srt_to_uint32(const char *str)
+{
+	char *end;
+	uint32_t value = strtoul(str, &end, 0);
+
+	if (end == str)
+		return -EINVAL;
+	else
+		return value;
+}

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/src/app_config.h

@@ -0,0 +1,55 @@
+/***************************************************************************//**
+ *   @file   app_config.h
+ *   @brief  Config file of AD9361/API Driver.
+ *   @author DBogdan ([email protected])
+********************************************************************************
+ * Copyright 2015(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+#ifndef CONFIG_H_
+#define CONFIG_H_
+
+#define XILINX_PLATFORM
+#define SPI_INTERFACE_SPI_ENGINE
+
+#define HAVE_SPLIT_GAIN_TABLE	1 /* only set to 0 in case split_gain_table_mode_enable = 0*/
+#define HAVE_TDD_SYNTH_TABLE	1 /* only set to 0 in case split_gain_table_mode_enable = 0*/
+
+#define AD9361_DEVICE			1 /* set it 1 if AD9361 device is used, 0 otherwise */
+#define AD9364_DEVICE			0 /* set it 1 if AD9364 device is used, 0 otherwise */
+#define AD9363A_DEVICE			0 /* set it 1 if AD9363A device is used, 0 otherwise */
+
+#define HAVE_VERBOSE_MESSAGES /* Recommended during development prints errors and warnings */
+//#define HAVE_DEBUG_MESSAGES /* For Debug purposes only */
+
+#endif

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/src/dev_profile/ad9516_profile.c

@@ -0,0 +1,89 @@
+#include "dev_profile.h"
+#include "../app_config.h"
+#include "../adi_noos/drivers/frequency/ad9516/ad9516.h"
+
+
+static spi_init_param ad9516_spi_init = {
+	.device_id = SPI_DEVICE_ID,
+    .max_speed_hz = SPI_ENGINE_MAX_SPEED,
+	.mode = SPI_MODE_4,
+	.chip_select = SPI_CS_AD9516,
+	.platform_ops = SPI_OPS,
+	.extra = SPI_PARAM
+};
+
+struct ad9516_init_param ad9516_default_init_param = {
+	/* SPI */
+	.spi_init = &ad9516_spi_init
+};
+
+const uint32_t ad9516_default_config_len = 66;
+const struct ad9516_config ad9516_default_config[] = {
+	{0x0000,0x18}, // 16-bit instruction, MSB first, 3-wire SPI
+	{0x0004,0x00}, // reads back buffer registers
+	{0x0010,0x7C},
+	{0x0011,0x04}, // R divider LSBs, R = 4
+	{0x0012,0x00}, // R divider MSBs, R = 4
+	{0x0013,0x08}, // A counter, A = 8
+	{0x0014,0x09}, // B counter LSBs, B = 9
+	{0x0015,0x00}, // B counter MSBs, B = 9
+	{0x0016,0x04}, // Divide-by-8 (8/9 mode)
+	{0x0017,0x10}, // STATUS pin output:  Prescaler output
+	{0x0018,0x06},
+	{0x0019,0x80}, // R, A, B counters synchronous reset on SYNCB
+	{0x001A,0x00}, // LD pin output: Digital lock detect (high = lock, low = unlock)
+	{0x001B,0xA1}, // enables VCO, REF1 frequency monitor; REFMON pin output: REF1 clock
+	{0x001C,0x07}, // selects REF1; REF1, REF2 power on; differential reference mode
+	{0x001D,0x00},
+	{0x001E,0x00},
+	{0x00A0,0x01},
+	{0x00A1,0x00},
+	{0x00A2,0x00},
+	{0x00A3,0x01},
+	{0x00A4,0x00},
+	{0x00A5,0x00},
+	{0x00A6,0x01},
+	{0x00A7,0x00},
+	{0x00A8,0x00},
+	{0x00A9,0x01},
+	{0x00AA,0x00},
+	{0x00AB,0x00},
+	{0x00F0,0x08},
+	{0x00F1,0x08},
+	{0x00F2,0x08},
+	{0x00F3,0x08},
+	{0x00F4,0x08},
+	{0x00F5,0x08},
+	{0x0140,0x59},
+	{0x0141,0x5A},
+	{0x0142,0x5A},
+	{0x0143,0x42},
+	{0x0190,0x33},
+	{0x0191,0x40},
+	{0x0192,0x00},
+	{0x0193,0x33},
+	{0x0194,0x40},
+	{0x0195,0x00},
+	{0x0196,0x44},
+	{0x0197,0x40},
+	{0x0198,0x00},
+	{0x0199,0x99}, // divider 3.1, Low Cycles = 10, High Cycles = 10
+	{0x019A,0x00},
+	{0x019B,0x00}, // divider 3.1, Low Cycles = 1, High Cycles = 1
+	{0x019C,0x00},
+	{0x019D,0x00},
+//	{0x019E,0xFF},
+	{0x019E,0x11},
+	{0x019F,0x00},
+	{0x01A0,0x11},
+	{0x01A1,0x20},
+	{0x01A2,0x00},
+	{0x01A3,0x00},
+	{0x01E0,0x00},
+	{0x01E1,0x02},
+	{0x0230,0x00},
+	{0x0231,0x00},
+	{0x0232,0x01}, // Update all registers
+	{0x0018,0x07}, // initiate the VCO calibration
+	{0x0232,0x01}  // Update all registers
+};

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/src/dev_profile/dev_profile.h

@@ -0,0 +1,43 @@
+#ifndef DEV_PROFILE_H_
+#define DEV_PROFILE_H_
+
+#include <inttypes.h>
+#include "../app_config.h"
+#include "../parameters.h"
+#include "../adi_noos/include/spi.h"
+#include "../adi_noos/include/gpio.h"
+#include "../adi_noos/include/delay.h"
+#include "../adi_noos/include/irq.h"
+#include "../adi_noos/include/error.h"
+#include "../adi_noos/drivers/rf-transceiver/ad9361_reg/ad9361_reg.h"
+#include "../adi_noos/drivers/frequency/ad9516/ad9516.h"
+
+// Platform includes
+#include "../adi_noos/drivers/platform/spi_extra.h"
+#include "../adi_noos/drivers/platform/gpio_extra.h"
+#include "../adi_noos/drivers/platform/irq_extra.h"
+
+// AXI-Cores includes
+#include "../adi_noos/drivers/axi_core/spi_engine/spi_engine.h"
+
+// Declare in mian.c
+extern struct spi_engine_init_param spi_engine_param;
+extern struct xil_gpio_init_param xil_gpio_param;
+
+#define GPIO_PARAM	&xil_gpio_param
+#define SPI_PARAM	&spi_engine_param
+#define GPIO_OPS	&xil_gpio_ops
+#define SPI_OPS		&spi_eng_platform_ops
+
+extern struct ad9516_init_param ad9516_default_init_param;
+extern const struct ad9516_config ad9516_default_config[];
+extern const uint32_t ad9516_default_config_len;
+
+extern struct ad9361_reg_init_param ad9361_1_reg_default_init_param;
+extern struct ad9361_reg_init_param ad9361_2_reg_default_init_param;
+
+uint32_t ad9361_reg_config(struct ad9361_reg_dev *dev);
+uint32_t ad9361_1_reg_config(struct ad9361_reg_dev *dev);
+uint32_t ad9361_2_reg_config(struct ad9361_reg_dev *dev);
+
+#endif /* SRC_DEV_PROFILE_H_ */

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/src/lscript.ld

@@ -0,0 +1,216 @@
+/*******************************************************************/
+/*                                                                 */
+/* This file is automatically generated by linker script generator.*/
+/*                                                                 */
+/* Version: 2018.3                                                 */
+/*                                                                 */
+/* Copyright (c) 2010-2019 Xilinx, Inc.  All rights reserved.      */
+/*                                                                 */
+/* Description : MicroBlaze Linker Script                           */
+/*                                                                 */
+/*******************************************************************/
+
+_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x4000;
+_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x8000;
+
+/* Define Memories in the system */
+
+MEMORY
+{
+   microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem : ORIGIN = 0x50, LENGTH = 0x3FFB0
+}
+
+/* Specify the default entry point to the program */
+
+ENTRY(_start)
+
+/* Define the sections, and where they are mapped in memory */
+
+SECTIONS
+{
+.vectors.reset 0x0 : {
+   KEEP (*(.vectors.reset))
+} 
+
+.vectors.sw_exception 0x8 : {
+   KEEP (*(.vectors.sw_exception))
+} 
+
+.vectors.interrupt 0x10 : {
+   KEEP (*(.vectors.interrupt))
+} 
+
+.vectors.hw_exception 0x20 : {
+   KEEP (*(.vectors.hw_exception))
+} 
+
+.text : {
+   *(.text)
+   *(.text.*)
+   *(.gnu.linkonce.t.*)
+} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem
+
+.note.gnu.build-id : {
+   KEEP (*(.note.gnu.build-id))
+} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem
+
+.init : {
+   KEEP (*(.init))
+} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem
+
+.fini : {
+   KEEP (*(.fini))
+} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem
+
+.ctors : {
+   __CTOR_LIST__ = .;
+   ___CTORS_LIST___ = .;
+   KEEP (*crtbegin.o(.ctors))
+   KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
+   KEEP (*(SORT(.ctors.*)))
+   KEEP (*(.ctors))
+   __CTOR_END__ = .;
+   ___CTORS_END___ = .;
+} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem
+
+.dtors : {
+   __DTOR_LIST__ = .;
+   ___DTORS_LIST___ = .;
+   KEEP (*crtbegin.o(.dtors))
+   KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
+   KEEP (*(SORT(.dtors.*)))
+   KEEP (*(.dtors))
+   PROVIDE(__DTOR_END__ = .);
+   PROVIDE(___DTORS_END___ = .);
+} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem
+
+.rodata : {
+   __rodata_start = .;
+   *(.rodata)
+   *(.rodata.*)
+   *(.gnu.linkonce.r.*)
+   __rodata_end = .;
+} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem
+
+.sdata2 : {
+   . = ALIGN(8);
+   __sdata2_start = .;
+   *(.sdata2)
+   *(.sdata2.*)
+   *(.gnu.linkonce.s2.*)
+   . = ALIGN(8);
+   __sdata2_end = .;
+} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem
+
+.sbss2 : {
+   __sbss2_start = .;
+   *(.sbss2)
+   *(.sbss2.*)
+   *(.gnu.linkonce.sb2.*)
+   __sbss2_end = .;
+} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem
+
+.data : {
+   . = ALIGN(4);
+   __data_start = .;
+   *(.data)
+   *(.data.*)
+   *(.gnu.linkonce.d.*)
+   __data_end = .;
+} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem
+
+.got : {
+   *(.got)
+} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem
+
+.got1 : {
+   *(.got1)
+} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem
+
+.got2 : {
+   *(.got2)
+} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem
+
+.eh_frame : {
+   *(.eh_frame)
+} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem
+
+.jcr : {
+   *(.jcr)
+} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem
+
+.gcc_except_table : {
+   *(.gcc_except_table)
+} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem
+
+.sdata : {
+   . = ALIGN(8);
+   __sdata_start = .;
+   *(.sdata)
+   *(.sdata.*)
+   *(.gnu.linkonce.s.*)
+   __sdata_end = .;
+} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem
+
+.sbss (NOLOAD) : {
+   . = ALIGN(4);
+   __sbss_start = .;
+   *(.sbss)
+   *(.sbss.*)
+   *(.gnu.linkonce.sb.*)
+   . = ALIGN(8);
+   __sbss_end = .;
+} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem
+
+.tdata : {
+   __tdata_start = .;
+   *(.tdata)
+   *(.tdata.*)
+   *(.gnu.linkonce.td.*)
+   __tdata_end = .;
+} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem
+
+.tbss : {
+   __tbss_start = .;
+   *(.tbss)
+   *(.tbss.*)
+   *(.gnu.linkonce.tb.*)
+   __tbss_end = .;
+} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem
+
+.bss (NOLOAD) : {
+   . = ALIGN(4);
+   __bss_start = .;
+   *(.bss)
+   *(.bss.*)
+   *(.gnu.linkonce.b.*)
+   *(COMMON)
+   . = ALIGN(4);
+   __bss_end = .;
+} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem
+
+_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
+
+_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
+
+/* Generate Stack and Heap definitions */
+
+.heap (NOLOAD) : {
+   . = ALIGN(8);
+   _heap = .;
+   _heap_start = .;
+   . += _HEAP_SIZE;
+   _heap_end = .;
+} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem
+
+.stack (NOLOAD) : {
+   _stack_end = .;
+   . += _STACK_SIZE;
+   . = ALIGN(8);
+   _stack = .;
+   __stack = _stack;
+} > microblaze_ps_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_ps_local_memory_dlmb_bram_if_cntlr_Mem
+
+_end = .;
+}
+

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/src/main.c

@@ -0,0 +1,422 @@
+/***************************************************************************//**
+ *   @file   ad9361/src/main.c
+ *   @brief  Implementation of Main Function.
+ *   @author DBogdan ([email protected])
+********************************************************************************
+ * Copyright 2013(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+// Platform includes
+#include <inttypes.h>
+#include "xparameters.h"
+#include "xil_assert.h"
+#include "xgpio.h"
+// ADI Drivers
+#include "app_config.h"
+#include "dev_profile/dev_profile.h"
+#include "adi_noos/drivers/axi_core/spi_engine/spi_engine.h"
+// AXI-Cores includes
+#include "adi_noos/drivers/axi_core/spi_engine/spi_engine.h"
+#include "adi_noos/drivers/platform/gpio_extra.h"
+
+/******************************************************************************/
+/************************ Variables Definitions *******************************/
+/******************************************************************************/
+
+struct spi_engine_init_param spi_engine_param = {
+	.ref_clk_hz = SPI_ENGINE_REF_CLK,
+	.type = SPI_ENGINE,
+	.spi_engine_baseaddr = SPI_ENGINE_BASEADDR,
+	.cs_delay = SPI_ENGINE_CS_DELAY,
+	.data_width = SPI_ENGINE_DATA_WIDTH
+};
+
+struct xil_gpio_init_param xil_gpio_param = {
+	.type = GPIO_PS,
+	.device_id = GPIO_DEVICE_ID
+};
+
+struct ad9516_dev *ad9516_inst;
+struct ad9361_reg_dev *ad9361_1_reg_inst;
+struct ad9361_reg_dev *ad9361_2_reg_inst;
+struct ad9361_rf_phy *ad9361_phy;
+
+XGpio Gpio;
+
+int XGpio_WritePin(XGpio *InstPtr, unsigned Channel, u32 Pin, u8 Value);
+int Hardware_SwitchFreq(struct ad9361_reg_dev *dev, ad9361TxFreq freq);
+
+/***************************************************************************//**
+ * @brief main
+*******************************************************************************/
+int main(void)
+{
+	int32_t Status;
+	Status = XGpio_Initialize(&Gpio, GPIO_DEVICE_ID);
+	if (Status != XST_SUCCESS)
+	{
+		return XST_FAILURE;
+	}
+	XGpio_SetDataDirection(&Gpio, GPIO_BANK_OUT, 0x00000000); // Bank 1 output
+	XGpio_SetDataDirection(&Gpio, GPIO_BANK_IN, 0xFFFFFFFF); // Bank 0 input
+
+	XGpio_DiscreteWrite(&Gpio, GPIO_BANK_OUT, 0x00000000);
+
+	/**********************************************************/
+	/****************** AD9516 Configuration ******************/
+	/**********************************************************/
+	Status = ad9516_init(&ad9516_inst, &ad9516_default_init_param);
+	XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9516_POWEDOWN_B, 1);
+	XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9516_SYNC_B, 1);
+	XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9516_RESET_B, 0);
+	mdelay(200);
+	XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9516_RESET_B, 1);
+	for(int i = 0; i < ad9516_default_config_len; i++){
+		Status = ad9516_write(ad9516_inst, ad9516_default_config[i].addr, ad9516_default_config[i].value);
+		if (ad9516_default_config[i].addr == 0x0000){
+			mdelay(500);
+		}
+	}
+
+	uint8_t rd_back;
+	Status = ad9516_read(ad9516_inst, 0x0003, &rd_back);
+	do
+	{
+		Status = ad9516_read(ad9516_inst, 0x001F, &rd_back);
+	}
+	while((rd_back & 0x01) != 0x01);
+
+	/**********************************************************/
+	/***************** AD9361-1 Configuration *****************/
+	/**********************************************************/
+	ad9361_reg_init(&ad9361_1_reg_inst, &ad9361_1_reg_default_init_param);
+
+	XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_1_RESET_B, 0);
+	mdelay(200);
+	XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_1_RESET_B, 1);
+
+	XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_1_ENABLE, 0);
+	ad9361_reg_config(ad9361_1_reg_inst);
+	XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_1_ENABLE, 1);
+
+	/**********************************************************/
+	/***************** AD9361-2 Configuration *****************/
+	/**********************************************************/
+	ad9361_reg_init(&ad9361_2_reg_inst, &ad9361_2_reg_default_init_param);
+
+	XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_2_RESET_B, 0);
+	mdelay(200);
+	XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_2_RESET_B, 1);
+
+	XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_2_ENABLE, 0);
+	ad9361_reg_config(ad9361_2_reg_inst);
+	XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_2_ENABLE, 1);
+
+	/**********************************************************/
+	/******* AD9361 Baseband Multichip Synchronization ********/
+	/**********************************************************/
+	// sync clock output
+	XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9516_SYNC_B, 0);
+	mdelay(500);
+	XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9516_SYNC_B, 1);
+
+	// SYNC BBPLL and DIGITAL SAMPLING CLOCKS
+	ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x0D);    // MCS RF Enable; MCS BBPLL Enable; MCS BB Enable
+	ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x0D);
+	ad9361_reg_write(ad9361_1_reg_inst, 0x0047, 0x80);    // MCS refclk Scale Enable
+	ad9361_reg_write(ad9361_2_reg_inst, 0x0047, 0x80);
+	XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_SYNC, 0);
+	mdelay(20);
+	XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_SYNC, 1); // Input a rising-edge pulse to the SYNC_IN pin
+	mdelay(500);
+	XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_SYNC, 0);
+	mdelay(2000);
+	ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x0B);    // MCS RF Enable; MCS Digital CLK Enable ; MCS BB Enable
+	ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x0B);
+	XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_SYNC, 1); // Input another rising-edge pulse to the SYNC_IN pin
+	mdelay(500);
+	XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_SYNC, 0);
+	ad9361_reg_write(ad9361_1_reg_inst, 0x0001, 0x08);    // clear MCS bits
+	ad9361_reg_write(ad9361_2_reg_inst, 0x0001, 0x08);
+
+	XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_RX_FIFO_RST, 0);
+	mdelay(20);
+	XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_RX_FIFO_RST, 1);
+	mdelay(20);
+	XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_RX_FIFO_RST, 0);
+
+	/**********************************************************/
+	/********* AD9361 Multichip Rx Phase Calibration **********/
+	/**********************************************************/
+	// switch to lower frequency
+	Status = Hardware_SwitchFreq(ad9361_1_reg_inst, TX_FREQ_126);
+	XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_TX_SW, 1);
+	mdelay(20);
+
+	// switch rx channel
+	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x30);
+	Status = ad9361_reg_write(ad9361_2_reg_inst, 0x0004, 0x30);
+
+	// enable dual ad9361 tx channels
+	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0002, 0xE4);	// Setup Tx Digital Filters/ Channels
+
+#ifdef DL814_BOARD_V3
+	// switch ad9361 tx channel
+    Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x70);	// Select Rx input pin(A,B,C)/ Tx out pin (A,B)
+    mdelay(20);
+#endif
+
+	// begin to calibrate the 1st ad9361
+	XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_1_CAL_START, 0);
+	XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_1_CAL_START, 1);
+	mdelay(1);
+	XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_1_CAL_START, 0);
+
+	// read calibration status
+	int32_t time_out_cnt = 0;
+	do{
+		mdelay(1);// Wait 1ms
+		time_out_cnt++;
+	}while((((XGpio_DiscreteRead(&Gpio, GPIO_BANK_IN) >> AD9361_1_CAL_DONE) & 0x00000001) == 0) && time_out_cnt <= TIMEOUT_TH);
+
+	if (time_out_cnt == TIMEOUT_TH){
+		return FAILURE;
+	}
+
+#ifdef DL814_BOARD_V2
+	// switch ad9361 tx channel
+    Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x70);	// Select Rx input pin(A,B,C)/ Tx out pin (A,B)
+    mdelay(20);
+#endif
+
+	// begin to calibrate the 2nd ad9361
+	XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_2_CAL_START, 1);
+	mdelay(1);
+	XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_2_CAL_START, 0);
+
+	// read calibration status
+	time_out_cnt = 0;
+	do{
+		mdelay(1);// Wait 1ms
+		time_out_cnt++;
+	}while((((XGpio_DiscreteRead(&Gpio, GPIO_BANK_IN) >> AD9361_2_CAL_DONE) & 0x00000001) == 0) && time_out_cnt <= TIMEOUT_TH);
+
+	if (time_out_cnt == TIMEOUT_TH){
+		return FAILURE;
+	}
+
+	// enable single ad9361 tx channels
+	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0002, 0xA4);	// Setup Tx Digital Filters/ Channels
+
+	// switch ad9361 tx & rx channel
+	Status = ad9361_reg_write(ad9361_1_reg_inst, 0x0004, 0x03);
+	Status = ad9361_reg_write(ad9361_2_reg_inst, 0x0004, 0x03);
+
+    // switch to higher frequency
+	Status = Hardware_SwitchFreq(ad9361_1_reg_inst, TX_FREQ_4125);
+	XGpio_WritePin(&Gpio, GPIO_BANK_OUT, AD9361_TX_SW, 0);
+
+	print("Done.\n");
+
+	return 0;
+}
+
+int Hardware_SwitchFreq(struct ad9361_reg_dev *dev, ad9361TxFreq freq){
+	int32_t status = 0;
+	uint8_t value = 0;
+	int32_t time_out_cnt = 0;
+
+	switch(freq){
+		case TX_FREQ_125: {
+			//************************************************************
+			// Setup Tx Frequency-Dependent Syntheisizer Registers
+			//************************************************************
+			status = ad9361_reg_write(dev, 0x027A, 0x4A);	// Set VCO Output level[3:0]
+			status = ad9361_reg_write(dev, 0x0279, 0xC1);	// Set Init ALC Value[3:0] and VCO Varactor[3:0]
+			status = ad9361_reg_write(dev, 0x0282, 0x0E);	// Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
+			status = ad9361_reg_write(dev, 0x0278, 0x78);	// Set VCO Cal Offset[3:0]
+			status = ad9361_reg_write(dev, 0x0285, 0x00);	// Set VCO Cal Ref Tcf[2:0]
+			status = ad9361_reg_write(dev, 0x0291, 0x0B);	// Set VCO Varactor Reference[3:0]
+			status = ad9361_reg_write(dev, 0x0290, 0x70);	// Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
+			status = ad9361_reg_write(dev, 0x027B, 0x94);	// Set Synth Loop Filter charge pump current (Icp)
+			status = ad9361_reg_write(dev, 0x027E, 0xF4);	// Set Synth Loop Filter C2 and C1
+			status = ad9361_reg_write(dev, 0x027F, 0xDF);	// Set Synth Loop Filter  R1 and C3
+			status = ad9361_reg_write(dev, 0x0280, 0x0A);	// Set Synth Loop Filter R3
+
+			//************************************************************
+			// Write Tx Frequency Words
+			//************************************************************
+			status = ad9361_reg_write(dev, 0x0273, 0x00);	// Write Tx Synth Fractional Freq Word[7:0]
+			status = ad9361_reg_write(dev, 0x0274, 0x00);	// Write Tx Synth Fractional Freq Word[15:8]
+			status = ad9361_reg_write(dev, 0x0275, 0x00);	// Write Tx Synth Fractional Freq Word[22:16]
+			status = ad9361_reg_write(dev, 0x0272, 0x00);	// Write Tx Synth Integer Freq Word[10:8]
+			status = ad9361_reg_write(dev, 0x0271, 0xA0);	// Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)
+			status = ad9361_reg_write(dev, 0x0005, 0x57);	// Set LO divider setting
+
+			//************************************************************
+			// Tx Quadrature Calibration Settings
+			//************************************************************
+			status = ad9361_reg_write(dev, 0x00A0, 0x75);	// Set TxQuadcal NCO frequency
+			status = ad9361_reg_write(dev, 0x00A3, 0xC0);	// Set TxQuadcal NCO frequency (Only update bits [7:6])
+			status = ad9361_reg_write(dev, 0x00A1, 0x7B);	// Tx Quad Cal Configuration, Phase and Gain Cal Enable
+			status = ad9361_reg_write(dev, 0x00A9, 0xFF);	// Set Tx Quad Cal Count
+			status = ad9361_reg_write(dev, 0x00A2, 0x7F);	// Set Tx Quad Cal Kexp
+			status = ad9361_reg_write(dev, 0x00A5, 0x01);	// Set Tx Quad Cal Magnitude Threshhold
+			status = ad9361_reg_write(dev, 0x00A6, 0x01);	// Set Tx Quad Cal Magnitude Threshhold
+			status = ad9361_reg_write(dev, 0x00AA, 0x22);	// Set Tx Quad Cal Gain Table index
+			status = ad9361_reg_write(dev, 0x00A4, 0xF0);	// Set Tx Quad Cal Settle Count
+			status = ad9361_reg_write(dev, 0x00AE, 0x00);	// Set Tx Quad Cal LPF Gain index incase Split table mode used
+
+			status = ad9361_reg_write(dev, 0x0169, 0xC0);	// Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration
+			status = ad9361_reg_write(dev, 0x0016, 0x10);	// Start Tx Quad cal
+
+			break;
+		}
+		case TX_FREQ_126: {
+			//************************************************************
+			// Setup Tx Frequency-Dependent Syntheisizer Registers
+			//************************************************************
+			status = ad9361_reg_write(dev, 0x027A, 0x4A);	// Set VCO Output level[3:0]
+			status = ad9361_reg_write(dev, 0x0279, 0xC1);	// Set Init ALC Value[3:0] and VCO Varactor[3:0]
+			status = ad9361_reg_write(dev, 0x0282, 0x0E);	// Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
+			status = ad9361_reg_write(dev, 0x0278, 0x78);	// Set VCO Cal Offset[3:0]
+			status = ad9361_reg_write(dev, 0x0285, 0x00);	// Set VCO Cal Ref Tcf[2:0]
+			status = ad9361_reg_write(dev, 0x0291, 0x0B);	// Set VCO Varactor Reference[3:0]
+			status = ad9361_reg_write(dev, 0x0290, 0x70);	// Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
+			status = ad9361_reg_write(dev, 0x027B, 0x93);	// Set Synth Loop Filter charge pump current (Icp)
+			status = ad9361_reg_write(dev, 0x027E, 0xF4);	// Set Synth Loop Filter C2 and C1
+			status = ad9361_reg_write(dev, 0x027F, 0xDF);	// Set Synth Loop Filter  R1 and C3
+			status = ad9361_reg_write(dev, 0x0280, 0x0A);	// Set Synth Loop Filter R3
+
+			//************************************************************
+			// Write Tx Frequency Words
+			//************************************************************
+			status = ad9361_reg_write(dev, 0x0273, 0x06);	// Write Tx Synth Fractional Freq Word[7:0]
+			status = ad9361_reg_write(dev, 0x0274, 0xD7);	// Write Tx Synth Fractional Freq Word[15:8]
+			status = ad9361_reg_write(dev, 0x0275, 0x23);	// Write Tx Synth Fractional Freq Word[22:16]
+			status = ad9361_reg_write(dev, 0x0272, 0x00);	// Write Tx Synth Integer Freq Word[10:8]
+			status = ad9361_reg_write(dev, 0x0271, 0xA1);	// Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)
+			status = ad9361_reg_write(dev, 0x0005, 0x57);	// Set LO divider setting
+
+			//************************************************************
+			// Tx Quadrature Calibration Settings
+			//************************************************************
+			status = ad9361_reg_write(dev, 0x00A0, 0x75);	// Set TxQuadcal NCO frequency
+			status = ad9361_reg_write(dev, 0x00A3, 0xC0);	// Set TxQuadcal NCO frequency (Only update bits [7:6])
+			status = ad9361_reg_write(dev, 0x00A1, 0x7B);	// Tx Quad Cal Configuration, Phase and Gain Cal Enable
+			status = ad9361_reg_write(dev, 0x00A9, 0xFF);	// Set Tx Quad Cal Count
+			status = ad9361_reg_write(dev, 0x00A2, 0x7F);	// Set Tx Quad Cal Kexp
+			status = ad9361_reg_write(dev, 0x00A5, 0x01);	// Set Tx Quad Cal Magnitude Threshhold
+			status = ad9361_reg_write(dev, 0x00A6, 0x01);	// Set Tx Quad Cal Magnitude Threshhold
+			status = ad9361_reg_write(dev, 0x00AA, 0x22);	// Set Tx Quad Cal Gain Table index
+			status = ad9361_reg_write(dev, 0x00A4, 0xF0);	// Set Tx Quad Cal Settle Count
+			status = ad9361_reg_write(dev, 0x00AE, 0x00);	// Set Tx Quad Cal LPF Gain index incase Split table mode used
+
+			status = ad9361_reg_write(dev, 0x0169, 0xC0);	// Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration
+			status = ad9361_reg_write(dev, 0x0016, 0x10);	// Start Tx Quad cal
+
+			break;
+		}
+		case TX_FREQ_4125: {
+			//************************************************************
+			// Setup Tx Frequency-Dependent Syntheisizer Registers
+			//************************************************************
+			status = ad9361_reg_write(dev, 0x027A, 0x4A);	// Set VCO Output level[3:0]
+			status = ad9361_reg_write(dev, 0x0279, 0xC1);	// Set Init ALC Value[3:0] and VCO Varactor[3:0]
+			status = ad9361_reg_write(dev, 0x0282, 0x0E);	// Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]
+			status = ad9361_reg_write(dev, 0x0278, 0x78);	// Set VCO Cal Offset[3:0]
+			status = ad9361_reg_write(dev, 0x0285, 0x00);	// Set VCO Cal Ref Tcf[2:0]
+			status = ad9361_reg_write(dev, 0x0291, 0x0B);	// Set VCO Varactor Reference[3:0]
+			status = ad9361_reg_write(dev, 0x0290, 0x70);	// Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]
+			status = ad9361_reg_write(dev, 0x027B, 0x93);	// Set Synth Loop Filter charge pump current (Icp)
+			status = ad9361_reg_write(dev, 0x027E, 0xF4);	// Set Synth Loop Filter C2 and C1
+			status = ad9361_reg_write(dev, 0x027F, 0xDF);	// Set Synth Loop Filter  R1 and C3
+			status = ad9361_reg_write(dev, 0x0280, 0x0A);	// Set Synth Loop Filter R3
+
+			//************************************************************
+			// Write Rx Frequency Words
+			//************************************************************
+			status = ad9361_reg_write(dev, 0x0273, 0x00);	// Write Tx Synth Fractional Freq Word[7:0]
+			status = ad9361_reg_write(dev, 0x0274, 0x00);	// Write Tx Synth Fractional Freq Word[15:8]
+			status = ad9361_reg_write(dev, 0x0275, 0x00);	// Write Tx Synth Fractional Freq Word[22:16]
+			status = ad9361_reg_write(dev, 0x0272, 0x00);	// Write Tx Synth Integer Freq Word[10:8]
+			status = ad9361_reg_write(dev, 0x0271, 0xA5);	// Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)
+			status = ad9361_reg_write(dev, 0x0005, 0x07);	// Set LO divider setting
+
+			//************************************************************
+			// Tx Quadrature Calibration Settings
+			//************************************************************
+			status = ad9361_reg_write(dev, 0x00A0, 0x75);	// Set TxQuadcal NCO frequency
+			status = ad9361_reg_write(dev, 0x00A3, 0xC0);	// Set TxQuadcal NCO frequency (Only update bits [7:6])
+			status = ad9361_reg_write(dev, 0x00A1, 0x7B);	// Tx Quad Cal Configuration, Phase and Gain Cal Enable
+			status = ad9361_reg_write(dev, 0x00A9, 0xFF);	// Set Tx Quad Cal Count
+			status = ad9361_reg_write(dev, 0x00A2, 0x7F);	// Set Tx Quad Cal Kexp
+			status = ad9361_reg_write(dev, 0x00A5, 0x01);	// Set Tx Quad Cal Magnitude Threshhold
+			status = ad9361_reg_write(dev, 0x00A6, 0x01);	// Set Tx Quad Cal Magnitude Threshhold
+			status = ad9361_reg_write(dev, 0x00AA, 0x28);	// Set Tx Quad Cal Gain Table index
+			status = ad9361_reg_write(dev, 0x00A4, 0xF0);	// Set Tx Quad Cal Settle Count
+			status = ad9361_reg_write(dev, 0x00AE, 0x04);	// Set Tx Quad Cal LPF Gain index incase Split table mode used
+
+			status = ad9361_reg_write(dev, 0x0169, 0xC0);	// Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration
+			status = ad9361_reg_write(dev, 0x0016, 0x10);	// Start Tx Quad cal
+
+			break;
+		}
+
+		// Wait for cal to complete (Done when 0x016[4]==0)
+		time_out_cnt = 0;
+		do{
+			status |= ad9361_reg_read(dev, 0x0016, &value);
+			mdelay(1);// Wait 1ms
+			time_out_cnt++;
+		} while((value & 0x10) != 0x00 && time_out_cnt <= TIMEOUT_TH);
+	}
+
+	return status;
+}
+int XGpio_WritePin(XGpio *InstPtr, unsigned Channel, u32 Pin, u8 Value){
+	Xil_AssertNonvoid(Pin <= 31 && Pin >=0 );
+	Xil_AssertNonvoid(InstPtr != NULL);
+	Xil_AssertNonvoid(InstPtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((Channel == 1) ||
+				((Channel == 2) && (InstPtr->IsDual == TRUE)));
+	u32 CurrValue = XGpio_DiscreteRead(InstPtr, Channel);
+	CurrValue = (Value == 0)? (CurrValue & (~(0x00000001 << Pin))) : (CurrValue | (0x00000001 << Pin));
+	XGpio_DiscreteWrite(InstPtr, Channel, CurrValue);
+	return XST_SUCCESS;
+}
+

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m/src/parameters.h

@@ -0,0 +1,137 @@
+/***************************************************************************//**
+ *   @file   ad9361/src/parameters.h
+ *   @brief  Parameters Definitions.
+ *   @author DBogdan ([email protected])
+********************************************************************************
+ * Copyright 2013(c) Analog Devices, Inc.
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *  - Neither the name of Analog Devices, Inc. nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *  - The use of this software may or may not infringe the patent rights
+ *    of one or more patent holders.  This license does not release you
+ *    from the requirement that you obtain separate licenses from these
+ *    patent holders to use this software.
+ *  - Use of the software either in source or binary form, must be run
+ *    on or directly connected to an Analog Devices Inc. component.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************/
+#ifndef __PARAMETERS_H__
+#define __PARAMETERS_H__
+
+/******************************************************************************/
+/***************************** Include Files **********************************/
+/******************************************************************************/
+#include <xparameters.h>
+#include "app_config.h"
+
+/******************************************************************************/
+/********************** Macros and Constants Definitions **********************/
+/******************************************************************************/
+#ifdef XILINX_PLATFORM
+
+#define FCLK_CLK0_HZ				25000000
+
+#define INTC_DEVICE_ID				XPAR_SCUGIC_SINGLE_DEVICE_ID
+
+#define GPIO_DEVICE_ID				XPAR_AXI_GPIO_DEVICE_ID
+#define GPIO_INPUT 					0
+#define GPIO_OUTPUT 				1
+#define GPIO_DISABLE 				0
+#define GPIO_ENABLE 				1
+
+#define AD9516_POWEDOWN_B			0
+#define AD9516_RESET_B				1
+#define AD9516_SYNC_B				2
+#define AD9361_1_TXNRX				3
+#define AD9361_1_ENABLE				4
+#define AD9361_1_EN_AGC				5
+#define AD9361_1_RESET_B			6
+#define AD9361_1_CTRL_IN_0			7
+#define AD9361_1_CTRL_IN_1			8
+#define AD9361_1_CTRL_IN_2			9
+#define AD9361_1_CTRL_IN_3			10
+#define AD9361_2_TXNRX				11
+#define AD9361_2_ENABLE				12
+#define AD9361_2_EN_AGC				13
+#define AD9361_2_RESET_B			14
+#define AD9361_2_CTRL_IN_0			15
+#define AD9361_2_CTRL_IN_1			16
+#define AD9361_2_CTRL_IN_2			17
+#define AD9361_2_CTRL_IN_3			18
+#define AD9361_SYNC					19
+#define AD9361_RX_FIFO_RST			20
+#define AD9361_1_CAL_START			21
+#define AD9361_2_CAL_START			22
+#define AD9361_RECAL				23
+#define AD9361_TX_SW				24
+
+#define AD9361_1_CTRL_OUT_0			0
+#define AD9361_1_CTRL_OUT_1			1
+#define AD9361_1_CTRL_OUT_2			2
+#define AD9361_1_CTRL_OUT_3			3
+#define AD9361_1_CTRL_OUT_4			4
+#define AD9361_1_CTRL_OUT_5			5
+#define AD9361_1_CTRL_OUT_6			6
+#define AD9361_1_CTRL_OUT_7			7
+#define AD9361_2_CTRL_OUT_0			8
+#define AD9361_2_CTRL_OUT_1			9
+#define AD9361_2_CTRL_OUT_2			10
+#define AD9361_2_CTRL_OUT_3			11
+#define AD9361_2_CTRL_OUT_4			12
+#define AD9361_2_CTRL_OUT_5			13
+#define AD9361_2_CTRL_OUT_6			14
+#define AD9361_2_CTRL_OUT_7			15
+#define AD9516_REFMON				16
+#define AD9516_LOCKDETECT			17
+#define AD9516_STARUS				18
+#define AD9361_1_CAL_DONE			19
+#define AD9361_2_CAL_DONE			20
+#define AD9361_CAL_RESULT			21
+
+#define GPIO_BANK_OUT				1
+#define GPIO_BANK_IN				2
+
+#define SPI_DEVICE_ID				0
+#define SPI_ENGINE_REF_CLK          FCLK_CLK0_HZ
+#define SPI_ENGINE_MAX_SPEED		5000000
+#define SPI_ENGINE_BASEADDR			XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR
+#define SPI_ENGINE_DATA_WIDTH       8
+#define SPI_ENGINE_CS_DELAY			3
+#define SPI_CS_AD9516           	0x00
+#define SPI_CS_AD9361_1             0x01
+#define SPI_CS_AD9361_2             0x02
+
+#define DL814_BOARD_V3
+#define TIMEOUT_TH	2000
+
+typedef enum
+{
+	TX_FREQ_125,
+	TX_FREQ_126,
+	TX_FREQ_4125
+} ad9361TxFreq;
+
+#endif
+
+#endif // __PARAMETERS_H__

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m_system/.cproject

@@ -0,0 +1,108 @@
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+    	
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+        		
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+                				
+                <externalSettings/>
+                				
+                <extensions>
+                    					
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+            </storageModule>
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+                <configuration artifactName="${ProjName}" buildProperties="" description="" id="com.xilinx.sdx.system.managedbuilder.debugConfiguration.447805480" name="Debug" parent="com.xilinx.sdx.system.managedbuilder.debugConfiguration">
+                    					
+                    <folderInfo id="com.xilinx.sdx.system.managedbuilder.debugConfiguration.447805480." name="/" resourcePath="">
+                        						
+                        <toolChain id="com.xilinx.sdx.system.managedbuilder.debug.toolChain.1588957857" name="System Toolchain" superClass="com.xilinx.sdx.system.managedbuilder.debug.toolChain">
+                            							
+                            <targetPlatform id="com.xilinx.sdx.system.managedbuilder.debugConfiguration.447805480..612211455" name=""/>
+                            							
+                            <builder buildPath="${workspace_loc:/dl814_k7_48m_system}/Debug" enableAutoBuild="true" id="com.xilinx.sdx.system.managedbuilder.systemBuilder.331494363" managedBuildOn="true" name="System Project Builder.Debug" superClass="com.xilinx.sdx.system.managedbuilder.systemBuilder"/>
+                            							
+                            <tool id="com.xilinx.sdx.system.managedbuilder.toolchain.cfjoinTool.181527336" name="System Builder" superClass="com.xilinx.sdx.system.managedbuilder.toolchain.cfjoinTool"/>
+                            						
+                        </toolChain>
+                        					
+                    </folderInfo>
+                    				
+                </configuration>
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+            </storageModule>
+            			
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+            		
+        </cconfiguration>
+        		
+        <cconfiguration id="com.xilinx.sdx.system.managedbuilder.releaseConfiguration.248830259">
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+            <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.xilinx.sdx.system.managedbuilder.releaseConfiguration.248830259" moduleId="org.eclipse.cdt.core.settings" name="Release">
+                				
+                <externalSettings/>
+                				
+                <extensions>
+                    					
+                    <extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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+                    <extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
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+                			
+            </storageModule>
+            			
+            <storageModule moduleId="cdtBuildSystem" version="4.0.0">
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+                    					
+                    <folderInfo id="com.xilinx.sdx.system.managedbuilder.releaseConfiguration.248830259." name="/" resourcePath="">
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+                        <toolChain id="com.xilinx.sdx.system.managedbuilder.release.toolChain.170829108" name="System Toolchain" superClass="com.xilinx.sdx.system.managedbuilder.release.toolChain">
+                            							
+                            <targetPlatform id="com.xilinx.sdx.system.managedbuilder.releaseConfiguration.248830259..873478928" name=""/>
+                            							
+                            <builder buildPath="${workspace_loc:/dl814_k7_48m_system}/Release" enableAutoBuild="true" id="com.xilinx.sdx.system.managedbuilder.systemBuilder.1087445966" managedBuildOn="true" name="System Project Builder.Release" superClass="com.xilinx.sdx.system.managedbuilder.systemBuilder"/>
+                            							
+                            <tool id="com.xilinx.sdx.system.managedbuilder.toolchain.cfjoinTool.1352342409" name="System Builder" superClass="com.xilinx.sdx.system.managedbuilder.toolchain.cfjoinTool"/>
+                            						
+                        </toolChain>
+                        					
+                    </folderInfo>
+                    				
+                </configuration>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+            		
+        </cconfiguration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+    	
+    <storageModule moduleId="cdtBuildSystem" version="4.0.0">
+        		
+        <project id="dl814_k7_48m_system.com.xilinx.sdx.system.managedbuilder.projectType.26280302" name="Vitis Embedded System Project" projectType="com.xilinx.sdx.system.managedbuilder.projectType"/>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="scannerConfiguration">
+        		
+        <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="refreshScope"/>
+    
+</cproject>

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m_system/.gitignore

@@ -0,0 +1,2 @@
+/Debug/
+/Release/

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m_system/.project

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+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>dl814_k7_48m_system</name>
+	<comment></comment>
+	<projects>
+		<project>dl814_k7_48m</project>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>com.xilinx.sdx.system.core.embedded</nature>
+		<nature>com.xilinx.sdx.system.systemprojectnature</nature>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.core.ccnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+</projectDescription>

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_48m_system/dl814_k7_48m_system.sprj

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+<?xml version="1.0" encoding="ASCII"?>
+<systemproject:SystemProject xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:sdsproject="http://www.xilinx.com/sdsproject" xmlns:systemproject="http://www.xilinx.com/systemproject" name="dl814_k7_48m_system" platform="/home/josh/Workspace/vivado/vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/export/dl814_k7_platform/dl814_k7_platform.xpfm" platformUID="xilinx:::0.0(custom)" sysConfig="dl814_k7_platform" runtime="C/C++" rootFSLocation="" linuxImage="" sysroot="">
+  <configuration name="Debug" id="com.xilinx.sdx.system.managedbuilder.debugConfiguration.447805480">
+    <configBuildOptions xsi:type="systemproject:SystemOptions">
+      <applications name="dl814_k7_48m" domainName="standalone_domain" domainPrettyName="standalone on microblaze_ps" appBuildConfig="Debug"/>
+      <options xsi:type="sdsproject:Option" gensdcard="true" dmclkid="0"/>
+    </configBuildOptions>
+    <lastBuildOptions xsi:type="systemproject:SystemOptions">
+      <applications name="dl814_k7_48m" domainName="standalone_domain" domainPrettyName="standalone on microblaze_ps" appBuildConfig="Debug"/>
+      <options xsi:type="sdsproject:Option" gensdcard="true" dmclkid="0"/>
+    </lastBuildOptions>
+  </configuration>
+  <configuration name="Release" id="com.xilinx.sdx.system.managedbuilder.releaseConfiguration.248830259">
+    <configBuildOptions xsi:type="systemproject:SystemOptions">
+      <applications name="dl814_k7_48m" domainName="standalone_domain" domainPrettyName="standalone on microblaze_ps" appBuildConfig="Release"/>
+      <options xsi:type="sdsproject:Option" gensdcard="true" dmclkid="0"/>
+    </configBuildOptions>
+  </configuration>
+</systemproject:SystemProject>

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/.cproject

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+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.settings">
+        		
+        <cconfiguration id="org.eclipse.cdt.core.default.config.2069594811">
+            			
+            <storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.2069594811" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
+                				
+                <externalSettings/>
+                				
+                <extensions/>
+                			
+            </storageModule>
+            			
+            <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+            		
+        </cconfiguration>
+        	
+    </storageModule>
+    	
+    <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+    
+</cproject>

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/.gitignore

@@ -0,0 +1,3 @@
+/export/
+*.o
+*.d

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/.project

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+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>dl814_k7_platform</name>
+	<comment>Created by Vitis v2023.2</comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.xilinx.sdx.scw.PlatformProjectBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>com.xilinx.sdx.scw.platformProject</nature>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+	</natures>
+</projectDescription>

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/hw/system_top.bit

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+version https://git-lfs.github.com/spec/v1
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+size 9326271

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/hw/system_top.mmi

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+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- SW Build 4081461 on Thu Dec 14 12:22:04 MST 2023                  -->
+<!--                                                                         -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
+<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Dec 14 2023                                                             -->
+<!--                                                                             -->
+<!-- This file is generated by the software with the Tcl write_mem_info command. -->
+<!-- Do not edit this file.                                                      -->
+
+<MemInfo Version="1" Minor="9">
+  <Processor Endianness="Little" InstPath="u_system_bd_wrapper/system_bd_i/microblaze_ps">
+    <AddressSpace Name="u_system_bd_wrapper_system_bd_i_microblaze_ps.u_system_bd_wrapper_system_bd_i_microblaze_ps_local_memory_dlmb_bram_if_cntlr" Begin="0" End="262143">
+      <AddressSpaceRange Name="u_system_bd_wrapper_system_bd_i_microblaze_ps.u_system_bd_wrapper_system_bd_i_microblaze_ps_local_memory_dlmb_bram_if_cntlr" Begin="0" End="262143" CoreMemory_Width="0" MemoryType="RAM_SP" MemoryConfiguration="">
+        <BusBlock>
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+            <BitLayout pattern=""/>
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+          </BitLane>
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+            <AddressRange Begin="0" End="32767"/>
+            <BitLayout pattern=""/>
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+          </BitLane>
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+          </BitLane>
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+            <Parity ON="false" NumBits="0"/>
+          </BitLane>
+          <BitLane MemType="RAMB36" Placement="X0Y64" Read_Width="0" SLR_INDEX="-1">
+            <DataWidth MSB="23" LSB="23"/>
+            <AddressRange Begin="32768" End="65535"/>
+            <BitLayout pattern=""/>
+            <Parity ON="false" NumBits="0"/>
+          </BitLane>
+          <BitLane MemType="RAMB36" Placement="X2Y51" Read_Width="0" SLR_INDEX="-1">
+            <DataWidth MSB="22" LSB="22"/>
+            <AddressRange Begin="32768" End="65535"/>
+            <BitLayout pattern=""/>
+            <Parity ON="false" NumBits="0"/>
+          </BitLane>
+          <BitLane MemType="RAMB36" Placement="X0Y41" Read_Width="0" SLR_INDEX="-1">
+            <DataWidth MSB="21" LSB="21"/>
+            <AddressRange Begin="32768" End="65535"/>
+            <BitLayout pattern=""/>
+            <Parity ON="false" NumBits="0"/>
+          </BitLane>
+          <BitLane MemType="RAMB36" Placement="X3Y65" Read_Width="0" SLR_INDEX="-1">
+            <DataWidth MSB="20" LSB="20"/>
+            <AddressRange Begin="32768" End="65535"/>
+            <BitLayout pattern=""/>
+            <Parity ON="false" NumBits="0"/>
+          </BitLane>
+          <BitLane MemType="RAMB36" Placement="X0Y47" Read_Width="0" SLR_INDEX="-1">
+            <DataWidth MSB="19" LSB="19"/>
+            <AddressRange Begin="32768" End="65535"/>
+            <BitLayout pattern=""/>
+            <Parity ON="false" NumBits="0"/>
+          </BitLane>
+          <BitLane MemType="RAMB36" Placement="X4Y63" Read_Width="0" SLR_INDEX="-1">
+            <DataWidth MSB="18" LSB="18"/>
+            <AddressRange Begin="32768" End="65535"/>
+            <BitLayout pattern=""/>
+            <Parity ON="false" NumBits="0"/>
+          </BitLane>
+          <BitLane MemType="RAMB36" Placement="X1Y67" Read_Width="0" SLR_INDEX="-1">
+            <DataWidth MSB="17" LSB="17"/>
+            <AddressRange Begin="32768" End="65535"/>
+            <BitLayout pattern=""/>
+            <Parity ON="false" NumBits="0"/>
+          </BitLane>
+          <BitLane MemType="RAMB36" Placement="X2Y67" Read_Width="0" SLR_INDEX="-1">
+            <DataWidth MSB="16" LSB="16"/>
+            <AddressRange Begin="32768" End="65535"/>
+            <BitLayout pattern=""/>
+            <Parity ON="false" NumBits="0"/>
+          </BitLane>
+          <BitLane MemType="RAMB36" Placement="X1Y51" Read_Width="0" SLR_INDEX="-1">
+            <DataWidth MSB="31" LSB="31"/>
+            <AddressRange Begin="32768" End="65535"/>
+            <BitLayout pattern=""/>
+            <Parity ON="false" NumBits="0"/>
+          </BitLane>
+          <BitLane MemType="RAMB36" Placement="X0Y49" Read_Width="0" SLR_INDEX="-1">
+            <DataWidth MSB="30" LSB="30"/>
+            <AddressRange Begin="32768" End="65535"/>
+            <BitLayout pattern=""/>
+            <Parity ON="false" NumBits="0"/>
+          </BitLane>
+          <BitLane MemType="RAMB36" Placement="X3Y56" Read_Width="0" SLR_INDEX="-1">
+            <DataWidth MSB="29" LSB="29"/>
+            <AddressRange Begin="32768" End="65535"/>
+            <BitLayout pattern=""/>
+            <Parity ON="false" NumBits="0"/>
+          </BitLane>
+          <BitLane MemType="RAMB36" Placement="X0Y53" Read_Width="0" SLR_INDEX="-1">
+            <DataWidth MSB="28" LSB="28"/>
+            <AddressRange Begin="32768" End="65535"/>
+            <BitLayout pattern=""/>
+            <Parity ON="false" NumBits="0"/>
+          </BitLane>
+          <BitLane MemType="RAMB36" Placement="X2Y54" Read_Width="0" SLR_INDEX="-1">
+            <DataWidth MSB="27" LSB="27"/>
+            <AddressRange Begin="32768" End="65535"/>
+            <BitLayout pattern=""/>
+            <Parity ON="false" NumBits="0"/>
+          </BitLane>
+          <BitLane MemType="RAMB36" Placement="X0Y45" Read_Width="0" SLR_INDEX="-1">
+            <DataWidth MSB="26" LSB="26"/>
+            <AddressRange Begin="32768" End="65535"/>
+            <BitLayout pattern=""/>
+            <Parity ON="false" NumBits="0"/>
+          </BitLane>
+          <BitLane MemType="RAMB36" Placement="X2Y48" Read_Width="0" SLR_INDEX="-1">
+            <DataWidth MSB="25" LSB="25"/>
+            <AddressRange Begin="32768" End="65535"/>
+            <BitLayout pattern=""/>
+            <Parity ON="false" NumBits="0"/>
+          </BitLane>
+          <BitLane MemType="RAMB36" Placement="X0Y51" Read_Width="0" SLR_INDEX="-1">
+            <DataWidth MSB="24" LSB="24"/>
+            <AddressRange Begin="32768" End="65535"/>
+            <BitLayout pattern=""/>
+            <Parity ON="false" NumBits="0"/>
+          </BitLane>
+        </BusBlock>
+      </AddressSpaceRange>
+    </AddressSpace>
+  </Processor>
+  <Config>
+    <Option Name="Part" Val="xc7k410tffg900-2"/>
+  </Config>
+  <DRC>
+    <Rule Name="RDADDRCHANGE" Val="false"/>
+  </DRC>
+</MemInfo>

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/hw/system_top.xsa

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:ff38e5b6d614299ccd049e5bca72a986b84c8209c589be7c31b453217cbc10ec
+size 2300879

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/microblaze_ps/standalone_domain/bsp/Makefile

@@ -0,0 +1,49 @@
+# Makefile generated by Xilinx.
+
+DRIVER_LIB_VERSION = 1.0
+PROCESSOR = microblaze_ps
+LIBRARIES = ${PROCESSOR}/lib/libxil.a
+BSP_MAKEFILES := $(wildcard $(PROCESSOR)/libsrc/*/src/Makefile)
+SUBDIRS := $(patsubst %/Makefile, %, $(BSP_MAKEFILES))
+BSP_SEQUENTIAL_MAKEFILES := 
+BSP_PARALLEL_MAKEFILES := $(filter-out $(BSP_SEQUENTIAL_MAKEFILES),$(BSP_MAKEFILES))
+SEQ_SUBDIRS := $(patsubst %/Makefile, %, $(BSP_SEQUENTIAL_MAKEFILES))
+PAR_SUBDIRS := $(patsubst %/Makefile, %, $(BSP_PARALLEL_MAKEFILES))
+
+ifneq (,$(findstring win,$(RDI_PLATFORM)))
+ SHELL = CMD
+endif
+
+all: 
+	$(MAKE) --no-print-directory seq_libs
+	$(MAKE) -j 18 --no-print-directory par_libs
+	$(MAKE) --no-print-directory archive
+	@echo 'Finished building libraries'
+
+include: $(addsuffix /make.include,$(SUBDIRS))
+
+seq_libs: $(addsuffix /make.libs,$(SEQ_SUBDIRS))
+	@echo 'Finished building libraries sequentially.'
+
+par_libs: $(addsuffix /make.libs,$(PAR_SUBDIRS))
+	@echo 'Finished building libraries parallelly.'
+
+archive:
+	mb-ar -r  $(LIBRARIES) $(sort $(wildcard $(PROCESSOR)/lib/*.o))
+
+clean: $(addsuffix /make.clean,$(SUBDIRS))
+	rm -f ${PROCESSOR}/lib/libxil.a
+
+$(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a
+	cp -f $< $@
+
+%/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,)
+	@echo "Running Make include in $(subst /make.include,,$@)"
+	$(MAKE) -C $(subst /make.include,,$@) -s include  "SHELL=$(SHELL)" "COMPILER=mb-gcc" "ASSEMBLER=mb-as" "ARCHIVER=mb-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=v11.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-g -ffunction-sections -fdata-sections -Wall -Wextra -fno-tree-loop-distribute-patterns"
+
+%/make.libs: include
+	@echo "Running Make libs in $(subst /make.libs,,$@)"
+	$(MAKE) -C $(subst /make.libs,,$@) -s libs  "SHELL=$(SHELL)" "COMPILER=mb-gcc" "ASSEMBLER=mb-as" "ARCHIVER=mb-ar" "COMPILER_FLAGS=  -O2 -c -mcpu=v11.0 -mlittle-endian -mxl-soft-mul" "EXTRA_COMPILER_FLAGS=-g -ffunction-sections -fdata-sections -Wall -Wextra -fno-tree-loop-distribute-patterns"
+
+%/make.clean: 
+	$(MAKE) -C $(subst /make.clean,,$@) -s clean 

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/microblaze_ps/standalone_domain/bsp/dep.mk

@@ -0,0 +1,3 @@
+#  generated by Xilinx.
+
+DEPENDENCY_FLAGS= -MMD -MP

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/microblaze_ps/standalone_domain/bsp/microblaze_ps/include/_profile_timer_hw.h

@@ -0,0 +1,281 @@
+/******************************************************************************
+* Copyright (c) 2004 - 2020 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+
+#ifndef PROFILE_TIMER_HW_H
+#define PROFILE_TIMER_HW_H
+
+#include "profile.h"
+
+#ifdef PROC_PPC
+#if defined __GNUC__
+#  define SYNCHRONIZE_IO __asm__ volatile ("eieio")
+#elif defined __DCC__
+#  define SYNCHRONIZE_IO __asm volatile(" eieio")
+#else
+#  define SYNCHRONIZE_IO
+#endif
+#endif
+
+#ifdef PROC_PPC
+#define ProfIo_In32(InputPtr) { (*(volatile u32 *)(InputPtr)); SYNCHRONIZE_IO; }
+#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = Value); SYNCHRONIZE_IO; }
+#else
+#define ProfIo_In32(InputPtr) (*(volatile u32 *)(InputPtr));
+#define ProfIo_Out32(OutputPtr, Value) { (*(volatile u32 *)(OutputPtr) = (Value)); }
+#endif
+
+#define ProfTmrCtr_mWriteReg(BaseAddress, TmrCtrNumber, RegOffset, ValueToWrite)\
+	ProfIo_Out32(((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] +	\
+			   (u32)(RegOffset)), (u32)(ValueToWrite))
+
+#define ProfTimerCtr_mReadReg(BaseAddress, TmrCtrNumber, RegOffset)	\
+	ProfIo_In32((u32)(BaseAddress) + (u32)XTmrCtr_Offsets[(TmrCtrNumber)] + (u32)(RegOffset))
+
+#define ProfTmrCtr_mSetControlStatusReg(BaseAddress, TmrCtrNumber, RegisterValue)\
+	ProfTmrCtr_mWriteReg((BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET,     \
+					   (RegisterValue))
+
+#define ProfTmrCtr_mGetControlStatusReg(BaseAddress, TmrCtrNumber)		\
+	ProfTimerCtr_mReadReg((u32)(BaseAddress), (TmrCtrNumber), XTC_TCSR_OFFSET)
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef PROC_PPC
+#include "xexception_l.h"
+#include "xtime_l.h"
+#include "xpseudo_asm.h"
+#endif
+
+#ifdef TIMER_CONNECT_INTC
+#include "xintc_l.h"
+#include "xintc.h"
+#endif	/* TIMER_CONNECT_INTC */
+
+#if (!defined PPC_PIT_INTERRUPT && !defined PROC_CORTEXA9)
+#include "xtmrctr_l.h"
+#endif
+
+#ifdef PROC_CORTEXA9
+#include "xscutimer_hw.h"
+#include "xscugic.h"
+#endif
+
+extern u32 timer_clk_ticks ;
+
+/*--------------------------------------------------------------------
+ * PowerPC Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_PPC
+
+#ifdef PPC_PIT_INTERRUPT
+u32 timer_lo_clk_ticks ;	/* Clk ticks when Timer is disabled in CG */
+#endif
+
+#ifdef PROC_PPC440
+#define XREG_TCR_PIT_INTERRUPT_ENABLE XREG_TCR_DEC_INTERRUPT_ENABLE
+#define XREG_TSR_PIT_INTERRUPT_STATUS XREG_TSR_DEC_INTERRUPT_STATUS
+#define XREG_SPR_PIT XREG_SPR_DEC
+#define XEXC_ID_PIT_INT XEXC_ID_DEC_INT
+#endif
+
+/* --------------------------------------------------------------------
+ * Disable the Timer - During Profiling
+ *
+ * For PIT Timer -
+ *	1. XTime_PITDisableInterrupt() ;
+ *	2. Store the remaining timer clk tick
+ *	3. Stop the PIT Timer
+ *-------------------------------------------------------------------- */
+
+#ifdef PPC_PIT_INTERRUPT
+#define disable_timer() 		\
+	{				\
+		u32 val;	\
+		val=mfspr(XREG_SPR_TCR);	\
+		mtspr(XREG_SPR_TCR, val & (~XREG_TCR_PIT_INTERRUPT_ENABLE));	\
+		timer_lo_clk_ticks = mfspr(XREG_SPR_PIT);			\
+		mtspr(XREG_SPR_PIT, 0);	\
+	}
+#else
+#define disable_timer() 	\
+   { \
+      u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
+      u32 tmp_v = ProfIo_In32(addr); \
+      tmp_v = tmp_v & (~XTC_CSR_ENABLE_TMR_MASK); \
+      ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
+   }
+#endif
+
+
+
+/* --------------------------------------------------------------------
+ * Enable the Timer
+ *
+ * For PIT Timer -
+ *	1. Load the remaining timer clk ticks
+ *	2. XTime_PITEnableInterrupt() ;
+ *-------------------------------------------------------------------- */
+#ifdef PPC_PIT_INTERRUPT
+#define enable_timer()				\
+	{					\
+		u32 val;		\
+		val=mfspr(XREG_SPR_TCR);	\
+		mtspr(XREG_SPR_PIT, timer_lo_clk_ticks);	\
+		mtspr(XREG_SPR_TCR, val | XREG_TCR_PIT_INTERRUPT_ENABLE); \
+	}
+#else
+#define enable_timer()						\
+	{							\
+      u32 addr = (PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET; \
+      u32 tmp_v = ProfIo_In32(addr); \
+      tmp_v = tmp_v |  XTC_CSR_ENABLE_TMR_MASK; \
+      ProfIo_Out32((PROFILE_TIMER_BASEADDR) + XTmrCtr_Offsets[(0)] + XTC_TCSR_OFFSET, tmp_v); \
+	}
+#endif
+
+
+
+/* --------------------------------------------------------------------
+ * Send Ack to Timer Interrupt
+ *
+ * For PIT Timer -
+ * 	1. Load the timer clk ticks
+ *	2. Enable AutoReload and Interrupt
+ *	3. Clear PIT Timer Status bits
+ *-------------------------------------------------------------------- */
+#ifdef PPC_PIT_INTERRUPT
+#define timer_ack()							\
+	{								\
+		u32 val;					\
+		mtspr(XREG_SPR_PIT, timer_clk_ticks);			\
+		mtspr(XREG_SPR_TSR, XREG_TSR_PIT_INTERRUPT_STATUS);	\
+		val=mfspr(XREG_SPR_TCR);				\
+		mtspr(XREG_SPR_TCR, val| XREG_TCR_PIT_INTERRUPT_ENABLE| XREG_TCR_AUTORELOAD_ENABLE); \
+	}
+#else
+#define timer_ack()				\
+	{						\
+		u32 csr;			\
+		csr = ProfTmrCtr_mGetControlStatusReg(PROFILE_TIMER_BASEADDR, 0);	\
+		ProfTmrCtr_mSetControlStatusReg(PROFILE_TIMER_BASEADDR, 0, csr);	\
+	}
+#endif
+
+/*-------------------------------------------------------------------- */
+#endif	/* PROC_PPC */
+/* -------------------------------------------------------------------- */
+
+
+
+
+/* --------------------------------------------------------------------
+ * MicroBlaze Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_MICROBLAZE
+
+/* --------------------------------------------------------------------
+ * Disable the Timer during Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define disable_timer()					\
+	{						\
+      u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
+	  Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
+	  Addr += (u32)XTC_TCSR_OFFSET; \
+      u32 tmp_v = ProfIo_In32(Addr); \
+      tmp_v = tmp_v & (u32)(~XTC_CSR_ENABLE_TMR_MASK); \
+      u32 OutAddr = (u32)PROFILE_TIMER_BASEADDR; \
+      OutAddr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
+      OutAddr += (u32)XTC_TCSR_OFFSET; \
+      ProfIo_Out32(OutAddr, (u32)tmp_v); \
+    }
+
+
+/* --------------------------------------------------------------------
+ * Enable the Timer after Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define enable_timer()					\
+	{						\
+      u32 Addr = ((u32)PROFILE_TIMER_BASEADDR); \
+	  Addr += (u32)XTmrCtr_Offsets[(u16)(0)]; \
+	  Addr += (u32)XTC_TCSR_OFFSET; \
+      u32 tmp_v = (u32)ProfIo_In32(Addr); \
+      tmp_v = tmp_v |  (u32)XTC_CSR_ENABLE_TMR_MASK; \
+      ProfIo_Out32((u32)(PROFILE_TIMER_BASEADDR) + (u32)XTmrCtr_Offsets[(u16)(0)] + (u32)XTC_TCSR_OFFSET, (u32)tmp_v); \
+	}
+
+
+/* --------------------------------------------------------------------
+ * Send Ack to Timer Interrupt
+ *
+ *-------------------------------------------------------------------- */
+#define timer_ack()				\
+	{						\
+		u32 csr;			\
+		csr = ProfTmrCtr_mGetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0);	\
+		ProfTmrCtr_mSetControlStatusReg((u32)PROFILE_TIMER_BASEADDR, (u16)0, (u32)csr);	\
+	}
+
+/*-------------------------------------------------------------------- */
+#endif	/* PROC_MICROBLAZE */
+/*-------------------------------------------------------------------- */
+
+/* --------------------------------------------------------------------
+ * Cortex A9 Target - Timer related functions
+ *-------------------------------------------------------------------- */
+#ifdef PROC_CORTEXA9
+
+/* --------------------------------------------------------------------
+ * Disable the Timer during Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define disable_timer()							\
+{								\
+	u32 Reg;							\
+	Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
+	Reg &= (~XSCUTIMER_CONTROL_ENABLE_MASK);\
+	Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
+}
+
+
+/* --------------------------------------------------------------------
+ * Enable the Timer after Call-Graph Data collection
+ *
+ *-------------------------------------------------------------------- */
+#define enable_timer()							\
+{								\
+	u32 Reg;							\
+	Reg = Xil_In32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET); \
+	Reg |= XSCUTIMER_CONTROL_ENABLE_MASK; \
+	Xil_Out32(PROFILE_TIMER_BASEADDR + XSCUTIMER_CONTROL_OFFSET, Reg);\
+}
+
+
+/* --------------------------------------------------------------------
+ * Send Ack to Timer Interrupt
+ *
+ *-------------------------------------------------------------------- */
+#define timer_ack()						\
+{							\
+	Xil_Out32((u32)PROFILE_TIMER_BASEADDR + (u32)XSCUTIMER_ISR_OFFSET, \
+		(u32)XSCUTIMER_ISR_EVENT_FLAG_MASK);\
+}
+
+/*-------------------------------------------------------------------- */
+#endif	/* PROC_CORTEXA9 */
+/*-------------------------------------------------------------------- */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/microblaze_ps/standalone_domain/bsp/microblaze_ps/include/bspconfig.h

@@ -0,0 +1,21 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 2023.2.1
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2024 Xilinx, Inc. All Rights Reserved.
+* SPDX-License-Identifier: MIT 
+
+* 
+* Description: Configurations for Standalone BSP
+*
+*******************************************************************/
+
+#ifndef BSPCONFIG_H  /* prevent circular inclusions */
+#define BSPCONFIG_H  /* by using protection macros */
+
+#define MICROBLAZE_PVR_NONE
+
+#endif /*end of __BSPCONFIG_H_*/

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/microblaze_ps/standalone_domain/bsp/microblaze_ps/include/fsl.h

@@ -0,0 +1,125 @@
+/******************************************************************************
+* Copyright (c) 2021 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+#ifndef FSL_H
+#define FSL_H
+/*****************************************************************************/
+/**
+*
+* @file fsl.h
+*
+* @addtogroup microblaze_fsl_macro MicroBlaze Processor FSL Macros
+*
+* Microblaze BSP includes macros to provide convenient access to accelerators
+* connected to the MicroBlaze Fast Simplex Link (FSL) Interfaces.To use these functions,
+* include the header file fsl.h in your source code
+*
+* @{
+*
+******************************************************************************/
+#include "mb_interface.h"       /* Legacy reasons. We just have to include this guy who defines the FSL stuff */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ *@cond nocomments
+ */
+/* Extended FSL macros. These now replace all of the previous FSL macros */
+#define FSL_DEFAULT
+#define FSL_NONBLOCKING                          n
+#define FSL_EXCEPTION                            e
+#define FSL_CONTROL                              c
+#define FSL_ATOMIC                               a
+
+#define FSL_NONBLOCKING_EXCEPTION                ne
+#define FSL_NONBLOCKING_CONTROL                  nc
+#define FSL_NONBLOCKING_ATOMIC                   na
+#define FSL_EXCEPTION_CONTROL                    ec
+#define FSL_EXCEPTION_ATOMIC                     ea
+#define FSL_CONTROL_ATOMIC                       ca
+
+#define FSL_NONBLOCKING_EXCEPTION_CONTROL        nec
+#define FSL_NONBLOCKING_EXCEPTION_ATOMIC         nea
+#define FSL_NONBLOCKING_CONTROL_ATOMIC           nca
+#define FSL_EXCEPTION_CONTROL_ATOMIC             eca
+
+#define FSL_NONBLOCKING_EXCEPTION_CONTROL_ATOMIC neca
+
+ /**
+  *@endcond
+  */
+
+/**
+Performs a get function on an input FSL of the MicroBlaze processor
+@param val    variable to sink data from get function
+@param id     literal in the range of 0 to 7 (0 to 15 for MicroBlaze v7.00.a and later)
+@param flags  valid FSL macro flags
+*/
+#define getfslx(val, id, flags)      asm volatile (stringify(flags) "get\t%0,rfsl" stringify(id) : "=d" (val))
+
+/**
+Performs a put function on an input FSL of the MicroBlaze processor
+@param val    variable to source data to put function
+@param id     literal in the range of 0 to 7 (0 to 15 for MicroBlaze v7.00.a and later)
+@param flags  valid FSL macro flags
+*/
+#define putfslx(val, id, flags)      asm volatile (stringify(flags) "put\t%0,rfsl" stringify(id) :: "d" (val))
+
+/**
+Performs a test get function on an input FSL of the MicroBlaze processor
+@param val    variable to sink data from get function
+@param id     literal in the range of 0 to 7 (0 to 15 for MicroBlaze v7.00.a and later)
+@param flags  valid FSL macro flags
+*/
+#define tgetfslx(val, id, flags)     asm volatile ("t" stringify(flags) "get\t%0,rfsl" stringify(id) : "=d" (val))
+
+/**
+Performs a put function on an input FSL of the MicroBlaze processor
+@param id     FSL identifier
+@param flags  valid FSL macro flags
+*/
+#define tputfslx(id, flags)          asm volatile ("t" stringify(flags) "put\trfsl" stringify(id))
+
+/**
+Performs a getd function on an input FSL of the MicroBlaze processor
+@param val    variable to sink data from getd function
+@param var    literal in the range of 0 to 7 (0 to 15 for MicroBlaze v7.00.a and later)
+@param flags  valid FSL macro flags
+*/
+#define getdfslx(val, var, flags)    asm volatile (stringify(flags) "getd\t%0,%1" : "=d" (val) : "d" (var))
+
+/**
+Performs a putd function on an input FSL of the MicroBlaze processor
+@param val    variable to source data to putd function
+@param var    literal in the range of 0 to 7 (0 to 15 for MicroBlaze v7.00.a and later)
+@param flags  valid FSL macro flags
+*/
+#define putdfslx(val, var, flags)    asm volatile (stringify(flags) "putd\t%0,%1" :: "d" (val), "d" (var))
+
+/**
+Performs a test getd function on an input FSL of the MicroBlaze processor;
+@param val    variable to sink data from getd function
+@param var    literal in the range of 0 to 7 (0 to 15 for MicroBlaze v7.00.a and later)
+@param flags  valid FSL macro flags
+*/
+#define tgetdfslx(val, var, flags)   asm volatile ("t" stringify(flags) "getd\t%0,%1" : "=d" (val) : "d" (var))
+
+/**
+Performs a put function on an input FSL of the MicroBlaze processor
+@param var     FSL identifier
+@param flags  valid FSL macro flags
+*/
+#define tputdfslx(var, flags)        asm volatile ("t" stringify(flags) "putd\t%0" :: "d" (var))
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* FSL_H */
+/**
+* @} End of "addtogroup microblaze_fsl_macro".
+*/

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/microblaze_ps/standalone_domain/bsp/microblaze_ps/include/mb_interface.h

@@ -0,0 +1,506 @@
+/******************************************************************************
+* Copyright (c) 2004 - 2021 Xilinx, Inc.  All rights reserved.
+* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file mb_interface.h
+*
+* @addtogroup microblaze_pseudo_asm_macro Microblaze Pseudo-asm Macros and Interrupt Handling APIs
+*
+* Microblaze BSP includes macros to provide convenient access to various registers
+* in the MicroBlaze processor. Some of these macros are very useful within
+* exception handlers for retrieving information about the exception.Also,
+* the interrupt handling functions help manage interrupt handling on MicroBlaze
+* processor devices.To use these functions, include the header file
+* mb_interface.h in your source code
+*
+* @{
+*
+******************************************************************************/
+/**
+ *@cond nocomments
+ */
+
+#ifndef _MICROBLAZE_INTERFACE_H_
+#define _MICROBLAZE_INTERFACE_H_
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_exception.h"
+#include "bspconfig.h"
+#ifdef SDT
+#include "xmicroblaze_config.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+extern void microblaze_enable_interrupts(void);                 /* Enable Interrupts */
+extern void microblaze_disable_interrupts(void);                /* Disable Interrupts */
+extern void microblaze_enable_icache(void);                     /* Enable Instruction Cache */
+extern void microblaze_disable_icache(void);                    /* Disable Instruction Cache */
+extern void microblaze_enable_dcache(void);                     /* Enable Instruction Cache */
+extern void microblaze_disable_dcache(void);                    /* Disable Instruction Cache */
+extern void microblaze_enable_exceptions(void);                 /* Enable hardware exceptions */
+extern void microblaze_disable_exceptions(void);                /* Disable hardware exceptions */
+
+/**
+ *@endcond
+ */
+extern void microblaze_register_handler(XInterruptHandler Handler, void *DataPtr); /* Register top level interrupt handler */
+extern void microblaze_register_exception_handler(u32 ExceptionId, Xil_ExceptionHandler Handler, void *DataPtr); /* Register exception handler */
+
+/**
+ *@cond nocomments
+ */
+extern void microblaze_invalidate_icache(void);         /* Invalidate the entire icache */
+extern void microblaze_invalidate_dcache(void);         /* Invalidate the entire dcache */
+extern void microblaze_flush_dcache(void);              /* Flush the whole dcache */
+extern void microblaze_invalidate_icache_range(UINTPTR cacheaddr, u32 len);   /* Invalidate a part of the icache */
+extern void microblaze_invalidate_dcache_range(UINTPTR cacheaddr, u32 len);   /* Invalidate a part of the dcache */
+extern void microblaze_flush_dcache_range(UINTPTR cacheaddr, u32 len);        /* Flush a part of the dcache */
+extern void microblaze_scrub(void);                     /* Scrub LMB and internal BRAM */
+extern void microblaze_invalidate_cache_ext(void);         /* Invalidate cache ext */
+extern void microblaze_flush_cache_ext(void);         /* Flush cache ext */
+extern void microblaze_flush_cache_ext_range(UINTPTR cacheaddr,
+			u32 len); /* Flush cache ext range */
+extern void microblaze_invalidate_cache_ext_range(UINTPTR cacheaddr,
+			u32 len); /* Invalidate cache ext range */
+
+/* Deprecated */
+extern void microblaze_update_icache (s32 , s32 , s32 ) __attribute__((deprecated));
+extern void microblaze_init_icache_range (s32 , s32 )  __attribute__((deprecated));
+extern void microblaze_update_dcache (s32 , s32 , s32 )  __attribute__((deprecated));
+extern void microblaze_init_dcache_range (s32 , s32 )  __attribute__((deprecated));
+
+/* necessary for pre-processor */
+#define stringify(s)    tostring(s)
+#define tostring(s)     #s
+
+/* FSL Access Macros */
+
+/* Blocking Data Read and Write to FSL no. id */
+#define getfsl(val, id)         asm volatile ("get\t%0,rfsl" stringify(id) : "=d" (val))
+#define putfsl(val, id)         asm volatile ("put\t%0,rfsl" stringify(id) :: "d" (val))
+
+/* Non-blocking Data Read and Write to FSL no. id */
+#define ngetfsl(val, id)        asm volatile ("nget\t%0,rfsl" stringify(id) : "=d" (val))
+#define nputfsl(val, id)        asm volatile ("nput\t%0,rfsl" stringify(id) :: "d" (val))
+
+/* Blocking Control Read and Write to FSL no. id */
+#define cgetfsl(val, id)        asm volatile ("cget\t%0,rfsl" stringify(id) : "=d" (val))
+#define cputfsl(val, id)        asm volatile ("cput\t%0,rfsl" stringify(id) :: "d" (val))
+
+/* Non-blocking Control Read and Write to FSL no. id */
+#define ncgetfsl(val, id)       asm volatile ("ncget\t%0,rfsl" stringify(id) : "=d" (val))
+#define ncputfsl(val, id)       asm volatile ("ncput\t%0,rfsl" stringify(id) :: "d" (val))
+
+/* Polling versions of FSL access macros. This makes the FSL access interruptible */
+#define getfsl_interruptible(val, id)       asm volatile ("\n1:\n\tnget\t%0,rfsl" stringify(id) "\n\t"   \
+                                                          "addic\tr18,r0,0\n\t"                \
+                                                          "bnei\tr18,1b\n"                     \
+                                                           : "=d" (val) :: "r18")
+
+#define putfsl_interruptible(val, id)       asm volatile ("\n1:\n\tnput\t%0,rfsl" stringify(id) "\n\t"   \
+                                                          "addic\tr18,r0,0\n\t"                \
+                                                          "bnei\tr18,1b\n"                     \
+                                                          :: "d" (val) : "r18")
+
+#define cgetfsl_interruptible(val, id)      asm volatile ("\n1:\n\tncget\t%0,rfsl" stringify(id) "\n\t"  \
+                                                          "addic\tr18,r0,0\n\t"                \
+                                                          "bnei\tr18,1b\n"                     \
+                                                          : "=d" (val) :: "r18")
+
+#define cputfsl_interruptible(val, id)      asm volatile ("\n1:\n\tncput\t%0,rfsl" stringify(id) "\n\t"  \
+                                                          "addic\tr18,r0,0\n\t"                \
+                                                          "bnei\tr18,1b\n"                     \
+                                                          :: "d" (val) : "r18")
+/* FSL valid and error check macros. */
+#define fsl_isinvalid(result)               asm volatile ("addic\t%0,r0,0"  : "=d" (result))
+#define fsl_iserror(error)                  asm volatile ("mfs\t%0,rmsr\n\t"  \
+                                                              "andi\t%0,%0,0x10" : "=d" (error))
+
+/* Pseudo assembler instructions */
+#define clz(v)          ({  u32 _rval = 0U;         \
+                            __asm__ __volatile__ (      \
+                                "clz\t%0,%1\n" : "=d"(_rval): "d" (v) \
+                            );                          \
+                            _rval;                      \
+                        })
+
+#define mbar(mask)      ({  __asm__ __volatile__ ("mbar\t" stringify(mask) ); })
+#define mb_sleep()     	({  __asm__ __volatile__ ("sleep\t"); })
+#define mb_hibernate() 	({  __asm__ __volatile__ ("hibernate\t"); })
+#define mb_suspend()   	({  __asm__ __volatile__ ("suspend\t"); })
+#define mb_swapb(v)		({	u32 _rval = 0U;         \
+							__asm__ __volatile__ (      \
+								"swapb\t%0,%1\n" : "=d"(_rval) : "d" (v) \
+							 );                          \
+							 _rval;                      \
+						})
+
+#define mb_swaph(v)		({	u32 _rval = 0U;         \
+							__asm__ __volatile__ (      \
+								"swaph\t%0,%1\n" : "=d"(_rval) : "d" (v) \
+							 );                          \
+							 _rval;                      \
+						})
+
+/** @name Microblaze pseudo-asm macros
+ *
+ * The following is a summary of the MicroBlaze processor pseudo-asm macros.
+ * @{
+ */
+
+ /**
+ Return value from the general purpose register (GPR) rn.
+ @param rn     General purpose register to be read.
+*/
+#define mfgpr(rn)       ({  UINTPTR _rval = 0U;         \
+                            __asm__ __volatile__ (      \
+                                "or\t%0,r0," stringify(rn) "\n" : "=d"(_rval) \
+                            );                          \
+                            _rval;                      \
+                        })
+
+ /**
+ Return the current value of the MSR.
+*/
+#define mfmsr()         ({  UINTPTR _rval = 0U;         \
+                            __asm__ __volatile__ (      \
+                                "mfs\t%0,rmsr\n" : "=d"(_rval) \
+                            );                          \
+                            _rval;                      \
+                        })
+
+ /**
+ Return the current value of the Exception Address Register (EAR).
+*/
+#define mfear()         ({  UINTPTR _rval = 0U;         \
+                            __asm__ __volatile__ (      \
+                                "mfs\t%0,rear\n" : "=d"(_rval) \
+                            );                          \
+                            _rval;                      \
+                        })
+
+#define mfeare()        ({  UINTPTR _rval = 0U; \
+                            __asm__ __volatile__ ( \
+                                "mfse\t%0,rear\n" : "=d"(_rval) \
+                            ); \
+                            _rval; \
+                          })
+ /**
+ Return the current value of the Exception Status Register (ESR).
+*/
+#define mfesr()         ({  UINTPTR _rval = 0U;         \
+                            __asm__ __volatile__ (      \
+                                "mfs\t%0,resr\n" : "=d"(_rval) \
+                            );                          \
+                            _rval;                      \
+                        })
+
+ /**
+ Return the current value of the Floating Point Status (FPS).
+*/
+#define mffsr()         ({  UINTPTR _rval = 0U;         \
+                            __asm__ __volatile__ (      \
+                                "mfs\t%0,rfsr\n" : "=d"(_rval) \
+                            );                          \
+                            _rval;                      \
+                        })
+/*@}*/
+#define mfpvr(rn)       ({  UINTPTR _rval = 0U;         \
+                            __asm__ __volatile__ (                          \
+                                "mfs\t%0,rpvr" stringify(rn) "\n" : "=d"(_rval) \
+                            );                                              \
+                            _rval;                                          \
+                        })
+
+#define mfpvre(rn)      ({  UINTPTR _rval = 0U; \
+                            __asm__ __volatile__ ( \
+                                "mfse\t%0,rpvr" stringify(rn) "\n" : "=d"(_rval) \
+                            ); \
+                            _rval; \
+                          })
+
+#define mfbtr()         ({  UINTPTR _rval = 0U;         \
+                            __asm__ __volatile__ (      \
+                                "mfs\t%0,rbtr\n" : "=d"(_rval)  \
+                            );                                  \
+                            _rval;                              \
+                        })
+
+#define mfedr()         ({  UINTPTR _rval = 0U;         \
+                            __asm__ __volatile__ (      \
+                                "mfs\t%0,redr\n" : "=d"(_rval)  \
+                            );                                  \
+                            _rval;                              \
+                        })
+
+#define mfpid()         ({  UINTPTR _rval = 0U;         \
+                            __asm__ __volatile__ (            \
+                                "mfs\t%0,rpid\n" : "=d"(_rval)\
+                            );                                \
+                            _rval;                            \
+                        })
+
+#define mfzpr()         ({  UINTPTR _rval = 0U;         \
+                            __asm__ __volatile__ (                  \
+                                "mfs\t%0,rzpr\n" : "=d"(_rval)      \
+                            );                                      \
+                            _rval;                                  \
+                        })
+
+#define mftlbx()        ({  UINTPTR _rval = 0U;         \
+                            __asm__ __volatile__ (                  \
+                                "mfs\t%0,rtlbx\n" : "=d"(_rval)     \
+                            );                                      \
+                            _rval;                                  \
+                        })
+
+#define mftlblo()       ({  UINTPTR _rval = 0U;                     \
+                            __asm__ __volatile__ (                  \
+                                "mfs\t%0,rtlblo\n" : "=d"(_rval)    \
+                            );                                      \
+                            _rval;                                  \
+                        })
+
+#define mftlbhi()       ({  UINTPTR _rval = 0U;         \
+                            __asm__ __volatile__ (                  \
+                                "mfs\t%0,rtlbhi\n" : "=d"(_rval)    \
+                            );                                      \
+                            _rval;                                  \
+                        })
+
+#define mfslr()         ({  UINTPTR _rval = 0U;         \
+                            __asm__ __volatile__ (                  \
+                                "mfs\t%0,rslr\n" : "=d"(_rval)    \
+                            );                                      \
+                            _rval;                                  \
+                        })
+
+#define mfshr()         ({  UINTPTR _rval = 0U;         \
+                            __asm__ __volatile__ (                  \
+                                "mfs\t%0,rshr\n" : "=d"(_rval)    \
+                            );                                      \
+                            _rval;                                  \
+                        })
+
+#define mtgpr(rn, v)    ({  __asm__ __volatile__ (                      \
+                                "or\t" stringify(rn) ",r0,%0\n" :: "d" (v) \
+                            );                          \
+                        })
+
+#define mtmsr(v)        ({  __asm__ __volatile__ (      \
+                                "mts\trmsr,%0\n\tnop\n" :: "d" (v)      \
+                            );                          \
+                        })
+
+
+#define mtfsr(v)        ({  __asm__ __volatile__ (      \
+                                "mts\trfsr,%0\n\tnop\n" :: "d" (v)  \
+                            );                                      \
+                        })
+
+#define mtpid(v)        ({  __asm__ __volatile__ (      \
+                                "mts\trpid,%0\n\tnop\n" :: "d" (v)      \
+                            );                                      \
+                        })
+
+#define mtzpr(v)        ({  __asm__ __volatile__ (                  \
+                                "mts\trzpr,%0\n\tnop\n" :: "d" (v)      \
+                            );                                      \
+                        })
+
+#define mttlbx(v)       ({  __asm__ __volatile__ (      \
+                                "mts\trtlbx,%0\n\tnop\n" :: "d" (v)     \
+                            );                                      \
+                        })
+
+#define mttlblo(v)      ({  __asm__ __volatile__ (      \
+                                "mts\trtlblo,%0\n\tnop\n" :: "d" (v)    \
+                            );                                      \
+                        })
+
+#define mttlbhi(v)      ({  __asm__ __volatile__ (      \
+                                "mts\trtlbhi,%0\n\tnop\n" :: "d" (v)    \
+                            );                                      \
+                        })
+
+#define mttlbsx(v)      ({  __asm__ __volatile__ (      \
+                                "mts\trtlbsx,%0\n\tnop\n" :: "d" (v)    \
+                            );                                      \
+                        })
+
+#define mtslr(v)        ({  __asm__ __volatile__ (      \
+                                "mts\trslr,%0\n\tnop\n" :: "d" (v)  \
+                            );                                      \
+                        })
+
+#define mtshr(v)        ({  __asm__ __volatile__ (      \
+                                "mts\trshr,%0\n\tnop\n" :: "d" (v)  \
+                            );                                      \
+                        })
+
+#define lwx(address)	({  u32 _rval = 0U; \
+                              __asm__ __volatile__ ( \
+                             "lwx\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
+                              ); \
+                              _rval; \
+                          })
+
+#define lwr(address)	({  u32 _rval = 0U; \
+                              __asm__ __volatile__ ( \
+                             "lwr\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
+                              ); \
+                              _rval; \
+                          })
+
+
+#define lwea(lladdr)	({  u32 _rval = 0U; \
+                              __asm__ __volatile__ ( \
+                             "lwea\t%0,%M1,%L1\n" : "=d"(_rval) : "d" (lladdr) \
+                              ); \
+                              _rval; \
+                          })
+
+#define lhur(address)	({  u32 _rval = 0U; \
+                              __asm__ __volatile__ ( \
+                             "lhur\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
+                              ); \
+                              _rval; \
+                          })
+
+#define lhuea(lladdr)	({  u32 _rval = 0U; \
+                              __asm__ __volatile__ ( \
+                             "lhuea\t%0,%M1,%L1\n" : "=d"(_rval) : "d" (lladdr) \
+                              ); \
+                              _rval; \
+                          })
+
+#define lbur(address)	({  u32 _rval = 0U; \
+                              __asm__ __volatile__ ( \
+                             "lbur\t%0,%1,r0\n" : "=d"(_rval) : "d" (address) \
+                              ); \
+                              _rval; \
+                          })
+
+#define lbuea(lladdr)	({  u32 _rval = 0U; \
+                              __asm__ __volatile__ ( \
+                             "lbuea\t%0,%M1,%L1\n" : "=d"(_rval) : "d" (lladdr) \
+                              ); \
+                              _rval; \
+                          })
+
+#define swx(address, data) ({  __asm__ __volatile__ ( \
+                                "swx\t%0,%1,r0\n" :: "d" (data), "d" (address) \
+                               ); \
+                           })
+
+#define swr(address, data) ({  __asm__ __volatile__ ( \
+                                "swr\t%0,%1,r0\n" :: "d" (data), "d" (address) \
+                               ); \
+                           })
+
+#define swea(lladdr, data) ({  __asm__ __volatile__ ( \
+                                "swea\t%0,%M1,%L1\n" :: "d" (data), "d" (lladdr) \
+                               ); \
+                           })
+
+#define shr(address, data) ({  __asm__ __volatile__ ( \
+                                "shr\t%0,%1,r0\n" :: "d" (data), "d" (address) \
+                               ); \
+                           })
+
+#define shea(lladdr, data) ({  __asm__ __volatile__ ( \
+                                "shea\t%0,%M1,%L1\n" :: "d" (data), "d" (lladdr) \
+                               ); \
+                           })
+
+#define sbr(address, data) ({  __asm__ __volatile__ ( \
+                                "sbr\t%0,%1,r0\n" :: "d" (data), "d" (address) \
+                               ); \
+                           })
+
+#define sbea(lladdr, data) ({  __asm__ __volatile__ ( \
+                                "sbea\t%0,%M1,%L1\n" :: "d" (data), "d" (lladdr) \
+                               ); \
+                           })
+
+#define microblaze_getfpex_operand_a()     ({          \
+                                    extern u32 mb_fpex_op_a;   \
+                                    mb_fpex_op_a;                       \
+                                })
+
+#define microblaze_getfpex_operand_b()     ({          \
+                                    extern u32 mb_fpex_op_b;   \
+                                    mb_fpex_op_b;                       \
+                                })
+
+#define mtwdcflush(val)   ({  __asm__ __volatile__ (      \
+                                "wdc.flush \t%0,r0\n\tnop\n" :: "d" (val)     \
+                            );                                      \
+                        })
+
+#define mtwdcclear(val1, val2)   ({  __asm__ __volatile__ (      \
+                                "wdc.clear \t%0,%1\n\tnop\n" :: "d" (val1), "d" (val2)     \
+                            );                                      \
+                        })
+
+#define mtwdcextflush(val)   ({  __asm__ __volatile__ (      \
+                                "wdc.ext.flush \t%0,r0\n\tnop\n" :: "d" (val)     \
+                            );                                      \
+                        })
+#define mtwdcextclear(val)   ({  __asm__ __volatile__ (      \
+                                "wdc.ext.clear \t%0,r0\n\tnop\n" :: "d" (val)     \
+                            );                                      \
+                        })
+#define mtwdc(val)   ({  __asm__ __volatile__ (      \
+                                "wdc \t%0,r0\n\tnop\n" :: "d" (val)     \
+                            );                                      \
+                        })
+
+#define mtwic(val)   ({  __asm__ __volatile__ (      \
+                                "wic \t%0,r0\n\tnop\n" :: "d" (val)     \
+                            );                                      \
+                        })
+
+#define msrclr(mask) ({ __asm__ __volatile__ ("	 msrclr	r0, %0;"	\
+				        "nop;"			\
+			            : : "i" (mask) : "memory"); \
+				     })
+#define msrset(mask) ({ __asm__ __volatile__ ("	 msrset	r0, %0;"	\
+				        "nop;"			\
+			            : : "i" (mask) : "memory"); \
+				     })
+
+/* Deprecated MicroBlaze FSL macros */
+#define microblaze_bread_datafsl(val, id)       getfsl(val,id)
+#define microblaze_bwrite_datafsl(val, id)      putfsl(val,id)
+#define microblaze_nbread_datafsl(val, id)      ngetfsl(val,id)
+#define microblaze_nbwrite_datafsl(val, id)     nputfsl(val,id)
+#define microblaze_bread_cntlfsl(val, id)       cgetfsl(val,id)
+#define microblaze_bwrite_cntlfsl(val, id)      cputfsl(val,id)
+#define microblaze_nbread_cntlfsl(val, id)      ncgetfsl(val,id)
+#define microblaze_nbwrite_cntlfsl(val, id)     ncputfsl(val,id)
+
+#ifdef SDT
+#define XMICROBLAZE_DCACHE_MASK 0x80U
+#define XMICROBLAZE_ICACHE_MASK 0x20U
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif // _MICROBLAZE_INTERFACE_H_
+/**
+ *@endcond
+ */
+
+/**
+* @} End of "addtogroup microblaze_pseudo_asm_macro".
+*/

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/microblaze_ps/standalone_domain/bsp/microblaze_ps/include/mblaze_nt_types.h

@@ -0,0 +1,28 @@
+/******************************************************************************
+* Copyright (c) 2002 - 2020 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+
+
+#ifndef _MBLAZE_NT_TYPES_H
+#define _MBLAZE_NT_TYPES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef char            byte;
+typedef short           half;
+typedef int             word;
+typedef unsigned char   ubyte;
+typedef unsigned short  uhalf;
+typedef unsigned int    uword;
+typedef ubyte           boolean;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/microblaze_ps/standalone_domain/bsp/microblaze_ps/include/microblaze_exceptions_g.h

@@ -0,0 +1,15 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 2023.2.1
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2024 Xilinx, Inc. All Rights Reserved.
+* SPDX-License-Identifier: MIT 
+
+* 
+* Description: Exception Handling Header for MicroBlaze Processor
+*
+*******************************************************************/
+

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/microblaze_ps/standalone_domain/bsp/microblaze_ps/include/microblaze_exceptions_i.h

@@ -0,0 +1,75 @@
+/******************************************************************************
+* Copyright (C) 2012 - 2022 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file microblaze_exceptions_i.h
+*
+* This header file contains defines for structures used by the microblaze
+* hardware exception handler.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Date     Changes
+* ----- -------- -----------------------------------------------
+* 1.00a 06/24/04 First release
+* 8.0	03/17/22 Add MB_ExceptionVectorTableEntry decalration to
+* 		 fix misra_c_2012_rule_8_5 violation.
+* 9.0   03/03/23 Add description to fix doxygen warnings.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef MICROBLAZE_EXCEPTIONS_I_H /**< prevent circular inclusions */
+#define MICROBLAZE_EXCEPTIONS_I_H /**< by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_exception.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ *@cond nocomments
+ */
+
+typedef struct
+{
+   Xil_ExceptionHandler Handler;
+   void *CallBackRef;
+} MB_ExceptionVectorTableEntry;
+
+extern MB_ExceptionVectorTableEntry MB_ExceptionVectorTable[XIL_EXCEPTION_ID_INT];
+
+/* Exception IDs */
+#define XEXC_ID_FSL                     0U
+#define XEXC_ID_UNALIGNED_ACCESS        1U
+#define XEXC_ID_ILLEGAL_OPCODE          2U
+#define XEXC_ID_M_AXI_I_EXCEPTION       3U
+#define XEXC_ID_IPLB_EXCEPTION          3U
+#define XEXC_ID_M_AXI_D_EXCEPTION       4U
+#define XEXC_ID_DPLB_EXCEPTION          4U
+#define XEXC_ID_DIV_BY_ZERO             5U
+#define XEXC_ID_FPU                     6U
+#define XEXC_ID_STACK_VIOLATION         7U
+#define XEXC_ID_MMU                     7U
+
+/**
+ *@endcond
+ */
+
+void microblaze_register_exception_handler(u32 ExceptionId, Xil_ExceptionHandler Handler, void *DataPtr);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* end of protection macro */

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/microblaze_ps/standalone_domain/bsp/microblaze_ps/include/microblaze_instructions.h

@@ -0,0 +1,149 @@
+/******************************************************************************
+* Copyright (c) 2018 - 2021 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file microblaze_instructions.h
+*
+* It provides wrapper macros to call 32/64 bit variant of specific
+* arithmetic/logical instructions, based on the processor in execution.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.8 	mus  	 10/09/18 First release
+*
+*
+* </pre>
+*
+******************************************************************************/
+
+/**
+ *@cond nocomments
+ */
+
+#ifndef MICROBLAZE_INSTRUCTIONS_H /* prevent circular inclusions */
+#define MICROBLAZE_INSTRUCTIONS_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined (__arch64__)
+#define ADD     addl
+#define ADDC    addlc
+#define ADDI    addli
+#define ADDIC   addlic
+#define ADDIK   addlik
+#define ADDIKC  addlikc
+#define ADDK    addlk
+#define ADDKC   addlkc
+#define AND     andl
+#define ANDI    andli
+#define ANDN    andnl
+#define ANDNI   andnli
+#define BEQI    beaeqi
+#define BEQID   beaeqid
+#define BGEI    beagei
+#define BGEID   beageid
+#define BGTI    beagti
+#define BGTID   beagtid
+#define BLEI    bealei
+#define BLEID   bealeid
+#define BLTI    bealti
+#define BLTID   bealtid
+#define BNEI    beanei
+#define BNEID   beaneid
+#define BR      brea
+#define BRALID  brealid
+#define BRD     bread
+#define BRI     breai
+#define BRID    breaid
+#define BRLD    breald
+#define BRLID   brealid
+#define CMP     cmpl
+#define CMPU    cmplu
+#define LI      lli
+#define LOAD    ll
+#define OR      orl
+#define ORI     orli
+#define RSUB    rsubl
+#define RSUBC   rsublc
+#define RSUBI   rsubli
+#define RSUBIC  rsublic
+#define RSUBIK  rsublik
+#define RSUBIKC rsublikc
+#define RSUBK   rsublk
+#define RSUBKC  rsublkc
+#define SI      sli
+#define STORE   sl
+#define SUBK    sublk
+#define XOR     xorl
+#define XORI    xorli
+#else
+#define ADD     add
+#define ADDC    addc
+#define ADDI    addi
+#define ADDIC   addic
+#define ADDIK   addik
+#define ADDIKC  addikc
+#define ADDK    addk
+#define ADDKC   addkc
+#define AND     and
+#define ANDI    andi
+#define ANDN    andn
+#define ANDNI   andni
+#define BEQI    beqi
+#define BEQID   beqid
+#define BGEI    bgei
+#define BGEID   bgeid
+#define BGTI    bgti
+#define BGTID   bgtid
+#define BLEI    blei
+#define BLEID   bleid
+#define BLTI    blti
+#define BLTID   bltid
+#define BNEI    bnei
+#define BNEID   bneid
+#define BR      br
+#define BRALID  bralid
+#define BRD     brd
+#define BRI     bri
+#define BRID    brid
+#define BRLD    brld
+#define BRLID   brlid
+#define CMP     cmp
+#define CMPU    cmpu
+#define LI      lwi
+#define LOAD    lw
+#define OR      or
+#define ORI     ori
+#define RSUB    rsub
+#define RSUBC   rsubc
+#define RSUBI   rsubi
+#define RSUBIC  rsubic
+#define RSUBIK  rsubik
+#define RSUBIKC rsubikc
+#define RSUBK   rsubk
+#define RSUBKC  rsubkc
+#define SI      swi
+#define STORE   sw
+#define SUBK    subk
+#define XOR     xor
+#define XORI    xori
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MICROBLAZE_INSTRUCTIONS_H */
+
+/**
+ *@endcond
+ */

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/microblaze_ps/standalone_domain/bsp/microblaze_ps/include/microblaze_interrupts_i.h

@@ -0,0 +1,63 @@
+/******************************************************************************
+* Copyright (c) 2008 - 2022 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file microblaze_interrupts_i.h
+*
+* This header file contains identifiers and low-level driver functions (or
+* macros) that can be used to access the device.  The user should refer to the
+* hardware device specification for more details of the device operation.
+* High-level driver functions are defined in xintc.h.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Date     Changes
+* ----- -------- -----------------------------------------------
+* 1.00b 10/03/03 First release
+* 8.0	03/17/22 Add MB_InterruptVectorTableEntry decalration to
+* 		 fix misra_c_2012_rule_8_5 violation.
+* </pre>
+*
+******************************************************************************/
+
+/**
+ *@cond nocomments
+ */
+
+#ifndef MICROBLAZE_INTERRUPTS_I_H /* prevent circular inclusions */
+#define MICROBLAZE_INTERRUPTS_I_H /* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_exception.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct
+{
+   XInterruptHandler Handler;
+   void *CallBackRef;
+} MB_InterruptVectorTableEntry;
+
+#define MB_INTERRUPT_VECTOR_TABLE_ENTRIES	1
+
+extern MB_InterruptVectorTableEntry MB_InterruptVectorTable[MB_INTERRUPT_VECTOR_TABLE_ENTRIES];
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+
+/**
+ *@endcond
+ */

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/microblaze_ps/standalone_domain/bsp/microblaze_ps/include/microblaze_sleep.h

@@ -0,0 +1,130 @@
+/******************************************************************************
+* Copyright (c) 2014 - 2021 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file microblaze_sleep.h
+*
+* @addtogroup microblaze_sleep_routines Sleep Routines for Microblaze
+*
+* The microblaze_sleep.h file contains microblaze sleep APIs. These APIs
+* provides delay for requested duration.
+*
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 4.1   asa  04/18/14 Add sleep function - first release.
+* 6.6   srm  10/18/17 Added the Register offset definitions and Control/Status
+*                     Register bit masks of the Axi timer.
+* 7.5   mus   04/21/21 Microblaze frequency can be changed run time. Sleep routines
+*                      needs to use updated frequency for delay calculation, else
+*                      sleep calls would result into incorrect behavior. Added
+*                      Xil_SetMBFrequency API to write updated frequency value to
+*                      MBFreq variable, and updated ITERS_PER_SEC macro to read
+*                      frequency value from MBFreq variable, instead of using XPARS.
+*                      Xil_SetMBFrequency must be called immediately after change
+*                      in Microblaze frequency run time, it would keep sleep
+*                      routines in sync with Microblaze frequency.
+*                      Added Xil_GetMBFrequency to read current Microbalze frequency.
+*                      It fixes CR#1094568.
+* 7.6   mus  08/23/21  Updated prototypes for functions which are not taking any
+*                      arguments with void keyword. This has been done to fix
+*                      compilation warnings with "-Wstrict-prototypes" flag.
+*                      It fixes CR#1108601.
+*
+* </pre>
+*
+* @note
+* The microblaze_sleep.h file may contain architecture-dependent items.
+*
+******************************************************************************/
+
+/**
+ *@cond nocomments
+ */
+#ifndef MICROBLAZE_SLEEP_H		/* prevent circular inclusions */
+#define MICROBLAZE_SLEEP_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "mb_interface.h"
+#include "xparameters.h"
+#include "sleep.h"
+
+/************************** Constant Definitions *****************************/
+
+#if defined (XSLEEP_TIMER_IS_AXI_TIMER)
+
+/** @name Register Offset Definitions
+ * Register offsets within the Axi timer counter, there are multiple
+ * timer counters within a single device
+ * @{
+ */
+#define XSLEEP_TIMER_AXITIMER_TCSR0_OFFSET	0U	/**< Control/Status register */
+#define XSLEEP_TIMER_AXITIMER_TLR_OFFSET	4U	/**< Load register */
+#define XSLEEP_TIMER_AXITIMER_TCR_OFFSET	8U	/**< Timer counter register */
+/* @} */
+
+/** @name Control Status Register Bit Definitions
+ * Control Status Register bit masks
+ * Used to configure the Axi timer counter device.
+ * @{
+ */
+#define XSLEEP_TIMER_AXITIMER_CSR_ENABLE_TMR_MASK	0x00000080U
+				 /**< Enables only the specific timer */
+#define XSLEEP_TIMER_AXITIMER_CSR_AUTO_RELOAD_MASK	0x00000010U
+			         /**< In compare mode, configures the timer
+ *                                    counter to  reload from the Load Register.
+ *                                    The default mode causes the timer counter
+ *                                    to hold when the compare value is hit. In
+ *                                    capture mode, configures the timer counter
+ *                                    to not hold the previous capture value if
+ *                                    a new event occurs. The default mode cause
+ *                                   the timer counter to hold the capture value
+ *                                    until recognized.*/
+#define XSLEEP_TIMER_AXITIMER_CSR_LOAD_MASK		0x00000020U
+				 /**< Loads the timer using the  load value
+ *                                    provided earlier in the Load Register,
+ *                                    XSLEEP_TIMER_AXITIMER_TLR_OFFSET. */
+#define XSLEEP_TIMER_AXITIMER_CSR_INT_OCCURED_MASK	0x00000100U
+				 /**< If bit is set, an interrupt has occurred.
+ *                                    If set and '1' is written to this bit
+ *                                    position, bit is cleared.*/
+#define XSLEEP_TIMER_AXITIMER_CSR_ENABLE_TMR_MASK   0x00000080U
+				 /**< Enables only the specific timer */
+/* @} */
+
+/**************************** Type Definitions *******************************/
+/************************** Function Prototypes ******************************/
+
+static void Xil_SleepAxiTimer(u32 delay, u64 frequency);
+static void XTime_StartAxiTimer(void);
+#else
+u32 Xil_SetMBFrequency(u32 Val);
+u32 Xil_GetMBFrequency(void);
+#endif
+/**
+ *@endcond
+ */
+void MB_Sleep(u32 MilliSeconds) __attribute__((__deprecated__));
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup microblaze_sleep_routines".
+*/

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/microblaze_ps/standalone_domain/bsp/microblaze_ps/include/pm_api_version.h

@@ -0,0 +1,269 @@
+/******************************************************************************
+* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+ * @file pm_api_version.h
+ *
+ * @addtogroup xpm_versal_apis XilPM APIs
+ *****************************************************************************/
+
+
+#ifndef PM_API_VERSION_H_
+#define PM_API_VERSION_H_
+
+/*****************************************************************************/
+/**
+ * @section EEMI_API_DETAIL XilPM EEMI API Version Detail
+ *
+ * This section provides details of EEMI API version and it's history for PM APIs of XilPM library.
+ *
+ * | NAME			| ID	| Platform	| Version| Description								     |
+ * |----------------------------|-------|---------------|:------:|---------------------------------------------------------------------------|
+ * | PM_GET_API_VERSION		| 0x1   | Both		| 1	 | The API is used to request the version number of the API		     |
+ * | PM_SET_CONFIGURATION	| 0x2	| ZynqMP	| 1	 | The API is used to configure the power management framework		     |
+ * | ^				| ^	| ^		| ^	 | Note: Deprecated in Versal but supported in ZynqMP			     |
+ * | PM_GET_NODE_STATUS		| 0x3	| Both		| 1	 | The API is used to obtain information about current status of a device    |
+ * | PM_GET_OP_CHARACTERISTIC	| 0x4	| Both		| 2	 | V1 - The API is used to get operating characteristics of a device	     |
+ * | ^				| ^	| ^		| ^	 | V2 - Added support of bitmask functionality, user can check the supported\n									"type" first before performing the actual functionality				       |
+ * | PM_REGISTER_NOTIFIER	| 0x5	| Both		| 2	 | V1 - The API is used to register a subsystem to be notified about the\n									device event									       |
+ * | ^				| ^	| ^		| ^	 | V2 - Added support of event management functionality			     |
+ * | ^				| ^	| ^		| ^	 | Note: V2 is supported in Versal but ZynqMP supports only V1		     |
+ * | PM_REQUEST_SUSPEND		| 0x6	| Both		| 1	 | The API is used to send suspend request to another subsystem		     |
+ * | PM_SELF_SUSPEND		| 0x7	| Both		| 2	 | V1 - The API is used to suspend a child subsystem			     |
+ * | ^				| ^	| ^		| ^	 | V2 - Added support of cpu idle functionality during force powerdown	     |
+ * | ^				| ^	| ^		| ^	 | Note: V2 is supported in Versal but ZynqMP supports only V1		     |
+ * | PM_FORCE_POWERDOWN		| 0x8	| Both		| 2	 | V1 - The API is used to Powerdown other processor or node		     |
+ * | ^				| ^	| ^		| ^	 | V2 - Added support of cpu idle functionality	during force powerdown	     |
+ * | ^				| ^	| ^		| ^	 | Note: V2 is supported in Versal but ZynqMP supports only V1		     |
+ * | PM_ABORT_SUSPEND		| 0x9	| Both		| 1	 | The API is used by a subsystem to abort suspend of a child subsystem	     |
+ * | PM_REQUEST_WAKEUP		| 0xA	| Both		| 1	 | The API is used to start-up and wake-up a child subsystem		     |
+ * | PM_SET_WAKEUP_SOURCE	| 0xB	| Both		| 1	 | The API is used to set wakeup source					     |
+ * | PM_SYSTEM_SHUTDOWN		| 0xC	| Both		| 1	 | The API is used to shutdown or restart the system			     |
+ * | PM_REQUEST_NODE		| 0xD	| Both		| 2	 | V1 - The API is used to request the usage of a device		     |
+ * | ^				| ^	| ^		| ^	 | V2 - Added support of security policy handling during request device	     |
+ * | ^				| ^	| ^		| ^	 | Note: V2 is supported in Versal but ZynqMP supports only V1		     |
+ * | PM_RELEASE_NODE		| 0xE	| Both		| 2	 | V1 - The API is used to release the usage of a device		     |
+ * | ^				| ^	| ^		| ^	 | V2 - Added support of security policy handling during request device      |
+ * | ^				| ^	| ^		| ^	 | Note: V2 is supported in Versal but ZynqMP supports only V1		     |
+ * | PM_SET_REQUIREMENT		| 0xF	| Both		| 1	 | The API is used to announce a change in requirement for a specific slave\n									node which is currently in use							       |
+ * | PM_SET_MAX_LATENCY		| 0x10	| Both		| 1	 | The API is used to set maximum allowed latency for the device	     |
+ * | PM_RESET_ASSERT		| 0x11	| Both		| 1	 | The API is used to reset or de-reset a device			     |
+ * | PM_RESET_GET_STATUS	| 0x12	| Both		| 1	 | The API is used to read the device reset state			     |
+ * | PM_MMIO_WRITE		| 0x13	| ZynqMP	| 1	 | The API is used to write a value into a register			     |
+ * | ^				| ^	| ^		| ^	 | Note: Deprecated in Versal but supported in ZynqMP			     |
+ * | PM_MMIO_READ		| 0x14	| ZynqMP	| 1	 | The API is used to read a value from a register			     |
+ * | ^				| ^	| ^		| ^	 | Note: Deprecated in Versal but supported in ZynqMP			     |
+ * | PM_INIT_FINALIZE		| 0x15	| Both		| 1	 | The API is used to initialize subsystem and release unused devices	     |
+ * | PM_GET_CHIPID		| 0x18	| Both		| 1	 | The API is used to request the version and ID code of a chip		     |
+ * | PM_PINCTRL_REQUEST		| 0x1C	| Both		| 1	 | The API is used to request the pin					     |
+ * | PM_PINCTRL_RELEASE		| 0x1D	| Both		| 1	 | The API is used to release the pin					     |
+ * | PM_PINCTRL_GET_FUNCTION	| 0x1E	| Both		| 1	 | The API is used to read the pin function				     |
+ * | PM_PINCTRL_SET_FUNCTION	| 0x1F	| Both		| 1	 | The API is used to set the pin function				     |
+ * | PM_PINCTRL_CONFIG_PARAM_GET| 0x20	| Both		| 1	 | The API is used to read the pin parameter value			     |
+ * | PM_PINCTRL_CONFIG_PARAM_SET| 0x21	| Both		| 2	 | V1 - The API is used to set the pin parameter value			     |
+ * | ^				| ^	| ^		| ^	 | V2 - Added support of MIO tri-state controlling functionality	     |
+ * | ^				| ^	| ^		| ^	 | Note: V2 is supported in ZynqMP but Versal supports only V1		     |
+ * | PM_IOCTL			| 0x22	| Both		| 3	 | V1 - The API is used to perform driver-like IOCTL functions on shared\n									system devices									       |
+ * | ^				| ^	| ^		| ^	 | V2 - Added support of bitmask functionality, user can check the supported\n									ID first before performing the actual functionality				       |
+ * | ^				| ^	| ^		| ^	 | V3 - Add support of zeroization of AIE data and program memory separately |
+ * | ^				| ^	| ^		| ^	 | Note: V3 is supported in Versal but ZynqMP supports only V2	             |
+ * | PM_QUERY_DATA		| 0x23	| Both		| 2	 | V1 - The API is used to query information about the platform resources  |
+ * | ^				| ^	| ^		| ^	 | V2 - Added support of bitmask functionality, user can check the supported\n									ID first before performing the actual functionality				       |
+ * | PM_CLOCK_ENABLE		| 0x24	| Both		| 1	 | The API is used to enable the clock					     |
+ * | PM_CLOCK_DISABLE		| 0x25	| Both		| 1	 | The API is used to disable the clock					     |
+ * | PM_CLOCK_GETSTATE		| 0x26	| Both		| 1	 | The API is used to read the clock state				     |
+ * | PM_CLOCK_SETDIVIDER	| 0x27	| Both		| 1	 | The API is used to set the divider value of the clock		     |
+ * | PM_CLOCK_GETDIVIDER	| 0x28	| Both		| 1	 | The API is used to read the clock divider				     |
+ * | PM_CLOCK_SETPARENT		| 0x2B	| Both		| 1	 | The API is used to set the parent of the clock			     |
+ * | PM_CLOCK_GETPARENT		| 0x2C	| Both		| 1	 | The API is used to read the clock parent				     |
+ * | PM_PLL_SET_PARAM		| 0x30	| Both		| 1	 | The API is used to set the parameter of PLL clock			     |
+ * | PM_PLL_GET_PARAM		| 0x31	| Both		| 1	 | The API is used to read the parameter of PLL clock			     |
+ * | PM_PLL_SET_MODE		| 0x32	| Both		| 1	 | The API is used to set the mode of PLL clock				     |
+ * | PM_PLL_GET_MODE		| 0x33	| Both		| 1	 | The API is used to read the mode of PLL clock			     |
+ * | PM_REGISTER_ACCESS		| 0x34	| ZynqMP	| 1	 | The API is used for register read/write access data			     |
+ * | ^				| ^	| ^		| ^	 | Note: Deprecated in Versal but supported in ZynqMP			     |
+ * | PM_EFUSE_ACCESS		| 0x35	| ZynqMP	| 1	 | The API is used to provide access to efuse memory			     |
+ * | ^				| ^	| ^		| ^	 | Note: Deprecated in Versal but supported in ZynqMP			     |
+ * | PM_FEATURE_CHECK		| 0x3F	| Both		| 2	 | V1 - The API is used to return supported version of the given API	     |
+ * | ^				| ^	| ^		| ^	 | V2 - Added support of bitmask payload functionality			     |
+ *
+ *****************************************************************************/
+
+/*****************************************************************************/
+/**
+ * @section IOCTL_ID_DETAIL XilPM IOCTL IDs Detail
+ *
+ * This section provides the details of the IOCTL IDs which are supported across the different platforms and their brief descriptions.
+ *
+ * | Name				| ID	| Platform	| Description				|
+ * |------------------------------------|-------|---------------|---------------------------------------|
+ * | IOCTL_GET_RPU_OPER_MODE		| 0	| Both		| Get RPU mode				|
+ * | IOCTL_SET_RPU_OPER_MODE		| 1	| Both		| Set RPU mode				|
+ * | IOCTL_RPU_BOOT_ADDR_CONFIG		| 2	| Both		| RPU boot address config		|
+ * | IOCTL_TCM_COMB_CONFIG		| 3	| Both		| TCM config				|
+ * | IOCTL_SET_TAPDELAY_BYPASS		| 4	| Both		| TAP delay bypass			|
+ * | IOCTL_SET_SGMII_MODE		| 5	| ZynqMP	| SGMII mode				|
+ * | IOCTL_SD_DLL_RESET			| 6	| Both		| SD DLL reset				|
+ * | IOCTL_SET_SD_TAPDELAY		| 7	| Both		| SD TAP delay				|
+ * | IOCTL_SET_PLL_FRAC_MODE		| 8	| Both		| Set PLL frac mode			|
+ * | IOCTL_GET_PLL_FRAC_MODE		| 9	| Both		| Get PLL frac mode			|
+ * | IOCTL_SET_PLL_FRAC_DATA		| 10	| Both		| Set PLL frac data			|
+ * | IOCTL_GET_PLL_FRAC_DATA		| 11	| Both		| Get PLL frac data			|
+ * | IOCTL_WRITE_GGS			| 12	| Both		| Write GGS				|
+ * | IOCTL_READ_GGS			| 13	| Both		| Read GGS				|
+ * | IOCTL_WRITE_PGGS			| 14	| Both		| Write PGGS				|
+ * | IOCTL_READ_PGGS			| 15	| Both		| Read PGGS				|
+ * | IOCTL_ULPI_RESET			| 16	| ZynqMP	| ULPI reset				|
+ * | IOCTL_SET_BOOT_HEALTH_STATUS	| 17	| Both		| Set boot status			|
+ * | IOCTL_AFI				| 18	| ZynqMP	| AFI					|
+ * | IOCTL_PROBE_COUNTER_READ		| 19	| Versal	| Probe counter read			|
+ * | IOCTL_PROBE_COUNTER_WRITE		| 20	| Versal	| Probe counter write			|
+ * | IOCTL_OSPI_MUX_SELECT		| 21	| Versal	| OSPI mux select			|
+ * | IOCTL_USB_SET_STATE		| 22	| Versal	| USB set state				|
+ * | IOCTL_GET_LAST_RESET_REASON	| 23	| Versal	| Get last reset reason			|
+ * | IOCTL_AIE_ISR_CLEAR		| 24	| Versal	| AIE ISR clear				|
+ * | IOCTL_REGISTER_SGI			| 25	| None		| Register SGI to ATF			|
+ * | IOCTL_SET_FEATURE_CONFIG		| 26	| ZynqMP	| Set runtime feature config		|
+ * | IOCTL_GET_FEATURE_CONFIG		| 27	| ZynqMP	| Get runtime feature config		|
+ * | IOCTL_READ_REG			| 28	| Versal	| Read a 32-bit register		|
+ * | IOCTL_MASK_WRITE_REG		| 29	| Versal	| RMW a 32-bit register			|
+ * | IOCTL_SET_SD_CONFIG		| 30	| ZynqMP	| Set SD config register value		|
+ * | IOCTL_SET_GEM_CONFIG		| 31	| ZynqMP	| Set GEM config register value		|
+ * | IOCTL_SET_USB_CONFIG		| 32	| ZynqMP	| Set USB config register value		|
+ * | IOCTL_AIE_OPS			| 33	| Versal	| AIE1/AIEML Run Time Operations	|
+ * | IOCTL_GET_QOS			| 34	| Versal	| Get Device QoS value			|
+ * | IOCTL_GET_APU_OPER_MODE		| 35	| Versal	| Get APU operation mode		|
+ * | IOCTL_SET_APU_OPER_MODE		| 36	| Versal	| Set APU operation mode		|
+ * | IOCTL_PREPARE_DDR_SHUTDOWN		| 37	| Versal	| Prepare DDR for shut down		|
+ * | IOCTL_GET_SSIT_TEMP		| 38	| Versal	| Get secondary SLR min/max temperature |
+ *
+ *****************************************************************************/
+
+/*****************************************************************************/
+/**
+ * @section QUERY_ID_DETAIL XilPM QUERY IDs Detail
+ *
+ * This section provides the details of the QUERY IDs which are supported across the different platforms and their brief descriptions.
+ *
+ * | Name					| ID	| Platform	| Description				|
+ * |--------------------------------------------|-------|---------------|---------------------------------------|
+ * | XPM_QID_INVALID				| 0	| Both		| Invalid Query ID			|
+ * | XPM_QID_CLOCK_GET_NAME			| 1	| Both		| Get clock name			|
+ * | XPM_QID_CLOCK_GET_TOPOLOGY			| 2	| Both		| Get clock topology			|
+ * | XPM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS	| 3	| Both		| Get clock fixedfactor parameter	|
+ * | XPM_QID_CLOCK_GET_MUXSOURCES		| 4	| Both		| Get clock mux sources			|
+ * | XPM_QID_CLOCK_GET_ATTRIBUTES		| 5	| Both		| Get clock attributes			|
+ * | XPM_QID_PINCTRL_GET_NUM_PINS		| 6	| Both		| Get total pins			|
+ * | XPM_QID_PINCTRL_GET_NUM_FUNCTIONS		| 7	| Both		| Get total pin functions		|
+ * | XPM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS	| 8	| Both		| Get total pin function groups		|
+ * | XPM_QID_PINCTRL_GET_FUNCTION_NAME		| 9	| Both		| Get pin function name			|
+ * | XPM_QID_PINCTRL_GET_FUNCTION_GROUPS	| 10	| Both		| Get pin function groups		|
+ * | XPM_QID_PINCTRL_GET_PIN_GROUPS		| 11	| Both		| Get pin groups			|
+ * | XPM_QID_CLOCK_GET_NUM_CLOCKS		| 12	| Both		| Get number of clocks			|
+ * | XPM_QID_CLOCK_GET_MAX_DIVISOR		| 13	| Both		| Get max clock divisor			|
+ * | XPM_QID_PLD_GET_PARENT			| 14	| Versal	| Get PLD parent			|
+ * | XPM_QID_PINCTRL_GET_ATTRIBUTES		| 15	| Versal	| Get pin attributes			|
+ *
+ *****************************************************************************/
+
+
+/*****************************************************************************/
+/**
+ * @section GET_OP_CHAR_DETAIL XilPM GET_OP_CHAR IDs Detail
+ *
+ * This section provides the details of the GET_OP_CHAR IDs which are supported across the different platforms and their brief descriptions.
+ *
+ * | Name				| ID	| Platform	| Description					|
+ * |------------------------------------|-------|---------------|-----------------------------------------------|
+ * | PM_OPCHAR_TYPE_POWER		| 1	| ZynqMP	| Operating characteristic ID power		|
+ * | PM_OPCHAR_TYPE_TEMP		| 2	| Versal	| Operating characteristic ID temperature	|
+ * | PM_OPCHAR_TYPE_LATENCY		| 3	| Both		| Operating characteristic ID latency		|
+ *
+ *****************************************************************************/
+
+
+/**
+ * PM API IDs
+ */
+typedef enum {
+	PM_API_MIN,					/**< 0x0 */
+	PM_GET_API_VERSION,				/**< 0x1 */
+	PM_SET_CONFIGURATION,				/**< 0x2 */
+	PM_GET_NODE_STATUS,				/**< 0x3 */
+	PM_GET_OP_CHARACTERISTIC,			/**< 0x4 */
+	PM_REGISTER_NOTIFIER,				/**< 0x5 */
+	PM_REQUEST_SUSPEND,				/**< 0x6 */
+	PM_SELF_SUSPEND,				/**< 0x7 */
+	PM_FORCE_POWERDOWN,				/**< 0x8 */
+	PM_ABORT_SUSPEND,				/**< 0x9 */
+	PM_REQUEST_WAKEUP,				/**< 0xA */
+	PM_SET_WAKEUP_SOURCE,				/**< 0xB */
+	PM_SYSTEM_SHUTDOWN,				/**< 0xC */
+	PM_REQUEST_NODE,				/**< 0xD */
+	PM_RELEASE_NODE,				/**< 0xE */
+	PM_SET_REQUIREMENT,				/**< 0xF */
+	PM_SET_MAX_LATENCY,				/**< 0x10 */
+	PM_RESET_ASSERT,				/**< 0x11 */
+	PM_RESET_GET_STATUS,				/**< 0x12 */
+	PM_MMIO_WRITE,					/**< 0x13 */
+	PM_MMIO_READ,					/**< 0x14 */
+	PM_INIT_FINALIZE,				/**< 0x15 */
+	PM_FPGA_LOAD,					/**< 0x16 */
+	PM_FPGA_GET_STATUS,				/**< 0x17 */
+	PM_GET_CHIPID,					/**< 0x18 */
+	PM_SECURE_RSA_AES,				/**< 0x19 */
+	PM_SECURE_SHA,					/**< 0x1A */
+	PM_SECURE_RSA,					/**< 0x1B */
+	PM_PINCTRL_REQUEST,				/**< 0x1C */
+	PM_PINCTRL_RELEASE,				/**< 0x1D */
+	PM_PINCTRL_GET_FUNCTION,			/**< 0x1E */
+	PM_PINCTRL_SET_FUNCTION,			/**< 0x1F */
+	PM_PINCTRL_CONFIG_PARAM_GET,			/**< 0x20 */
+	PM_PINCTRL_CONFIG_PARAM_SET,			/**< 0x21 */
+	PM_IOCTL,					/**< 0x22 */
+	PM_QUERY_DATA,					/**< 0x23 */
+	PM_CLOCK_ENABLE,				/**< 0x24 */
+	PM_CLOCK_DISABLE,				/**< 0x25 */
+	PM_CLOCK_GETSTATE,				/**< 0x26 */
+	PM_CLOCK_SETDIVIDER,				/**< 0x27 */
+	PM_CLOCK_GETDIVIDER,				/**< 0x28 */
+	PM_CLOCK_SETRATE,				/**< 0x29 */
+	PM_CLOCK_GETRATE,				/**< 0x2A */
+	PM_CLOCK_SETPARENT,				/**< 0x2B */
+	PM_CLOCK_GETPARENT,				/**< 0x2C */
+	PM_SECURE_IMAGE,				/**< 0x2D */
+	PM_FPGA_READ,					/**< 0x2E */
+	PM_SECURE_AES,					/**< 0x2F */
+	PM_PLL_SET_PARAMETER,				/**< 0x30 */
+	PM_PLL_GET_PARAMETER,				/**< 0x31 */
+	PM_PLL_SET_MODE,				/**< 0x32 */
+	PM_PLL_GET_MODE,				/**< 0x33 */
+	PM_REGISTER_ACCESS,				/**< 0x34 */
+	PM_EFUSE_ACCESS,				/**< 0x35 */
+	PM_ADD_SUBSYSTEM,				/**< 0x36 */
+	PM_DESTROY_SUBSYSTEM,				/**< 0x37 */
+	PM_DESCRIBE_NODES,				/**< 0x38 */
+	PM_ADD_NODE,					/**< 0x39 */
+	PM_ADD_NODE_PARENT,				/**< 0x3A */
+	PM_ADD_NODE_NAME,				/**< 0x3B */
+	PM_ADD_REQUIREMENT,				/**< 0x3C */
+	PM_SET_CURRENT_SUBSYSTEM,			/**< 0x3D */
+	PM_INIT_NODE,					/**< 0x3E */
+	PM_FEATURE_CHECK,				/**< 0x3F */
+	PM_ISO_CONTROL,					/**< 0x40 */
+	PM_ACTIVATE_SUBSYSTEM,				/**< 0x41 */
+	PM_SET_NODE_ACCESS,				/**< 0x42 */
+	PM_BISR,					/**< 0x43 */
+	PM_APPLY_TRIM,					/**< 0x44 */
+	PM_NOC_CLOCK_ENABLE,				/**< 0x45 */
+	PM_IF_NOC_CLOCK_ENABLE,				/**< 0x46 */
+	PM_FORCE_HOUSECLEAN,				/**< 0x47 */
+	PM_FPGA_GET_VERSION,				/**< 0x48 */
+	PM_FPGA_GET_FEATURE_LIST,			/**< 0x49 */
+	PM_API_MAX					/**< 0x4A */
+} XPm_ApiId;
+
+#endif  /* PM_API_VERSION_H_ */

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/microblaze_ps/standalone_domain/bsp/microblaze_ps/include/profile.h

@@ -0,0 +1,105 @@
+/******************************************************************************
+* Copyright (c) 2002 - 2020 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+
+#ifndef	PROFILE_H
+#define	PROFILE_H	1
+
+#include <stdio.h>
+#include "xil_types.h"
+#include "profile_config.h"
+
+#ifdef PROC_MICROBLAZE
+#include "mblaze_nt_types.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void _system_init( void ) ;
+void _system_clean( void ) ;
+void mcount(u32 frompc, u32 selfpc);
+void profile_intr_handler( void ) ;
+void _profile_init( void );
+
+
+
+/****************************************************************************
+ * Profiling on hardware - Hash table maintained on hardware and data sent
+ * to xmd for gmon.out generation.
+ ****************************************************************************/
+/*
+ * histogram counters are unsigned shorts (according to the kernel).
+ */
+#define	HISTCOUNTER	u16
+
+struct tostruct {
+	u32  selfpc;
+	s32	 count;
+	s16  link;
+	u16	 pad;
+};
+
+struct fromstruct {
+	u32 frompc ;
+	s16 link ;
+	u16 pad ;
+} ;
+
+/*
+ * general rounding functions.
+ */
+#define ROUNDDOWN(x,y)	(((x)/(y))*(y))
+#define ROUNDUP(x,y)	((((x)+(y)-1)/(y))*(y))
+
+/*
+ * The profiling data structures are housed in this structure.
+ */
+struct gmonparam {
+	s32		state;
+
+	/* Histogram Information */
+	u16		*kcount;	/* No. of bins in histogram */
+	u32		kcountsize;	/* Histogram samples */
+
+	/* Call-graph Information */
+	struct fromstruct	*froms;
+	u32		fromssize;
+	struct tostruct		*tos;
+	u32		tossize;
+
+	/* Initialization I/Ps */
+	u32    	lowpc;
+	u32		highpc;
+	u32		textsize;
+	/* u32 		cg_froms, */
+	/* u32 		cg_tos, */
+};
+extern struct gmonparam *_gmonparam;
+extern s32 n_gmon_sections;
+
+/*
+ * Possible states of profiling.
+ */
+#define	GMON_PROF_ON	0
+#define	GMON_PROF_BUSY	1
+#define	GMON_PROF_ERROR	2
+#define	GMON_PROF_OFF	3
+
+/*
+ * Sysctl definitions for extracting profiling information from the kernel.
+ */
+#define	GPROF_STATE	0	/* int: profiling enabling variable */
+#define	GPROF_COUNT	1	/* struct: profile tick count buffer */
+#define	GPROF_FROMS	2	/* struct: from location hash bucket */
+#define	GPROF_TOS	3	/* struct: destination/count structure */
+#define	GPROF_GMONPARAM	4	/* struct: profiling parameters (see above) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 		/* PROFILE_H */

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/microblaze_ps/standalone_domain/bsp/microblaze_ps/include/pvr.h

@@ -0,0 +1,527 @@
+/******************************************************************************
+* Copyright (c) 2006 - 2022 Xilinx, Inc.  All rights reserved.
+* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file pvr.h
+*
+* @addtogroup microblaze_pvr_macros Microblaze PVR access routines and macros
+*
+* MicroBlaze processor v5.00.a and later versions have configurable
+* Processor Version Registers (PVRs). The contents of the PVR are captured
+* using the pvr_t data structure, which is defined as an array of 32-bit words,
+* with each word corresponding to a PVR register on hardware. The number of PVR
+* words is determined by the number of PVRs configured in the hardware. You should
+* not attempt to access PVR registers that are not present in hardware, as the
+* pvr_t data structure is resized to hold only as many PVRs as are present in
+* hardware.
+* To access information in the PVR:
+* 1. Use the microblaze_get_pvr() function to populate the PVR data into a pvr_t
+*    data structure.
+* 2. In subsequent steps, you can use any one of the PVR access macros list to
+*    get individual data stored in the PVR.
+* 3. pvr.h header file must be included to source to use PVR macros.
+*
+* @{
+*
+******************************************************************************/
+/**
+ *@cond nocomments
+ */
+
+#ifndef PVR_H
+#define PVR_H
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "mb_interface.h"
+#include "bspconfig.h"
+#ifndef SDT
+#include "xparameters.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Defs */
+typedef struct pvr_s {
+#ifdef MICROBLAZE_PVR_FULL
+  u32  pvr[16];
+#else
+  u32  pvr[1];
+#endif
+} pvr_t;
+
+
+#define getpvr(pvrid, val)      asm volatile ("mfs\t%0,rpvr" stringify(pvrid) "\n\t" : "=d" (val))
+
+/* Basic PVR mask */
+#define MICROBLAZE_PVR0_PVR_FULL_MASK               0x80000000U
+#define MICROBLAZE_PVR0_USE_BARREL_MASK             0x40000000
+#define MICROBLAZE_PVR0_USE_DIV_MASK                0x20000000
+#define MICROBLAZE_PVR0_USE_HW_MUL_MASK             0x10000000
+#define MICROBLAZE_PVR0_USE_FPU_MASK                0x08000000
+#define MICROBLAZE_PVR0_USE_EXCEPTION_MASK          0x04000000
+#define MICROBLAZE_PVR0_USE_ICACHE_MASK             0x02000000
+#define MICROBLAZE_PVR0_USE_DCACHE_MASK             0x01000000
+#define MICROBLAZE_PVR0_USE_MMU_MASK                0x00800000
+#define MICROBLAZE_PVR0_USE_BTC_MASK                0x00400000
+#define MICROBLAZE_PVR0_ENDIANNESS_MASK             0x00200000
+#define MICROBLAZE_PVR0_FAULT_TOLERANT_MASK         0x00100000
+#define MICROBLAZE_PVR0_STACK_PROTECTION_MASK       0x00080000
+#define MICROBLAZE_PVR0_MICROBLAZE_VERSION_MASK     0x0000FF00
+#define MICROBLAZE_PVR0_USER1_MASK                  0x000000FF
+
+/* User 2 PVR mask */
+#define MICROBLAZE_PVR1_USER2_MASK                  0xFFFFFFFFU
+
+/* Configuration PVR masks */
+#define MICROBLAZE_PVR2_D_AXI_MASK                  0x80000000U
+#define MICROBLAZE_PVR2_D_LMB_MASK                  0x40000000
+#define MICROBLAZE_PVR2_D_PLB_MASK                  0x02000000
+#define MICROBLAZE_PVR2_I_AXI_MASK                  0x20000000
+#define MICROBLAZE_PVR2_I_LMB_MASK                  0x10000000
+#define MICROBLAZE_PVR2_I_PLB_MASK                  0x01000000
+#define MICROBLAZE_PVR2_INTERRUPT_IS_EDGE_MASK      0x08000000
+#define MICROBLAZE_PVR2_EDGE_IS_POSITIVE_MASK       0x04000000
+#define MICROBLAZE_PVR2_INTERCONNECT_MASK           0x00800000
+#define MICROBLAZE_PVR2_STREAM_INTERCONNECT_MASK    0x00400000
+#define MICROBLAZE_PVR2_USE_EXTENDED_FSL_INSTR_MASK 0x00080000
+#define MICROBLAZE_PVR2_USE_MSR_INSTR_MASK          0x00020000
+#define MICROBLAZE_PVR2_USE_PCMP_INSTR_MASK         0x00010000
+#define MICROBLAZE_PVR2_AREA_OPTIMIZED_MASK         0x00008000
+#define MICROBLAZE_PVR2_USE_BARREL_MASK             0x00004000
+#define MICROBLAZE_PVR2_USE_DIV_MASK                0x00002000
+#define MICROBLAZE_PVR2_USE_HW_MUL_MASK             0x00001000
+#define MICROBLAZE_PVR2_USE_FPU_MASK                0x00000800
+#define MICROBLAZE_PVR2_USE_FPU2_MASK               0x00000200
+#define MICROBLAZE_PVR2_USE_MUL64_MASK              0x00000400
+#define MICROBLAZE_PVR2_OPCODE_0x0_ILLEGAL_MASK     0x00000040
+#define MICROBLAZE_PVR2_UNALIGNED_EXCEPTION_MASK    0x00000020
+#define MICROBLAZE_PVR2_ILL_OPCODE_EXCEPTION_MASK   0x00000010
+#define MICROBLAZE_PVR2_M_AXI_I_BUS_EXCEPTION_MASK  0x00000008
+#define MICROBLAZE_PVR2_M_AXI_D_BUS_EXCEPTION_MASK  0x00000004
+#define MICROBLAZE_PVR2_IPLB_BUS_EXCEPTION_MASK     0x00000100
+#define MICROBLAZE_PVR2_DPLB_BUS_EXCEPTION_MASK     0x00000080
+#define MICROBLAZE_PVR2_DIV_ZERO_EXCEPTION_MASK     0x00000002
+#define MICROBLAZE_PVR2_FPU_EXCEPTION_MASK          0x00000001
+#define MICROBLAZE_PVR2_FSL_EXCEPTION_MASK          0x00040000
+
+/* Debug and exception PVR masks */
+#define MICROBLAZE_PVR3_DEBUG_ENABLED_MASK          0x80000000U
+#define MICROBLAZE_PVR3_NUMBER_OF_PC_BRK_MASK       0x1E000000
+#define MICROBLAZE_PVR3_NUMBER_OF_RD_ADDR_BRK_MASK  0x00380000
+#define MICROBLAZE_PVR3_NUMBER_OF_WR_ADDR_BRK_MASK  0x0000E000
+#define MICROBLAZE_PVR3_FSL_LINKS_MASK              0x00000380
+#define MICROBLAZE_PVR3_BTC_SIZE_MASK               0x00000007
+
+/* ICache config PVR masks */
+#define MICROBLAZE_PVR4_USE_ICACHE_MASK              0x80000000U
+#define MICROBLAZE_PVR4_ICACHE_ADDR_TAG_BITS_MASK    0x7C000000
+#define MICROBLAZE_PVR4_ICACHE_ALLOW_WR_MASK         0x01000000
+#define MICROBLAZE_PVR4_ICACHE_LINE_LEN_MASK         0x00E00000
+#define MICROBLAZE_PVR4_ICACHE_BYTE_SIZE_MASK        0x001F0000
+#define MICROBLAZE_PVR4_ICACHE_ALWAYS_USED_MASK      0x00008000
+#define MICROBLAZE_PVR4_ICACHE_INTERFACE_MASK        0x00002000
+#define MICROBLAZE_PVR4_ICACHE_VICTIMS_MASK          0x00001C00
+#define MICROBLAZE_PVR4_ICACHE_STREAMS_MASK          0x00000300
+#define MICROBLAZE_PVR4_ICACHE_FORCE_TAG_LUTRAM_MASK 0x00000080
+#define MICROBLAZE_PVR4_ICACHE_DATA_WIDTH_MASK       0x00000040
+
+/* DCache config PVR masks */
+#define MICROBLAZE_PVR5_USE_DCACHE_MASK              0x80000000U
+#define MICROBLAZE_PVR5_DCACHE_ADDR_TAG_BITS_MASK    0x7C000000
+#define MICROBLAZE_PVR5_DCACHE_ALLOW_WR_MASK         0x01000000
+#define MICROBLAZE_PVR5_DCACHE_LINE_LEN_MASK         0x00E00000
+#define MICROBLAZE_PVR5_DCACHE_BYTE_SIZE_MASK        0x001F0000
+#define MICROBLAZE_PVR5_DCACHE_ALWAYS_USED_MASK      0x00008000
+#define MICROBLAZE_PVR5_DCACHE_USE_WRITEBACK_MASK    0x00004000
+#define MICROBLAZE_PVR5_DCACHE_INTERFACE_MASK        0x00002000
+#define MICROBLAZE_PVR5_DCACHE_VICTIMS_MASK          0x00001C00
+#define MICROBLAZE_PVR5_DCACHE_FORCE_TAG_LUTRAM_MASK 0x00000080
+#define MICROBLAZE_PVR5_DCACHE_DATA_WIDTH_MASK       0x00000040
+
+#if defined(__arch64__)
+/* ICache base address PVR mask */
+#define MICROBLAZE_PVR6_ICACHE_BASEADDR_MASK        0xFFFFFFFFFFFFFFFFU
+
+/* ICache high address PVR mask */
+#define MICROBLAZE_PVR7_ICACHE_HIGHADDR_MASK        0xFFFFFFFFFFFFFFFFU
+
+/* DCache base address PVR mask */
+#define MICROBLAZE_PVR8_DCACHE_BASEADDR_MASK        0xFFFFFFFFFFFFFFFFU
+
+/* DCache high address PVR mask */
+#define MICROBLAZE_PVR9_DCACHE_HIGHADDR_MASK        0xFFFFFFFFFFFFFFFFU
+
+#else
+/* ICache base address PVR mask */
+#define MICROBLAZE_PVR6_ICACHE_BASEADDR_MASK        0xFFFFFFFFU
+
+/* ICache high address PVR mask */
+#define MICROBLAZE_PVR7_ICACHE_HIGHADDR_MASK        0xFFFFFFFFU
+
+/* DCache base address PVR mask */
+#define MICROBLAZE_PVR8_DCACHE_BASEADDR_MASK        0xFFFFFFFFU
+
+/* DCache high address PVR mask */
+#define MICROBLAZE_PVR9_DCACHE_HIGHADDR_MASK        0xFFFFFFFFU
+#endif
+
+/* Target family PVR mask */
+#define MICROBLAZE_PVR10_TARGET_FAMILY_MASK         0xFF000000U
+
+/* MSR Reset value PVR mask */
+#define MICROBLAZE_PVR11_MSR_RESET_VALUE_MASK       0x000007FF
+
+/* MMU value PVR mask */
+#define MICROBLAZE_PVR11_MMU_MASK                   0xC0000000U
+#define MICROBLAZE_PVR11_MMU_ITLB_SIZE_MASK         0x38000000
+#define MICROBLAZE_PVR11_MMU_DTLB_SIZE_MASK         0x07000000
+#define MICROBLAZE_PVR11_MMU_TLB_ACCESS_MASK        0x00C00000
+#define MICROBLAZE_PVR11_MMU_ZONES_MASK             0x003E0000
+#define MICROBLAZE_PVR11_MMU_PRIVILEGED_INSTR_MASK  0x00010000
+
+/**
+ *@endcond
+ */
+/* PVR access macros */
+
+/**
+Return non-zero integer if PVR is of type FULL, 0 if basic
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_IS_FULL(_pvr)                 (_pvr.pvr[0] & MICROBLAZE_PVR0_PVR_FULL_MASK)
+/**
+Return non-zero integer if hardware barrel shifter present.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_USE_BARREL(_pvr)              (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_BARREL_MASK)
+/**
+Return non-zero integer if hardware divider present.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_USE_DIV(_pvr)                 (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_DIV_MASK)
+/**
+Return non-zero integer if hardware multiplier present.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_USE_HW_MUL(_pvr)              (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_HW_MUL_MASK)
+/**
+Return non-zero integer if hardware floating point unit (FPU) present.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_USE_FPU(_pvr)                 (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_FPU_MASK)
+/**
+Return non-zero integer if I-cache present.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_USE_ICACHE(_pvr)              (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_ICACHE_MASK)
+/**
+Return non-zero integer if D-cache present.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_USE_DCACHE(_pvr)              (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_DCACHE_MASK)
+
+/**
+ *@cond nocomments
+ */
+#define MICROBLAZE_PVR_USE_MMU(_pvr)                 (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_MMU_MASK)
+#define MICROBLAZE_PVR_USE_BTC(_pvr)                 (_pvr.pvr[0] & MICROBLAZE_PVR0_USE_BTC_MASK)
+#define MICROBLAZE_PVR_ENDIANNESS(_pvr)              (_pvr.pvr[0] & MICROBLAZE_PVR0_ENDIANNESS_MASK)
+#define MICROBLAZE_PVR_FAULT_TOLERANT(_pvr)          (_pvr.pvr[0] & MICROBLAZE_PVR0_FAULT_TOLERANT_MASK)
+#define MICROBLAZE_PVR_STACK_PROTECTION(_pvr)        (_pvr.pvr[0] & MICROBLAZE_PVR0_STACK_PROTECTION_MASK)
+/**
+Return MicroBlaze processor version encoding. Refer to the MicroBlaze Processor
+Reference Guide (UG081) for mappings from encodings to actual hardware versions.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_MICROBLAZE_VERSION(_pvr)      ((_pvr.pvr[0] & MICROBLAZE_PVR0_MICROBLAZE_VERSION_MASK) >> 8)
+/**
+Return the USER1 field stored in the PVR.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_USER1(_pvr)                   (_pvr.pvr[0] & MICROBLAZE_PVR0_USER1_MASK)
+
+/**
+Return the USER2 field stored in the PVR.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_USER2(_pvr)                   (_pvr.pvr[1] & MICROBLAZE_PVR1_USER2_MASK)
+
+#define MICROBLAZE_PVR_D_AXI(_pvr)                   (_pvr.pvr[2] & MICROBLAZE_PVR2_D_AXI_MASK)
+
+/**
+Return non-zero integer if Data Side PLB
+interface is present.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_D_LMB(_pvr)                   (_pvr.pvr[2] & MICROBLAZE_PVR2_D_LMB_MASK)
+
+/**
+Return non-zero integer if Data Side PLB interface is present.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_D_PLB(_pvr)                   (_pvr.pvr[2] & MICROBLAZE_PVR2_D_PLB_MASK)
+
+#define MICROBLAZE_PVR_I_AXI(_pvr)                   (_pvr.pvr[2] & MICROBLAZE_PVR2_I_AXI_MASK)
+
+/**
+Return non-zero integer if Instruction Side Local Memory Bus (LMB) interface present.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_I_LMB(_pvr)                   (_pvr.pvr[2] & MICROBLAZE_PVR2_I_LMB_MASK)
+
+/**
+Return non-zero integer if Instruction Side PLB interface present.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_I_PLB(_pvr)                   (_pvr.pvr[2] & MICROBLAZE_PVR2_I_PLB_MASK)
+
+/**
+Return non-zero integer if interrupts are configured as edge-triggered.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_INTERRUPT_IS_EDGE(_pvr)       (_pvr.pvr[2] & MICROBLAZE_PVR2_INTERRUPT_IS_EDGE_MASK)
+
+/**
+Return non-zero integer if interrupts are configured as positive edge triggered.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_EDGE_IS_POSITIVE(_pvr)        (_pvr.pvr[2] & MICROBLAZE_PVR2_EDGE_IS_POSITIVE_MASK)
+
+/**
+Return non-zero if MicroBlaze processor has PLB interconnect; otherwise return zero.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_INTERCONNECT(_pvr)            (_pvr.pvr[2] & MICROBLAZE_PVR2_INTERCONNECT_MASK)
+
+#define MICROBLAZE_PVR_STREAM_INTERCONNECT(_pvr)     (_pvr.pvr[2] & MICROBLAZE_PVR2_STREAM_INTERCONNECT_MASK)
+#define MICROBLAZE_PVR_USE_EXTENDED_FSL_INSTR(_pvr)  (_pvr.pvr[2] & MICROBLAZE_PVR2_USE_EXTENDED_FSL_INSTR_MASK)
+#define MICROBLAZE_PVR_USE_MSR_INSTR(_pvr)           (_pvr.pvr[2] & MICROBLAZE_PVR2_USE_MSR_INSTR_MASK)
+#define MICROBLAZE_PVR_USE_PCMP_INSTR(_pvr)          (_pvr.pvr[2] & MICROBLAZE_PVR2_USE_PCMP_INSTR_MASK)
+#define MICROBLAZE_PVR_AREA_OPTIMIZED(_pvr)          (_pvr.pvr[2] & MICROBLAZE_PVR2_AREA_OPTIMIZED_MASK)
+
+/**
+Return non-zero integer if MicroBlaze processor supports 64-bit products for
+multiplies.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_USE_MUL64(_pvr)               (_pvr.pvr[2] & MICROBLAZE_PVR2_USE_MUL64_MASK)
+
+/**
+Return non-zero integer if opcode 0x0 is treated as an illegal opcode.
+multiplies.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_OPCODE_0x0_ILLEGAL(_pvr)      (_pvr.pvr[2] & MICROBLAZE_PVR2_OPCODE_0x0_ILLEGAL_MASK)
+
+/**
+Return non-zero integer if unaligned exceptions are supported.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_UNALIGNED_EXCEPTION(_pvr)     (_pvr.pvr[2] & MICROBLAZE_PVR2_UNALIGNED_EXCEPTION_MASK)
+
+/**
+Return non-zero integer if illegal opcode exceptions are supported.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_ILL_OPCODE_EXCEPTION(_pvr)    (_pvr.pvr[2] & MICROBLAZE_PVR2_ILL_OPCODE_EXCEPTION_MASK)
+
+#define MICROBLAZE_PVR_M_AXI_I_BUS_EXCEPTION(_pvr)   (_pvr.pvr[2] & MICROBLAZE_PVR2_M_AXI_I_BUS_EXCEPTION_MASK)
+
+/**
+Return non-zero integer if I-PLB exceptions are supported.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_IPLB_BUS_EXCEPTION(_pvr)      (_pvr.pvr[2] & MICROBLAZE_PVR2_IPLB_BUS_EXCEPTION_MASK)
+
+#define MICROBLAZE_PVR_M_AXI_D_BUS_EXCEPTION(_pvr)   (_pvr.pvr[2] & MICROBLAZE_PVR2_M_AXI_D_BUS_EXCEPTION_MASK)
+
+/**
+Return non-zero integer if I-PLB exceptions are supported.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_DPLB_BUS_EXCEPTION(_pvr)      (_pvr.pvr[2] & MICROBLAZE_PVR2_DPLB_BUS_EXCEPTION_MASK)
+
+/**
+Return non-zero integer if divide by zero exceptions are supported.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_DIV_ZERO_EXCEPTION(_pvr)      (_pvr.pvr[2] & MICROBLAZE_PVR2_DIV_ZERO_EXCEPTION_MASK)
+
+/**
+Return non-zero integer if FPU exceptions are supported.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_FPU_EXCEPTION(_pvr)           (_pvr.pvr[2] & MICROBLAZE_PVR2_FPU_EXCEPTION_MASK)
+
+/**
+Return non-zero integer if FSL exceptions are present.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_FSL_EXCEPTION(_pvr)           (_pvr.pvr[2] & MICROBLAZE_PVR2_FSL_EXCEPTION_MASK)
+
+/**
+Return non-zero integer if debug is enabled.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_DEBUG_ENABLED(_pvr)           (_pvr.pvr[3] & MICROBLAZE_PVR3_DEBUG_ENABLED_MASK)
+
+/**
+Return the number of hardware PC breakpoints available.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_NUMBER_OF_PC_BRK(_pvr)        ((_pvr.pvr[3] & MICROBLAZE_PVR3_NUMBER_OF_PC_BRK_MASK) >> 25)
+
+/**
+Return the number of read address hardware watchpoints supported.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_NUMBER_OF_RD_ADDR_BRK(_pvr)   ((_pvr.pvr[3] & MICROBLAZE_PVR3_NUMBER_OF_RD_ADDR_BRK_MASK) >> 19)
+
+/**
+Return the number of write address hardware watchpoints supported.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_NUMBER_OF_WR_ADDR_BRK(_pvr)   ((_pvr.pvr[3] & MICROBLAZE_PVR3_NUMBER_OF_WR_ADDR_BRK_MASK) >> 13)
+
+/**
+Return the number of FSL links present.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_FSL_LINKS(_pvr)               ((_pvr.pvr[3] & MICROBLAZE_PVR3_FSL_LINKS_MASK) >> 7)
+#define MICROBLAZE_PVR_BTC_SIZE(_pvr)                (_pvr.pvr[3] & MICROBLAZE_PVR3_BTC_SIZE_MASK)
+
+/**
+Return the number of address tag bits for the I-cache.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_ICACHE_ADDR_TAG_BITS(_pvr)    ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_ADDR_TAG_BITS_MASK) >> 26)
+
+/**
+Return non-zero if writes to I-caches are allowed.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_ICACHE_ALLOW_WR(_pvr)         (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_ALLOW_WR_MASK)
+
+/**
+Return the length of each I-cache line in bytes.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_ICACHE_LINE_LEN(_pvr)         (1 << ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_LINE_LEN_MASK) >> 21))
+
+/**
+Return the size of the D-cache in bytes.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_ICACHE_BYTE_SIZE(_pvr)        (1 << ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_BYTE_SIZE_MASK) >> 16))
+
+#define MICROBLAZE_PVR_ICACHE_ALWAYS_USED(_pvr)      (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_ALWAYS_USED_MASK)
+#define MICROBLAZE_PVR_ICACHE_INTERFACE(_pvr)        (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_INTERFACE_MASK)
+#define MICROBLAZE_PVR_ICACHE_VICTIMS(_pvr)          ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_VICTIMS_MASK) >> 10)
+#define MICROBLAZE_PVR_ICACHE_STREAMS(_pvr)          ((_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_STREAMS_MASK) >> 8)
+#define MICROBLAZE_PVR_ICACHE_FORCE_TAG_LUTRAM(_pvr) (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_FORCE_TAG_LUTRAM_MASK)
+#define MICROBLAZE_PVR_ICACHE_DATA_WIDTH(_pvr)       (_pvr.pvr[4] & MICROBLAZE_PVR4_ICACHE_DATA_WIDTH_MASK)
+
+/**
+Return the number of address tag bits for the D-cache.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_DCACHE_ADDR_TAG_BITS(_pvr)    ((_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_ADDR_TAG_BITS_MASK) >> 26)
+
+/**
+Return non-zero if writes to D-cache are allowed.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_DCACHE_ALLOW_WR(_pvr)         (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_ALLOW_WR_MASK)
+
+/**
+Return the length of each line in the D-cache in bytes.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_DCACHE_LINE_LEN(_pvr)         (1 << ((_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_LINE_LEN_MASK) >> 21))
+
+/**
+Return the size of the D-cache in bytes.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_DCACHE_BYTE_SIZE(_pvr)        (1 << ((_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_BYTE_SIZE_MASK) >> 16))
+
+
+#define MICROBLAZE_PVR_DCACHE_ALWAYS_USED(_pvr)      (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_ALWAYS_USED_MASK)
+#define MICROBLAZE_PVR_DCACHE_USE_WRITEBACK(_pvr)    (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_USE_WRITEBACK_MASK)
+#define MICROBLAZE_PVR_DCACHE_INTERFACE(_pvr)        (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_INTERFACE_MASK)
+#define MICROBLAZE_PVR_DCACHE_VICTIMS(_pvr)          ((_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_VICTIMS_MASK) >> 10)
+#define MICROBLAZE_PVR_DCACHE_FORCE_TAG_LUTRAM(_pvr) (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_FORCE_TAG_LUTRAM_MASK)
+#define MICROBLAZE_PVR_DCACHE_DATA_WIDTH(_pvr)       (_pvr.pvr[5] & MICROBLAZE_PVR5_DCACHE_DATA_WIDTH_MASK)
+
+/**
+Return the base address of the I-cache.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_ICACHE_BASEADDR(_pvr)         (_pvr.pvr[6] & MICROBLAZE_PVR6_ICACHE_BASEADDR_MASK)
+
+/**
+Return the high address of the I-cache.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_ICACHE_HIGHADDR(_pvr)         (_pvr.pvr[7] & MICROBLAZE_PVR7_ICACHE_HIGHADDR_MASK)
+
+/**
+Return the base address of the D-cache.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_DCACHE_BASEADDR(_pvr)         (_pvr.pvr[8] & MICROBLAZE_PVR8_DCACHE_BASEADDR_MASK)
+
+/**
+Return the high address of the D-cache.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_DCACHE_HIGHADDR(_pvr)         (_pvr.pvr[9] & MICROBLAZE_PVR9_DCACHE_HIGHADDR_MASK)
+
+/**
+Return the encoded target family identifier.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_TARGET_FAMILY(_pvr)           ((_pvr.pvr[10] & MICROBLAZE_PVR10_TARGET_FAMILY_MASK) >> 24)
+
+/**
+Refer to the MicroBlaze Processor Reference Guide (UG081) for mappings from encodings
+to target family name strings.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_MSR_RESET_VALUE(_pvr)         (_pvr.pvr[11] & MICROBLAZE_PVR11_MSR_RESET_VALUE_MASK)
+
+/**
+Returns the value of C_USE_MMU. Refer to the MicroBlaze Processor Reference Guide
+(UG081) for mappings from MMU type values to MMU function.
+@param _pvr     pvr data structure
+*/
+#define MICROBLAZE_PVR_MMU_TYPE(_pvr)                ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_MASK) >> 30)
+#define MICROBLAZE_PVR_MMU_ITLB_SIZE(_pvr)           ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_ITLB_SIZE_MASK) >> 27)
+#define MICROBLAZE_PVR_MMU_DTLB_SIZE(_pvr)           ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_DTLB_SIZE_MASK) >> 24)
+#define MICROBLAZE_PVR_MMU_TLB_ACCESS(_pvr)          ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_TLB_ACCESS_MASK) >> 22)
+#define MICROBLAZE_PVR_MMU_ZONES(_pvr)               ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_ZONES_MASK) >> 17)
+#define MICROBLAZE_PVR_MMU_PRIVILEGED_INSTR(_pvr)    ((_pvr.pvr[11] & MICROBLAZE_PVR11_MMU_PRIVILEGED_INSTR_MASK) >> 16)
+
+/* Protos */
+/**
+ *@endcond
+ */
+int microblaze_get_pvr (pvr_t *pvr);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* PVR_H */
+
+/**
+* @} End of "addtogroup microblaze_pvr_macros".
+*/

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/microblaze_ps/standalone_domain/bsp/microblaze_ps/include/sleep.h

@@ -0,0 +1,109 @@
+/******************************************************************************
+* Copyright (C) 2014 - 2022 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+
+/*****************************************************************************/
+/**
+* @file sleep.h
+*
+*  This header file contains ARM Cortex A53,A9,R5,Microblaze specific sleep
+*  related APIs.
+*
+* <pre>
+* MODIFICATION HISTORY :
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6   srm  11/02/17 Added processor specific sleep routines
+*								 function prototypes.
+* 7.7	sk   01/10/22 Typecast sleep declaration argument from unsigned int to
+* 		      u32 to fix misra_c_2012_directive_4_6 violation.
+* 7.7	sk   01/10/22 Modify the return type of sleep_R5 and usleep_R5 from
+* 		      unsigned to void to fix misra_c_2012_rule_17_7 violation.
+* 8.0	sk   03/02/22 Update usleep_R5 and usleep parameter types to fix misra_
+*		      c_2012_directive_4_6 violation.
+* 8.0	sk   03/17/22 Modify the return type of usleep_MB from int to void and
+*		      sleep_MB from unsigned to void to fix misra_c_2012_rule_
+*		      17_7 violation.
+* 8.0	sk   03/17/22 Modify sleep_MB parameter type from unsigned int to
+*		      u32 and usleep_MB parameter type from unsigned long to
+*		      ULONG to fix misra_c_2012_rule_4_6 violation.
+* 9.0   ml   03/03/23 Add description to fix doxygen warnings.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef SLEEP_H
+#define SLEEP_H
+
+#include "xil_types.h"
+#include "xil_io.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*****************************************************************************/
+/**
+*
+* This macro polls an address periodically until a condition is met or till the
+* timeout occurs.
+* The minimum timeout for calling this macro is 100us. If the timeout is less
+* than 100us, it still waits for 100us. Also the unit for the timeout is 100us.
+* If the timeout is not a multiple of 100us, it waits for a timeout of
+* the next usec value which is a multiple of 100us.
+*
+* @param            IO_func - accessor function to read the register contents.
+*                   Depends on the register width.
+* @param            ADDR - Address to be polled
+* @param            VALUE - variable to read the value
+* @param            COND - Condition to checked (usually involves VALUE)
+* @param            TIMEOUT_US - timeout in micro seconds
+*
+* @return           0 - when the condition is met
+*                   -1 - when the condition is not met till the timeout period
+*
+* @note             none
+*
+*****************************************************************************/
+#define Xil_poll_timeout(IO_func, ADDR, VALUE, COND, TIMEOUT_US) \
+ ( {	  \
+	u64 timeout = TIMEOUT_US/100;    \
+	if(TIMEOUT_US%100!=0)	\
+		timeout++;   \
+	for(;;) { \
+		VALUE = IO_func(ADDR); \
+		if(COND) \
+			break; \
+		else {    \
+			usleep(100);  \
+			timeout--; \
+			if(timeout==0) \
+			break;  \
+		}  \
+	}    \
+	(timeout>0) ? 0 : -1;  \
+ }  )
+
+/************************** Function Prototypes ******************************/
+void usleep(ULONG useconds);
+void sleep(u32 seconds);
+void usleep_R5(ULONG useconds);
+void sleep_R5(u32 seconds);
+void usleep_MB(ULONG useconds);
+void sleep_MB(u32 seconds);
+int usleep_A53(unsigned long useconds);
+unsigned sleep_A53(unsigned int seconds);
+int usleep_A9(unsigned long useconds);
+unsigned sleep_A9(unsigned int seconds);
+
+/*****************************************************************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/microblaze_ps/standalone_domain/bsp/microblaze_ps/include/xbasic_types.h

@@ -0,0 +1,113 @@
+/******************************************************************************
+* Copyright (c) 2010 - 2021 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xbasic_types.h
+*
+*
+* @note  Dummy File for backwards compatibility
+*
+
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a adk   1/31/14  Added in bsp common folder for backward compatibility
+* 7.0   aru   01/21/19 Modified the typedef of u32,u16,u8
+* 7.0 	aru   02/06/19 Included stdint.h and stddef.h
+* </pre>
+*
+******************************************************************************/
+
+/**
+ *@cond nocomments
+ */
+
+#ifndef XBASIC_TYPES_H	/* prevent circular inclusions */
+#define XBASIC_TYPES_H	/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stddef.h>
+
+/** @name Legacy types
+ * Deprecated legacy types.
+ * @{
+ */
+typedef uint8_t	Xuint8;		/**< unsigned 8-bit */
+typedef char		Xint8;		/**< signed 8-bit */
+typedef uint16_t	Xuint16;	/**< unsigned 16-bit */
+typedef short		Xint16;		/**< signed 16-bit */
+typedef uint32_t	Xuint32;	/**< unsigned 32-bit */
+typedef long		Xint32;		/**< signed 32-bit */
+typedef float		Xfloat32;	/**< 32-bit floating point */
+typedef double		Xfloat64;	/**< 64-bit double precision FP */
+typedef unsigned long	Xboolean;	/**< boolean (XTRUE or XFALSE) */
+
+#if !defined __XUINT64__
+typedef struct
+{
+	Xuint32 Upper;
+	Xuint32 Lower;
+} Xuint64;
+#endif
+
+/** @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XIL_TYPES_H
+typedef Xuint32         u32;
+typedef Xuint16         u16;
+typedef Xuint8          u8;
+#endif
+#else
+#include <linux/types.h>
+#endif
+
+#ifndef TRUE
+#  define TRUE		1U
+#endif
+
+#ifndef FALSE
+#  define FALSE		0U
+#endif
+
+#ifndef NULL
+#define NULL		0U
+#endif
+
+/*
+ * Xilinx NULL, TRUE and FALSE legacy support. Deprecated.
+ * Please use NULL, TRUE and FALSE
+ */
+#define XNULL		NULL
+#define XTRUE		TRUE
+#define XFALSE		FALSE
+
+/*
+ * This file is deprecated and users
+ * should use xil_types.h and xil_assert.h\n\r
+ */
+#warning  The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert.
+#warning  Please refer the Standalone BSP UG647 for further details
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
+
+/**
+ *@endcond
+ */

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/microblaze_ps/standalone_domain/bsp/microblaze_ps/include/xbram.h

@@ -0,0 +1,220 @@
+/******************************************************************************
+* Copyright (C) 2010 - 2022 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+* @file xbram.h
+* @addtogroup bram Overview
+* @{
+* @details
+*
+* If ECC is not enabled, this driver exists only to allow the tools to
+* create a memory test application and to populate xparameters.h with memory
+* range constants. In this case there is no source code.
+*
+* If ECC is enabled, this file contains the software API definition of the
+* Xilinx BRAM Interface Controller (XBram) device driver.
+*
+* The Xilinx BRAM controller is a soft IP core designed for Xilinx
+* FPGAs and contains the following general features:
+*   - LMB v2.0 bus interfaces with byte enable support
+*   - Used in conjunction with bram_block peripheral to provide fast BRAM
+*     memory solution for MicroBlaze ILMB and DLMB ports
+*   - Supports byte, half-word, and word transfers
+*   - Supports optional BRAM error correction and detection.
+*
+* The driver provides interrupt management functions. Implementation of
+* interrupt handlers is left to the user. Refer to the provided interrupt
+* example in the examples directory for details.
+*
+* This driver is intended to be RTOS and processor independent. Any needs for
+* dynamic memory management, threads or thread mutual exclusion, virtual
+* memory, or cache control must be satisfied by the layer above this driver.
+*
+* <b>Initialization & Configuration</b>
+*
+* The XBram_Config structure is used by the driver to configure
+* itself. This configuration structure is typically created by the tool-chain
+* based on HW build properties.
+*
+* To support multiple runtime loading and initialization strategies employed
+* by various operating systems, the driver instance can be initialized as
+* follows:
+*
+*   - XBram_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) -
+*     Uses a configuration structure provided by the caller. If running in a
+*     system with address translation, the provided virtual memory base address
+*     replaces the physical address present in the configuration structure.
+*
+* @note
+*
+* This API utilizes 32 bit I/O to the BRAM registers. With less
+* than 32 bits, the unused bits from registers are read as zero and written as
+* don't cares.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 3.00a sa  05/11/10 Added ECC support
+* 3.01a sa  01/13/12  Changed Selftest API from
+*		      XBram_SelfTest(XBram *InstancePtr) to
+*		      XBram_SelfTest(XBram *InstancePtr, u8 IntMask) and
+*		      fixed a problem with interrupt generation for CR 639274
+*		      Modified Selftest example to return XST_SUCCESS when
+*		      ECC is not enabled and return XST_FAILURE when ECC is
+*		      enabled and Control Base Address is zero (CR 636581)
+*		      Modified Selftest to use correct CorrectableCounterBits
+*		      for CR 635655
+*		      Updated to check CorrectableFailingDataRegs in the case
+*		      of LMB BRAM.
+* 		      Added CorrectableFailingDataRegs and
+*		      UncorrectableFailingDataRegs to the config structure to
+*		      distinguish between AXI BRAM and LMB BRAM.
+*		      These registers are not present in the current version of
+*		      the AXI BRAM Controller.
+* 3.02a sa 04/16/12   Added test of byte and halfword read-modify-write
+* 3.02a sa 04/16/12   Modified driver tcl to sort the address parameters
+*  	       	      to support both xps and vivado designs.
+* 3.02a adk 24/4/13   Modified the tcl file to avoid warnings
+*	       	      when ecc is disabled cr:705002.
+* 3.03a bss 05/22/13  Added Xil_DCacheFlushRange in xbram_selftest.c to
+*		      flush the Cache after writing to BRAM in InjectErrors
+*		      API(CR #719011)
+* 4.0   adk  19/12/13 Updated as per the New Tcl API's
+* 4.1   sk   11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
+*                     Changed the prototype of XBram_CfgInitialize API.
+*       ms  01/23/17 Modified xil_printf statement in main function for all
+*                    examples to ensure that "Successfully ran" and "Failed"
+*                    strings are available in all examples. This is a fix
+*                    for CR-965028.
+*       ms  03/17/17 Added readme.txt file in examples folder for doxygen
+*                    generation.
+* 4.2   ms  04/18/17 Modified tcl file to add suffix U for all macro
+*                    definitions of bram in xparameters.h
+*       ms  08/07/17 Fixed compilation warnings in xbram_sinit.c
+* 4.6	sk  02/18/21 Use UINTPTR instead of u32 for MemBaseAddress and
+* 		     MemHighAddress variables.
+* 4.8   adk 04/11/22 Modified driver tcl fix lmb_bram_if_cntlr canonical
+* 		     redefinition warnings when multiple lmb_bram_if_cntlr
+* 		     instances are present.
+* 4.9   sd  07/07/23 Added SDT support.
+* </pre>
+*****************************************************************************/
+#ifndef XBRAM_H		/* prevent circular inclusions */
+#define XBRAM_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xbram_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+#ifndef SDT
+	u16 DeviceId;			   /**< Unique ID  of device */
+#else
+	char *Name;
+	UINTPTR BaseAddress;		   /**< Device register base address.*/
+#endif
+	u32 DataWidth;			   /**< BRAM data width */
+	int EccPresent;			   /**< Is ECC supported in H/W */
+	int FaultInjectionPresent;	   /**< Is Fault Injection
+					     *  supported in H/W */
+	int CorrectableFailingRegisters;   /**< Is Correctable Failing Registers
+					     *  supported in H/W */
+	int CorrectableFailingDataRegs;    /**< Is Correctable Failing Data
+					    *   Registers supported in H/W */
+	int UncorrectableFailingRegisters; /**< Is Un-correctable Failing
+					     *  Registers supported in H/W */
+	int UncorrectableFailingDataRegs;  /**< Is Un-correctable Failing Data
+					     *  Registers supported in H/W */
+	int EccStatusInterruptPresent;	   /**< Are ECC status and interrupts
+					     *  supported in H/W */
+	int CorrectableCounterBits;	   /**< Number of bits in the
+					     *  Correctable Error Counter */
+	int EccOnOffRegister;		   /**< Is ECC on/off register supported
+					     *  in h/w */
+	int EccOnOffResetValue;		   /**< Reset value of the ECC on/off
+					     *  register in h/w */
+	int WriteAccess;		   /**< Is write access enabled in
+					     *  h/w */
+	UINTPTR MemBaseAddress;		   /**< Device memory base address */
+	UINTPTR MemHighAddress;		   /**< Device memory high address */
+	UINTPTR CtrlBaseAddress;		   /**< Device register base address.*/
+	UINTPTR CtrlHighAddress;		   /**< Device register base address.*/
+#ifdef SDT
+	u32 IntId;			   /**< Interrupt ID on GIC **/
+	UINTPTR IntrParent; 		   /** Bit[0] Interrupt parent type Bit[64/32:1]
+						 * Parent base address */
+#endif
+} XBram_Config;
+
+/**
+ * The XBram driver instance data. The user is required to
+ * allocate a variable of this type for every BRAM device in the
+ * system. A pointer to a variable of this type is then passed to the driver
+ * API functions.
+ */
+typedef struct {
+	XBram_Config  Config;		/* BRAM config structure */
+	u32 IsReady;			/* Device is initialized and ready */
+} XBram;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes *****************************/
+
+/*
+ * Functions in xbram_sinit.c
+ */
+#ifndef SDT
+XBram_Config *XBram_LookupConfig(u16 DeviceId);
+#else
+XBram_Config *XBram_LookupConfig(UINTPTR BaseAddress);
+#endif
+
+/*
+ * Functions implemented in xbram.c
+ */
+int XBram_CfgInitialize(XBram *InstancePtr, XBram_Config *Config,
+			UINTPTR EffectiveAddr);
+
+/*
+ * Functions implemented in xbram_selftest.c
+ */
+int XBram_SelfTest(XBram *InstancePtr, u8 IntMask);
+
+/*
+ * Functions implemented in xbram_intr.c
+ */
+void XBram_InterruptEnable(XBram *InstancePtr, u32 Mask);
+void XBram_InterruptDisable(XBram *InstancePtr, u32 Mask);
+void XBram_InterruptClear(XBram *InstancePtr, u32 Mask);
+u32 XBram_InterruptGetEnabled(XBram *InstancePtr);
+u32 XBram_InterruptGetStatus(XBram *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/microblaze_ps/standalone_domain/bsp/microblaze_ps/include/xbram_hw.h

@@ -0,0 +1,384 @@
+/******************************************************************************
+* Copyright (C) 2011 - 2022 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xbram_hw.h
+* @addtogroup bram Overview
+* @{
+*
+* This header file contains identifiers and driver functions (or
+* macros) that can be used to access the device.  The user should refer to the
+* hardware device specification for more details of the device operation.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sa   24/11/10 First release
+* </pre>
+*
+******************************************************************************/
+#ifndef XBRAM_HW_H		/* prevent circular inclusions */
+#define XBRAM_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Registers
+ *
+ * Register offsets for this device.
+ * @{
+ */
+
+#define XBRAM_ECC_STATUS_OFFSET	0x0  /**< ECC status Register */
+#define XBRAM_ECC_EN_IRQ_OFFSET	0x4  /**< ECC interrupt enable Register */
+#define XBRAM_ECC_ON_OFF_OFFSET	0x8  /**< ECC on/off register */
+#define XBRAM_CE_CNT_OFFSET	0xC  /**< Correctable error counter Register */
+
+#define XBRAM_CE_FFD_0_OFFSET	0x100 /**< Correctable error first failing
+				        *  data Register, 31-0 */
+#define XBRAM_CE_FFD_1_OFFSET	0x104 /**< Correctable error first failing
+				        *  data Register, 63-32 */
+#define XBRAM_CE_FFD_2_OFFSET	0x108 /**< Correctable error first failing
+				        *  data Register, 95-64 */
+#define XBRAM_CE_FFD_3_OFFSET	0x10C /**< Correctable error first failing
+				        *  data Register, 127-96 */
+#define XBRAM_CE_FFD_4_OFFSET	0x110 /**< Correctable error first failing
+				        *  data Register, 159-128 */
+#define XBRAM_CE_FFD_5_OFFSET	0x114 /**< Correctable error first failing
+				        *  data Register, 191-160 */
+#define XBRAM_CE_FFD_6_OFFSET	0x118 /**< Correctable error first failing
+				        *  data Register, 223-192 */
+#define XBRAM_CE_FFD_7_OFFSET	0x11C /**< Correctable error first failing
+				        *  data Register, 255-224 */
+#define XBRAM_CE_FFD_8_OFFSET	0x120 /**< Correctable error first failing
+				        *  data Register, 287-256 */
+#define XBRAM_CE_FFD_9_OFFSET	0x124 /**< Correctable error first failing
+				        *  data Register, 319-288 */
+#define XBRAM_CE_FFD_10_OFFSET	0x128 /**< Correctable error first failing
+				        *  data Register, 351-320 */
+#define XBRAM_CE_FFD_11_OFFSET	0x12C /**< Correctable error first failing
+				        *  data Register, 383-352 */
+#define XBRAM_CE_FFD_12_OFFSET	0x130 /**< Correctable error first failing
+				        *  data Register, 415-384 */
+#define XBRAM_CE_FFD_13_OFFSET	0x134 /**< Correctable error first failing
+				        *  data Register, 447-416 */
+#define XBRAM_CE_FFD_14_OFFSET	0x138 /**< Correctable error first failing
+				        *  data Register, 479-448 */
+#define XBRAM_CE_FFD_15_OFFSET	0x13C /**< Correctable error first failing
+				        *  data Register, 511-480 */
+#define XBRAM_CE_FFD_16_OFFSET	0x140 /**< Correctable error first failing
+				        *  data Register, 543-512 */
+#define XBRAM_CE_FFD_17_OFFSET	0x144 /**< Correctable error first failing
+				        *  data Register, 575-544 */
+#define XBRAM_CE_FFD_18_OFFSET	0x148 /**< Correctable error first failing
+				        *  data Register, 607-576 */
+#define XBRAM_CE_FFD_19_OFFSET	0x14C /**< Correctable error first failing
+				        *  data Register, 639-608 */
+#define XBRAM_CE_FFD_20_OFFSET	0x150 /**< Correctable error first failing
+				        *  data Register, 671-640 */
+#define XBRAM_CE_FFD_21_OFFSET	0x154 /**< Correctable error first failing
+				        *  data Register, 703-672 */
+#define XBRAM_CE_FFD_22_OFFSET	0x158 /**< Correctable error first failing
+				        *  data Register, 735-704 */
+#define XBRAM_CE_FFD_23_OFFSET	0x15C /**< Correctable error first failing
+				        *  data Register, 767-736 */
+#define XBRAM_CE_FFD_24_OFFSET	0x160 /**< Correctable error first failing
+				        *  data Register, 799-768 */
+#define XBRAM_CE_FFD_25_OFFSET	0x164 /**< Correctable error first failing
+				        *  data Register, 831-800 */
+#define XBRAM_CE_FFD_26_OFFSET	0x168 /**< Correctable error first failing
+				        *  data Register, 863-832 */
+#define XBRAM_CE_FFD_27_OFFSET	0x16C /**< Correctable error first failing
+				        *  data Register, 895-864 */
+#define XBRAM_CE_FFD_28_OFFSET	0x170 /**< Correctable error first failing
+				        *  data Register, 927-896 */
+#define XBRAM_CE_FFD_29_OFFSET	0x174 /**< Correctable error first failing
+				        *  data Register, 959-928 */
+#define XBRAM_CE_FFD_30_OFFSET	0x178 /**< Correctable error first failing
+				        *  data Register, 991-960 */
+#define XBRAM_CE_FFD_31_OFFSET	0x17C /**< Correctable error first failing
+				        *  data Register, 1023-992 */
+
+#define XBRAM_CE_FFE_0_OFFSET	0x180 /**< Correctable error first failing
+				        *  ECC Register, 31-0 */
+#define XBRAM_CE_FFE_1_OFFSET	0x184 /**< Correctable error first failing
+				        *  ECC Register, 63-32 */
+#define XBRAM_CE_FFE_2_OFFSET	0x188 /**< Correctable error first failing
+				        *  ECC Register, 95-64 */
+#define XBRAM_CE_FFE_3_OFFSET	0x18C /**< Correctable error first failing
+				        *  ECC Register, 127-96 */
+#define XBRAM_CE_FFE_4_OFFSET	0x190 /**< Correctable error first failing
+				        *  ECC Register, 159-128 */
+#define XBRAM_CE_FFE_5_OFFSET	0x194 /**< Correctable error first failing
+				        *  ECC Register, 191-160 */
+#define XBRAM_CE_FFE_6_OFFSET	0x198 /**< Correctable error first failing
+				        *  ECC Register, 223-192 */
+#define XBRAM_CE_FFE_7_OFFSET	0x19C /**< Correctable error first failing
+				        *  ECC Register, 255-224 */
+
+#define XBRAM_CE_FFA_0_OFFSET	0x1C0 /**< Correctable error first failing
+				        *  address Register 31-0 */
+#define XBRAM_CE_FFA_1_OFFSET	0x1C4 /**< Correctable error first failing
+				        *  address Register 63-32 */
+
+#define XBRAM_UE_FFD_0_OFFSET	0x200 /**< Uncorrectable error first failing
+				        *  data Register, 31-0 */
+#define XBRAM_UE_FFD_1_OFFSET	0x204 /**< Uncorrectable error first failing
+				        *  data Register, 63-32 */
+#define XBRAM_UE_FFD_2_OFFSET	0x208 /**< Uncorrectable error first failing
+				        *  data Register, 95-64 */
+#define XBRAM_UE_FFD_3_OFFSET	0x20C /**< Uncorrectable error first failing
+				        *  data Register, 127-96 */
+#define XBRAM_UE_FFD_4_OFFSET	0x210 /**< Uncorrectable error first failing
+				        *  data Register, 159-128 */
+#define XBRAM_UE_FFD_5_OFFSET	0x214 /**< Uncorrectable error first failing
+				        *  data Register, 191-160 */
+#define XBRAM_UE_FFD_6_OFFSET	0x218 /**< Uncorrectable error first failing
+				        *  data Register, 223-192 */
+#define XBRAM_UE_FFD_7_OFFSET	0x21C /**< Uncorrectable error first failing
+				        *  data Register, 255-224 */
+#define XBRAM_UE_FFD_8_OFFSET	0x220 /**< Uncorrectable error first failing
+				        *  data Register, 287-256 */
+#define XBRAM_UE_FFD_9_OFFSET	0x224 /**< Uncorrectable error first failing
+				        *  data Register, 319-288 */
+#define XBRAM_UE_FFD_10_OFFSET	0x228 /**< Uncorrectable error first failing
+				        *  data Register, 351-320 */
+#define XBRAM_UE_FFD_11_OFFSET	0x22C /**< Uncorrectable error first failing
+				        *  data Register, 383-352 */
+#define XBRAM_UE_FFD_12_OFFSET	0x230 /**< Uncorrectable error first failing
+				        *  data Register, 415-384 */
+#define XBRAM_UE_FFD_13_OFFSET	0x234 /**< Uncorrectable error first failing
+				        *  data Register, 447-416 */
+#define XBRAM_UE_FFD_14_OFFSET	0x238 /**< Uncorrectable error first failing
+				        *  data Register, 479-448 */
+#define XBRAM_UE_FFD_15_OFFSET	0x23C /**< Uncorrectable error first failing
+				        *  data Register, 511-480 */
+#define XBRAM_UE_FFD_16_OFFSET	0x240 /**< Uncorrectable error first failing
+				        *  data Register, 543-512 */
+#define XBRAM_UE_FFD_17_OFFSET	0x244 /**< Uncorrectable error first failing
+				        *  data Register, 575-544 */
+#define XBRAM_UE_FFD_18_OFFSET	0x248 /**< Uncorrectable error first failing
+				        *  data Register, 607-576 */
+#define XBRAM_UE_FFD_19_OFFSET	0x24C /**< Uncorrectable error first failing
+				        *  data Register, 639-608 */
+#define XBRAM_UE_FFD_20_OFFSET	0x250 /**< Uncorrectable error first failing
+				        *  data Register, 671-640 */
+#define XBRAM_UE_FFD_21_OFFSET	0x254 /**< Uncorrectable error first failing
+				        *  data Register, 703-672 */
+#define XBRAM_UE_FFD_22_OFFSET	0x258 /**< Uncorrectable error first failing
+				        *  data Register, 735-704 */
+#define XBRAM_UE_FFD_23_OFFSET	0x25C /**< Uncorrectable error first failing
+				        *  data Register, 767-736 */
+#define XBRAM_UE_FFD_24_OFFSET	0x260 /**< Uncorrectable error first failing
+				        *  data Register, 799-768 */
+#define XBRAM_UE_FFD_25_OFFSET	0x264 /**< Uncorrectable error first failing
+				        *  data Register, 831-800 */
+#define XBRAM_UE_FFD_26_OFFSET	0x268 /**< Uncorrectable error first failing
+				        *  data Register, 863-832 */
+#define XBRAM_UE_FFD_27_OFFSET	0x26C /**< Uncorrectable error first failing
+				        *  data Register, 895-864 */
+#define XBRAM_UE_FFD_28_OFFSET	0x270 /**< Uncorrectable error first failing
+				        *  data Register, 927-896 */
+#define XBRAM_UE_FFD_29_OFFSET	0x274 /**< Uncorrectable error first failing
+				        *  data Register, 959-928 */
+#define XBRAM_UE_FFD_30_OFFSET	0x278 /**< Uncorrectable error first failing
+				        *  data Register, 991-960 */
+#define XBRAM_UE_FFD_31_OFFSET	0x27C /**< Uncorrectable error first failing
+				        *  data Register, 1023-992 */
+
+#define XBRAM_UE_FFE_0_OFFSET	0x280 /**< Uncorrectable error first failing
+				        *  ECC Register, 31-0 */
+#define XBRAM_UE_FFE_1_OFFSET	0x284 /**< Uncorrectable error first failing
+				        *  ECC Register, 63-32 */
+#define XBRAM_UE_FFE_2_OFFSET	0x288 /**< Uncorrectable error first failing
+				        *  ECC Register, 95-64 */
+#define XBRAM_UE_FFE_3_OFFSET	0x28C /**< Uncorrectable error first failing
+				        *  ECC Register, 127-96 */
+#define XBRAM_UE_FFE_4_OFFSET	0x290 /**< Uncorrectable error first failing
+				        *  ECC Register, 159-128 */
+#define XBRAM_UE_FFE_5_OFFSET	0x294 /**< Uncorrectable error first failing
+				        *  ECC Register, 191-160 */
+#define XBRAM_UE_FFE_6_OFFSET	0x298 /**< Uncorrectable error first failing
+				        *  ECC Register, 223-192 */
+#define XBRAM_UE_FFE_7_OFFSET	0x29C /**< Uncorrectable error first failing
+				        *  ECC Register, 255-224 */
+
+#define XBRAM_UE_FFA_0_OFFSET	0x2C0 /**< Uncorrectable error first failing
+				        *  address Register 31-0 */
+#define XBRAM_UE_FFA_1_OFFSET	0x2C4 /**< Uncorrectable error first failing
+				        *  address Register 63-32 */
+
+#define XBRAM_FI_D_0_OFFSET	0x300 /**< Fault injection Data Register,
+				        *  31-0 */
+#define XBRAM_FI_D_1_OFFSET	0x304 /**< Fault injection Data Register,
+				        *  63-32 */
+#define XBRAM_FI_D_2_OFFSET	0x308 /**< Fault injection Data Register,
+				        *  95-64 */
+#define XBRAM_FI_D_3_OFFSET	0x30C /**< Fault injection Data Register,
+				        *  127-96 */
+#define XBRAM_FI_D_4_OFFSET	0x310 /**< Fault injection Data Register,
+				        *  159-128 */
+#define XBRAM_FI_D_5_OFFSET	0x314 /**< Fault injection Data Register,
+				        *  191-160 */
+#define XBRAM_FI_D_6_OFFSET	0x318 /**< Fault injection Data Register,
+				        *  223-192 */
+#define XBRAM_FI_D_7_OFFSET	0x31C /**< Fault injection Data Register,
+				        *  255-224 */
+#define XBRAM_FI_D_8_OFFSET	0x320 /**< Fault injection Data Register,
+				        *  287-256 */
+#define XBRAM_FI_D_9_OFFSET	0x324 /**< Fault injection Data Register,
+				        *  319-288 */
+#define XBRAM_FI_D_10_OFFSET	0x328 /**< Fault injection Data Register,
+				        *  351-320 */
+#define XBRAM_FI_D_11_OFFSET	0x32C /**< Fault injection Data Register,
+				        *  383-352 */
+#define XBRAM_FI_D_12_OFFSET	0x330 /**< Fault injection Data Register,
+				        *  415-384 */
+#define XBRAM_FI_D_13_OFFSET	0x334 /**< Fault injection Data Register,
+				        *  447-416 */
+#define XBRAM_FI_D_14_OFFSET	0x338 /**< Fault injection Data Register,
+				        *  479-448 */
+#define XBRAM_FI_D_15_OFFSET	0x33C /**< Fault injection Data Register,
+				        *  511-480 */
+#define XBRAM_FI_D_16_OFFSET	0x340 /**< Fault injection Data Register,
+				        *  543-512 */
+#define XBRAM_FI_D_17_OFFSET	0x344 /**< Fault injection Data Register,
+				        *  575-544 */
+#define XBRAM_FI_D_18_OFFSET	0x348 /**< Fault injection Data Register,
+				        *  607-576 */
+#define XBRAM_FI_D_19_OFFSET	0x34C /**< Fault injection Data Register,
+				        *  639-608 */
+#define XBRAM_FI_D_20_OFFSET	0x350 /**< Fault injection Data Register,
+				        *  671-640 */
+#define XBRAM_FI_D_21_OFFSET	0x354 /**< Fault injection Data Register,
+				        *  703-672 */
+#define XBRAM_FI_D_22_OFFSET	0x358 /**< Fault injection Data Register,
+				        *  735-704 */
+#define XBRAM_FI_D_23_OFFSET	0x35C /**< Fault injection Data Register,
+				        *  767-736 */
+#define XBRAM_FI_D_24_OFFSET	0x360 /**< Fault injection Data Register,
+				        *  799-768 */
+#define XBRAM_FI_D_25_OFFSET	0x364 /**< Fault injection Data Register,
+				        *  831-800 */
+#define XBRAM_FI_D_26_OFFSET	0x368 /**< Fault injection Data Register,
+				        *  863-832 */
+#define XBRAM_FI_D_27_OFFSET	0x36C /**< Fault injection Data Register,
+				        *  895-864 */
+#define XBRAM_FI_D_28_OFFSET	0x370 /**< Fault injection Data Register,
+				        *  927-896 */
+#define XBRAM_FI_D_29_OFFSET	0x374 /**< Fault injection Data Register,
+				        *  959-928 */
+#define XBRAM_FI_D_30_OFFSET	0x378 /**< Fault injection Data Register,
+				        *  991-960 */
+#define XBRAM_FI_D_31_OFFSET	0x37C /**< Fault injection Data Register,
+				        *  1023-992 */
+
+#define XBRAM_FI_ECC_0_OFFSET	0x380 /**< Fault injection ECC Register,
+				        *  31-0 */
+#define XBRAM_FI_ECC_1_OFFSET	0x384 /**< Fault injection ECC Register,
+				        *  63-32 */
+#define XBRAM_FI_ECC_2_OFFSET	0x388 /**< Fault injection ECC Register,
+				        *  95-64 */
+#define XBRAM_FI_ECC_3_OFFSET	0x38C /**< Fault injection ECC Register,
+				        *  127-96 */
+#define XBRAM_FI_ECC_4_OFFSET	0x390 /**< Fault injection ECC Register,
+				        *  159-128 */
+#define XBRAM_FI_ECC_5_OFFSET	0x394 /**< Fault injection ECC Register,
+				        *  191-160 */
+#define XBRAM_FI_ECC_6_OFFSET	0x398 /**< Fault injection ECC Register,
+				        *  223-192 */
+#define XBRAM_FI_ECC_7_OFFSET	0x39C /**< Fault injection ECC Register,
+				        *  255-224 */
+
+
+/* @} */
+
+/** @name Interrupt Status and Enable Register bitmaps and masks
+ *
+ * Bit definitions for the ECC status register and ECC interrupt enable register.
+ * @{
+ */
+#define XBRAM_IR_CE_MASK	0x2 /**< Mask for the correctable error */
+#define XBRAM_IR_UE_MASK	0x1 /**< Mask for the uncorrectable error */
+#define XBRAM_IR_ALL_MASK	0x3 /**< Mask of all bits */
+/*@}*/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XBram_In32  Xil_In32
+#define XBram_Out32 Xil_Out32
+
+#define XBram_In16  Xil_In16
+#define XBram_Out16 Xil_Out16
+
+#define XBram_In8  Xil_In8
+#define XBram_Out8 Xil_Out8
+
+
+/****************************************************************************/
+/**
+*
+* Write a value to a BRAM register. A 32 bit write is performed.
+*
+* @param	BaseAddress is the base address of the BRAM device register.
+* @param	RegOffset is the register offset from the base to write to.
+* @param	Data is the data written to the register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XBram_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+****************************************************************************/
+#define XBram_WriteReg(BaseAddress, RegOffset, Data) \
+	XBram_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+
+/****************************************************************************/
+/**
+*
+* Read a value from a BRAM register. A 32 bit read is performed.
+*
+* @param	BaseAddress is the base address of the BRAM device registers.
+* @param	RegOffset is the register offset from the base to read from.
+*
+* @return	Data read from the register.
+*
+* @note		C-style signature:
+*		u32 XBram_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+****************************************************************************/
+#define XBram_ReadReg(BaseAddress, RegOffset) \
+	XBram_In32((BaseAddress) + (RegOffset))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/microblaze_ps/standalone_domain/bsp/microblaze_ps/include/xdebug.h

@@ -0,0 +1,78 @@
+/******************************************************************************
+* Copyright (C) 2002 - 2021 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+
+#ifndef XDEBUG
+#define XDEBUG
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xil_printf.h"
+
+#if defined(DEBUG) && !defined(NDEBUG)
+
+#ifndef XDEBUG_WARNING
+#define XDEBUG_WARNING
+#warning DEBUG is enabled
+#endif
+
+int printf(const char *format, ...);
+
+#define XDBG_DEBUG_ERROR             0x00000001U    /* error  condition messages */
+#define XDBG_DEBUG_GENERAL           0x00000002U    /* general debug  messages */
+#define XDBG_DEBUG_ALL               0xFFFFFFFFU    /* all debugging data */
+
+#define XDBG_DEBUG_FIFO_REG          0x00000100U    /* display register reads/writes */
+#define XDBG_DEBUG_FIFO_RX           0x00000101U    /* receive debug messages */
+#define XDBG_DEBUG_FIFO_TX           0x00000102U    /* transmit debug messages */
+#define XDBG_DEBUG_FIFO_ALL          0x0000010FU    /* all fifo debug messages */
+
+#define XDBG_DEBUG_TEMAC_REG         0x00000400U    /* display register reads/writes */
+#define XDBG_DEBUG_TEMAC_RX          0x00000401U    /* receive debug messages */
+#define XDBG_DEBUG_TEMAC_TX          0x00000402U    /* transmit debug messages */
+#define XDBG_DEBUG_TEMAC_ALL         0x0000040FU    /* all temac  debug messages */
+
+#define XDBG_DEBUG_TEMAC_ADPT_RX     0x00000800U    /* receive debug messages */
+#define XDBG_DEBUG_TEMAC_ADPT_TX     0x00000801U    /* transmit debug messages */
+#define XDBG_DEBUG_TEMAC_ADPT_IOCTL  0x00000802U    /* ioctl debug messages */
+#define XDBG_DEBUG_TEMAC_ADPT_MISC   0x00000803U    /* debug msg for other routines */
+#define XDBG_DEBUG_TEMAC_ADPT_ALL    0x0000080FU    /* all temac adapter debug messages */
+
+
+#define xdbg_current_types (XDBG_DEBUG_GENERAL | XDBG_DEBUG_ERROR | XDBG_DEBUG_TEMAC_REG | XDBG_DEBUG_FIFO_RX | XDBG_DEBUG_FIFO_TX | XDBG_DEBUG_FIFO_REG)
+
+#define xdbg_stmnt(x)  x
+
+/* In VxWorks, if _WRS_GNU_VAR_MACROS is defined, special syntax is needed for
+ * macros that accept variable number of arguments
+ */
+#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS)
+#define xdbg_printf(type, args...) (((type) & xdbg_current_types) ? printf (## args) : 0)
+#else /* ANSI Syntax */
+#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
+#endif
+
+#define xdbg_exception_printf(type, ...) (((type) & xdbg_current_types) ? xil_printf (__VA_ARGS__) : 0)
+
+#else /* defined(DEBUG) && !defined(NDEBUG) */
+
+#define xdbg_stmnt(x) /**< Debug statement */
+
+/* See VxWorks comments above */
+#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS)
+#define xdbg_printf(type, args...)
+#else /* ANSI Syntax */
+#define xdbg_printf(...) /**< Debug printf */
+#endif
+#endif /* defined(DEBUG) && !defined(NDEBUG) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XDEBUG */

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/microblaze_ps/standalone_domain/bsp/microblaze_ps/include/xenv.h

@@ -0,0 +1,169 @@
+/******************************************************************************
+* Copyright (c) 2002 - 2021 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xenv.h
+*
+* Defines common services that are typically found in a host operating.
+* environment. This include file simply includes an OS specific file based
+* on the compile-time constant BUILD_ENV_*, where * is the name of the target
+* environment.
+*
+* All services are defined as macros.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b ch   10/24/02 Added XENV_LINUX
+* 1.00a rmm  04/17/02 First release
+* </pre>
+*
+******************************************************************************/
+
+/**
+ *@cond nocomments
+ */
+
+#ifndef XENV_H /* prevent circular inclusions */
+#define XENV_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Select which target environment we are operating under
+ */
+
+/* VxWorks target environment */
+#if defined XENV_VXWORKS
+#include "xenv_vxworks.h"
+
+/* Linux target environment */
+#elif defined XENV_LINUX
+#include "xenv_linux.h"
+
+/* Unit test environment */
+#elif defined XENV_UNITTEST
+#include "ut_xenv.h"
+
+/* Integration test environment */
+#elif defined XENV_INTTEST
+#include "int_xenv.h"
+
+/* Standalone environment selected */
+#else
+#include "xenv_standalone.h"
+#endif
+
+
+/*
+ * The following comments specify the types and macro wrappers that are
+ * expected to be defined by the target specific header files
+ */
+
+/**************************** Type Definitions *******************************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP
+ *
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param   DestPtr is the destination address to copy data to.
+ * @param   SrcPtr is the source address to copy data from.
+ * @param   Bytes is the number of bytes to copy.
+ *
+ * @return  None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param   DestPtr is the destination address to set.
+ * @param   Data contains the value to set.
+ * @param   Bytes is the number of bytes to set.
+ *
+ * @return  None
+ */
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ *
+ * Samples the processor's or external timer's time base counter.
+ *
+ * @param   StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return  None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param   Stamp1Ptr - First sampled time stamp.
+ * @param   Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return  An unsigned int value with units of microseconds.
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param   Stamp1Ptr - First sampled time stamp.
+ * @param   Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return  An unsigned int value with units of milliseconds.
+ */
+
+/*****************************************************************************//**
+ *
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds.
+ *
+ * @param   delay is the number of microseconds to delay.
+ *
+ * @return  None
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif            /* end of protection macro */
+
+/**
+ *@endcond
+ */

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/microblaze_ps/standalone_domain/bsp/microblaze_ps/include/xenv_standalone.h

@@ -0,0 +1,350 @@
+/******************************************************************************
+* Copyright (c) 2002 - 2021 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xenv_standalone.h
+*
+* Defines common services specified by xenv.h.
+*
+* @note
+* 	This file is not intended to be included directly by driver code.
+* 	Instead, the generic xenv.h file is intended to be included by driver
+* 	code.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a wgr  02/28/07 Added cache handling macros.
+* 1.00a wgr  02/27/07 Simplified code. Deprecated old-style macro names.
+* 1.00a rmm  01/24/06 Implemented XENV_USLEEP. Assume implementation is being
+*                     used under Xilinx standalone BSP.
+* 1.00a xd   11/03/04 Improved support for doxygen.
+* 1.00a rmm  03/21/02 First release
+* 1.00a wgr  03/22/07 Converted to new coding style.
+* 1.00a rpm  06/29/07 Added udelay macro for standalone
+* 1.00a xd   07/19/07 Included xparameters.h as XPAR_ constants are referred
+*                     to in MICROBLAZE section
+* 1.00a ecm  09/19/08 updated for v7.20 of Microblaze, new functionality
+*
+* </pre>
+*
+*
+******************************************************************************/
+
+/**
+ *@cond nocomments
+ */
+
+#ifndef XENV_STANDALONE_H
+#define XENV_STANDALONE_H
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+/******************************************************************************
+ *
+ * Get the processor dependent includes
+ *
+ ******************************************************************************/
+
+#include <string.h>
+
+#if defined __MICROBLAZE__
+#  include "mb_interface.h"
+#  include "xparameters.h"   /* XPAR constants used below in MB section */
+
+#elif defined __PPC__
+#  include "sleep.h"
+#  include "xcache_l.h"      /* also include xcache_l.h for caching macros */
+#endif
+
+/******************************************************************************
+ *
+ * MEMCPY / MEMSET related macros.
+ *
+ * The following are straight forward implementations of memset and memcpy.
+ *
+ * NOTE: memcpy may not work if source and target memory area are overlapping.
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param	DestPtr
+ *		Destination address to copy data to.
+ *
+ * @param	SrcPtr
+ * 		Source address to copy data from.
+ *
+ * @param	Bytes
+ * 		Number of bytes to copy.
+ *
+ * @return	None.
+ *
+ * @note
+ * 		The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
+ *
+ * @note
+ * 		This implementation MAY BREAK work if source and target memory
+ * 		area are overlapping.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
+	memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
+
+
+
+/*****************************************************************************/
+/**
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param	DestPtr
+ *		Destination address to copy data to.
+ *
+ * @param	Data
+ * 		Value to set.
+ *
+ * @param	Bytes
+ * 		Number of bytes to copy.
+ *
+ * @return	None.
+ *
+ * @note
+ * 		The use of XENV_MEM_FILL is deprecated. Use memset() instead.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
+	memset((void *) DestPtr, (s32) Data, (size_t) Bytes)
+
+
+
+/******************************************************************************
+ *
+ * TIME related macros
+ *
+ ******************************************************************************/
+
+/**
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+typedef s32 XENV_TIME_STAMP;
+
+/*****************************************************************************/
+/**
+ *
+ * Time is derived from the 64 bit PPC timebase register
+ *
+ * @param   StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return  None.
+ *
+ * @note
+ *
+ * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ * <br><br>
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_GET(StampPtr)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param   Stamp1Ptr is the first sampled time stamp.
+ * @param   Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return  0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr)     (0)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param   Stamp1Ptr is the first sampled time stamp.
+ * @param   Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return  0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr)     (0)
+
+/*****************************************************************************/
+/**
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds. Not implemented without OS
+ * support.
+ *
+ * @param	delay
+ * 		Number of microseconds to delay.
+ *
+ * @return	None.
+ *
+ *****************************************************************************/
+
+#ifdef __PPC__
+#define XENV_USLEEP(delay)	usleep(delay)
+#define udelay(delay)	usleep(delay)
+#else
+#define XENV_USLEEP(delay)
+#define udelay(delay)
+#endif
+
+
+/******************************************************************************
+ *
+ * CACHE handling macros / mappings
+ *
+ ******************************************************************************/
+/******************************************************************************
+ *
+ * Processor independent macros
+ *
+ ******************************************************************************/
+
+#define XCACHE_ENABLE_CACHE()	\
+		{ XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
+
+#define XCACHE_DISABLE_CACHE()	\
+		{ XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
+
+
+/******************************************************************************
+ *
+ * MicroBlaze case
+ *
+ * NOTE: Currently the following macros will only work on systems that contain
+ * only ONE MicroBlaze processor. Also, the macros will only be enabled if the
+ * system is built using a xparameters.h file.
+ *
+ ******************************************************************************/
+
+#if defined __MICROBLAZE__
+
+/* Check if MicroBlaze data cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
+#  define XCACHE_ENABLE_DCACHE()		microblaze_enable_dcache()
+#  define XCACHE_DISABLE_DCACHE()		microblaze_disable_dcache()
+#  define XCACHE_INVALIDATE_DCACHE()  	microblaze_invalidate_dcache()
+
+#  define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+			microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
+
+#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
+#  define XCACHE_FLUSH_DCACHE()  		microblaze_flush_dcache()
+#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+			microblaze_flush_dcache_range((s32)(Addr), (s32)(Len))
+#else
+#  define XCACHE_FLUSH_DCACHE()  		microblaze_invalidate_dcache()
+#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+			microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
+#endif	/*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
+
+#else
+#  define XCACHE_ENABLE_DCACHE()
+#  define XCACHE_DISABLE_DCACHE()
+#  define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
+#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
+#endif	/*XPAR_MICROBLAZE_USE_DCACHE*/
+
+
+/* Check if MicroBlaze instruction cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
+#  define XCACHE_ENABLE_ICACHE()		microblaze_enable_icache()
+#  define XCACHE_DISABLE_ICACHE()		microblaze_disable_icache()
+
+#  define XCACHE_INVALIDATE_ICACHE()  	microblaze_invalidate_icache()
+
+#  define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
+			microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len))
+
+#else
+#  define XCACHE_ENABLE_ICACHE()
+#  define XCACHE_DISABLE_ICACHE()
+#endif	/*XPAR_MICROBLAZE_USE_ICACHE*/
+
+
+/******************************************************************************
+ *
+ * PowerPC case
+ *
+ *   Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
+ *   specific memory region (0x80000001). Each bit (0-30) in the regions
+ *   bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
+ *   range.
+ *
+ *   regions    --> cached address range
+ *   ------------|--------------------------------------------------
+ *   0x80000000  | [0, 0x7FFFFFF]
+ *   0x00000001  | [0xF8000000, 0xFFFFFFFF]
+ *   0x80000001  | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
+ *
+ ******************************************************************************/
+
+#elif defined __PPC__
+
+#define XCACHE_ENABLE_DCACHE()		XCache_EnableDCache(0x80000001)
+#define XCACHE_DISABLE_DCACHE()		XCache_DisableDCache()
+#define XCACHE_ENABLE_ICACHE()		XCache_EnableICache(0x80000001)
+#define XCACHE_DISABLE_ICACHE()		XCache_DisableICache()
+
+#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+		XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len))
+
+#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+		XCache_FlushDCacheRange((u32)(Addr), (u32)(Len))
+
+#define XCACHE_INVALIDATE_ICACHE()	XCache_InvalidateICache()
+
+
+/******************************************************************************
+ *
+ * Unknown processor / architecture
+ *
+ ******************************************************************************/
+
+#else
+/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* #ifndef XENV_STANDALONE_H */
+
+ /**
+ *@endcond
+ */

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/microblaze_ps/standalone_domain/bsp/microblaze_ps/include/xgpio.h

@@ -0,0 +1,212 @@
+/******************************************************************************
+* Copyright (C) 2002 - 2021 Xilinx, Inc.  All rights reserved.
+* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+* @file xgpio.h
+* @addtogroup gpio Overview
+* @{
+* @details
+*
+* This section explains the implementation of the XGpio driver's basic
+* functionality.
+* This header file contains the software API definition of the Xilinx General
+* Purpose I/O (XGpio) device driver.
+*
+* The Xilinx GPIO controller is a soft IP core designed for Xilinx FPGAs and
+* contains the following general features:
+*   - Support for up to 32 I/O discretes for each channel (64 bits total).
+*   - Each of the discretes can be configured for input or output.
+*   - Configurable support for dual channels and interrupt generation.
+*
+* The driver provides interrupt management functions. Implementation of
+* interrupt handlers is left to the user. Refer to the provided interrupt
+* example in the examples directory for details.
+*
+* This driver is intended to be RTOS and processor independent. Any needs for
+* dynamic memory management, threads or thread mutual exclusion, virtual
+* memory, or cache control must be satisfied by the layer above this driver.
+*
+* <b>Initialization & Configuration</b>
+*
+* The XGpio_Config structure is used by the driver to configure itself. This
+* configuration structure is typically created by the tool-chain based on HW
+* build properties.
+*
+* To support multiple runtime loading and initialization strategies employed
+* by various operating systems, the driver instance can be initialized in one
+* of the following ways:
+*
+*   - XGpio_Initialize(InstancePtr, DeviceId) - The driver looks up its own
+*     configuration structure created by the tool-chain based on an ID provided
+*     by the tool-chain.
+*
+*   - XGpio_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+*     configuration structure provided by the caller. If running in a system
+*     with address translation, the provided virtual memory base address
+*     replaces the physical address present in the configuration structure.
+*
+* @note
+*
+* This API utilizes 32 bit I/O to the GPIO registers. With less than 32 bits,
+* the unused bits from registers are read as zero and written as don't cares.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a rmm  03/13/02 First release
+* 2.00a jhl  11/26/03 Added support for dual channels and interrupts
+* 2.01a jvb  12/14/05 I separated dependency on the static config table and
+*                     xparameters.h from the driver initialization by moving
+*                     _Initialize and _LookupConfig to _sinit.c. I also added
+*                     the new _CfgInitialize routine.
+* 2.11a mta  03/21/07 Updated to new coding style, added GetDataDirection
+* 2.12a sv   11/21/07 Updated driver to support access through DCR bus
+* 2.12a sv   06/05/08 Updated driver to fix the XGpio_InterruptDisable function
+*		      to properly update the Interrupt Enable register
+* 2.13a sdm  08/22/08 Removed support for static interrupt handlers from the MDD
+*		      file
+* 3.00a sv   11/21/09 Updated to use HAL Processor APIs.
+*		      Renamed the macros XGpio_mWriteReg to XGpio_WriteReg and
+*		      XGpio_mReadReg to XGpio_ReadReg. Removed the macros
+*		      XGpio_mSetDataDirection, XGpio_mGetDataReg and
+*		      XGpio_mSetDataReg. Users should use XGpio_WriteReg and
+*		      XGpio_ReadReg to achieve the same functionality.
+* 3.01a bss  04/18/13 Updated driver tcl to generate Canonical params in
+*		      xparameters.h. CR#698589
+* 4.0   adk  19/12/13 Updated as per the New Tcl API's
+* 4.1   lks  11/18/15 Updated to use canonical xparameters in examples and
+*		      clean up of the comments, removed support for DCR bridge
+*		      and removed xgpio_intr_example for CR 900381
+* 4.2   sk   08/16/16 Used UINTPTR instead of u32 for Baseaddress as part of
+*                     adding 64 bit support. CR# 867425.
+*                     Changed the prototype of XGpio_CfgInitialize API.
+* 4.3   sk   09/29/16 Modified the example to make it work when LED_bits are
+*                     configured as an output. CR# 958644
+*       ms   01/23/17 Added xil_printf statement in main function for all
+*                     examples to ensure that "Successfully ran" and "Failed"
+*                     strings are available in all examples. This is a fix
+*                     for CR-965028.
+*       ms   03/17/17 Added readme.txt file in examples folder for doxygen
+*                     generation.
+* 4.4   sne  04/25/19 Updated Makefile for IAR compier (CR-1029421).
+* 4.5   sne  06/14/19 Fixed IAR compiler warnings on example files.
+* 4.6	sne  08/11/19 Fixed compilation error of armcc compiler.
+* 4.7   sne  08/28/20 Modify Makefile to support parallel make execution.
+* 4.8	sne  02/10/21 Fixed doxygen warnings.
+* 4.10  gm   07/11/23 Added SDT support.
+* 4.10  gm   08/28/23 Added Width member to XGpio_Config in SDT flow.
+*
+* </pre>
+*****************************************************************************/
+
+#ifndef XGPIO_H			/* prevent circular inclusions */
+#define XGPIO_H			/**< by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xgpio_l.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+#ifndef SDT
+	u16 DeviceId;		/**< Unique ID  of device */
+#else
+	char *Name;
+#endif
+	UINTPTR BaseAddress;	/**< Device base address */
+	int InterruptPresent;	/**< Are interrupts supported in h/w */
+	int IsDual;		/**< Are 2 channels supported in h/w */
+#ifdef SDT
+	u16 IntrId; /** Bits[11:0] Interrupt-id Bits[15:12] trigger type and level flags */
+	UINTPTR IntrParent; /** Bit[0] Interrupt parent type Bit[64/32:1] Parent base address */
+	u16 Width;  /** Gpio width */
+#endif
+} XGpio_Config;
+
+/**
+ * The XGpio driver instance data. The user is required to allocate a
+ * variable of this type for every GPIO device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	UINTPTR BaseAddress;	/**< Device base address */
+	u32 IsReady;		/**< Device is initialized and ready */
+	int InterruptPresent;	/**< Are interrupts supported in h/w */
+	int IsDual;		/**< Are 2 channels supported in h/w */
+} XGpio;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes *****************************/
+
+/*
+ * Initialization functions in xgpio_sinit.c
+ */
+#ifndef SDT
+int XGpio_Initialize(XGpio *InstancePtr, u16 DeviceId);
+XGpio_Config *XGpio_LookupConfig(u16 DeviceId);
+#else
+int XGpio_Initialize(XGpio *InstancePtr, UINTPTR BaseAddress);
+XGpio_Config *XGpio_LookupConfig(UINTPTR BaseAddress);
+#endif
+
+/*
+ * API Basic functions implemented in xgpio.c
+ */
+int XGpio_CfgInitialize(XGpio *InstancePtr, XGpio_Config * Config,
+			UINTPTR EffectiveAddr);
+void XGpio_SetDataDirection(XGpio *InstancePtr, unsigned Channel,
+			    u32 DirectionMask);
+u32 XGpio_GetDataDirection(XGpio *InstancePtr, unsigned Channel);
+u32 XGpio_DiscreteRead(XGpio *InstancePtr, unsigned Channel);
+void XGpio_DiscreteWrite(XGpio *InstancePtr, unsigned Channel, u32 Mask);
+
+
+/*
+ * API Functions implemented in xgpio_extra.c
+ */
+void XGpio_DiscreteSet(XGpio *InstancePtr, unsigned Channel, u32 Mask);
+void XGpio_DiscreteClear(XGpio *InstancePtr, unsigned Channel, u32 Mask);
+
+/*
+ * API Functions implemented in xgpio_selftest.c
+ */
+int XGpio_SelfTest(XGpio *InstancePtr);
+
+/*
+ * API Functions implemented in xgpio_intr.c
+ */
+void XGpio_InterruptGlobalEnable(XGpio *InstancePtr);
+void XGpio_InterruptGlobalDisable(XGpio *InstancePtr);
+void XGpio_InterruptEnable(XGpio *InstancePtr, u32 Mask);
+void XGpio_InterruptDisable(XGpio *InstancePtr, u32 Mask);
+void XGpio_InterruptClear(XGpio *InstancePtr, u32 Mask);
+u32 XGpio_InterruptGetEnabled(XGpio *InstancePtr);
+u32 XGpio_InterruptGetStatus(XGpio *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/microblaze_ps/standalone_domain/bsp/microblaze_ps/include/xgpio_i.h

@@ -0,0 +1,57 @@
+/******************************************************************************
+* Copyright (C) 2002 - 2021 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/******************************************************************************/
+/**
+* @file xgpio_i.h
+* @addtogroup gpio Overview
+* @{
+*
+* The xgpio_i.h header file contains internal identifiers, which are those
+* shared between the files of the driver. It is intended for internal use only.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a rmm  03/13/02 First release
+* 2.11a mta  03/21/07 Updated to new coding style
+* </pre>
+******************************************************************************/
+
+#ifndef XGPIO_I_H		/* prevent circular inclusions */
+#define XGPIO_I_H		/**< by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xgpio.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions ****************************/
+
+extern XGpio_Config XGpio_ConfigTable[];
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/microblaze_ps/standalone_domain/bsp/microblaze_ps/include/xgpio_l.h

@@ -0,0 +1,167 @@
+/******************************************************************************
+* Copyright (C) 2002 - 2021 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xgpio_l.h
+* @addtogroup gpio Overview
+* @{
+*
+* This header file contains identifiers and driver functions (or
+* macros) that can be used to access the device.  The user should refer to the
+* hardware device specification for more details of the device operation.
+*
+* The macros that are available in this file use a multiply to calculate the
+* addresses of registers. The user can control whether that multiply is done
+* at run time or at compile time. A constant passed as the channel parameter
+* will cause the multiply to be done at compile time. A variable passed as the
+* channel parameter will cause it to occur at run time.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a jhl  04/24/02 First release of low level driver
+* 2.00a jhl  11/26/03 Added support for dual channels and interrupts. This
+*                     change required the functions to be changed such that
+*                     the interface is not compatible with previous versions.
+*                     See the examples in the example directory for macros
+*                     to help compile an application that was designed for
+*                     previous versions of the driver. The interrupt registers
+*                     are accessible using the ReadReg and WriteReg macros and
+*                     a channel parameter was added to the other macros.
+* 2.11a mta  03/21/07 Updated to new coding style
+* 2.12a sv   11/21/07 Updated driver to support access through DCR bus.
+* 3.00a sv   11/21/09 Renamed the macros XGpio_mWriteReg to XGpio_WriteReg
+*		      XGpio_mReadReg to XGpio_ReadReg.
+*		      Removed the macros XGpio_mSetDataDirection,
+*		      XGpio_mGetDataReg and XGpio_mSetDataReg. Users
+*		      should use XGpio_WriteReg/XGpio_ReadReg to achieve the
+*		      same functionality.
+* 4.1  lks   11/18/15 Removed support for DCR bridge
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XGPIO_L_H		/* prevent circular inclusions */
+#define XGPIO_L_H		/**< by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+
+/************************** Constant Definitions *****************************/
+
+/** @name Registers
+ *
+ * Register offsets for this device.
+ * @{
+ */
+#define XGPIO_DATA_OFFSET	0x0   /**< Data register for 1st channel */
+#define XGPIO_TRI_OFFSET	0x4   /**< I/O direction reg for 1st channel */
+#define XGPIO_DATA2_OFFSET	0x8   /**< Data register for 2nd channel */
+#define XGPIO_TRI2_OFFSET	0xC   /**< I/O direction reg for 2nd channel */
+
+#define XGPIO_GIE_OFFSET	0x11C /**< Glogal interrupt enable register */
+#define XGPIO_ISR_OFFSET	0x120 /**< Interrupt status register */
+#define XGPIO_IER_OFFSET	0x128 /**< Interrupt enable register */
+
+/** @} */
+
+/* The following constant describes the offset of each channels data and
+ * tristate register from the base address.
+ */
+#define XGPIO_CHAN_OFFSET  8	/**< Channel offeset */
+
+/** @name Interrupt Status and Enable Register bitmaps and masks
+ *
+ * Bit definitions for the interrupt status register and interrupt enable
+ * registers.
+ * @{
+ */
+#define XGPIO_IR_MASK		0x3 /**< Mask of all bits */
+#define XGPIO_IR_CH1_MASK	0x1 /**< Mask for the 1st channel */
+#define XGPIO_IR_CH2_MASK	0x2 /**< Mask for the 2nd channel */
+/** @}*/
+
+
+/** @name Global Interrupt Enable Register bitmaps and masks
+ *
+ * Bit definitions for the Global Interrupt  Enable register
+ * @{
+ */
+#define XGPIO_GIE_GINTR_ENABLE_MASK	0x80000000 /**< Mask for Global Interrupt */
+/** @}*/
+
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XGpio_In32  Xil_In32	/**< Input Operations */
+#define XGpio_Out32 Xil_Out32	/**< Output Operations */
+
+
+/****************************************************************************/
+/**
+*
+* Write a value to a GPIO register. A 32 bit write is performed. If the
+* GPIO core is implemented in a smaller width, only the least significant data
+* is written.
+*
+* @param	BaseAddress is the base address of the GPIO device.
+* @param	RegOffset is the register offset from the base to write to.
+* @param	Data is the data written to the register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XGpio_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+****************************************************************************/
+#define XGpio_WriteReg(BaseAddress, RegOffset, Data) \
+	XGpio_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+
+/****************************************************************************/
+/**
+*
+* Read a value from a GPIO register. A 32 bit read is performed. If the
+* GPIO core is implemented in a smaller width, only the least
+* significant data is read from the register. The most significant data
+* will be read as 0.
+*
+* @param	BaseAddress is the base address of the GPIO device.
+* @param	RegOffset is the register offset from the base to read from.
+*
+* @return	Data read from the register.
+*
+* @note		C-style signature:
+*		u32 XGpio_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+****************************************************************************/
+#define XGpio_ReadReg(BaseAddress, RegOffset) \
+	XGpio_In32((BaseAddress) + (RegOffset))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/microblaze_ps/standalone_domain/bsp/microblaze_ps/include/xil_assert.h

@@ -0,0 +1,176 @@
+/******************************************************************************
+* Copyright (c) 2009 - 2021 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xil_assert.h
+*
+* @addtogroup common_assert_apis Assert APIs and Macros
+*
+* The xil_assert.h file contains assert related functions and macros.
+* Assert APIs/Macros specifies that a application program satisfies certain
+* conditions at particular points in its execution. These function can be
+* used by application programs to ensure that, application code is satisfying
+* certain conditions.
+*
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 First release
+* 6.0   kvn  05/31/16 Make Xil_AsserWait a global variable
+* </pre>
+*
+******************************************************************************/
+
+/**
+ *@cond nocomments
+ */
+
+#ifndef XIL_ASSERT_H	/* prevent circular inclusions */
+#define XIL_ASSERT_H	/* by using protection macros */
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+
+/************************** Constant Definitions *****************************/
+
+#define XIL_ASSERT_NONE     0U
+#define XIL_ASSERT_OCCURRED 1U
+#define XNULL NULL
+
+extern u32 Xil_AssertStatus;
+extern s32 Xil_AssertWait;
+extern void Xil_Assert(const char8 *File, s32 Line);
+/**
+ *@endcond
+ */
+void XNullHandler(void *NullParameter);
+
+/**
+ * This data type defines a callback to be invoked when an
+ * assert occurs. The callback is invoked only when asserts are enabled
+ */
+typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#ifndef NDEBUG
+
+/*****************************************************************************/
+/**
+* @brief    This assert macro is to be used for void functions. This in
+*           conjunction with the Xil_AssertWait boolean can be used to
+*           accommodate tests so that asserts which fail allow execution to
+*           continue.
+*
+* @param    Expression: expression to be evaluated. If it evaluates to
+*           false, the assert occurs.
+*
+* @return   Returns void unless the Xil_AssertWait variable is true, in which
+*           case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertVoid(Expression)                \
+{                                                  \
+    if (Expression) {                              \
+        Xil_AssertStatus = XIL_ASSERT_NONE;       \
+    } else {                                       \
+        Xil_Assert(__FILE__, __LINE__);            \
+        Xil_AssertStatus = XIL_ASSERT_OCCURRED;   \
+        return;                                    \
+    }                                              \
+}
+
+/*****************************************************************************/
+/**
+* @brief    This assert macro is to be used for functions that do return a
+*           value. This in conjunction with the Xil_AssertWait boolean can be
+*           used to accommodate tests so that asserts which fail allow execution
+*           to continue.
+*
+* @param    Expression: expression to be evaluated. If it evaluates to false,
+*           the assert occurs.
+*
+* @return   Returns 0 unless the Xil_AssertWait variable is true, in which
+* 	        case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertNonvoid(Expression)             \
+{                                                  \
+    if (Expression) {                              \
+        Xil_AssertStatus = XIL_ASSERT_NONE;       \
+    } else {                                       \
+        Xil_Assert(__FILE__, __LINE__);            \
+        Xil_AssertStatus = XIL_ASSERT_OCCURRED;   \
+        return 0;                                  \
+    }                                              \
+}
+
+/*****************************************************************************/
+/**
+* @brief     Always assert. This assert macro is to be used for void functions.
+*            Use for instances where an assert should always occur.
+*
+* @return    Returns void unless the Xil_AssertWait variable is true, in which
+*	         case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertVoidAlways()                   \
+{                                                  \
+   Xil_Assert(__FILE__, __LINE__);                 \
+   Xil_AssertStatus = XIL_ASSERT_OCCURRED;        \
+   return;                                         \
+}
+
+/*****************************************************************************/
+/**
+* @brief   Always assert. This assert macro is to be used for functions that
+*          do return a value. Use for instances where an assert should always
+*          occur.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+*	      case no return is made and an infinite loop is entered.
+*
+******************************************************************************/
+#define Xil_AssertNonvoidAlways()                \
+{                                                  \
+   Xil_Assert(__FILE__, __LINE__);                 \
+   Xil_AssertStatus = XIL_ASSERT_OCCURRED;        \
+   return 0;                                       \
+}
+
+
+#else
+
+#define Xil_AssertVoid(Expression)
+#define Xil_AssertVoidAlways()
+#define Xil_AssertNonvoid(Expression)
+#define Xil_AssertNonvoidAlways()
+
+#endif
+
+/************************** Function Prototypes ******************************/
+
+void Xil_AssertSetCallback(Xil_AssertCallback Routine);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
+/**
+* @} End of "addtogroup common_assert_apis".
+*/

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/microblaze_ps/standalone_domain/bsp/microblaze_ps/include/xil_cache.h

@@ -0,0 +1,402 @@
+/******************************************************************************
+* Copyright (c) 2009 - 2021 Xilinx, Inc.  All rights reserved.
+* Copyright (c) 2022 - 2023 Advanced Micro Devices, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xil_cache.h
+*
+* @addtogroup microblaze_cache_apis Microblaze Cache APIs
+* @{
+*
+*
+* The xil_cache.h file contains cache related driver functions (or macros)
+* that can be used to access the device.  The user should refer to the
+* hardware device specification for more details of the device operation.
+* The functions in this header file can be used across all Xilinx supported
+* processors.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00  hbm  07/28/09 Initial release
+* 3.02a sdm  10/24/11 Updated the file to include xparameters.h so that
+*                     the correct cache flush routines are used based on
+*                     whether the write-back or write-through caches are
+*                     used (cr #630532).
+* 3.10a asa  05/04/13 This version of MicroBlaze BSP adds support for system
+*					  cache/L2 cache. The existing/old APIs/macros in this
+*					  file are renamed to imply that they deal with L1 cache.
+*					  New macros/APIs are added to address similar features for
+*					  L2 cache. Users can include this file in their application
+*					  to use the various cache related APIs. These changes are
+*					  done for implementing PR #697214.
+*
+* </pre>
+*
+*
+******************************************************************************/
+
+#ifndef XIL_CACHE_H
+#define XIL_CACHE_H
+
+#if defined XENV_VXWORKS
+/* VxWorks environment */
+#error "Unknown processor / architecture. Must be PPC for VxWorks."
+#else
+/* standalone environment */
+
+#include "mb_interface.h"
+#include "xil_types.h"
+#ifndef SDT
+#include "xparameters.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/****************************************************************************/
+/**
+*
+* @brief    Invalidate the entire L1 data cache. If the cacheline is modified
+*            (dirty), the modified contents are lost.
+*
+*
+* @return   None.
+*
+* @note		Processor must be in real mode.
+****************************************************************************/
+#define Xil_L1DCacheInvalidate() microblaze_invalidate_dcache()
+
+/****************************************************************************/
+/**
+*
+* @brief    Invalidate the entire L2 data cache. If the cacheline is modified
+*           (dirty),the modified contents are lost.
+*
+* @return   None.
+*
+* @note		Processor must be in real mode.
+****************************************************************************/
+#define Xil_L2CacheInvalidate() microblaze_invalidate_cache_ext()
+
+/****************************************************************************/
+/**
+*
+* @brief    Invalidate the L1 data cache for the given address range.
+*           If the bytes specified by the address (Addr) are cached by the L1
+*           data cache, the cacheline containing that byte is invalidated.If
+*           the cacheline is modified (dirty), the modified contents are lost.
+*
+* @param    Addr is address of range to be invalidated.
+* @param    Len is the length in bytes to be invalidated.
+*
+* @return   None.
+*
+* @note     Processor must be in real mode.
+****************************************************************************/
+#define Xil_L1DCacheInvalidateRange(Addr, Len) \
+			microblaze_invalidate_dcache_range((Addr), (Len))
+
+/****************************************************************************/
+/**
+*
+* @brief    Invalidate the L1 data cache for the given address range.
+*           If the bytes specified by the address (Addr) are cached by the
+*           L1 data cache, the cacheline containing that byte is invalidated.
+*           If the cacheline is modified (dirty), the modified contents are lost.
+*
+* @param    Addr: address of range to be invalidated.
+* @param    Len: length in bytes to be invalidated.
+*
+* @return   None.
+*
+* @note     Processor must be in real mode.
+****************************************************************************/
+#define Xil_L2CacheInvalidateRange(Addr, Len) \
+		microblaze_invalidate_cache_ext_range((Addr), (Len))
+
+/****************************************************************************/
+/**
+* @brief   Flush the L1 data cache for the given address range.
+*          If the bytes specified by the address (Addr) are cached by the
+*          data cache, and is modified (dirty), the cacheline will be written
+*          to system memory.The cacheline will also be invalidated.
+*
+* @param    Addr: the starting address of the range to be flushed.
+* @param    Len: length in byte to be flushed.
+*
+* @return   None.
+*
+****************************************************************************/
+#ifndef SDT
+#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
+#   define Xil_L1DCacheFlushRange(Addr, Len) \
+		microblaze_flush_dcache_range((Addr), (Len))
+#else
+#   define Xil_L1DCacheFlushRange(Addr, Len) \
+		microblaze_invalidate_dcache_range((Addr), (Len))
+#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK */
+#else
+void Xil_L1DCacheFlushRange(UINTPTR Addr,u32 Len);
+#endif /* #ifndef SDT */
+/****************************************************************************/
+/**
+* @brief    Flush the L2 data cache for the given address range.
+*           If the bytes specified by the address (Addr) are cached by the
+*           data cache, and is modified (dirty), the cacheline will be
+*           written to system memory. The cacheline will also be invalidated.
+*
+* @param   Addr: the starting address of the range to be flushed.
+* @param   Len: length in byte to be flushed.
+*
+* @return   None.
+*
+****************************************************************************/
+#define Xil_L2CacheFlushRange(Addr, Len) \
+		microblaze_flush_cache_ext_range((Addr), (Len))
+
+/****************************************************************************/
+/**
+* @brief    Flush the entire L1 data cache. If any cacheline is dirty, the
+*           cacheline will be written to system memory. The entire data cache
+*           will be invalidated.
+*
+* @return   None.
+*
+****************************************************************************/
+#ifndef SDT
+#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
+#   define Xil_L1DCacheFlush() microblaze_flush_dcache()
+#else
+#   define Xil_L1DCacheFlush() microblaze_invalidate_dcache()
+#endif /* XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK */
+#else
+void Xil_L1DCacheFlush(void);
+#endif /* #ifndef SDT */
+
+/****************************************************************************/
+/**
+* @brief    Flush the entire L2 data cache. If any cacheline is dirty, the
+*           cacheline will be written to system memory. The entire data cache
+*           will be invalidated.
+*
+* @return   None.
+*
+****************************************************************************/
+#define Xil_L2CacheFlush() microblaze_flush_cache_ext()
+
+/****************************************************************************/
+/**
+*
+* @brief    Invalidate the instruction cache for the given address range.
+*
+* @param    Addr is address of ragne to be invalidated.
+* @param    Len is the length in bytes to be invalidated.
+*
+* @return   None.
+*
+****************************************************************************/
+#define Xil_L1ICacheInvalidateRange(Addr, Len) \
+			microblaze_invalidate_icache_range((Addr), (Len))
+
+/****************************************************************************/
+/**
+*
+* @brief    Invalidate the entire instruction cache.
+*
+* @return   None.
+*
+****************************************************************************/
+#define Xil_L1ICacheInvalidate() \
+			microblaze_invalidate_icache()
+
+
+/****************************************************************************/
+/**
+*
+* @brief    Enable the L1 data cache.
+*
+* @return   None.
+*
+* @note     This is processor specific.
+*
+****************************************************************************/
+#define Xil_L1DCacheEnable() \
+			microblaze_enable_dcache()
+
+/****************************************************************************/
+/**
+*
+* @brief    Disable the L1 data cache.
+*
+* @return   None.
+*
+* @note     This is processor specific.
+*
+****************************************************************************/
+#define Xil_L1DCacheDisable() \
+			microblaze_disable_dcache()
+
+/****************************************************************************/
+/**
+*
+* @brief    Enable the instruction cache.
+*
+* @return   None.
+*
+* @note     This is processor specific.
+*
+****************************************************************************/
+#define Xil_L1ICacheEnable() \
+			microblaze_enable_icache()
+
+/****************************************************************************/
+/**
+*
+* @brief    Disable the L1 Instruction cache.
+*
+* @return   None.
+*
+* @note     This is processor specific.
+*
+****************************************************************************/
+#define Xil_L1ICacheDisable() \
+			microblaze_disable_icache()
+
+/****************************************************************************/
+/**
+*
+* @brief    Enable the data cache.
+*
+* @return   None.
+*
+****************************************************************************/
+#define Xil_DCacheEnable() Xil_L1DCacheEnable()
+
+/****************************************************************************/
+/**
+*
+* @brief    Enable the instruction cache.
+*
+* @return   None.
+*
+*
+****************************************************************************/
+#define Xil_ICacheEnable() Xil_L1ICacheEnable()
+
+/****************************************************************************/
+/**
+*
+* @brief    Invalidate the entire Data cache.
+*
+* @return	None.
+*
+****************************************************************************/
+#define Xil_DCacheInvalidate() \
+	Xil_L2CacheInvalidate(); \
+	Xil_L1DCacheInvalidate();
+
+
+/****************************************************************************/
+/**
+*
+* @brief    Invalidate the Data cache for the given address range.
+*           If the bytes specified by the address (adr) are cached by the
+*           Data cache, the cacheline containing that byte is invalidated.
+*           If the cacheline is modified (dirty), the modified contents are
+*           lost and are NOT written to system memory before the line is
+*           invalidated.
+*
+* @param	Addr: Start address of range to be invalidated.
+* @param	Len: Length of range to be invalidated in bytes.
+*
+* @return	None.
+*
+****************************************************************************/
+#define Xil_DCacheInvalidateRange(Addr, Len) \
+	Xil_L2CacheInvalidateRange((Addr), (Len)); \
+	Xil_L1DCacheInvalidateRange((Addr), (Len));
+
+
+/****************************************************************************/
+/**
+*
+* @brief    Flush the entire Data cache.
+*
+* @return	None.
+*
+****************************************************************************/
+#define Xil_DCacheFlush() \
+	Xil_L2CacheFlush(); \
+	Xil_L1DCacheFlush();
+
+/****************************************************************************/
+/**
+* @brief     Flush the Data cache for the given address range.
+*            If the bytes specified by the address (adr) are cached by the
+*            Data cache, the cacheline containing that byte is invalidated.
+*            If the cacheline is modified (dirty), the written to system
+*            memory first before the before the line is invalidated.
+*
+* @param	Addr: Start address of range to be flushed.
+* @param	Len: Length of range to be flushed in bytes.
+*
+* @return	None.
+*
+****************************************************************************/
+#define Xil_DCacheFlushRange(Addr, Len) \
+	Xil_L2CacheFlushRange((Addr), (Len)); \
+	Xil_L1DCacheFlushRange((Addr), (Len));
+
+
+/****************************************************************************/
+/**
+* @brief    Invalidate the entire instruction cache.
+*
+* @return	None.
+*
+****************************************************************************/
+#define Xil_ICacheInvalidate() \
+	Xil_L2CacheInvalidate(); \
+	Xil_L1ICacheInvalidate();
+
+
+/****************************************************************************/
+/**
+* @brief     Invalidate the instruction cache for the given address range.
+*            If the bytes specified by the address (adr) are cached by the
+*            Data cache, the cacheline containing that byte is invalidated.
+*            If the cacheline is modified (dirty), the modified contents are
+*            lost and are NOT written to system memory before the line is
+*            invalidated.
+*
+* @param	Addr: Start address of ragne to be invalidated.
+* @param	Len: Length of range to be invalidated in bytes.
+*
+* @return	None.
+*
+****************************************************************************/
+#define Xil_ICacheInvalidateRange(Addr, Len) \
+	Xil_L2CacheInvalidateRange((Addr), (Len)); \
+	Xil_L1ICacheInvalidateRange((Addr), (Len));
+
+void Xil_DCacheDisable(void);
+void Xil_ICacheDisable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+/**
+* @} End of "addtogroup microblaze_cache_apis".
+*/

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/microblaze_ps/standalone_domain/bsp/microblaze_ps/include/xil_cache_vxworks.h

@@ -0,0 +1,75 @@
+/******************************************************************************
+* Copyright (c) 2009 - 2021 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xil_cache_vxworks.h
+*
+* Contains the cache related functions for VxWorks that is wrapped by
+* xil_cache.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  12/11/09 Initial release
+*
+* </pre>
+*
+* @note
+*
+******************************************************************************/
+
+/**
+ *@cond nocomments
+ */
+
+#ifndef XIL_CACHE_VXWORKS_H
+#define XIL_CACHE_VXWORKS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "vxWorks.h"
+#include "vxLib.h"
+#include "sysLibExtra.h"
+#include "cacheLib.h"
+
+#if (CPU_FAMILY==PPC)
+
+#define Xil_DCacheEnable()		cacheEnable(DATA_CACHE)
+
+#define Xil_DCacheDisable()		cacheDisable(DATA_CACHE)
+
+#define Xil_DCacheInvalidateRange(Addr, Len) \
+		cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
+
+#define Xil_DCacheFlushRange(Addr, Len) \
+		cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
+
+#define Xil_ICacheEnable()		cacheEnable(INSTRUCTION_CACHE)
+
+#define Xil_ICacheDisable()		cacheDisable(INSTRUCTION_CACHE)
+
+#define Xil_ICacheInvalidateRange(Addr, Len) \
+		cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
+
+
+#else
+#error "Unknown processor / architecture. Must be PPC for VxWorks."
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/**
+ *@endcond
+ */

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/microblaze_ps/standalone_domain/bsp/microblaze_ps/include/xil_clocking.h

@@ -0,0 +1,67 @@
+/******************************************************************************
+* Copyright (c) 2020 - 2022 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xil_clocking.h
+*
+* The xil_clocking.h file contains clocking related functions and macros.
+* certain conditions.
+*
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 7.2 sd  12/11/19 First release
+* 7.2 sd  03/20/20 Added checking for isolation case
+* 7.7 sk  01/10/22 Add function prototype for Xil_ClockGetRate to fix
+* 		   misra_c_2012_rule_8_4 violation.
+* 9.0 ml  03/03/23 Added description to fix doxygen warnings.
+* </pre>
+*
+******************************************************************************/
+
+#ifndef XIL_CLOCKING_H	/**< prevent circular inclusions */
+#define XIL_CLOCKING_H	/**< by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xdebug.h"
+#include "xil_printf.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xparameters.h"
+#include "xstatus.h"
+#if defined  (XPAR_XCRPSU_0_DEVICE_ID) || defined(XPAR_PSU_CRL_APB_BASEADDR)
+#include "xclockps.h"
+#else
+typedef u32 XClock_OutputClks;
+typedef u64 XClockRate;
+#endif
+
+/***************************** Include Files *********************************/
+
+
+/************************** Constant Definitions *****************************/
+
+
+XStatus Xil_ClockDisable(XClock_OutputClks ClockId);
+XStatus Xil_ClockEnable(XClock_OutputClks ClockId);
+XStatus Xil_ClockInit(void);
+XStatus Xil_ClockGet(void);
+XStatus Xil_ClockSetRate(XClock_OutputClks ClockId, XClockRate Rate, XClockRate *SetRate);
+XStatus Xil_ClockGetRate(XClock_OutputClks ClockId, XClockRate *Rate);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/microblaze_ps/standalone_domain/bsp/microblaze_ps/include/xil_cryptoalginfo.h

@@ -0,0 +1,50 @@
+/******************************************************************************/
+/**
+* Copyright (c) 2023 Advanced Micro Devices, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/****************************************************************************/
+/**
+* @file xil_cryptoalginfo.h
+* @{
+* @details
+*
+* Crypto algotithm information structure declaration.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 9.0   mmd      07/04/23 First release.
+* </pre>
+*
+*****************************************************************************/
+#ifndef XIL_CRYPTOALGINFO_H
+#define XIL_CRYPTOALGINFO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/**************************** Type Definitions *******************************/
+typedef enum _Xil_CryptoAlgNistStatus {
+	NOT_APPLICABLE = 0x00,
+	NIST_COMPLIANT = 0x11,
+	NIST_NON_COMPLIANT = 0xFE,
+} Xil_CryptoAlgNistStatus;
+
+typedef struct _Xil_CryptoAlgInfo {
+	u32 Version;
+	Xil_CryptoAlgNistStatus NistStatus;
+} Xil_CryptoAlgInfo;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XIL_CRYPTOALGINFO_H */

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/microblaze_ps/standalone_domain/bsp/microblaze_ps/include/xil_exception.h

@@ -0,0 +1,114 @@
+/******************************************************************************
+* Copyright (C) 2009 - 2021 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xil_exception.h
+*
+* @addtogroup microblaze_exception_apis Microblaze Exception APIs
+* @{
+*
+* The xil_exception.h file, available in the <install-directory>/src/microblaze folder,
+* contains Microblaze specific exception related APIs and macros. Application programs
+* can use these APIs for various exception related operations. For example, enable exception,
+* disable exception, register exception hander.
+*
+* @note To use exception related functions, xil_exception.h must be added in source code
+*
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00  hbm  07/28/09 Initial release
+* 9.0   ml   03/03/23 Add description to fix doxygen warnings.
+* </pre>
+*
+******************************************************************************/
+
+/**
+ *@cond nocomments
+ */
+#ifndef XIL_EXCEPTION_H /**< prevent circular inclusions */
+#define XIL_EXCEPTION_H /**< by using protection macros */
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * These constants are specific to Microblaze processor.
+ */
+
+#define XIL_EXCEPTION_ID_FIRST                0U
+#define XIL_EXCEPTION_ID_FSL                  0U
+#define XIL_EXCEPTION_ID_UNALIGNED_ACCESS     1U
+#define XIL_EXCEPTION_ID_ILLEGAL_OPCODE       2U
+#define XIL_EXCEPTION_ID_M_AXI_I_EXCEPTION    3U
+#define XIL_EXCEPTION_ID_IPLB_EXCEPTION       3U
+#define XIL_EXCEPTION_ID_M_AXI_D_EXCEPTION    4U
+#define XIL_EXCEPTION_ID_DPLB_EXCEPTION       4U
+#define XIL_EXCEPTION_ID_DIV_BY_ZERO          5U
+#define XIL_EXCEPTION_ID_FPU                  6U
+#define XIL_EXCEPTION_ID_STACK_VIOLATION      7U
+#define XIL_EXCEPTION_ID_MMU                  7U
+#define XIL_EXCEPTION_ID_LAST		      XIL_EXCEPTION_ID_MMU
+#define XIL_EXCEPTION_MASK		      0x100U
+#define XIL_INTERRUPTS_MASK		      0x2U
+/*
+ * XIL_EXCEPTION_ID_INT is defined for all processors, but with different value.
+ */
+#define XIL_EXCEPTION_ID_INT		      16U /**
+						  * exception ID for interrupt
+						  */
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef is the exception handler function.
+ */
+typedef void (*Xil_ExceptionHandler)(void *Data);
+
+/**
+ * This data type defines an interrupt handler for a device.
+ * The argument points to the instance of the component
+ */
+typedef void (*XInterruptHandler) (void *InstancePtr);
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
+					 Xil_ExceptionHandler Handler,
+					 void *Data);
+
+extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
+
+extern void Xil_ExceptionInit(void);
+extern void Xil_ExceptionEnable(void);
+extern void Xil_ExceptionDisable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/**
+ *@endcond
+ */
+
+/**
+* @} End of "addtogroup microblaze_exception_apis".
+*/

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/microblaze_ps/standalone_domain/bsp/microblaze_ps/include/xil_hal.h

@@ -0,0 +1,43 @@
+/******************************************************************************
+* Copyright (c) 2009 - 2020 Xilinx, Inc.  All rights reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xil_hal.h
+*
+* Contains all the HAL header files.
+*
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/28/09 Initial release
+*
+* </pre>
+*
+* @note
+*
+******************************************************************************/
+
+#ifndef XIL_HAL_H
+#define XIL_HAL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xil_cache.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+#include "xil_exception.h"
+#include "xil_types.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/vitis/dl814_k7_platform/microblaze_ps/standalone_domain/bsp/microblaze_ps/include/xil_io.h

@@ -0,0 +1,433 @@
+/******************************************************************************
+* Copyright (C) 2014 - 2021 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2022 - 2023 Advanced Micro Devices, Inc. All Rights Reserved.
+* SPDX-License-Identifier: MIT
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xil_io.h
+*
+* @addtogroup common_io_interfacing_apis Register IO interfacing APIs
+*
+* The xil_io.h file contains the interface for the general I/O component, which
+* encapsulates the Input/Output functions for the processors that do not
+* require any special I/O handling.
+*
+* @{
+* <pre>
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 05/29/14 First release
+* 6.00  mus      08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for
+*                         ARM processors
+* 7.20  har      01/03/20 Added Xil_SecureOut32 for avoiding blindwrite for
+*                         CR-1049218
+* 7.30  kpt      09/21/20 Moved Xil_EndianSwap16 and Xil_EndianSwap32 to
+*                         xil_io.h and made them as static inline
+*       am       10/13/20 Changed the return type of Xil_SecureOut32 function
+*                         from u32 to int
+* 7.50  dp       02/12/21 Fix compilation error in Xil_EndianSwap32() that occur
+*                         when -Werror=conversion compiler flag is enabled
+* 7.5   mus      05/17/21 Update the functions with comments. It fixes CR#1067739.
+* 9.0   ml       03/03/23 Add description and remove comments to fix doxygen warnings.
+* </pre>
+******************************************************************************/
+
+#ifndef XIL_IO_H           /**< prevent circular inclusions */
+#define XIL_IO_H           /**< by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_printf.h"
+#include "xstatus.h"
+
+#if defined (__MICROBLAZE__)
+#include "mb_interface.h"
+#else
+#include "xpseudo_asm.h"
+#endif
+
+/************************** Function Prototypes ******************************/
+#ifdef ENABLE_SAFETY
+extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal);
+#endif
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#if defined __GNUC__
+#if defined (__MICROBLAZE__)
+#  define INST_SYNC		mbar(0) /**< Instruction Synchronization Barrier */
+#  define DATA_SYNC		mbar(1) /**<  Data Synchronization Barrier  */
+# else
+#  define SYNCHRONIZE_IO	dmb() /**< Data Memory Barrier */
+#  define INST_SYNC		isb() /**< Instruction Synchronization Barrier */
+#  define DATA_SYNC		dsb() /**<  Data Synchronization Barrier  */
+# endif
+#else
+# define SYNCHRONIZE_IO /**< Data Memory Barrier */
+# define INST_SYNC /**< Instruction Synchronization Barrier */
+# define DATA_SYNC /**<  Data Synchronization Barrier  */
+# define INST_SYNC /**< Instruction Synchronization Barrier */
+# define DATA_SYNC /**<  Data Synchronization Barrier  */
+#endif
+
+#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__)
+#define INLINE inline /**< static inline keyword */
+#else
+#define INLINE __inline /**<static inline keyword */
+#endif
+
+/*****************************************************************************/
+/**
+*
+* @brief    Performs an input operation for a memory location by reading
+*           from the specified address and returning the 8 bit Value read from
+*            that address.
+*
+* @param	Addr contains the address to perform the input operation
+*
+* @return	The 8 bit Value read from the specified input address.
+
+*
+******************************************************************************/
+static INLINE u8 Xil_In8(UINTPTR Addr)
+{
+	return *(volatile u8 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Performs an input operation for a memory location by reading from
+*           the specified address and returning the 16 bit Value read from that
+*           address.
+*
+* @param	Addr contains the address to perform the input operation
+*
+* @return	The 16 bit Value read from the specified input address.
+*
+******************************************************************************/
+static INLINE u16 Xil_In16(UINTPTR Addr)
+{
+	return *(volatile u16 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Performs an input operation for a memory location by
+*           reading from the specified address and returning the 32 bit Value
+*           read  from that address.
+*
+* @param	Addr contains the address to perform the input operation
+*
+* @return	The 32 bit Value read from the specified input address.
+*
+******************************************************************************/
+static INLINE u32 Xil_In32(UINTPTR Addr)
+{
+	return *(volatile u32 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief     Performs an input operation for a memory location by reading the
+*            64 bit Value read  from that address.
+*
+*
+* @param	Addr contains the address to perform the input operation
+*
+* @return	The 64 bit Value read from the specified input address.
+*
+******************************************************************************/
+static INLINE u64 Xil_In64(UINTPTR Addr)
+{
+	return *(volatile u64 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Performs an output operation for an memory location by
+*           writing the 8 bit Value to the the specified address.
+*
+* @param	Addr contains the address to perform the output operation
+* @param	Value contains the 8 bit Value to be written at the specified
+*           address.
+*
+* @return	None.
+*
+******************************************************************************/
+static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
+{
+	/* write 8 bit value to specified address */
+	volatile u8 *LocalAddr = (volatile u8 *)Addr;
+	*LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Performs an output operation for a memory location by writing the
+*            16 bit Value to the the specified address.
+*
+* @param	Addr contains the address to perform the output operation
+* @param	Value contains the Value to be written at the specified address.
+*
+* @return	None.
+*
+******************************************************************************/
+static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
+{
+	/* write 16 bit value to specified address */
+	volatile u16 *LocalAddr = (volatile u16 *)Addr;
+	*LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Performs an output operation for a memory location by writing the
+*           32 bit Value to the the specified address.
+*
+* @param	Addr contains the address to perform the output operation
+* @param	Value contains the 32 bit Value to be written at the specified
+*           address.
+*
+* @return	None.
+*
+******************************************************************************/
+static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
+{
+	/* write 32 bit value to specified address */
+#ifndef ENABLE_SAFETY
+	volatile u32 *LocalAddr = (volatile u32 *)Addr;
+	*LocalAddr = Value;
+#else
+	XStl_RegUpdate(Addr, Value);
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Performs an output operation for a memory location by writing the
+*           64 bit Value to the the specified address.
+*
+* @param	Addr contains the address to perform the output operation
+* @param	Value contains 64 bit Value to be written at the specified address.
+*
+* @return	None.
+*
+******************************************************************************/
+static INLINE void Xil_Out64(UINTPTR Addr, u64 Value)
+{
+	/* write 64 bit value to specified address */
+	volatile u64 *LocalAddr = (volatile u64 *)Addr;
+	*LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+ *
+ * @brief	Performs an output operation for a memory location by writing the
+ *       	32 bit Value to the the specified address and then reading it
+ *       	back to verify the value written in the register.
+ *
+ * @param	Addr contains the address to perform the output operation
+ * @param	Value contains 32 bit Value to be written at the specified address
+ *
+ * @return	Returns Status
+ *        	- XST_SUCCESS on success
+ *        	- XST_FAILURE on failure
+ *
+ *****************************************************************************/
+static INLINE int Xil_SecureOut32(UINTPTR Addr, u32 Value)
+{
+	int Status = XST_FAILURE;
+	u32 ReadReg;
+	u32 ReadRegTemp;
+
+	/* writing 32 bit value to specified address */
+	Xil_Out32(Addr, Value);
+
+	/* verify value written to specified address with multiple reads */
+	ReadReg = Xil_In32(Addr);
+	ReadRegTemp = Xil_In32(Addr);
+
+	if( (ReadReg == Value) && (ReadRegTemp == Value) ) {
+		Status = XST_SUCCESS;
+	}
+
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Perform a 16-bit endian conversion.
+*
+* @param	Data 16 bit value to be converted
+*
+* @return	16 bit Data with converted endianness
+*
+******************************************************************************/
+static INLINE __attribute__((always_inline)) u16 Xil_EndianSwap16(u16 Data)
+{
+	return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U));
+}
+
+/*****************************************************************************/
+/**
+*
+* @brief    Perform a 32-bit endian conversion.
+*
+* @param	Data : 32 bit value to be converted
+*
+* @return	32 bit data with converted endianness
+*
+******************************************************************************/
+static INLINE __attribute__((always_inline)) u32 Xil_EndianSwap32(u32 Data)
+{
+	u16 LoWord;
+	u16 HiWord;
+
+	/* get each of the half words from the 32 bit word */
+
+	LoWord = (u16) (Data & 0x0000FFFFU);
+	HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U);
+
+	/* byte swap each of the 16 bit half words */
+
+	LoWord = (u16)(((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U));
+	HiWord = (u16)(((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U));
+
+	/* swap the half words before returning the value */
+
+	return ((((u32)LoWord) << (u32)16U) | (u32)HiWord);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+# define Xil_In16LE	Xil_In16 /**< Register Read of 16 Bits in Little Endian */
+# define Xil_In32LE	Xil_In32 /**< Register Read of 32 Bits in Little Endian */
+# define Xil_Out16LE	Xil_Out16 /**< Register Write of 16 Bits in Little Endian */
+# define Xil_Out32LE	Xil_Out32 /**< Register Write of 32 Bits in Little Endian */
+# define Xil_Htons	Xil_EndianSwap16 /**< Endian swap of 16 bits */
+# define Xil_Htonl	Xil_EndianSwap32 /**< Endian swap of 32 bits */
+# define Xil_Ntohs	Xil_EndianSwap16 /**< Endian swap of 16 bits */
+# define Xil_Ntohl	Xil_EndianSwap32 /**< Endian swap of 32 bits */
+# else
+# define Xil_In16BE	Xil_In16 /**< Register Read of 16 Bits in Big Endian */
+# define Xil_In32BE	Xil_In32 /**< Register Read of 32 Bits in Big Endian */
+# define Xil_Out16BE	Xil_Out16 /**< Register Write of 16 Bits in Big Endian */
+# define Xil_Out32BE	Xil_Out32 /**< Register Write of 32 Bits in Big Endian */
+# define Xil_Htons(Data) (Data) /**< Endian swap of 16 bits */
+# define Xil_Htonl(Data) (Data) /**< Endian swap of 32 bits */
+# define Xil_Ntohs(Data) (Data) /**< Endian swap of 16 bits */
+# define Xil_Ntohl(Data) (Data) /**< Endian swap of 32 bits */
+#endif
+#else
+# define Xil_In16LE	Xil_In16 /**< Register Read of 16 Bits in Little Endian */
+# define Xil_In32LE	Xil_In32 /**< Register Read of 32 Bits in Little Endian */
+# define Xil_Out16LE	Xil_Out16 /**< Register Write of 16 Bits in Little Endian */
+# define Xil_Out32LE	Xil_Out32 /**< Register Write of 32 Bits in Little Endian */
+# define Xil_Htons	Xil_EndianSwap16 /**< Endian swap of 16 bits */
+# define Xil_Htonl	Xil_EndianSwap32 /**< Endian swap of 32 bits */
+# define Xil_Ntohs	Xil_EndianSwap16 /**< Endian swap of 16 bits */
+# define Xil_Ntohl	Xil_EndianSwap32 /**< Endian swap of 32 bits */
+#endif
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE u16 Xil_In16BE(UINTPTR Addr) /**< Static inline function to Read
+                                                Register of 16 Bits in Big Endian */
+#else
+static INLINE u16 Xil_In16LE(UINTPTR Addr) /**< Static inline function to Read
+                                                Register of 16 Bits in Little Endian */
+#endif
+#else
+/**
+* Static inline function to Read Register of 16 Bits in Big Endian.
+**********************************************************************************/
+static INLINE u16 Xil_In16BE(UINTPTR Addr)
+#endif
+{
+	u16 value = Xil_In16(Addr);
+	return Xil_EndianSwap16(value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE u32 Xil_In32BE(UINTPTR Addr) /**< Static inline function to Read
+                                                Register of 32 Bits in Big Endian */
+#else
+static INLINE u32 Xil_In32LE(UINTPTR Addr) /**< Static inline function to Read
+                                                Register of 32 Bits in Little Endian */
+#endif
+#else
+/**
+* Static inline function to Read Register of 32 Bits in Big Endian.
+**********************************************************************************/
+static INLINE u32 Xil_In32BE(UINTPTR Addr)
+#endif
+{
+	u32 value = Xil_In32(Addr);
+	return Xil_EndianSwap32(value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value) /**< Static inline function to write
+                                                Register of 16 Bits in Big Endian */
+#else
+static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value) /**< Static inline function to write
+                                                Register of 16 Bits in Little Endian */
+#endif
+#else
+/**
+* Static inline function to write Register of 16 Bits in Big Endian.
+**********************************************************************************/
+static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value)
+#endif
+{
+	Value = Xil_EndianSwap16(Value);
+	Xil_Out16(Addr, Value);
+}
+
+#if defined (__MICROBLAZE__)
+#ifdef __LITTLE_ENDIAN__
+static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value) /**< Static inline function to write
+                                                Register of 32 Bits in Big Endian */
+#else
+static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value) /**< Static inline function to write
+                                                Register of 32 Bits in Little Endian */
+#endif
+#else
+/**
+* Static inline function to Read Register of 16 Bits in Big Endian.
+**********************************************************************************/
+static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
+#endif
+{
+	Value = Xil_EndianSwap32(Value);
+	Xil_Out32(Addr, Value);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_io_interfacing_apis".
+*/