add project duifei_cal_coarse
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version https://git-lfs.github.com/spec/v1
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oid sha256:087df634810175dc34ca2fcc9ae807b0765bc767a4b067092af9df11dff88809
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size 17416456
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# df_z7100_2ad9361
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## Timing Assertions Section
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## Physical Constraints Section
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# Clocks
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set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVDS } [get_ports clk_250m_p ] ;# FPGA_DAC_LOGIC_CLK_C_P
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set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS18} [get_ports ad9361_1_buffer_clk ] ;# AD9361_CLK_OUT
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set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS18} [get_ports ad9361_2_buffer_clk ] ;# B_AD9361_CLK_OUT
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# HMC7044-1 Interface
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set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVCMOS33} [get_ports hmc7044_spi_clk ] ;# HMC7044_1_SCLK
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set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVCMOS33} [get_ports hmc7044_spi_csn ] ;# HMC7044_1_SLEN
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set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVCMOS33} [get_ports hmc7044_spi_sdio ] ;# HMC7044_1_DATA
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set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS33} [get_ports hmc7044_reset ] ;# HMC7044_1_RESET
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set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVCMOS33} [get_ports hmc7044_sync ] ;# HMC7044_1_SYNC
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set_property -dict {PACKAGE_PIN AH16 IOSTANDARD LVCMOS33} [get_ports hmc7044_gpio[0] ] ;# HMC7044_1_GPIO1
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set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS33} [get_ports hmc7044_gpio[1] ] ;# HMC7044_1_GPIO2
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set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS33} [get_ports hmc7044_gpio[2] ] ;# HMC7044_1_GPIO3
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set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVCMOS33} [get_ports hmc7044_gpio[3] ] ;# HMC7044_1_GPIO4
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# AD9361-1 Interface
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set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data_clk ] ;# AD9361_DATA_CLK_P
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set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_frame ] ;# AD9361_RX_FRAME_P
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set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[0] ] ;# AD9361_TX_00_D0_N
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set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[1] ] ;# AD9361_TX_01_D0_P
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set_property -dict {PACKAGE_PIN C3 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[2] ] ;# AD9361_TX_02_D1_N
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set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[3] ] ;# AD9361_TX_03_D1_P
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set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[4] ] ;# AD9361_TX_04_D2_N
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set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[5] ] ;# AD9361_TX_05_D2_P
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set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[6] ] ;# AD9361_TX_06_D3_N
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set_property -dict {PACKAGE_PIN B5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[7] ] ;# AD9361_TX_07_D3_P
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set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[8] ] ;# AD9361_TX_08_D4_N
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set_property -dict {PACKAGE_PIN B9 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[9] ] ;# AD9361_TX_09_D4_P
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set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[10] ] ;# AD9361_TX_10_D5_N
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set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[11] ] ;# AD9361_TX_11_D5_P
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set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_fb_clk ] ;# AD9361_FB_CLK_P
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set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_frame ] ;# AD9361_TX_FRAME_P
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set_property -dict {PACKAGE_PIN A2 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[0] ] ;# AD9361_RX_00_D0_N
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set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[1] ] ;# AD9361_RX_01_D0_P
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set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[2] ] ;# AD9361_RX_02_D1_N
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set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[3] ] ;# AD9361_RX_03_D1_P
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set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[4] ] ;# AD9361_RX_04_D2_N
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set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[5] ] ;# AD9361_RX_05_D2_P
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set_property -dict {PACKAGE_PIN A10 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[6] ] ;# AD9361_RX_06_D3_N
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set_property -dict {PACKAGE_PIN B10 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[7] ] ;# AD9361_RX_07_D3_P
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set_property -dict {PACKAGE_PIN A7 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[8] ] ;# AD9361_RX_08_D4_N
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set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[9] ] ;# AD9361_RX_09_D4_P
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set_property -dict {PACKAGE_PIN C8 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[10] ] ;# AD9361_RX_10_D5_N
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set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[11] ] ;# AD9361_RX_11_D5_P
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set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_clk ] ;# AD9361_SPI_CLK
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set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_csn ] ;# AD9361_SPI_ENB
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set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_mosi ] ;# AD9361_SPI_DI
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set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_miso ] ;# AD9361_SPI_DO
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set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_reset_b ] ;# AD9361_RESETB
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set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_en_agc ] ;# AD9361_EN_AGC
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set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVCMOS18} [get_ports ad9361_1_enable ] ;# AD9361_ENABLE
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set_property -dict {PACKAGE_PIN A12 IOSTANDARD LVCMOS18} [get_ports ad9361_1_txnrx ] ;# AD9361_TXNRX
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set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[0] ] ;# AD9361_CTRL_IN0
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set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[1] ] ;# AD9361_CTRL_IN1
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set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[2] ] ;# AD9361_CTRL_IN2
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set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[3] ] ;# AD9361_CTRL_IN3
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set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[0] ] ;# AD9361_CTRL_OUT0
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set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[1] ] ;# AD9361_CTRL_OUT1
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set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[2] ] ;# AD9361_CTRL_OUT2
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set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[3] ] ;# AD9361_CTRL_OUT3
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set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[4] ] ;# AD9361_CTRL_OUT4
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set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[5] ] ;# AD9361_CTRL_OUT5
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set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[6] ] ;# AD9361_CTRL_OUT6
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set_property -dict {PACKAGE_PIN M12 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[7] ] ;# AD9361_CTRL_OUT7
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set_property -dict {PACKAGE_PIN F9 IOSTANDARD LVCMOS18} [get_ports ad9361_sync ] ;# AD9361_SYNC_IN
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# AD9361-2 Interface
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set_property -dict {PACKAGE_PIN G5 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data_clk ] ;# B_AD9361_DATA_CLK_P
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set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_frame ] ;# B_AD9361_RX_FRAME_P
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set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[0] ] ;# B_AD9361_TX_00_D0_N
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set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[1] ] ;# B_AD9361_TX_01_D0_P
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set_property -dict {PACKAGE_PIN H3 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[2] ] ;# B_AD9361_TX_02_D1_N
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set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[3] ] ;# B_AD9361_TX_03_D1_P
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set_property -dict {PACKAGE_PIN J6 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[4] ] ;# B_AD9361_TX_04_D2_N
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set_property -dict {PACKAGE_PIN K6 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[5] ] ;# B_AD9361_TX_05_D2_P
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set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[6] ] ;# B_AD9361_TX_06_D3_N
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set_property -dict {PACKAGE_PIN K5 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[7] ] ;# B_AD9361_TX_07_D3_P
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set_property -dict {PACKAGE_PIN L2 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[8] ] ;# B_AD9361_TX_08_D4_N
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set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[9] ] ;# B_AD9361_TX_09_D4_P
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set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[10] ] ;# B_AD9361_TX_10_D5_N
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set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[11] ] ;# B_AD9361_TX_11_D5_P
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set_property -dict {PACKAGE_PIN G10 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_fb_clk ] ;# B_AD9361_FB_CLK_P
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set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_frame ] ;# B_AD9361_TX_FRAME_P
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set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[0] ] ;# B_AD9361_RX_00_D0_N
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set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[1] ] ;# B_AD9361_RX_01_D0_P
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set_property -dict {PACKAGE_PIN F2 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[2] ] ;# B_AD9361_RX_02_D1_N
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set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[3] ] ;# B_AD9361_RX_03_D1_P
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set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[4] ] ;# B_AD9361_RX_04_D2_N
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set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[5] ] ;# B_AD9361_RX_05_D2_P
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set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[6] ] ;# B_AD9361_RX_06_D3_N
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set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[7] ] ;# B_AD9361_RX_07_D3_P
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set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[8] ] ;# B_AD9361_RX_08_D4_N
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set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[9] ] ;# B_AD9361_RX_09_D4_P
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set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[10] ] ;# B_AD9361_RX_10_D5_N
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set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[11] ] ;# B_AD9361_RX_11_D5_P
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set_property -dict {PACKAGE_PIN L9 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_clk ] ;# B_AD9361_SPI_CLK
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set_property -dict {PACKAGE_PIN M10 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_csn ] ;# B_AD9361_SPI_ENB
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set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_mosi ] ;# B_AD9361_SPI_DI
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set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_miso ] ;# B_AD9361_SPI_DO
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set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS18} [get_ports ad9361_2_reset_b ] ;# B_AD9361_RESETB
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set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS18} [get_ports ad9361_2_en_agc ] ;# B_AD9361_EN_AGC
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set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS18} [get_ports ad9361_2_enable ] ;# B_AD9361_ENABLE
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set_property -dict {PACKAGE_PIN J9 IOSTANDARD LVCMOS18} [get_ports ad9361_2_txnrx ] ;# B_AD9361_TXNRX
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set_property -dict {PACKAGE_PIN L10 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[0] ] ;# B_AD9361_CTRL_IN0
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set_property -dict {PACKAGE_PIN D6 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[1] ] ;# B_AD9361_CTRL_IN1
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set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[2] ] ;# B_AD9361_CTRL_IN2
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set_property -dict {PACKAGE_PIN K8 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[3] ] ;# B_AD9361_CTRL_IN3
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set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[0] ] ;# B_AD9361_CTRL_OUT0
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set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[1] ] ;# B_AD9361_CTRL_OUT1
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set_property -dict {PACKAGE_PIN K7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[2] ] ;# B_AD9361_CTRL_OUT2
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set_property -dict {PACKAGE_PIN L7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[3] ] ;# B_AD9361_CTRL_OUT3
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set_property -dict {PACKAGE_PIN G7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[4] ] ;# B_AD9361_CTRL_OUT4
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set_property -dict {PACKAGE_PIN H7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[5] ] ;# B_AD9361_CTRL_OUT5
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set_property -dict {PACKAGE_PIN K10 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[6] ] ;# B_AD9361_CTRL_OUT6
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set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[7] ] ;# B_AD9361_CTRL_OUT7
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# Phased-Array Control
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set_property -dict {PACKAGE_PIN AC28 IOSTANDARD LVTTL } [get_ports ant_clk ] ;# ANT_CLK
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set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVTTL } [get_ports ant_en ] ;# ANT_EN
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set_property -dict {PACKAGE_PIN AD29 IOSTANDARD LVTTL } [get_ports ant_data ] ;# ANT_DATA
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set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVTTL } [get_ports ant_tr ] ;# ANT_TR
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set_property -dict {PACKAGE_PIN AB27 IOSTANDARD LVTTL } [get_ports ant_dary ] ;# ANT_DARY
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set_property -dict {PACKAGE_PIN AC27 IOSTANDARD LVTTL } [get_ports ant_dout ] ;# ANT_DOUT
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# RF Synthesizer Control
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set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS33} [get_ports rf_standby ] ;# ANT_standby_R
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set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVCMOS33} [get_ports rf_sw_pll ] ;# ANT_SW_PLL_R
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set_property -dict {PACKAGE_PIN T23 IOSTANDARD LVCMOS33} [get_ports rf_t ] ;# ANT_T_R
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set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS33} [get_ports rf_r ] ;# ANT_R_R
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set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS33} [get_ports rf_sw_bpf ] ;# ANT_SW_BPF_R
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set_property -dict {PACKAGE_PIN R25 IOSTANDARD LVCMOS33} [get_ports rf_sclk1 ] ;# ANT_SCLK1_R
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set_property -dict {PACKAGE_PIN T27 IOSTANDARD LVCMOS33} [get_ports rf_sdio1 ] ;# ANT_SDIO1_R
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set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS33} [get_ports rf_cs1 ] ;# ANT_CS1_R
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set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVCMOS33} [get_ports rf_ld1 ] ;# ANT_LD1_R
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set_property -dict {PACKAGE_PIN U26 IOSTANDARD LVCMOS33} [get_ports rf_sclk2 ] ;# ANT_SCLK2_R
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set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVCMOS33} [get_ports rf_sdio2 ] ;# ANT_SDIO2_R
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set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS33} [get_ports rf_cs2 ] ;# ANT_CS2_R
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set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS33} [get_ports rf_ld2 ] ;# ANT_LD2_R
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set_property -dict {PACKAGE_PIN AE28 IOSTANDARD LVCMOS33} [get_ports rf_sclk3 ] ;# ANT_SCLK3_R
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set_property -dict {PACKAGE_PIN N29 IOSTANDARD LVCMOS33} [get_ports rf_sdio3 ] ;# ANT_SDIO3_R
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set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVCMOS33} [get_ports rf_cs3 ] ;# ANT_CS3_R
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set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVCMOS33} [get_ports rf_ld3 ] ;# ANT_LD3_R
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set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVCMOS33} [get_ports rf_tmgc_16 ] ;# ANT_TMGC_16_R
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set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVCMOS33} [get_ports rf_tmgc_8 ] ;# ANT_TMGC_8_R
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set_property -dict {PACKAGE_PIN AF27 IOSTANDARD LVCMOS33} [get_ports rf_tmgc_4 ] ;# ANT_TMGC_4_R
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set_property -dict {PACKAGE_PIN AG29 IOSTANDARD LVCMOS33} [get_ports rf_tmgc_2 ] ;# ANT_TMGC_2_R
|
||||
set_property -dict {PACKAGE_PIN AE27 IOSTANDARD LVCMOS33} [get_ports rf_tmgc_1 ] ;# ANT_TMGC_1_R
|
||||
set_property -dict {PACKAGE_PIN AG30 IOSTANDARD LVCMOS33} [get_ports rf_rmgc_16 ] ;# ANT_RMGC_16_R
|
||||
set_property -dict {PACKAGE_PIN AF28 IOSTANDARD LVCMOS33} [get_ports rf_rmgc_8 ] ;# ANT_RMGC_8_R
|
||||
set_property -dict {PACKAGE_PIN AG27 IOSTANDARD LVCMOS33} [get_ports rf_rmgc_4 ] ;# ANT_RMGC_4_R
|
||||
set_property -dict {PACKAGE_PIN AD28 IOSTANDARD LVCMOS33} [get_ports rf_rmgc_2 ] ;# ANT_RMGC_2_R
|
||||
set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVCMOS33} [get_ports rf_rmgc_1 ] ;# ANT_RMGC_1_R
|
||||
set_property -dict {PACKAGE_PIN AK27 IOSTANDARD LVCMOS33} [get_ports rf_enable ] ;# ANT_ENABLE_R
|
||||
set_property -dict {PACKAGE_PIN AH26 IOSTANDARD LVCMOS33} [get_ports rf_sc ] ;# ANT_SC_R
|
||||
set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVCMOS33} [get_ports rf_sd ] ;# ANT_SD_R
|
||||
set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVCMOS33} [get_ports rf_endsyn ] ;# ANT_END/SYN_R
|
||||
set_property -dict {PACKAGE_PIN AF25 IOSTANDARD LVCMOS33} [get_ports rf_sdout ] ;# ANT_SDOUT_R
|
||||
set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS33} [get_ports rf_dq_wd ] ;# ANT_DQ-WD_R 15
|
||||
set_property -dict {PACKAGE_PIN AJ29 IOSTANDARD LVCMOS33} [get_ports rf_sw_rx ] ;# ANT_SW_RX_R
|
||||
|
||||
# Debug IO
|
||||
set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports uart1_txd ] ;# UART1_TXD
|
||||
set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS33} [get_ports uart1_rxd ] ;# UART1_RXD
|
||||
set_property -dict {PACKAGE_PIN AC18 IOSTANDARD LVCMOS33} [get_ports uart2_txd ] ;# UART2_TXD
|
||||
set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS33} [get_ports uart2_rxd ] ;# UART2_RXD
|
||||
set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS33} [get_ports uart3_txd ] ;# UART3_TXD
|
||||
set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS33} [get_ports uart3_rxd ] ;# UART3_RXD
|
||||
set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18} [get_ports debug_io_1 ] ;# DEBUG_IO_1
|
||||
set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS18} [get_ports debug_io_2 ] ;# DEBUG_IO_2
|
||||
set_property -dict {PACKAGE_PIN AG16 IOSTANDARD LVCMOS33} [get_ports debug_io_3 ] ;# DEBUG_IO_3
|
||||
set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVCMOS33} [get_ports debug_io_4 ] ;# DEBUG_IO_4
|
||||
set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVCMOS33} [get_ports debug_io_5 ] ;# DEBUG_IO_5
|
||||
set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVCMOS33} [get_ports debug_io_6 ] ;# DEBUG_IO_6
|
||||
set_property -dict {PACKAGE_PIN AG17 IOSTANDARD LVCMOS33} [get_ports debug_io_7 ] ;# DEBUG_IO_7
|
||||
+1
@@ -0,0 +1 @@
|
||||
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets u_clk_dist/u_ad9361_2_clk_gen/inst/clk_in1_ad9361_clk_gen_cmos_2t2r]
|
||||
+301
@@ -0,0 +1,301 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_bd_auto_pc_0",
|
||||
"cell_name": "ps7_axi_periph/s00_couplers/auto_pc",
|
||||
"component_reference": "xilinx.com:ip:axi_protocol_converter:2.1",
|
||||
"ip_revision": "30",
|
||||
"gen_directory": "../../../../../../duifei_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_auto_pc_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"SI_PROTOCOL": [ { "value": "AXI3", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
|
||||
"MI_PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
|
||||
"TRANSLATION_MODE": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "12", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_bd_auto_pc_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_M_AXI_PROTOCOL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_PROTOCOL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_IGNORE_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_ID_WIDTH": [ { "value": "12", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_SUPPORTS_WRITE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_SUPPORTS_READ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_SUPPORTS_USER_SIGNALS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_AWUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_ARUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_WUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_RUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AXI_BUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_TRANSLATION_MODE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z100" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "30" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../duifei_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_auto_pc_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "rtl" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.2.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"aclk": [ { "direction": "in" } ],
|
||||
"aresetn": [ { "direction": "in" } ],
|
||||
"s_axi_awid": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0x000" } ],
|
||||
"s_axi_awaddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
|
||||
"s_axi_awlen": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x1" } ],
|
||||
"s_axi_awlock": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axi_awready": [ { "direction": "out" } ],
|
||||
"s_axi_wid": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0x000" } ],
|
||||
"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
|
||||
"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0xF" } ],
|
||||
"s_axi_wlast": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axi_wready": [ { "direction": "out" } ],
|
||||
"s_axi_bid": [ { "direction": "out", "size_left": "11", "size_right": "0" } ],
|
||||
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_bvalid": [ { "direction": "out" } ],
|
||||
"s_axi_bready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axi_arid": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0x000" } ],
|
||||
"s_axi_araddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
|
||||
"s_axi_arlen": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_arsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_arburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x1" } ],
|
||||
"s_axi_arlock": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_arcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_arqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"s_axi_arvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"s_axi_arready": [ { "direction": "out" } ],
|
||||
"s_axi_rid": [ { "direction": "out", "size_left": "11", "size_right": "0" } ],
|
||||
"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
|
||||
"s_axi_rlast": [ { "direction": "out" } ],
|
||||
"s_axi_rvalid": [ { "direction": "out" } ],
|
||||
"s_axi_rready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"m_axi_awaddr": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"m_axi_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"m_axi_awvalid": [ { "direction": "out" } ],
|
||||
"m_axi_awready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"m_axi_wdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"m_axi_wstrb": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
|
||||
"m_axi_wvalid": [ { "direction": "out" } ],
|
||||
"m_axi_wready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"m_axi_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"m_axi_bvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"m_axi_bready": [ { "direction": "out" } ],
|
||||
"m_axi_araddr": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
|
||||
"m_axi_arprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"m_axi_arvalid": [ { "direction": "out" } ],
|
||||
"m_axi_arready": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"m_axi_rdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ],
|
||||
"m_axi_rresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ],
|
||||
"m_axi_rvalid": [ { "direction": "in", "driver_value": "0x0" } ],
|
||||
"m_axi_rready": [ { "direction": "out" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"S_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI3", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "12", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "16", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "4", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "4", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWID": [ { "physical_name": "s_axi_awid" } ],
|
||||
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||
"AWLEN": [ { "physical_name": "s_axi_awlen" } ],
|
||||
"AWSIZE": [ { "physical_name": "s_axi_awsize" } ],
|
||||
"AWBURST": [ { "physical_name": "s_axi_awburst" } ],
|
||||
"AWLOCK": [ { "physical_name": "s_axi_awlock" } ],
|
||||
"AWCACHE": [ { "physical_name": "s_axi_awcache" } ],
|
||||
"AWPROT": [ { "physical_name": "s_axi_awprot" } ],
|
||||
"AWQOS": [ { "physical_name": "s_axi_awqos" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||
"WID": [ { "physical_name": "s_axi_wid" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||
"WLAST": [ { "physical_name": "s_axi_wlast" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||
"BID": [ { "physical_name": "s_axi_bid" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_bready" } ],
|
||||
"ARID": [ { "physical_name": "s_axi_arid" } ],
|
||||
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
|
||||
"ARLEN": [ { "physical_name": "s_axi_arlen" } ],
|
||||
"ARSIZE": [ { "physical_name": "s_axi_arsize" } ],
|
||||
"ARBURST": [ { "physical_name": "s_axi_arburst" } ],
|
||||
"ARLOCK": [ { "physical_name": "s_axi_arlock" } ],
|
||||
"ARCACHE": [ { "physical_name": "s_axi_arcache" } ],
|
||||
"ARPROT": [ { "physical_name": "s_axi_arprot" } ],
|
||||
"ARQOS": [ { "physical_name": "s_axi_arqos" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
|
||||
"RID": [ { "physical_name": "s_axi_rid" } ],
|
||||
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
|
||||
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
|
||||
"RLAST": [ { "physical_name": "s_axi_rlast" } ],
|
||||
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
|
||||
"RREADY": [ { "physical_name": "s_axi_rready" } ]
|
||||
}
|
||||
},
|
||||
"M_AXI": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "4", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "4", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "m_axi_awaddr" } ],
|
||||
"AWPROT": [ { "physical_name": "m_axi_awprot" } ],
|
||||
"AWVALID": [ { "physical_name": "m_axi_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "m_axi_awready" } ],
|
||||
"WDATA": [ { "physical_name": "m_axi_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "m_axi_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "m_axi_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "m_axi_wready" } ],
|
||||
"BRESP": [ { "physical_name": "m_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "m_axi_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "m_axi_bready" } ],
|
||||
"ARADDR": [ { "physical_name": "m_axi_araddr" } ],
|
||||
"ARPROT": [ { "physical_name": "m_axi_arprot" } ],
|
||||
"ARVALID": [ { "physical_name": "m_axi_arvalid" } ],
|
||||
"ARREADY": [ { "physical_name": "m_axi_arready" } ],
|
||||
"RDATA": [ { "physical_name": "m_axi_rdata" } ],
|
||||
"RRESP": [ { "physical_name": "m_axi_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "m_axi_rvalid" } ],
|
||||
"RREADY": [ { "physical_name": "m_axi_rready" } ]
|
||||
}
|
||||
},
|
||||
"CLK": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "S_AXI:M_AXI", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "ARESETN", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "aclk" } ]
|
||||
}
|
||||
},
|
||||
"RST": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TYPE": [ { "value": "INTERCONNECT", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aresetn" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+293
@@ -0,0 +1,293 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_bd_axi_spi_engine_0_0",
|
||||
"cell_name": "axi_spi_engine/axi_spi_engine",
|
||||
"component_reference": "analog.com:user:axi_spi_engine:1.0",
|
||||
"ip_revision": "1",
|
||||
"gen_directory": "../../../../../../duifei_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"CMD_FIFO_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SYNC_FIFO_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SDO_FIFO_ADDRESS_WIDTH": [ { "value": "5", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SDI_FIFO_ADDRESS_WIDTH": [ { "value": "5", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MM_IF_TYPE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ASYNC_SPI_CLK": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"NUM_OFFLOAD": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"OFFLOAD0_CMD_MEM_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"OFFLOAD0_SDO_MEM_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ID": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_OF_SDI": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CFG_INFO_0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CFG_INFO_1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CFG_INFO_2": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CFG_INFO_3": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_bd_axi_spi_engine_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"CMD_FIFO_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SYNC_FIFO_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SDO_FIFO_ADDRESS_WIDTH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SDI_FIFO_ADDRESS_WIDTH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"MM_IF_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"ASYNC_SPI_CLK": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"NUM_OFFLOAD": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"OFFLOAD0_CMD_MEM_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"OFFLOAD0_SDO_MEM_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"NUM_OF_SDI": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"CFG_INFO_0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"CFG_INFO_1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"CFG_INFO_2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"CFG_INFO_3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z100" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "1" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../duifei_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.2.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"s_axi_aclk": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_aresetn": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_awaddr": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_awready": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_wready": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"s_axi_bvalid": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_araddr": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_arready": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"s_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_rvalid": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"s_axi_rready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
|
||||
"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"irq": [ { "direction": "out" } ],
|
||||
"spi_clk": [ { "direction": "in" } ],
|
||||
"spi_resetn": [ { "direction": "out" } ],
|
||||
"cmd_ready": [ { "direction": "in" } ],
|
||||
"cmd_valid": [ { "direction": "out" } ],
|
||||
"cmd_data": [ { "direction": "out", "size_left": "15", "size_right": "0" } ],
|
||||
"sdo_data_ready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"sdo_data_valid": [ { "direction": "out" } ],
|
||||
"sdo_data": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||
"sdi_data_ready": [ { "direction": "out" } ],
|
||||
"sdi_data_valid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"sdi_data": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"sync_ready": [ { "direction": "out" } ],
|
||||
"sync_valid": [ { "direction": "in" } ],
|
||||
"sync_data": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"s_axi": {
|
||||
"vlnv": "xilinx.com:interface:aximm:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"memory_map_ref": "s_axi",
|
||||
"parameters": {
|
||||
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ADDR_WIDTH": [ { "value": "16", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_RRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_READ_THREADS": [ { "value": "4", "value_src": "constant_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"NUM_WRITE_THREADS": [ { "value": "4", "value_src": "constant_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
|
||||
"AWPROT": [ { "physical_name": "s_axi_awprot" } ],
|
||||
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
|
||||
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
|
||||
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
|
||||
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
|
||||
"WVALID": [ { "physical_name": "s_axi_wvalid" } ],
|
||||
"WREADY": [ { "physical_name": "s_axi_wready" } ],
|
||||
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
|
||||
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
|
||||
"BREADY": [ { "physical_name": "s_axi_bready" } ],
|
||||
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
|
||||
"ARPROT": [ { "physical_name": "s_axi_arprot" } ],
|
||||
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
|
||||
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
|
||||
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
|
||||
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
|
||||
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
|
||||
"RREADY": [ { "physical_name": "s_axi_rready" } ]
|
||||
}
|
||||
},
|
||||
"s_axi_aclk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "s_axi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axi_aclk" } ]
|
||||
}
|
||||
},
|
||||
"s_axi_aresetn": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axi_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"spi_engine_ctrl": {
|
||||
"vlnv": "analog.com:interface:spi_engine_ctrl:1.0",
|
||||
"abstraction_type": "analog.com:interface:spi_engine_ctrl_rtl:1.0",
|
||||
"mode": "master",
|
||||
"port_maps": {
|
||||
"CMD_READY": [ { "physical_name": "cmd_ready" } ],
|
||||
"CMD_VALID": [ { "physical_name": "cmd_valid" } ],
|
||||
"CMD_DATA": [ { "physical_name": "cmd_data" } ],
|
||||
"SDO_READY": [ { "physical_name": "sdo_data_ready" } ],
|
||||
"SDO_VALID": [ { "physical_name": "sdo_data_valid" } ],
|
||||
"SDO_DATA": [ { "physical_name": "sdo_data" } ],
|
||||
"SDI_READY": [ { "physical_name": "sdi_data_ready" } ],
|
||||
"SDI_VALID": [ { "physical_name": "sdi_data_valid" } ],
|
||||
"SDI_DATA": [ { "physical_name": "sdi_data" } ],
|
||||
"SYNC_READY": [ { "physical_name": "sync_ready" } ],
|
||||
"SYNC_VALID": [ { "physical_name": "sync_valid" } ],
|
||||
"SYNC_DATA": [ { "physical_name": "sync_data" } ]
|
||||
}
|
||||
},
|
||||
"spi_engine_ctrl_signal_clock": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "spi_engine_ctrl", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "spi_resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "spi_clk" } ]
|
||||
}
|
||||
},
|
||||
"spi_engine_ctrl_signal_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "spi_resetn" } ]
|
||||
}
|
||||
},
|
||||
"spi_engine_offload_ctrl0_s_axi_signal_clock": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "spi_engine_offload_ctrl0:s_axi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "s_axi_aclk" } ]
|
||||
}
|
||||
},
|
||||
"spi_engine_offload_ctrl0_s_axi_signal_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "s_axi_aresetn" } ]
|
||||
}
|
||||
}
|
||||
},
|
||||
"memory_maps": {
|
||||
"s_axi": {
|
||||
"address_blocks": {
|
||||
"axi_lite": {
|
||||
"base_address": "0",
|
||||
"range": "65536"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+1288
File diff suppressed because it is too large
Load Diff
+352
@@ -0,0 +1,352 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_bd_ps7_axi_periph_0",
|
||||
"cell_name": "ps7_axi_periph",
|
||||
"component_reference": "xilinx.com:ip:axi_interconnect:2.1",
|
||||
"ip_revision": "31",
|
||||
"gen_directory": "../../../../../../duifei_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_ps7_axi_periph_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"NUM_SI": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_MI": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"STRATEGY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ENABLE_ADVANCED_OPTIONS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ENABLE_PROTOCOL_CHECKERS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"XBAR_DATA_WIDTH": [ { "value": "32", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCHK_WAITS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCHK_MAX_RD_BURSTS": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PCHK_MAX_WR_BURSTS": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SYNCHRONIZATION_STAGES": [ { "value": "3", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M00_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M01_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M02_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M03_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M04_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M05_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M06_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M07_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M08_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M09_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M10_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M11_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M12_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M13_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M14_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M15_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M16_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M17_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M18_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M19_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M20_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M21_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M22_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M23_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M24_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M25_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M26_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M27_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M28_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M29_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M30_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M31_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M32_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M33_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M34_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M35_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M36_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M37_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M38_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M39_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M40_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M41_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M42_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M43_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M44_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M45_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M46_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M47_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M48_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M49_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M50_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M51_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M52_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M53_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M54_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M55_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M56_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M57_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M58_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M59_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M60_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M61_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M62_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M63_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M00_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M01_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M02_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M03_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M04_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M05_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M06_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M07_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M08_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M09_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M10_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M11_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M12_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M13_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M14_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M15_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M16_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M17_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M18_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M19_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M20_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M21_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M22_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M23_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M24_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M25_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M26_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M27_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M28_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M29_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M30_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M31_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M32_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M33_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M34_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M35_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M36_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M37_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M38_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M39_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M40_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M41_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M42_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M43_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M44_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M45_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M46_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M47_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M48_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M49_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M50_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M51_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M52_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M53_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M54_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M55_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"M56_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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||||
"S06_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S07_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S08_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S09_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S10_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S11_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S12_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S13_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S14_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"S15_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_bd_ps7_axi_periph_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z100" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator_AppCore" } ],
|
||||
"IPREVISION": [ { "value": "31" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../duifei_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_ps7_axi_periph_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.2.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+195
@@ -0,0 +1,195 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_bd_rst_ps7_100M_0",
|
||||
"cell_name": "rst_ps7_100M",
|
||||
"component_reference": "xilinx.com:ip:proc_sys_reset:5.0",
|
||||
"ip_revision": "14",
|
||||
"gen_directory": "../../../../../../duifei_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_rst_ps7_100M_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"C_NUM_PERP_ARESETN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_INTERCONNECT_ARESETN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_PERP_RST": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_BUS_RST": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_AUX_RESET_HIGH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_EXT_RESET_HIGH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_AUX_RST_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"C_EXT_RST_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_bd_rst_ps7_100M_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_EXT_RST_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AUX_RST_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_EXT_RESET_HIGH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_AUX_RESET_HIGH": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_BUS_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_PERP_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_INTERCONNECT_ARESETN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_PERP_ARESETN": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z100" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "14" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../duifei_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_rst_ps7_100M_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.2.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"slowest_sync_clk": [ { "direction": "in" } ],
|
||||
"ext_reset_in": [ { "direction": "in" } ],
|
||||
"aux_reset_in": [ { "direction": "in", "driver_value": "1" } ],
|
||||
"mb_debug_sys_rst": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"dcm_locked": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"mb_reset": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||
"bus_struct_reset": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"peripheral_reset": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"interconnect_aresetn": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "1" } ],
|
||||
"peripheral_aresetn": [ { "direction": "out", "size_left": "0", "size_right": "0", "driver_value": "1" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"clock": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_RESET": [ { "value": "mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "slowest_sync_clk" } ]
|
||||
}
|
||||
},
|
||||
"ext_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"BOARD.ASSOCIATED_PARAM": [ { "value": "RESET_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "ext_reset_in" } ]
|
||||
}
|
||||
},
|
||||
"aux_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "aux_reset_in" } ]
|
||||
}
|
||||
},
|
||||
"dbg_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "mb_debug_sys_rst" } ]
|
||||
}
|
||||
},
|
||||
"mb_rst": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"TYPE": [ { "value": "PROCESSOR", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "mb_reset" } ]
|
||||
}
|
||||
},
|
||||
"bus_struct_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"TYPE": [ { "value": "INTERCONNECT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "bus_struct_reset" } ]
|
||||
}
|
||||
},
|
||||
"interconnect_low_rst": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"TYPE": [ { "value": "INTERCONNECT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "interconnect_aresetn" } ]
|
||||
}
|
||||
},
|
||||
"peripheral_high_rst": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"TYPE": [ { "value": "PERIPHERAL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "peripheral_reset" } ]
|
||||
}
|
||||
},
|
||||
"peripheral_low_rst": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"TYPE": [ { "value": "PERIPHERAL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "peripheral_aresetn" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+175
@@ -0,0 +1,175 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_bd_spi_engine_execution_0_0",
|
||||
"cell_name": "axi_spi_engine/spi_engine_execution",
|
||||
"component_reference": "analog.com:user:spi_engine_execution:1.0",
|
||||
"ip_revision": "1",
|
||||
"gen_directory": "../../../../../../duifei_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"NUM_OF_CS": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DEFAULT_SPI_CFG": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DEFAULT_CLK_DIV": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"NUM_OF_SDI": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"SDO_DEFAULT": [ { "value": "\"0\"", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
|
||||
"ECHO_SCLK": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SDI_DELAY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "system_bd_spi_engine_execution_0_0", "resolve_type": "user", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"NUM_OF_CS": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DEFAULT_SPI_CFG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DEFAULT_CLK_DIV": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"NUM_OF_SDI": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"SDO_DEFAULT": [ { "value": "\"0\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
|
||||
"ECHO_SCLK": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"SDI_DELAY": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z100" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "1" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../duifei_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.2.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clk": [ { "direction": "in" } ],
|
||||
"resetn": [ { "direction": "in" } ],
|
||||
"active": [ { "direction": "out" } ],
|
||||
"cmd_ready": [ { "direction": "out" } ],
|
||||
"cmd_valid": [ { "direction": "in" } ],
|
||||
"cmd": [ { "direction": "in", "size_left": "15", "size_right": "0" } ],
|
||||
"sdo_data_valid": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"sdo_data_ready": [ { "direction": "out" } ],
|
||||
"sdo_data": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
|
||||
"sdi_data_ready": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"sdi_data_valid": [ { "direction": "out" } ],
|
||||
"sdi_data": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||
"sync_ready": [ { "direction": "in" } ],
|
||||
"sync_valid": [ { "direction": "out" } ],
|
||||
"sync": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
|
||||
"sclk": [ { "direction": "out" } ],
|
||||
"sdo": [ { "direction": "out" } ],
|
||||
"sdo_t": [ { "direction": "out" } ],
|
||||
"sdi": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"cs": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
|
||||
"three_wire": [ { "direction": "out" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"ctrl": {
|
||||
"vlnv": "analog.com:interface:spi_engine_ctrl:1.0",
|
||||
"abstraction_type": "analog.com:interface:spi_engine_ctrl_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"port_maps": {
|
||||
"CMD_READY": [ { "physical_name": "cmd_ready" } ],
|
||||
"CMD_VALID": [ { "physical_name": "cmd_valid" } ],
|
||||
"CMD_DATA": [ { "physical_name": "cmd" } ],
|
||||
"SDO_READY": [ { "physical_name": "sdo_data_ready" } ],
|
||||
"SDO_VALID": [ { "physical_name": "sdo_data_valid" } ],
|
||||
"SDO_DATA": [ { "physical_name": "sdo_data" } ],
|
||||
"SDI_READY": [ { "physical_name": "sdi_data_ready" } ],
|
||||
"SDI_VALID": [ { "physical_name": "sdi_data_valid" } ],
|
||||
"SDI_DATA": [ { "physical_name": "sdi_data" } ],
|
||||
"SYNC_READY": [ { "physical_name": "sync_ready" } ],
|
||||
"SYNC_VALID": [ { "physical_name": "sync_valid" } ],
|
||||
"SYNC_DATA": [ { "physical_name": "sync" } ]
|
||||
}
|
||||
},
|
||||
"ctrl_signal_clock": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "ctrl", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "clk" } ]
|
||||
}
|
||||
},
|
||||
"ctrl_signal_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "resetn" } ]
|
||||
}
|
||||
},
|
||||
"spi": {
|
||||
"vlnv": "analog.com:interface:spi_master:1.0",
|
||||
"abstraction_type": "analog.com:interface:spi_master_rtl:1.0",
|
||||
"mode": "master",
|
||||
"port_maps": {
|
||||
"SCLK": [ { "physical_name": "sclk" } ],
|
||||
"SDI": [ { "physical_name": "sdi" } ],
|
||||
"SDO": [ { "physical_name": "sdo" } ],
|
||||
"SDO_T": [ { "physical_name": "sdo_t" } ],
|
||||
"THREE_WIRE": [ { "physical_name": "three_wire" } ],
|
||||
"CS": [ { "physical_name": "cs" } ]
|
||||
}
|
||||
},
|
||||
"spi_signal_clock": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "spi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "clk" } ]
|
||||
}
|
||||
},
|
||||
"spi_signal_reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "resetn" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+306
@@ -0,0 +1,306 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "system_bd_xlconcat_0_0",
|
||||
"cell_name": "xlconcat_irq",
|
||||
"component_reference": "xilinx.com:ip:xlconcat:2.1",
|
||||
"ip_revision": "5",
|
||||
"gen_directory": "../../../../../../duifei_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_xlconcat_0_0",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "system_bd_xlconcat_0_0", "resolve_type": "user", "usage": "all" } ],
|
||||
"NUM_PORTS": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN0_WIDTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN1_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN2_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN3_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN4_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN5_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN6_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN7_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN8_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN9_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN10_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN11_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN12_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN13_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN14_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN15_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN16_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN17_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN18_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN19_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN20_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN21_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN22_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN23_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN24_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN25_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN26_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN27_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN28_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN29_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN30_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN31_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN32_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN33_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN34_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN35_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN36_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN37_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN38_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN39_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN40_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN41_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN42_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN43_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN44_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN45_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN46_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN47_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN48_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN49_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN50_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN51_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN52_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN53_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN54_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN55_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN56_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN57_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN58_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN59_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN60_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN61_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN62_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN63_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"IN64_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"IN100_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN101_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN102_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN103_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN104_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN105_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN106_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN107_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN108_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN109_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN110_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN111_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN112_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN113_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN114_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN115_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN116_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN117_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN118_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN119_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN120_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN121_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN122_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN123_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN124_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN125_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN126_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"IN127_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"dout_width": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"NUM_PORTS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z100" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
|
||||
"IPREVISION": [ { "value": "5" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../../../duifei_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_xlconcat_0_0" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "../../ipshared" } ],
|
||||
"SWVERSION": [ { "value": "2023.2.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"In0": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
|
||||
"dout": [ { "direction": "out", "size_left": "0", "size_right": "0" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+1087
File diff suppressed because it is too large
Load Diff
+226
@@ -0,0 +1,226 @@
|
||||
{
|
||||
"graphjs": {
|
||||
"version": "1.0",
|
||||
"keys": [
|
||||
{
|
||||
"abrv": "VH",
|
||||
"name": "vert_hid",
|
||||
"type": "int",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VM",
|
||||
"name": "vert_name",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "VT",
|
||||
"name": "vert_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BA",
|
||||
"name": "base_addr",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HA",
|
||||
"name": "high_addr",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BP",
|
||||
"name": "base_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "HP",
|
||||
"name": "high_param",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MA",
|
||||
"name": "master_addrspace",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MX",
|
||||
"name": "master_instance",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MI",
|
||||
"name": "master_interface",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MS",
|
||||
"name": "master_segment",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MV",
|
||||
"name": "master_vlnv",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SX",
|
||||
"name": "slave_instance",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SI",
|
||||
"name": "slave_interface",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "MM",
|
||||
"name": "slave_memmap",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SS",
|
||||
"name": "slave_segment",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "SV",
|
||||
"name": "slave_vlnv",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "TM",
|
||||
"name": "memory_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "TU",
|
||||
"name": "usage_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "LT",
|
||||
"name": "lock_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "BT",
|
||||
"name": "boot_type",
|
||||
"type": "string",
|
||||
"for": "node"
|
||||
},
|
||||
{
|
||||
"abrv": "EH",
|
||||
"name": "edge_hid",
|
||||
"type": "int",
|
||||
"for": "edge"
|
||||
}
|
||||
],
|
||||
"vertice_type_order": [
|
||||
{
|
||||
"abrv": "BC",
|
||||
"desc": "Block Container"
|
||||
},
|
||||
{
|
||||
"abrv": "PR",
|
||||
"desc": "Parital Reference"
|
||||
},
|
||||
{
|
||||
"abrv": "VR",
|
||||
"desc": "Variant"
|
||||
},
|
||||
{
|
||||
"abrv": "PM",
|
||||
"desc": "Variant Permutations"
|
||||
},
|
||||
{
|
||||
"abrv": "CX",
|
||||
"desc": "Boundary Connection"
|
||||
},
|
||||
{
|
||||
"abrv": "AC",
|
||||
"desc": "Assignment Coordinate"
|
||||
},
|
||||
{
|
||||
"abrv": "ACE",
|
||||
"desc": "Excluded Assign Coordinate"
|
||||
},
|
||||
{
|
||||
"abrv": "APX",
|
||||
"desc": "Boundary Aperture"
|
||||
},
|
||||
{
|
||||
"abrv": "CIP",
|
||||
"desc": "High level Processing System"
|
||||
}
|
||||
],
|
||||
"vertices": {
|
||||
"V0": {
|
||||
"VM": "system_bd",
|
||||
"VT": "BC"
|
||||
},
|
||||
"V1": {
|
||||
"VH": "2",
|
||||
"VM": "system_bd",
|
||||
"VT": "VR"
|
||||
},
|
||||
"V2": {
|
||||
"VH": "2",
|
||||
"VT": "PM",
|
||||
"TU": "active"
|
||||
},
|
||||
"V3": {
|
||||
"VT": "AC",
|
||||
"BA": "0x43C00000",
|
||||
"HA": "0x43C0FFFF",
|
||||
"BP": "C_BASEADDR",
|
||||
"HP": "C_HIGHADDR",
|
||||
"MA": "Data",
|
||||
"MX": "/processing_system7",
|
||||
"MI": "M_AXI_GP0",
|
||||
"MS": "SEG_axi_spi_engine_axi_lite",
|
||||
"MV": "xilinx.com:ip:processing_system7:5.5",
|
||||
"SX": "/axi_spi_engine/axi_spi_engine",
|
||||
"SI": "s_axi",
|
||||
"SS": "axi_lite",
|
||||
"SV": "analog.com:user:axi_spi_engine:1.0",
|
||||
"TM": "both",
|
||||
"TU": "register"
|
||||
}
|
||||
},
|
||||
"edges": [
|
||||
{
|
||||
"src": "V0",
|
||||
"trg": "V1"
|
||||
},
|
||||
{
|
||||
"src": "V1",
|
||||
"trg": "V2"
|
||||
},
|
||||
{
|
||||
"src": "V3",
|
||||
"trg": "V2",
|
||||
"EH": "2"
|
||||
}
|
||||
]
|
||||
}
|
||||
}
|
||||
+41
@@ -0,0 +1,41 @@
|
||||
{
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"1.0",
|
||||
"Default View_TopLeft":"-393,-47",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 TLS
|
||||
# -string -flagsOSRD
|
||||
preplace port DDR -pg 1 -lvl 3 -x 870 -y 180 -defaultsOSRD
|
||||
preplace port FIXED_IO -pg 1 -lvl 3 -x 870 -y 200 -defaultsOSRD
|
||||
preplace port spi -pg 1 -lvl 3 -x 870 -y 590 -defaultsOSRD
|
||||
preplace port port-id_spi_active -pg 1 -lvl 3 -x 870 -y 630 -defaultsOSRD
|
||||
preplace portBus GPIO_O -pg 1 -lvl 3 -x 870 -y 140 -defaultsOSRD
|
||||
preplace portBus GPIO_I -pg 1 -lvl 3 -x 870 -y 120 -defaultsOSRD -right
|
||||
preplace portBus GPIO_T -pg 1 -lvl 3 -x 870 -y 160 -defaultsOSRD
|
||||
preplace inst processing_system7 -pg 1 -lvl 1 -x 270 -y 180 -defaultsOSRD
|
||||
preplace inst axi_spi_engine -pg 1 -lvl 1 -x 270 -y 610 -defaultsOSRD
|
||||
preplace inst ps7_axi_periph -pg 1 -lvl 1 -x 270 -y 420 -defaultsOSRD
|
||||
preplace inst rst_ps7_100M -pg 1 -lvl 2 -x 670 -y 300 -defaultsOSRD
|
||||
preplace inst xlconcat_irq -pg 1 -lvl 2 -x 670 -y 530 -defaultsOSRD -orient R180
|
||||
preplace netloc GPIO_I_0_1 1 1 2 N 120 N
|
||||
preplace netloc axi_spi_engine_active 1 1 2 NJ 630 NJ
|
||||
preplace netloc axi_spi_engine_irq 1 1 2 N 610 840
|
||||
preplace netloc processing_system7_0_GPIO_O 1 1 2 N 140 N
|
||||
preplace netloc processing_system7_0_GPIO_T 1 1 2 N 160 N
|
||||
preplace netloc processing_system7_FCLK_CLK0 1 0 2 70 30 470
|
||||
preplace netloc processing_system7_FCLK_RESET0_N 1 1 1 460 260n
|
||||
preplace netloc rst_ps7_100M_peripheral_aresetn 1 0 3 50 20 NJ 20 840
|
||||
preplace netloc xlconcat_irq_dout 1 0 2 60 700 470
|
||||
preplace netloc axi_spi_engine_spi 1 1 2 NJ 590 NJ
|
||||
preplace netloc processing_system7_0_DDR 1 1 2 NJ 180 N
|
||||
preplace netloc processing_system7_0_FIXED_IO 1 1 2 NJ 200 N
|
||||
preplace netloc processing_system7_M_AXI_GP0 1 0 2 80 40 460J
|
||||
preplace netloc ps7_axi_periph_M00_AXI 1 0 2 80 690 460J
|
||||
levelinfo -pg 1 0 270 670 870
|
||||
pagesize -pg 1 -db -bbox -sgen 0 0 1020 710
|
||||
"
|
||||
}
|
||||
{
|
||||
"da_axi4_cnt":"1",
|
||||
"da_ps7_cnt":"1"
|
||||
}
|
||||
+30
@@ -0,0 +1,30 @@
|
||||
{
|
||||
"ActiveEmotionalView":"Default View",
|
||||
"Default View_ScaleFactor":"1.0",
|
||||
"Default View_TopLeft":"-778,-240",
|
||||
"ExpandedHierarchyInLayout":"",
|
||||
"guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 TLS
|
||||
# -string -flagsOSRD
|
||||
preplace port s_axi -pg 1 -lvl 0 -x 0 -y 70 -defaultsOSRD
|
||||
preplace port spi -pg 1 -lvl 2 -x 340 -y 230 -defaultsOSRD
|
||||
preplace port port-id_irq -pg 1 -lvl 2 -x 340 -y 100 -defaultsOSRD
|
||||
preplace port port-id_s_axi_aclk -pg 1 -lvl 0 -x 0 -y 90 -defaultsOSRD
|
||||
preplace port port-id_s_axi_aresetn -pg 1 -lvl 0 -x 0 -y 110 -defaultsOSRD
|
||||
preplace port port-id_spi_clk -pg 1 -lvl 0 -x 0 -y 130 -defaultsOSRD
|
||||
preplace port port-id_active -pg 1 -lvl 2 -x 340 -y 250 -defaultsOSRD
|
||||
preplace inst axi_spi_engine -pg 1 -lvl 1 -x 180 -y 90 -defaultsOSRD
|
||||
preplace inst spi_engine_execution -pg 1 -lvl 1 -x 180 -y 240 -defaultsOSRD
|
||||
preplace netloc axi_spi_engine_spi_resetn 1 0 2 40 320 320
|
||||
preplace netloc axi_spi_engine_irq 1 1 1 320J 90n
|
||||
preplace netloc s_axi_aclk_0_1 1 0 1 20 80n
|
||||
preplace netloc spi_clk_0_1 1 0 1 30 120n
|
||||
preplace netloc spi_engine_execution_active 1 1 1 N 250
|
||||
preplace netloc s_axi_aresetn_1 1 0 1 20 100n
|
||||
preplace netloc axi_spi_engine_spi_engine_ctrl 1 0 2 40 0 320
|
||||
preplace netloc Conn1 1 0 1 20 60n
|
||||
preplace netloc Conn2 1 1 1 N 230
|
||||
levelinfo -pg 1 0 180 340
|
||||
pagesize -pg 1 -db -bbox -sgen -150 -10 440 350
|
||||
"
|
||||
}
|
||||
|
||||
+713
@@ -0,0 +1,713 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "ad9361_clk_gen_cmos_2t2r",
|
||||
"component_reference": "xilinx.com:ip:clk_wiz:6.0",
|
||||
"ip_revision": "13",
|
||||
"gen_directory": "../../../../duifei_cal_coarse.gen/sources_1/ip/ad9361_clk_gen_cmos_2t2r",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "ad9361_clk_gen_cmos_2t2r", "resolve_type": "user", "usage": "all" } ],
|
||||
"USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"ENABLE_CLOCK_MONITOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_USER_CLOCK0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_USER_CLOCK1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_USER_CLOCK2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_USER_CLOCK3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Enable_PLL0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Enable_PLL1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
|
||||
"PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_PHASE_ALIGNMENT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ],
|
||||
"PRIM_IN_FREQ": [ { "value": "96", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ],
|
||||
"PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "user", "usage": "all" } ],
|
||||
"IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ],
|
||||
"RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_INCLK_SWITCHOVER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ],
|
||||
"SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
|
||||
"JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKIN1_JITTER_PS": [ { "value": "104.16", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT2_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT3_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT4_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"NUM_OUT_CLKS": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ],
|
||||
"DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ],
|
||||
"DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ],
|
||||
"DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ],
|
||||
"DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ],
|
||||
"DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ],
|
||||
"DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ],
|
||||
"DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ],
|
||||
"PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ],
|
||||
"PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ],
|
||||
"PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ],
|
||||
"PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "48", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "96", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "144", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "192", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ],
|
||||
"PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ],
|
||||
"SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_RESET": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ],
|
||||
"LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ],
|
||||
"POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ],
|
||||
"STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ],
|
||||
"INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ],
|
||||
"SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ],
|
||||
"SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
|
||||
"MMCM_DIVCLK_DIVIDE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
|
||||
"MMCM_CLKFBOUT_MULT_F": [ { "value": "12.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKIN1_PERIOD": [ { "value": "10.417", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKIN2_PERIOD": [ { "value": "10.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "user", "usage": "all" } ],
|
||||
"MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_DIVIDE_F": [ { "value": "24.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT1_DIVIDE": [ { "value": "12", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT2_DIVIDE": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT3_DIVIDE": [ { "value": "6", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
|
||||
"PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
|
||||
"PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ],
|
||||
"PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKIN_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ],
|
||||
"PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"RESET_TYPE": [ { "value": "ACTIVE_HIGH", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_SAFE_CLOCK_STARTUP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_CLOCK_SEQUENCING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"DIFF_CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"DIFF_CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
|
||||
"RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"ENABLE_CDDC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "user", "usage": "all" } ],
|
||||
"CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ],
|
||||
"ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_JITTER": [ { "value": "139.139", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_PHASE_ERROR": [ { "value": "89.958", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_JITTER": [ { "value": "120.859", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_PHASE_ERROR": [ { "value": "89.958", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT3_JITTER": [ { "value": "112.241", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT3_PHASE_ERROR": [ { "value": "89.958", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT4_JITTER": [ { "value": "106.524", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT4_PHASE_ERROR": [ { "value": "89.958", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT5_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT5_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT6_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT6_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT7_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT7_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"INPUT_MODE": [ { "value": "frequency", "resolve_type": "user", "usage": "all" } ],
|
||||
"INTERFACE_SELECTION": [ { "value": "Enable_AXI", "resolve_type": "user", "usage": "all" } ],
|
||||
"AXI_DRP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"PHASE_DUTY_CONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_CLKOUT2_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_ENABLE_CLOCK_MONITOR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_USER_CLOCK0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_USER_CLOCK1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_USER_CLOCK2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_USER_CLOCK3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_Enable_PLL0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_Enable_PLL1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PRECISION": [ { "value": "1", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT4_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT5_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT6_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT7_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLKOUT1_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLKOUT2_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLKOUT3_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLKOUT4_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"c_component_name": [ { "value": "ad9361_clk_gen_cmos_2t2r", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_FREQ_SYNTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_PHASE_ALIGNMENT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_MIN_POWER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_MIN_O_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_MAX_I_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_DYN_PHASE_SHIFT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_INCLK_SWITCHOVER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_DYN_RECONFIG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_SPREAD_SPECTRUM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_FAST_SIMULATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIMTYPE_SEL": [ { "value": "AUTO", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_CLK_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIM_IN_FREQ": [ { "value": "96", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_RESET": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RESET_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_LOCKED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_INCLK_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLKFB_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_POWER_DOWN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_STATUS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_FREEZE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_OUT_CLKS": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INCLK_SUM_ROW0": [ { "value": "Input Clock Freq (MHz) Input Jitter (UI)", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INCLK_SUM_ROW1": [ { "value": "__primary______________96____________0.010", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INCLK_SUM_ROW2": [ { "value": "no_secondary_input_clock ", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW0A": [ { "value": " Output Output Phase Duty Cycle Pk-to-Pk Phase", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW0B": [ { "value": " Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__48.00000______0.000______50.0______139.139_____89.958", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW2": [ { "value": "clk_out2__96.00000______0.000______50.0______120.859_____89.958", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW3": [ { "value": "clk_out3__144.00000______0.000______50.0______112.241_____89.958", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW4": [ { "value": "clk_out4__192.00000______0.000______50.0______106.524_____89.958", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW6": [ { "value": "no_CLK_OUT6_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW7": [ { "value": "no_CLK_OUT7_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "48", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "96", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "144", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "192", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_OUT_FREQ": [ { "value": "48.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_OUT_FREQ": [ { "value": "96.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_OUT_FREQ": [ { "value": "144.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_OUT_FREQ": [ { "value": "192.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_USE_SAFE_CLOCK_STARTUP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLOCK_SEQUENCING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_NOTES": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKFBOUT_MULT_F": [ { "value": "12.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKIN1_PERIOD": [ { "value": "10.417", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKIN2_PERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT4_CASCADE": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"C_MMCM_CLOCK_HOLD": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"C_MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "24.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT1_DIVIDE": [ { "value": "12", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT2_DIVIDE": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT3_DIVIDE": [ { "value": "6", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLL_NOTES": [ { "value": "No notes", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLL_CLKFBOUT_MULT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKIN_PERIOD": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLOCK_MGR_TYPE": [ { "value": "NA", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OVERRIDE_MMCM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OVERRIDE_PLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_RESET_PORT": [ { "value": "reset", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_LOCKED_PORT": [ { "value": "locked", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DADDR_PORT": [ { "value": "daddr", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DCLK_PORT": [ { "value": "dclk", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DRDY_PORT": [ { "value": "drdy", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DWE_PORT": [ { "value": "dwe", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIN_PORT": [ { "value": "din", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DOUT_PORT": [ { "value": "dout", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DEN_PORT": [ { "value": "den", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PSCLK_PORT": [ { "value": "psclk", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PSEN_PORT": [ { "value": "psen", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PSDONE_PORT": [ { "value": "psdone", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_STATUS_PORT": [ { "value": "STATUS", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKIN1_JITTER_PS": [ { "value": "104.16", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SS_MOD_PERIOD": [ { "value": "4000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_HAS_CDDC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUTPHY_MODE": [ { "value": "VCO", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_ENABLE_CLKOUTPHY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INTERFACE_SELECTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_ADDR_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_POWER_REG": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT0_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT0_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT2_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT2_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT3_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT3_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT4_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT4_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT5_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT5_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT6_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT6_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFBOUT_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFBOUT_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVCLK": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_LOCK_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_LOCK_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_LOCK_3": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_FILTER_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE2_AUTO": [ { "value": "0.5", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE3_AUTO": [ { "value": "0.3333333333333333", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE4_AUTO": [ { "value": "0.25", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE5_AUTO": [ { "value": "0.041666666666666664", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE6_AUTO": [ { "value": "0.041666666666666664", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE7_AUTO": [ { "value": "0.041666666666666664", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV5": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV6": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV7": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT0_ACTUAL_FREQ": [ { "value": "48.00000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_ACTUAL_FREQ": [ { "value": "96.00000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT2_ACTUAL_FREQ": [ { "value": "144.00000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT3_ACTUAL_FREQ": [ { "value": "192.00000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT4_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT5_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT6_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_M_MAX": [ { "value": "64.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_M_MIN": [ { "value": "2.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_D_MAX": [ { "value": "93.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_D_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_O_MAX": [ { "value": "128.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_O_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_VCO_MIN": [ { "value": "600.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_VCO_MAX": [ { "value": "1440.000", "resolve_type": "generated", "format": "float", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z100" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "13" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../duifei_cal_coarse.gen/sources_1/ip/ad9361_clk_gen_cmos_2t2r" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clk_in1": [ { "direction": "in" } ],
|
||||
"clk_out1": [ { "direction": "out" } ],
|
||||
"clk_out2": [ { "direction": "out" } ],
|
||||
"clk_out3": [ { "direction": "out" } ],
|
||||
"clk_out4": [ { "direction": "out" } ],
|
||||
"locked": [ { "direction": "out" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"clock_CLK_IN1": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BOARD.ASSOCIATED_PARAM": [ { "value": "CLK_IN1_BOARD_INTERFACE", "usage": "all", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK_IN1": [ { "physical_name": "clk_in1" } ]
|
||||
}
|
||||
},
|
||||
"clock_CLK_OUT1": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK_OUT1": [ { "physical_name": "clk_out1" } ]
|
||||
}
|
||||
},
|
||||
"clock_CLK_OUT2": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK_OUT2": [ { "physical_name": "clk_out2" } ]
|
||||
}
|
||||
},
|
||||
"clock_CLK_OUT3": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK_OUT3": [ { "physical_name": "clk_out3" } ]
|
||||
}
|
||||
},
|
||||
"clock_CLK_OUT4": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK_OUT4": [ { "physical_name": "clk_out4" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+652
@@ -0,0 +1,652 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "ant_clk_gen_stg1",
|
||||
"component_reference": "xilinx.com:ip:clk_wiz:6.0",
|
||||
"ip_revision": "13",
|
||||
"gen_directory": "../../../../duifei_cal_coarse.gen/sources_1/ip/ant_clk_gen_stg1",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "ant_clk_gen_stg1", "resolve_type": "user", "usage": "all" } ],
|
||||
"USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"ENABLE_CLOCK_MONITOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_USER_CLOCK0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_USER_CLOCK1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_USER_CLOCK2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_USER_CLOCK3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Enable_PLL0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Enable_PLL1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
|
||||
"PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_PHASE_ALIGNMENT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ],
|
||||
"PRIM_IN_FREQ": [ { "value": "250", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ],
|
||||
"PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "user", "usage": "all" } ],
|
||||
"IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ],
|
||||
"RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_INCLK_SWITCHOVER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ],
|
||||
"SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
|
||||
"JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKIN1_JITTER_PS": [ { "value": "40.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT2_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT3_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT4_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"NUM_OUT_CLKS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ],
|
||||
"DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ],
|
||||
"DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ],
|
||||
"DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ],
|
||||
"DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ],
|
||||
"DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ],
|
||||
"DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ],
|
||||
"DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ],
|
||||
"PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ],
|
||||
"PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ],
|
||||
"PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ],
|
||||
"PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "96", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"PRIM_SOURCE": [ { "value": "Differential_clock_capable_pin", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ],
|
||||
"PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ],
|
||||
"SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_RESET": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ],
|
||||
"LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ],
|
||||
"POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ],
|
||||
"STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ],
|
||||
"INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ],
|
||||
"SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ],
|
||||
"SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
|
||||
"MMCM_DIVCLK_DIVIDE": [ { "value": "5", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
|
||||
"MMCM_CLKFBOUT_MULT_F": [ { "value": "18.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKIN1_PERIOD": [ { "value": "4.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "user", "usage": "all" } ],
|
||||
"MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_DIVIDE_F": [ { "value": "9.375", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
|
||||
"PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
|
||||
"PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ],
|
||||
"PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKIN_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ],
|
||||
"PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"RESET_TYPE": [ { "value": "ACTIVE_HIGH", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_SAFE_CLOCK_STARTUP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_CLOCK_SEQUENCING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"DIFF_CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"DIFF_CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
|
||||
"RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"ENABLE_CDDC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "user", "usage": "all" } ],
|
||||
"CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ],
|
||||
"ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_JITTER": [ { "value": "168.397", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_PHASE_ERROR": [ { "value": "161.614", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT3_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT3_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT4_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT4_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT5_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT5_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT6_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT6_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT7_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT7_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"INPUT_MODE": [ { "value": "frequency", "resolve_type": "user", "usage": "all" } ],
|
||||
"INTERFACE_SELECTION": [ { "value": "Enable_AXI", "resolve_type": "user", "usage": "all" } ],
|
||||
"AXI_DRP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"PHASE_DUTY_CONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_CLKOUT2_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_ENABLE_CLOCK_MONITOR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_USER_CLOCK0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_USER_CLOCK1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_USER_CLOCK2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_USER_CLOCK3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_Enable_PLL0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_Enable_PLL1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PRECISION": [ { "value": "1", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT4_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT5_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT6_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT7_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLKOUT1_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLKOUT2_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLKOUT3_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLKOUT4_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"c_component_name": [ { "value": "ant_clk_gen_stg1", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_FREQ_SYNTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_PHASE_ALIGNMENT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_MIN_POWER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_MIN_O_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_MAX_I_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_DYN_PHASE_SHIFT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_INCLK_SWITCHOVER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_DYN_RECONFIG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_SPREAD_SPECTRUM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_FAST_SIMULATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIMTYPE_SEL": [ { "value": "AUTO", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_CLK_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIM_IN_FREQ": [ { "value": "250", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PRIM_SOURCE": [ { "value": "Differential_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_RESET": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RESET_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_LOCKED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_INCLK_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLKFB_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_POWER_DOWN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_STATUS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_FREEZE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_OUT_CLKS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INCLK_SUM_ROW0": [ { "value": "Input Clock Freq (MHz) Input Jitter (UI)", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INCLK_SUM_ROW1": [ { "value": "__primary_____________250____________0.010", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INCLK_SUM_ROW2": [ { "value": "no_secondary_input_clock ", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW0A": [ { "value": " Output Output Phase Duty Cycle Pk-to-Pk Phase", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW0B": [ { "value": " Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__96.00000______0.000______50.0______168.397____161.614", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW2": [ { "value": "no_CLK_OUT2_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW3": [ { "value": "no_CLK_OUT3_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW4": [ { "value": "no_CLK_OUT4_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW6": [ { "value": "no_CLK_OUT6_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW7": [ { "value": "no_CLK_OUT7_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "96", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_OUT_FREQ": [ { "value": "96.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_USE_SAFE_CLOCK_STARTUP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLOCK_SEQUENCING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_NOTES": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKFBOUT_MULT_F": [ { "value": "18.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKIN1_PERIOD": [ { "value": "4.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT4_CASCADE": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"C_MMCM_CLOCK_HOLD": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"C_MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_DIVCLK_DIVIDE": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "9.375", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLL_NOTES": [ { "value": "No notes", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLL_CLKFBOUT_MULT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKIN_PERIOD": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLOCK_MGR_TYPE": [ { "value": "NA", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OVERRIDE_MMCM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OVERRIDE_PLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_RESET_PORT": [ { "value": "reset", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_LOCKED_PORT": [ { "value": "locked", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DADDR_PORT": [ { "value": "daddr", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DCLK_PORT": [ { "value": "dclk", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DRDY_PORT": [ { "value": "drdy", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DWE_PORT": [ { "value": "dwe", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIN_PORT": [ { "value": "din", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DOUT_PORT": [ { "value": "dout", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DEN_PORT": [ { "value": "den", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PSCLK_PORT": [ { "value": "psclk", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PSEN_PORT": [ { "value": "psen", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PSDONE_PORT": [ { "value": "psdone", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_STATUS_PORT": [ { "value": "STATUS", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKIN1_JITTER_PS": [ { "value": "40.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SS_MOD_PERIOD": [ { "value": "4000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_HAS_CDDC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUTPHY_MODE": [ { "value": "VCO", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_ENABLE_CLKOUTPHY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INTERFACE_SELECTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_ADDR_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_POWER_REG": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT0_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT0_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT2_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT2_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT3_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT3_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT4_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT4_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT5_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT5_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT6_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT6_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFBOUT_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFBOUT_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVCLK": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_LOCK_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_LOCK_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_LOCK_3": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_FILTER_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE2_AUTO": [ { "value": "0.10666666666666667", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE3_AUTO": [ { "value": "0.10666666666666667", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE4_AUTO": [ { "value": "0.10666666666666667", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE5_AUTO": [ { "value": "0.10666666666666667", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE6_AUTO": [ { "value": "0.10666666666666667", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE7_AUTO": [ { "value": "0.10666666666666667", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV5": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV6": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV7": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT0_ACTUAL_FREQ": [ { "value": "96.00000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT2_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT3_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT4_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT5_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT6_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_M_MAX": [ { "value": "64.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_M_MIN": [ { "value": "2.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_D_MAX": [ { "value": "93.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_D_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_O_MAX": [ { "value": "128.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_O_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_VCO_MIN": [ { "value": "600.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_VCO_MAX": [ { "value": "1440.000", "resolve_type": "generated", "format": "float", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z100" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "13" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../duifei_cal_coarse.gen/sources_1/ip/ant_clk_gen_stg1" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clk_in1_p": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"clk_in1_n": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"clk_out1": [ { "direction": "out" } ],
|
||||
"locked": [ { "direction": "out" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"CLK_IN1_D": {
|
||||
"vlnv": "xilinx.com:interface:diff_clock:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:diff_clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"BOARD.ASSOCIATED_PARAM": [ { "value": "CLK_IN1_BOARD_INTERFACE", "value_src": "constant", "usage": "all" } ],
|
||||
"CAN_DEBUG": [ { "value": "false", "resolve_type": "generated", "format": "bool", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK_N": [ { "physical_name": "clk_in1_n" } ],
|
||||
"CLK_P": [ { "physical_name": "clk_in1_p" } ]
|
||||
}
|
||||
},
|
||||
"clock_CLK_OUT1": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK_OUT1": [ { "physical_name": "clk_out1" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+713
@@ -0,0 +1,713 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "ant_clk_gen_stg2",
|
||||
"component_reference": "xilinx.com:ip:clk_wiz:6.0",
|
||||
"ip_revision": "13",
|
||||
"gen_directory": "../../../../duifei_cal_coarse.gen/sources_1/ip/ant_clk_gen_stg2",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "ant_clk_gen_stg2", "resolve_type": "user", "usage": "all" } ],
|
||||
"USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"ENABLE_CLOCK_MONITOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_USER_CLOCK0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_USER_CLOCK1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_USER_CLOCK2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"ENABLE_USER_CLOCK3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Enable_PLL0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Enable_PLL1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
|
||||
"PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_PHASE_ALIGNMENT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ],
|
||||
"PRIM_IN_FREQ": [ { "value": "96", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ],
|
||||
"PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "user", "usage": "all" } ],
|
||||
"IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ],
|
||||
"RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_INCLK_SWITCHOVER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ],
|
||||
"SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
|
||||
"JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKIN1_JITTER_PS": [ { "value": "104.16", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT2_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT3_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT4_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"NUM_OUT_CLKS": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ],
|
||||
"DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ],
|
||||
"DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ],
|
||||
"DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ],
|
||||
"DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ],
|
||||
"DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ],
|
||||
"DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ],
|
||||
"DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ],
|
||||
"PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ],
|
||||
"PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ],
|
||||
"PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ],
|
||||
"PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "96", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "48", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "19.2", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"PRIM_SOURCE": [ { "value": "Global_buffer", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
|
||||
"FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ],
|
||||
"PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ],
|
||||
"SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_RESET": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ],
|
||||
"LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ],
|
||||
"POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ],
|
||||
"STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ],
|
||||
"INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ],
|
||||
"SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ],
|
||||
"SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
|
||||
"MMCM_DIVCLK_DIVIDE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
|
||||
"MMCM_CLKFBOUT_MULT_F": [ { "value": "10.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKIN1_PERIOD": [ { "value": "10.417", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKIN2_PERIOD": [ { "value": "10.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "user", "usage": "all" } ],
|
||||
"MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_DIVIDE_F": [ { "value": "10.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT1_DIVIDE": [ { "value": "20", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT2_DIVIDE": [ { "value": "30", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT3_DIVIDE": [ { "value": "50", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
|
||||
"PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
|
||||
"PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ],
|
||||
"PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKIN_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ],
|
||||
"PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"RESET_TYPE": [ { "value": "ACTIVE_HIGH", "resolve_type": "user", "usage": "all" } ],
|
||||
"USE_SAFE_CLOCK_STARTUP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"USE_CLOCK_SEQUENCING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"DIFF_CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"DIFF_CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
|
||||
"RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||
"ENABLE_CDDC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "user", "usage": "all" } ],
|
||||
"CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ],
|
||||
"ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_JITTER": [ { "value": "136.435", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT1_PHASE_ERROR": [ { "value": "101.715", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_JITTER": [ { "value": "158.351", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT2_PHASE_ERROR": [ { "value": "101.715", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT3_JITTER": [ { "value": "172.426", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT3_PHASE_ERROR": [ { "value": "101.715", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT4_JITTER": [ { "value": "190.665", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT4_PHASE_ERROR": [ { "value": "101.715", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT5_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT5_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT6_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT6_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT7_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"CLKOUT7_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||
"INPUT_MODE": [ { "value": "frequency", "resolve_type": "user", "usage": "all" } ],
|
||||
"INTERFACE_SELECTION": [ { "value": "Enable_AXI", "resolve_type": "user", "usage": "all" } ],
|
||||
"AXI_DRP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"PHASE_DUTY_CONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_CLKOUT2_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_ENABLE_CLOCK_MONITOR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_USER_CLOCK0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_USER_CLOCK1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_USER_CLOCK2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_USER_CLOCK3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_Enable_PLL0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_Enable_PLL1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PRECISION": [ { "value": "1", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT4_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT5_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT6_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT7_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLKOUT1_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLKOUT2_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLKOUT3_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLKOUT4_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"c_component_name": [ { "value": "ant_clk_gen_stg2", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_FREQ_SYNTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_PHASE_ALIGNMENT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_MIN_POWER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_MIN_O_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_MAX_I_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_DYN_PHASE_SHIFT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_INCLK_SWITCHOVER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_DYN_RECONFIG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_SPREAD_SPECTRUM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_FAST_SIMULATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIMTYPE_SEL": [ { "value": "AUTO", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_CLK_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIM_IN_FREQ": [ { "value": "96", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PRIM_SOURCE": [ { "value": "Global_buffer", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_USE_RESET": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RESET_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_LOCKED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_INCLK_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLKFB_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_POWER_DOWN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_STATUS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_FREEZE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_NUM_OUT_CLKS": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INCLK_SUM_ROW0": [ { "value": "Input Clock Freq (MHz) Input Jitter (UI)", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INCLK_SUM_ROW1": [ { "value": "__primary______________96____________0.010", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INCLK_SUM_ROW2": [ { "value": "no_secondary_input_clock ", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW0A": [ { "value": " Output Output Phase Duty Cycle Pk-to-Pk Phase", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW0B": [ { "value": " Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__96.00000______0.000______50.0______136.435____101.715", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW2": [ { "value": "clk_out2__48.00000______0.000______50.0______158.351____101.715", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW3": [ { "value": "clk_out3__32.00000______0.000______50.0______172.426____101.715", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW4": [ { "value": "clk_out4__19.20000______0.000______50.0______190.665____101.715", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW6": [ { "value": "no_CLK_OUT6_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OUTCLK_SUM_ROW7": [ { "value": "no_CLK_OUT7_output", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "96", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "48", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "32", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "19.2", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_OUT_FREQ": [ { "value": "96.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_OUT_FREQ": [ { "value": "48.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_OUT_FREQ": [ { "value": "32.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_OUT_FREQ": [ { "value": "19.20000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT1_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT2_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT3_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT4_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT5_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT6_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKOUT7_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_USE_SAFE_CLOCK_STARTUP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_CLOCK_SEQUENCING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_NOTES": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKFBOUT_MULT_F": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKIN1_PERIOD": [ { "value": "10.417", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKIN2_PERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT4_CASCADE": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"C_MMCM_CLOCK_HOLD": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||
"C_MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT1_DIVIDE": [ { "value": "20", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT2_DIVIDE": [ { "value": "30", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT3_DIVIDE": [ { "value": "50", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLL_NOTES": [ { "value": "No notes", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLL_CLKFBOUT_MULT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKIN_PERIOD": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLOCK_MGR_TYPE": [ { "value": "NA", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OVERRIDE_MMCM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OVERRIDE_PLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_RESET_PORT": [ { "value": "reset", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_LOCKED_PORT": [ { "value": "locked", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DADDR_PORT": [ { "value": "daddr", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DCLK_PORT": [ { "value": "dclk", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DRDY_PORT": [ { "value": "drdy", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DWE_PORT": [ { "value": "dwe", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIN_PORT": [ { "value": "din", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DOUT_PORT": [ { "value": "dout", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DEN_PORT": [ { "value": "den", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PSCLK_PORT": [ { "value": "psclk", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PSEN_PORT": [ { "value": "psen", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PSDONE_PORT": [ { "value": "psdone", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_STATUS_PORT": [ { "value": "STATUS", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKIN1_JITTER_PS": [ { "value": "104.16", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_SS_MOD_PERIOD": [ { "value": "4000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_HAS_CDDC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUTPHY_MODE": [ { "value": "VCO", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_ENABLE_CLKOUTPHY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INTERFACE_SELECTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_ADDR_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_POWER_REG": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT0_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT0_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT2_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT2_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT3_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT3_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT4_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT4_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT5_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT5_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT6_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT6_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFBOUT_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKFBOUT_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVCLK": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_LOCK_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_LOCK_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_LOCK_3": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_FILTER_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE2_AUTO": [ { "value": "2.0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE3_AUTO": [ { "value": "3.0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE4_AUTO": [ { "value": "5.0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE5_AUTO": [ { "value": "0.1", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE6_AUTO": [ { "value": "0.1", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIVIDE7_AUTO": [ { "value": "0.1", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PLLBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV5": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV6": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_MMCMBUFGCEDIV7": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT0_ACTUAL_FREQ": [ { "value": "96.00000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT1_ACTUAL_FREQ": [ { "value": "48.00000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT2_ACTUAL_FREQ": [ { "value": "32.00000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT3_ACTUAL_FREQ": [ { "value": "19.20000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT4_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT5_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_CLKOUT6_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_M_MAX": [ { "value": "64.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_M_MIN": [ { "value": "2.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_D_MAX": [ { "value": "93.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_D_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_O_MAX": [ { "value": "128.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_O_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_VCO_MIN": [ { "value": "600.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||
"C_VCO_MAX": [ { "value": "1440.000", "resolve_type": "generated", "format": "float", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "zynq" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7z100" } ],
|
||||
"PACKAGE": [ { "value": "ffg900" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "13" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "../../../../duifei_cal_coarse.gen/sources_1/ip/ant_clk_gen_stg2" } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2023.2.1" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clk_in1": [ { "direction": "in" } ],
|
||||
"clk_out1": [ { "direction": "out" } ],
|
||||
"clk_out2": [ { "direction": "out" } ],
|
||||
"clk_out3": [ { "direction": "out" } ],
|
||||
"clk_out4": [ { "direction": "out" } ],
|
||||
"locked": [ { "direction": "out" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"clock_CLK_IN1": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BOARD.ASSOCIATED_PARAM": [ { "value": "CLK_IN1_BOARD_INTERFACE", "usage": "all", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK_IN1": [ { "physical_name": "clk_in1" } ]
|
||||
}
|
||||
},
|
||||
"clock_CLK_OUT1": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK_OUT1": [ { "physical_name": "clk_out1" } ]
|
||||
}
|
||||
},
|
||||
"clock_CLK_OUT2": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK_OUT2": [ { "physical_name": "clk_out2" } ]
|
||||
}
|
||||
},
|
||||
"clock_CLK_OUT3": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK_OUT3": [ { "physical_name": "clk_out3" } ]
|
||||
}
|
||||
},
|
||||
"clock_CLK_OUT4": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK_OUT4": [ { "physical_name": "clk_out4" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+479
@@ -0,0 +1,479 @@
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "fifo_AntCtrl",
|
||||
"component_reference": "xilinx.com:ip:fifo_generator:13.2",
|
||||
"ip_revision": "9",
|
||||
"gen_directory": "../../../../duifei_cal_coarse.gen/sources_1/ip/fifo_AntCtrl",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"Component_Name": [ { "value": "fifo_AntCtrl", "resolve_type": "user", "usage": "all" } ],
|
||||
"Fifo_Implementation": [ { "value": "Independent_Clocks_Distributed_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"synchronization_stages": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"synchronization_stages_axi": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"INTERFACE_TYPE": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
|
||||
"Performance_Options": [ { "value": "Standard_FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"asymmetric_port_width": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Data_Width": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Input_Depth": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Output_Data_Width": [ { "value": "4", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Output_Depth": [ { "value": "1024", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Use_Embedded_Registers": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Reset_Pin": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Enable_Reset_Synchronization": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Reset_Type": [ { "value": "Asynchronous_Reset", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Flags_Reset_Value": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"Use_Dout_Reset": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Dout_Reset_Value": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
|
||||
"dynamic_power_saving": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
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|
||||
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|
||||
"Valid_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Valid_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Underflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Underflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Write_Acknowledge_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Write_Acknowledge_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Overflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Overflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"ecc_pipeline_reg": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Use_Extra_Logic": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Write_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Write_Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Read_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Read_Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Disable_Timing_Violations": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Read_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Write_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value": [ { "value": "1021", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Negate_Value": [ { "value": "1020", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value": [ { "value": "2", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Negate_Value": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PROTOCOL": [ { "value": "AXI4", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Clock_Type_AXI": [ { "value": "Common_Clock", "resolve_type": "user", "usage": "all" } ],
|
||||
"HAS_ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Clock_Enable_Type": [ { "value": "Slave_Interface_Clock_Enable", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "user", "usage": "all" } ],
|
||||
"ID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ADDRESS_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"DATA_WIDTH": [ { "value": "64", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"AWUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"WUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"BUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"ARUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"RUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"TDATA_NUM_BYTES": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
|
||||
"TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"TUSER_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Enable_TREADY": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Enable_TLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"HAS_TSTRB": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"TSTRB_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"HAS_TKEEP": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"TKEEP_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"wrch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_wrch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_wrch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_wrch": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_wrch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_wrch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_wrch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_wrch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"rach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_rach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_rach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_rach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_rach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_rach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_rach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_rach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"rdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_rdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_rdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_rdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_rdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_rdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_rdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_rdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"axis_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Implementation_axis": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
|
||||
"FIFO_Application_Type_axis": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Sbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Inject_Dbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Input_Depth_axis": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
|
||||
"Enable_Data_Counts_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Full_Type_axis": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Full_Threshold_Assert_Value_axis": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Programmable_Empty_Type_axis": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Empty_Threshold_Assert_Value_axis": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"Register_Slice_Mode_wach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_wdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_wrch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_rach": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_rdch": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Register_Slice_Mode_axis": [ { "value": "Fully_Registered", "resolve_type": "user", "usage": "all" } ],
|
||||
"Underflow_Flag_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Underflow_Sense_AXI": [ { "value": "Active_High", "resolve_type": "user", "usage": "all" } ],
|
||||
"Overflow_Flag_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Overflow_Sense_AXI": [ { "value": "Active_High", "resolve_type": "user", "usage": "all" } ],
|
||||
"Disable_Timing_Violations_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Add_NGC_Constraint_AXI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Enable_Common_Underflow": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Enable_Common_Overflow": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"enable_read_pointer_increment_by2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"Use_Embedded_Registers_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"enable_low_latency": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"use_dout_register": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Master_interface_Clock_enable_memory_mapped": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Slave_interface_Clock_enable_memory_mapped": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Output_Register_Type": [ { "value": "Embedded_Reg", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"Enable_Safety_Circuit": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"Enable_ECC_Type": [ { "value": "Hard_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"C_SELECT_XPM": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_COMMON_CLOCK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_SELECT_XPM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_COUNT_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DATA_COUNT_WIDTH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DEFAULT_VALUE": [ { "value": "BlankString", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DIN_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_DOUT_RST_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_DOUT_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ENABLE_RLOCS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_FULL_FLAGS_RST_VAL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_ALMOST_EMPTY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_ALMOST_FULL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_BACKUP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_INT_CLK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_MEMINIT_FILE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_OVERFLOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_RD_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_RD_RST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_SRST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_UNDERFLOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_WR_ACK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_WR_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_WR_RST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_IMPLEMENTATION_TYPE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_INIT_WR_PNTR_VAL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MEMORY_TYPE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MIF_FILE_NAME": [ { "value": "BlankString", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_OPTIMIZATION_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OVERFLOW_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRELOAD_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRELOAD_REGS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PRIM_FIFO_TYPE": [ { "value": "1kx18", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH_ASSERT_VAL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_THRESH_NEGATE_VAL": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_EMPTY_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH_ASSERT_VAL": [ { "value": "1021", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_THRESH_NEGATE_VAL": [ { "value": "1020", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_PROG_FULL_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RD_DATA_COUNT_WIDTH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RD_DEPTH": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RD_FREQ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_RD_PNTR_WIDTH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_UNDERFLOW_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_DOUT_RST": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_EMBEDDED_REG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_PIPELINE_REG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_POWER_SAVING_MODE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_FIFO16_FLAGS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_USE_FWFT_DATA_COUNT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_VALID_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_ACK_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_DATA_COUNT_WIDTH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_DEPTH": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_FREQ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_PNTR_WIDTH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_WR_RESPONSE_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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|
||||
"interfaces": {
|
||||
"write_clk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "wr_clk" } ]
|
||||
}
|
||||
},
|
||||
"read_clk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "rd_clk" } ]
|
||||
}
|
||||
},
|
||||
"FIFO_WRITE": {
|
||||
"vlnv": "xilinx.com:interface:fifo_write:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:fifo_write_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"port_maps": {
|
||||
"FULL": [ { "physical_name": "full" } ],
|
||||
"WR_DATA": [ { "physical_name": "din" } ],
|
||||
"WR_EN": [ { "physical_name": "wr_en" } ]
|
||||
}
|
||||
},
|
||||
"FIFO_READ": {
|
||||
"vlnv": "xilinx.com:interface:fifo_read:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:fifo_read_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"port_maps": {
|
||||
"EMPTY": [ { "physical_name": "empty" } ],
|
||||
"RD_DATA": [ { "physical_name": "dout" } ],
|
||||
"RD_EN": [ { "physical_name": "rd_en" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
+6299
File diff suppressed because it is too large
Load Diff
+6305
File diff suppressed because it is too large
Load Diff
+6310
File diff suppressed because it is too large
Load Diff
+6312
File diff suppressed because it is too large
Load Diff
+6347
File diff suppressed because it is too large
Load Diff
+1632
File diff suppressed because it is too large
Load Diff
+1630
File diff suppressed because it is too large
Load Diff
+1628
File diff suppressed because it is too large
Load Diff
+1631
File diff suppressed because it is too large
Load Diff
+1636
File diff suppressed because it is too large
Load Diff
+1639
File diff suppressed because it is too large
Load Diff
+188
@@ -0,0 +1,188 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 11:51:06 06/08/2020
|
||||
// Design Name:
|
||||
// Module Name: test_784TR_top
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
// ??????9?byte? ?1-8?????????????????8???????????????????3?byte???5?don't care??
|
||||
// ?9byte??4bit??spi??4bit??????
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
/*************?????????*******************/
|
||||
module adf4351_2(
|
||||
input i_sysclk ,
|
||||
input i_arstn ,
|
||||
output o_cfgover ,
|
||||
output o_ADF4351_SCK ,
|
||||
output o_ADF4351_DATA ,
|
||||
output o_ADF4351_LE ,
|
||||
output o_ADF4351_CE ,
|
||||
output o_ADF4351_mutel ,
|
||||
input i_ADF4351_locked
|
||||
);
|
||||
|
||||
|
||||
localparam DATA_WIDTH = 32;
|
||||
localparam DATA_LENTH = 6;
|
||||
localparam SYS_CLOCK = 10;
|
||||
localparam LOCK_PIRED = SYS_CLOCK * 100000;
|
||||
localparam rst_time = 16'h7fff;//16'h7fff
|
||||
reg[7:0] cnt_word = 8'd0;
|
||||
reg[5:0] cnt_bits = 6'd0;
|
||||
|
||||
reg [DATA_WIDTH-1:0] cfgdata = 0;
|
||||
wire [DATA_WIDTH-1:0] regdata;
|
||||
reg cfgover = 1'b0 ;
|
||||
reg pll_locked = 1'b0 ;
|
||||
reg load_en = 1'b0 ;
|
||||
reg [31:0] cnt_lock = 32'b0;
|
||||
(* KEEP = "TRUE" *)reg[3:0] cfgstate = 4'b0000;
|
||||
wire spiIdle;
|
||||
|
||||
reg spi_sdi = 1'b0,spi_csb = 1'b1 ;
|
||||
assign o_cfgover = cfgover ;
|
||||
assign o_ADF4351_LE = load_en ;
|
||||
assign o_ADF4351_mutel= 1'b1 ;
|
||||
assign o_ADF4351_SCK = o_ADF4351_CE ? 1'b0 : i_sysclk ;
|
||||
assign o_ADF4351_CE = spi_csb ;
|
||||
assign o_ADF4351_DATA = spi_sdi ;
|
||||
reg [DATA_WIDTH-1:0] CFGREG0 ;
|
||||
assign regdata = CFGREG0 ;
|
||||
reg cfg_start ;
|
||||
reg [15:0] counter0 ;
|
||||
|
||||
always@ (posedge i_sysclk)
|
||||
if(~i_arstn)
|
||||
CFGREG0 <= 32'b0;
|
||||
else begin
|
||||
//RFout = Fpfd*(INT + (Frac/Mod)) Fpfd = Refin*[(1+D)/(R*(1+T))]
|
||||
case (cnt_word)
|
||||
8'h00: CFGREG0 <= {32'h580005}; //reg 5
|
||||
8'h01: CFGREG0 <= {32'h85003C}; //reg 4
|
||||
8'h02: CFGREG0 <= {32'h4B3}; //reg 3
|
||||
8'h03: CFGREG0 <= {32'h28F42}; //reg 2 {5'b0,T,R,D,12'h,reg2} R = 1 D = 1 T = 1
|
||||
8'h04: CFGREG0 <= {32'h8008011}; //reg 1 {3'd0,phase adjust,prescaler,phase value,Frac,reg1}mod = 25
|
||||
8'h05: CFGREG0 <= {32'hC80000}; //reg 0 {1'b0,int,frac,reg0} int = 52 frac= 8
|
||||
default : CFGREG0 <= 32'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
always@(negedge i_sysclk)begin
|
||||
if(~i_arstn)begin
|
||||
cfgdata <= 0;
|
||||
cnt_word <= 8'd0;
|
||||
cnt_bits <= 6'd0;
|
||||
cfgover <= 1'b0;
|
||||
cfgstate <= 4'd0;
|
||||
spi_csb <= 1'b1;
|
||||
load_en <= 1'b1;
|
||||
spi_sdi <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
case(cfgstate)
|
||||
4'd0:begin
|
||||
if(cfg_start)begin
|
||||
cfgstate <= 4'd1;
|
||||
end
|
||||
else begin
|
||||
spi_csb <= 1'b1;
|
||||
load_en <= 1'b0;
|
||||
spi_sdi <= 1'b0;
|
||||
cfgover <= 1'b0;
|
||||
cfgstate <= 4'd0;
|
||||
end
|
||||
end
|
||||
4'd1:begin
|
||||
cfgdata <= regdata;
|
||||
cnt_lock <= 32'd0;
|
||||
cnt_bits <= 6'd0;
|
||||
cfgstate <= cfgstate + 1'b1;
|
||||
end
|
||||
4'd2:begin
|
||||
spi_csb <= 1'b0;
|
||||
load_en <= 1'b0;
|
||||
spi_sdi <= cfgdata[DATA_WIDTH-1];
|
||||
cfgdata <= cfgdata << 1'b1;
|
||||
cnt_bits <= cnt_bits + 1'b1;
|
||||
if(cnt_bits == DATA_WIDTH-1)begin
|
||||
cfgstate <= cfgstate + 1'b1;
|
||||
cnt_word <= cnt_word + 1'b1;
|
||||
end
|
||||
end
|
||||
4'd3:begin
|
||||
spi_csb <= 1'b1;
|
||||
load_en <= 1'b1;
|
||||
spi_sdi <= 1'b0;
|
||||
if(cnt_word == DATA_LENTH)
|
||||
cfgstate <= cfgstate + 1'b1;
|
||||
else
|
||||
cfgstate <= 4'd0;
|
||||
end
|
||||
4'd4:begin
|
||||
cfgstate <= 4'd5;
|
||||
spi_csb <= 1'b1;
|
||||
load_en <= 1'b0;
|
||||
spi_sdi <= 1'b0;
|
||||
end
|
||||
4'd5:begin//ftw cfg
|
||||
if(cnt_lock > LOCK_PIRED)
|
||||
begin
|
||||
pll_locked <= i_ADF4351_locked;
|
||||
cnt_lock <= cnt_lock;
|
||||
if( (pll_locked == 1'b0) && (cnt_lock > LOCK_PIRED))
|
||||
begin
|
||||
cfgstate <= 4'd1;
|
||||
cnt_word <= 8'd0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
cfgstate <= 4'd5;
|
||||
spi_csb <= 1'b1;
|
||||
spi_sdi <= 1'b0;
|
||||
cfgover <= 1'b1;
|
||||
end
|
||||
end
|
||||
else
|
||||
begin
|
||||
cnt_lock <= cnt_lock + 1'b1;
|
||||
end
|
||||
end
|
||||
default:cfgstate <= 4'd0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(negedge i_sysclk)begin
|
||||
if(~i_arstn)begin
|
||||
counter0 <= 16'd0;
|
||||
cfg_start <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
if(counter0 == rst_time)begin//16'h7fff
|
||||
counter0 <= counter0;
|
||||
cfg_start <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
counter0 <= counter0 + 1'b1;
|
||||
cfg_start <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
+441
@@ -0,0 +1,441 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 14:37:16 01/15/2022
|
||||
// Design Name:
|
||||
// Module Name: FRAC1
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module FRAC1(
|
||||
input clka,
|
||||
input [15:0] addra,
|
||||
output reg[24:0] douta
|
||||
);
|
||||
|
||||
|
||||
reg[11:0] addr=0;
|
||||
|
||||
always@(posedge clka)begin
|
||||
addr<= (addra+375) % 400 ;
|
||||
end
|
||||
|
||||
always@(posedge clka)begin
|
||||
case(addr)
|
||||
0 : douta <= 0 ;
|
||||
1 : douta <= 83886 ;
|
||||
2 : douta <= 167772 ;
|
||||
3 : douta <= 251658 ;
|
||||
4 : douta <= 335544 ;
|
||||
5 : douta <= 419430 ;
|
||||
6 : douta <= 503316 ;
|
||||
7 : douta <= 587202 ;
|
||||
8 : douta <= 671088 ;
|
||||
9 : douta <= 754974 ;
|
||||
10 : douta <= 838860 ;
|
||||
11 : douta <= 922746 ;
|
||||
12 : douta <= 1006632 ;
|
||||
13 : douta <= 1090519 ;
|
||||
14 : douta <= 1174405 ;
|
||||
15 : douta <= 1258291 ;
|
||||
16 : douta <= 1342177 ;
|
||||
17 : douta <= 1426063 ;
|
||||
18 : douta <= 1509949 ;
|
||||
19 : douta <= 1593835 ;
|
||||
20 : douta <= 1677721 ;
|
||||
21 : douta <= 1761607 ;
|
||||
22 : douta <= 1845493 ;
|
||||
23 : douta <= 1929379 ;
|
||||
24 : douta <= 2013265 ;
|
||||
25 : douta <= 2097152 ;
|
||||
26 : douta <= 2181038 ;
|
||||
27 : douta <= 2264924 ;
|
||||
28 : douta <= 2348810 ;
|
||||
29 : douta <= 2432696 ;
|
||||
30 : douta <= 2516582 ;
|
||||
31 : douta <= 2600468 ;
|
||||
32 : douta <= 2684354 ;
|
||||
33 : douta <= 2768240 ;
|
||||
34 : douta <= 2852126 ;
|
||||
35 : douta <= 2936012 ;
|
||||
36 : douta <= 3019898 ;
|
||||
37 : douta <= 3103784 ;
|
||||
38 : douta <= 3187671 ;
|
||||
39 : douta <= 3271557 ;
|
||||
40 : douta <= 3355443 ;
|
||||
41 : douta <= 3439329 ;
|
||||
42 : douta <= 3523215 ;
|
||||
43 : douta <= 3607101 ;
|
||||
44 : douta <= 3690987 ;
|
||||
45 : douta <= 3774873 ;
|
||||
46 : douta <= 3858759 ;
|
||||
47 : douta <= 3942645 ;
|
||||
48 : douta <= 4026531 ;
|
||||
49 : douta <= 4110417 ;
|
||||
50 : douta <= 4194304 ;
|
||||
51 : douta <= 4278190 ;
|
||||
52 : douta <= 4362076 ;
|
||||
53 : douta <= 4445962 ;
|
||||
54 : douta <= 4529848 ;
|
||||
55 : douta <= 4613734 ;
|
||||
56 : douta <= 4697620 ;
|
||||
57 : douta <= 4781506 ;
|
||||
58 : douta <= 4865392 ;
|
||||
59 : douta <= 4949278 ;
|
||||
60 : douta <= 5033164 ;
|
||||
61 : douta <= 5117050 ;
|
||||
62 : douta <= 5200936 ;
|
||||
63 : douta <= 5284823 ;
|
||||
64 : douta <= 5368709 ;
|
||||
65 : douta <= 5452595 ;
|
||||
66 : douta <= 5536481 ;
|
||||
67 : douta <= 5620367 ;
|
||||
68 : douta <= 5704253 ;
|
||||
69 : douta <= 5788139 ;
|
||||
70 : douta <= 5872025 ;
|
||||
71 : douta <= 5955911 ;
|
||||
72 : douta <= 6039797 ;
|
||||
73 : douta <= 6123683 ;
|
||||
74 : douta <= 6207569 ;
|
||||
75 : douta <= 6291456 ;
|
||||
76 : douta <= 6375342 ;
|
||||
77 : douta <= 6459228 ;
|
||||
78 : douta <= 6543114 ;
|
||||
79 : douta <= 6627000 ;
|
||||
80 : douta <= 6710886 ;
|
||||
81 : douta <= 6794772 ;
|
||||
82 : douta <= 6878658 ;
|
||||
83 : douta <= 6962544 ;
|
||||
84 : douta <= 7046430 ;
|
||||
85 : douta <= 7130316 ;
|
||||
86 : douta <= 7214202 ;
|
||||
87 : douta <= 7298088 ;
|
||||
88 : douta <= 7381975 ;
|
||||
89 : douta <= 7465861 ;
|
||||
90 : douta <= 7549747 ;
|
||||
91 : douta <= 7633633 ;
|
||||
92 : douta <= 7717519 ;
|
||||
93 : douta <= 7801405 ;
|
||||
94 : douta <= 7885291 ;
|
||||
95 : douta <= 7969177 ;
|
||||
96 : douta <= 8053063 ;
|
||||
97 : douta <= 8136949 ;
|
||||
98 : douta <= 8220835 ;
|
||||
99 : douta <= 8304721 ;
|
||||
100 : douta <= 8388608 ;
|
||||
101 : douta <= 8472494 ;
|
||||
102 : douta <= 8556380 ;
|
||||
103 : douta <= 8640266 ;
|
||||
104 : douta <= 8724152 ;
|
||||
105 : douta <= 8808038 ;
|
||||
106 : douta <= 8891924 ;
|
||||
107 : douta <= 8975810 ;
|
||||
108 : douta <= 9059696 ;
|
||||
109 : douta <= 9143582 ;
|
||||
110 : douta <= 9227468 ;
|
||||
111 : douta <= 9311354 ;
|
||||
112 : douta <= 9395240 ;
|
||||
113 : douta <= 9479127 ;
|
||||
114 : douta <= 9563013 ;
|
||||
115 : douta <= 9646899 ;
|
||||
116 : douta <= 9730785 ;
|
||||
117 : douta <= 9814671 ;
|
||||
118 : douta <= 9898557 ;
|
||||
119 : douta <= 9982443 ;
|
||||
120 : douta <= 10066329 ;
|
||||
121 : douta <= 10150215 ;
|
||||
122 : douta <= 10234101 ;
|
||||
123 : douta <= 10317987 ;
|
||||
124 : douta <= 10401873 ;
|
||||
125 : douta <= 10485760 ;
|
||||
126 : douta <= 10569646 ;
|
||||
127 : douta <= 10653532 ;
|
||||
128 : douta <= 10737418 ;
|
||||
129 : douta <= 10821304 ;
|
||||
130 : douta <= 10905190 ;
|
||||
131 : douta <= 10989076 ;
|
||||
132 : douta <= 11072962 ;
|
||||
133 : douta <= 11156848 ;
|
||||
134 : douta <= 11240734 ;
|
||||
135 : douta <= 11324620 ;
|
||||
136 : douta <= 11408506 ;
|
||||
137 : douta <= 11492392 ;
|
||||
138 : douta <= 11576279 ;
|
||||
139 : douta <= 11660165 ;
|
||||
140 : douta <= 11744051 ;
|
||||
141 : douta <= 11827937 ;
|
||||
142 : douta <= 11911823 ;
|
||||
143 : douta <= 11995709 ;
|
||||
144 : douta <= 12079595 ;
|
||||
145 : douta <= 12163481 ;
|
||||
146 : douta <= 12247367 ;
|
||||
147 : douta <= 12331253 ;
|
||||
148 : douta <= 12415139 ;
|
||||
149 : douta <= 12499025 ;
|
||||
150 : douta <= 12582912 ;
|
||||
151 : douta <= 12666798 ;
|
||||
152 : douta <= 12750684 ;
|
||||
153 : douta <= 12834570 ;
|
||||
154 : douta <= 12918456 ;
|
||||
155 : douta <= 13002342 ;
|
||||
156 : douta <= 13086228 ;
|
||||
157 : douta <= 13170114 ;
|
||||
158 : douta <= 13254000 ;
|
||||
159 : douta <= 13337886 ;
|
||||
160 : douta <= 13421772 ;
|
||||
161 : douta <= 13505658 ;
|
||||
162 : douta <= 13589544 ;
|
||||
163 : douta <= 13673431 ;
|
||||
164 : douta <= 13757317 ;
|
||||
165 : douta <= 13841203 ;
|
||||
166 : douta <= 13925089 ;
|
||||
167 : douta <= 14008975 ;
|
||||
168 : douta <= 14092861 ;
|
||||
169 : douta <= 14176747 ;
|
||||
170 : douta <= 14260633 ;
|
||||
171 : douta <= 14344519 ;
|
||||
172 : douta <= 14428405 ;
|
||||
173 : douta <= 14512291 ;
|
||||
174 : douta <= 14596177 ;
|
||||
175 : douta <= 14680064 ;
|
||||
176 : douta <= 14763950 ;
|
||||
177 : douta <= 14847836 ;
|
||||
178 : douta <= 14931722 ;
|
||||
179 : douta <= 15015608 ;
|
||||
180 : douta <= 15099494 ;
|
||||
181 : douta <= 15183380 ;
|
||||
182 : douta <= 15267266 ;
|
||||
183 : douta <= 15351152 ;
|
||||
184 : douta <= 15435038 ;
|
||||
185 : douta <= 15518924 ;
|
||||
186 : douta <= 15602810 ;
|
||||
187 : douta <= 15686696 ;
|
||||
188 : douta <= 15770583 ;
|
||||
189 : douta <= 15854469 ;
|
||||
190 : douta <= 15938355 ;
|
||||
191 : douta <= 16022241 ;
|
||||
192 : douta <= 16106127 ;
|
||||
193 : douta <= 16190013 ;
|
||||
194 : douta <= 16273899 ;
|
||||
195 : douta <= 16357785 ;
|
||||
196 : douta <= 16441671 ;
|
||||
197 : douta <= 16525557 ;
|
||||
198 : douta <= 16609443 ;
|
||||
199 : douta <= 16693329 ;
|
||||
200 : douta <= 16777216 ;
|
||||
201 : douta <= 16861102 ;
|
||||
202 : douta <= 16944988 ;
|
||||
203 : douta <= 17028874 ;
|
||||
204 : douta <= 17112760 ;
|
||||
205 : douta <= 17196646 ;
|
||||
206 : douta <= 17280532 ;
|
||||
207 : douta <= 17364418 ;
|
||||
208 : douta <= 17448304 ;
|
||||
209 : douta <= 17532190 ;
|
||||
210 : douta <= 17616076 ;
|
||||
211 : douta <= 17699962 ;
|
||||
212 : douta <= 17783848 ;
|
||||
213 : douta <= 17867735 ;
|
||||
214 : douta <= 17951621 ;
|
||||
215 : douta <= 18035507 ;
|
||||
216 : douta <= 18119393 ;
|
||||
217 : douta <= 18203279 ;
|
||||
218 : douta <= 18287165 ;
|
||||
219 : douta <= 18371051 ;
|
||||
220 : douta <= 18454937 ;
|
||||
221 : douta <= 18538823 ;
|
||||
222 : douta <= 18622709 ;
|
||||
223 : douta <= 18706595 ;
|
||||
224 : douta <= 18790481 ;
|
||||
225 : douta <= 18874368 ;
|
||||
226 : douta <= 18958254 ;
|
||||
227 : douta <= 19042140 ;
|
||||
228 : douta <= 19126026 ;
|
||||
229 : douta <= 19209912 ;
|
||||
230 : douta <= 19293798 ;
|
||||
231 : douta <= 19377684 ;
|
||||
232 : douta <= 19461570 ;
|
||||
233 : douta <= 19545456 ;
|
||||
234 : douta <= 19629342 ;
|
||||
235 : douta <= 19713228 ;
|
||||
236 : douta <= 19797114 ;
|
||||
237 : douta <= 19881000 ;
|
||||
238 : douta <= 19964887 ;
|
||||
239 : douta <= 20048773 ;
|
||||
240 : douta <= 20132659 ;
|
||||
241 : douta <= 20216545 ;
|
||||
242 : douta <= 20300431 ;
|
||||
243 : douta <= 20384317 ;
|
||||
244 : douta <= 20468203 ;
|
||||
245 : douta <= 20552089 ;
|
||||
246 : douta <= 20635975 ;
|
||||
247 : douta <= 20719861 ;
|
||||
248 : douta <= 20803747 ;
|
||||
249 : douta <= 20887633 ;
|
||||
250 : douta <= 20971520 ;
|
||||
251 : douta <= 21055406 ;
|
||||
252 : douta <= 21139292 ;
|
||||
253 : douta <= 21223178 ;
|
||||
254 : douta <= 21307064 ;
|
||||
255 : douta <= 21390950 ;
|
||||
256 : douta <= 21474836 ;
|
||||
257 : douta <= 21558722 ;
|
||||
258 : douta <= 21642608 ;
|
||||
259 : douta <= 21726494 ;
|
||||
260 : douta <= 21810380 ;
|
||||
261 : douta <= 21894266 ;
|
||||
262 : douta <= 21978152 ;
|
||||
263 : douta <= 22062039 ;
|
||||
264 : douta <= 22145925 ;
|
||||
265 : douta <= 22229811 ;
|
||||
266 : douta <= 22313697 ;
|
||||
267 : douta <= 22397583 ;
|
||||
268 : douta <= 22481469 ;
|
||||
269 : douta <= 22565355 ;
|
||||
270 : douta <= 22649241 ;
|
||||
271 : douta <= 22733127 ;
|
||||
272 : douta <= 22817013 ;
|
||||
273 : douta <= 22900899 ;
|
||||
274 : douta <= 22984785 ;
|
||||
275 : douta <= 23068672 ;
|
||||
276 : douta <= 23152558 ;
|
||||
277 : douta <= 23236444 ;
|
||||
278 : douta <= 23320330 ;
|
||||
279 : douta <= 23404216 ;
|
||||
280 : douta <= 23488102 ;
|
||||
281 : douta <= 23571988 ;
|
||||
282 : douta <= 23655874 ;
|
||||
283 : douta <= 23739760 ;
|
||||
284 : douta <= 23823646 ;
|
||||
285 : douta <= 23907532 ;
|
||||
286 : douta <= 23991418 ;
|
||||
287 : douta <= 24075304 ;
|
||||
288 : douta <= 24159191 ;
|
||||
289 : douta <= 24243077 ;
|
||||
290 : douta <= 24326963 ;
|
||||
291 : douta <= 24410849 ;
|
||||
292 : douta <= 24494735 ;
|
||||
293 : douta <= 24578621 ;
|
||||
294 : douta <= 24662507 ;
|
||||
295 : douta <= 24746393 ;
|
||||
296 : douta <= 24830279 ;
|
||||
297 : douta <= 24914165 ;
|
||||
298 : douta <= 24998051 ;
|
||||
299 : douta <= 25081937 ;
|
||||
300 : douta <= 25165824 ;
|
||||
301 : douta <= 25249710 ;
|
||||
302 : douta <= 25333596 ;
|
||||
303 : douta <= 25417482 ;
|
||||
304 : douta <= 25501368 ;
|
||||
305 : douta <= 25585254 ;
|
||||
306 : douta <= 25669140 ;
|
||||
307 : douta <= 25753026 ;
|
||||
308 : douta <= 25836912 ;
|
||||
309 : douta <= 25920798 ;
|
||||
310 : douta <= 26004684 ;
|
||||
311 : douta <= 26088570 ;
|
||||
312 : douta <= 26172456 ;
|
||||
313 : douta <= 26256343 ;
|
||||
314 : douta <= 26340229 ;
|
||||
315 : douta <= 26424115 ;
|
||||
316 : douta <= 26508001 ;
|
||||
317 : douta <= 26591887 ;
|
||||
318 : douta <= 26675773 ;
|
||||
319 : douta <= 26759659 ;
|
||||
320 : douta <= 26843545 ;
|
||||
321 : douta <= 26927431 ;
|
||||
322 : douta <= 27011317 ;
|
||||
323 : douta <= 27095203 ;
|
||||
324 : douta <= 27179089 ;
|
||||
325 : douta <= 27262976 ;
|
||||
326 : douta <= 27346862 ;
|
||||
327 : douta <= 27430748 ;
|
||||
328 : douta <= 27514634 ;
|
||||
329 : douta <= 27598520 ;
|
||||
330 : douta <= 27682406 ;
|
||||
331 : douta <= 27766292 ;
|
||||
332 : douta <= 27850178 ;
|
||||
333 : douta <= 27934064 ;
|
||||
334 : douta <= 28017950 ;
|
||||
335 : douta <= 28101836 ;
|
||||
336 : douta <= 28185722 ;
|
||||
337 : douta <= 28269608 ;
|
||||
338 : douta <= 28353495 ;
|
||||
339 : douta <= 28437381 ;
|
||||
340 : douta <= 28521267 ;
|
||||
341 : douta <= 28605153 ;
|
||||
342 : douta <= 28689039 ;
|
||||
343 : douta <= 28772925 ;
|
||||
344 : douta <= 28856811 ;
|
||||
345 : douta <= 28940697 ;
|
||||
346 : douta <= 29024583 ;
|
||||
347 : douta <= 29108469 ;
|
||||
348 : douta <= 29192355 ;
|
||||
349 : douta <= 29276241 ;
|
||||
350 : douta <= 29360128 ;
|
||||
351 : douta <= 29444014 ;
|
||||
352 : douta <= 29527900 ;
|
||||
353 : douta <= 29611786 ;
|
||||
354 : douta <= 29695672 ;
|
||||
355 : douta <= 29779558 ;
|
||||
356 : douta <= 29863444 ;
|
||||
357 : douta <= 29947330 ;
|
||||
358 : douta <= 30031216 ;
|
||||
359 : douta <= 30115102 ;
|
||||
360 : douta <= 30198988 ;
|
||||
361 : douta <= 30282874 ;
|
||||
362 : douta <= 30366760 ;
|
||||
363 : douta <= 30450647 ;
|
||||
364 : douta <= 30534533 ;
|
||||
365 : douta <= 30618419 ;
|
||||
366 : douta <= 30702305 ;
|
||||
367 : douta <= 30786191 ;
|
||||
368 : douta <= 30870077 ;
|
||||
369 : douta <= 30953963 ;
|
||||
370 : douta <= 31037849 ;
|
||||
371 : douta <= 31121735 ;
|
||||
372 : douta <= 31205621 ;
|
||||
373 : douta <= 31289507 ;
|
||||
374 : douta <= 31373393 ;
|
||||
375 : douta <= 31457280 ;
|
||||
376 : douta <= 31541166 ;
|
||||
377 : douta <= 31625052 ;
|
||||
378 : douta <= 31708938 ;
|
||||
379 : douta <= 31792824 ;
|
||||
380 : douta <= 31876710 ;
|
||||
381 : douta <= 31960596 ;
|
||||
382 : douta <= 32044482 ;
|
||||
383 : douta <= 32128368 ;
|
||||
384 : douta <= 32212254 ;
|
||||
385 : douta <= 32296140 ;
|
||||
386 : douta <= 32380026 ;
|
||||
387 : douta <= 32463912 ;
|
||||
388 : douta <= 32547799 ;
|
||||
389 : douta <= 32631685 ;
|
||||
390 : douta <= 32715571 ;
|
||||
391 : douta <= 32799457 ;
|
||||
392 : douta <= 32883343 ;
|
||||
393 : douta <= 32967229 ;
|
||||
394 : douta <= 33051115 ;
|
||||
395 : douta <= 33135001 ;
|
||||
396 : douta <= 33218887 ;
|
||||
397 : douta <= 33302773 ;
|
||||
398 : douta <= 33386659 ;
|
||||
399 : douta <= 33470545 ;
|
||||
default : douta <= douta ;
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
+3569
File diff suppressed because it is too large
Load Diff
+348
@@ -0,0 +1,348 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 17:05:24 04/08/2022
|
||||
// Design Name:
|
||||
// Module Name: R_CAL
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module R_CAL_1(
|
||||
input i_clk ,
|
||||
input i_rstn ,
|
||||
input signed[7:0] i_temp ,
|
||||
input [15:0] fre_mode ,
|
||||
output reg[3:0] R_CAL
|
||||
|
||||
);
|
||||
|
||||
//接收通道1
|
||||
always@(posedge i_clk,negedge i_rstn)begin //1dB 步进
|
||||
if(!i_rstn)
|
||||
R_CAL<='d0;
|
||||
else if(i_temp>=8'sd70)begin//高温校准接收通道1
|
||||
case(fre_mode)
|
||||
0 : R_CAL<= 7 ; //20375 ~ 20414
|
||||
1 : R_CAL<= 7 ; //20415 ~ 20454
|
||||
2 : R_CAL<= 7 ; //20455 ~ 20494
|
||||
3 : R_CAL<= 6 ; //20495 ~ 20534
|
||||
4 : R_CAL<= 6 ; //20535 ~ 20574
|
||||
5 : R_CAL<= 6 ; //20575 ~ 20614
|
||||
6 : R_CAL<= 6 ; //20615 ~ 20654
|
||||
7 : R_CAL<= 6 ; //20655 ~ 20694
|
||||
8 : R_CAL<= 5 ; //20695 ~ 20734
|
||||
9 : R_CAL<= 5 ; //20735 ~ 20774
|
||||
10: R_CAL<= 6 ; //20775 ~ 20814
|
||||
11: R_CAL<= 6 ; //20815 ~ 20854
|
||||
12: R_CAL<= 6 ; //20855 ~ 20894
|
||||
13: R_CAL<= 6 ; //20895 ~ 20934
|
||||
14: R_CAL<= 6 ; //20935 ~ 20974
|
||||
15: R_CAL<= 6 ; //20975 ~ 21014
|
||||
16: R_CAL<= 6 ; //21015 ~ 21054
|
||||
17: R_CAL<= 6 ; //21055 ~ 21094
|
||||
18: R_CAL<= 6 ; //21095 ~ 21134
|
||||
19: R_CAL<= 7 ; //21135 ~ 21174
|
||||
20: R_CAL<= 7 ; //21175 ~ 21214
|
||||
21: R_CAL<= 7 ; //21215 ~ 21254
|
||||
22: R_CAL<= 8 ; //21255 ~ 21294
|
||||
23: R_CAL<= 8 ; //21295 ~ 21334
|
||||
24: R_CAL<= 8 ; //21335 ~ 21374
|
||||
25: R_CAL<= 8 ; //21375 ~ 21414
|
||||
26: R_CAL<= 8 ; //21415 ~ 21454
|
||||
27: R_CAL<= 8 ; //21455 ~ 21494
|
||||
28: R_CAL<= 8 ; //21495 ~ 21534
|
||||
29: R_CAL<= 8 ; //21535 ~ 21574
|
||||
30: R_CAL<= 8 ; //21575 ~ 21614
|
||||
31: R_CAL<= 8 ; //21615 ~ 21654
|
||||
32: R_CAL<= 8 ; //21655 ~ 21694
|
||||
33: R_CAL<= 8 ; //21695 ~ 21734
|
||||
34: R_CAL<= 8 ; //21735 ~ 21774
|
||||
35: R_CAL<= 8 ; //21775 ~ 21814
|
||||
36: R_CAL<= 8 ; //21815 ~ 21854
|
||||
37: R_CAL<= 8 ; //21855 ~ 21894
|
||||
38: R_CAL<= 7 ; //21895 ~ 21934
|
||||
39: R_CAL<= 7 ; //21935 ~ 21974
|
||||
40: R_CAL<= 7 ; //21975 ~ 22014
|
||||
41: R_CAL<= 7 ; //22015 ~ 22054
|
||||
42: R_CAL<= 7 ; //22055 ~ 22094
|
||||
43: R_CAL<= 7 ; //22095 ~ 22134
|
||||
44: R_CAL<= 7 ; //22135 ~ 22174
|
||||
45: R_CAL<= 7 ; //22175 ~ 22214
|
||||
46: R_CAL<= 7 ; //22215 ~ 22254
|
||||
47: R_CAL<= 7 ; //22255 ~ 22294
|
||||
48: R_CAL<= 7 ; //22295 ~ 22334
|
||||
49: R_CAL<= 7 ; //22335 ~ 22374
|
||||
50: R_CAL<= 7 ; //22375 ~ 22414
|
||||
51: R_CAL<= 7 ; //22415 ~ 22454
|
||||
52: R_CAL<= 7 ; //22455 ~ 22494
|
||||
53: R_CAL<= 7 ; //22495 ~ 22534
|
||||
54: R_CAL<= 7 ; //22535 ~ 22574
|
||||
55: R_CAL<= 7 ; //22575 ~ 22614
|
||||
56: R_CAL<= 7 ; //22615 ~ 22654
|
||||
57: R_CAL<= 7 ; //22655 ~ 22694
|
||||
58: R_CAL<= 8 ; //22695 ~ 22734
|
||||
59: R_CAL<= 8 ; //22735 ~ 22774
|
||||
60: R_CAL<= 8 ; //22775 ~ 22814
|
||||
61: R_CAL<= 8 ; //22815 ~ 22854
|
||||
62: R_CAL<= 8 ; //22855 ~ 22894
|
||||
63: R_CAL<= 8 ; //22895 ~ 22934
|
||||
64: R_CAL<= 8 ; //22935 ~ 22974
|
||||
65: R_CAL<= 8 ; //22975 ~ 23014
|
||||
66: R_CAL<= 8 ; //23015 ~ 23054
|
||||
67: R_CAL<= 8 ; //23055 ~ 23094
|
||||
68: R_CAL<= 7 ; //23095 ~ 23134
|
||||
69: R_CAL<= 7 ; //23135 ~ 23174
|
||||
70: R_CAL<= 7 ; //23175 ~ 23214
|
||||
71: R_CAL<= 7 ; //23215 ~ 23254
|
||||
72: R_CAL<= 6 ; //23255 ~ 23294
|
||||
73: R_CAL<= 6 ; //23295 ~ 23334
|
||||
74: R_CAL<= 6 ; //23335 ~ 23374
|
||||
75: R_CAL<= 6 ; //23375 ~ 23414
|
||||
76: R_CAL<= 6 ; //23415 ~ 23454
|
||||
77: R_CAL<= 6 ; //23455 ~ 23494
|
||||
78: R_CAL<= 6 ; //23495 ~ 23534
|
||||
79: R_CAL<= 5 ; //23535 ~ 23574
|
||||
80: R_CAL<= 6 ; //23575 ~ 23614
|
||||
81: R_CAL<= 6 ; //23615 ~ 23654
|
||||
82: R_CAL<= 6 ; //23655 ~ 23694
|
||||
83: R_CAL<= 6 ; //23695 ~ 23734
|
||||
84: R_CAL<= 6 ; //23735 ~ 23774
|
||||
85: R_CAL<= 6 ; //23775 ~ 23814
|
||||
86: R_CAL<= 6 ; //23815 ~ 23854
|
||||
87: R_CAL<= 6 ; //23855 ~ 23875
|
||||
default:R_CAL<=R_CAL;
|
||||
endcase
|
||||
end
|
||||
|
||||
else if(i_temp>=8'sd0)begin//常温校准接收通道1
|
||||
case(fre_mode)
|
||||
0 : R_CAL<= 7 ; //20375 ~ 20414
|
||||
1 : R_CAL<= 7 ; //20415 ~ 20454
|
||||
2 : R_CAL<= 7 ; //20455 ~ 20494
|
||||
3 : R_CAL<= 6 ; //20495 ~ 20534
|
||||
4 : R_CAL<= 6 ; //20535 ~ 20574
|
||||
5 : R_CAL<= 6 ; //20575 ~ 20614
|
||||
6 : R_CAL<= 6 ; //20615 ~ 20654
|
||||
7 : R_CAL<= 6 ; //20655 ~ 20694
|
||||
8 : R_CAL<= 5 ; //20695 ~ 20734
|
||||
9 : R_CAL<= 5 ; //20735 ~ 20774
|
||||
10: R_CAL<= 6 ; //20775 ~ 20814
|
||||
11: R_CAL<= 6 ; //20815 ~ 20854
|
||||
12: R_CAL<= 6 ; //20855 ~ 20894
|
||||
13: R_CAL<= 6 ; //20895 ~ 20934
|
||||
14: R_CAL<= 6 ; //20935 ~ 20974
|
||||
15: R_CAL<= 6 ; //20975 ~ 21014
|
||||
16: R_CAL<= 6 ; //21015 ~ 21054
|
||||
17: R_CAL<= 6 ; //21055 ~ 21094
|
||||
18: R_CAL<= 6 ; //21095 ~ 21134
|
||||
19: R_CAL<= 7 ; //21135 ~ 21174
|
||||
20: R_CAL<= 7 ; //21175 ~ 21214
|
||||
21: R_CAL<= 7 ; //21215 ~ 21254
|
||||
22: R_CAL<= 8 ; //21255 ~ 21294
|
||||
23: R_CAL<= 8 ; //21295 ~ 21334
|
||||
24: R_CAL<= 8 ; //21335 ~ 21374
|
||||
25: R_CAL<= 8 ; //21375 ~ 21414
|
||||
26: R_CAL<= 8 ; //21415 ~ 21454
|
||||
27: R_CAL<= 8 ; //21455 ~ 21494
|
||||
28: R_CAL<= 8 ; //21495 ~ 21534
|
||||
29: R_CAL<= 8 ; //21535 ~ 21574
|
||||
30: R_CAL<= 8 ; //21575 ~ 21614
|
||||
31: R_CAL<= 8 ; //21615 ~ 21654
|
||||
32: R_CAL<= 8 ; //21655 ~ 21694
|
||||
33: R_CAL<= 8 ; //21695 ~ 21734
|
||||
34: R_CAL<= 8 ; //21735 ~ 21774
|
||||
35: R_CAL<= 8 ; //21775 ~ 21814
|
||||
36: R_CAL<= 8 ; //21815 ~ 21854
|
||||
37: R_CAL<= 8 ; //21855 ~ 21894
|
||||
38: R_CAL<= 7 ; //21895 ~ 21934
|
||||
39: R_CAL<= 7 ; //21935 ~ 21974
|
||||
40: R_CAL<= 7 ; //21975 ~ 22014
|
||||
41: R_CAL<= 7 ; //22015 ~ 22054
|
||||
42: R_CAL<= 7 ; //22055 ~ 22094
|
||||
43: R_CAL<= 7 ; //22095 ~ 22134
|
||||
44: R_CAL<= 7 ; //22135 ~ 22174
|
||||
45: R_CAL<= 7 ; //22175 ~ 22214
|
||||
46: R_CAL<= 7 ; //22215 ~ 22254
|
||||
47: R_CAL<= 7 ; //22255 ~ 22294
|
||||
48: R_CAL<= 7 ; //22295 ~ 22334
|
||||
49: R_CAL<= 7 ; //22335 ~ 22374
|
||||
50: R_CAL<= 7 ; //22375 ~ 22414
|
||||
51: R_CAL<= 7 ; //22415 ~ 22454
|
||||
52: R_CAL<= 7 ; //22455 ~ 22494
|
||||
53: R_CAL<= 7 ; //22495 ~ 22534
|
||||
54: R_CAL<= 7 ; //22535 ~ 22574
|
||||
55: R_CAL<= 7 ; //22575 ~ 22614
|
||||
56: R_CAL<= 7 ; //22615 ~ 22654
|
||||
57: R_CAL<= 7 ; //22655 ~ 22694
|
||||
58: R_CAL<= 8 ; //22695 ~ 22734
|
||||
59: R_CAL<= 8 ; //22735 ~ 22774
|
||||
60: R_CAL<= 8 ; //22775 ~ 22814
|
||||
61: R_CAL<= 8 ; //22815 ~ 22854
|
||||
62: R_CAL<= 8 ; //22855 ~ 22894
|
||||
63: R_CAL<= 8 ; //22895 ~ 22934
|
||||
64: R_CAL<= 8 ; //22935 ~ 22974
|
||||
65: R_CAL<= 8 ; //22975 ~ 23014
|
||||
66: R_CAL<= 8 ; //23015 ~ 23054
|
||||
67: R_CAL<= 8 ; //23055 ~ 23094
|
||||
68: R_CAL<= 7 ; //23095 ~ 23134
|
||||
69: R_CAL<= 7 ; //23135 ~ 23174
|
||||
70: R_CAL<= 7 ; //23175 ~ 23214
|
||||
71: R_CAL<= 7 ; //23215 ~ 23254
|
||||
72: R_CAL<= 6 ; //23255 ~ 23294
|
||||
73: R_CAL<= 6 ; //23295 ~ 23334
|
||||
74: R_CAL<= 6 ; //23335 ~ 23374
|
||||
75: R_CAL<= 6 ; //23375 ~ 23414
|
||||
76: R_CAL<= 6 ; //23415 ~ 23454
|
||||
77: R_CAL<= 6 ; //23455 ~ 23494
|
||||
78: R_CAL<= 6 ; //23495 ~ 23534
|
||||
79: R_CAL<= 5 ; //23535 ~ 23574
|
||||
80: R_CAL<= 6 ; //23575 ~ 23614
|
||||
81: R_CAL<= 6 ; //23615 ~ 23654
|
||||
82: R_CAL<= 6 ; //23655 ~ 23694
|
||||
83: R_CAL<= 6 ; //23695 ~ 23734
|
||||
84: R_CAL<= 6 ; //23735 ~ 23774
|
||||
85: R_CAL<= 6 ; //23775 ~ 23814
|
||||
86: R_CAL<= 6 ; //23815 ~ 23854
|
||||
87: R_CAL<= 6 ; //23855 ~ 23875
|
||||
default:R_CAL<=R_CAL;
|
||||
endcase
|
||||
end
|
||||
else begin//低温校准接收通道1
|
||||
case(fre_mode)
|
||||
0 : R_CAL<= 7 ; //20375 ~ 20414
|
||||
1 : R_CAL<= 7 ; //20415 ~ 20454
|
||||
2 : R_CAL<= 7 ; //20455 ~ 20494
|
||||
3 : R_CAL<= 6 ; //20495 ~ 20534
|
||||
4 : R_CAL<= 6 ; //20535 ~ 20574
|
||||
5 : R_CAL<= 6 ; //20575 ~ 20614
|
||||
6 : R_CAL<= 6 ; //20615 ~ 20654
|
||||
7 : R_CAL<= 6 ; //20655 ~ 20694
|
||||
8 : R_CAL<= 5 ; //20695 ~ 20734
|
||||
9 : R_CAL<= 5 ; //20735 ~ 20774
|
||||
10: R_CAL<= 6 ; //20775 ~ 20814
|
||||
11: R_CAL<= 6 ; //20815 ~ 20854
|
||||
12: R_CAL<= 6 ; //20855 ~ 20894
|
||||
13: R_CAL<= 6 ; //20895 ~ 20934
|
||||
14: R_CAL<= 6 ; //20935 ~ 20974
|
||||
15: R_CAL<= 6 ; //20975 ~ 21014
|
||||
16: R_CAL<= 6 ; //21015 ~ 21054
|
||||
17: R_CAL<= 6 ; //21055 ~ 21094
|
||||
18: R_CAL<= 6 ; //21095 ~ 21134
|
||||
19: R_CAL<= 7 ; //21135 ~ 21174
|
||||
20: R_CAL<= 7 ; //21175 ~ 21214
|
||||
21: R_CAL<= 7 ; //21215 ~ 21254
|
||||
22: R_CAL<= 8 ; //21255 ~ 21294
|
||||
23: R_CAL<= 8 ; //21295 ~ 21334
|
||||
24: R_CAL<= 8 ; //21335 ~ 21374
|
||||
25: R_CAL<= 8 ; //21375 ~ 21414
|
||||
26: R_CAL<= 8 ; //21415 ~ 21454
|
||||
27: R_CAL<= 8 ; //21455 ~ 21494
|
||||
28: R_CAL<= 8 ; //21495 ~ 21534
|
||||
29: R_CAL<= 8 ; //21535 ~ 21574
|
||||
30: R_CAL<= 8 ; //21575 ~ 21614
|
||||
31: R_CAL<= 8 ; //21615 ~ 21654
|
||||
32: R_CAL<= 8 ; //21655 ~ 21694
|
||||
33: R_CAL<= 8 ; //21695 ~ 21734
|
||||
34: R_CAL<= 8 ; //21735 ~ 21774
|
||||
35: R_CAL<= 8 ; //21775 ~ 21814
|
||||
36: R_CAL<= 8 ; //21815 ~ 21854
|
||||
37: R_CAL<= 8 ; //21855 ~ 21894
|
||||
38: R_CAL<= 7 ; //21895 ~ 21934
|
||||
39: R_CAL<= 7 ; //21935 ~ 21974
|
||||
40: R_CAL<= 7 ; //21975 ~ 22014
|
||||
41: R_CAL<= 7 ; //22015 ~ 22054
|
||||
42: R_CAL<= 7 ; //22055 ~ 22094
|
||||
43: R_CAL<= 7 ; //22095 ~ 22134
|
||||
44: R_CAL<= 7 ; //22135 ~ 22174
|
||||
45: R_CAL<= 7 ; //22175 ~ 22214
|
||||
46: R_CAL<= 7 ; //22215 ~ 22254
|
||||
47: R_CAL<= 7 ; //22255 ~ 22294
|
||||
48: R_CAL<= 7 ; //22295 ~ 22334
|
||||
49: R_CAL<= 7 ; //22335 ~ 22374
|
||||
50: R_CAL<= 7 ; //22375 ~ 22414
|
||||
51: R_CAL<= 7 ; //22415 ~ 22454
|
||||
52: R_CAL<= 7 ; //22455 ~ 22494
|
||||
53: R_CAL<= 7 ; //22495 ~ 22534
|
||||
54: R_CAL<= 7 ; //22535 ~ 22574
|
||||
55: R_CAL<= 7 ; //22575 ~ 22614
|
||||
56: R_CAL<= 7 ; //22615 ~ 22654
|
||||
57: R_CAL<= 7 ; //22655 ~ 22694
|
||||
58: R_CAL<= 8 ; //22695 ~ 22734
|
||||
59: R_CAL<= 8 ; //22735 ~ 22774
|
||||
60: R_CAL<= 8 ; //22775 ~ 22814
|
||||
61: R_CAL<= 8 ; //22815 ~ 22854
|
||||
62: R_CAL<= 8 ; //22855 ~ 22894
|
||||
63: R_CAL<= 8 ; //22895 ~ 22934
|
||||
64: R_CAL<= 8 ; //22935 ~ 22974
|
||||
65: R_CAL<= 8 ; //22975 ~ 23014
|
||||
66: R_CAL<= 8 ; //23015 ~ 23054
|
||||
67: R_CAL<= 8 ; //23055 ~ 23094
|
||||
68: R_CAL<= 7 ; //23095 ~ 23134
|
||||
69: R_CAL<= 7 ; //23135 ~ 23174
|
||||
70: R_CAL<= 7 ; //23175 ~ 23214
|
||||
71: R_CAL<= 7 ; //23215 ~ 23254
|
||||
72: R_CAL<= 6 ; //23255 ~ 23294
|
||||
73: R_CAL<= 6 ; //23295 ~ 23334
|
||||
74: R_CAL<= 6 ; //23335 ~ 23374
|
||||
75: R_CAL<= 6 ; //23375 ~ 23414
|
||||
76: R_CAL<= 6 ; //23415 ~ 23454
|
||||
77: R_CAL<= 6 ; //23455 ~ 23494
|
||||
78: R_CAL<= 6 ; //23495 ~ 23534
|
||||
79: R_CAL<= 5 ; //23535 ~ 23574
|
||||
80: R_CAL<= 6 ; //23575 ~ 23614
|
||||
81: R_CAL<= 6 ; //23615 ~ 23654
|
||||
82: R_CAL<= 6 ; //23655 ~ 23694
|
||||
83: R_CAL<= 6 ; //23695 ~ 23734
|
||||
84: R_CAL<= 6 ; //23735 ~ 23774
|
||||
85: R_CAL<= 6 ; //23775 ~ 23814
|
||||
86: R_CAL<= 6 ; //23815 ~ 23854
|
||||
87: R_CAL<= 6 ; //23855 ~ 23875
|
||||
default:R_CAL<=R_CAL;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
+349
@@ -0,0 +1,349 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 17:05:24 04/08/2022
|
||||
// Design Name:
|
||||
// Module Name: R_CAL
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module R_CAL_2(
|
||||
input i_clk ,
|
||||
input i_rstn ,
|
||||
input signed[7:0] i_temp ,
|
||||
input [15:0] fre_mode ,
|
||||
output reg[3:0] R_CAL
|
||||
|
||||
);
|
||||
|
||||
|
||||
//接收通道2
|
||||
always@(posedge i_clk,negedge i_rstn)begin //1dB 步进
|
||||
if(!i_rstn)
|
||||
R_CAL<='d0;
|
||||
else if(i_temp>=8'sd70)begin//高温校准接收通道2
|
||||
case(fre_mode)
|
||||
0 : R_CAL<= 6 ; //20375 ~ 20414
|
||||
1 : R_CAL<= 6 ; //20415 ~ 20454
|
||||
2 : R_CAL<= 6 ; //20455 ~ 20494
|
||||
3 : R_CAL<= 5 ; //20495 ~ 20534
|
||||
4 : R_CAL<= 5 ; //20535 ~ 20574
|
||||
5 : R_CAL<= 5 ; //20575 ~ 20614
|
||||
6 : R_CAL<= 5 ; //20615 ~ 20654
|
||||
7 : R_CAL<= 5 ; //20655 ~ 20694
|
||||
8 : R_CAL<= 5 ; //20695 ~ 20734
|
||||
9 : R_CAL<= 5 ; //20735 ~ 20774
|
||||
10: R_CAL<= 5 ; //20775 ~ 20814
|
||||
11: R_CAL<= 5 ; //20815 ~ 20854
|
||||
12: R_CAL<= 5 ; //20855 ~ 20894
|
||||
13: R_CAL<= 5 ; //20895 ~ 20934
|
||||
14: R_CAL<= 5 ; //20935 ~ 20974
|
||||
15: R_CAL<= 6 ; //20975 ~ 21014
|
||||
16: R_CAL<= 6 ; //21015 ~ 21054
|
||||
17: R_CAL<= 6 ; //21055 ~ 21094
|
||||
18: R_CAL<= 6 ; //21095 ~ 21134
|
||||
19: R_CAL<= 6 ; //21135 ~ 21174
|
||||
20: R_CAL<= 6 ; //21175 ~ 21214
|
||||
21: R_CAL<= 7 ; //21215 ~ 21254
|
||||
22: R_CAL<= 7 ; //21255 ~ 21294
|
||||
23: R_CAL<= 7 ; //21295 ~ 21334
|
||||
24: R_CAL<= 8 ; //21335 ~ 21374
|
||||
25: R_CAL<= 8 ; //21375 ~ 21414
|
||||
26: R_CAL<= 8 ; //21415 ~ 21454
|
||||
27: R_CAL<= 8 ; //21455 ~ 21494
|
||||
28: R_CAL<= 8 ; //21495 ~ 21534
|
||||
29: R_CAL<= 8 ; //21535 ~ 21574
|
||||
30: R_CAL<= 8 ; //21575 ~ 21614
|
||||
31: R_CAL<= 8 ; //21615 ~ 21654
|
||||
32: R_CAL<= 8 ; //21655 ~ 21694
|
||||
33: R_CAL<= 8 ; //21695 ~ 21734
|
||||
34: R_CAL<= 8 ; //21735 ~ 21774
|
||||
35: R_CAL<= 8 ; //21775 ~ 21814
|
||||
36: R_CAL<= 8 ; //21815 ~ 21854
|
||||
37: R_CAL<= 8 ; //21855 ~ 21894
|
||||
38: R_CAL<= 7 ; //21895 ~ 21934
|
||||
39: R_CAL<= 7 ; //21935 ~ 21974
|
||||
40: R_CAL<= 7 ; //21975 ~ 22014
|
||||
41: R_CAL<= 7 ; //22015 ~ 22054
|
||||
42: R_CAL<= 7 ; //22055 ~ 22094
|
||||
43: R_CAL<= 7 ; //22095 ~ 22134
|
||||
44: R_CAL<= 7 ; //22135 ~ 22174
|
||||
45: R_CAL<= 7 ; //22175 ~ 22214
|
||||
46: R_CAL<= 7 ; //22215 ~ 22254
|
||||
47: R_CAL<= 7 ; //22255 ~ 22294
|
||||
48: R_CAL<= 7 ; //22295 ~ 22334
|
||||
49: R_CAL<= 7 ; //22335 ~ 22374
|
||||
50: R_CAL<= 7 ; //22375 ~ 22414
|
||||
51: R_CAL<= 7 ; //22415 ~ 22454
|
||||
52: R_CAL<= 7 ; //22455 ~ 22494
|
||||
53: R_CAL<= 7 ; //22495 ~ 22534
|
||||
54: R_CAL<= 7 ; //22535 ~ 22574
|
||||
55: R_CAL<= 7 ; //22575 ~ 22614
|
||||
56: R_CAL<= 7 ; //22615 ~ 22654
|
||||
57: R_CAL<= 7 ; //22655 ~ 22694
|
||||
58: R_CAL<= 7 ; //22695 ~ 22734
|
||||
59: R_CAL<= 7 ; //22735 ~ 22774
|
||||
60: R_CAL<= 7 ; //22775 ~ 22814
|
||||
61: R_CAL<= 7 ; //22815 ~ 22854
|
||||
62: R_CAL<= 7 ; //22855 ~ 22894
|
||||
63: R_CAL<= 8 ; //22895 ~ 22934
|
||||
64: R_CAL<= 8 ; //22935 ~ 22974
|
||||
65: R_CAL<= 8 ; //22975 ~ 23014
|
||||
66: R_CAL<= 8 ; //23015 ~ 23054
|
||||
67: R_CAL<= 7 ; //23055 ~ 23094
|
||||
68: R_CAL<= 7 ; //23095 ~ 23134
|
||||
69: R_CAL<= 7 ; //23135 ~ 23174
|
||||
70: R_CAL<= 7 ; //23175 ~ 23214
|
||||
71: R_CAL<= 7 ; //23215 ~ 23254
|
||||
72: R_CAL<= 7 ; //23255 ~ 23294
|
||||
73: R_CAL<= 6 ; //23295 ~ 23334
|
||||
74: R_CAL<= 6 ; //23335 ~ 23374
|
||||
75: R_CAL<= 6 ; //23375 ~ 23414
|
||||
76: R_CAL<= 6 ; //23415 ~ 23454
|
||||
77: R_CAL<= 6 ; //23455 ~ 23494
|
||||
78: R_CAL<= 5 ; //23495 ~ 23534
|
||||
79: R_CAL<= 5 ; //23535 ~ 23574
|
||||
80: R_CAL<= 6 ; //23575 ~ 23614
|
||||
81: R_CAL<= 5 ; //23615 ~ 23654
|
||||
82: R_CAL<= 5 ; //23655 ~ 23694
|
||||
83: R_CAL<= 6 ; //23695 ~ 23734
|
||||
84: R_CAL<= 5 ; //23735 ~ 23774
|
||||
85: R_CAL<= 6 ; //23775 ~ 23814
|
||||
86: R_CAL<= 6 ; //23815 ~ 23854
|
||||
87: R_CAL<= 6 ; //23855 ~ 23875
|
||||
default:R_CAL<=R_CAL;
|
||||
endcase
|
||||
end
|
||||
|
||||
else if(i_temp>=8'sd0)begin//常温校准接收通道2
|
||||
case(fre_mode)
|
||||
0 : R_CAL<= 6 ; //20375 ~ 20414
|
||||
1 : R_CAL<= 6 ; //20415 ~ 20454
|
||||
2 : R_CAL<= 6 ; //20455 ~ 20494
|
||||
3 : R_CAL<= 5 ; //20495 ~ 20534
|
||||
4 : R_CAL<= 5 ; //20535 ~ 20574
|
||||
5 : R_CAL<= 5 ; //20575 ~ 20614
|
||||
6 : R_CAL<= 5 ; //20615 ~ 20654
|
||||
7 : R_CAL<= 5 ; //20655 ~ 20694
|
||||
8 : R_CAL<= 5 ; //20695 ~ 20734
|
||||
9 : R_CAL<= 5 ; //20735 ~ 20774
|
||||
10: R_CAL<= 5 ; //20775 ~ 20814
|
||||
11: R_CAL<= 5 ; //20815 ~ 20854
|
||||
12: R_CAL<= 5 ; //20855 ~ 20894
|
||||
13: R_CAL<= 5 ; //20895 ~ 20934
|
||||
14: R_CAL<= 5 ; //20935 ~ 20974
|
||||
15: R_CAL<= 6 ; //20975 ~ 21014
|
||||
16: R_CAL<= 6 ; //21015 ~ 21054
|
||||
17: R_CAL<= 6 ; //21055 ~ 21094
|
||||
18: R_CAL<= 6 ; //21095 ~ 21134
|
||||
19: R_CAL<= 6 ; //21135 ~ 21174
|
||||
20: R_CAL<= 6 ; //21175 ~ 21214
|
||||
21: R_CAL<= 7 ; //21215 ~ 21254
|
||||
22: R_CAL<= 7 ; //21255 ~ 21294
|
||||
23: R_CAL<= 7 ; //21295 ~ 21334
|
||||
24: R_CAL<= 8 ; //21335 ~ 21374
|
||||
25: R_CAL<= 8 ; //21375 ~ 21414
|
||||
26: R_CAL<= 8 ; //21415 ~ 21454
|
||||
27: R_CAL<= 8 ; //21455 ~ 21494
|
||||
28: R_CAL<= 8 ; //21495 ~ 21534
|
||||
29: R_CAL<= 8 ; //21535 ~ 21574
|
||||
30: R_CAL<= 8 ; //21575 ~ 21614
|
||||
31: R_CAL<= 8 ; //21615 ~ 21654
|
||||
32: R_CAL<= 8 ; //21655 ~ 21694
|
||||
33: R_CAL<= 8 ; //21695 ~ 21734
|
||||
34: R_CAL<= 8 ; //21735 ~ 21774
|
||||
35: R_CAL<= 8 ; //21775 ~ 21814
|
||||
36: R_CAL<= 8 ; //21815 ~ 21854
|
||||
37: R_CAL<= 8 ; //21855 ~ 21894
|
||||
38: R_CAL<= 7 ; //21895 ~ 21934
|
||||
39: R_CAL<= 7 ; //21935 ~ 21974
|
||||
40: R_CAL<= 7 ; //21975 ~ 22014
|
||||
41: R_CAL<= 7 ; //22015 ~ 22054
|
||||
42: R_CAL<= 7 ; //22055 ~ 22094
|
||||
43: R_CAL<= 7 ; //22095 ~ 22134
|
||||
44: R_CAL<= 7 ; //22135 ~ 22174
|
||||
45: R_CAL<= 7 ; //22175 ~ 22214
|
||||
46: R_CAL<= 7 ; //22215 ~ 22254
|
||||
47: R_CAL<= 7 ; //22255 ~ 22294
|
||||
48: R_CAL<= 7 ; //22295 ~ 22334
|
||||
49: R_CAL<= 7 ; //22335 ~ 22374
|
||||
50: R_CAL<= 7 ; //22375 ~ 22414
|
||||
51: R_CAL<= 7 ; //22415 ~ 22454
|
||||
52: R_CAL<= 7 ; //22455 ~ 22494
|
||||
53: R_CAL<= 7 ; //22495 ~ 22534
|
||||
54: R_CAL<= 7 ; //22535 ~ 22574
|
||||
55: R_CAL<= 7 ; //22575 ~ 22614
|
||||
56: R_CAL<= 7 ; //22615 ~ 22654
|
||||
57: R_CAL<= 7 ; //22655 ~ 22694
|
||||
58: R_CAL<= 7 ; //22695 ~ 22734
|
||||
59: R_CAL<= 7 ; //22735 ~ 22774
|
||||
60: R_CAL<= 7 ; //22775 ~ 22814
|
||||
61: R_CAL<= 7 ; //22815 ~ 22854
|
||||
62: R_CAL<= 7 ; //22855 ~ 22894
|
||||
63: R_CAL<= 8 ; //22895 ~ 22934
|
||||
64: R_CAL<= 8 ; //22935 ~ 22974
|
||||
65: R_CAL<= 8 ; //22975 ~ 23014
|
||||
66: R_CAL<= 8 ; //23015 ~ 23054
|
||||
67: R_CAL<= 7 ; //23055 ~ 23094
|
||||
68: R_CAL<= 7 ; //23095 ~ 23134
|
||||
69: R_CAL<= 7 ; //23135 ~ 23174
|
||||
70: R_CAL<= 7 ; //23175 ~ 23214
|
||||
71: R_CAL<= 7 ; //23215 ~ 23254
|
||||
72: R_CAL<= 7 ; //23255 ~ 23294
|
||||
73: R_CAL<= 6 ; //23295 ~ 23334
|
||||
74: R_CAL<= 6 ; //23335 ~ 23374
|
||||
75: R_CAL<= 6 ; //23375 ~ 23414
|
||||
76: R_CAL<= 6 ; //23415 ~ 23454
|
||||
77: R_CAL<= 6 ; //23455 ~ 23494
|
||||
78: R_CAL<= 5 ; //23495 ~ 23534
|
||||
79: R_CAL<= 5 ; //23535 ~ 23574
|
||||
80: R_CAL<= 6 ; //23575 ~ 23614
|
||||
81: R_CAL<= 5 ; //23615 ~ 23654
|
||||
82: R_CAL<= 5 ; //23655 ~ 23694
|
||||
83: R_CAL<= 6 ; //23695 ~ 23734
|
||||
84: R_CAL<= 5 ; //23735 ~ 23774
|
||||
85: R_CAL<= 6 ; //23775 ~ 23814
|
||||
86: R_CAL<= 6 ; //23815 ~ 23854
|
||||
87: R_CAL<= 6 ; //23855 ~ 23875
|
||||
default:R_CAL<=R_CAL;
|
||||
endcase
|
||||
end
|
||||
else begin//低温校准接收通道2
|
||||
case(fre_mode)
|
||||
0 : R_CAL<= 6 ; //20375 ~ 20414
|
||||
1 : R_CAL<= 6 ; //20415 ~ 20454
|
||||
2 : R_CAL<= 6 ; //20455 ~ 20494
|
||||
3 : R_CAL<= 5 ; //20495 ~ 20534
|
||||
4 : R_CAL<= 5 ; //20535 ~ 20574
|
||||
5 : R_CAL<= 5 ; //20575 ~ 20614
|
||||
6 : R_CAL<= 5 ; //20615 ~ 20654
|
||||
7 : R_CAL<= 5 ; //20655 ~ 20694
|
||||
8 : R_CAL<= 5 ; //20695 ~ 20734
|
||||
9 : R_CAL<= 5 ; //20735 ~ 20774
|
||||
10: R_CAL<= 5 ; //20775 ~ 20814
|
||||
11: R_CAL<= 5 ; //20815 ~ 20854
|
||||
12: R_CAL<= 5 ; //20855 ~ 20894
|
||||
13: R_CAL<= 5 ; //20895 ~ 20934
|
||||
14: R_CAL<= 5 ; //20935 ~ 20974
|
||||
15: R_CAL<= 6 ; //20975 ~ 21014
|
||||
16: R_CAL<= 6 ; //21015 ~ 21054
|
||||
17: R_CAL<= 6 ; //21055 ~ 21094
|
||||
18: R_CAL<= 6 ; //21095 ~ 21134
|
||||
19: R_CAL<= 6 ; //21135 ~ 21174
|
||||
20: R_CAL<= 6 ; //21175 ~ 21214
|
||||
21: R_CAL<= 7 ; //21215 ~ 21254
|
||||
22: R_CAL<= 7 ; //21255 ~ 21294
|
||||
23: R_CAL<= 7 ; //21295 ~ 21334
|
||||
24: R_CAL<= 8 ; //21335 ~ 21374
|
||||
25: R_CAL<= 8 ; //21375 ~ 21414
|
||||
26: R_CAL<= 8 ; //21415 ~ 21454
|
||||
27: R_CAL<= 8 ; //21455 ~ 21494
|
||||
28: R_CAL<= 8 ; //21495 ~ 21534
|
||||
29: R_CAL<= 8 ; //21535 ~ 21574
|
||||
30: R_CAL<= 8 ; //21575 ~ 21614
|
||||
31: R_CAL<= 8 ; //21615 ~ 21654
|
||||
32: R_CAL<= 8 ; //21655 ~ 21694
|
||||
33: R_CAL<= 8 ; //21695 ~ 21734
|
||||
34: R_CAL<= 8 ; //21735 ~ 21774
|
||||
35: R_CAL<= 8 ; //21775 ~ 21814
|
||||
36: R_CAL<= 8 ; //21815 ~ 21854
|
||||
37: R_CAL<= 8 ; //21855 ~ 21894
|
||||
38: R_CAL<= 7 ; //21895 ~ 21934
|
||||
39: R_CAL<= 7 ; //21935 ~ 21974
|
||||
40: R_CAL<= 7 ; //21975 ~ 22014
|
||||
41: R_CAL<= 7 ; //22015 ~ 22054
|
||||
42: R_CAL<= 7 ; //22055 ~ 22094
|
||||
43: R_CAL<= 7 ; //22095 ~ 22134
|
||||
44: R_CAL<= 7 ; //22135 ~ 22174
|
||||
45: R_CAL<= 7 ; //22175 ~ 22214
|
||||
46: R_CAL<= 7 ; //22215 ~ 22254
|
||||
47: R_CAL<= 7 ; //22255 ~ 22294
|
||||
48: R_CAL<= 7 ; //22295 ~ 22334
|
||||
49: R_CAL<= 7 ; //22335 ~ 22374
|
||||
50: R_CAL<= 7 ; //22375 ~ 22414
|
||||
51: R_CAL<= 7 ; //22415 ~ 22454
|
||||
52: R_CAL<= 7 ; //22455 ~ 22494
|
||||
53: R_CAL<= 7 ; //22495 ~ 22534
|
||||
54: R_CAL<= 7 ; //22535 ~ 22574
|
||||
55: R_CAL<= 7 ; //22575 ~ 22614
|
||||
56: R_CAL<= 7 ; //22615 ~ 22654
|
||||
57: R_CAL<= 7 ; //22655 ~ 22694
|
||||
58: R_CAL<= 7 ; //22695 ~ 22734
|
||||
59: R_CAL<= 7 ; //22735 ~ 22774
|
||||
60: R_CAL<= 7 ; //22775 ~ 22814
|
||||
61: R_CAL<= 7 ; //22815 ~ 22854
|
||||
62: R_CAL<= 7 ; //22855 ~ 22894
|
||||
63: R_CAL<= 8 ; //22895 ~ 22934
|
||||
64: R_CAL<= 8 ; //22935 ~ 22974
|
||||
65: R_CAL<= 8 ; //22975 ~ 23014
|
||||
66: R_CAL<= 8 ; //23015 ~ 23054
|
||||
67: R_CAL<= 7 ; //23055 ~ 23094
|
||||
68: R_CAL<= 7 ; //23095 ~ 23134
|
||||
69: R_CAL<= 7 ; //23135 ~ 23174
|
||||
70: R_CAL<= 7 ; //23175 ~ 23214
|
||||
71: R_CAL<= 7 ; //23215 ~ 23254
|
||||
72: R_CAL<= 7 ; //23255 ~ 23294
|
||||
73: R_CAL<= 6 ; //23295 ~ 23334
|
||||
74: R_CAL<= 6 ; //23335 ~ 23374
|
||||
75: R_CAL<= 6 ; //23375 ~ 23414
|
||||
76: R_CAL<= 6 ; //23415 ~ 23454
|
||||
77: R_CAL<= 6 ; //23455 ~ 23494
|
||||
78: R_CAL<= 5 ; //23495 ~ 23534
|
||||
79: R_CAL<= 5 ; //23535 ~ 23574
|
||||
80: R_CAL<= 6 ; //23575 ~ 23614
|
||||
81: R_CAL<= 5 ; //23615 ~ 23654
|
||||
82: R_CAL<= 5 ; //23655 ~ 23694
|
||||
83: R_CAL<= 6 ; //23695 ~ 23734
|
||||
84: R_CAL<= 5 ; //23735 ~ 23774
|
||||
85: R_CAL<= 6 ; //23775 ~ 23814
|
||||
86: R_CAL<= 6 ; //23815 ~ 23854
|
||||
87: R_CAL<= 6 ; //23855 ~ 23875
|
||||
default:R_CAL<=R_CAL;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
+348
@@ -0,0 +1,348 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 17:05:24 04/08/2022
|
||||
// Design Name:
|
||||
// Module Name: R_CAL
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module R_CAL_3(
|
||||
input i_clk ,
|
||||
input i_rstn ,
|
||||
input signed[7:0] i_temp ,
|
||||
input [15:0] fre_mode ,
|
||||
output reg[3:0] R_CAL
|
||||
|
||||
);
|
||||
|
||||
//接收通道3
|
||||
always@(posedge i_clk,negedge i_rstn)begin //1dB 步进
|
||||
if(!i_rstn)
|
||||
R_CAL<='d0;
|
||||
else if(i_temp>=8'sd70)begin//高温校准接收通道3
|
||||
case(fre_mode)
|
||||
0 : R_CAL<= 7 ; //20375 ~ 20414
|
||||
1 : R_CAL<= 7 ; //20415 ~ 20454
|
||||
2 : R_CAL<= 7 ; //20455 ~ 20494
|
||||
3 : R_CAL<= 7 ; //20495 ~ 20534
|
||||
4 : R_CAL<= 7 ; //20535 ~ 20574
|
||||
5 : R_CAL<= 7 ; //20575 ~ 20614
|
||||
6 : R_CAL<= 6 ; //20615 ~ 20654
|
||||
7 : R_CAL<= 6 ; //20655 ~ 20694
|
||||
8 : R_CAL<= 6 ; //20695 ~ 20734
|
||||
9 : R_CAL<= 6 ; //20735 ~ 20774
|
||||
10: R_CAL<= 6 ; //20775 ~ 20814
|
||||
11: R_CAL<= 6 ; //20815 ~ 20854
|
||||
12: R_CAL<= 6 ; //20855 ~ 20894
|
||||
13: R_CAL<= 6 ; //20895 ~ 20934
|
||||
14: R_CAL<= 6 ; //20935 ~ 20974
|
||||
15: R_CAL<= 6 ; //20975 ~ 21014
|
||||
16: R_CAL<= 6 ; //21015 ~ 21054
|
||||
17: R_CAL<= 7 ; //21055 ~ 21094
|
||||
18: R_CAL<= 7 ; //21095 ~ 21134
|
||||
19: R_CAL<= 7 ; //21135 ~ 21174
|
||||
20: R_CAL<= 8 ; //21175 ~ 21214
|
||||
21: R_CAL<= 8 ; //21215 ~ 21254
|
||||
22: R_CAL<= 8 ; //21255 ~ 21294
|
||||
23: R_CAL<= 8 ; //21295 ~ 21334
|
||||
24: R_CAL<= 8 ; //21335 ~ 21374
|
||||
25: R_CAL<= 8 ; //21375 ~ 21414
|
||||
26: R_CAL<= 9 ; //21415 ~ 21454
|
||||
27: R_CAL<= 9 ; //21455 ~ 21494
|
||||
28: R_CAL<= 9 ; //21495 ~ 21534
|
||||
29: R_CAL<= 9 ; //21535 ~ 21574
|
||||
30: R_CAL<= 9 ; //21575 ~ 21614
|
||||
31: R_CAL<= 9 ; //21615 ~ 21654
|
||||
32: R_CAL<= 9 ; //21655 ~ 21694
|
||||
33: R_CAL<= 9 ; //21695 ~ 21734
|
||||
34: R_CAL<= 9 ; //21735 ~ 21774
|
||||
35: R_CAL<= 9 ; //21775 ~ 21814
|
||||
36: R_CAL<= 9 ; //21815 ~ 21854
|
||||
37: R_CAL<= 9 ; //21855 ~ 21894
|
||||
38: R_CAL<= 9 ; //21895 ~ 21934
|
||||
39: R_CAL<= 9 ; //21935 ~ 21974
|
||||
40: R_CAL<= 8 ; //21975 ~ 22014
|
||||
41: R_CAL<= 8 ; //22015 ~ 22054
|
||||
42: R_CAL<= 8 ; //22055 ~ 22094
|
||||
43: R_CAL<= 8 ; //22095 ~ 22134
|
||||
44: R_CAL<= 8 ; //22135 ~ 22174
|
||||
45: R_CAL<= 8 ; //22175 ~ 22214
|
||||
46: R_CAL<= 8 ; //22215 ~ 22254
|
||||
47: R_CAL<= 8 ; //22255 ~ 22294
|
||||
48: R_CAL<= 8 ; //22295 ~ 22334
|
||||
49: R_CAL<= 8 ; //22335 ~ 22374
|
||||
50: R_CAL<= 8 ; //22375 ~ 22414
|
||||
51: R_CAL<= 8 ; //22415 ~ 22454
|
||||
52: R_CAL<= 8 ; //22455 ~ 22494
|
||||
53: R_CAL<= 8 ; //22495 ~ 22534
|
||||
54: R_CAL<= 8 ; //22535 ~ 22574
|
||||
55: R_CAL<= 8 ; //22575 ~ 22614
|
||||
56: R_CAL<= 8 ; //22615 ~ 22654
|
||||
57: R_CAL<= 8 ; //22655 ~ 22694
|
||||
58: R_CAL<= 8 ; //22695 ~ 22734
|
||||
59: R_CAL<= 8 ; //22735 ~ 22774
|
||||
60: R_CAL<= 8 ; //22775 ~ 22814
|
||||
61: R_CAL<= 8 ; //22815 ~ 22854
|
||||
62: R_CAL<= 8 ; //22855 ~ 22894
|
||||
63: R_CAL<= 9 ; //22895 ~ 22934
|
||||
64: R_CAL<= 9 ; //22935 ~ 22974
|
||||
65: R_CAL<= 9 ; //22975 ~ 23014
|
||||
66: R_CAL<= 9 ; //23015 ~ 23054
|
||||
67: R_CAL<= 9 ; //23055 ~ 23094
|
||||
68: R_CAL<= 8 ; //23095 ~ 23134
|
||||
69: R_CAL<= 8 ; //23135 ~ 23174
|
||||
70: R_CAL<= 8 ; //23175 ~ 23214
|
||||
71: R_CAL<= 8 ; //23215 ~ 23254
|
||||
72: R_CAL<= 8 ; //23255 ~ 23294
|
||||
73: R_CAL<= 7 ; //23295 ~ 23334
|
||||
74: R_CAL<= 7 ; //23335 ~ 23374
|
||||
75: R_CAL<= 7 ; //23375 ~ 23414
|
||||
76: R_CAL<= 7 ; //23415 ~ 23454
|
||||
77: R_CAL<= 7 ; //23455 ~ 23494
|
||||
78: R_CAL<= 7 ; //23495 ~ 23534
|
||||
79: R_CAL<= 7 ; //23535 ~ 23574
|
||||
80: R_CAL<= 7 ; //23575 ~ 23614
|
||||
81: R_CAL<= 7 ; //23615 ~ 23654
|
||||
82: R_CAL<= 7 ; //23655 ~ 23694
|
||||
83: R_CAL<= 7 ; //23695 ~ 23734
|
||||
84: R_CAL<= 7 ; //23735 ~ 23774
|
||||
85: R_CAL<= 7 ; //23775 ~ 23814
|
||||
86: R_CAL<= 7 ; //23815 ~ 23854
|
||||
87: R_CAL<= 7 ; //23855 ~ 23875
|
||||
default:R_CAL<=R_CAL;
|
||||
endcase
|
||||
end
|
||||
|
||||
else if(i_temp>=8'sd0)begin//常温校准接收通道3
|
||||
case(fre_mode)
|
||||
0 : R_CAL<= 7 ; //20375 ~ 20414
|
||||
1 : R_CAL<= 7 ; //20415 ~ 20454
|
||||
2 : R_CAL<= 7 ; //20455 ~ 20494
|
||||
3 : R_CAL<= 7 ; //20495 ~ 20534
|
||||
4 : R_CAL<= 7 ; //20535 ~ 20574
|
||||
5 : R_CAL<= 7 ; //20575 ~ 20614
|
||||
6 : R_CAL<= 6 ; //20615 ~ 20654
|
||||
7 : R_CAL<= 6 ; //20655 ~ 20694
|
||||
8 : R_CAL<= 6 ; //20695 ~ 20734
|
||||
9 : R_CAL<= 6 ; //20735 ~ 20774
|
||||
10: R_CAL<= 6 ; //20775 ~ 20814
|
||||
11: R_CAL<= 6 ; //20815 ~ 20854
|
||||
12: R_CAL<= 6 ; //20855 ~ 20894
|
||||
13: R_CAL<= 6 ; //20895 ~ 20934
|
||||
14: R_CAL<= 6 ; //20935 ~ 20974
|
||||
15: R_CAL<= 6 ; //20975 ~ 21014
|
||||
16: R_CAL<= 6 ; //21015 ~ 21054
|
||||
17: R_CAL<= 7 ; //21055 ~ 21094
|
||||
18: R_CAL<= 7 ; //21095 ~ 21134
|
||||
19: R_CAL<= 7 ; //21135 ~ 21174
|
||||
20: R_CAL<= 8 ; //21175 ~ 21214
|
||||
21: R_CAL<= 8 ; //21215 ~ 21254
|
||||
22: R_CAL<= 8 ; //21255 ~ 21294
|
||||
23: R_CAL<= 8 ; //21295 ~ 21334
|
||||
24: R_CAL<= 8 ; //21335 ~ 21374
|
||||
25: R_CAL<= 8 ; //21375 ~ 21414
|
||||
26: R_CAL<= 9 ; //21415 ~ 21454
|
||||
27: R_CAL<= 9 ; //21455 ~ 21494
|
||||
28: R_CAL<= 9 ; //21495 ~ 21534
|
||||
29: R_CAL<= 9 ; //21535 ~ 21574
|
||||
30: R_CAL<= 9 ; //21575 ~ 21614
|
||||
31: R_CAL<= 9 ; //21615 ~ 21654
|
||||
32: R_CAL<= 9 ; //21655 ~ 21694
|
||||
33: R_CAL<= 9 ; //21695 ~ 21734
|
||||
34: R_CAL<= 9 ; //21735 ~ 21774
|
||||
35: R_CAL<= 9 ; //21775 ~ 21814
|
||||
36: R_CAL<= 9 ; //21815 ~ 21854
|
||||
37: R_CAL<= 9 ; //21855 ~ 21894
|
||||
38: R_CAL<= 9 ; //21895 ~ 21934
|
||||
39: R_CAL<= 9 ; //21935 ~ 21974
|
||||
40: R_CAL<= 8 ; //21975 ~ 22014
|
||||
41: R_CAL<= 8 ; //22015 ~ 22054
|
||||
42: R_CAL<= 8 ; //22055 ~ 22094
|
||||
43: R_CAL<= 8 ; //22095 ~ 22134
|
||||
44: R_CAL<= 8 ; //22135 ~ 22174
|
||||
45: R_CAL<= 8 ; //22175 ~ 22214
|
||||
46: R_CAL<= 8 ; //22215 ~ 22254
|
||||
47: R_CAL<= 8 ; //22255 ~ 22294
|
||||
48: R_CAL<= 8 ; //22295 ~ 22334
|
||||
49: R_CAL<= 8 ; //22335 ~ 22374
|
||||
50: R_CAL<= 8 ; //22375 ~ 22414
|
||||
51: R_CAL<= 8 ; //22415 ~ 22454
|
||||
52: R_CAL<= 8 ; //22455 ~ 22494
|
||||
53: R_CAL<= 8 ; //22495 ~ 22534
|
||||
54: R_CAL<= 8 ; //22535 ~ 22574
|
||||
55: R_CAL<= 8 ; //22575 ~ 22614
|
||||
56: R_CAL<= 8 ; //22615 ~ 22654
|
||||
57: R_CAL<= 8 ; //22655 ~ 22694
|
||||
58: R_CAL<= 8 ; //22695 ~ 22734
|
||||
59: R_CAL<= 8 ; //22735 ~ 22774
|
||||
60: R_CAL<= 8 ; //22775 ~ 22814
|
||||
61: R_CAL<= 8 ; //22815 ~ 22854
|
||||
62: R_CAL<= 8 ; //22855 ~ 22894
|
||||
63: R_CAL<= 9 ; //22895 ~ 22934
|
||||
64: R_CAL<= 9 ; //22935 ~ 22974
|
||||
65: R_CAL<= 9 ; //22975 ~ 23014
|
||||
66: R_CAL<= 9 ; //23015 ~ 23054
|
||||
67: R_CAL<= 9 ; //23055 ~ 23094
|
||||
68: R_CAL<= 8 ; //23095 ~ 23134
|
||||
69: R_CAL<= 8 ; //23135 ~ 23174
|
||||
70: R_CAL<= 8 ; //23175 ~ 23214
|
||||
71: R_CAL<= 8 ; //23215 ~ 23254
|
||||
72: R_CAL<= 8 ; //23255 ~ 23294
|
||||
73: R_CAL<= 7 ; //23295 ~ 23334
|
||||
74: R_CAL<= 7 ; //23335 ~ 23374
|
||||
75: R_CAL<= 7 ; //23375 ~ 23414
|
||||
76: R_CAL<= 7 ; //23415 ~ 23454
|
||||
77: R_CAL<= 7 ; //23455 ~ 23494
|
||||
78: R_CAL<= 7 ; //23495 ~ 23534
|
||||
79: R_CAL<= 7 ; //23535 ~ 23574
|
||||
80: R_CAL<= 7 ; //23575 ~ 23614
|
||||
81: R_CAL<= 7 ; //23615 ~ 23654
|
||||
82: R_CAL<= 7 ; //23655 ~ 23694
|
||||
83: R_CAL<= 7 ; //23695 ~ 23734
|
||||
84: R_CAL<= 7 ; //23735 ~ 23774
|
||||
85: R_CAL<= 7 ; //23775 ~ 23814
|
||||
86: R_CAL<= 7 ; //23815 ~ 23854
|
||||
87: R_CAL<= 7 ; //23855 ~ 23875
|
||||
default:R_CAL<=R_CAL;
|
||||
endcase
|
||||
end
|
||||
else begin//低温校准接收通道3
|
||||
case(fre_mode)
|
||||
0 : R_CAL<= 7 ; //20375 ~ 20414
|
||||
1 : R_CAL<= 7 ; //20415 ~ 20454
|
||||
2 : R_CAL<= 7 ; //20455 ~ 20494
|
||||
3 : R_CAL<= 7 ; //20495 ~ 20534
|
||||
4 : R_CAL<= 7 ; //20535 ~ 20574
|
||||
5 : R_CAL<= 7 ; //20575 ~ 20614
|
||||
6 : R_CAL<= 6 ; //20615 ~ 20654
|
||||
7 : R_CAL<= 6 ; //20655 ~ 20694
|
||||
8 : R_CAL<= 6 ; //20695 ~ 20734
|
||||
9 : R_CAL<= 6 ; //20735 ~ 20774
|
||||
10: R_CAL<= 6 ; //20775 ~ 20814
|
||||
11: R_CAL<= 6 ; //20815 ~ 20854
|
||||
12: R_CAL<= 6 ; //20855 ~ 20894
|
||||
13: R_CAL<= 6 ; //20895 ~ 20934
|
||||
14: R_CAL<= 6 ; //20935 ~ 20974
|
||||
15: R_CAL<= 6 ; //20975 ~ 21014
|
||||
16: R_CAL<= 6 ; //21015 ~ 21054
|
||||
17: R_CAL<= 7 ; //21055 ~ 21094
|
||||
18: R_CAL<= 7 ; //21095 ~ 21134
|
||||
19: R_CAL<= 7 ; //21135 ~ 21174
|
||||
20: R_CAL<= 8 ; //21175 ~ 21214
|
||||
21: R_CAL<= 8 ; //21215 ~ 21254
|
||||
22: R_CAL<= 8 ; //21255 ~ 21294
|
||||
23: R_CAL<= 8 ; //21295 ~ 21334
|
||||
24: R_CAL<= 8 ; //21335 ~ 21374
|
||||
25: R_CAL<= 8 ; //21375 ~ 21414
|
||||
26: R_CAL<= 9 ; //21415 ~ 21454
|
||||
27: R_CAL<= 9 ; //21455 ~ 21494
|
||||
28: R_CAL<= 9 ; //21495 ~ 21534
|
||||
29: R_CAL<= 9 ; //21535 ~ 21574
|
||||
30: R_CAL<= 9 ; //21575 ~ 21614
|
||||
31: R_CAL<= 9 ; //21615 ~ 21654
|
||||
32: R_CAL<= 9 ; //21655 ~ 21694
|
||||
33: R_CAL<= 9 ; //21695 ~ 21734
|
||||
34: R_CAL<= 9 ; //21735 ~ 21774
|
||||
35: R_CAL<= 9 ; //21775 ~ 21814
|
||||
36: R_CAL<= 9 ; //21815 ~ 21854
|
||||
37: R_CAL<= 9 ; //21855 ~ 21894
|
||||
38: R_CAL<= 9 ; //21895 ~ 21934
|
||||
39: R_CAL<= 9 ; //21935 ~ 21974
|
||||
40: R_CAL<= 8 ; //21975 ~ 22014
|
||||
41: R_CAL<= 8 ; //22015 ~ 22054
|
||||
42: R_CAL<= 8 ; //22055 ~ 22094
|
||||
43: R_CAL<= 8 ; //22095 ~ 22134
|
||||
44: R_CAL<= 8 ; //22135 ~ 22174
|
||||
45: R_CAL<= 8 ; //22175 ~ 22214
|
||||
46: R_CAL<= 8 ; //22215 ~ 22254
|
||||
47: R_CAL<= 8 ; //22255 ~ 22294
|
||||
48: R_CAL<= 8 ; //22295 ~ 22334
|
||||
49: R_CAL<= 8 ; //22335 ~ 22374
|
||||
50: R_CAL<= 8 ; //22375 ~ 22414
|
||||
51: R_CAL<= 8 ; //22415 ~ 22454
|
||||
52: R_CAL<= 8 ; //22455 ~ 22494
|
||||
53: R_CAL<= 8 ; //22495 ~ 22534
|
||||
54: R_CAL<= 8 ; //22535 ~ 22574
|
||||
55: R_CAL<= 8 ; //22575 ~ 22614
|
||||
56: R_CAL<= 8 ; //22615 ~ 22654
|
||||
57: R_CAL<= 8 ; //22655 ~ 22694
|
||||
58: R_CAL<= 8 ; //22695 ~ 22734
|
||||
59: R_CAL<= 8 ; //22735 ~ 22774
|
||||
60: R_CAL<= 8 ; //22775 ~ 22814
|
||||
61: R_CAL<= 8 ; //22815 ~ 22854
|
||||
62: R_CAL<= 8 ; //22855 ~ 22894
|
||||
63: R_CAL<= 9 ; //22895 ~ 22934
|
||||
64: R_CAL<= 9 ; //22935 ~ 22974
|
||||
65: R_CAL<= 9 ; //22975 ~ 23014
|
||||
66: R_CAL<= 9 ; //23015 ~ 23054
|
||||
67: R_CAL<= 9 ; //23055 ~ 23094
|
||||
68: R_CAL<= 8 ; //23095 ~ 23134
|
||||
69: R_CAL<= 8 ; //23135 ~ 23174
|
||||
70: R_CAL<= 8 ; //23175 ~ 23214
|
||||
71: R_CAL<= 8 ; //23215 ~ 23254
|
||||
72: R_CAL<= 8 ; //23255 ~ 23294
|
||||
73: R_CAL<= 7 ; //23295 ~ 23334
|
||||
74: R_CAL<= 7 ; //23335 ~ 23374
|
||||
75: R_CAL<= 7 ; //23375 ~ 23414
|
||||
76: R_CAL<= 7 ; //23415 ~ 23454
|
||||
77: R_CAL<= 7 ; //23455 ~ 23494
|
||||
78: R_CAL<= 7 ; //23495 ~ 23534
|
||||
79: R_CAL<= 7 ; //23535 ~ 23574
|
||||
80: R_CAL<= 7 ; //23575 ~ 23614
|
||||
81: R_CAL<= 7 ; //23615 ~ 23654
|
||||
82: R_CAL<= 7 ; //23655 ~ 23694
|
||||
83: R_CAL<= 7 ; //23695 ~ 23734
|
||||
84: R_CAL<= 7 ; //23735 ~ 23774
|
||||
85: R_CAL<= 7 ; //23775 ~ 23814
|
||||
86: R_CAL<= 7 ; //23815 ~ 23854
|
||||
87: R_CAL<= 7 ; //23855 ~ 23875
|
||||
default:R_CAL<=R_CAL;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
+349
@@ -0,0 +1,349 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 17:05:24 04/08/2022
|
||||
// Design Name:
|
||||
// Module Name: R_CAL
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module R_CAL_4(
|
||||
input i_clk ,
|
||||
input i_rstn ,
|
||||
input signed[7:0] i_temp ,
|
||||
input [15:0] fre_mode ,
|
||||
output reg[3:0] R_CAL
|
||||
|
||||
);
|
||||
|
||||
|
||||
//接收通道4
|
||||
always@(posedge i_clk,negedge i_rstn)begin //1dB 步进
|
||||
if(!i_rstn)
|
||||
R_CAL<='d0;
|
||||
else if(i_temp>=8'sd70)begin//高温校准接收通道4
|
||||
case(fre_mode)
|
||||
0 : R_CAL<= 7 ; //20375 ~ 20414
|
||||
1 : R_CAL<= 7 ; //20415 ~ 20454
|
||||
2 : R_CAL<= 7 ; //20455 ~ 20494
|
||||
3 : R_CAL<= 7 ; //20495 ~ 20534
|
||||
4 : R_CAL<= 7 ; //20535 ~ 20574
|
||||
5 : R_CAL<= 7 ; //20575 ~ 20614
|
||||
6 : R_CAL<= 7 ; //20615 ~ 20654
|
||||
7 : R_CAL<= 7 ; //20655 ~ 20694
|
||||
8 : R_CAL<= 7 ; //20695 ~ 20734
|
||||
9 : R_CAL<= 7 ; //20735 ~ 20774
|
||||
10: R_CAL<= 7 ; //20775 ~ 20814
|
||||
11: R_CAL<= 7 ; //20815 ~ 20854
|
||||
12: R_CAL<= 7 ; //20855 ~ 20894
|
||||
13: R_CAL<= 7 ; //20895 ~ 20934
|
||||
14: R_CAL<= 7 ; //20935 ~ 20974
|
||||
15: R_CAL<= 7 ; //20975 ~ 21014
|
||||
16: R_CAL<= 7 ; //21015 ~ 21054
|
||||
17: R_CAL<= 7 ; //21055 ~ 21094
|
||||
18: R_CAL<= 7 ; //21095 ~ 21134
|
||||
19: R_CAL<= 7 ; //21135 ~ 21174
|
||||
20: R_CAL<= 7 ; //21175 ~ 21214
|
||||
21: R_CAL<= 7 ; //21215 ~ 21254
|
||||
22: R_CAL<= 7 ; //21255 ~ 21294
|
||||
23: R_CAL<= 8 ; //21295 ~ 21334
|
||||
24: R_CAL<= 8 ; //21335 ~ 21374
|
||||
25: R_CAL<= 8 ; //21375 ~ 21414
|
||||
26: R_CAL<= 8 ; //21415 ~ 21454
|
||||
27: R_CAL<= 8 ; //21455 ~ 21494
|
||||
28: R_CAL<= 8 ; //21495 ~ 21534
|
||||
29: R_CAL<= 8 ; //21535 ~ 21574
|
||||
30: R_CAL<= 8 ; //21575 ~ 21614
|
||||
31: R_CAL<= 8 ; //21615 ~ 21654
|
||||
32: R_CAL<= 8 ; //21655 ~ 21694
|
||||
33: R_CAL<= 8 ; //21695 ~ 21734
|
||||
34: R_CAL<= 8 ; //21735 ~ 21774
|
||||
35: R_CAL<= 8 ; //21775 ~ 21814
|
||||
36: R_CAL<= 8 ; //21815 ~ 21854
|
||||
37: R_CAL<= 8 ; //21855 ~ 21894
|
||||
38: R_CAL<= 8 ; //21895 ~ 21934
|
||||
39: R_CAL<= 8 ; //21935 ~ 21974
|
||||
40: R_CAL<= 8 ; //21975 ~ 22014
|
||||
41: R_CAL<= 8 ; //22015 ~ 22054
|
||||
42: R_CAL<= 7 ; //22055 ~ 22094
|
||||
43: R_CAL<= 7 ; //22095 ~ 22134
|
||||
44: R_CAL<= 7 ; //22135 ~ 22174
|
||||
45: R_CAL<= 7 ; //22175 ~ 22214
|
||||
46: R_CAL<= 7 ; //22215 ~ 22254
|
||||
47: R_CAL<= 7 ; //22255 ~ 22294
|
||||
48: R_CAL<= 7 ; //22295 ~ 22334
|
||||
49: R_CAL<= 7 ; //22335 ~ 22374
|
||||
50: R_CAL<= 7 ; //22375 ~ 22414
|
||||
51: R_CAL<= 7 ; //22415 ~ 22454
|
||||
52: R_CAL<= 7 ; //22455 ~ 22494
|
||||
53: R_CAL<= 7 ; //22495 ~ 22534
|
||||
54: R_CAL<= 7 ; //22535 ~ 22574
|
||||
55: R_CAL<= 7 ; //22575 ~ 22614
|
||||
56: R_CAL<= 7 ; //22615 ~ 22654
|
||||
57: R_CAL<= 7 ; //22655 ~ 22694
|
||||
58: R_CAL<= 7 ; //22695 ~ 22734
|
||||
59: R_CAL<= 7 ; //22735 ~ 22774
|
||||
60: R_CAL<= 8 ; //22775 ~ 22814
|
||||
61: R_CAL<= 8 ; //22815 ~ 22854
|
||||
62: R_CAL<= 8 ; //22855 ~ 22894
|
||||
63: R_CAL<= 8 ; //22895 ~ 22934
|
||||
64: R_CAL<= 8 ; //22935 ~ 22974
|
||||
65: R_CAL<= 8 ; //22975 ~ 23014
|
||||
66: R_CAL<= 8 ; //23015 ~ 23054
|
||||
67: R_CAL<= 8 ; //23055 ~ 23094
|
||||
68: R_CAL<= 8 ; //23095 ~ 23134
|
||||
69: R_CAL<= 8 ; //23135 ~ 23174
|
||||
70: R_CAL<= 7 ; //23175 ~ 23214
|
||||
71: R_CAL<= 7 ; //23215 ~ 23254
|
||||
72: R_CAL<= 7 ; //23255 ~ 23294
|
||||
73: R_CAL<= 7 ; //23295 ~ 23334
|
||||
74: R_CAL<= 7 ; //23335 ~ 23374
|
||||
75: R_CAL<= 7 ; //23375 ~ 23414
|
||||
76: R_CAL<= 6 ; //23415 ~ 23454
|
||||
77: R_CAL<= 6 ; //23455 ~ 23494
|
||||
78: R_CAL<= 6 ; //23495 ~ 23534
|
||||
79: R_CAL<= 6 ; //23535 ~ 23574
|
||||
80: R_CAL<= 6 ; //23575 ~ 23614
|
||||
81: R_CAL<= 6 ; //23615 ~ 23654
|
||||
82: R_CAL<= 6 ; //23655 ~ 23694
|
||||
83: R_CAL<= 6 ; //23695 ~ 23734
|
||||
84: R_CAL<= 6 ; //23735 ~ 23774
|
||||
85: R_CAL<= 6 ; //23775 ~ 23814
|
||||
86: R_CAL<= 6 ; //23815 ~ 23854
|
||||
87: R_CAL<= 6 ; //23855 ~ 23875
|
||||
default:R_CAL<=R_CAL;
|
||||
endcase
|
||||
end
|
||||
|
||||
else if(i_temp>=8'sd0)begin//常温校准接收通道4
|
||||
case(fre_mode)
|
||||
0 : R_CAL<= 7 ; //20375 ~ 20414
|
||||
1 : R_CAL<= 7 ; //20415 ~ 20454
|
||||
2 : R_CAL<= 7 ; //20455 ~ 20494
|
||||
3 : R_CAL<= 7 ; //20495 ~ 20534
|
||||
4 : R_CAL<= 7 ; //20535 ~ 20574
|
||||
5 : R_CAL<= 7 ; //20575 ~ 20614
|
||||
6 : R_CAL<= 7 ; //20615 ~ 20654
|
||||
7 : R_CAL<= 7 ; //20655 ~ 20694
|
||||
8 : R_CAL<= 7 ; //20695 ~ 20734
|
||||
9 : R_CAL<= 7 ; //20735 ~ 20774
|
||||
10: R_CAL<= 7 ; //20775 ~ 20814
|
||||
11: R_CAL<= 7 ; //20815 ~ 20854
|
||||
12: R_CAL<= 7 ; //20855 ~ 20894
|
||||
13: R_CAL<= 7 ; //20895 ~ 20934
|
||||
14: R_CAL<= 7 ; //20935 ~ 20974
|
||||
15: R_CAL<= 7 ; //20975 ~ 21014
|
||||
16: R_CAL<= 7 ; //21015 ~ 21054
|
||||
17: R_CAL<= 7 ; //21055 ~ 21094
|
||||
18: R_CAL<= 7 ; //21095 ~ 21134
|
||||
19: R_CAL<= 7 ; //21135 ~ 21174
|
||||
20: R_CAL<= 7 ; //21175 ~ 21214
|
||||
21: R_CAL<= 7 ; //21215 ~ 21254
|
||||
22: R_CAL<= 7 ; //21255 ~ 21294
|
||||
23: R_CAL<= 8 ; //21295 ~ 21334
|
||||
24: R_CAL<= 8 ; //21335 ~ 21374
|
||||
25: R_CAL<= 8 ; //21375 ~ 21414
|
||||
26: R_CAL<= 8 ; //21415 ~ 21454
|
||||
27: R_CAL<= 8 ; //21455 ~ 21494
|
||||
28: R_CAL<= 8 ; //21495 ~ 21534
|
||||
29: R_CAL<= 8 ; //21535 ~ 21574
|
||||
30: R_CAL<= 8 ; //21575 ~ 21614
|
||||
31: R_CAL<= 8 ; //21615 ~ 21654
|
||||
32: R_CAL<= 8 ; //21655 ~ 21694
|
||||
33: R_CAL<= 8 ; //21695 ~ 21734
|
||||
34: R_CAL<= 8 ; //21735 ~ 21774
|
||||
35: R_CAL<= 8 ; //21775 ~ 21814
|
||||
36: R_CAL<= 8 ; //21815 ~ 21854
|
||||
37: R_CAL<= 8 ; //21855 ~ 21894
|
||||
38: R_CAL<= 8 ; //21895 ~ 21934
|
||||
39: R_CAL<= 8 ; //21935 ~ 21974
|
||||
40: R_CAL<= 8 ; //21975 ~ 22014
|
||||
41: R_CAL<= 8 ; //22015 ~ 22054
|
||||
42: R_CAL<= 7 ; //22055 ~ 22094
|
||||
43: R_CAL<= 7 ; //22095 ~ 22134
|
||||
44: R_CAL<= 7 ; //22135 ~ 22174
|
||||
45: R_CAL<= 7 ; //22175 ~ 22214
|
||||
46: R_CAL<= 7 ; //22215 ~ 22254
|
||||
47: R_CAL<= 7 ; //22255 ~ 22294
|
||||
48: R_CAL<= 7 ; //22295 ~ 22334
|
||||
49: R_CAL<= 7 ; //22335 ~ 22374
|
||||
50: R_CAL<= 7 ; //22375 ~ 22414
|
||||
51: R_CAL<= 7 ; //22415 ~ 22454
|
||||
52: R_CAL<= 7 ; //22455 ~ 22494
|
||||
53: R_CAL<= 7 ; //22495 ~ 22534
|
||||
54: R_CAL<= 7 ; //22535 ~ 22574
|
||||
55: R_CAL<= 7 ; //22575 ~ 22614
|
||||
56: R_CAL<= 7 ; //22615 ~ 22654
|
||||
57: R_CAL<= 7 ; //22655 ~ 22694
|
||||
58: R_CAL<= 7 ; //22695 ~ 22734
|
||||
59: R_CAL<= 7 ; //22735 ~ 22774
|
||||
60: R_CAL<= 8 ; //22775 ~ 22814
|
||||
61: R_CAL<= 8 ; //22815 ~ 22854
|
||||
62: R_CAL<= 8 ; //22855 ~ 22894
|
||||
63: R_CAL<= 8 ; //22895 ~ 22934
|
||||
64: R_CAL<= 8 ; //22935 ~ 22974
|
||||
65: R_CAL<= 8 ; //22975 ~ 23014
|
||||
66: R_CAL<= 8 ; //23015 ~ 23054
|
||||
67: R_CAL<= 8 ; //23055 ~ 23094
|
||||
68: R_CAL<= 8 ; //23095 ~ 23134
|
||||
69: R_CAL<= 8 ; //23135 ~ 23174
|
||||
70: R_CAL<= 7 ; //23175 ~ 23214
|
||||
71: R_CAL<= 7 ; //23215 ~ 23254
|
||||
72: R_CAL<= 7 ; //23255 ~ 23294
|
||||
73: R_CAL<= 7 ; //23295 ~ 23334
|
||||
74: R_CAL<= 7 ; //23335 ~ 23374
|
||||
75: R_CAL<= 7 ; //23375 ~ 23414
|
||||
76: R_CAL<= 6 ; //23415 ~ 23454
|
||||
77: R_CAL<= 6 ; //23455 ~ 23494
|
||||
78: R_CAL<= 6 ; //23495 ~ 23534
|
||||
79: R_CAL<= 6 ; //23535 ~ 23574
|
||||
80: R_CAL<= 6 ; //23575 ~ 23614
|
||||
81: R_CAL<= 6 ; //23615 ~ 23654
|
||||
82: R_CAL<= 6 ; //23655 ~ 23694
|
||||
83: R_CAL<= 6 ; //23695 ~ 23734
|
||||
84: R_CAL<= 6 ; //23735 ~ 23774
|
||||
85: R_CAL<= 6 ; //23775 ~ 23814
|
||||
86: R_CAL<= 6 ; //23815 ~ 23854
|
||||
87: R_CAL<= 6 ; //23855 ~ 23875
|
||||
default:R_CAL<=R_CAL;
|
||||
endcase
|
||||
end
|
||||
else begin//低温校准接收通道4
|
||||
case(fre_mode)
|
||||
0 : R_CAL<= 7 ; //20375 ~ 20414
|
||||
1 : R_CAL<= 7 ; //20415 ~ 20454
|
||||
2 : R_CAL<= 7 ; //20455 ~ 20494
|
||||
3 : R_CAL<= 7 ; //20495 ~ 20534
|
||||
4 : R_CAL<= 7 ; //20535 ~ 20574
|
||||
5 : R_CAL<= 7 ; //20575 ~ 20614
|
||||
6 : R_CAL<= 7 ; //20615 ~ 20654
|
||||
7 : R_CAL<= 7 ; //20655 ~ 20694
|
||||
8 : R_CAL<= 7 ; //20695 ~ 20734
|
||||
9 : R_CAL<= 7 ; //20735 ~ 20774
|
||||
10: R_CAL<= 7 ; //20775 ~ 20814
|
||||
11: R_CAL<= 7 ; //20815 ~ 20854
|
||||
12: R_CAL<= 7 ; //20855 ~ 20894
|
||||
13: R_CAL<= 7 ; //20895 ~ 20934
|
||||
14: R_CAL<= 7 ; //20935 ~ 20974
|
||||
15: R_CAL<= 7 ; //20975 ~ 21014
|
||||
16: R_CAL<= 7 ; //21015 ~ 21054
|
||||
17: R_CAL<= 7 ; //21055 ~ 21094
|
||||
18: R_CAL<= 7 ; //21095 ~ 21134
|
||||
19: R_CAL<= 7 ; //21135 ~ 21174
|
||||
20: R_CAL<= 7 ; //21175 ~ 21214
|
||||
21: R_CAL<= 7 ; //21215 ~ 21254
|
||||
22: R_CAL<= 7 ; //21255 ~ 21294
|
||||
23: R_CAL<= 8 ; //21295 ~ 21334
|
||||
24: R_CAL<= 8 ; //21335 ~ 21374
|
||||
25: R_CAL<= 8 ; //21375 ~ 21414
|
||||
26: R_CAL<= 8 ; //21415 ~ 21454
|
||||
27: R_CAL<= 8 ; //21455 ~ 21494
|
||||
28: R_CAL<= 8 ; //21495 ~ 21534
|
||||
29: R_CAL<= 8 ; //21535 ~ 21574
|
||||
30: R_CAL<= 8 ; //21575 ~ 21614
|
||||
31: R_CAL<= 8 ; //21615 ~ 21654
|
||||
32: R_CAL<= 8 ; //21655 ~ 21694
|
||||
33: R_CAL<= 8 ; //21695 ~ 21734
|
||||
34: R_CAL<= 8 ; //21735 ~ 21774
|
||||
35: R_CAL<= 8 ; //21775 ~ 21814
|
||||
36: R_CAL<= 8 ; //21815 ~ 21854
|
||||
37: R_CAL<= 8 ; //21855 ~ 21894
|
||||
38: R_CAL<= 8 ; //21895 ~ 21934
|
||||
39: R_CAL<= 8 ; //21935 ~ 21974
|
||||
40: R_CAL<= 8 ; //21975 ~ 22014
|
||||
41: R_CAL<= 8 ; //22015 ~ 22054
|
||||
42: R_CAL<= 7 ; //22055 ~ 22094
|
||||
43: R_CAL<= 7 ; //22095 ~ 22134
|
||||
44: R_CAL<= 7 ; //22135 ~ 22174
|
||||
45: R_CAL<= 7 ; //22175 ~ 22214
|
||||
46: R_CAL<= 7 ; //22215 ~ 22254
|
||||
47: R_CAL<= 7 ; //22255 ~ 22294
|
||||
48: R_CAL<= 7 ; //22295 ~ 22334
|
||||
49: R_CAL<= 7 ; //22335 ~ 22374
|
||||
50: R_CAL<= 7 ; //22375 ~ 22414
|
||||
51: R_CAL<= 7 ; //22415 ~ 22454
|
||||
52: R_CAL<= 7 ; //22455 ~ 22494
|
||||
53: R_CAL<= 7 ; //22495 ~ 22534
|
||||
54: R_CAL<= 7 ; //22535 ~ 22574
|
||||
55: R_CAL<= 7 ; //22575 ~ 22614
|
||||
56: R_CAL<= 7 ; //22615 ~ 22654
|
||||
57: R_CAL<= 7 ; //22655 ~ 22694
|
||||
58: R_CAL<= 7 ; //22695 ~ 22734
|
||||
59: R_CAL<= 7 ; //22735 ~ 22774
|
||||
60: R_CAL<= 8 ; //22775 ~ 22814
|
||||
61: R_CAL<= 8 ; //22815 ~ 22854
|
||||
62: R_CAL<= 8 ; //22855 ~ 22894
|
||||
63: R_CAL<= 8 ; //22895 ~ 22934
|
||||
64: R_CAL<= 8 ; //22935 ~ 22974
|
||||
65: R_CAL<= 8 ; //22975 ~ 23014
|
||||
66: R_CAL<= 8 ; //23015 ~ 23054
|
||||
67: R_CAL<= 8 ; //23055 ~ 23094
|
||||
68: R_CAL<= 8 ; //23095 ~ 23134
|
||||
69: R_CAL<= 8 ; //23135 ~ 23174
|
||||
70: R_CAL<= 7 ; //23175 ~ 23214
|
||||
71: R_CAL<= 7 ; //23215 ~ 23254
|
||||
72: R_CAL<= 7 ; //23255 ~ 23294
|
||||
73: R_CAL<= 7 ; //23295 ~ 23334
|
||||
74: R_CAL<= 7 ; //23335 ~ 23374
|
||||
75: R_CAL<= 7 ; //23375 ~ 23414
|
||||
76: R_CAL<= 6 ; //23415 ~ 23454
|
||||
77: R_CAL<= 6 ; //23455 ~ 23494
|
||||
78: R_CAL<= 6 ; //23495 ~ 23534
|
||||
79: R_CAL<= 6 ; //23535 ~ 23574
|
||||
80: R_CAL<= 6 ; //23575 ~ 23614
|
||||
81: R_CAL<= 6 ; //23615 ~ 23654
|
||||
82: R_CAL<= 6 ; //23655 ~ 23694
|
||||
83: R_CAL<= 6 ; //23695 ~ 23734
|
||||
84: R_CAL<= 6 ; //23735 ~ 23774
|
||||
85: R_CAL<= 6 ; //23775 ~ 23814
|
||||
86: R_CAL<= 6 ; //23815 ~ 23854
|
||||
87: R_CAL<= 6 ; //23855 ~ 23875
|
||||
default:R_CAL<=R_CAL;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
+301
@@ -0,0 +1,301 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company: Chengdu Tiger
|
||||
// Engineer: Tangxy
|
||||
//
|
||||
// Create Date: 14:14:49 09/06/2021
|
||||
// Design Name:
|
||||
// Module Name: top
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module Sisyif(
|
||||
input clk_40m ,
|
||||
input clk_20m ,
|
||||
input rst_n ,
|
||||
//调零至信处接口
|
||||
input SPI_CLK_F ,//SPI控制，时钟暂定50MHz，用来发送跳频频点、发射MGC值、接收MGC值
|
||||
input SPI_SYN_F ,//片选
|
||||
input SPI_MOSI_F ,
|
||||
output SPI_MISO_F ,
|
||||
input TP_EN_F ,//跳频使能控制(上升沿更新)
|
||||
input TR_MGC_F ,//接收发射MGC使能控制(上升沿更新)
|
||||
input CAL_F ,//校准MGC使能(上升沿更新)
|
||||
input PRF ,//高发低收，默认接收
|
||||
|
||||
//信处至射频接口
|
||||
output standby ,//高开低待机，默认待机
|
||||
output SW_PLL ,//乒乓频率源选择0：频率源A —— 1：频率源B
|
||||
output T ,//发射电源控制
|
||||
output R ,//接收电源控制
|
||||
output SW_BPF ,//开关滤波器选择
|
||||
output SCLK1 ,//锁相环A控制
|
||||
output SDIO1 ,//
|
||||
output CS1 ,//
|
||||
input LD1 ,//
|
||||
output SCLK2 ,//锁相环B控制
|
||||
output SDIO2 ,//
|
||||
output CS2 ,//
|
||||
input LD2 ,//
|
||||
output SCLK3 ,//点频源控制
|
||||
output SDIO3 ,//
|
||||
output CS3 ,//
|
||||
input LD3 ,//
|
||||
output TMGC_16db ,//发射通道MGC控制,高电平衰减
|
||||
output TMGC_8db ,//
|
||||
output TMGC_4db ,//
|
||||
output TMGC_2db ,//
|
||||
output TMGC_1db ,//
|
||||
output RMGC_16db ,//四个接收通道MGC控制，同时控制，高电平衰减
|
||||
output RMGC_8db ,//
|
||||
output RMGC_4db ,//
|
||||
output RMGC_2db ,//
|
||||
output RMGC_1db ,//
|
||||
output ENABLE ,//SPI控制四个接收通道增益校准
|
||||
output SC ,//
|
||||
output SD ,//
|
||||
output END_SYN ,//
|
||||
input SDOUT ,//
|
||||
inout DQ_WD ,//温度传感器
|
||||
output SW_RX //接收监测控制
|
||||
|
||||
);
|
||||
|
||||
wire vio_rstn ;
|
||||
wire [9:0] SYNC_OUT ;
|
||||
wire [35:0] CONTROL0 ;
|
||||
wire [35:0] CONTROL1 ;
|
||||
wire [150:0] TRIG0 ;
|
||||
|
||||
wire[15:0] temp_data ;//LSB =0.625 C
|
||||
wire[7:0] temp ;//LSB =1°C
|
||||
wire[11:0] hop_fre_code;
|
||||
wire adf4371_hop1 ;
|
||||
wire adf4371_hop2 ;
|
||||
wire [15:0] fre_code ;
|
||||
wire [7:0] tx_mgc ;
|
||||
wire [7:0] rx1_mgc ;
|
||||
wire [7:0] rx2_mgc ;
|
||||
wire [7:0] rx3_mgc ;
|
||||
wire [7:0] rx4_mgc ;
|
||||
wire [3:0] cal1_mgc ;
|
||||
wire [3:0] cal2_mgc ;
|
||||
wire [3:0] cal3_mgc ;
|
||||
wire [3:0] cal4_mgc ;
|
||||
wire [7:0] tx_cal_mgc ;
|
||||
wire [3:0] model ;
|
||||
wire [3:0] rf_en ;
|
||||
wire [31:0] frame_count;
|
||||
wire [3:0] ceshi_model;
|
||||
wire [15:0] current_fre_code ;
|
||||
wire [15:0] cal_fre_code ;
|
||||
wire [7:0] R_MGC_1 ;
|
||||
|
||||
wire SW_C1;
|
||||
wire SW;
|
||||
wire SW2;
|
||||
wire SW3;
|
||||
|
||||
wire [3:0] R_CAL1;
|
||||
wire [3:0] R_CAL2;
|
||||
wire [3:0] R_CAL3;
|
||||
wire [3:0] R_CAL4;
|
||||
wire [4:0] T_CAL ;
|
||||
|
||||
assign temp = temp_data[11:4] ;
|
||||
assign RMGC_16db = R_MGC_1[4] ;
|
||||
assign RMGC_8db = R_MGC_1[3] ;
|
||||
assign RMGC_4db = R_MGC_1[2] ;
|
||||
assign RMGC_2db = R_MGC_1[1] ;
|
||||
assign RMGC_1db = R_MGC_1[0] ;
|
||||
assign standby = rf_en == 4'b0 ;
|
||||
assign T = PRF ;
|
||||
assign R = ~PRF ;
|
||||
assign SW_BPF = SW_C1 ;
|
||||
assign SW_PLL = SW ;
|
||||
assign SW_RX = rx2_mgc == 8'b0 ? 1'b0 :1'b1 ;
|
||||
|
||||
|
||||
spi_slave u_spi_slave (
|
||||
.i_sys_clk(clk_40m),
|
||||
.i_sys_rst_n(rst_n),
|
||||
.i_spi_sck(SPI_CLK_F),
|
||||
.i_spi_cs(SPI_SYN_F),
|
||||
.i_spi_sdi(SPI_MOSI_F),
|
||||
.o_frame_count(frame_count),
|
||||
.o_fre_code(fre_code),
|
||||
.o_tx_mgc(tx_mgc),
|
||||
.o_model(model),
|
||||
.o_rf_en(rf_en),
|
||||
.o_cal1_mgc(cal1_mgc),
|
||||
.o_cal2_mgc(cal2_mgc),
|
||||
.o_cal3_mgc(cal3_mgc),
|
||||
.o_cal4_mgc(cal4_mgc),
|
||||
.o_tx_cal_mgc(tx_cal_mgc),
|
||||
.o_rx1_mgc(rx1_mgc),
|
||||
.o_rx2_mgc(rx2_mgc),
|
||||
.o_rx3_mgc(rx3_mgc),
|
||||
.o_rx4_mgc(rx4_mgc),
|
||||
.o_ceshi_model(ceshi_model)
|
||||
);
|
||||
|
||||
spi_master u_spi_master (
|
||||
.i_sys_rst_n (rst_n) ,
|
||||
.i_clk (clk_40m) ,
|
||||
//.debug_clk (clk_80m) ,
|
||||
.i_spi_sck (SPI_CLK_F) ,
|
||||
.i_spi_cs (SPI_SYN_F) ,
|
||||
.o_spi_sdo (SPI_MISO_F) ,
|
||||
.i_spi_sdi (SPI_MOSI_F) ,
|
||||
.i_LD_LO3 (LD3) ,
|
||||
.i_LD1 (LD1) ,
|
||||
.i_LD2 (LD2) ,
|
||||
.i_cal1_mgc (R_CAL4) ,
|
||||
.i_cal2_mgc (R_CAL3) ,
|
||||
.i_cal3_mgc (R_CAL2) ,
|
||||
.i_cal4_mgc (R_CAL1) ,
|
||||
.i_temp (temp ) ,
|
||||
.i_frame_count (frame_count)
|
||||
);
|
||||
|
||||
mgc_ctrl u_mgc_ctrl(
|
||||
.i_sys_clk (clk_40m ),
|
||||
.i_rst_n (rst_n ),
|
||||
.i_TR_SW_F (PRF ),
|
||||
.i_TP_EN_F (TP_EN_F ),
|
||||
.i_T_MGC_EN_F (TR_MGC_F ),
|
||||
.i_R_MGC_EN_F (TR_MGC_F ),
|
||||
.i_CAL_F (CAL_F ),
|
||||
.i_fre_code (fre_code ),
|
||||
.i_tx_mgc (tx_mgc ),
|
||||
.i_rx1_mgc (rx1_mgc ),
|
||||
.i_rx2_mgc (rx2_mgc ),
|
||||
.i_rx3_mgc (rx3_mgc ),
|
||||
.i_rx4_mgc (rx4_mgc ),
|
||||
.i_ceshi_module (ceshi_model ),
|
||||
.o_current_fre_code (current_fre_code ),
|
||||
.o_cal_fre_code (cal_fre_code ),
|
||||
.o_hop_fre_code (hop_fre_code ), //0(20.375GHz)~3500(23.875GHz)
|
||||
.o_adf4371_hop1 (adf4371_hop1 ), //high active
|
||||
.o_adf4371_hop2 (adf4371_hop2 ),
|
||||
.o_SW (SW ),
|
||||
.o_SW2 (SW2 ),
|
||||
.o_SW3 (SW3 ),
|
||||
.o_SW_C1 (SW_C1 ),
|
||||
.o_T_MGC_1dB (TMGC_1db ),
|
||||
.o_T_MGC_2dB (TMGC_2db ),
|
||||
.o_T_MGC_4dB (TMGC_4db ),
|
||||
.o_T_MGC_8dB (TMGC_8db ),
|
||||
.o_T_MGC_16dB (TMGC_16db ),
|
||||
.o_R_MGC_1 (R_MGC_1 )
|
||||
//.o_R_MGC_2 (R_MGC_2 ),
|
||||
//.o_R_MGC_3 (R_MGC_3 ),
|
||||
//.o_R_MGC_4 (R_MGC_4 )
|
||||
);
|
||||
|
||||
wire cfgover;
|
||||
adf4371_a u_adf4371_a (
|
||||
.sysclk (clk_40m ),
|
||||
.arstn (rst_n&vio_rstn ),
|
||||
.cs (CS1 ),
|
||||
.mux_out (LD1 ),
|
||||
.sclk (SCLK1 ),
|
||||
.sdio (SDIO1 ),
|
||||
.rf_en (rf_en ),
|
||||
.SW_PLL (SW_PLL ),
|
||||
.CAL_F (CAL_F ),
|
||||
.o_cfgover (cfgover ),
|
||||
.ceshi_model(ceshi_model ),
|
||||
.adf4371_hop(adf4371_hop1),
|
||||
.fre_code (hop_fre_code)
|
||||
);
|
||||
|
||||
adf4371_b u_adf4371_b (
|
||||
.sysclk (clk_40m ),
|
||||
.arstn (rst_n&vio_rstn),
|
||||
.cs (CS2 ),
|
||||
.mux_out (LD2 ),
|
||||
.sclk (SCLK2 ),
|
||||
.sdio (SDIO2 ),
|
||||
.rf_en (rf_en ),
|
||||
.SW_PLL (SW_PLL ),
|
||||
.CAL_F (CAL_F ),
|
||||
.i_cfgover (cfgover ),
|
||||
.ceshi_model(ceshi_model ),
|
||||
.adf4371_hop(adf4371_hop2),
|
||||
.fre_code (hop_fre_code)
|
||||
);
|
||||
|
||||
fre_caliatt u_fre_caliatt (
|
||||
.i_clk (clk_40m ),
|
||||
.i_rstn (rst_n ),
|
||||
.ENABLE (ENABLE ),
|
||||
.SC (SC ),
|
||||
.SD (SD ),
|
||||
.END_SYN (END_SYN ),
|
||||
.SDOUT (SDOUT ),
|
||||
.CAL_F (CAL_F ),
|
||||
.i_temp (temp ),
|
||||
.i_fre_mode (current_fre_code ),
|
||||
.i_cal_fre_code (cal_fre_code ),
|
||||
// .SYNC_OUT (SYNC_OUT ),
|
||||
.SW (SW ),
|
||||
.cal1_mgc (cal1_mgc ),
|
||||
.cal2_mgc (cal2_mgc ),
|
||||
.cal3_mgc (cal3_mgc ),
|
||||
.cal4_mgc (cal4_mgc ),
|
||||
.tx_cal_mgc (tx_cal_mgc ),
|
||||
.tx_mgc (tx_mgc ),
|
||||
.i_ceshi_module (ceshi_model ),
|
||||
.R_CAL1 (R_CAL1 ),
|
||||
.R_CAL2 (R_CAL2 ),
|
||||
.R_CAL3 (R_CAL3 ),
|
||||
.R_CAL4 (R_CAL4 ),
|
||||
.T_CAL (T_CAL )
|
||||
);
|
||||
|
||||
|
||||
adf4351_2 u_adf4351 (
|
||||
.i_sysclk(clk_20m),
|
||||
.i_arstn(rst_n),
|
||||
.o_ADF4351_SCK(SCLK3),
|
||||
.o_ADF4351_DATA(SDIO3),
|
||||
.o_ADF4351_LE(CS3),
|
||||
.i_ADF4351_locked(LD3)
|
||||
);
|
||||
|
||||
|
||||
ds18b20_temp u_temp (
|
||||
.clk(clk_40m),
|
||||
.rstn(rst_n),
|
||||
.dq(DQ_WD),
|
||||
.temp_data(temp_data)
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
assign vio_rstn = 1'b1;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
+631
@@ -0,0 +1,631 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 17:05:24 04/08/2022
|
||||
// Design Name:
|
||||
// Module Name: T_CAL_
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module T_CAL(
|
||||
input i_clk ,
|
||||
input i_rstn ,
|
||||
input SW ,
|
||||
input signed[7:0] i_temp ,
|
||||
input [31:0] hop_fre_mode ,
|
||||
output reg[4:0] T_CAL_
|
||||
|
||||
);
|
||||
|
||||
|
||||
|
||||
//发射通道
|
||||
always@(posedge i_clk,negedge i_rstn)begin//1dB 步进
|
||||
if(!i_rstn)
|
||||
T_CAL_<='d0;
|
||||
else if(SW==1'b1)//B环校准值
|
||||
begin
|
||||
if(i_temp>=8'sd70)//B环高温校准值
|
||||
begin
|
||||
if(hop_fre_mode<=20414) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=20454) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=20494) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=20534) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=20574) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20614) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20654) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20694) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20734) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20774) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20814) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20854) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20894) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20934) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20974) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=21014) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=21054) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=21094) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21134) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21174) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21214) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21254) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21294) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21334) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21374) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21414) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21454) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21494) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21534) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21574) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21614) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21654) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21694) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21734) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21774) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21814) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21854) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21875) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21894) T_CAL_<= 11 ; //21894
|
||||
else if(hop_fre_mode<=21934) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=21974) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22014) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22054) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22094) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22134) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22174) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22214) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22254) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22294) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22334) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22374) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22414) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22454) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22494) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22534) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22574) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22614) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22654) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22694) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22734) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22774) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22814) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22854) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22894) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22934) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22974) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=23014) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=23054) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23094) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23134) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23174) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23214) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23254) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23294) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23334) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23374) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23414) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23454) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23494) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23534) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23574) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23614) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23654) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23694) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23734) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23774) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23814) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23854) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23875) T_CAL_<= 9 ;
|
||||
end
|
||||
|
||||
else if(i_temp>=8'sd0)//B环常温校准值
|
||||
begin
|
||||
if(hop_fre_mode<=20414) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=20454) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=20494) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=20534) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=20574) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20614) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20654) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20694) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20734) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20774) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20814) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20854) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20894) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20934) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20974) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=21014) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=21054) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=21094) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21134) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21174) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21214) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21254) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21294) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21334) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21374) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21414) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21454) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21494) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21534) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21574) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21614) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21654) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21694) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21734) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21774) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21814) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21854) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21875) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21894) T_CAL_<= 11 ; //21894
|
||||
else if(hop_fre_mode<=21934) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=21974) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22014) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22054) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22094) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22134) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22174) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22214) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22254) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22294) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22334) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22374) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22414) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22454) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22494) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22534) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22574) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22614) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22654) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22694) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22734) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22774) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22814) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22854) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22894) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22934) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22974) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=23014) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=23054) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23094) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23134) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23174) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23214) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23254) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23294) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23334) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23374) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23414) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23454) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23494) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23534) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23574) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23614) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23654) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23694) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23734) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23774) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23814) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23854) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23875) T_CAL_<= 9 ;
|
||||
end
|
||||
|
||||
else //B环低温校准值
|
||||
begin
|
||||
if(hop_fre_mode<=20414) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=20454) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=20494) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=20534) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=20574) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20614) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20654) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20694) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20734) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20774) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20814) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20854) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20894) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20934) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20974) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=21014) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=21054) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=21094) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21134) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21174) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21214) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21254) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21294) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21334) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21374) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21414) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21454) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21494) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21534) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21574) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21614) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21654) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21694) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21734) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21774) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21814) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21854) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21875) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21894) T_CAL_<= 11 ; //21894
|
||||
else if(hop_fre_mode<=21934) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=21974) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22014) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22054) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22094) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22134) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22174) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22214) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22254) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22294) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22334) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22374) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22414) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22454) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22494) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22534) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22574) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22614) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22654) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22694) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22734) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22774) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22814) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22854) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22894) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22934) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22974) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=23014) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=23054) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23094) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23134) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23174) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23214) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23254) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23294) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23334) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23374) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23414) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23454) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23494) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23534) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23574) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23614) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23654) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23694) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23734) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23774) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23814) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23854) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23875) T_CAL_<= 9 ;
|
||||
end
|
||||
end
|
||||
else //A环校准值
|
||||
begin
|
||||
if(i_temp>=8'sd70)//A环高温校准值
|
||||
begin
|
||||
if(hop_fre_mode<=20414) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=20454) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=20494) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=20534) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=20574) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20614) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20654) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20694) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20734) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20774) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20814) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20854) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20894) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20934) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20974) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=21014) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=21054) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=21094) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21134) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21174) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21214) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21254) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21294) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21334) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21374) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21414) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21454) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21494) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21534) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21574) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21614) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21654) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21694) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21734) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21774) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21814) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21854) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21875) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21894) T_CAL_<= 11 ; //21894
|
||||
else if(hop_fre_mode<=21934) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=21974) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22014) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22054) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22094) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22134) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22174) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22214) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22254) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22294) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22334) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22374) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22414) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22454) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22494) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22534) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22574) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22614) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22654) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22694) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22734) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22774) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22814) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22854) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22894) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22934) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22974) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=23014) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=23054) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23094) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23134) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23174) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23214) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23254) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23294) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23334) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23374) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23414) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23454) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23494) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23534) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23574) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23614) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23654) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23694) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23734) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23774) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23814) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23854) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23875) T_CAL_<= 9 ;
|
||||
end
|
||||
|
||||
else if(i_temp>=8'sd0)//A环常温校准值
|
||||
begin
|
||||
if(hop_fre_mode<=20414) T_CAL_<= 14 ; //20375 ~ 20414
|
||||
else if(hop_fre_mode<=20454) T_CAL_<= 14 ; //20415 ~ 20454
|
||||
else if(hop_fre_mode<=20494) T_CAL_<= 14 ; //20455 ~ 20494
|
||||
else if(hop_fre_mode<=20534) T_CAL_<= 14 ; //20495 ~ 20534
|
||||
else if(hop_fre_mode<=20574) T_CAL_<= 15 ; //20535 ~ 20574
|
||||
else if(hop_fre_mode<=20614) T_CAL_<= 15 ; //20575 ~ 20614
|
||||
else if(hop_fre_mode<=20654) T_CAL_<= 15 ; //20615 ~ 20654
|
||||
else if(hop_fre_mode<=20694) T_CAL_<= 15 ; //20655 ~ 20694
|
||||
else if(hop_fre_mode<=20734) T_CAL_<= 15 ; //20695 ~ 20734
|
||||
else if(hop_fre_mode<=20774) T_CAL_<= 16 ; //20735 ~ 20774
|
||||
else if(hop_fre_mode<=20814) T_CAL_<= 16 ; //20775 ~ 20814
|
||||
else if(hop_fre_mode<=20854) T_CAL_<= 16 ; //20815 ~ 20854
|
||||
else if(hop_fre_mode<=20894) T_CAL_<= 16 ; //20855 ~ 20894
|
||||
else if(hop_fre_mode<=20934) T_CAL_<= 16 ; //20895 ~ 20934
|
||||
else if(hop_fre_mode<=20974) T_CAL_<= 16 ; //20935 ~ 20974
|
||||
else if(hop_fre_mode<=21014) T_CAL_<= 16 ; //20975 ~ 21014
|
||||
else if(hop_fre_mode<=21054) T_CAL_<= 16 ; //21015 ~ 21054
|
||||
else if(hop_fre_mode<=21094) T_CAL_<= 15 ; //21055 ~ 21094
|
||||
else if(hop_fre_mode<=21134) T_CAL_<= 14 ; //21095 ~ 21134
|
||||
else if(hop_fre_mode<=21174) T_CAL_<= 14 ; //21135 ~ 21174
|
||||
else if(hop_fre_mode<=21214) T_CAL_<= 13 ; //21175 ~ 21214
|
||||
else if(hop_fre_mode<=21254) T_CAL_<= 13 ; //21215 ~ 21254
|
||||
else if(hop_fre_mode<=21294) T_CAL_<= 13 ; //21255 ~ 21294
|
||||
else if(hop_fre_mode<=21334) T_CAL_<= 13 ; //21295 ~ 21334
|
||||
else if(hop_fre_mode<=21374) T_CAL_<= 14 ; //21335 ~ 21374
|
||||
else if(hop_fre_mode<=21414) T_CAL_<= 14 ; //21375 ~ 21414
|
||||
else if(hop_fre_mode<=21454) T_CAL_<= 15 ; //21415 ~ 21454
|
||||
else if(hop_fre_mode<=21494) T_CAL_<= 15 ; //21455 ~ 21494
|
||||
else if(hop_fre_mode<=21534) T_CAL_<= 15 ; //21495 ~ 21534
|
||||
else if(hop_fre_mode<=21574) T_CAL_<= 15 ; //21535 ~ 21574
|
||||
else if(hop_fre_mode<=21614) T_CAL_<= 15 ; //21575 ~ 21614
|
||||
else if(hop_fre_mode<=21654) T_CAL_<= 15 ; //21615 ~ 21654
|
||||
else if(hop_fre_mode<=21694) T_CAL_<= 15 ; //21655 ~ 21694
|
||||
else if(hop_fre_mode<=21734) T_CAL_<= 14 ; //21695 ~ 21734
|
||||
else if(hop_fre_mode<=21774) T_CAL_<= 14 ; //21735 ~ 21774
|
||||
else if(hop_fre_mode<=21814) T_CAL_<= 13 ; //21775 ~ 21814
|
||||
else if(hop_fre_mode<=21854) T_CAL_<= 13 ; //21815 ~ 21854
|
||||
else if(hop_fre_mode<=21875) T_CAL_<= 13 ; //21855 ~ 21875
|
||||
else if(hop_fre_mode<=21894) T_CAL_<= 11 ; //21874 ~ 21894
|
||||
else if(hop_fre_mode<=21934) T_CAL_<= 11 ; //21895 ~ 21934
|
||||
else if(hop_fre_mode<=21974) T_CAL_<= 11 ; //21935 ~ 21974
|
||||
else if(hop_fre_mode<=22014) T_CAL_<= 11 ; //21975 ~ 22014
|
||||
else if(hop_fre_mode<=22054) T_CAL_<= 11 ; //22015 ~ 22054
|
||||
else if(hop_fre_mode<=22094) T_CAL_<= 11 ; //22055 ~ 22094
|
||||
else if(hop_fre_mode<=22134) T_CAL_<= 11 ; //22095 ~ 22134
|
||||
else if(hop_fre_mode<=22174) T_CAL_<= 11 ; //22135 ~ 22174
|
||||
else if(hop_fre_mode<=22214) T_CAL_<= 11 ; //22175 ~ 22214
|
||||
else if(hop_fre_mode<=22254) T_CAL_<= 11 ; //22215 ~ 22254
|
||||
else if(hop_fre_mode<=22294) T_CAL_<= 11 ; //22255 ~ 22294
|
||||
else if(hop_fre_mode<=22334) T_CAL_<= 11 ; //22295 ~ 22334
|
||||
else if(hop_fre_mode<=22374) T_CAL_<= 11 ; //22335 ~ 22374
|
||||
else if(hop_fre_mode<=22414) T_CAL_<= 11 ; //22375 ~ 22414
|
||||
else if(hop_fre_mode<=22454) T_CAL_<= 11 ; //22415 ~ 22454
|
||||
else if(hop_fre_mode<=22494) T_CAL_<= 11 ; //22455 ~ 22494
|
||||
else if(hop_fre_mode<=22534) T_CAL_<= 11 ; //22495 ~ 22534
|
||||
else if(hop_fre_mode<=22574) T_CAL_<= 11 ; //22535 ~ 22574
|
||||
else if(hop_fre_mode<=22614) T_CAL_<= 11 ; //22575 ~ 22614
|
||||
else if(hop_fre_mode<=22654) T_CAL_<= 11 ; //22615 ~ 22654
|
||||
else if(hop_fre_mode<=22694) T_CAL_<= 11 ; //22655 ~ 22694
|
||||
else if(hop_fre_mode<=22734) T_CAL_<= 11 ; //22695 ~ 22734
|
||||
else if(hop_fre_mode<=22774) T_CAL_<= 11 ; //22735 ~ 22774
|
||||
else if(hop_fre_mode<=22814) T_CAL_<= 11 ; //22775 ~ 22814
|
||||
else if(hop_fre_mode<=22854) T_CAL_<= 11 ; //22815 ~ 22854
|
||||
else if(hop_fre_mode<=22894) T_CAL_<= 11 ; //22855 ~ 22894
|
||||
else if(hop_fre_mode<=22934) T_CAL_<= 11 ; //22895 ~ 22934
|
||||
else if(hop_fre_mode<=22974) T_CAL_<= 11 ; //22935 ~ 22974
|
||||
else if(hop_fre_mode<=23014) T_CAL_<= 11 ; //22975 ~ 23014
|
||||
else if(hop_fre_mode<=23054) T_CAL_<= 10 ; //23015 ~ 23054
|
||||
else if(hop_fre_mode<=23094) T_CAL_<= 10 ; //23055 ~ 23094
|
||||
else if(hop_fre_mode<=23134) T_CAL_<= 10 ; //23095 ~ 23134
|
||||
else if(hop_fre_mode<=23174) T_CAL_<= 10 ; //23135 ~ 23174
|
||||
else if(hop_fre_mode<=23214) T_CAL_<= 10 ; //23175 ~ 23214
|
||||
else if(hop_fre_mode<=23254) T_CAL_<= 10 ; //23215 ~ 23254
|
||||
else if(hop_fre_mode<=23294) T_CAL_<= 10 ; //23255 ~ 23294
|
||||
else if(hop_fre_mode<=23334) T_CAL_<= 10 ; //23295 ~ 23334
|
||||
else if(hop_fre_mode<=23374) T_CAL_<= 10 ; //23335 ~ 23374
|
||||
else if(hop_fre_mode<=23414) T_CAL_<= 10 ; //23375 ~ 23414
|
||||
else if(hop_fre_mode<=23454) T_CAL_<= 10 ; //23415 ~ 23454
|
||||
else if(hop_fre_mode<=23494) T_CAL_<= 10 ; //23455 ~ 23494
|
||||
else if(hop_fre_mode<=23534) T_CAL_<= 10 ; //23495 ~ 23534
|
||||
else if(hop_fre_mode<=23574) T_CAL_<= 10 ; //23535 ~ 23574
|
||||
else if(hop_fre_mode<=23614) T_CAL_<= 9 ; //23575 ~ 23614
|
||||
else if(hop_fre_mode<=23654) T_CAL_<= 9 ; //23615 ~ 23654
|
||||
else if(hop_fre_mode<=23694) T_CAL_<= 9 ; //23655 ~ 23694
|
||||
else if(hop_fre_mode<=23734) T_CAL_<= 9 ; //23695 ~ 23734
|
||||
else if(hop_fre_mode<=23774) T_CAL_<= 9 ; //23735 ~ 23774
|
||||
else if(hop_fre_mode<=23814) T_CAL_<= 9 ; //23775 ~ 23814
|
||||
else if(hop_fre_mode<=23854) T_CAL_<= 9 ; //23815 ~ 23854
|
||||
else if(hop_fre_mode<=23875) T_CAL_<= 9 ; //23855 ~ 23875
|
||||
end
|
||||
else //A环低温校准值
|
||||
begin
|
||||
if(hop_fre_mode<=20414) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=20454) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=20494) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=20534) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=20574) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20614) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20654) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20694) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20734) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20774) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20814) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20854) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20894) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20934) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20974) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=21014) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=21054) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=21094) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21134) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21174) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21214) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21254) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21294) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21334) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21374) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21414) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21454) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21494) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21534) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21574) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21614) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21654) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21694) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21734) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21774) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21814) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21854) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21875) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21894) T_CAL_<= 11 ; //21894
|
||||
else if(hop_fre_mode<=21934) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=21974) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22014) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22054) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22094) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22134) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22174) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22214) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22254) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22294) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22334) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22374) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22414) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22454) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22494) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22534) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22574) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22614) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22654) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22694) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22734) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22774) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22814) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22854) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22894) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22934) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22974) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=23014) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=23054) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23094) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23134) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23174) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23214) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23254) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23294) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23334) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23374) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23414) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23454) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23494) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23534) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23574) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23614) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23654) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23694) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23734) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23774) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23814) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23854) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23875) T_CAL_<= 9 ;
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
+633
@@ -0,0 +1,633 @@
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2021/8/13 00:24:20
|
||||
// Design Name:
|
||||
// Module Name: LMX2595
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
|
||||
// fRFOUT= (INT+ (FRAC1+FRAC2/MOD2)/MOD1)× (fPFD/R)
|
||||
// fPFD = fPFD = REFIN × ((1 + D)/(R × (1 + T)))
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module adf4371_a(//20.375Ghz ~ 23.875Ghz
|
||||
input sysclk ,//40MHZ
|
||||
input arstn ,
|
||||
output cs ,
|
||||
input mux_out ,
|
||||
output sclk ,
|
||||
output sdio ,
|
||||
input [3:0] rf_en ,
|
||||
input SW_PLL ,
|
||||
input CAL_F ,
|
||||
input [3:0] ceshi_model ,
|
||||
input adf4371_hop ,
|
||||
output o_cfgover ,
|
||||
input[11:0] fre_code
|
||||
);
|
||||
|
||||
localparam DATA_WIDTH = 24 ;
|
||||
localparam DATA_LENTH = 72 ;
|
||||
localparam WAIT_ld = 40000 ;
|
||||
//*****************************************************************************
|
||||
reg[7:0] cnt_word = 8'd0 ;
|
||||
reg csb_reg = 1'b1 ;
|
||||
reg[5:0] cnt_bits = 6'd0 ;
|
||||
reg[DATA_WIDTH-1:0] cfgdata = 0, regdata = 0 ;
|
||||
reg[3:0] state = 4'b000 ;
|
||||
reg spi_sdo = 1'b0, spi_csb = 1'b1;
|
||||
wire pll_locked ;
|
||||
reg cfgover ;
|
||||
reg[31:0] cnt_lock = 32'd0 ;
|
||||
reg[31:0] cnt_locked = 32'd0 ;
|
||||
wire[15:0] band ;
|
||||
assign o_cfgover =cfgover ;
|
||||
//-----------------------------------
|
||||
assign pll_locked = mux_out ;
|
||||
assign sclk = spi_csb ? 1'b0 : ~sysclk ;
|
||||
assign cs = spi_csb & csb_reg ;
|
||||
assign sdio = spi_sdo ;
|
||||
//-----------------------------------
|
||||
|
||||
wire [7:0] SI_BAND_SEL ; //VCO频段
|
||||
wire [7:0] SI_VCO_SEL_BIAS_CODE ; //[7:4]=VCO内核, [3:0]=VCO偏置
|
||||
reg[13:0] MOD2 ;
|
||||
reg[13:0] FRAC2 ;
|
||||
reg[24:0] FRAC1 ;
|
||||
reg[15:0] INT ;
|
||||
|
||||
assign SI_BAND_SEL = band[15:8] ;
|
||||
assign SI_VCO_SEL_BIAS_CODE = band[7:0] ;
|
||||
|
||||
reg[2:0] hop_en ;
|
||||
reg[15:0] code ;
|
||||
reg[11:0] pre_fre_code ;
|
||||
reg[3:0] rf_en_r ;
|
||||
reg[2:0] CAL_F_R ;
|
||||
|
||||
reg [3:0] R_DIV ;
|
||||
reg [3:0] D ;
|
||||
wire[13:0] douta3 ;
|
||||
wire[13:0] douta4 ;
|
||||
wire[24:0] douta2 ;
|
||||
wire[15:0] douta1 ;
|
||||
//-----------------------------------
|
||||
|
||||
INT_ROMb int_rom (
|
||||
.sysclk(sysclk),
|
||||
.addra(code),
|
||||
.douta(douta1)
|
||||
);
|
||||
|
||||
// Instantiate the module
|
||||
FRAC1 frac1_rom (
|
||||
.clka(sysclk),
|
||||
.addra(code),
|
||||
.douta(douta2)
|
||||
);
|
||||
|
||||
|
||||
// FRAC1_ROM FRAC1_ROM (
|
||||
// .clka(sysclk), // input clka
|
||||
// .addra(code), // input [11 : 0] addra
|
||||
// .douta(douta2) // output [24 : 0] douta
|
||||
//);
|
||||
|
||||
frac2_rom frac2_rom (
|
||||
.sysclk(sysclk),
|
||||
.addra(code),
|
||||
.douta(douta4)
|
||||
);
|
||||
|
||||
mod2_rom mod2_rom (
|
||||
.sysclk(sysclk),
|
||||
.addra(code),
|
||||
.douta(douta3)
|
||||
);
|
||||
|
||||
|
||||
band_rom_a band_rom_a (
|
||||
.sysclk(sysclk),
|
||||
.addra(code),
|
||||
.douta(band) // output [15 : 0] douta
|
||||
);
|
||||
|
||||
|
||||
//-------------------整数边界杂散用66.666666Mhz鉴相----------------------------------
|
||||
always@(posedge sysclk,negedge arstn)
|
||||
begin
|
||||
if(!arstn)
|
||||
INT<=douta1;
|
||||
else if(code==24 || code==26 )
|
||||
INT<=76;
|
||||
else if(code==424 )
|
||||
INT<=77;
|
||||
else if(code==426 )
|
||||
INT<=78;
|
||||
else if(code==824 || code==826 )
|
||||
INT<=79;
|
||||
else if(code==1224)
|
||||
INT<=80;
|
||||
else if(code==1226 )
|
||||
INT<=81;
|
||||
else if(code==1624 || code==1626 )
|
||||
INT<=82;
|
||||
else if(code==2024 )
|
||||
INT<=83;
|
||||
else if(code==2026 )
|
||||
INT<=84;
|
||||
else if(code==2424 || code==2426 )
|
||||
INT<=85;
|
||||
else if(code==2824 )
|
||||
INT<=86;
|
||||
else if( code==2826 )
|
||||
INT<=87;
|
||||
else
|
||||
INT<=douta1;
|
||||
end
|
||||
|
||||
always@(posedge sysclk,negedge arstn)
|
||||
begin
|
||||
if(!arstn)
|
||||
FRAC1<=douta2;
|
||||
else if(code==24 )
|
||||
FRAC1<=16651386;
|
||||
else if(code==26 )
|
||||
FRAC1<=16903045;
|
||||
else if(code==424 )
|
||||
FRAC1<=33428602;
|
||||
else if(code==426 )
|
||||
FRAC1<=125829;
|
||||
else if(code==824 )
|
||||
FRAC1<=16651386;
|
||||
else if(code==826 )
|
||||
FRAC1<=16903045;
|
||||
else if(code==1224)
|
||||
FRAC1<=33428602;
|
||||
else if(code==1226 )
|
||||
FRAC1<=125829;
|
||||
else if(code==1624)
|
||||
FRAC1<=16651386;
|
||||
else if(code==1626 )
|
||||
FRAC1<=16903045;
|
||||
else if(code==2024 )
|
||||
FRAC1<=33428602;
|
||||
else if(code==2026 )
|
||||
FRAC1<=125829;
|
||||
else if(code==2424 )
|
||||
FRAC1<=16651386;
|
||||
else if(code==2426 )
|
||||
FRAC1<=16903045;
|
||||
else if(code==2824 )
|
||||
FRAC1<=33428602;
|
||||
else if( code==2826 )
|
||||
FRAC1<=125829;
|
||||
else
|
||||
FRAC1<=douta2;
|
||||
end
|
||||
|
||||
always@(posedge sysclk,negedge arstn)
|
||||
begin
|
||||
if(!arstn)
|
||||
MOD2<=douta3;
|
||||
else if(code==24 )
|
||||
MOD2<=25;
|
||||
else if(code==26 )
|
||||
MOD2<=25;
|
||||
else if(code==424 )
|
||||
MOD2<=25;
|
||||
else if(code==426 )
|
||||
MOD2<=25;
|
||||
else if(code==824 )
|
||||
MOD2<=25;
|
||||
else if(code==826 )
|
||||
MOD2<=25;
|
||||
else if(code==1224)
|
||||
MOD2<=25;
|
||||
else if(code==1226 )
|
||||
MOD2<=25;
|
||||
else if(code==1624)
|
||||
MOD2<=25;
|
||||
else if(code==1626 )
|
||||
MOD2<=25;
|
||||
else if(code==2024 )
|
||||
MOD2<=25;
|
||||
else if(code==2026 )
|
||||
MOD2<=25;
|
||||
else if(code==2424 )
|
||||
MOD2<=25;
|
||||
else if(code==2426 )
|
||||
MOD2<=25;
|
||||
else if(code==2824 )
|
||||
MOD2<=25;
|
||||
else if( code==2826 )
|
||||
MOD2<=25;
|
||||
else
|
||||
MOD2<=douta3;
|
||||
end
|
||||
|
||||
always@(posedge sysclk,negedge arstn)
|
||||
begin
|
||||
if(!arstn)
|
||||
FRAC2<=douta4;
|
||||
else if(code==24 )
|
||||
FRAC2<=22;
|
||||
else if(code==26 )
|
||||
FRAC2<=3;
|
||||
else if(code==424 )
|
||||
FRAC2<=22;
|
||||
else if(code==426 )
|
||||
FRAC2<=3;
|
||||
else if(code==824 )
|
||||
FRAC2<=22;
|
||||
else if(code==826 )
|
||||
FRAC2<=3;
|
||||
else if(code==1224)
|
||||
FRAC2<=22;
|
||||
else if(code==1226 )
|
||||
FRAC2<=3;
|
||||
else if(code==1624)
|
||||
FRAC2<=22;
|
||||
else if(code==1626 )
|
||||
FRAC2<=3;
|
||||
else if(code==2024 )
|
||||
FRAC2<=22;
|
||||
else if(code==2026 )
|
||||
FRAC2<=3;
|
||||
else if(code==2424 )
|
||||
FRAC2<=22;
|
||||
else if(code==2426 )
|
||||
FRAC2<=3;
|
||||
else if(code==2824 )
|
||||
FRAC2<=22;
|
||||
else if( code==2826 )
|
||||
FRAC2<=3;
|
||||
else
|
||||
FRAC2<=douta4;
|
||||
end
|
||||
|
||||
always@(posedge sysclk,negedge arstn)
|
||||
begin
|
||||
if(!arstn)begin
|
||||
R_DIV<=4'b1;
|
||||
D<=4'b0;
|
||||
end
|
||||
else if(code==24 || code==26 || code==424 || code==426 || code==824 || code==826|| code==1224 || code==1226 || code==1624 || code==1626 ||code==2024 || code==2026 ||code==2424 || code==2426 ||code==2824 || code==2826 )
|
||||
begin
|
||||
R_DIV<= 4'd3;
|
||||
D<=4'd2;
|
||||
end
|
||||
else
|
||||
begin
|
||||
R_DIV<=4'b1;
|
||||
D<=4'b0;
|
||||
end
|
||||
end
|
||||
|
||||
//----------------------------------------------------------------
|
||||
|
||||
always@(posedge sysclk,negedge arstn)begin
|
||||
if(~arstn)
|
||||
pre_fre_code<=11'h6d6;
|
||||
else if(CAL_F_R==3'b011)
|
||||
pre_fre_code<=fre_code;
|
||||
else
|
||||
pre_fre_code<=pre_fre_code;
|
||||
end
|
||||
|
||||
|
||||
always@(posedge sysclk,negedge arstn)begin
|
||||
if(~arstn)
|
||||
code<=16'h0;
|
||||
else if(hop_en==2'b01)
|
||||
code<=fre_code;
|
||||
else
|
||||
code<=code;
|
||||
end
|
||||
|
||||
|
||||
always@(posedge sysclk,negedge arstn)begin
|
||||
if(~arstn)begin
|
||||
hop_en <= 3'b0;
|
||||
rf_en_r <= 4'b0;
|
||||
CAL_F_R <= 3'b0;
|
||||
end
|
||||
else begin
|
||||
hop_en <= {hop_en[1:0],adf4371_hop};
|
||||
CAL_F_R <= {CAL_F_R[1:0],CAL_F};
|
||||
rf_en_r <= rf_en ;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge sysclk,negedge arstn)begin
|
||||
if(~arstn)
|
||||
csb_reg <= 1'b1;
|
||||
else
|
||||
csb_reg <= spi_csb;
|
||||
end
|
||||
|
||||
|
||||
always@(posedge sysclk,negedge arstn)begin
|
||||
if(~arstn)
|
||||
cnt_locked<=32'b0;
|
||||
else if(cnt_locked==WAIT_ld)
|
||||
cnt_locked<=32'b0;
|
||||
else if(!pll_locked)
|
||||
cnt_locked<=cnt_locked+1'b1;
|
||||
else
|
||||
cnt_locked<=32'b0;
|
||||
end
|
||||
|
||||
always@(posedge sysclk,negedge arstn)begin
|
||||
if(~arstn)begin
|
||||
cfgdata <= 0;
|
||||
cnt_word <= 7'd0;
|
||||
cnt_bits <= 6'd0;
|
||||
state <= 4'b0;
|
||||
cnt_lock <= 32'd0;
|
||||
spi_csb <= 1'b1;
|
||||
cfgover <= 1'b0;
|
||||
spi_sdo <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
case(state)
|
||||
4'd0:begin
|
||||
cnt_word <= 7'd0;
|
||||
if(rf_en==1'b1)
|
||||
state <= 4'd0;
|
||||
else if(cnt_lock >= 32'd4000)
|
||||
state <= 4'd1;
|
||||
else
|
||||
state <= state;
|
||||
|
||||
if(rf_en==1'b0)
|
||||
cnt_lock <= cnt_lock + 1'b1;
|
||||
else
|
||||
cnt_lock<=32'd0;
|
||||
|
||||
end
|
||||
4'd1:begin
|
||||
spi_csb <= 1'b1;
|
||||
spi_sdo <= 1'b0;
|
||||
if(rf_en==1'b1)
|
||||
state <= 4'd0;
|
||||
else
|
||||
state <= 4'd2;
|
||||
end
|
||||
4'd2:begin
|
||||
cfgdata <= regdata;
|
||||
cnt_bits <= 6'd0;
|
||||
state <= 4'd3;
|
||||
end
|
||||
4'd3:begin
|
||||
spi_csb <= 1'b0;
|
||||
spi_sdo <= cfgdata[DATA_WIDTH-1];
|
||||
cfgdata <= cfgdata << 1'b1;
|
||||
cnt_bits <= cnt_bits + 1'b1;
|
||||
if(cnt_bits == DATA_WIDTH-1)begin
|
||||
state <= 4'd4;
|
||||
cnt_word <= cnt_word + 1'b1;
|
||||
end
|
||||
cnt_lock <= 32'd0;
|
||||
end
|
||||
4'd4:begin
|
||||
spi_csb <= 1'b1;
|
||||
spi_sdo <= 1'b0;
|
||||
cnt_lock <= 32'd0;
|
||||
cnt_bits <= 32'd0;
|
||||
if(cnt_word == DATA_LENTH)begin
|
||||
state <= 4'd5;
|
||||
end
|
||||
else
|
||||
state <= 4'd1;
|
||||
end
|
||||
4'd5:begin
|
||||
if(cnt_lock>=40000 || pll_locked)begin
|
||||
cnt_lock <= 32'd0 ;
|
||||
state <= 4'd6 ;
|
||||
end
|
||||
else begin
|
||||
cnt_lock <=cnt_lock+1'b1;
|
||||
state <= state ;
|
||||
end
|
||||
end
|
||||
4'd6:begin
|
||||
cnt_word <= 7'd0;
|
||||
if(pll_locked)
|
||||
state <= 4'd7 ;
|
||||
else
|
||||
state <= 4'b1 ;
|
||||
end
|
||||
//----------------------------------------------------------------
|
||||
4'd7:begin//IDLE
|
||||
cnt_word <= DATA_LENTH;
|
||||
spi_csb <= 1'b1;
|
||||
spi_sdo <= 1'b0;
|
||||
cnt_bits <= 6'd0;
|
||||
cfgover <= 1'b0;
|
||||
if(rf_en==4'b1)
|
||||
state <= state;
|
||||
else if(rf_en==4'b0 && rf_en_r==4'b1 )
|
||||
state <= 4'd0;
|
||||
else if(hop_en==2'b10 || cnt_locked==WAIT_ld )
|
||||
state <= 4'd8;
|
||||
else if(CAL_F_R==3'b011 && (pre_fre_code!=fre_code))//打开RF_OUT
|
||||
state <= 4'd12;
|
||||
else
|
||||
state <= state;
|
||||
end
|
||||
4'd8:begin
|
||||
spi_csb <= 1'b1;
|
||||
spi_sdo <= 1'b0;
|
||||
state <= 4'd9;
|
||||
end
|
||||
4'd9:begin
|
||||
cfgdata <= regdata;
|
||||
cnt_bits <= 6'd0;
|
||||
state <= 4'd10;
|
||||
end
|
||||
4'd10:begin
|
||||
spi_csb <= 1'b0;
|
||||
spi_sdo <= cfgdata[DATA_WIDTH-1];
|
||||
cfgdata <= cfgdata << 1'b1;
|
||||
cnt_bits <= cnt_bits + 1'b1;
|
||||
if(cnt_bits == DATA_WIDTH-1)begin
|
||||
state <= 4'd11;
|
||||
cnt_word <= cnt_word + 1'b1;
|
||||
end
|
||||
end
|
||||
4'd11:begin
|
||||
spi_csb <= 1'b1;
|
||||
spi_sdo <= 1'b0;
|
||||
cnt_lock <= 32'd0;
|
||||
cnt_bits <= 32'd0;
|
||||
if(cnt_word == 8'd85)begin
|
||||
state <= 4'd7;
|
||||
end
|
||||
else
|
||||
state <= 4'd8;
|
||||
end
|
||||
4'd12:begin
|
||||
spi_csb <= 1'b1;
|
||||
spi_sdo <= 1'b0;
|
||||
state <= 4'd13;
|
||||
end
|
||||
4'd13:begin
|
||||
cnt_bits <= 6'd0;
|
||||
state <= 4'd14;
|
||||
if(ceshi_model==4'ha)
|
||||
cfgdata<={16'h0025,8'h13};
|
||||
else if(ceshi_model==4'hb)
|
||||
cfgdata<={16'h0025,8'h00};
|
||||
else if(SW_PLL)
|
||||
cfgdata<={16'h0025,8'h13};
|
||||
else
|
||||
cfgdata<={16'h0025,8'h00};
|
||||
end
|
||||
4'd14:begin
|
||||
spi_csb <= 1'b0;
|
||||
spi_sdo <= cfgdata[DATA_WIDTH-1];
|
||||
cfgdata <= cfgdata << 1'b1;
|
||||
cnt_bits <= cnt_bits + 1'b1;
|
||||
if(cnt_bits == DATA_WIDTH-1)begin
|
||||
state <= 4'd7;
|
||||
cfgover <= 1'b1;
|
||||
cnt_word <= cnt_word ;
|
||||
end
|
||||
end
|
||||
|
||||
//&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#//
|
||||
default: begin
|
||||
spi_csb <= 1'b1;
|
||||
state <= 4'd0;
|
||||
cnt_lock <= 32'd0;
|
||||
cnt_word <= 8'd0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge sysclk,negedge arstn)
|
||||
begin
|
||||
if(!arstn)
|
||||
regdata <= {16'h0000,8'h18 };
|
||||
else case(cnt_word)
|
||||
8'd0 : regdata <= {16'h0000,8'h18 };
|
||||
8'd1 : regdata <= {16'h0001,8'h00 };
|
||||
8'd2 : regdata <= {16'h0003,8'h00 };
|
||||
8'd3 : regdata <= {16'h0004,8'h00 };
|
||||
8'd4 : regdata <= {16'h0005,8'h00 };
|
||||
8'd5 : regdata <= {16'h0006,8'hFF };
|
||||
8'd6 : regdata <= {16'h000C,8'h00 };
|
||||
8'd7 : regdata <= {16'h000D,8'h00 };
|
||||
8'd8 : regdata <= {16'h0010 ,INT[7:0] } ;
|
||||
8'd9 : regdata <= {16'h0011 ,INT[15:8] } ;
|
||||
8'd10 : regdata <= {16'h0012,8'h00 };//[6]No Autocalibration
|
||||
//8'd10 : regdata <= {16'h0012,8'h40 };//[6]Autocalibration
|
||||
8'd11 : regdata <= {16'h0014 ,FRAC1[7:0]} ;
|
||||
8'd12 : regdata <= {16'h0015 ,FRAC1[15:8]} ;
|
||||
8'd13 : regdata <= {16'h0016 ,FRAC1[23:16]} ;
|
||||
8'd14 : regdata <= {16'h0017 ,FRAC2[6:0],FRAC1[24]} ;
|
||||
8'd15 : regdata <= {16'h0018 ,1'b0,FRAC2[13:7] } ;
|
||||
8'd16 : regdata <= {16'h0019 ,MOD2[7:0]} ;
|
||||
8'd17 : regdata <= {16'h001A ,2'b0,MOD2[13:8]} ;
|
||||
8'd18 : regdata <= {16'h001B,8'h00 };
|
||||
8'd19 : regdata <= {16'h001C,8'h00 };
|
||||
8'd20 : regdata <= {16'h001D,8'h00 };
|
||||
8'd21 : regdata <= {16'h001E,8'h18 };//CP_CURRENT 电荷泵
|
||||
// 8'd21 : regdata <= { 16'h001E,cp,4'h8 };//CP_CURRENT 电荷泵
|
||||
8'd22 : regdata <= { 16'h001F,4'h0,R_DIV };//R DIV R分频器
|
||||
8'd23 : regdata <= {16'h0020,8'h1c };//digital lock detect 数字锁定ld
|
||||
8'd24 : regdata <= {16'h0021,8'h00 };
|
||||
8'd25 : regdata <= {16'h0022,D,4'd0 };//[4]2分频 [5]double 2倍频器
|
||||
8'd26 : regdata <= {16'h0023,8'h00 };
|
||||
8'd27 : regdata <= {16'h0024,8'h80 };//Fout_clk DIV_SEL
|
||||
8'd28 : regdata <= {16'h0025,8'h13 };//X4_EN
|
||||
8'd29 : regdata <= {16'h0026,8'h1F };
|
||||
8'd30 : regdata <= {16'h0027,8'hCD };
|
||||
//8'd30 : regdata <= {16'h0027,8'hCD };
|
||||
8'd31 : regdata <= {16'h0028,8'h83 };
|
||||
8'd32 : regdata <= {16'h002A,8'h00 };
|
||||
8'd33 : regdata <= {16'h002B,8'h00 };
|
||||
8'd34 : regdata <= {16'h002C,8'h44 };
|
||||
8'd35 : regdata <= {16'h002D,8'h11 };
|
||||
8'd36 : regdata <= {16'h002E,8'h12 };
|
||||
8'd37 : regdata <= {16'h002F,8'h94 };
|
||||
8'd38 : regdata <= {16'h0030,8'h2A };
|
||||
8'd39 : regdata <= {16'h0031,8'h02 };
|
||||
8'd40 : regdata <= {16'h0032,8'h04 };
|
||||
8'd41 : regdata <= {16'h0033,8'h22 };
|
||||
8'd42 : regdata <= {16'h0034,8'h25 };
|
||||
8'd43 : regdata <= {16'h0035,8'hFA };
|
||||
8'd44 : regdata <= {16'h0036,8'h30 };
|
||||
8'd45 : regdata <= {16'h0037,SI_BAND_SEL} ;//VCO频段
|
||||
8'd46 : regdata <= {16'h0038,SI_VCO_SEL_BIAS_CODE };//[7:4]=VCO内核,[3:0]VCO偏置
|
||||
8'd47 : regdata <= {16'h0039,8'h07 };
|
||||
8'd48 : regdata <= {16'h003A,8'h55 };
|
||||
8'd49 : regdata <= {16'h003D,8'h00 };
|
||||
8'd50 : regdata <= {16'h003E,8'h0C };
|
||||
8'd51 : regdata <= {16'h003F,8'h80 };
|
||||
8'd52 : regdata <= {16'h0040,8'h50 };
|
||||
8'd53 : regdata <= {16'h0041,8'h28 };
|
||||
8'd54 : regdata <= {16'h0042,8'h00 };
|
||||
8'd55 : regdata <= {16'h0043,8'h00 };
|
||||
8'd56 : regdata <= {16'h0044,8'h00 };
|
||||
8'd57 : regdata <= {16'h0045,8'h00 };
|
||||
8'd58 : regdata <= {16'h0046,8'h00 };
|
||||
8'd59 : regdata <= {16'h0047,8'hC0 };
|
||||
8'd60 : regdata <= {16'h0052,8'hF4 };
|
||||
8'd61 : regdata <= {16'h006C,8'h00 };
|
||||
8'd62 : regdata <= {16'h006E,8'h00 };
|
||||
8'd63 : regdata <= {16'h006F,8'h00 };
|
||||
8'd64 : regdata <= {16'h0070,8'hE3 };
|
||||
8'd65 : regdata <= {16'h0071,8'h60 };
|
||||
8'd66 : regdata <= {16'h0072,8'h32 };
|
||||
8'd67 : regdata <= {16'h0073,8'h00 };
|
||||
8'd68 : regdata <= {16'h0079,8'h00 };
|
||||
8'd69 : regdata <= {16'h007A,8'h00 };
|
||||
8'd70 : regdata <= {16'h007B,8'h00 };
|
||||
8'd71 : regdata <= {16'h007C,8'h00 };
|
||||
|
||||
//跳频
|
||||
8'd72:regdata <= { 16'h0022,D,4'd0 };//double D倍频器
|
||||
8'd73:regdata <= { 16'h001F,4'h0,R_DIV };//R DIV R分频器
|
||||
8'd74:regdata <= { 16'h001A ,2'b0,MOD2[13:8] } ;
|
||||
8'd75:regdata <= { 16'h0019 ,MOD2[7:0] } ;
|
||||
8'd76:regdata <= { 16'h0018 ,1'b0,FRAC2[13:7] } ;
|
||||
8'd77:regdata <= { 16'h0017 ,FRAC2[6:0],FRAC1[24] } ;
|
||||
8'd78:regdata <= { 16'h0016 ,FRAC1[23:16] } ;
|
||||
8'd79:regdata <= { 16'h0015 ,FRAC1[15:8] } ;
|
||||
8'd80:regdata <= { 16'h0014 ,FRAC1[7:0] } ;
|
||||
8'd81:regdata <= { 16'h0037 ,SI_BAND_SEL } ;
|
||||
8'd82:regdata <= { 16'h0038 ,SI_VCO_SEL_BIAS_CODE } ;
|
||||
8'd83:regdata <= { 16'h0011 ,INT[15:8] } ;
|
||||
8'd84:regdata <= { 16'h0010 ,INT[7:0] } ;
|
||||
|
||||
default: regdata <= regdata;
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
+622
@@ -0,0 +1,622 @@
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2021/8/13 00:24:20
|
||||
// Design Name:
|
||||
// Module Name: LMX2595
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
|
||||
// fRFOUT= (INT+ (FRAC1+FRAC2/MOD2)/MOD1)× (fPFD/R)
|
||||
// fPFD = fPFD = REFIN × ((1 + D)/(R × (1 + T)))
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module adf4371_b(//20.375Ghz ~ 23.875Ghz
|
||||
input sysclk ,//40MHZ
|
||||
input arstn ,
|
||||
output cs ,
|
||||
input mux_out ,
|
||||
output sclk ,
|
||||
output sdio ,
|
||||
input [3:0] rf_en ,
|
||||
input CAL_F ,
|
||||
input SW_PLL ,
|
||||
input i_cfgover ,
|
||||
input [3:0] ceshi_model ,
|
||||
input adf4371_hop ,
|
||||
input[11:0] fre_code
|
||||
);
|
||||
|
||||
localparam DATA_WIDTH = 24 ;
|
||||
localparam DATA_LENTH = 72 ;
|
||||
localparam WAIT_ld = 40000 ;
|
||||
//***********************************************************************************************************//
|
||||
reg[7:0] cnt_word = 8'd0 ;
|
||||
reg csb_reg = 1'b1 ;
|
||||
reg[5:0] cnt_bits = 6'd0 ;
|
||||
reg[DATA_WIDTH-1:0] cfgdata = 0, regdata = 0 ;
|
||||
reg[3:0] state = 4'b000 ;
|
||||
reg spi_sdo = 1'b0, spi_csb = 1'b1;
|
||||
wire pll_locked ;
|
||||
reg[31:0] cnt_lock = 32'd0 ;
|
||||
reg[31:0] cnt_locked = 32'd0 ;
|
||||
wire[15:0] band ;
|
||||
|
||||
//-----------------------------------
|
||||
assign pll_locked = mux_out ;
|
||||
assign sclk = spi_csb ? 1'b0 : ~sysclk ;
|
||||
assign cs = spi_csb & csb_reg ;
|
||||
assign sdio = spi_sdo ;
|
||||
//-----------------------------------
|
||||
|
||||
wire [7:0] SI_BAND_SEL ; //VCO频段
|
||||
wire [7:0] SI_VCO_SEL_BIAS_CODE ; //[7:4]=VCO内核, [3:0]=VCO偏置
|
||||
reg[13:0] MOD2 ;
|
||||
reg[13:0] FRAC2 ;
|
||||
reg[24:0] FRAC1 ;
|
||||
reg[15:0] INT ;
|
||||
|
||||
assign SI_BAND_SEL = band[15:8] ;
|
||||
assign SI_VCO_SEL_BIAS_CODE = band[7:0] ;
|
||||
|
||||
reg[2:0] hop_en;
|
||||
reg[15:0] code;
|
||||
reg[11:0] pre_fre_code;
|
||||
reg[3:0] cp_r;
|
||||
reg[3:0] rf_en_r;
|
||||
reg[2:0] CAL_F_R;
|
||||
|
||||
reg [3:0] R_DIV ;
|
||||
reg [3:0] D ;
|
||||
wire[13:0] douta3 ;
|
||||
wire[13:0] douta4 ;
|
||||
wire[24:0] douta2 ;
|
||||
wire[15:0] douta1 ;
|
||||
|
||||
//-----------------------------------
|
||||
INT_ROMb int_rom (
|
||||
.sysclk(sysclk),
|
||||
.addra(code),
|
||||
.douta(douta1)
|
||||
);
|
||||
|
||||
FRAC1 frac1_rom (
|
||||
.clka(sysclk),
|
||||
.addra(code),
|
||||
.douta(douta2)
|
||||
);
|
||||
|
||||
// FRAC1_ROM FRAC1_ROM (
|
||||
// .clka(sysclk), // input clka
|
||||
// .addra(code), // input [11 : 0] addra
|
||||
// .douta(douta2) // output [24 : 0] douta
|
||||
//);
|
||||
|
||||
frac2_rom frac2_rom (
|
||||
.sysclk(sysclk),
|
||||
.addra(code),
|
||||
.douta(douta4)
|
||||
);
|
||||
|
||||
mod2_rom mod2_rom (
|
||||
.sysclk(sysclk),
|
||||
.addra(code),
|
||||
.douta(douta3)
|
||||
);
|
||||
|
||||
|
||||
band_rom_b band_rom_b (
|
||||
.sysclk(sysclk),
|
||||
.addra(code),
|
||||
.douta(band) // output [15 : 0] douta
|
||||
);
|
||||
|
||||
//-------------------整数边界杂散用66.666666Mhz鉴相----------------------------------
|
||||
|
||||
always@(posedge sysclk,negedge arstn)
|
||||
begin
|
||||
if(!arstn)
|
||||
INT<=douta1;
|
||||
else if(code==24 || code==26 )
|
||||
INT<=76;
|
||||
else if(code==424 )
|
||||
INT<=77;
|
||||
else if(code==426 )
|
||||
INT<=78;
|
||||
else if(code==824 || code==826 )
|
||||
INT<=79;
|
||||
else if(code==1224)
|
||||
INT<=80;
|
||||
else if(code==1226 )
|
||||
INT<=81;
|
||||
else if(code==1624 || code==1626 )
|
||||
INT<=82;
|
||||
else if(code==2024 )
|
||||
INT<=83;
|
||||
else if(code==2026 )
|
||||
INT<=84;
|
||||
else if(code==2424 || code==2426 )
|
||||
INT<=85;
|
||||
else if(code==2824 )
|
||||
INT<=86;
|
||||
else if( code==2826 )
|
||||
INT<=87;
|
||||
else
|
||||
INT<=douta1;
|
||||
end
|
||||
|
||||
always@(posedge sysclk,negedge arstn)
|
||||
begin
|
||||
if(!arstn)
|
||||
FRAC1<=douta2;
|
||||
else if(code==24 )
|
||||
FRAC1<=16651386;
|
||||
else if(code==26 )
|
||||
FRAC1<=16903045;
|
||||
else if(code==424 )
|
||||
FRAC1<=33428602;
|
||||
else if(code==426 )
|
||||
FRAC1<=125829;
|
||||
else if(code==824 )
|
||||
FRAC1<=16651386;
|
||||
else if(code==826 )
|
||||
FRAC1<=16903045;
|
||||
else if(code==1224)
|
||||
FRAC1<=33428602;
|
||||
else if(code==1226 )
|
||||
FRAC1<=125829;
|
||||
else if(code==1624)
|
||||
FRAC1<=16651386;
|
||||
else if(code==1626 )
|
||||
FRAC1<=16903045;
|
||||
else if(code==2024 )
|
||||
FRAC1<=33428602;
|
||||
else if(code==2026 )
|
||||
FRAC1<=125829;
|
||||
else if(code==2424 )
|
||||
FRAC1<=16651386;
|
||||
else if(code==2426 )
|
||||
FRAC1<=16903045;
|
||||
else if(code==2824 )
|
||||
FRAC1<=33428602;
|
||||
else if( code==2826 )
|
||||
FRAC1<=125829;
|
||||
else
|
||||
FRAC1<=douta2;
|
||||
end
|
||||
|
||||
always@(posedge sysclk,negedge arstn)
|
||||
begin
|
||||
if(!arstn)
|
||||
MOD2<=douta3;
|
||||
else if(code==24 )
|
||||
MOD2<=25;
|
||||
else if(code==26 )
|
||||
MOD2<=25;
|
||||
else if(code==424 )
|
||||
MOD2<=25;
|
||||
else if(code==426 )
|
||||
MOD2<=25;
|
||||
else if(code==824 )
|
||||
MOD2<=25;
|
||||
else if(code==826 )
|
||||
MOD2<=25;
|
||||
else if(code==1224)
|
||||
MOD2<=25;
|
||||
else if(code==1226 )
|
||||
MOD2<=25;
|
||||
else if(code==1624)
|
||||
MOD2<=25;
|
||||
else if(code==1626 )
|
||||
MOD2<=25;
|
||||
else if(code==2024 )
|
||||
MOD2<=25;
|
||||
else if(code==2026 )
|
||||
MOD2<=25;
|
||||
else if(code==2424 )
|
||||
MOD2<=25;
|
||||
else if(code==2426 )
|
||||
MOD2<=25;
|
||||
else if(code==2824 )
|
||||
MOD2<=25;
|
||||
else if( code==2826 )
|
||||
MOD2<=25;
|
||||
else
|
||||
MOD2<=douta3;
|
||||
end
|
||||
|
||||
always@(posedge sysclk,negedge arstn)
|
||||
begin
|
||||
if(!arstn)
|
||||
FRAC2<=douta4;
|
||||
else if(code==24 )
|
||||
FRAC2<=22;
|
||||
else if(code==26 )
|
||||
FRAC2<=3;
|
||||
else if(code==424 )
|
||||
FRAC2<=22;
|
||||
else if(code==426 )
|
||||
FRAC2<=3;
|
||||
else if(code==824 )
|
||||
FRAC2<=22;
|
||||
else if(code==826 )
|
||||
FRAC2<=3;
|
||||
else if(code==1224)
|
||||
FRAC2<=22;
|
||||
else if(code==1226 )
|
||||
FRAC2<=3;
|
||||
else if(code==1624)
|
||||
FRAC2<=22;
|
||||
else if(code==1626 )
|
||||
FRAC2<=3;
|
||||
else if(code==2024 )
|
||||
FRAC2<=22;
|
||||
else if(code==2026 )
|
||||
FRAC2<=3;
|
||||
else if(code==2424 )
|
||||
FRAC2<=22;
|
||||
else if(code==2426 )
|
||||
FRAC2<=3;
|
||||
else if(code==2824 )
|
||||
FRAC2<=22;
|
||||
else if( code==2826 )
|
||||
FRAC2<=3;
|
||||
else
|
||||
FRAC2<=douta4;
|
||||
end
|
||||
|
||||
always@(posedge sysclk,negedge arstn)
|
||||
begin
|
||||
if(!arstn)begin
|
||||
R_DIV<=4'b1;
|
||||
D<=4'b0;
|
||||
end
|
||||
else if(code==24 || code==26 || code==424 || code==426 || code==824 || code==826|| code==1224 || code==1226 || code==1624 || code==1626 ||code==2024 || code==2026 ||code==2424 || code==2426 ||code==2824 || code==2826 )
|
||||
begin
|
||||
R_DIV<= 4'd3;
|
||||
D<=4'd2;
|
||||
end
|
||||
else
|
||||
begin
|
||||
R_DIV<=4'b1;
|
||||
D<=4'b0;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge sysclk,negedge arstn)begin
|
||||
if(~arstn)
|
||||
pre_fre_code<=11'h6d6;
|
||||
else if(CAL_F_R==3'b011)
|
||||
pre_fre_code<=fre_code;
|
||||
else
|
||||
pre_fre_code<=pre_fre_code;
|
||||
end
|
||||
|
||||
always@(posedge sysclk,negedge arstn)begin
|
||||
if(~arstn)
|
||||
code<=16'h6d6;
|
||||
else if(hop_en==2'b01)
|
||||
code<=fre_code;
|
||||
else
|
||||
code<=code;
|
||||
end
|
||||
|
||||
always@(posedge sysclk,negedge arstn)begin
|
||||
if(~arstn)begin
|
||||
hop_en <= 3'b0;
|
||||
CAL_F_R <= 3'b0;
|
||||
rf_en_r <= 4'b0;
|
||||
end
|
||||
else begin
|
||||
hop_en <= {hop_en[1:0],adf4371_hop};
|
||||
CAL_F_R <= {CAL_F_R[1:0],CAL_F};
|
||||
rf_en_r <= rf_en ;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge sysclk,negedge arstn)begin
|
||||
if(~arstn)
|
||||
csb_reg <= 1'b1;
|
||||
else
|
||||
csb_reg <= spi_csb;
|
||||
end
|
||||
|
||||
|
||||
always@(posedge sysclk,negedge arstn)begin
|
||||
if(~arstn)
|
||||
cnt_locked<=32'b0;
|
||||
else if(cnt_locked==WAIT_ld)
|
||||
cnt_locked<=32'b0;
|
||||
else if(!pll_locked)
|
||||
cnt_locked<=cnt_locked+1'b1;
|
||||
else
|
||||
cnt_locked<=32'b0;
|
||||
end
|
||||
|
||||
always@(posedge sysclk,negedge arstn)begin
|
||||
if(~arstn)begin
|
||||
cfgdata <= 0;
|
||||
cnt_word <= 7'd0;
|
||||
cnt_bits <= 6'd0;
|
||||
state <= 4'b0;
|
||||
cnt_lock <= 32'd0;
|
||||
spi_csb <= 1'b1;
|
||||
spi_sdo <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
case(state)
|
||||
4'd0:begin
|
||||
cnt_word <= 7'd0;
|
||||
if(rf_en==1'b1)
|
||||
state <= 4'd0;
|
||||
else if(cnt_lock >= 32'd6000)
|
||||
state <= 4'd1;
|
||||
else
|
||||
state <= state;
|
||||
|
||||
if(rf_en==1'b0)
|
||||
cnt_lock <= cnt_lock + 1'b1;
|
||||
else
|
||||
cnt_lock<=32'd0;
|
||||
|
||||
end
|
||||
4'd1:begin
|
||||
spi_csb <= 1'b1;
|
||||
spi_sdo <= 1'b0;
|
||||
state <= 4'd2;
|
||||
end
|
||||
4'd2:begin
|
||||
cfgdata <= regdata;
|
||||
cnt_bits <= 6'd0;
|
||||
state <= 4'd3;
|
||||
end
|
||||
4'd3:begin
|
||||
spi_csb <= 1'b0;
|
||||
spi_sdo <= cfgdata[DATA_WIDTH-1];
|
||||
cfgdata <= cfgdata << 1'b1;
|
||||
cnt_bits <= cnt_bits + 1'b1;
|
||||
if(cnt_bits == DATA_WIDTH-1)begin
|
||||
state <= 4'd4;
|
||||
cnt_word <= cnt_word + 1'b1;
|
||||
end
|
||||
cnt_lock <= 32'd0;
|
||||
end
|
||||
4'd4:begin
|
||||
spi_csb <= 1'b1;
|
||||
spi_sdo <= 1'b0;
|
||||
cnt_lock <= 32'd0;
|
||||
cnt_bits <= 32'd0;
|
||||
if(cnt_word == DATA_LENTH)begin
|
||||
state <= 4'd5;
|
||||
end
|
||||
else
|
||||
state <= 4'd1;
|
||||
end
|
||||
4'd5:begin
|
||||
if(cnt_lock>=40000 || pll_locked)begin
|
||||
cnt_lock <= 32'd0 ;
|
||||
state <= 4'd6 ;
|
||||
end
|
||||
else begin
|
||||
cnt_lock <=cnt_lock+1'b1;
|
||||
state <= state ;
|
||||
end
|
||||
end
|
||||
4'd6:begin
|
||||
cnt_word <= 7'd0;
|
||||
if(pll_locked)
|
||||
state <= 4'd7 ;
|
||||
else
|
||||
state <= 4'b1 ;
|
||||
end
|
||||
//&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#//
|
||||
4'd7:begin//IDLE
|
||||
cnt_word <= DATA_LENTH;
|
||||
spi_csb <= 1'b1;
|
||||
spi_sdo <= 1'b0;
|
||||
cnt_bits <= 6'd0;
|
||||
if(rf_en==4'b1)
|
||||
state <= state;
|
||||
else if(rf_en==4'b0 && rf_en_r==4'b1 )
|
||||
state <= 4'd0;
|
||||
else if(hop_en==2'b10 || cnt_locked==WAIT_ld )
|
||||
state <= 4'd8;
|
||||
//else if(CAL_F_R==3'b011 && (pre_fre_code!=fre_code))//打开RF_OUT
|
||||
else if(i_cfgover)
|
||||
state <= 4'd12;
|
||||
else
|
||||
state <= state;
|
||||
end
|
||||
4'd8:begin
|
||||
spi_csb <= 1'b1;
|
||||
spi_sdo <= 1'b0;
|
||||
state <= 4'd9;
|
||||
end
|
||||
4'd9:begin
|
||||
cfgdata <= regdata;
|
||||
cnt_bits <= 6'd0;
|
||||
state <= 4'd10;
|
||||
end
|
||||
4'd10:begin
|
||||
spi_csb <= 1'b0;
|
||||
spi_sdo <= cfgdata[DATA_WIDTH-1];
|
||||
cfgdata <= cfgdata << 1'b1;
|
||||
cnt_bits <= cnt_bits + 1'b1;
|
||||
if(cnt_bits == DATA_WIDTH-1)begin
|
||||
state <= 4'd11;
|
||||
cnt_word <= cnt_word + 1'b1;
|
||||
end
|
||||
end
|
||||
4'd11:begin
|
||||
spi_csb <= 1'b1;
|
||||
spi_sdo <= 1'b0;
|
||||
cnt_lock <= 32'd0;
|
||||
cnt_bits <= 32'd0;
|
||||
if(cnt_word == 8'd85)begin
|
||||
state <= 4'd7;
|
||||
end
|
||||
else
|
||||
state <= 4'd8;
|
||||
end
|
||||
4'd12:begin
|
||||
spi_csb <= 1'b1;
|
||||
spi_sdo <= 1'b0;
|
||||
state <= 4'd13;
|
||||
end
|
||||
4'd13:begin
|
||||
cnt_bits <= 6'd0;
|
||||
state <= 4'd14;
|
||||
if(ceshi_model==4'hb)
|
||||
cfgdata <= {16'h0025,8'h13};
|
||||
else if(ceshi_model==4'ha)
|
||||
cfgdata <= {16'h0025,8'h00};
|
||||
else if (SW_PLL)
|
||||
cfgdata <= {16'h0025,8'h00};
|
||||
else
|
||||
cfgdata <= {16'h0025,8'h13};
|
||||
end
|
||||
4'd14:begin
|
||||
spi_csb <= 1'b0;
|
||||
spi_sdo <= cfgdata[DATA_WIDTH-1];
|
||||
cfgdata <= cfgdata << 1'b1;
|
||||
cnt_bits <= cnt_bits + 1'b1;
|
||||
if(cnt_bits == DATA_WIDTH-1)begin
|
||||
state <= 4'd7;
|
||||
cnt_word <= cnt_word ;
|
||||
end
|
||||
end
|
||||
//&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#//
|
||||
default: begin
|
||||
spi_csb <= 1'b1;
|
||||
state <= 4'd0;
|
||||
cnt_lock <= 32'd0;
|
||||
cnt_word <= 8'd0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge sysclk,negedge arstn)
|
||||
begin
|
||||
if(!arstn)
|
||||
regdata <= {16'h0000,8'h18 };
|
||||
else case(cnt_word)
|
||||
8'd0 : regdata <= {16'h0000,8'h18 };
|
||||
8'd1 : regdata <= {16'h0001,8'h00 };
|
||||
8'd2 : regdata <= {16'h0003,8'h00 };
|
||||
8'd3 : regdata <= {16'h0004,8'h00 };
|
||||
8'd4 : regdata <= {16'h0005,8'h00 };
|
||||
8'd5 : regdata <= {16'h0006,8'hFF };
|
||||
8'd6 : regdata <= {16'h000C,8'h00 };
|
||||
8'd7 : regdata <= {16'h000D,8'h00 };
|
||||
8'd8 : regdata <= {16'h0010 ,INT[7:0] } ;
|
||||
8'd9 : regdata <= {16'h0011 ,INT[15:8] } ;
|
||||
8'd10 : regdata <= {16'h0012,8'h00 };//[6]Autocalibration
|
||||
//8'd10 : regdata <= {16'h0012,8'h40 };//[6]Autocalibration
|
||||
8'd11 : regdata <= {16'h0014 ,FRAC1[7:0]} ;
|
||||
8'd12 : regdata <= {16'h0015 ,FRAC1[15:8]} ;
|
||||
8'd13 : regdata <= {16'h0016 ,FRAC1[23:16]} ;
|
||||
8'd14 : regdata <= {16'h0017 ,FRAC2[6:0],FRAC1[24]} ;
|
||||
8'd15 : regdata <= {16'h0018 ,1'b0,FRAC2[13:7] } ;
|
||||
8'd16 : regdata <= {16'h0019 ,MOD2[7:0]} ;
|
||||
8'd17 : regdata <= {16'h001A ,2'b0,MOD2[13:8]} ;
|
||||
8'd18 : regdata <= {16'h001B,8'h00 };
|
||||
8'd19 : regdata <= {16'h001C,8'h00 };
|
||||
8'd20 : regdata <= {16'h001D,8'h00 };
|
||||
8'd21 : regdata <= {16'h001E,8'h18 };//CP_CURRENT 电荷泵
|
||||
//8'd21 : regdata <= {16'h001E,cp,4'h8 };//CP_CURRENT 电荷泵
|
||||
8'd22 : regdata <= { 16'h001F,4'h0,R_DIV };//R DIV R分频器
|
||||
8'd23 : regdata <= {16'h0020,8'h1c };//digital lock detect 数字锁定ld
|
||||
8'd24 : regdata <= {16'h0021,8'h00 };
|
||||
8'd25 : regdata <= { 16'h0022,D,4'd0 };//double D倍频器
|
||||
8'd26 : regdata <= {16'h0023,8'h00 };
|
||||
8'd27 : regdata <= {16'h0024,8'h80 };//DIV_SEL
|
||||
8'd28 : regdata <= {16'h0025,8'h13 };//X4_EN
|
||||
8'd29 : regdata <= {16'h0026,8'h1F };
|
||||
8'd30 : regdata <= {16'h0027,8'hCD };
|
||||
//8'd30 : regdata <= {16'h0027,8'hCD };
|
||||
8'd31 : regdata <= {16'h0028,8'h83 };
|
||||
8'd32 : regdata <= {16'h002A,8'h00 };
|
||||
8'd33 : regdata <= {16'h002B,8'h00 };
|
||||
8'd34 : regdata <= {16'h002C,8'h44 };
|
||||
8'd35 : regdata <= {16'h002D,8'h11 };
|
||||
8'd36 : regdata <= {16'h002E,8'h12 };
|
||||
8'd37 : regdata <= {16'h002F,8'h94 };
|
||||
8'd38 : regdata <= {16'h0030,8'h2A };
|
||||
8'd39 : regdata <= {16'h0031,8'h02 };
|
||||
8'd40 : regdata <= {16'h0032,8'h04 };
|
||||
8'd41 : regdata <= {16'h0033,8'h22 };
|
||||
8'd42 : regdata <= {16'h0034,8'h25 };
|
||||
8'd43 : regdata <= {16'h0035,8'hFA };
|
||||
8'd44 : regdata <= {16'h0036,8'h30 };
|
||||
8'd45 : regdata <= {16'h0037,SI_BAND_SEL} ;//VCO频段
|
||||
8'd46 : regdata <= {16'h0038,SI_VCO_SEL_BIAS_CODE };//[7:4]=VCO内核,[3:0]VCO偏置
|
||||
8'd47 : regdata <= {16'h0039,8'h07 };
|
||||
8'd48 : regdata <= {16'h003A,8'h55 };
|
||||
8'd49 : regdata <= {16'h003D,8'h00 };
|
||||
8'd50 : regdata <= {16'h003E,8'h0C };
|
||||
8'd51 : regdata <= {16'h003F,8'h80 };
|
||||
8'd52 : regdata <= {16'h0040,8'h50 };
|
||||
8'd53 : regdata <= {16'h0041,8'h28 };
|
||||
8'd54 : regdata <= {16'h0042,8'h00 };
|
||||
8'd55 : regdata <= {16'h0043,8'h00 };
|
||||
8'd56 : regdata <= {16'h0044,8'h00 };
|
||||
8'd57 : regdata <= {16'h0045,8'h00 };
|
||||
8'd58 : regdata <= {16'h0046,8'h00 };
|
||||
8'd59 : regdata <= {16'h0047,8'hC0 };
|
||||
8'd60 : regdata <= {16'h0052,8'hF4 };
|
||||
8'd61 : regdata <= {16'h006C,8'h00 };
|
||||
8'd62 : regdata <= {16'h006E,8'h00 };
|
||||
8'd63 : regdata <= {16'h006F,8'h00 };
|
||||
8'd64 : regdata <= {16'h0070,8'hE3 };
|
||||
8'd65 : regdata <= {16'h0071,8'h60 };
|
||||
8'd66 : regdata <= {16'h0072,8'h32 };
|
||||
8'd67 : regdata <= {16'h0073,8'h00 };
|
||||
8'd68 : regdata <= {16'h0079,8'h00 };
|
||||
8'd69 : regdata <= {16'h007A,8'h00 };
|
||||
8'd70 : regdata <= {16'h007B,8'h00 };
|
||||
8'd71 : regdata <= {16'h007C,8'h00 };
|
||||
|
||||
//跳频
|
||||
8'd72:regdata <= { 16'h0022,D,4'd0 };//double D倍频器
|
||||
8'd73:regdata <= { 16'h001F,4'h0,R_DIV };//R DIV R分频器
|
||||
8'd74:regdata <= { 16'h001A ,2'b0,MOD2[13:8] } ;
|
||||
8'd75:regdata <= { 16'h0019 ,MOD2[7:0] } ;
|
||||
8'd76:regdata <= { 16'h0018 ,1'b0,FRAC2[13:7] } ;
|
||||
8'd77:regdata <= { 16'h0017 ,FRAC2[6:0],FRAC1[24] } ;
|
||||
8'd78:regdata <= { 16'h0016 ,FRAC1[23:16] } ;
|
||||
8'd79:regdata <= { 16'h0015 ,FRAC1[15:8] } ;
|
||||
8'd80:regdata <= { 16'h0014 ,FRAC1[7:0] } ;
|
||||
8'd81:regdata <= { 16'h0037 ,SI_BAND_SEL } ;
|
||||
8'd82:regdata <= { 16'h0038 ,SI_VCO_SEL_BIAS_CODE } ;
|
||||
8'd83:regdata <= { 16'h0011 ,INT[15:8] } ;
|
||||
8'd84:regdata <= { 16'h0010 ,INT[7:0] } ;
|
||||
|
||||
default: regdata <= regdata;
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
+3573
File diff suppressed because it is too large
Load Diff
+3573
File diff suppressed because it is too large
Load Diff
+368
@@ -0,0 +1,368 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 13:59:21 10/19/2020
|
||||
// Design Name:
|
||||
// Module Name: DS18B20
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
|
||||
//+125 0000 0111 1101 0000 07D0h
|
||||
//+85* 0000 0101 0101 0000 0550h
|
||||
//+25.0625 0000 0001 1001 0001 0191h
|
||||
//+10.125 0000 0000 1010 0010 00A2h
|
||||
//+0.5 0000 0000 0000 1000 0008h
|
||||
//0 0000 0000 0000 0000 0000h
|
||||
//-0.5 1111 1111 1111 1000 FFF8h
|
||||
//-10.125 1111 1111 0101 1110 FF5Eh
|
||||
//-25.0625 1111 1110 0110 1111 FE6Fh
|
||||
//-55 1111 1100 1001 0000 FC90h
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module ds18b20_temp(
|
||||
input clk , //40_000_000
|
||||
input rstn ,
|
||||
inout dq ,
|
||||
output reg signed[15:0] temp_data //LSB =0.625 C
|
||||
);
|
||||
|
||||
parameter FRE = 40 ;// //clk为40M时钟，若clk为50M，则 FRE=50；
|
||||
|
||||
parameter INIT = 3'b000 , //Gray code
|
||||
WR_CMD = 3'b001 ,
|
||||
WAIT = 3'b011 ,
|
||||
INIT_AGAIN = 3'b010 ,
|
||||
RD_CMD = 3'b110 ,
|
||||
RD_TEMP = 3'b111 ;
|
||||
|
||||
localparam WR_CC_44 = 16'h44cc ;
|
||||
localparam WR_CC_BE = 16'hbecc ;
|
||||
localparam cnt_max = FRE[31:1]-1 ;
|
||||
localparam WAIT_TEMP_CNT = 20'd750_000 ;//750ms
|
||||
|
||||
reg flag ;
|
||||
reg [15:0] data_reg ;
|
||||
reg [2:0] state ;
|
||||
reg clk_1us ;
|
||||
reg [31:0] cnt_1us ;
|
||||
reg dq_en ;
|
||||
reg dq_reg ;
|
||||
reg [19:0] cnt ;
|
||||
reg [3:0] bit_cnt ;
|
||||
|
||||
assign dq = dq_en ? dq_reg : 1'bz;
|
||||
|
||||
always@(posedge clk,negedge rstn)
|
||||
if(!rstn)
|
||||
cnt_1us<=32'b0;
|
||||
else if(cnt_1us==cnt_max)
|
||||
cnt_1us<=32'b0;
|
||||
else
|
||||
cnt_1us<=cnt_1us+1'b1;
|
||||
|
||||
always@(posedge clk,negedge rstn)
|
||||
if(!rstn)
|
||||
clk_1us<=1'b0;
|
||||
else if(cnt_1us==cnt_max)
|
||||
clk_1us<=~clk_1us;
|
||||
else
|
||||
clk_1us<=clk_1us;
|
||||
|
||||
always@(posedge clk_1us,negedge rstn)
|
||||
if(!rstn)
|
||||
begin
|
||||
dq_en <=1'b1;
|
||||
dq_reg <=1'b0;
|
||||
state <=INIT;
|
||||
cnt <=20'd0;
|
||||
flag <=1'b0;
|
||||
bit_cnt <=4'b0;
|
||||
data_reg <=16'd0;
|
||||
temp_data<=12'b0;
|
||||
end
|
||||
else case(state)
|
||||
INIT :begin
|
||||
//if(cnt==16'd999)begin //for sim
|
||||
if(cnt==16'd9999)
|
||||
cnt <=20'd0;
|
||||
else if(cnt==16'd999&&flag)begin
|
||||
cnt <=20'd0;
|
||||
state<=WR_CMD;
|
||||
end
|
||||
else begin
|
||||
cnt <=cnt+1'd1;
|
||||
state<=INIT;
|
||||
end
|
||||
//------------------
|
||||
if(cnt==16'd9999)begin
|
||||
dq_en <=1'b1;
|
||||
dq_reg<=1'b0;
|
||||
end
|
||||
//else if(cnt==16'd499)begin
|
||||
else if(cnt==16'd599)begin
|
||||
dq_en <=1'b0;
|
||||
dq_reg<=1'b0;
|
||||
end
|
||||
else begin
|
||||
dq_en <=dq_en;
|
||||
dq_reg<=dq_reg;
|
||||
end
|
||||
//------------------
|
||||
// if(cnt==20'd570)//&&dq==1'b0)
|
||||
if(cnt==20'd670)//&&dq==1'b0)
|
||||
flag<= ~dq;
|
||||
else if(cnt==20'd999)
|
||||
flag<=1'b0;
|
||||
else
|
||||
flag<=flag;
|
||||
end
|
||||
/* INIT :begin
|
||||
//if(cnt==16'd999)begin //for sim
|
||||
if(cnt==16'd999&&flag)begin
|
||||
cnt <=20'd0;
|
||||
state<=WR_CMD;
|
||||
end
|
||||
else begin
|
||||
cnt <=cnt+1'd1;
|
||||
state<=INIT;
|
||||
end
|
||||
//------------------
|
||||
if(cnt==16'd499)begin
|
||||
dq_en <=1'b0;
|
||||
dq_reg<=1'b0;
|
||||
end
|
||||
else begin
|
||||
dq_en <=dq_en;
|
||||
dq_reg<=dq_reg;
|
||||
end
|
||||
//------------------
|
||||
if(cnt==20'd570)//&&dq==1'b0)
|
||||
flag<= ~dq;
|
||||
else if(cnt==20'd999)
|
||||
flag<=1'b0;
|
||||
else
|
||||
flag<=flag;
|
||||
end */
|
||||
WR_CMD :begin
|
||||
if(cnt==20'd64 && bit_cnt==4'd15)
|
||||
begin
|
||||
bit_cnt<=4'd0;
|
||||
state<=WAIT;
|
||||
end
|
||||
else if(cnt==20'd64)
|
||||
begin
|
||||
bit_cnt<=bit_cnt+1'd1;
|
||||
state<=WR_CMD;
|
||||
end
|
||||
else
|
||||
begin
|
||||
bit_cnt<=bit_cnt;
|
||||
state<=WR_CMD;
|
||||
end
|
||||
//------------------
|
||||
if(cnt==20'd64 && bit_cnt==4'd15)
|
||||
cnt<=20'd0;
|
||||
else if(cnt==20'd64)
|
||||
cnt<=20'd0;
|
||||
else
|
||||
cnt<=cnt+1'd1;
|
||||
//------------------
|
||||
if(WR_CC_44[bit_cnt]==1'b0 && cnt<=20'd62)
|
||||
begin
|
||||
dq_en <=1'b1;
|
||||
dq_reg<=1'b0;
|
||||
end
|
||||
else if(WR_CC_44[bit_cnt]==1'b1 && cnt<=20'd1)
|
||||
begin
|
||||
dq_en <=1'b1;
|
||||
dq_reg<=1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
dq_en <=1'b0;
|
||||
dq_reg<=1'b0;
|
||||
end
|
||||
end
|
||||
WAIT : if(cnt==WAIT_TEMP_CNT)
|
||||
begin
|
||||
dq_en <=1'b1;
|
||||
dq_reg<=1'b0;
|
||||
cnt<=20'd0;
|
||||
state<=INIT_AGAIN;
|
||||
end
|
||||
else
|
||||
begin
|
||||
dq_en <=1'b1;
|
||||
dq_reg<=1'b1;
|
||||
cnt<=cnt+1'd1;
|
||||
state<=WAIT;
|
||||
end
|
||||
INIT_AGAIN :begin
|
||||
if(cnt==16'd999&&flag)
|
||||
//if(cnt==16'd999) //for sim
|
||||
begin
|
||||
cnt <=20'd0;
|
||||
state<=RD_CMD;
|
||||
end
|
||||
else
|
||||
begin
|
||||
cnt <=cnt+1'd1;
|
||||
state<=INIT_AGAIN;
|
||||
end
|
||||
//------------------
|
||||
if(cnt==16'd499)
|
||||
begin
|
||||
dq_en <=1'b0;
|
||||
dq_reg<=1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
dq_en <=dq_en;
|
||||
dq_reg<=dq_reg;
|
||||
end
|
||||
//------------------
|
||||
if(cnt==20'd570)//&&dq==1'b0)
|
||||
flag<=~dq;
|
||||
else if(cnt==20'd999)
|
||||
flag<=1'b0;
|
||||
else
|
||||
flag<=flag;
|
||||
end
|
||||
RD_CMD :begin
|
||||
if(cnt==20'd64 && bit_cnt==4'd15)
|
||||
begin
|
||||
bit_cnt<=4'd0;
|
||||
state<=RD_TEMP;
|
||||
end
|
||||
else if(cnt==20'd64)
|
||||
begin
|
||||
bit_cnt<=bit_cnt+1'd1;
|
||||
state<=RD_CMD;
|
||||
end
|
||||
else
|
||||
begin
|
||||
bit_cnt<=bit_cnt;
|
||||
state<=RD_CMD;
|
||||
end
|
||||
//------------------
|
||||
if(cnt==20'd64 && bit_cnt==4'd15)
|
||||
cnt<=20'd0;
|
||||
else if(cnt==20'd64)
|
||||
cnt<=20'd0;
|
||||
else
|
||||
cnt<=cnt+1'd1;
|
||||
//------------------
|
||||
if(WR_CC_BE[bit_cnt]==1'b0 && cnt<=20'd62)
|
||||
begin
|
||||
dq_en <=1'b1;
|
||||
dq_reg<=1'b0;
|
||||
end
|
||||
else if(WR_CC_BE[bit_cnt]==1'b1 && cnt<=20'd1)
|
||||
begin
|
||||
dq_en <=1'b1;
|
||||
dq_reg<=1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
dq_en <=1'b0;
|
||||
dq_reg<=1'b0;
|
||||
end
|
||||
end
|
||||
RD_TEMP :begin
|
||||
if(cnt==20'd64 && bit_cnt==4'd15)
|
||||
cnt <=20'd0;
|
||||
else if(cnt==20'd64)
|
||||
cnt<=20'd0;
|
||||
else
|
||||
cnt<=cnt+1'd1;
|
||||
//------------------
|
||||
if(cnt<=20'd1|| (cnt==20'd64 && bit_cnt==4'd15))
|
||||
begin
|
||||
dq_en <=1'b1;
|
||||
dq_reg<=1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
dq_en <=1'b0;
|
||||
dq_reg<=1'b0;
|
||||
end
|
||||
//------------------
|
||||
if(cnt==20'd64 && bit_cnt==4'd15)
|
||||
begin
|
||||
bit_cnt<=4'd0;
|
||||
state<=INIT;
|
||||
end
|
||||
else if(cnt==20'd64)
|
||||
begin
|
||||
bit_cnt<=bit_cnt+1'd1;
|
||||
state<=RD_TEMP;
|
||||
end
|
||||
else
|
||||
begin
|
||||
bit_cnt<=bit_cnt;
|
||||
state<=RD_TEMP;
|
||||
end
|
||||
//------------------
|
||||
if(cnt==20'd8)
|
||||
data_reg<={dq,data_reg[15:1]};
|
||||
else
|
||||
data_reg<=data_reg;
|
||||
//------------------
|
||||
if(cnt==20'd64 && bit_cnt==4'd15)
|
||||
temp_data<=data_reg;
|
||||
else
|
||||
temp_data<=temp_data;
|
||||
end
|
||||
default: state<=INIT;
|
||||
endcase
|
||||
|
||||
|
||||
/* wire[33:0]SYNC_OUT;
|
||||
wire[35:0]CONTROL0;
|
||||
wire[35:0]CONTROL1;
|
||||
wire[149:0]TRIG0;
|
||||
|
||||
vio u_vio (
|
||||
.CONTROL (CONTROL0), // INOUT BUS [35:0]
|
||||
.CLK (clk), // IN
|
||||
.SYNC_OUT (SYNC_OUT) // OUT BUS [33:0]
|
||||
);
|
||||
|
||||
|
||||
icon u_icon (
|
||||
.CONTROL0 (CONTROL0), // INOUT BUS [35:0]
|
||||
.CONTROL1 (CONTROL1) // INOUT BUS [35:0]
|
||||
);
|
||||
|
||||
|
||||
ila u_ila (
|
||||
.CONTROL (CONTROL1), // INOUT BUS [35:0]
|
||||
.CLK (clk), // IN
|
||||
.TRIG0 (TRIG0) // IN BUS [39:0]
|
||||
);
|
||||
|
||||
|
||||
assign TRIG0[2:0] = state ;
|
||||
assign TRIG0[21:3] = cnt ;
|
||||
assign TRIG0[22] = dq ;
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
+72
@@ -0,0 +1,72 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 15:35:03 01/27/2022
|
||||
// Design Name:
|
||||
// Module Name: mod2_rom
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module frac2_rom(
|
||||
input sysclk,
|
||||
input [11 : 0] addra,
|
||||
output reg[13:0] douta
|
||||
);
|
||||
|
||||
|
||||
reg[11:0] addr=0;
|
||||
|
||||
always@(posedge sysclk)begin
|
||||
addr<=addra%25;
|
||||
end
|
||||
|
||||
always@(posedge sysclk)begin
|
||||
case(addr)
|
||||
0 : douta <= 0;
|
||||
1 : douta <= 2;
|
||||
2 : douta <= 4;
|
||||
3 : douta <= 6;
|
||||
4 : douta <= 8;
|
||||
5 : douta <= 2;
|
||||
6 : douta <= 12;
|
||||
7 : douta <= 14;
|
||||
8 : douta <= 16;
|
||||
9 : douta <= 18;
|
||||
10 : douta <= 4;
|
||||
11 : douta <= 22;
|
||||
12 : douta <= 24;
|
||||
13 : douta <= 1;
|
||||
14 : douta <= 3;
|
||||
15 : douta <= 1;
|
||||
16 : douta <= 7;
|
||||
17 : douta <= 9;
|
||||
18 : douta <= 11;
|
||||
19 : douta <= 13;
|
||||
20 : douta <= 3;
|
||||
21 : douta <= 17;
|
||||
22 : douta <= 19;
|
||||
23 : douta <= 21;
|
||||
24 : douta <= 23;
|
||||
default:douta <= douta ;
|
||||
endcase
|
||||
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
+210
@@ -0,0 +1,210 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 10:03:33 09/24/2021
|
||||
// Design Name:
|
||||
// Module Name: fre_caliatt
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module fre_caliatt(
|
||||
input i_clk ,
|
||||
input i_rstn ,
|
||||
output ENABLE ,
|
||||
output SC ,
|
||||
output SD ,
|
||||
output END_SYN ,
|
||||
input SDOUT ,
|
||||
input CAL_F ,
|
||||
input signed[7:0] i_temp ,
|
||||
input[15:0] i_fre_mode ,
|
||||
input[15:0] i_cal_fre_code ,
|
||||
input [3:0] cal1_mgc ,
|
||||
input [3:0] cal2_mgc ,
|
||||
input [3:0] cal3_mgc ,
|
||||
input [3:0] cal4_mgc ,
|
||||
input [3:0] i_ceshi_module ,
|
||||
input [40:0] SYNC_OUT ,
|
||||
input SW ,
|
||||
output [3:0] R_CAL1 ,
|
||||
output [3:0] R_CAL2 ,
|
||||
output [3:0] R_CAL3 ,
|
||||
output [3:0] R_CAL4 ,
|
||||
input [4:0] tx_mgc ,
|
||||
input [4:0] tx_cal_mgc ,
|
||||
output [4:0] T_CAL
|
||||
);
|
||||
|
||||
|
||||
wire[15:0] fre_mode ;
|
||||
wire[31:0] hop_fre_mode ;
|
||||
assign fre_mode = i_cal_fre_code/40 ;//20.375Ghz~23.875Ghz
|
||||
assign hop_fre_mode = i_cal_fre_code+20375 ;//20.375Ghz~23.875Ghz
|
||||
|
||||
|
||||
wire [3:0] R_CAL4_r ;
|
||||
wire [3:0] R_CAL3_r ;
|
||||
wire [3:0] R_CAL2_r ;
|
||||
wire [3:0] R_CAL1_r ;
|
||||
wire [4:0] T_CAL_r ;
|
||||
wire [31:0] data_in ;
|
||||
reg [31:0] data_in_r ;
|
||||
reg R_CAL_F ;
|
||||
wire[15:0] cal_mgc_r ;
|
||||
reg [15:0] cal_mgc_rr ;
|
||||
reg tx_en ;
|
||||
reg vio_en ;
|
||||
|
||||
|
||||
|
||||
|
||||
always@(posedge i_clk)
|
||||
begin
|
||||
cal_mgc_rr <= cal_mgc_r;
|
||||
end
|
||||
//------------------vio_debug------------------------//
|
||||
/* always@(posedge i_clk)
|
||||
begin
|
||||
vio_R_CAL_4 <= SYNC_OUT[4:0];
|
||||
vio_R_CAL_3 <= SYNC_OUT[9:5];
|
||||
vio_R_CAL_2 <= SYNC_OUT[14:10];
|
||||
vio_R_CAL_1 <= SYNC_OUT[19:15];
|
||||
vio_T_CAL <= SYNC_OUT[24:20];
|
||||
vio_en <= SYNC_OUT[25];
|
||||
end */
|
||||
|
||||
//------------------vio_debug------------------------//
|
||||
assign R_CAL1 = R_CAL1_r + cal1_mgc ;//通道1
|
||||
assign R_CAL2 = R_CAL2_r + cal2_mgc ;//通道2
|
||||
assign R_CAL3 = R_CAL3_r + cal3_mgc ;//通道3
|
||||
assign R_CAL4 = R_CAL4_r + cal4_mgc ;//通道4
|
||||
assign T_CAL = ( i_ceshi_module==4'ha || i_ceshi_module==4'hb) ? (tx_mgc[4:0] + tx_cal_mgc) : (T_CAL_r + tx_cal_mgc) ;//发射通道，低衰减
|
||||
|
||||
assign cal_mgc_r = {cal1_mgc,cal2_mgc,cal3_mgc,cal4_mgc};
|
||||
assign data_in = { 4'h0,3'b0,
|
||||
T_CAL , //发射通道
|
||||
R_CAL1[0], //接收通道1_1dB
|
||||
R_CAL1[1], //接收通道1_2dB
|
||||
R_CAL1[2], //接收通道1_4dB
|
||||
R_CAL1[3], //接收通道1_8dB
|
||||
R_CAL2[0], //接收通道2_1dB
|
||||
R_CAL2[1], //接收通道2_2dB
|
||||
R_CAL2[2], //接收通道2_4dB
|
||||
R_CAL2[3], //接收通道2_8dB
|
||||
R_CAL3[0], //接收通道3_1dB
|
||||
R_CAL3[1], //接收通道3_2dB
|
||||
R_CAL3[2], //接收通道3_4dB
|
||||
R_CAL3[3], //接收通道3_8dB
|
||||
R_CAL4 , //
|
||||
4'b0 };
|
||||
reg [31:0] cnt5us=0;
|
||||
|
||||
always@(posedge i_clk)begin
|
||||
if(cnt5us==2000)
|
||||
cnt5us<=2000;
|
||||
else
|
||||
cnt5us<=cnt5us+1'b1;
|
||||
end
|
||||
|
||||
always@(posedge i_clk or negedge i_rstn)begin
|
||||
if(!i_rstn)
|
||||
R_CAL_F <= 1'b0;
|
||||
else
|
||||
R_CAL_F <= CAL_F;
|
||||
end
|
||||
|
||||
always@(posedge i_clk or negedge i_rstn)begin
|
||||
if(!i_rstn)
|
||||
tx_en<=1'b0;
|
||||
else if(cnt5us==1999)
|
||||
tx_en<=1'b1;
|
||||
else if({R_CAL_F,CAL_F}==2'b01 || cal_mgc_rr!=cal_mgc_r)
|
||||
tx_en<=1'b1;
|
||||
else
|
||||
tx_en<=1'b0;
|
||||
end
|
||||
|
||||
|
||||
|
||||
R_CAL_1 R_CAL_1 (
|
||||
.i_clk(i_clk),
|
||||
.i_rstn(i_rstn),
|
||||
.i_temp(i_temp),
|
||||
.fre_mode(fre_mode),
|
||||
.R_CAL(R_CAL1_r)
|
||||
);
|
||||
|
||||
R_CAL_2 R_CAL_2 (
|
||||
.i_clk(i_clk),
|
||||
.i_rstn(i_rstn),
|
||||
.i_temp(i_temp),
|
||||
.fre_mode(fre_mode),
|
||||
.R_CAL(R_CAL2_r)
|
||||
);
|
||||
|
||||
R_CAL_3 R_CAL_3 (
|
||||
.i_clk(i_clk),
|
||||
.i_rstn(i_rstn),
|
||||
.i_temp(i_temp),
|
||||
.fre_mode(fre_mode),
|
||||
.R_CAL(R_CAL3_r)
|
||||
);
|
||||
|
||||
R_CAL_4 R_CAL_4 (
|
||||
.i_clk(i_clk),
|
||||
.i_rstn(i_rstn),
|
||||
.i_temp(i_temp),
|
||||
.fre_mode(fre_mode),
|
||||
.R_CAL(R_CAL4_r)
|
||||
);
|
||||
|
||||
|
||||
T_CAL T_CAL__ (
|
||||
.i_clk(i_clk),
|
||||
.i_rstn(i_rstn),
|
||||
.SW(SW),
|
||||
.i_temp(i_temp),
|
||||
.hop_fre_mode(hop_fre_mode),
|
||||
.T_CAL_(T_CAL_r)
|
||||
);
|
||||
|
||||
|
||||
spi_tx SPI_TX (
|
||||
.clk (i_clk ) ,
|
||||
.rstn (i_rstn ) ,
|
||||
.tx_en (tx_en ) ,
|
||||
.data_in (data_in ) ,
|
||||
.spi_cs (ENABLE ) ,
|
||||
.spi_sclk (SC ) ,
|
||||
.spi_sdo (SD ) ,
|
||||
.DARY (END_SYN )
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
+434
@@ -0,0 +1,434 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 19:54:29 09/06/2021
|
||||
// Design Name:
|
||||
// Module Name: mgc_ctrl
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module mgc_ctrl(
|
||||
input i_sys_clk ,
|
||||
input i_rst_n ,
|
||||
input i_TR_SW_F ,
|
||||
input i_TP_EN_F ,
|
||||
input i_CAL_F ,
|
||||
input i_T_MGC_EN_F ,
|
||||
input i_R_MGC_EN_F ,
|
||||
|
||||
input [15:0] i_fre_code ,
|
||||
input [7:0] i_tx_mgc ,
|
||||
input [7:0] i_rx1_mgc ,
|
||||
input [7:0] i_rx2_mgc ,
|
||||
input [7:0] i_rx3_mgc ,
|
||||
input [7:0] i_rx4_mgc ,
|
||||
input [3:0] i_ceshi_module,
|
||||
output [15:0] o_current_fre_code,
|
||||
output [15:0] o_cal_fre_code,
|
||||
output [15:0] o_hop_fre_code,
|
||||
output o_adf4371_hop1,
|
||||
output o_adf4371_hop2,
|
||||
|
||||
output o_SW,
|
||||
output o_SW2,
|
||||
output o_SW3,
|
||||
output o_SW_C1,
|
||||
|
||||
//发射通道MGC控制，高衰。31dB，步进1dB。初始态直通（全置1）
|
||||
output o_T_MGC_1dB,
|
||||
output o_T_MGC_2dB,
|
||||
output o_T_MGC_4dB,
|
||||
output o_T_MGC_8dB,
|
||||
output o_T_MGC_16dB,
|
||||
//接收通道1MGC控制，高衰。31dB，步进1dB。初始态直通（全置1）
|
||||
output reg[7:0] o_R_MGC_1,
|
||||
|
||||
//接收通道2MGC控制，高衰。31dB，步进1dB。初始态直通（全置1）
|
||||
output reg[7:0] o_R_MGC_2,
|
||||
|
||||
//接收通道3MGC控制，高衰。31dB，步进1dB。初始态直通（全置1）
|
||||
output reg[7:0] o_R_MGC_3,
|
||||
//接收通道4MGC控制，高衰。31dB，步进1dB。初始态直通（全置1）
|
||||
output reg[7:0] o_R_MGC_4
|
||||
|
||||
);
|
||||
|
||||
|
||||
reg TR_SW_F;
|
||||
reg [2:0] TP_EN_r;
|
||||
reg [2:0] T_MGC_EN_r;
|
||||
reg [2:0] R_MGC_EN_r;
|
||||
reg [2:0] R_CAL_F;
|
||||
reg [15:0] hop_fre_code;
|
||||
reg [15:0] current_fre_code;
|
||||
wire [15:0] cal_fre_code;
|
||||
reg [47:0] fre_code_a_b;
|
||||
reg hop_en;
|
||||
reg hop_en_r;
|
||||
reg hop_en_rr;
|
||||
reg cfg_en;
|
||||
reg cfg_en_r;
|
||||
reg cfg_en_rr;
|
||||
reg hmc704_1_hop;
|
||||
reg hmc704_2_hop;
|
||||
reg [1:0] cnt_cfg;
|
||||
reg [1:0] cnt_hop;
|
||||
|
||||
|
||||
reg sw1;
|
||||
reg sw2;
|
||||
reg sw3;
|
||||
reg SW_C1;
|
||||
|
||||
reg T_MGC_1dB_r ;
|
||||
reg T_MGC_2dB_r ;
|
||||
reg T_MGC_4dB_r ;
|
||||
reg T_MGC_8dB_r ;
|
||||
reg T_MGC_16dB_r;
|
||||
|
||||
assign o_SW = sw1;
|
||||
assign o_SW2 = sw2;
|
||||
assign o_SW3 = sw3;
|
||||
assign o_SW_C1 = SW_C1;
|
||||
|
||||
assign o_current_fre_code= current_fre_code;
|
||||
assign o_cal_fre_code = cal_fre_code;
|
||||
assign o_hop_fre_code = hop_fre_code;
|
||||
assign o_adf4371_hop1 = hmc704_1_hop;
|
||||
assign o_adf4371_hop2 = hmc704_2_hop;
|
||||
|
||||
assign o_T_MGC_1dB = T_MGC_1dB_r ;
|
||||
assign o_T_MGC_2dB = T_MGC_2dB_r ;
|
||||
assign o_T_MGC_4dB = T_MGC_4dB_r ;
|
||||
assign o_T_MGC_8dB = T_MGC_8dB_r ;
|
||||
assign o_T_MGC_16dB = T_MGC_16dB_r ;
|
||||
|
||||
|
||||
always@(posedge i_sys_clk or negedge i_rst_n)begin
|
||||
if(!i_rst_n)begin
|
||||
TR_SW_F <= 1'b0;
|
||||
TP_EN_r <= 3'b0;
|
||||
T_MGC_EN_r <= 3'b0;
|
||||
R_MGC_EN_r <= 3'b0;
|
||||
R_CAL_F <= 3'b0;
|
||||
end
|
||||
else begin
|
||||
TR_SW_F <= i_TR_SW_F;
|
||||
TP_EN_r <= {TP_EN_r[1:0] ,i_TP_EN_F};
|
||||
T_MGC_EN_r <= {T_MGC_EN_r[1:0] ,i_T_MGC_EN_F};
|
||||
R_MGC_EN_r <= {R_MGC_EN_r[1:0] ,i_R_MGC_EN_F};
|
||||
R_CAL_F <= {R_CAL_F[1:0] ,i_CAL_F};
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge i_sys_clk or negedge i_rst_n)begin
|
||||
if(!i_rst_n)begin
|
||||
SW_C1 <= 1'b0;
|
||||
current_fre_code <= 16'h6d6 ;
|
||||
end
|
||||
else begin
|
||||
current_fre_code <= hop_en ? hop_fre_code : current_fre_code ;
|
||||
if(TR_SW_F==1'b1)begin
|
||||
if(current_fre_code<=1500)//20.375Ghz~21.875Ghz
|
||||
SW_C1 <= 1'b1;
|
||||
else //21.875Ghz~23.875Ghz
|
||||
SW_C1 <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
SW_C1 <= SW_C1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
assign cal_fre_code = R_CAL_F==3'b001 ? hop_fre_code : cal_fre_code ;
|
||||
|
||||
|
||||
|
||||
|
||||
always@(posedge i_sys_clk or negedge i_rst_n)begin
|
||||
if(!i_rst_n)begin
|
||||
fre_code_a_b <= 48'h0000000006d6;
|
||||
end
|
||||
else if(cfg_en)begin
|
||||
fre_code_a_b <= {fre_code_a_b[31:0],i_fre_code};
|
||||
end
|
||||
else begin
|
||||
fre_code_a_b <= fre_code_a_b;
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge i_sys_clk or negedge i_rst_n)begin
|
||||
if(!i_rst_n)begin
|
||||
hop_en <= 1'b0;
|
||||
end
|
||||
else if(TP_EN_r==3'b011)begin
|
||||
hop_en <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
hop_en <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge i_sys_clk or negedge i_rst_n)begin
|
||||
if(!i_rst_n)begin
|
||||
hop_fre_code <= 16'h6d6;
|
||||
end
|
||||
else begin
|
||||
hop_fre_code <= i_fre_code;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge i_sys_clk or negedge i_rst_n)begin
|
||||
if(!i_rst_n)begin
|
||||
cfg_en <= 1'b0;
|
||||
end
|
||||
else if(hop_fre_code != i_fre_code)begin
|
||||
cfg_en <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
cfg_en <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always @ (posedge i_sys_clk or negedge i_rst_n)begin
|
||||
if(!i_rst_n)begin
|
||||
hop_en_r <= 1'b0;
|
||||
hop_en_rr <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
hop_en_r <= hop_en;
|
||||
hop_en_rr <= hop_en_r;
|
||||
end
|
||||
end
|
||||
|
||||
always @ (posedge i_sys_clk or negedge i_rst_n)begin
|
||||
if(!i_rst_n)begin
|
||||
cfg_en_r <= 1'b0;
|
||||
cfg_en_rr <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
cfg_en_r <= cfg_en;
|
||||
cfg_en_rr <= cfg_en_r;
|
||||
end
|
||||
end
|
||||
|
||||
reg [15:0] pre_hop_fre_code;
|
||||
always @ (posedge i_sys_clk or negedge i_rst_n)begin
|
||||
if(!i_rst_n)begin
|
||||
cnt_hop <= 2'b00;
|
||||
end
|
||||
else if(cnt_hop == 2'b10)begin
|
||||
cnt_hop <= 2'b00;
|
||||
end
|
||||
else if(~hop_en_r & hop_en && (pre_hop_fre_code!=hop_fre_code ))begin
|
||||
cnt_hop <= cnt_hop + 1'b1;
|
||||
end
|
||||
else begin
|
||||
cnt_hop <= cnt_hop;
|
||||
end
|
||||
end
|
||||
|
||||
always @ (posedge i_sys_clk or negedge i_rst_n)begin
|
||||
if(!i_rst_n)begin
|
||||
cnt_cfg <= 2'b00;
|
||||
end
|
||||
else if(cnt_cfg == 2'b10)begin
|
||||
cnt_cfg <= 2'b00;
|
||||
end
|
||||
else if(~cfg_en_r&cfg_en)begin
|
||||
cnt_cfg <= cnt_cfg + 1'b1;
|
||||
end
|
||||
else begin
|
||||
cnt_cfg <= cnt_cfg;
|
||||
end
|
||||
end
|
||||
|
||||
always @ (posedge i_sys_clk or negedge i_rst_n)begin
|
||||
if(!i_rst_n)
|
||||
pre_hop_fre_code<=16'h6d6;
|
||||
else if(hop_en_rr)
|
||||
pre_hop_fre_code<=hop_fre_code;
|
||||
else
|
||||
pre_hop_fre_code<=pre_hop_fre_code;
|
||||
end
|
||||
|
||||
always @ (posedge i_sys_clk or negedge i_rst_n)begin
|
||||
if(!i_rst_n)begin
|
||||
sw1 <= 1'b1;
|
||||
sw2 <= 1'b1;
|
||||
sw3 <= 1'b0;
|
||||
end
|
||||
else if(i_ceshi_module==4'ha)//自动校准开关到a
|
||||
begin
|
||||
sw1 <= 1'b0;
|
||||
sw2 <= 1'b0;
|
||||
sw3 <= 1'b1;
|
||||
end
|
||||
else if(i_ceshi_module==4'hb)//自动校准开关到b
|
||||
begin
|
||||
sw1 <= 1'b1;
|
||||
sw2 <= 1'b1;
|
||||
sw3 <= 1'b0;
|
||||
end
|
||||
else if(hop_en_rr && pre_hop_fre_code != hop_fre_code)begin
|
||||
if(cnt_hop == 2'b01)begin
|
||||
sw1 <= 1'b0;
|
||||
sw2 <= 1'b0;
|
||||
sw3 <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
sw1 <= 1'b1;
|
||||
sw2 <= 1'b1;
|
||||
sw3 <= 1'b0;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
sw1 <= sw1;
|
||||
sw2 <= sw2;
|
||||
sw3 <= sw3;
|
||||
end
|
||||
end
|
||||
|
||||
always @ (posedge i_sys_clk or negedge i_rst_n)begin
|
||||
if(!i_rst_n)begin
|
||||
hmc704_1_hop <= 1'b0;
|
||||
hmc704_2_hop <= 1'b0;
|
||||
end
|
||||
else if(i_ceshi_module==4'ha&&cfg_en_rr)begin
|
||||
hmc704_1_hop <= 1'b1;
|
||||
hmc704_2_hop <= 1'b0;
|
||||
end
|
||||
else if(i_ceshi_module==4'hb&&cfg_en_rr)begin
|
||||
hmc704_1_hop <= 1'b0;
|
||||
hmc704_2_hop <= 1'b1;
|
||||
end
|
||||
else if(cfg_en_rr)begin
|
||||
if(fre_code_a_b[47:32]==fre_code_a_b[15:0])begin
|
||||
hmc704_1_hop <= 1'b0;
|
||||
hmc704_2_hop <= 1'b0;
|
||||
end
|
||||
else if(cnt_cfg == 2'b01)begin
|
||||
hmc704_1_hop <= 1'b1;
|
||||
hmc704_2_hop <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
hmc704_1_hop <= 1'b0;
|
||||
hmc704_2_hop <= 1'b1;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
hmc704_1_hop <= 1'b0;
|
||||
hmc704_2_hop <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
/* always @ (posedge i_sys_clk or negedge i_rst_n)begin
|
||||
if(!i_rst_n)begin
|
||||
sw1 <= 1'b1;
|
||||
sw2 <= 1'b1;
|
||||
sw3 <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @ (posedge i_sys_clk or negedge i_rst_n)begin
|
||||
if(!i_rst_n)begin
|
||||
hmc704_1_hop <= 1'b0;
|
||||
hmc704_2_hop <= 1'b0;
|
||||
end
|
||||
else if(cfg_en_rr)begin
|
||||
hmc704_1_hop <= 1'b0;
|
||||
hmc704_2_hop <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
hmc704_1_hop <= 1'b0;
|
||||
hmc704_2_hop <= 1'b0;
|
||||
end
|
||||
end */
|
||||
|
||||
|
||||
|
||||
|
||||
always@(posedge i_sys_clk or negedge i_rst_n)begin
|
||||
if(!i_rst_n)begin
|
||||
T_MGC_1dB_r <= 1'b0;
|
||||
T_MGC_2dB_r <= 1'b0;
|
||||
T_MGC_4dB_r <= 1'b0;
|
||||
T_MGC_8dB_r <= 1'b0;
|
||||
T_MGC_16dB_r <= 1'b0;
|
||||
end
|
||||
else if(i_ceshi_module==4'ha || i_ceshi_module==4'hb )begin
|
||||
T_MGC_1dB_r <= 1'b0;
|
||||
T_MGC_2dB_r <= 1'b0;
|
||||
T_MGC_4dB_r <= 1'b0;
|
||||
T_MGC_8dB_r <= 1'b0;
|
||||
T_MGC_16dB_r <= 1'b0;
|
||||
end
|
||||
else if(T_MGC_EN_r==3'b011)begin
|
||||
T_MGC_1dB_r <= i_tx_mgc[0];
|
||||
T_MGC_2dB_r <= i_tx_mgc[1];
|
||||
T_MGC_4dB_r <= i_tx_mgc[2];
|
||||
T_MGC_8dB_r <= i_tx_mgc[3];
|
||||
T_MGC_16dB_r <= i_tx_mgc[4];
|
||||
end
|
||||
else begin
|
||||
T_MGC_1dB_r <= T_MGC_1dB_r ;
|
||||
T_MGC_2dB_r <= T_MGC_2dB_r ;
|
||||
T_MGC_4dB_r <= T_MGC_4dB_r ;
|
||||
T_MGC_8dB_r <= T_MGC_8dB_r ;
|
||||
T_MGC_16dB_r <= T_MGC_16dB_r ;
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge i_sys_clk or negedge i_rst_n)begin
|
||||
if(!i_rst_n)begin
|
||||
o_R_MGC_1 <= 1'b0;
|
||||
end
|
||||
else if(R_MGC_EN_r==3'b011)begin
|
||||
o_R_MGC_1 <= i_rx1_mgc;
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge i_sys_clk or negedge i_rst_n)begin
|
||||
if(!i_rst_n)begin
|
||||
o_R_MGC_2 <= 1'b0;
|
||||
end
|
||||
else if(R_MGC_EN_r==3'b011)begin
|
||||
o_R_MGC_2 <= i_rx2_mgc;
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge i_sys_clk or negedge i_rst_n)begin
|
||||
if(!i_rst_n)begin
|
||||
o_R_MGC_3 <= 1'b0;
|
||||
end
|
||||
else if(R_MGC_EN_r==3'b011)begin
|
||||
o_R_MGC_3 <= i_rx3_mgc;
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge i_sys_clk or negedge i_rst_n)begin
|
||||
if(!i_rst_n)begin
|
||||
o_R_MGC_4 <= 1'b0;
|
||||
end
|
||||
else if(R_MGC_EN_r==3'b011)begin
|
||||
o_R_MGC_4 <= i_rx4_mgc;
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
+71
@@ -0,0 +1,71 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 15:35:03 01/27/2022
|
||||
// Design Name:
|
||||
// Module Name: mod2_rom
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module mod2_rom(
|
||||
input sysclk,
|
||||
input [11 : 0] addra,
|
||||
|
||||
output reg[13:0] douta
|
||||
);
|
||||
|
||||
reg[11:0] addr=0;
|
||||
always@(posedge sysclk)begin
|
||||
addr<=addra%25;
|
||||
end
|
||||
|
||||
always@(posedge sysclk)begin
|
||||
case(addr)
|
||||
0 : douta <= 1 ;
|
||||
1 : douta <= 25 ;
|
||||
2 : douta <= 25 ;
|
||||
3 : douta <= 25 ;
|
||||
4 : douta <= 25 ;
|
||||
5 : douta <= 5 ;
|
||||
6 : douta <= 25 ;
|
||||
7 : douta <= 25 ;
|
||||
8 : douta <= 25 ;
|
||||
9 : douta <= 25 ;
|
||||
10 : douta <= 5 ;
|
||||
11 : douta <= 25 ;
|
||||
12 : douta <= 25 ;
|
||||
13 : douta <= 25 ;
|
||||
14 : douta <= 25 ;
|
||||
15 : douta <= 5 ;
|
||||
16 : douta <= 25 ;
|
||||
17 : douta <= 25 ;
|
||||
18 : douta <= 25 ;
|
||||
19 : douta <= 25 ;
|
||||
20 : douta <= 5 ;
|
||||
21 : douta <= 25 ;
|
||||
22 : douta <= 25 ;
|
||||
23 : douta <= 25 ;
|
||||
24 : douta <= 25 ;
|
||||
default:douta <= douta ;
|
||||
endcase
|
||||
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
+150
@@ -0,0 +1,150 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 20:42:39 09/29/2021
|
||||
// Design Name:
|
||||
// Module Name: spi_master
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module spi_master #(parameter BIT_NUM = 95 )(
|
||||
input i_clk ,
|
||||
input debug_clk ,
|
||||
input i_sys_rst_n ,
|
||||
input i_spi_sck ,
|
||||
input i_spi_cs ,
|
||||
output o_spi_sdo ,
|
||||
input i_spi_sdi ,
|
||||
input i_LD_LO3 ,
|
||||
input i_LD1 ,
|
||||
input i_LD2 ,
|
||||
input[3:0] i_cal1_mgc ,
|
||||
input[3:0] i_cal2_mgc ,
|
||||
input[3:0] i_cal3_mgc ,
|
||||
input[3:0] i_cal4_mgc ,
|
||||
input[7:0] i_temp ,
|
||||
input[31:0] i_frame_count
|
||||
|
||||
);
|
||||
|
||||
wire [BIT_NUM:0] data ;
|
||||
reg [BIT_NUM:0] data_r ;
|
||||
reg [BIT_NUM:0] data_reg ;
|
||||
assign data={ 8'hAA ,
|
||||
i_temp ,
|
||||
7'b0,i_LD_LO3 ,
|
||||
7'b0,i_LD1 ,
|
||||
7'b0,i_LD2 ,
|
||||
i_cal1_mgc,i_cal2_mgc ,
|
||||
i_cal3_mgc,i_cal4_mgc ,
|
||||
i_frame_count ,
|
||||
8'hCC } ;
|
||||
|
||||
wire spi_sck ;
|
||||
wire spi_cs ;
|
||||
reg spi_sdo ;
|
||||
reg [2:0] reg_cs ;
|
||||
reg [31:0] cnt ;
|
||||
|
||||
assign spi_sck = i_spi_sck;
|
||||
assign spi_cs = i_spi_cs;
|
||||
assign o_spi_sdo = spi_sdo;
|
||||
|
||||
always@(negedge spi_sck,negedge i_sys_rst_n)begin
|
||||
if(!i_sys_rst_n)
|
||||
reg_cs<=3'b111;
|
||||
else
|
||||
reg_cs<={reg_cs[1:0],i_spi_cs};
|
||||
end
|
||||
|
||||
always@(negedge spi_sck,negedge i_sys_rst_n)begin
|
||||
if(!i_sys_rst_n)
|
||||
data_r<={8'hAA,80'b0,8'hCC};
|
||||
else if(reg_cs[2:1]==2'b10)
|
||||
data_r<={8'hAA,data[87:8],8'hCC};
|
||||
end
|
||||
|
||||
always@(negedge spi_sck,negedge i_sys_rst_n)begin
|
||||
if(!i_sys_rst_n)
|
||||
spi_sdo <= 1'b0 ;
|
||||
else if(!spi_cs)
|
||||
spi_sdo <= data_r[cnt];
|
||||
else
|
||||
spi_sdo <= 1'b0 ;
|
||||
end
|
||||
|
||||
always@(posedge spi_sck,negedge i_sys_rst_n)begin
|
||||
if(!i_sys_rst_n)
|
||||
cnt<=BIT_NUM;
|
||||
else if(spi_cs==1 | cnt==0)
|
||||
cnt<=BIT_NUM;
|
||||
else
|
||||
cnt<=cnt-1;
|
||||
end
|
||||
|
||||
//------------debug------------
|
||||
always@(posedge spi_sck,negedge i_sys_rst_n)begin
|
||||
if(!i_sys_rst_n)
|
||||
data_reg <= 0 ;
|
||||
else if(!spi_cs)
|
||||
data_reg <= {data_reg,spi_sdo} ;
|
||||
else
|
||||
data_reg <= data_reg ;
|
||||
end
|
||||
//------------debug------------
|
||||
|
||||
/*
|
||||
wire [40:0] SYNC_OUT ;
|
||||
wire [35:0] CONTROL0 ;
|
||||
wire [35:0] CONTROL1 ;
|
||||
wire [150:0] TRIG0 ;
|
||||
|
||||
vio u_vio (
|
||||
.CONTROL (CONTROL0), // INOUT BUS [35:0]
|
||||
.CLK (i_clk), // IN
|
||||
.SYNC_OUT (SYNC_OUT) // OUT BUS [33:0]
|
||||
);
|
||||
|
||||
|
||||
icon u_icon (
|
||||
.CONTROL0 (CONTROL0), // INOUT BUS [35:0]
|
||||
.CONTROL1 (CONTROL1) // INOUT BUS [35:0]
|
||||
);
|
||||
|
||||
|
||||
ila u_ila (
|
||||
.CONTROL (CONTROL1), // INOUT BUS [35:0]
|
||||
.CLK (debug_clk), // IN
|
||||
.TRIG0 (TRIG0) // IN BUS [39:0]
|
||||
);
|
||||
|
||||
|
||||
assign TRIG0[0] = i_LD_LO3;
|
||||
assign TRIG0[1] = i_LD1 ;
|
||||
assign TRIG0[2] = i_LD2 ;
|
||||
assign TRIG0[98:3] = data_r ;
|
||||
assign TRIG0[101:99] = reg_cs ;
|
||||
assign TRIG0[132:102] = cnt ;
|
||||
assign TRIG0[133] = i_spi_sck ;
|
||||
assign TRIG0[134] = i_spi_cs ;
|
||||
assign TRIG0[135] = o_spi_sdo ;
|
||||
assign TRIG0[136] = i_spi_sdi ;
|
||||
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
+171
@@ -0,0 +1,171 @@
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2020/09/02 10:48:55
|
||||
// Design Name:
|
||||
// Module Name: d
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
// SPI时钟频率50MHz。每一帧数据12个字节，共96bit数据。
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module spi_slave#(
|
||||
parameter BIT_NUM = 96
|
||||
)
|
||||
(
|
||||
input i_sys_clk,
|
||||
input i_sys_rst_n,
|
||||
|
||||
input i_spi_sck, //从机在时钟下降沿采样数据
|
||||
input i_spi_cs, //低电平时从机接收数据指令
|
||||
input i_spi_sdi,
|
||||
output [31:0] o_frame_count, //帧计数
|
||||
output [15:0] o_fre_code , //天线频率
|
||||
output [7:0] o_tx_mgc, //发射MGC
|
||||
output [3:0] o_model, //模式字
|
||||
output [3:0] o_rf_en, //射频使能
|
||||
output [3:0] o_cal1_mgc, //接收校准1mgc
|
||||
output [3:0] o_cal2_mgc, //接收校准2mgc
|
||||
output [3:0] o_cal3_mgc, //接收校准3mgc
|
||||
output [3:0] o_cal4_mgc, //接收校准4mgc
|
||||
output [7:0] o_tx_cal_mgc, //发射校准mgc
|
||||
output [7:0] o_rx1_mgc, //接收1mgc
|
||||
output [7:0] o_rx2_mgc, //接收2mgc
|
||||
output [7:0] o_rx3_mgc, //接收3mgc
|
||||
output [7:0] o_rx4_mgc , //接收4mgc
|
||||
|
||||
output [3:0] o_ceshi_model
|
||||
);
|
||||
|
||||
reg [BIT_NUM -1:0] receive_data;
|
||||
reg [3:0] rf_en ;
|
||||
reg [3:0] model;
|
||||
reg [31:0] frame_count;
|
||||
reg [11:0] fre_code;
|
||||
reg [7:0] tx_mgc;
|
||||
reg [7:0] rx1_mgc;
|
||||
reg [7:0] rx2_mgc;
|
||||
reg [7:0] rx3_mgc;
|
||||
reg [7:0] rx4_mgc;
|
||||
reg [3:0] cal1_mgc;
|
||||
reg [3:0] cal2_mgc;
|
||||
reg [3:0] cal3_mgc;
|
||||
reg [3:0] cal4_mgc;
|
||||
reg [7:0] tx_cal_mgc;
|
||||
reg [3:0] ceshi_module;
|
||||
|
||||
|
||||
assign o_frame_count= frame_count;
|
||||
assign o_fre_code = {4'b0,fre_code};
|
||||
assign o_rf_en = rf_en;
|
||||
assign o_model = model;
|
||||
assign o_tx_mgc = tx_mgc;
|
||||
assign o_cal1_mgc = cal1_mgc;
|
||||
assign o_cal2_mgc = cal2_mgc;
|
||||
assign o_cal3_mgc = cal3_mgc;
|
||||
assign o_cal4_mgc = cal4_mgc;
|
||||
assign o_tx_cal_mgc = tx_cal_mgc;
|
||||
assign o_rx1_mgc = rx1_mgc;
|
||||
assign o_rx2_mgc = rx2_mgc;
|
||||
assign o_rx3_mgc = rx3_mgc;
|
||||
assign o_rx4_mgc = rx4_mgc;
|
||||
assign o_ceshi_model = ceshi_module;
|
||||
|
||||
always @ ( negedge i_spi_sck or negedge i_sys_rst_n)begin
|
||||
if( !i_sys_rst_n )
|
||||
receive_data <= 'b0;
|
||||
else if(i_spi_cs == 1'b0)
|
||||
receive_data <= {receive_data,i_spi_sdi};
|
||||
else
|
||||
receive_data <= receive_data;
|
||||
end
|
||||
|
||||
|
||||
reg [2:0] cs_reg;
|
||||
|
||||
always @ ( posedge i_sys_clk or negedge i_sys_rst_n)begin
|
||||
if( !i_sys_rst_n )
|
||||
cs_reg <= 3'b111;
|
||||
else
|
||||
cs_reg <= {cs_reg[1:0],i_spi_cs};
|
||||
end
|
||||
|
||||
|
||||
|
||||
always @ ( posedge i_sys_clk or negedge i_sys_rst_n)begin
|
||||
if(!i_sys_rst_n)begin
|
||||
tx_cal_mgc<=8'h0;
|
||||
end
|
||||
else if(cs_reg[2:1]==2'b01 && (receive_data[95:88] == 8'hbb) && (receive_data[7:0] == 8'hdd))begin
|
||||
tx_cal_mgc<=receive_data[15:8];
|
||||
end
|
||||
else begin
|
||||
tx_cal_mgc<=tx_cal_mgc;
|
||||
end
|
||||
end
|
||||
|
||||
always @ ( posedge i_sys_clk or negedge i_sys_rst_n)begin
|
||||
if(!i_sys_rst_n)begin
|
||||
fre_code <= 12'h6d6;
|
||||
tx_mgc <= 8'h00;
|
||||
rf_en <= 4'b1;
|
||||
model <= 4'b0;
|
||||
frame_count <= 32'd1;
|
||||
rx1_mgc <= 4'h0;
|
||||
rx2_mgc <= 4'h0;
|
||||
rx3_mgc <= 4'h0;
|
||||
rx4_mgc <= 4'h0;
|
||||
cal1_mgc <= 4'h0;
|
||||
cal2_mgc <= 4'h0;
|
||||
cal3_mgc <= 4'h0;
|
||||
cal4_mgc <= 4'h0;
|
||||
ceshi_module <= 4'h0;
|
||||
end
|
||||
else if(cs_reg[2:1]==2'b01 && (receive_data[95:88] == 8'haa) && (receive_data[7:0] == 8'hcc))begin
|
||||
frame_count <= frame_count+1'b1;
|
||||
rf_en <= receive_data[87:84];
|
||||
model <= receive_data[83:80];
|
||||
ceshi_module<= receive_data[79:76];
|
||||
fre_code <= receive_data[75:64];
|
||||
tx_mgc <= receive_data[63:56];
|
||||
cal1_mgc <= receive_data[55:52];
|
||||
cal2_mgc <= receive_data[51:48];
|
||||
cal3_mgc <= receive_data[47:44];
|
||||
cal4_mgc <= receive_data[43:40];
|
||||
rx1_mgc <= receive_data[39:32];
|
||||
rx2_mgc <= receive_data[31:24];
|
||||
rx3_mgc <= receive_data[23:16];
|
||||
rx4_mgc <= receive_data[15:8];
|
||||
end
|
||||
else begin
|
||||
frame_count <= frame_count ;
|
||||
rf_en <= rf_en ;
|
||||
model <= model ;
|
||||
fre_code <= fre_code ;
|
||||
tx_mgc <= tx_mgc ;
|
||||
cal1_mgc <= cal1_mgc ;
|
||||
cal2_mgc <= cal2_mgc ;
|
||||
cal3_mgc <= cal3_mgc ;
|
||||
cal4_mgc <= cal4_mgc ;
|
||||
rx1_mgc <= rx1_mgc ;
|
||||
rx2_mgc <= rx2_mgc ;
|
||||
rx3_mgc <= rx3_mgc ;
|
||||
rx4_mgc <= rx4_mgc ;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
+118
@@ -0,0 +1,118 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 15:23:58 10/12/2020
|
||||
// Design Name: spi发送模块
|
||||
// Module Name: spi
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module spi_tx #(parameter WHITH=32)(
|
||||
input clk,//系统时钟
|
||||
input rstn,//异步复位
|
||||
input tx_en,//发送使能
|
||||
input [WHITH-1:0] data_in,//待发送数据
|
||||
output reg spi_cs, //片选
|
||||
output reg spi_sclk, //同步时钟，等于clk/2
|
||||
output reg spi_sdo, //发送数据的线
|
||||
output reg DARY
|
||||
);
|
||||
|
||||
//localparam [1:0] polaeity = 2'b10;//negedge 数据下降沿保持
|
||||
localparam [1:0] polaeity = 2'b01;//posedge 数据上降沿保持
|
||||
reg [2:0] state ; //状态机
|
||||
reg [WHITH-1:0] reg_data;//移位寄存器
|
||||
reg [5:0] cnt;//计数器，必须大于数据位宽
|
||||
|
||||
wire CPOL ; //时钟空闲时电平
|
||||
wire CPHA ; //极性
|
||||
assign CPOL = polaeity[0] ;
|
||||
assign CPHA = polaeity[1] ;
|
||||
|
||||
always @(posedge clk,negedge rstn)begin
|
||||
if(!rstn)begin
|
||||
state <= 3'd0;
|
||||
spi_cs <= 1'b1;
|
||||
spi_sclk <= CPOL;
|
||||
reg_data <= 1'd0;
|
||||
cnt <= 5'b0;
|
||||
spi_sdo <= 1'b0;
|
||||
DARY <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
case(state)
|
||||
3'd0:begin//空闲态
|
||||
spi_sclk <= CPOL ;
|
||||
spi_cs <= 1'b1 ;
|
||||
spi_sdo <= 1'b0 ;
|
||||
DARY <= 1'b1 ;
|
||||
cnt <= 5'b0 ;
|
||||
reg_data <= data_in ;
|
||||
if(tx_en)//发送使能跳下一个状态
|
||||
state <= 3'd1 ;
|
||||
else
|
||||
state <= state ;
|
||||
end
|
||||
3'd1:begin
|
||||
spi_cs <= 1'b0 ;
|
||||
state <= 3'd2 ;
|
||||
reg_data <= data_in ;
|
||||
end
|
||||
3'd2:begin//数据移位态
|
||||
spi_cs <= 1'b0 ;
|
||||
reg_data <= reg_data<<1'b1 ;
|
||||
spi_sdo <= reg_data[WHITH-1] ;
|
||||
spi_sclk <= CPHA ;
|
||||
state <= (cnt >= WHITH-1) ? 3'd4:3'd3;
|
||||
end
|
||||
3'd3:begin//时钟翻转
|
||||
cnt <= cnt+1'b1 ;
|
||||
spi_sclk <= ~CPHA ;
|
||||
state <= 3'd2 ;
|
||||
end
|
||||
3'd4:begin//结束态
|
||||
state <= 3'd5;
|
||||
spi_sclk <= ~CPHA;
|
||||
end
|
||||
3'd5:begin//结束态
|
||||
state <= 3'd6;
|
||||
DARY <= 0;
|
||||
spi_sdo <= 1'b0 ;
|
||||
spi_cs <= 1'b1 ;
|
||||
end
|
||||
3'd6:begin//结束态
|
||||
state <= 3'd7;
|
||||
DARY <= 1;
|
||||
spi_cs <= 1'b1 ;
|
||||
end
|
||||
3'd7:begin//结束态
|
||||
state <= 3'd8;
|
||||
DARY <= 0;
|
||||
end
|
||||
3'd8:begin//结束态
|
||||
state <= 3'd0;
|
||||
DARY <= 1;
|
||||
end
|
||||
default :state<=3'd0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
+509
@@ -0,0 +1,509 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2022/07/13 14:20:24
|
||||
// Design Name:
|
||||
// Module Name: ant_rf_ctrl
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module ant_rf_ctrl
|
||||
(
|
||||
input clk_48m ,
|
||||
input clk_96m ,
|
||||
input clk_32m ,
|
||||
input clk_19p2m ,
|
||||
input sys_rst ,
|
||||
|
||||
output ant_clk ,
|
||||
output ant_en ,
|
||||
output ant_data ,
|
||||
output ant_tr ,
|
||||
output ant_dary ,
|
||||
input ant_dout ,
|
||||
|
||||
output rf_standby ,
|
||||
output rf_sw_pll ,
|
||||
output rf_t ,
|
||||
output rf_r ,
|
||||
output rf_sw_bpf ,
|
||||
output rf_sclk1 ,
|
||||
output rf_sdio1 ,
|
||||
output rf_cs1 ,
|
||||
input rf_ld1 ,
|
||||
output rf_sclk2 ,
|
||||
output rf_sdio2 ,
|
||||
output rf_cs2 ,
|
||||
input rf_ld2 ,
|
||||
output rf_sclk3 ,
|
||||
output rf_sdio3 ,
|
||||
output rf_cs3 ,
|
||||
input rf_ld3 ,
|
||||
output rf_tmgc_16 ,
|
||||
output rf_tmgc_8 ,
|
||||
output rf_tmgc_4 ,
|
||||
output rf_tmgc_2 ,
|
||||
output rf_tmgc_1 ,
|
||||
output rf_rmgc_16 ,
|
||||
output rf_rmgc_8 ,
|
||||
output rf_rmgc_4 ,
|
||||
output rf_rmgc_2 ,
|
||||
output rf_rmgc_1 ,
|
||||
output rf_enable ,
|
||||
output rf_sc ,
|
||||
output rf_sd ,
|
||||
output rf_endsyn ,
|
||||
input rf_sdout ,
|
||||
inout rf_dq_wd ,
|
||||
output rf_sw_rx
|
||||
);
|
||||
|
||||
|
||||
(*dont_touch = "true"*) wire vio_switch ; // 键控开关，沿有效
|
||||
(*dont_touch = "true"*) wire vio_trdirection ; // 收发方向
|
||||
(*dont_touch = "true"*) wire [15:0] vio_frequency ; // 收发频率
|
||||
(*dont_touch = "true"*) wire [ 7:0] vio_emitMGC ; // 发送MGC
|
||||
(*dont_touch = "true"*) wire [ 3:0] vio_ch01MGC ; // 1通道校准MGC
|
||||
(*dont_touch = "true"*) wire [ 3:0] vio_ch02MGC ; // 2通道校准MGC
|
||||
(*dont_touch = "true"*) wire [ 3:0] vio_ch03MGC ; // 3通道校准MGC
|
||||
(*dont_touch = "true"*) wire [ 3:0] vio_ch04MGC ; // 4通道校准MGC
|
||||
(*dont_touch = "true"*) wire [ 7:0] vio_recvMGC ; // 接收MGC
|
||||
(*dont_touch = "true"*) wire [ 7:0] vio_AntMod ; // 天线工作模式
|
||||
(*dont_touch = "true"*) wire [15:0] vio_AntOffAxis ; // 天线离轴角
|
||||
(*dont_touch = "true"*) wire [15:0] vio_AntYaw ; // 天线偏航角
|
||||
(*dont_touch = "true"*) wire [15:0] vio_PrecessTime ; // 处理时间，从EN拉低到DARY拉低
|
||||
|
||||
(*dont_touch = "true"*)wire vio_mode_ant ; // 0定频手动，1扫频模式
|
||||
(*dont_touch = "true"*)wire vio_hop_start ; // 0跳频终止，1重新跳频
|
||||
(*dont_touch = "true"*)wire vio_standby ; // 0待机模式，1工作模式
|
||||
(*dont_touch = "true"*)wire [15:0] vio_hoptime ; // 单跳时间计数器
|
||||
|
||||
reg Ant_switch_D1 = 0;
|
||||
reg data_valid = 0;
|
||||
reg switch_valid = 0;
|
||||
reg [95:0] RF_CtrlWord = 0;
|
||||
reg [127:0] Ant_CtrlWord = 0;
|
||||
reg [15:0] data_valid_countdown = 0;
|
||||
reg [15:0] rst_countdown = 100;
|
||||
reg [95:0] RF_CtrlWord_running = 0;
|
||||
reg [127:0] Ant_CtrlWord_running = 0;
|
||||
reg rst_n = 0;
|
||||
reg SPI_SYN_F = 1;
|
||||
reg SPI_MOSI_F = 1;
|
||||
reg TP_EN_F = 0;
|
||||
reg TR_MGC_F = 0;
|
||||
reg CAL_F = 0;
|
||||
reg PRF = 0;
|
||||
wire SPI_MISO_F;
|
||||
reg Ant_DATA = 0;
|
||||
reg Ant_EN = 0;
|
||||
reg Ant_DARY = 0;
|
||||
reg Ant_TR = 0;
|
||||
|
||||
|
||||
|
||||
//相控阵测试程序
|
||||
reg [15:0] cnt_freq_change = 16'd0;
|
||||
|
||||
reg Ant_switch ; // 键控开关，沿有效
|
||||
reg [15:0] Ant_frequency; // 收发频率
|
||||
reg [ 7:0] Ant_mode ; // 相控阵模式
|
||||
reg [ 7:0] RF_mode ; // 射频模式
|
||||
|
||||
always @ (posedge clk_48m) begin
|
||||
if(sys_rst) begin
|
||||
Ant_switch <= 1'b0;
|
||||
cnt_freq_change[15:0] <= 16'd0;
|
||||
Ant_frequency[15:0] <= 16'd0;
|
||||
RF_mode[7:0] <= 8'h10;
|
||||
Ant_mode[7:0] <= 8'h0f;
|
||||
end
|
||||
else begin
|
||||
if(vio_mode_ant) begin
|
||||
if(vio_hop_start) begin
|
||||
if(cnt_freq_change[15:0] == (vio_hoptime[15:0] - 16'd1)) begin
|
||||
Ant_switch <= ~Ant_switch;
|
||||
if(Ant_frequency[15:0] == 16'd3500) begin
|
||||
Ant_frequency[15:0] <= 16'd0;
|
||||
end
|
||||
else begin
|
||||
Ant_frequency[15:0] <= Ant_frequency[15:0] + 16'd1;
|
||||
end
|
||||
cnt_freq_change[15:0] <= 16'd0;
|
||||
end
|
||||
else begin
|
||||
Ant_switch <= Ant_switch;
|
||||
Ant_frequency[15:0] <= Ant_frequency[15:0];
|
||||
cnt_freq_change[15:0] <= cnt_freq_change[15:0] + 16'd1;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
Ant_switch <= Ant_switch;
|
||||
Ant_frequency[15:0] <= 16'd0;
|
||||
cnt_freq_change[15:0] <= 16'd0;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
Ant_switch <= vio_switch;
|
||||
Ant_frequency[15:0] <= vio_frequency[15:0];
|
||||
cnt_freq_change[15:0] <= 16'd0;
|
||||
end
|
||||
|
||||
if(vio_standby) begin
|
||||
RF_mode[7:0] <= 8'h10;
|
||||
Ant_mode[7:0] <= 8'h0f;
|
||||
end
|
||||
else begin
|
||||
RF_mode[7:0] <= 8'h00;
|
||||
Ant_mode[7:0] <= vio_AntMod[7:0];
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
always @(posedge clk_48m)
|
||||
begin
|
||||
Ant_switch_D1 <= Ant_switch;
|
||||
if(Ant_switch_D1 != Ant_switch)
|
||||
switch_valid <= 1'b1;
|
||||
else
|
||||
switch_valid <= 1'b0;
|
||||
|
||||
if(switch_valid)
|
||||
begin
|
||||
RF_CtrlWord[95:88] <= 8'hAA;
|
||||
RF_CtrlWord[87:80] <= RF_mode[7:0];
|
||||
RF_CtrlWord[79:64] <= Ant_frequency[15:0];
|
||||
RF_CtrlWord[63:56] <= vio_emitMGC[7:0];
|
||||
RF_CtrlWord[55:52] <= vio_ch01MGC[3:0];
|
||||
RF_CtrlWord[51:48] <= vio_ch02MGC[3:0];
|
||||
RF_CtrlWord[47:44] <= vio_ch03MGC[3:0];
|
||||
RF_CtrlWord[43:40] <= vio_ch04MGC[3:0];
|
||||
RF_CtrlWord[39:32] <= vio_recvMGC[7:0];
|
||||
RF_CtrlWord[31:8] <= 24'h00_0000;
|
||||
RF_CtrlWord[7:0] <= 8'hCC;
|
||||
|
||||
Ant_CtrlWord[127:120] <= 8'hAA;
|
||||
Ant_CtrlWord[119:112] <= 8'h00;
|
||||
Ant_CtrlWord[111:104] <= Ant_mode[7:0];
|
||||
Ant_CtrlWord[103: 88] <= vio_AntOffAxis[15:0];
|
||||
Ant_CtrlWord[ 87: 72] <= vio_AntYaw[15:0];
|
||||
Ant_CtrlWord[ 71: 56] <= Ant_frequency[15:0];
|
||||
Ant_CtrlWord[ 55: 8] <= 48'h00_00_00_00_00_00;
|
||||
Ant_CtrlWord[ 7: 0] <= 8'hCC;
|
||||
end
|
||||
else
|
||||
begin
|
||||
RF_CtrlWord[95:0] <= RF_CtrlWord[95:0];
|
||||
Ant_CtrlWord[127:0] <= Ant_CtrlWord[127:0];
|
||||
end
|
||||
|
||||
if(switch_valid)
|
||||
data_valid_countdown[15:0] <= vio_PrecessTime[15:0];
|
||||
else if(data_valid_countdown[15:0] != 16'd0)
|
||||
data_valid_countdown[15:0] <= data_valid_countdown[15:0] - 16'd1;
|
||||
|
||||
|
||||
// RF控制
|
||||
if(data_valid_countdown[15:0] == vio_PrecessTime[15:0])
|
||||
RF_CtrlWord_running[95:0] <= RF_CtrlWord[95:0];
|
||||
else
|
||||
RF_CtrlWord_running[95:0] <= {RF_CtrlWord_running[94:0],1'b0};
|
||||
|
||||
if(data_valid_countdown[15:0] >= vio_PrecessTime[15:0]-16'd96 && data_valid_countdown[15:0] < vio_PrecessTime[15:0])
|
||||
begin
|
||||
SPI_SYN_F <= 1'b0;
|
||||
SPI_MOSI_F <= RF_CtrlWord_running[95];
|
||||
end
|
||||
else
|
||||
begin
|
||||
SPI_SYN_F <= 1'b1;
|
||||
SPI_MOSI_F <= 1'b0;
|
||||
end
|
||||
|
||||
|
||||
if(data_valid_countdown[15:0] <= 16'd128 && data_valid_countdown[15:0] > 16'd80)
|
||||
CAL_F <= 1'b1;
|
||||
else
|
||||
CAL_F <= 1'b0;
|
||||
|
||||
if(data_valid_countdown[15:0] <= 16'd48 && data_valid_countdown[15:0] > 16'd0)
|
||||
begin
|
||||
TP_EN_F <= 1'b1;
|
||||
TR_MGC_F <= 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
TP_EN_F <= 1'b0;
|
||||
TR_MGC_F <= 1'b0;
|
||||
end
|
||||
|
||||
if(data_valid_countdown[15:0] == 16'd48)
|
||||
PRF <= vio_trdirection;
|
||||
else
|
||||
PRF <= PRF;
|
||||
|
||||
if(sys_rst)
|
||||
rst_countdown[15:0] <= 16'd100;
|
||||
else if(rst_countdown[15:0] != 0)
|
||||
begin
|
||||
rst_countdown[15:0] <= rst_countdown[15:0] - 16'd1;
|
||||
rst_n <= 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
rst_countdown[15:0] <= rst_countdown[15:0];
|
||||
rst_n <= 1'b1;
|
||||
end
|
||||
|
||||
// 天线控制
|
||||
if(data_valid_countdown[15:0] == vio_PrecessTime[15:0])
|
||||
Ant_CtrlWord_running[127:0] <= Ant_CtrlWord[127:0];
|
||||
else
|
||||
Ant_CtrlWord_running[127:0] <= {Ant_CtrlWord_running[126:0],1'b0};
|
||||
|
||||
if(data_valid_countdown[15:0] >= vio_PrecessTime[15:0]-16'd128 && data_valid_countdown[15:0] < vio_PrecessTime[15:0])
|
||||
begin
|
||||
Ant_EN <= 1'b0;
|
||||
Ant_DATA <= Ant_CtrlWord_running[127];
|
||||
end
|
||||
else
|
||||
begin
|
||||
Ant_EN <= 1'b1;
|
||||
Ant_DATA <= 1'b0;
|
||||
end
|
||||
|
||||
if(data_valid_countdown[15:0] <= 16'd48 && data_valid_countdown[15:0] > 16'd0)
|
||||
Ant_DARY <= 1'b0;
|
||||
else
|
||||
Ant_DARY <= 1'b1;
|
||||
|
||||
if(data_valid_countdown[15:0] == 16'd48)
|
||||
Ant_TR <= vio_trdirection;
|
||||
else
|
||||
Ant_TR <= Ant_TR;
|
||||
end
|
||||
|
||||
|
||||
//RF recv_data
|
||||
reg [1:0] state_rfdata;
|
||||
reg SPI_SYN_F_d1 = 1'b0;
|
||||
reg [15:0] cnt_rfdata = 16'd0;
|
||||
reg [95:0] RF_RecvWord = 96'd0;
|
||||
reg [95:0] RF_RecvWord_last = 96'd0;
|
||||
|
||||
reg [7:0] RF_temperature = 8'd0 ;
|
||||
reg [7:0] RF_IFlocked = 8'd0 ;
|
||||
reg [7:0] RF_RFAlocked = 8'd0 ;
|
||||
reg [7:0] RF_RFBlocked = 8'd0 ;
|
||||
reg [3:0] RF_ch1mgc = 4'd0 ;
|
||||
reg [3:0] RF_ch2mgc = 4'd0 ;
|
||||
reg [3:0] RF_ch3mgc = 4'd0 ;
|
||||
reg [3:0] RF_ch4mgc = 4'd0 ;
|
||||
reg [31:0] RF_Framecount = 32'd0 ;
|
||||
|
||||
always @ (posedge clk_48m) begin
|
||||
if(sys_rst) begin
|
||||
state_rfdata[1:0] <= 2'd0;
|
||||
SPI_SYN_F_d1 <= 1'b0;
|
||||
RF_RecvWord[95:0] <= 96'd0;
|
||||
cnt_rfdata[15:0] <= 16'd0;
|
||||
RF_temperature[7:0] <= 8'd0 ;
|
||||
RF_IFlocked[7:0] <= 8'd0 ;
|
||||
RF_RFAlocked[7:0] <= 8'd0 ;
|
||||
RF_RFBlocked[7:0] <= 8'd0 ;
|
||||
RF_ch1mgc[3:0] <= 4'd0 ;
|
||||
RF_ch2mgc[3:0] <= 4'd0 ;
|
||||
RF_ch3mgc[3:0] <= 4'd0 ;
|
||||
RF_ch4mgc[3:0] <= 4'd0 ;
|
||||
RF_Framecount[31:0] <= 32'd0;
|
||||
end
|
||||
else begin
|
||||
RF_RecvWord[95:0] <= {RF_RecvWord[94:0],SPI_MISO_F};
|
||||
|
||||
if (RF_RecvWord[95:88] == 8'hAA && RF_RecvWord[7:0] == 8'hCC) begin//校验帧头帧尾
|
||||
RF_temperature[7:0] <= RF_RecvWord[87:80];
|
||||
RF_IFlocked[7:0] <= RF_RecvWord[79:72];
|
||||
RF_RFAlocked[7:0] <= RF_RecvWord[71:64];
|
||||
RF_RFBlocked[7:0] <= RF_RecvWord[63:56];
|
||||
RF_ch1mgc[3:0] <= RF_RecvWord[55:52];
|
||||
RF_ch2mgc[3:0] <= RF_RecvWord[51:48];
|
||||
RF_ch3mgc[3:0] <= RF_RecvWord[47:44];
|
||||
RF_ch4mgc[3:0] <= RF_RecvWord[43:40];
|
||||
RF_Framecount[31:0] <= RF_RecvWord[39:8];
|
||||
RF_RecvWord_last <= RF_RecvWord;
|
||||
end
|
||||
else begin // hold otherwise
|
||||
RF_temperature[7:0] <= RF_temperature[7:0];
|
||||
RF_IFlocked[7:0] <= RF_IFlocked[7:0] ;
|
||||
RF_RFAlocked[7:0] <= RF_RFAlocked[7:0] ;
|
||||
RF_RFBlocked[7:0] <= RF_RFBlocked[7:0] ;
|
||||
RF_ch1mgc[3:0] <= RF_ch1mgc[3:0] ;
|
||||
RF_ch2mgc[3:0] <= RF_ch2mgc[3:0] ;
|
||||
RF_ch3mgc[3:0] <= RF_ch3mgc[3:0] ;
|
||||
RF_ch4mgc[3:0] <= RF_ch4mgc[3:0] ;
|
||||
RF_Framecount[31:0] <= RF_Framecount[31:0];
|
||||
RF_RecvWord_last <= RF_RecvWord_last;
|
||||
end
|
||||
end
|
||||
end
|
||||
// 天线的输出时钟转换
|
||||
reg Ant_dclk_96m = 1;
|
||||
wire [3:0] fifo_wr_din, fifo_rd_dout;
|
||||
wire fifo_full, fifo_empty;
|
||||
reg Ant_EN_96m = 0;
|
||||
reg Ant_DATA_96m = 0;
|
||||
reg Ant_DARY_96m = 1;
|
||||
reg Ant_TR_96m = 0;
|
||||
assign fifo_wr_din[3] = Ant_EN;
|
||||
assign fifo_wr_din[2] = Ant_DATA;
|
||||
assign fifo_wr_din[1] = Ant_DARY;
|
||||
assign fifo_wr_din[0] = Ant_TR;
|
||||
reg fifo_rd_en = 0;
|
||||
reg fifo_rst = 0;
|
||||
reg [8:0] Ant_clk_countdown = 0;
|
||||
always @(posedge clk_96m)
|
||||
begin
|
||||
fifo_rst <= sys_rst;
|
||||
|
||||
fifo_rd_en <= (fifo_rst == 1'b1)? 1'b0:!fifo_rd_en;
|
||||
|
||||
if(fifo_rd_en)
|
||||
{Ant_EN_96m,Ant_DATA_96m,Ant_DARY_96m,Ant_TR_96m} <= fifo_rd_dout[3:0];
|
||||
else
|
||||
{Ant_EN_96m,Ant_DATA_96m,Ant_DARY_96m,Ant_TR_96m} <= {Ant_EN_96m,Ant_DATA_96m,Ant_DARY_96m,Ant_TR_96m};
|
||||
|
||||
if(fifo_rd_en && Ant_EN_96m && !fifo_rd_dout[3])
|
||||
Ant_clk_countdown[8:0] <= 9'd276;
|
||||
else if(Ant_clk_countdown[8:0] != 9'd0)
|
||||
Ant_clk_countdown[8:0] <= Ant_clk_countdown[8:0] - 9'd1;
|
||||
else
|
||||
Ant_clk_countdown[8:0] <= Ant_clk_countdown[8:0];
|
||||
end
|
||||
assign ant_clk = !Ant_clk_countdown[0];
|
||||
assign ant_en = Ant_EN_96m;
|
||||
assign ant_data = Ant_DATA_96m;
|
||||
assign ant_tr = Ant_TR_96m;
|
||||
assign ant_dary = Ant_DARY_96m;
|
||||
|
||||
fifo_AntCtrl fifo_AntCtrl
|
||||
(
|
||||
.rst (fifo_rst ), // input wire rst
|
||||
.wr_clk (clk_48m ), // input wire wr_clk
|
||||
.rd_clk (clk_96m ), // input wire rd_clk
|
||||
.din (fifo_wr_din[3:0] ), // input wire [3 : 0] din
|
||||
.wr_en (!fifo_rst ), // input wire wr_en
|
||||
.rd_en (fifo_rd_en ), // input wire rd_en
|
||||
.dout (fifo_rd_dout[3:0] ), // output wire [3 : 0] dout
|
||||
.full (fifo_full ), // output wire full
|
||||
.empty (fifo_empty ) // output wire empty
|
||||
);
|
||||
//Ant recv_data
|
||||
reg [1:0] state_antdata;
|
||||
reg Ant_EN_96m_d1 = 1'b0;
|
||||
reg [15:0] cnt_antdata = 16'd0;
|
||||
reg [95:0] Ant_RecvWord = 'b0;
|
||||
reg [95:0] Ant_RecvWord_last = 'b0;
|
||||
|
||||
reg [7:0] Ant_Ant_Volt = 8'd0 ;
|
||||
reg [7:0] Ant_RF_Volt = 8'd0 ;
|
||||
reg [7:0] Ant_IF_Volt = 8'd0 ;
|
||||
reg [7:0] Ant_state = 8'd0 ;
|
||||
reg [31:0] Ant_Framecount = 32'd0 ;
|
||||
|
||||
always @ (posedge clk_96m) begin
|
||||
if(sys_rst) begin
|
||||
state_antdata[1:0] <= 2'd0;
|
||||
Ant_EN_96m_d1 <= 1'b0;
|
||||
Ant_RecvWord[95:0] <= 'd0;
|
||||
cnt_antdata[15:0] <= 16'd0;
|
||||
Ant_Ant_Volt[7:0] <= 8'd0 ;
|
||||
Ant_RF_Volt[7:0] <= 8'd0 ;
|
||||
Ant_IF_Volt[7:0] <= 8'd0 ;
|
||||
Ant_state[7:0] <= 8'd0 ;
|
||||
Ant_Framecount[31:0] <= 32'd0;
|
||||
end
|
||||
else begin
|
||||
Ant_RecvWord[95:0] <= {Ant_RecvWord[94:0],ant_dout};
|
||||
|
||||
if(Ant_RecvWord[95:88] == 8'hAA && Ant_RecvWord[7:0] == 8'hCC) begin//校验帧头帧尾
|
||||
Ant_Ant_Volt[7:0] <= Ant_RecvWord[87:80];
|
||||
Ant_RF_Volt[7:0] <= Ant_RecvWord[79:72];
|
||||
Ant_IF_Volt[7:0] <= Ant_RecvWord[71:64];
|
||||
Ant_state[7:0] <= Ant_RecvWord[47:40];
|
||||
Ant_Framecount[31:0] <= Ant_RecvWord[39:8] ;
|
||||
Ant_RecvWord_last <= Ant_RecvWord ;
|
||||
end
|
||||
else begin // hold otherwise
|
||||
Ant_Ant_Volt[7:0] <= Ant_Ant_Volt[7:0] ;
|
||||
Ant_RF_Volt[7:0] <= Ant_RF_Volt[7:0] ;
|
||||
Ant_IF_Volt[7:0] <= Ant_IF_Volt[7:0] ;
|
||||
Ant_state[7:0] <= Ant_state[7:0] ;
|
||||
Ant_Framecount[31:0] <= Ant_Framecount[31:0] ;
|
||||
Ant_RecvWord_last <= Ant_RecvWord_last ;
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
Sisyif uut(
|
||||
.clk_40m(clk_32m),
|
||||
.clk_20m(clk_19p2m),
|
||||
.SPI_CLK_F(clk_48m),
|
||||
.rst_n(rst_n),
|
||||
.SPI_SYN_F(SPI_SYN_F),
|
||||
.SPI_MOSI_F(SPI_MOSI_F),
|
||||
.SPI_MISO_F(SPI_MISO_F),
|
||||
.TP_EN_F(TP_EN_F),
|
||||
.TR_MGC_F(TR_MGC_F),
|
||||
.CAL_F(CAL_F),
|
||||
.PRF(PRF),
|
||||
.standby(rf_standby),
|
||||
.SW_PLL(rf_sw_pll),
|
||||
.T(rf_t),
|
||||
.R(rf_r),
|
||||
.SW_BPF(rf_sw_bpf),
|
||||
.SCLK1(rf_sclk1),
|
||||
.SDIO1(rf_sdio1),
|
||||
.CS1(rf_cs1),
|
||||
.LD1(rf_ld1),
|
||||
.SCLK2(rf_sclk2),
|
||||
.SDIO2(rf_sdio2),
|
||||
.CS2(rf_cs2),
|
||||
.LD2(rf_ld2),
|
||||
.SCLK3(rf_sclk3),
|
||||
.SDIO3(rf_sdio3),
|
||||
.CS3(rf_cs3),
|
||||
.LD3(rf_ld3),
|
||||
.TMGC_16db(rf_tmgc_16),
|
||||
.TMGC_8db(rf_tmgc_8),
|
||||
.TMGC_4db(rf_tmgc_4),
|
||||
.TMGC_2db(rf_tmgc_2),
|
||||
.TMGC_1db(rf_tmgc_1),
|
||||
.RMGC_16db(rf_rmgc_16),
|
||||
.RMGC_8db(rf_rmgc_8),
|
||||
.RMGC_4db(rf_rmgc_4),
|
||||
.RMGC_2db(rf_rmgc_2),
|
||||
.RMGC_1db(rf_rmgc_1),
|
||||
.ENABLE(rf_enable),
|
||||
.SC(rf_sc),
|
||||
.SD(rf_sd),
|
||||
.END_SYN(rf_endsyn),
|
||||
.SDOUT(rf_sdout),
|
||||
.DQ_WD(rf_dq_wd),
|
||||
.SW_RX(rf_sw_rx)
|
||||
);
|
||||
|
||||
endmodule
|
||||
+443
@@ -0,0 +1,443 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 2022/09/14 16:45:10
|
||||
// Last Modified Data: 2023/02/12 17:10
|
||||
// Design Name:
|
||||
// Module Name: ad9361_phase_cal_coarse
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// 2022/09/14 16:45:10 - File Created
|
||||
// 2023/02/12 17:10 - 修改：校准未完成时，将输入信号寄存输出。
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module ad9361_phase_cal_coarse
|
||||
#(
|
||||
parameter COUNTER_MOD = 48,
|
||||
parameter PEAK_POS = 12,
|
||||
parameter ADC_DATA_WIDTH = 12
|
||||
)
|
||||
(
|
||||
// clock & reset
|
||||
input clk ,
|
||||
input rst ,
|
||||
// control interface
|
||||
input ad9361_1_cal_start ,
|
||||
output ad9361_1_cal_done ,
|
||||
input ad9361_2_cal_start ,
|
||||
output ad9361_2_cal_done ,
|
||||
output ad9361_cal_result ,
|
||||
output ad9361_cal_valid ,
|
||||
input ad9361_recal ,
|
||||
// input data interface
|
||||
input [ADC_DATA_WIDTH-1:0] rx_ch1_i ,
|
||||
input [ADC_DATA_WIDTH-1:0] rx_ch1_q ,
|
||||
input [ADC_DATA_WIDTH-1:0] rx_ch2_i ,
|
||||
input [ADC_DATA_WIDTH-1:0] rx_ch2_q ,
|
||||
input [ADC_DATA_WIDTH-1:0] rx_ch3_i ,
|
||||
input [ADC_DATA_WIDTH-1:0] rx_ch3_q ,
|
||||
input [ADC_DATA_WIDTH-1:0] rx_ch4_i ,
|
||||
input [ADC_DATA_WIDTH-1:0] rx_ch4_q ,
|
||||
// output data interface
|
||||
output [ADC_DATA_WIDTH-1:0] rx_cal_ch1_i,
|
||||
output [ADC_DATA_WIDTH-1:0] rx_cal_ch1_q,
|
||||
output [ADC_DATA_WIDTH-1:0] rx_cal_ch2_i,
|
||||
output [ADC_DATA_WIDTH-1:0] rx_cal_ch2_q,
|
||||
output [ADC_DATA_WIDTH-1:0] rx_cal_ch3_i,
|
||||
output [ADC_DATA_WIDTH-1:0] rx_cal_ch3_q,
|
||||
output [ADC_DATA_WIDTH-1:0] rx_cal_ch4_i,
|
||||
output [ADC_DATA_WIDTH-1:0] rx_cal_ch4_q
|
||||
);
|
||||
|
||||
localparam STATE_IDLE = 2'd0;
|
||||
localparam STATE_CAL_1 = 2'd1;
|
||||
localparam STATE_CAL_2 = 2'd2;
|
||||
localparam STATE_DONE = 2'd3;
|
||||
|
||||
// buffer input control signals
|
||||
reg ad9361_1_cal_start_d1 = 'b0;
|
||||
reg ad9361_1_cal_start_d2 = 'b0;
|
||||
reg ad9361_2_cal_start_d1 = 'b0;
|
||||
reg ad9361_2_cal_start_d2 = 'b0;
|
||||
reg ad9361_recal_d1 = 'b0;
|
||||
reg ad9361_recal_d2 = 'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
ad9361_1_cal_start_d1 <= ad9361_1_cal_start;
|
||||
ad9361_1_cal_start_d2 <= ad9361_1_cal_start_d1;
|
||||
|
||||
ad9361_2_cal_start_d1 <= ad9361_2_cal_start;
|
||||
ad9361_2_cal_start_d2 <= ad9361_2_cal_start_d1;
|
||||
|
||||
ad9361_recal_d1 <= ad9361_recal;
|
||||
ad9361_recal_d2 <= ad9361_recal_d1;
|
||||
end
|
||||
|
||||
// center state machine
|
||||
reg [ 1:0] curr_state = STATE_IDLE;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
curr_state <= STATE_IDLE;
|
||||
end
|
||||
else begin
|
||||
case (curr_state)
|
||||
STATE_IDLE: begin
|
||||
// move to next state when [ad9361_1_cal_start] asserts
|
||||
curr_state <= ad9361_1_cal_start_d2 ? STATE_CAL_1 : STATE_IDLE;
|
||||
end
|
||||
STATE_CAL_1: begin
|
||||
// move to next state when 1st cal finishes [ad9361_2_cal_start] asserts
|
||||
curr_state <= (ad9361_1_cal_done && ad9361_2_cal_start_d2) ? STATE_CAL_2 : STATE_CAL_1;
|
||||
end
|
||||
STATE_CAL_2: begin
|
||||
// move to next state when 2nd cal finishes
|
||||
curr_state <= ad9361_2_cal_done ? STATE_DONE : STATE_CAL_2;
|
||||
end
|
||||
STATE_DONE: begin
|
||||
// move to ILDA state when it needs to recal
|
||||
curr_state <= (ad9361_recal_d2) ? STATE_IDLE : STATE_DONE;
|
||||
end
|
||||
default: begin
|
||||
curr_state <= STATE_IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
//
|
||||
reg rx_ch2_i_msb_d1 = 'b0;
|
||||
reg cnt_start = 'b0;
|
||||
reg cnt_start_flag = 'b0;
|
||||
reg [$clog2(COUNTER_MOD)-1:0] cnt = 'b0;
|
||||
reg [ADC_DATA_WIDTH-1:0] rx_ch2_i_rec = 'b0;
|
||||
reg rx_ch2_i_rec_flag = 'b0;
|
||||
|
||||
assign ad9361_1_cal_done = rx_ch2_i_rec_flag;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
rx_ch2_i_msb_d1 <= 'b0;
|
||||
end
|
||||
else if (curr_state == STATE_IDLE) begin
|
||||
// reset at IDLE state
|
||||
rx_ch2_i_msb_d1 <= 'b0;
|
||||
end
|
||||
else if (curr_state == STATE_CAL_1) begin
|
||||
rx_ch2_i_msb_d1 <= rx_ch2_i[ADC_DATA_WIDTH-1];
|
||||
end
|
||||
else begin
|
||||
rx_ch2_i_msb_d1 <= rx_ch2_i_msb_d1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cnt_start <= 'b0;
|
||||
end
|
||||
else if (curr_state == STATE_IDLE) begin
|
||||
// reset at IDLE state
|
||||
cnt_start <= 'b0;
|
||||
end
|
||||
else if (curr_state == STATE_CAL_1 && ~cnt_start) begin
|
||||
// assert when the 1st falling edge of msb of rx_ch2_i is detected
|
||||
cnt_start <= (rx_ch2_i_msb_d1 & ~rx_ch2_i[ADC_DATA_WIDTH-1]) ? 1'b1 : 1'b0;
|
||||
end
|
||||
else begin
|
||||
cnt_start <= cnt_start;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cnt <= 'b0;
|
||||
end
|
||||
else if (curr_state == STATE_IDLE) begin
|
||||
// reset at IDLE state
|
||||
cnt <= 'b0;
|
||||
end
|
||||
else if (cnt_start) begin
|
||||
cnt <= (cnt == COUNTER_MOD - 1) ? 'b0 : cnt + 1'b1;
|
||||
end
|
||||
else begin
|
||||
cnt <= cnt;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
rx_ch2_i_rec <= 'b0;
|
||||
rx_ch2_i_rec_flag <= 'b0;
|
||||
end
|
||||
else if (curr_state == STATE_IDLE) begin
|
||||
// reset at IDLE state
|
||||
rx_ch2_i_rec <= 'b0;
|
||||
rx_ch2_i_rec_flag <= 'b0;
|
||||
end
|
||||
else if (curr_state == STATE_CAL_1 && cnt == PEAK_POS && ~rx_ch2_i_rec_flag) begin
|
||||
rx_ch2_i_rec <= rx_ch2_i;
|
||||
rx_ch2_i_rec_flag <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
rx_ch2_i_rec <= rx_ch2_i_rec;
|
||||
rx_ch2_i_rec_flag <= rx_ch2_i_rec_flag;
|
||||
end
|
||||
end
|
||||
|
||||
//
|
||||
reg [ADC_DATA_WIDTH-1:0] rx_ch4_i_rec = 'b0;
|
||||
reg rx_ch4_i_rec_flag = 'b0;
|
||||
|
||||
assign ad9361_2_cal_done = rx_ch4_i_rec_flag;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
rx_ch4_i_rec <= 'b0;
|
||||
rx_ch4_i_rec_flag <= 'b0;
|
||||
end
|
||||
else if (curr_state == STATE_IDLE) begin
|
||||
// reset at IDLE state
|
||||
rx_ch4_i_rec <= 'b0;
|
||||
rx_ch4_i_rec_flag <= 'b0;
|
||||
end
|
||||
else if (curr_state == STATE_CAL_2 && cnt == COUNTER_MOD/4 && ~rx_ch4_i_rec_flag) begin
|
||||
rx_ch4_i_rec <= rx_ch4_i;
|
||||
rx_ch4_i_rec_flag <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
rx_ch4_i_rec <= rx_ch4_i_rec;
|
||||
rx_ch4_i_rec_flag <= rx_ch4_i_rec_flag;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
reg ad9361_cal_valid_buf = 'b0;
|
||||
reg ad9361_cal_result_buf = 'b0;
|
||||
reg [ADC_DATA_WIDTH-1:0] rx_cal_ch1_i_buf = 'b0;
|
||||
reg [ADC_DATA_WIDTH-1:0] rx_cal_ch2_i_buf = 'b0;
|
||||
reg [ADC_DATA_WIDTH-1:0] rx_cal_ch3_i_buf = 'b0;
|
||||
reg [ADC_DATA_WIDTH-1:0] rx_cal_ch4_i_buf = 'b0;
|
||||
reg [ADC_DATA_WIDTH-1:0] rx_cal_ch1_q_buf = 'b0;
|
||||
reg [ADC_DATA_WIDTH-1:0] rx_cal_ch2_q_buf = 'b0;
|
||||
reg [ADC_DATA_WIDTH-1:0] rx_cal_ch3_q_buf = 'b0;
|
||||
reg [ADC_DATA_WIDTH-1:0] rx_cal_ch4_q_buf = 'b0;
|
||||
|
||||
assign ad9361_cal_valid = ad9361_cal_valid_buf;
|
||||
assign ad9361_cal_result = ad9361_cal_result_buf;
|
||||
assign rx_cal_ch1_i = rx_cal_ch1_i_buf;
|
||||
assign rx_cal_ch2_i = rx_cal_ch2_i_buf;
|
||||
assign rx_cal_ch3_i = rx_cal_ch3_i_buf;
|
||||
assign rx_cal_ch4_i = rx_cal_ch4_i_buf;
|
||||
assign rx_cal_ch1_q = rx_cal_ch1_q_buf;
|
||||
assign rx_cal_ch2_q = rx_cal_ch2_q_buf;
|
||||
assign rx_cal_ch3_q = rx_cal_ch3_q_buf;
|
||||
assign rx_cal_ch4_q = rx_cal_ch4_q_buf;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
ad9361_cal_valid_buf <= 'b0;
|
||||
ad9361_cal_result_buf <= 'b0;
|
||||
rx_cal_ch1_i_buf <= 'b0;
|
||||
rx_cal_ch2_i_buf <= 'b0;
|
||||
rx_cal_ch3_i_buf <= 'b0;
|
||||
rx_cal_ch4_i_buf <= 'b0;
|
||||
rx_cal_ch1_q_buf <= 'b0;
|
||||
rx_cal_ch2_q_buf <= 'b0;
|
||||
rx_cal_ch3_q_buf <= 'b0;
|
||||
rx_cal_ch4_q_buf <= 'b0;
|
||||
end
|
||||
else if (curr_state == STATE_DONE) begin
|
||||
ad9361_cal_valid_buf <= 1'b1;
|
||||
|
||||
if (rx_ch2_i_rec[ADC_DATA_WIDTH-1] == rx_ch4_i_rec[ADC_DATA_WIDTH-1]) begin
|
||||
ad9361_cal_result_buf <= 'b0;
|
||||
rx_cal_ch1_i_buf <= rx_ch1_i;
|
||||
rx_cal_ch2_i_buf <= -rx_ch2_i;
|
||||
rx_cal_ch3_i_buf <= rx_ch3_i;
|
||||
rx_cal_ch4_i_buf <= -rx_ch4_i;
|
||||
rx_cal_ch1_q_buf <= rx_ch1_q;
|
||||
rx_cal_ch2_q_buf <= -rx_ch2_q;
|
||||
rx_cal_ch3_q_buf <= rx_ch3_q;
|
||||
rx_cal_ch4_q_buf <= -rx_ch4_q;
|
||||
end
|
||||
else begin
|
||||
ad9361_cal_result_buf <= 'b1;
|
||||
rx_cal_ch1_i_buf <= rx_ch1_i;
|
||||
rx_cal_ch2_i_buf <= -rx_ch2_i;
|
||||
rx_cal_ch3_i_buf <= -rx_ch3_i;
|
||||
rx_cal_ch4_i_buf <= rx_ch4_i;
|
||||
rx_cal_ch1_q_buf <= rx_ch1_q;
|
||||
rx_cal_ch2_q_buf <= -rx_ch2_q;
|
||||
rx_cal_ch3_q_buf <= -rx_ch3_q;
|
||||
rx_cal_ch4_q_buf <= rx_ch4_q;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
ad9361_cal_valid_buf <= 1'b0;
|
||||
ad9361_cal_result_buf <= ad9361_cal_result_buf;
|
||||
rx_cal_ch1_i_buf <= rx_ch1_i;
|
||||
rx_cal_ch2_i_buf <= rx_ch2_i;
|
||||
rx_cal_ch3_i_buf <= rx_ch3_i;
|
||||
rx_cal_ch4_i_buf <= rx_ch4_i;
|
||||
rx_cal_ch1_q_buf <= rx_ch1_q;
|
||||
rx_cal_ch2_q_buf <= rx_ch2_q;
|
||||
rx_cal_ch3_q_buf <= rx_ch3_q;
|
||||
rx_cal_ch4_q_buf <= rx_ch4_q;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 2022/09/15 11:12:45
|
||||
// Last Modified Data: 2022/11/02
|
||||
// Design Name:
|
||||
// Module Name: tb_ad9361_cal_coarse
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description: testbench for [ad9361_phase_cal_coarse]
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
// module tb_ad9361_cal_coarse;
|
||||
|
||||
// reg clk = 'b0;
|
||||
// reg rst = 1'b1;
|
||||
|
||||
// reg ad9361_1_cal_start = 'b0;
|
||||
// wire ad9361_1_cal_done ;
|
||||
// reg ad9361_2_cal_start = 'b0;
|
||||
// wire ad9361_2_cal_done ;
|
||||
// wire ad9361_cal_result ;
|
||||
// wire ad9361_cal_valid;
|
||||
// reg ad9361_recal = 'b0;
|
||||
|
||||
// // phase difference of 180 degree
|
||||
// reg [11:0] rx_ch1_i = 12'd2047;
|
||||
// reg [11:0] rx_ch1_q = 12'd2047;
|
||||
// reg [11:0] rx_ch2_i = -12'd2047;
|
||||
// reg [11:0] rx_ch2_q = -12'd2047;
|
||||
// reg [11:0] rx_ch3_q = -12'd2047;
|
||||
// reg [11:0] rx_ch3_i = -12'd2047;
|
||||
// reg [11:0] rx_ch4_i = 12'd2047;
|
||||
// reg [11:0] rx_ch4_q = 12'd2047;
|
||||
|
||||
// wire [11:0] rx_cal_ch1_i;
|
||||
// wire [11:0] rx_cal_ch2_i;
|
||||
// wire [11:0] rx_cal_ch3_i;
|
||||
// wire [11:0] rx_cal_ch4_i;
|
||||
// wire [11:0] rx_cal_ch1_q;
|
||||
// wire [11:0] rx_cal_ch2_q;
|
||||
// wire [11:0] rx_cal_ch3_q;
|
||||
// wire [11:0] rx_cal_ch4_q;
|
||||
|
||||
// ad9361_phase_cal #(
|
||||
// .COUNTER_MOD (48),
|
||||
// .PEAK_POS (12)
|
||||
// ) u_ad9361_phase_cal
|
||||
// (
|
||||
// // clock & reset
|
||||
// .clk (clk ), // input clk
|
||||
// .rst (rst ), // input rst
|
||||
// // control interface
|
||||
// .ad9361_1_cal_start (ad9361_1_cal_start ), // input ad9361_1_cal_start
|
||||
// .ad9361_1_cal_done (ad9361_1_cal_done ), // output ad9361_1_cal_done
|
||||
// .ad9361_2_cal_start (ad9361_2_cal_start ), // input ad9361_2_cal_start
|
||||
// .ad9361_2_cal_done (ad9361_2_cal_done ), // output ad9361_2_cal_done
|
||||
// .ad9361_cal_result (ad9361_cal_result ), // output ad9361_cal_result
|
||||
// .ad9361_cal_valid (ad9361_cal_valid ), // output ad9361_cal_valid
|
||||
// .ad9361_recal (ad9361_recal ), // input ad9361_recal
|
||||
// // input data interface
|
||||
// .rx_ch1_i (rx_ch1_i ), // input [11:0] rx_ch1_i
|
||||
// .rx_ch2_i (rx_ch2_i ), // input [11:0] rx_ch2_i
|
||||
// .rx_ch3_i (rx_ch3_i ), // input [11:0] rx_ch3_i
|
||||
// .rx_ch4_i (rx_ch4_i ), // input [11:0] rx_ch4_i
|
||||
// .rx_ch1_q (rx_ch1_q ), // input [11:0] rx_ch1_q
|
||||
// .rx_ch2_q (rx_ch2_q ), // input [11:0] rx_ch2_q
|
||||
// .rx_ch3_q (rx_ch3_q ), // input [11:0] rx_ch3_q
|
||||
// .rx_ch4_q (rx_ch4_q ), // input [11:0] rx_ch4_q
|
||||
// // output data interface
|
||||
// .rx_cal_ch1_i (rx_cal_ch1_i ), // output [11:0] rx_cal_ch1_i
|
||||
// .rx_cal_ch2_i (rx_cal_ch2_i ), // output [11:0] rx_cal_ch2_i
|
||||
// .rx_cal_ch3_i (rx_cal_ch3_i ), // output [11:0] rx_cal_ch3_i
|
||||
// .rx_cal_ch4_i (rx_cal_ch4_i ), // output [11:0] rx_cal_ch4_i
|
||||
// .rx_cal_ch1_q (rx_cal_ch1_q ), // output [11:0] rx_cal_ch1_q
|
||||
// .rx_cal_ch2_q (rx_cal_ch2_q ), // output [11:0] rx_cal_ch2_q
|
||||
// .rx_cal_ch3_q (rx_cal_ch3_q ), // output [11:0] rx_cal_ch3_q
|
||||
// .rx_cal_ch4_q (rx_cal_ch4_q ) // output [11:0] rx_cal_ch4_q
|
||||
// );
|
||||
|
||||
// initial begin
|
||||
// #102
|
||||
// rst = 1'b0;
|
||||
// #100
|
||||
// ad9361_1_cal_start = 1'b1;
|
||||
// end
|
||||
|
||||
// initial begin
|
||||
// #10000
|
||||
// ad9361_recal = 1'b1;
|
||||
// #20
|
||||
// ad9361_recal = 1'b0;
|
||||
// end
|
||||
|
||||
// always begin
|
||||
// #2 clk = ~clk;
|
||||
// end
|
||||
|
||||
// always begin
|
||||
// #72
|
||||
// rx_ch1_i = ~rx_ch1_i;
|
||||
// rx_ch2_i = ~rx_ch2_i;
|
||||
// rx_ch3_i = ~rx_ch3_i;
|
||||
// rx_ch4_i = ~rx_ch4_i;
|
||||
// #24
|
||||
// rx_ch1_q = ~rx_ch1_q;
|
||||
// rx_ch2_q = ~rx_ch2_q;
|
||||
// rx_ch3_q = ~rx_ch3_q;
|
||||
// rx_ch4_q = ~rx_ch4_q;
|
||||
// end
|
||||
|
||||
// always @(posedge clk) begin
|
||||
// if (ad9361_1_cal_done) begin
|
||||
// ad9361_2_cal_start <= 1'b1;
|
||||
// end
|
||||
// else begin
|
||||
// ad9361_2_cal_start <= 1'b0;
|
||||
// end
|
||||
// end
|
||||
|
||||
// endmodule
|
||||
+133
@@ -0,0 +1,133 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 2022/11/01 11:15:25
|
||||
// Design Name:
|
||||
// Module Name: clk_dist
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description: Clock distribution module
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module clk_dist
|
||||
(
|
||||
// input clocks
|
||||
input clk_250m_p , // generated by ad9516, 250mhz
|
||||
input clk_250m_n ,
|
||||
input ad9361_1_rx_data_clk, // ad9361 rx data clock, 83.3333mhz
|
||||
input ad9361_2_rx_data_clk, // ad9361 rx data clock, 83.3333mhz
|
||||
|
||||
// output clocks & reset
|
||||
// global reset
|
||||
output sys_rst , // global reset signal, active high
|
||||
output ant_rst , // phased-array & rf control reset signal, active high
|
||||
|
||||
// pl signal processing clock
|
||||
output sys_clk , // 41.6667mhz
|
||||
output sys_clk_2x , // 83.3333mhz
|
||||
output sys_clk_3x , // 125mhz
|
||||
output sys_clk_4x , // 166.6667mhz
|
||||
output sys_clk_ld , // system main clock locked indicator
|
||||
|
||||
// ad9361-1 clocks
|
||||
output ad9361_1_clk , // 41.6667mhz
|
||||
output ad9361_1_clk_2x , // 83.3333mhz
|
||||
output ad9361_1_clk_3x , // 125mhz
|
||||
output ad9361_1_clk_4x , // 166.6667mhz
|
||||
output ad9361_1_clk_ld , // ad9361-1 clock group locked indicator
|
||||
|
||||
// ad9361-2 clocks
|
||||
output ad9361_2_clk , // 41.6667mhz
|
||||
output ad9361_2_clk_2x , // 83.3333mhz
|
||||
output ad9361_2_clk_3x , // 125mhz
|
||||
output ad9361_2_clk_4x , // 166.6667mhz
|
||||
output ad9361_2_clk_ld , // ad9361-2 clock group locked indicator
|
||||
|
||||
// phased-array & rf control clocks
|
||||
output clk_96m ,
|
||||
output clk_48m ,
|
||||
output clk_32m ,
|
||||
output clk_19p2m
|
||||
);
|
||||
|
||||
assign sys_clk = ad9361_1_clk ;
|
||||
assign sys_clk_2x = ad9361_1_clk_2x;
|
||||
assign sys_clk_3x = ad9361_1_clk_3x;
|
||||
assign sys_clk_4x = ad9361_1_clk_4x;
|
||||
assign sys_clk_ld = ad9361_1_clk_ld;
|
||||
|
||||
assign sys_rst = ~sys_clk_ld;
|
||||
|
||||
ad9361_clk_gen_cmos_2t2r u_ad9361_1_clk_gen
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1 (ad9361_1_clk ), // output clk_out1
|
||||
.clk_out2 (ad9361_1_clk_2x ), // output clk_out2
|
||||
.clk_out3 (ad9361_1_clk_3x ), // output clk_out3
|
||||
.clk_out4 (ad9361_1_clk_4x ), // output clk_out4
|
||||
// Status and control signals
|
||||
.locked (ad9361_1_clk_ld ), // output locked
|
||||
// Clock in ports
|
||||
.clk_in1 (ad9361_1_rx_data_clk ) // input clk_in1
|
||||
);
|
||||
|
||||
ad9361_clk_gen_cmos_2t2r u_ad9361_2_clk_gen
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1 (ad9361_2_clk ), // output clk_out1
|
||||
.clk_out2 (ad9361_2_clk_2x ), // output clk_out2
|
||||
.clk_out3 (ad9361_2_clk_3x ), // output clk_out3
|
||||
.clk_out4 (ad9361_2_clk_4x ), // output clk_out4
|
||||
// Status and control signals
|
||||
.locked (ad9361_2_clk_ld ), // output locked
|
||||
// Clock in ports
|
||||
.clk_in1 (ad9361_2_rx_data_clk ) // input clk_in1
|
||||
);
|
||||
|
||||
wire ant_clk_stg1_96m;
|
||||
wire ant_clk_stg1_ld;
|
||||
wire ant_clk_stg2_ld;
|
||||
|
||||
assign ant_rst = ~ant_clk_stg2_ld;
|
||||
|
||||
ant_clk_gen_stg1 u_ant_clk_gen_stg1
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1 (ant_clk_stg1_96m ), // output clk_out1
|
||||
// Status and control signals
|
||||
.locked (ant_clk_stg1_ld ), // output locked
|
||||
// Clock in ports
|
||||
.clk_in1_p (clk_250m_p ), // input clk_in1_p
|
||||
.clk_in1_n (clk_250m_n ) // input clk_in1_n
|
||||
);
|
||||
|
||||
ant_clk_gen_stg2 u_ant_clk_gen_stg2
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1 (clk_96m ), // output clk_out1
|
||||
.clk_out2 (clk_48m ), // output clk_out2
|
||||
.clk_out3 (clk_32m ), // output clk_out3
|
||||
.clk_out4 (clk_19p2m ), // output clk_out4
|
||||
// Status and control signals
|
||||
.locked (ant_clk_stg2_ld ), // output locked
|
||||
// Clock in ports
|
||||
.clk_in1 (ant_clk_stg1_96m ) // input clk_in1
|
||||
);
|
||||
|
||||
endmodule
|
||||
+784
@@ -0,0 +1,784 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 2021/12/14 15:54:11
|
||||
// Design Name:
|
||||
// Module Name: system_top
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module system_top
|
||||
(
|
||||
/***************************************************************************
|
||||
* Contents
|
||||
* 01. Clocks
|
||||
* 02. HMC7044 Interface
|
||||
* 03. AD9361-1 Interface
|
||||
* 04. AD9361-2 Interface
|
||||
* 05. Phased-Array Control
|
||||
* 06. RF Synthesizer Control
|
||||
* 07. Debug IO
|
||||
* 08. DDR and Fixed-io (Do NOT Modify)
|
||||
**************************************************************************/
|
||||
|
||||
// *************************************************************************
|
||||
// ******************************** Clocks *********************************
|
||||
// *************************************************************************
|
||||
// fpga logic clock
|
||||
input clk_250m_p , // generated by hmc7044, 250mhz
|
||||
input clk_250m_n ,
|
||||
// ad9361 buffered clock
|
||||
input ad9361_1_buffer_clk , // derived from ad9361 input clock
|
||||
input ad9361_2_buffer_clk , // derived from ad9361 input clock
|
||||
// *************************************************************************
|
||||
// *************************** HMC7044 Interface ***************************
|
||||
// *************************************************************************
|
||||
// spi interface
|
||||
output hmc7044_spi_clk ,
|
||||
output hmc7044_spi_csn ,
|
||||
inout hmc7044_spi_sdio ,
|
||||
// control signals
|
||||
output hmc7044_reset , // hmc7044 active-high reset signal, set to 0 in normal operation
|
||||
output hmc7044_sync , // hmc7044 multichip synchronization signal, set to 0 if not used
|
||||
// gpio
|
||||
inout [ 3:0] hmc7044_gpio ,
|
||||
// *************************************************************************
|
||||
// ************************** AD9361-1 Interface ***************************
|
||||
// *************************************************************************
|
||||
// rx data (rx channels are tied to ground physically)
|
||||
input ad9361_1_rx_data_clk, // ad9361 rx data clock, 96mhz
|
||||
input ad9361_1_rx_frame ,
|
||||
input [11:0] ad9361_1_rx_data ,
|
||||
// tx data
|
||||
output ad9361_1_tx_fb_clk ,
|
||||
output ad9361_1_tx_frame ,
|
||||
output [11:0] ad9361_1_tx_data ,
|
||||
// spi interface
|
||||
output ad9361_1_spi_clk ,
|
||||
output ad9361_1_spi_csn ,
|
||||
output ad9361_1_spi_mosi ,
|
||||
input ad9361_1_spi_miso ,
|
||||
// control signals
|
||||
output ad9361_1_reset_b , // ad9361 active-low reset control
|
||||
output ad9361_1_en_agc , // ad9361 manual agc control
|
||||
output ad9361_1_enable , // ad9361 enable state machine pin control (spi control is also allowed)
|
||||
output ad9361_1_txnrx , // ad9361 enable state machine pin control (spi control is also allowed)
|
||||
input [ 3:0] ad9361_1_ctrl_in ,
|
||||
output [ 7:0] ad9361_1_ctrl_out ,
|
||||
output ad9361_sync ,
|
||||
// *************************************************************************
|
||||
// ************************** AD9361-2 Interface ***************************
|
||||
// *************************************************************************
|
||||
// rx data (rx channels are tied to ground physically)
|
||||
input ad9361_2_rx_data_clk,
|
||||
input ad9361_2_rx_frame ,
|
||||
input [11:0] ad9361_2_rx_data ,
|
||||
// tx data
|
||||
output ad9361_2_tx_fb_clk ,
|
||||
output ad9361_2_tx_frame ,
|
||||
output [11:0] ad9361_2_tx_data ,
|
||||
// spi interface
|
||||
output ad9361_2_spi_clk ,
|
||||
output ad9361_2_spi_csn ,
|
||||
output ad9361_2_spi_mosi ,
|
||||
input ad9361_2_spi_miso ,
|
||||
// control signals
|
||||
output ad9361_2_reset_b , // ad9361 active-low reset control
|
||||
output ad9361_2_en_agc , // ad9361 manual agc control
|
||||
output ad9361_2_enable , // ad9361 enable state machine pin control (spi control is also allowed)
|
||||
output ad9361_2_txnrx , // ad9361 enable state machine pin control (spi control is also allowed)
|
||||
input [ 3:0] ad9361_2_ctrl_in ,
|
||||
output [ 7:0] ad9361_2_ctrl_out ,
|
||||
// *************************************************************************
|
||||
// ************************* Phased-Array Control **************************
|
||||
// *************************************************************************
|
||||
output ant_clk ,
|
||||
output ant_en ,
|
||||
output ant_data ,
|
||||
output ant_tr ,
|
||||
output ant_dary ,
|
||||
input ant_dout ,
|
||||
// *************************************************************************
|
||||
// ************************ RF Synthesizer Control *************************
|
||||
// *************************************************************************
|
||||
output rf_standby ,
|
||||
output rf_sw_pll ,
|
||||
output rf_t ,
|
||||
output rf_r ,
|
||||
output rf_sw_bpf ,
|
||||
output rf_sclk1 ,
|
||||
output rf_sdio1 ,
|
||||
output rf_cs1 ,
|
||||
input rf_ld1 ,
|
||||
output rf_sclk2 ,
|
||||
output rf_sdio2 ,
|
||||
output rf_cs2 ,
|
||||
input rf_ld2 ,
|
||||
output rf_sclk3 ,
|
||||
output rf_sdio3 ,
|
||||
output rf_cs3 ,
|
||||
input rf_ld3 ,
|
||||
output rf_tmgc_16 ,
|
||||
output rf_tmgc_8 ,
|
||||
output rf_tmgc_4 ,
|
||||
output rf_tmgc_2 ,
|
||||
output rf_tmgc_1 ,
|
||||
output rf_rmgc_16 ,
|
||||
output rf_rmgc_8 ,
|
||||
output rf_rmgc_4 ,
|
||||
output rf_rmgc_2 ,
|
||||
output rf_rmgc_1 ,
|
||||
output rf_enable ,
|
||||
output rf_sc ,
|
||||
output rf_sd ,
|
||||
output rf_endsyn ,
|
||||
input rf_sdout ,
|
||||
inout rf_dq_wd ,
|
||||
output rf_sw_rx ,
|
||||
// *************************************************************************
|
||||
// ******************************* Debug IO ********************************
|
||||
// *************************************************************************
|
||||
// 3.3v ports
|
||||
output uart1_txd ,
|
||||
input uart1_rxd ,
|
||||
output uart2_txd ,
|
||||
input uart2_rxd ,
|
||||
output uart3_txd ,
|
||||
input uart3_rxd ,
|
||||
// 1.8v ports
|
||||
inout debug_io_1 ,
|
||||
inout debug_io_2 ,
|
||||
// 3.3v ports
|
||||
inout debug_io_3 ,
|
||||
inout debug_io_4 ,
|
||||
inout debug_io_5 ,
|
||||
inout debug_io_6 ,
|
||||
inout debug_io_7 ,
|
||||
// *************************************************************************
|
||||
// ******************* DDR and Fixed-io (Do NOT Modify) ********************
|
||||
// *************************************************************************
|
||||
// ddr
|
||||
inout [14:0] ddr_addr ,
|
||||
inout [ 2:0] ddr_ba ,
|
||||
inout ddr_cas_n ,
|
||||
inout ddr_ck_n ,
|
||||
inout ddr_ck_p ,
|
||||
inout ddr_cke ,
|
||||
inout ddr_cs_n ,
|
||||
inout [ 3:0] ddr_dm ,
|
||||
inout [31:0] ddr_dq ,
|
||||
inout [ 3:0] ddr_dqs_n ,
|
||||
inout [ 3:0] ddr_dqs_p ,
|
||||
inout ddr_odt ,
|
||||
inout ddr_ras_n ,
|
||||
inout ddr_reset_n ,
|
||||
inout ddr_we_n ,
|
||||
// fixed-io
|
||||
inout fixed_io_ddr_vrn ,
|
||||
inout fixed_io_ddr_vrp ,
|
||||
inout [53:0] fixed_io_mio ,
|
||||
inout fixed_io_ps_clk ,
|
||||
inout fixed_io_ps_porb ,
|
||||
inout fixed_io_ps_srstb
|
||||
);
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/////////////////////////// System Clock Generation ////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// global reset
|
||||
wire sys_rst ; // global reset signal, active high
|
||||
wire ant_rst ; // phased-array & rf control reset signal, active high
|
||||
|
||||
// pl signal processing clock
|
||||
wire sys_clk ; // 48MHz 41.6667MHz
|
||||
wire sys_clk_2x ; // 96MHz 83.3333MHz
|
||||
wire sys_clk_3x ; // 144MHz 125MHz
|
||||
wire sys_clk_4x ; // 192MHz 166.6667MHz
|
||||
wire sys_clk_ld ; // system main clock locked indicator
|
||||
|
||||
// ad9361-1 clocks
|
||||
wire ad9361_1_clk ; // 48MHz 41.6667MHz
|
||||
wire ad9361_1_clk_2x ; // 96MHz 83.3333MHz
|
||||
wire ad9361_1_clk_3x ; // 144MHz 125MHz
|
||||
wire ad9361_1_clk_4x ; // 192MHz 166.6667MHz
|
||||
wire ad9361_1_clk_ld ; // ad9361-1 clock group locked indicator
|
||||
|
||||
// ad9361-2 clocks
|
||||
wire ad9361_2_clk ; // 48MHz 41.6667MHz
|
||||
wire ad9361_2_clk_2x ; // 96MHz 83.3333MHz
|
||||
wire ad9361_2_clk_3x ; // 144MHz 125MHz
|
||||
wire ad9361_2_clk_4x ; // 192MHz 166.6667MHz
|
||||
wire ad9361_2_clk_ld ; // ad9361-2 clock group locked indicator
|
||||
|
||||
// phased-array & rf control clocks
|
||||
wire clk_96m ;
|
||||
wire clk_48m ;
|
||||
wire clk_32m ;
|
||||
wire clk_19p2m ;
|
||||
|
||||
clk_dist u_clk_dist
|
||||
(
|
||||
// input clocks
|
||||
.clk_250m_p (clk_250m_p ), // generated by ad9516, 250mhz
|
||||
.clk_250m_n (clk_250m_n ),
|
||||
.ad9361_1_rx_data_clk(ad9361_1_rx_data_clk), // ad9361 rx data clock, 83.3333mhz
|
||||
.ad9361_2_rx_data_clk(ad9361_2_rx_data_clk), // ad9361 rx data clock, 83.3333mhz
|
||||
|
||||
// output clocks & reset
|
||||
// global reset
|
||||
.sys_rst (sys_rst ), // global reset signal, active high
|
||||
.ant_rst (ant_rst ), // phased-array & rf control reset signal, active high
|
||||
|
||||
// pl signal processing clock
|
||||
.sys_clk (sys_clk ), // 48MHz 41.6667MHz
|
||||
.sys_clk_2x (sys_clk_2x ), // 96MHz 83.3333MHz
|
||||
.sys_clk_3x (sys_clk_3x ), // 144MHz 125MHz
|
||||
.sys_clk_4x (sys_clk_4x ), // 192MHz 166.6667MHz
|
||||
.sys_clk_ld (sys_clk_ld ), // system main clock locked indicator
|
||||
|
||||
// ad9361-1 clocks
|
||||
.ad9361_1_clk (ad9361_1_clk ), // 48MHz 41.6667MHz
|
||||
.ad9361_1_clk_2x (ad9361_1_clk_2x ), // 96MHz 83.3333MHz
|
||||
.ad9361_1_clk_3x (ad9361_1_clk_3x ), // 144MHz 125MHz
|
||||
.ad9361_1_clk_4x (ad9361_1_clk_4x ), // 192MHz 166.6667MHz
|
||||
.ad9361_1_clk_ld (ad9361_1_clk_ld ), // ad9361-1 clock group locked indicator
|
||||
|
||||
// ad9361-2 clocks
|
||||
.ad9361_2_clk (ad9361_2_clk ), // 48MHz 41.6667MHz
|
||||
.ad9361_2_clk_2x (ad9361_2_clk_2x ), // 96MHz 83.3333MHz
|
||||
.ad9361_2_clk_3x (ad9361_2_clk_3x ), // 144MHz 125MHz
|
||||
.ad9361_2_clk_4x (ad9361_2_clk_4x ), // 192MHz 166.6667MHz
|
||||
.ad9361_2_clk_ld (ad9361_2_clk_ld ), // ad9361-2 clock group locked indicator
|
||||
|
||||
// phased-array & rf control clocks
|
||||
.clk_96m (clk_96m ),
|
||||
.clk_48m (clk_48m ),
|
||||
.clk_32m (clk_32m ),
|
||||
.clk_19p2m (clk_19p2m )
|
||||
);
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//////////////////////////// Block Design Interface ////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// gpio
|
||||
wire [47:0] gpio_i;
|
||||
wire [47:0] gpio_o;
|
||||
wire [47:0] gpio_t;
|
||||
wire ad9361_rx_fifo_rst;
|
||||
wire ad9361_1_cal_start;
|
||||
wire ad9361_1_cal_done;
|
||||
wire ad9361_2_cal_start;
|
||||
wire ad9361_2_cal_done;
|
||||
wire ad9361_cal_result;
|
||||
wire ad9361_recal;
|
||||
|
||||
assign gpio_i[47:47] = gpio_o[47:47];
|
||||
|
||||
// hmc7044
|
||||
assign hmc7044_reset = gpio_o[ 0]; // hmc7044 reset
|
||||
assign hmc7044_sync = gpio_o[ 1]; // hmc7044 multichip synchronization
|
||||
assign hmc7044_gpio[0] = gpio_t[ 2] ? gpio_i[ 2] : gpio_o[ 2];
|
||||
assign hmc7044_gpio[1] = gpio_t[ 3] ? gpio_i[ 3] : gpio_o[ 3];
|
||||
assign hmc7044_gpio[2] = gpio_t[ 4] ? gpio_i[ 4] : gpio_o[ 4];
|
||||
assign hmc7044_gpio[3] = gpio_t[ 5] ? gpio_i[ 5] : gpio_o[ 5];
|
||||
// ad9361-1
|
||||
assign ad9361_1_txnrx = gpio_o[ 6]; // ad9361 enable state machine control
|
||||
assign ad9361_1_enable = gpio_o[ 7]; // ad9361 enable state machine control
|
||||
assign ad9361_1_en_agc = gpio_o[ 8]; // ad9361 agc control
|
||||
assign ad9361_1_reset_b = gpio_o[ 9]; // ad9361 reset
|
||||
assign ad9361_1_ctrl_out = gpio_o[17:10];
|
||||
assign gpio_i[21:18] = ad9361_1_ctrl_in;
|
||||
// ad9361-2
|
||||
assign ad9361_2_txnrx = gpio_o[22]; // ad9361 enable state machine control
|
||||
assign ad9361_2_enable = gpio_o[23]; // ad9361 enable state machine control
|
||||
assign ad9361_2_en_agc = gpio_o[24]; // ad9361 agc control
|
||||
assign ad9361_2_reset_b = gpio_o[25]; // ad9361 reset
|
||||
assign ad9361_2_ctrl_out = gpio_o[33:26];
|
||||
assign gpio_i[37:34] = ad9361_2_ctrl_in;
|
||||
// ad9361 multichip sync
|
||||
assign ad9361_sync = gpio_o[38];
|
||||
assign ad9361_rx_fifo_rst = gpio_o[39];
|
||||
assign ad9361_1_cal_start = gpio_o[40];
|
||||
assign ad9361_2_cal_start = gpio_o[41];
|
||||
assign ad9361_recal = gpio_o[42];
|
||||
assign ad9361_tx_switch = gpio_o[43];
|
||||
assign gpio_i[44] = ad9361_1_cal_done;
|
||||
assign gpio_i[45] = ad9361_2_cal_done;
|
||||
assign gpio_i[46] = ad9361_cal_result;
|
||||
|
||||
// spi interface
|
||||
wire spi_sclk ;
|
||||
wire [ 2:0] spi_cs ;
|
||||
reg spi_sdi ;
|
||||
wire spi_sdo ;
|
||||
wire spi_sdo_t ;
|
||||
wire spi_three_wire;
|
||||
wire spi_active ;
|
||||
|
||||
// hmc7044 - three-wire spi
|
||||
assign hmc7044_spi_clk = spi_sclk;
|
||||
assign hmc7044_spi_csn = spi_cs[0];
|
||||
assign hmc7044_spi_sdio = spi_sdo_t ? 1'bz : spi_sdo;
|
||||
// ad9361-1 - three-wire spi or four-wire spi
|
||||
assign ad9361_1_spi_clk = spi_sclk;
|
||||
assign ad9361_1_spi_csn = spi_cs[1];
|
||||
assign ad9361_1_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
|
||||
// ad9361-2 - three-wire spi or four-wire spi
|
||||
assign ad9361_2_spi_clk = spi_sclk;
|
||||
assign ad9361_2_spi_csn = spi_cs[2];
|
||||
assign ad9361_2_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
|
||||
// select sdi signal
|
||||
always @(*) begin
|
||||
if (~hmc7044_spi_csn)
|
||||
spi_sdi = hmc7044_spi_sdio;
|
||||
else if (~ad9361_1_spi_csn)
|
||||
spi_sdi = spi_three_wire ? ad9361_1_spi_mosi : ad9361_1_spi_miso;
|
||||
else if (~ad9361_2_spi_csn)
|
||||
spi_sdi = spi_three_wire ? ad9361_2_spi_mosi : ad9361_2_spi_miso;
|
||||
else
|
||||
spi_sdi = 1'bz;
|
||||
end
|
||||
|
||||
system_bd_wrapper u_system_bd_wrapper
|
||||
(
|
||||
// ddr
|
||||
.DDR_addr (ddr_addr ), // inout [14:0]DDR_addr
|
||||
.DDR_ba (ddr_ba ), // inout [2:0]DDR_ba
|
||||
.DDR_cas_n (ddr_cas_n ), // inout DDR_cas_n
|
||||
.DDR_ck_n (ddr_ck_n ), // inout DDR_ck_n
|
||||
.DDR_ck_p (ddr_ck_p ), // inout DDR_ck_p
|
||||
.DDR_cke (ddr_cke ), // inout DDR_cke
|
||||
.DDR_cs_n (ddr_cs_n ), // inout DDR_cs_n
|
||||
.DDR_dm (ddr_dm ), // inout [3:0]DDR_dm
|
||||
.DDR_dq (ddr_dq ), // inout [31:0]DDR_dq
|
||||
.DDR_dqs_n (ddr_dqs_n ), // inout [3:0]DDR_dqs_n
|
||||
.DDR_dqs_p (ddr_dqs_p ), // inout [3:0]DDR_dqs_p
|
||||
.DDR_odt (ddr_odt ), // inout DDR_odt
|
||||
.DDR_ras_n (ddr_ras_n ), // inout DDR_ras_n
|
||||
.DDR_reset_n (ddr_reset_n ), // inout DDR_reset_n
|
||||
.DDR_we_n (ddr_we_n ), // inout DDR_we_n
|
||||
|
||||
// fixed-io
|
||||
.FIXED_IO_ddr_vrn (fixed_io_ddr_vrn ), // inout FIXED_IO_ddr_vrn
|
||||
.FIXED_IO_ddr_vrp (fixed_io_ddr_vrp ), // inout FIXED_IO_ddr_vrp
|
||||
.FIXED_IO_mio (fixed_io_mio ), // inout [53:0]FIXED_IO_mio
|
||||
.FIXED_IO_ps_clk (fixed_io_ps_clk ), // inout FIXED_IO_ps_clk
|
||||
.FIXED_IO_ps_porb (fixed_io_ps_porb ), // inout FIXED_IO_ps_porb
|
||||
.FIXED_IO_ps_srstb (fixed_io_ps_srstb ), // inout FIXED_IO_ps_srstb
|
||||
|
||||
// gpio, for control signals
|
||||
.GPIO_I (gpio_i ), // input [47:0]GPIO_I_0
|
||||
.GPIO_O (gpio_o ), // output [47:0]GPIO_O_0
|
||||
.GPIO_T (gpio_t ), // output [47:0]GPIO_T_0
|
||||
|
||||
// spi interface
|
||||
.spi_sclk (spi_sclk ), // output spi_sclk
|
||||
.spi_cs (spi_cs ), // output [2:0]spi_cs
|
||||
.spi_sdi (spi_sdi ), // input [0:0]spi_sdi
|
||||
.spi_sdo (spi_sdo ), // output spi_sdo
|
||||
.spi_sdo_t (spi_sdo_t ), // output spi_sdo_t
|
||||
.spi_three_wire (spi_three_wire ), // output spi_three_wire
|
||||
.spi_active (spi_active ) // output spi_active
|
||||
);
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
////////////////////////////////// Tx Signal ///////////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// baseband signal
|
||||
wire [11:0] tx_data_i;
|
||||
wire [11:0] tx_data_q;
|
||||
|
||||
ad9361_tx_map_cmos_dual u_ad9361_tx_map
|
||||
(
|
||||
.clk_2x_in (ad9361_1_clk_2x ), // input clk_2x_in
|
||||
.clk_in_rst (~ad9361_1_clk_ld ), // input clk_in_rst
|
||||
|
||||
.tx_data_clk (sys_clk ), // input tx_data_clk
|
||||
.tx_data_clk_rst(sys_rst ), // input tx_data_clk_rst
|
||||
|
||||
.tx_ch1_i (tx_data_i ), // input [11:0] tx_ch1_i
|
||||
.tx_ch1_q (tx_data_q ), // input [11:0] tx_ch1_q
|
||||
.tx_ch2_i (tx_data_i ), // input [11:0] tx_ch2_i
|
||||
.tx_ch2_q (tx_data_q ), // input [11:0] tx_ch2_q
|
||||
.clk_out (ad9361_1_tx_fb_clk ), // output clk_out
|
||||
.tx_frame (ad9361_1_tx_frame ), // output tx_frame
|
||||
.tx_data (ad9361_1_tx_data ) // output [11:0] tx_data
|
||||
);
|
||||
|
||||
assign ad9361_2_tx_fb_clk = ad9361_1_tx_fb_clk;
|
||||
// assign ad9361_2_tx_frame = ad9361_1_tx_frame ;
|
||||
// assign ad9361_2_tx_data = ad9361_1_tx_data ;
|
||||
|
||||
// <--------------------------------------------------------------------------->
|
||||
// <--------------------- insert transmitter logic below ---------------------->
|
||||
// <--------------------------------------------------------------------------->
|
||||
wire [ 1:0] waveform_sel;
|
||||
wire sweep_on ;
|
||||
wire [31:0] freq_set ;
|
||||
wire [ 1:0] iq_sel ;
|
||||
wire [ 3:0] bb_rshift ;
|
||||
|
||||
tx_qpsk u_tx_qpsk
|
||||
(
|
||||
.clk (sys_clk ), // input clk
|
||||
.rst (sys_rst ), // input rst
|
||||
.tx_data_i (tx_data_i ), // output [11:0] tx_data_i
|
||||
.tx_data_q (tx_data_q ), // output [11:0] tx_data_q
|
||||
// debug ports
|
||||
.waveform_sel (waveform_sel[1:0] ), // input [ 1:0] waveform_sel
|
||||
.sweep_on (sweep_on ), // input sweep_on
|
||||
.freq_set (freq_set ), // input [31:0] freq_set
|
||||
.iq_sel (iq_sel ), // input [ 1:0] iq_sel
|
||||
.bb_rshift (bb_rshift ) // input [ 3:0] bb_rshift
|
||||
);
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
////////////////////////////////// RF control //////////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
ant_rf_ctrl u_ant_rf_ctrl
|
||||
(
|
||||
.clk_48m (clk_48m ),
|
||||
.clk_96m (clk_96m ),
|
||||
.clk_32m (clk_32m ),
|
||||
.clk_19p2m (clk_19p2m ),
|
||||
.sys_rst (ant_rst ),
|
||||
|
||||
.ant_clk (ant_clk ),
|
||||
.ant_en (ant_en ),
|
||||
.ant_data (ant_data ),
|
||||
.ant_tr (ant_tr ),
|
||||
.ant_dary (ant_dary ),
|
||||
.ant_dout (ant_dout ),
|
||||
|
||||
.rf_standby (rf_standby ),
|
||||
.rf_sw_pll (rf_sw_pll ),
|
||||
.rf_t (rf_t ),
|
||||
.rf_r (rf_r ),
|
||||
.rf_sw_bpf (rf_sw_bpf ),
|
||||
.rf_sclk1 (rf_sclk1 ),
|
||||
.rf_sdio1 (rf_sdio1 ),
|
||||
.rf_cs1 (rf_cs1 ),
|
||||
.rf_ld1 (rf_ld1 ),
|
||||
.rf_sclk2 (rf_sclk2 ),
|
||||
.rf_sdio2 (rf_sdio2 ),
|
||||
.rf_cs2 (rf_cs2 ),
|
||||
.rf_ld2 (rf_ld2 ),
|
||||
.rf_sclk3 (rf_sclk3 ),
|
||||
.rf_sdio3 (rf_sdio3 ),
|
||||
.rf_cs3 (rf_cs3 ),
|
||||
.rf_ld3 (rf_ld3 ),
|
||||
.rf_tmgc_16 (rf_tmgc_16 ),
|
||||
.rf_tmgc_8 (rf_tmgc_8 ),
|
||||
.rf_tmgc_4 (rf_tmgc_4 ),
|
||||
.rf_tmgc_2 (rf_tmgc_2 ),
|
||||
.rf_tmgc_1 (rf_tmgc_1 ),
|
||||
.rf_rmgc_16 (rf_rmgc_16 ),
|
||||
.rf_rmgc_8 (rf_rmgc_8 ),
|
||||
.rf_rmgc_4 (rf_rmgc_4 ),
|
||||
.rf_rmgc_2 (rf_rmgc_2 ),
|
||||
.rf_rmgc_1 (rf_rmgc_1 ),
|
||||
.rf_enable (rf_enable ),
|
||||
.rf_sc (rf_sc ),
|
||||
.rf_sd (rf_sd ),
|
||||
.rf_endsyn (rf_endsyn ),
|
||||
.rf_sdout (rf_sdout ),
|
||||
.rf_dq_wd (rf_dq_wd ),
|
||||
.rf_sw_rx (rf_sw_rx )
|
||||
);
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
////////////////////////////////// Rx Signals //////////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
wire [11:0] rx_ch1_i, rx_ch1_q;
|
||||
wire [11:0] rx_ch2_i, rx_ch2_q;
|
||||
wire [11:0] rx_ch3_i, rx_ch3_q;
|
||||
wire [11:0] rx_ch4_i, rx_ch4_q;
|
||||
|
||||
wire [11:0] rx_cal_ch1_i, rx_cal_ch1_q;
|
||||
wire [11:0] rx_cal_ch2_i, rx_cal_ch2_q;
|
||||
wire [11:0] rx_cal_ch3_i, rx_cal_ch3_q;
|
||||
wire [11:0] rx_cal_ch4_i, rx_cal_ch4_q;
|
||||
|
||||
ad9361_rx_map_cmos_dual u_ad9361_1_rx_map
|
||||
(
|
||||
.clk_2x_in (ad9361_1_clk_2x ), // input clk_2x_in
|
||||
.clk_in_rst (~ad9361_1_clk_ld ), // input clk_in_rst
|
||||
|
||||
.rx_data_clk (sys_clk ), // input rx_data_clk
|
||||
.rx_data_clk_rst(sys_rst ), // input rx_data_clk_rst
|
||||
|
||||
.rx_fifo_rst (ad9361_rx_fifo_rst ), // input rx_fifo_rst
|
||||
|
||||
.rx_frame (ad9361_1_rx_frame ), // input rx_frame
|
||||
.rx_data (ad9361_1_rx_data ), // input [11:0] rx_data
|
||||
.rx_ch1_i (rx_ch1_i ), // output [11:0] rx_ch1_i
|
||||
.rx_ch1_q (rx_ch1_q ), // output [11:0] rx_ch1_q
|
||||
.rx_ch2_i (rx_ch2_i ), // output [11:0] rx_ch2_i
|
||||
.rx_ch2_q (rx_ch2_q ) // output [11:0] rx_ch2_q
|
||||
);
|
||||
|
||||
ad9361_rx_map_cmos_dual u_ad9361_2_rx_map
|
||||
(
|
||||
.clk_2x_in (ad9361_2_clk_2x ), // input clk_2x_in
|
||||
.clk_in_rst (~ad9361_2_clk_ld ), // input clk_in_rst
|
||||
|
||||
.rx_data_clk (sys_clk ), // input rx_data_clk
|
||||
.rx_data_clk_rst(sys_rst ), // input rx_data_clk_rst
|
||||
|
||||
.rx_fifo_rst (ad9361_rx_fifo_rst ), // input rx_fifo_rst
|
||||
|
||||
.rx_frame (ad9361_2_rx_frame ), // input rx_frame
|
||||
.rx_data (ad9361_2_rx_data ), // input [11:0] rx_data
|
||||
.rx_ch1_i (rx_ch3_i ), // output [11:0] rx_ch1_i
|
||||
.rx_ch1_q (rx_ch3_q ), // output [11:0] rx_ch1_q
|
||||
.rx_ch2_i (rx_ch4_i ), // output [11:0] rx_ch2_i
|
||||
.rx_ch2_q (rx_ch4_q ) // output [11:0] rx_ch2_q
|
||||
);
|
||||
|
||||
ad9361_phase_cal_coarse u_ad9361_phase_cal
|
||||
(
|
||||
// clock & reset
|
||||
.clk (sys_clk ), // input clk
|
||||
.rst (sys_rst ), // input rst
|
||||
// control interface
|
||||
.ad9361_1_cal_start (ad9361_1_cal_start ), // input ad9361_1_cal_start
|
||||
.ad9361_1_cal_done (ad9361_1_cal_done ), // output ad9361_1_cal_done
|
||||
.ad9361_2_cal_start (ad9361_2_cal_start ), // input ad9361_2_cal_start
|
||||
.ad9361_2_cal_done (ad9361_2_cal_done ), // output ad9361_2_cal_done
|
||||
.ad9361_cal_result (ad9361_cal_result ), // output ad9361_cal_result
|
||||
.ad9361_cal_valid (ad9361_cal_valid ), // output ad9361_cal_valid
|
||||
.ad9361_recal (ad9361_recal ), // input ad9361_recal
|
||||
// input data interface
|
||||
.rx_ch1_i (rx_ch1_i ), // input [ADC_DATA_WIDTH-1:0] rx_ch1_i
|
||||
.rx_ch1_q (rx_ch1_q ), // input [ADC_DATA_WIDTH-1:0] rx_ch1_q
|
||||
.rx_ch2_i (rx_ch2_i ), // input [ADC_DATA_WIDTH-1:0] rx_ch2_i
|
||||
.rx_ch2_q (rx_ch2_q ), // input [ADC_DATA_WIDTH-1:0] rx_ch2_q
|
||||
.rx_ch3_i (rx_ch3_i ), // input [ADC_DATA_WIDTH-1:0] rx_ch3_i
|
||||
.rx_ch3_q (rx_ch3_q ), // input [ADC_DATA_WIDTH-1:0] rx_ch3_q
|
||||
.rx_ch4_i (rx_ch4_i ), // input [ADC_DATA_WIDTH-1:0] rx_ch4_i
|
||||
.rx_ch4_q (rx_ch4_q ), // input [ADC_DATA_WIDTH-1:0] rx_ch4_q
|
||||
// output data interface
|
||||
.rx_cal_ch1_i (rx_cal_ch1_i ), // output [ADC_DATA_WIDTH-1:0] rx_cal_ch1_i
|
||||
.rx_cal_ch1_q (rx_cal_ch1_q ), // output [ADC_DATA_WIDTH-1:0] rx_cal_ch1_q
|
||||
.rx_cal_ch2_i (rx_cal_ch2_i ), // output [ADC_DATA_WIDTH-1:0] rx_cal_ch2_i
|
||||
.rx_cal_ch2_q (rx_cal_ch2_q ), // output [ADC_DATA_WIDTH-1:0] rx_cal_ch2_q
|
||||
.rx_cal_ch3_i (rx_cal_ch3_i ), // output [ADC_DATA_WIDTH-1:0] rx_cal_ch3_i
|
||||
.rx_cal_ch3_q (rx_cal_ch3_q ), // output [ADC_DATA_WIDTH-1:0] rx_cal_ch3_q
|
||||
.rx_cal_ch4_i (rx_cal_ch4_i ), // output [ADC_DATA_WIDTH-1:0] rx_cal_ch4_i
|
||||
.rx_cal_ch4_q (rx_cal_ch4_q ) // output [ADC_DATA_WIDTH-1:0] rx_cal_ch4_q
|
||||
);
|
||||
|
||||
// <--------------------------------------------------------------------------->
|
||||
// <----------------------- insert receiver logic below ----------------------->
|
||||
// <--------------------------------------------------------------------------->
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//////////////////////////////// ILAs and VIOs /////////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
vio_clk_ld_rd u_vio_clk_ld_rd
|
||||
(
|
||||
.clk (sys_clk ),
|
||||
.probe_in0 (ad9361_1_clk_ld),
|
||||
.probe_in1 (ad9361_2_clk_ld)
|
||||
);
|
||||
|
||||
vio_rfcontrl u_vio_rfcontrl
|
||||
(
|
||||
.clk (clk_48m ), // input wire clk
|
||||
.probe_out0 (u_ant_rf_ctrl.vio_switch ), // output wire [0 : 0] probe_out0
|
||||
.probe_out1 (u_ant_rf_ctrl.vio_trdirection ), // output wire [0 : 0] probe_out1
|
||||
.probe_out2 (u_ant_rf_ctrl.vio_frequency[15:0] ), // output wire [15 : 0] probe_out2
|
||||
.probe_out3 (u_ant_rf_ctrl.vio_emitMGC[7:0] ), // output wire [7 : 0] probe_out3
|
||||
.probe_out4 (u_ant_rf_ctrl.vio_ch01MGC[3:0] ), // output wire [3 : 0] probe_out4
|
||||
.probe_out5 (u_ant_rf_ctrl.vio_ch02MGC[3:0] ), // output wire [3 : 0] probe_out5
|
||||
.probe_out6 (u_ant_rf_ctrl.vio_ch03MGC[3:0] ), // output wire [3 : 0] probe_out6
|
||||
.probe_out7 (u_ant_rf_ctrl.vio_ch04MGC[3:0] ), // output wire [3 : 0] probe_out7
|
||||
.probe_out8 (u_ant_rf_ctrl.vio_recvMGC[7:0] ), // output wire [7 : 0] probe_out8
|
||||
.probe_out9 (u_ant_rf_ctrl.vio_AntMod[7:0] ), // output wire [7 : 0] probe_out9
|
||||
.probe_out10(u_ant_rf_ctrl.vio_AntOffAxis[15:0] ), // output wire [15 : 0] probe_out10
|
||||
.probe_out11(u_ant_rf_ctrl.vio_AntYaw[15:0] ), // output wire [15 : 0] probe_out11
|
||||
.probe_out12(u_ant_rf_ctrl.vio_PrecessTime[15:0] ) // output wire [15 : 0] probe_out12
|
||||
);
|
||||
|
||||
vio_ant_test u_vio_ant_test
|
||||
(
|
||||
.clk (clk_48m ),
|
||||
.probe_out0 (u_ant_rf_ctrl.vio_mode_ant ),
|
||||
.probe_out1 (u_ant_rf_ctrl.vio_hop_start ),
|
||||
.probe_out2 (u_ant_rf_ctrl.vio_standby ),
|
||||
.probe_out3 (u_ant_rf_ctrl.vio_hoptime[15:0] )
|
||||
);
|
||||
|
||||
ila_rfcontrl u_ila_rfcontrl
|
||||
(
|
||||
.clk (clk_48m ), // input wire clk
|
||||
.probe0 (u_ant_rf_ctrl.SPI_MOSI_F ), // input wire [0:0]
|
||||
.probe1 (u_ant_rf_ctrl.SPI_MISO_F ), // input wire [0:0]
|
||||
.probe2 (u_ant_rf_ctrl.SPI_SYN_F ), // input wire [0:0]
|
||||
.probe3 (u_ant_rf_ctrl.TP_EN_F ), // input wire [0:0]
|
||||
.probe4 (u_ant_rf_ctrl.TR_MGC_F ), // input wire [0:0]
|
||||
.probe5 (u_ant_rf_ctrl.CAL_F ), // input wire [0:0]
|
||||
.probe6 (u_ant_rf_ctrl.PRF ), // input wire [0:0]
|
||||
.probe7 (u_ant_rf_ctrl.rf_standby ), // input wire [0:0]
|
||||
.probe8 (u_ant_rf_ctrl.rf_sw_pll ), // input wire [0:0]
|
||||
.probe9 (u_ant_rf_ctrl.rf_t ), // input wire [0:0]
|
||||
.probe10(u_ant_rf_ctrl.rf_r ), // input wire [0:0]
|
||||
.probe11(u_ant_rf_ctrl.rf_sw_bpf ), // input wire [0:0]
|
||||
.probe12(u_ant_rf_ctrl.rf_sclk1 ), // input wire [0:0]
|
||||
.probe13(u_ant_rf_ctrl.rf_sdio1 ), // input wire [0:0]
|
||||
.probe14(u_ant_rf_ctrl.rf_cs1 ), // input wire [0:0]
|
||||
.probe15(u_ant_rf_ctrl.rf_ld1 ), // input wire [0:0]
|
||||
.probe16(u_ant_rf_ctrl.rf_sclk2 ), // input wire [0:0]
|
||||
.probe17(u_ant_rf_ctrl.rf_sdio2 ), // input wire [0:0]
|
||||
.probe18(u_ant_rf_ctrl.rf_cs2 ), // input wire [0:0]
|
||||
.probe19(u_ant_rf_ctrl.rf_ld2 ), // input wire [0:0]
|
||||
.probe20(u_ant_rf_ctrl.rf_sclk3 ), // input wire [0:0]
|
||||
.probe21(u_ant_rf_ctrl.rf_sdio3 ), // input wire [0:0]
|
||||
.probe22(u_ant_rf_ctrl.rf_cs3 ), // input wire [0:0]
|
||||
.probe23(u_ant_rf_ctrl.rf_ld3 ), // input wire [0:0]
|
||||
.probe24(u_ant_rf_ctrl.rf_tmgc_16 ), // input wire [0:0]
|
||||
.probe25(u_ant_rf_ctrl.rf_tmgc_8 ), // input wire [0:0]
|
||||
.probe26(u_ant_rf_ctrl.rf_tmgc_4 ), // input wire [0:0]
|
||||
.probe27(u_ant_rf_ctrl.rf_tmgc_2 ), // input wire [0:0]
|
||||
.probe28(u_ant_rf_ctrl.rf_tmgc_1 ), // input wire [0:0]
|
||||
.probe29(u_ant_rf_ctrl.rf_rmgc_16 ), // input wire [0:0]
|
||||
.probe30(u_ant_rf_ctrl.rf_rmgc_8 ), // input wire [0:0]
|
||||
.probe31(u_ant_rf_ctrl.rf_rmgc_4 ), // input wire [0:0]
|
||||
.probe32(u_ant_rf_ctrl.rf_rmgc_2 ), // input wire [0:0]
|
||||
.probe33(u_ant_rf_ctrl.rf_rmgc_1 ), // input wire [0:0]
|
||||
.probe34(u_ant_rf_ctrl.rf_enable ), // input wire [0:0]
|
||||
.probe35(u_ant_rf_ctrl.rf_sc ), // input wire [0:0]
|
||||
.probe36(u_ant_rf_ctrl.rf_sd ), // input wire [0:0]
|
||||
.probe37(u_ant_rf_ctrl.rf_endsyn ), // input wire [0:0]
|
||||
.probe38(u_ant_rf_ctrl.rf_sdout ), // input wire [0:0]
|
||||
.probe39(u_ant_rf_ctrl.state_rfdata[1:0] ), // input wire [0:0]
|
||||
.probe40(u_ant_rf_ctrl.RF_temperature[7:0] ), // input wire [0:0]
|
||||
.probe41(u_ant_rf_ctrl.RF_IFlocked[7:0] ), // input wire [0:0]
|
||||
.probe42(u_ant_rf_ctrl.RF_RFAlocked[7:0] ), // input wire [0:0]
|
||||
.probe43(u_ant_rf_ctrl.RF_RFBlocked[7:0] ), // input wire [0:0]
|
||||
.probe44(u_ant_rf_ctrl.RF_ch1mgc[3:0] ), // input wire [0:0]
|
||||
.probe45(u_ant_rf_ctrl.RF_ch2mgc[3:0] ), // input wire [0:0]
|
||||
.probe46(u_ant_rf_ctrl.RF_ch3mgc[3:0] ), // input wire [0:0]
|
||||
.probe47(u_ant_rf_ctrl.RF_ch4mgc[3:0] ), // input wire [0:0]
|
||||
.probe48(u_ant_rf_ctrl.RF_Framecount[31:0] ), // input wire [0:0]
|
||||
.probe49(u_ant_rf_ctrl.RF_RecvWord[95:0] ) // input wire [0:0]
|
||||
);
|
||||
|
||||
ila_AntCtrl u_ila_AntCtrl
|
||||
(
|
||||
.clk (clk_96m ), // input wire clk
|
||||
.probe0 (u_ant_rf_ctrl.ant_clk ), // input wire [0:0] probe0
|
||||
.probe1 (u_ant_rf_ctrl.ant_en ), // input wire [0:0] probe1
|
||||
.probe2 (u_ant_rf_ctrl.ant_data ), // input wire [0:0] probe2
|
||||
.probe3 (u_ant_rf_ctrl.ant_tr ), // input wire [0:0] probe3
|
||||
.probe4 (u_ant_rf_ctrl.ant_dary ), // input wire [0:0] probe4
|
||||
.probe5 (u_ant_rf_ctrl.ant_dout ), // input wire [0:0] probe5
|
||||
.probe6 (u_ant_rf_ctrl.state_antdata[1:0] ), // input wire [0:0] probe5
|
||||
.probe7 (u_ant_rf_ctrl.Ant_Ant_Volt[7:0] ), // input wire [0:0] probe5
|
||||
.probe8 (u_ant_rf_ctrl.Ant_RF_Volt[7:0] ), // input wire [0:0] probe5
|
||||
.probe9 (u_ant_rf_ctrl.Ant_IF_Volt[7:0] ), // input wire [0:0] probe5
|
||||
.probe10(u_ant_rf_ctrl.Ant_state[7:0] ), // input wire [0:0] probe5
|
||||
.probe11(u_ant_rf_ctrl.Ant_Framecount[31:0] ), // input wire [0:0] probe5
|
||||
.probe12(u_ant_rf_ctrl.Ant_RecvWord[95:0] ) // input wire [0:0] probe5
|
||||
);
|
||||
|
||||
vio_rf_rd u_vio_rf_rd (
|
||||
.clk (clk_96m ), // input wire clk
|
||||
.probe_in0 (u_ant_rf_ctrl.RF_temperature[7:0] ), // input wire [7 : 0] probe_in0
|
||||
.probe_in1 (u_ant_rf_ctrl.RF_IFlocked[7:0] ), // input wire [7 : 0] probe_in1
|
||||
.probe_in2 (u_ant_rf_ctrl.RF_RFAlocked[7:0] ), // input wire [7 : 0] probe_in2
|
||||
.probe_in3 (u_ant_rf_ctrl.RF_RFBlocked[7:0] ), // input wire [7 : 0] probe_in3
|
||||
.probe_in4 (u_ant_rf_ctrl.RF_ch1mgc[3:0] ), // input wire [3 : 0] probe_in4
|
||||
.probe_in5 (u_ant_rf_ctrl.RF_ch2mgc[3:0] ), // input wire [3 : 0] probe_in5
|
||||
.probe_in6 (u_ant_rf_ctrl.RF_ch3mgc[3:0] ), // input wire [3 : 0] probe_in6
|
||||
.probe_in7 (u_ant_rf_ctrl.RF_ch4mgc[3:0] ), // input wire [3 : 0] probe_in7
|
||||
.probe_in8 (u_ant_rf_ctrl.RF_Framecount[31:0] ), // input wire [31 : 0] probe_in8
|
||||
.probe_in9 (u_ant_rf_ctrl.RF_RecvWord_last ) // input wire [95 : 0] probe_in9
|
||||
);
|
||||
|
||||
vio_ant_rd u_vio_ant_rd (
|
||||
.clk (clk_96m ), // input wire clk
|
||||
.probe_in0 (u_ant_rf_ctrl.Ant_Ant_Volt[7:0] ), // input wire [7 : 0] probe_in0
|
||||
.probe_in1 (u_ant_rf_ctrl.Ant_RF_Volt[7:0] ), // input wire [7 : 0] probe_in1
|
||||
.probe_in2 (u_ant_rf_ctrl.Ant_IF_Volt[7:0] ), // input wire [7 : 0] probe_in2
|
||||
.probe_in3 (u_ant_rf_ctrl.Ant_state[7:0] ), // input wire [7 : 0] probe_in3
|
||||
.probe_in4 (u_ant_rf_ctrl.Ant_Framecount[31:0] ), // input wire [31 : 0] probe_in4
|
||||
.probe_in5 (u_ant_rf_ctrl.Ant_RecvWord_last ) // input wire [95 : 0] probe_in5
|
||||
);
|
||||
|
||||
ila_2x12x131072 u_ila_tx
|
||||
(
|
||||
.clk (sys_clk ), // input wire clk
|
||||
.probe0 (tx_data_i ), // input wire [11:0] probe0
|
||||
.probe1 (tx_data_q ) // input wire [11:0] probe1
|
||||
);
|
||||
|
||||
ila_8x12x131072 u_ila_rx
|
||||
(
|
||||
.clk (sys_clk ), // input wire clk
|
||||
.probe0 (rx_ch1_i ), // input wire [11:0] probe0
|
||||
.probe1 (rx_ch1_q ), // input wire [11:0] probe1
|
||||
.probe2 (rx_ch2_i ), // input wire [11:0] probe2
|
||||
.probe3 (rx_ch2_q ), // input wire [11:0] probe3
|
||||
.probe4 (rx_ch3_i ), // input wire [11:0] probe4
|
||||
.probe5 (rx_ch3_q ), // input wire [11:0] probe5
|
||||
.probe6 (rx_ch4_i ), // input wire [11:0] probe6
|
||||
.probe7 (rx_ch4_q ) // input wire [11:0] probe7
|
||||
);
|
||||
|
||||
ila_cal u_ila_cal
|
||||
(
|
||||
.clk (sys_clk ), // input wire clk
|
||||
.probe0 (u_ad9361_phase_cal.ad9361_1_cal_start_d2 ), // input wire [0:0] probe0
|
||||
.probe1 (u_ad9361_phase_cal.ad9361_1_cal_done ), // input wire [0:0] probe1
|
||||
.probe2 (u_ad9361_phase_cal.ad9361_2_cal_start_d2 ), // input wire [0:0] probe2
|
||||
.probe3 (u_ad9361_phase_cal.ad9361_2_cal_done ), // input wire [0:0] probe3
|
||||
.probe4 (u_ad9361_phase_cal.ad9361_cal_result ), // input wire [0:0] probe4
|
||||
.probe5 (u_ad9361_phase_cal.ad9361_recal_d2 ), // input wire [0:0] probe5
|
||||
.probe6 (u_ad9361_phase_cal.curr_state ), // input wire [1:0] probe6
|
||||
.probe7 (rx_ch2_i ), // input wire [11:0] probe7
|
||||
.probe8 (rx_ch2_q ), // input wire [11:0] probe8
|
||||
.probe9 (rx_ch4_i ), // input wire [11:0] probe9
|
||||
.probe10(rx_ch4_q ), // input wire [11:0] probe10
|
||||
.probe11(rx_cal_ch2_i ), // input wire [11:0] probe11
|
||||
.probe12(rx_cal_ch2_q ), // input wire [11:0] probe12
|
||||
.probe13(rx_cal_ch4_i ), // input wire [11:0] probe13
|
||||
.probe14(rx_cal_ch4_q ) // input wire [11:0] probe14
|
||||
);
|
||||
|
||||
vio_manual_ctrl u_vio_manual_ctrl
|
||||
(
|
||||
.clk (sys_clk ), // input wire clk
|
||||
.probe_out0 (waveform_sel ), // output wire [1 : 0] probe_out0
|
||||
.probe_out1 (sweep_on ), // output wire [0 : 0] probe_out1
|
||||
.probe_out2 (freq_set ), // output wire [31 : 0] probe_out2
|
||||
.probe_out3 (iq_sel ), // output wire [1 : 0] probe_out3
|
||||
.probe_out4 (bb_rshift ) // output wire [3 : 0] probe_out4
|
||||
);
|
||||
|
||||
endmodule
|
||||
+3
@@ -0,0 +1,3 @@
|
||||
version https://git-lfs.github.com/spec/v1
|
||||
oid sha256:ef2494810258f3a94f005dc09f4146fe015fa6492c805913820ca070e9a39ee6
|
||||
size 982059
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,3 @@
|
||||
version https://git-lfs.github.com/spec/v1
|
||||
oid sha256:2023b48d07f7e7dd794652b40e683170e8c36bfc94175ab71862786d5f151c82
|
||||
size 1719370
|
||||
@@ -0,0 +1,336 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
|
||||
|
||||
<storageModule moduleId="org.eclipse.cdt.core.settings">
|
||||
|
||||
<cconfiguration id="xilinx.gnu.armv7.exe.debug.2088626454">
|
||||
|
||||
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="xilinx.gnu.armv7.exe.debug.2088626454" moduleId="org.eclipse.cdt.core.settings" name="Debug">
|
||||
|
||||
<externalSettings/>
|
||||
|
||||
<extensions>
|
||||
|
||||
<extension id="com.xilinx.sdk.managedbuilder.XELF.arm.a53.x32" point="org.eclipse.cdt.core.BinaryParser"/>
|
||||
|
||||
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
|
||||
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
|
||||
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
|
||||
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
|
||||
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
|
||||
</extensions>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
|
||||
<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" id="xilinx.gnu.armv7.exe.debug.2088626454" name="Debug" parent="xilinx.gnu.armv7.exe.debug" prebuildStep="a9-linaro-pre-build-step">
|
||||
|
||||
<folderInfo id="xilinx.gnu.armv7.exe.debug.2088626454." name="/" resourcePath="">
|
||||
|
||||
<toolChain id="xilinx.gnu.armv7.exe.debug.toolchain.265802415" name="Vitis ARM v7 GNU Toolchain" superClass="xilinx.gnu.armv7.exe.debug.toolchain">
|
||||
|
||||
<targetPlatform binaryParser="com.xilinx.sdk.managedbuilder.XELF.arm.a53.x32" id="xilinx.armv7.target.gnu.base.debug.367473571" isAbstract="false" name="Debug Platform" superClass="xilinx.armv7.target.gnu.base.debug"/>
|
||||
|
||||
<builder buildPath="${workspace_loc:/duifei_cmos_48m}/Debug" enableAutoBuild="true" id="xilinx.gnu.armv7.toolchain.builder.debug.1927472616" managedBuildOn="true" name="GNU make.Debug" superClass="xilinx.gnu.armv7.toolchain.builder.debug"/>
|
||||
|
||||
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<?xml version="1.0" encoding="UTF-8"?>
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version https://git-lfs.github.com/spec/v1
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3240750090
|
||||
+643
@@ -0,0 +1,643 @@
|
||||
proc ps7_pll_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000110 0x003FFFF0 0x000FA220
|
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mask_write 0XF8000100 0x0007F000 0x00028000
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mask_write 0XF8000100 0x00000010 0x00000010
|
||||
mask_write 0XF8000100 0x00000001 0x00000001
|
||||
mask_write 0XF8000100 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000001
|
||||
mask_write 0XF8000100 0x00000010 0x00000000
|
||||
mask_write 0XF8000120 0x1F003F30 0x1F000200
|
||||
mask_write 0XF8000114 0x003FFFF0 0x0012C220
|
||||
mask_write 0XF8000104 0x0007F000 0x00020000
|
||||
mask_write 0XF8000104 0x00000010 0x00000010
|
||||
mask_write 0XF8000104 0x00000001 0x00000001
|
||||
mask_write 0XF8000104 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x000FA240
|
||||
mask_write 0XF8000108 0x0007F000 0x00036000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000004
|
||||
mask_write 0XF8000108 0x00000010 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_clock_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||
mask_write 0XF800014C 0x00003F31 0x00000901
|
||||
mask_write 0XF8000168 0x00003F31 0x00000901
|
||||
mask_write 0XF8000170 0x03F03F30 0x00300600
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01CC000D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_3_0 {} {
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000084
|
||||
mask_write 0XF8006004 0x0007FFFF 0x00001082
|
||||
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
|
||||
mask_write 0XF800600C 0x03FFFFFF 0x02001001
|
||||
mask_write 0XF8006010 0x03FFFFFF 0x00014001
|
||||
mask_write 0XF8006014 0x001FFFFF 0x0004285B
|
||||
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
|
||||
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
|
||||
mask_write 0XF8006020 0x7FDFFFFC 0x270872D0
|
||||
mask_write 0XF8006024 0x0FFFFFC3 0x00000000
|
||||
mask_write 0XF8006028 0x00003FFF 0x00002007
|
||||
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
|
||||
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
|
||||
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
|
||||
mask_write 0XF8006038 0x00000003 0x00000000
|
||||
mask_write 0XF800603C 0x000FFFFF 0x00000666
|
||||
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
|
||||
mask_write 0XF8006044 0x0FFFFFFF 0x0F555555
|
||||
mask_write 0XF8006048 0x0003F03F 0x0003C008
|
||||
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
|
||||
mask_write 0XF8006058 0x00010000 0x00000000
|
||||
mask_write 0XF800605C 0x0000FFFF 0x00005003
|
||||
mask_write 0XF8006060 0x000017FF 0x0000003E
|
||||
mask_write 0XF8006064 0x00021FE0 0x00020000
|
||||
mask_write 0XF8006068 0x03FFFFFF 0x00284141
|
||||
mask_write 0XF800606C 0x0000FFFF 0x00001610
|
||||
mask_write 0XF8006078 0x03FFFFFF 0x00466111
|
||||
mask_write 0XF800607C 0x000FFFFF 0x00032222
|
||||
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
|
||||
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
|
||||
mask_write 0XF80060AC 0x000001FF 0x000001FE
|
||||
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
|
||||
mask_write 0XF80060B4 0x00000200 0x00000200
|
||||
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
|
||||
mask_write 0XF80060C4 0x00000003 0x00000000
|
||||
mask_write 0XF80060C8 0x000000FF 0x00000000
|
||||
mask_write 0XF80060DC 0x00000001 0x00000000
|
||||
mask_write 0XF80060F0 0x0000FFFF 0x00000000
|
||||
mask_write 0XF80060F4 0x0000000F 0x00000008
|
||||
mask_write 0XF8006114 0x000000FF 0x00000000
|
||||
mask_write 0XF8006118 0x7FFFFFCF 0x40000001
|
||||
mask_write 0XF800611C 0x7FFFFFCF 0x40000001
|
||||
mask_write 0XF8006120 0x7FFFFFCF 0x40000000
|
||||
mask_write 0XF8006124 0x7FFFFFCF 0x40000000
|
||||
mask_write 0XF800612C 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006130 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006134 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006138 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006140 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006144 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006148 0x000FFFFF 0x00000035
|
||||
mask_write 0XF800614C 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006154 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006158 0x000FFFFF 0x00000080
|
||||
mask_write 0XF800615C 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006160 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006168 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800616C 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006170 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006174 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800617C 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006180 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006184 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006188 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006190 0x6FFFFEFE 0x00040080
|
||||
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
|
||||
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8006208 0x000703FF 0x000003FF
|
||||
mask_write 0XF800620C 0x000703FF 0x000003FF
|
||||
mask_write 0XF8006210 0x000703FF 0x000003FF
|
||||
mask_write 0XF8006214 0x000703FF 0x000003FF
|
||||
mask_write 0XF8006218 0x000F03FF 0x000003FF
|
||||
mask_write 0XF800621C 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006220 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006224 0x000F03FF 0x000003FF
|
||||
mask_write 0XF80062A8 0x00000FF5 0x00000000
|
||||
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF80062B0 0x003FFFFF 0x00005125
|
||||
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
|
||||
mask_poll 0XF8000B74 0x00002000
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000085
|
||||
mask_poll 0XF8006054 0x00000007
|
||||
}
|
||||
proc ps7_mio_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B40 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B44 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B48 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B4C 0x00000FFF 0x00000800
|
||||
mask_write 0XF8000B50 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B54 0x00000FFF 0x00000800
|
||||
mask_write 0XF8000B58 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
|
||||
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B6C 0x00007FFF 0x00000220
|
||||
mask_write 0XF8000B70 0x00000001 0x00000001
|
||||
mask_write 0XF8000B70 0x00000021 0x00000020
|
||||
mask_write 0XF8000B70 0x07FEFFFF 0x00000823
|
||||
mask_write 0XF8000704 0x00003FFF 0x00001602
|
||||
mask_write 0XF8000708 0x00003FFF 0x00000602
|
||||
mask_write 0XF800070C 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000710 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000714 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000718 0x00003FFF 0x00000602
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_peripherals_init_data_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B48 0x00000180 0x00000180
|
||||
mask_write 0XF8000B4C 0x00000180 0x00000000
|
||||
mask_write 0XF8000B50 0x00000180 0x00000180
|
||||
mask_write 0XF8000B54 0x00000180 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
mask_write 0XE000D000 0x00080000 0x00080000
|
||||
mask_write 0XF8007000 0x20000000 0x00000000
|
||||
}
|
||||
proc ps7_post_config_3_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000900 0x0000000F 0x0000000F
|
||||
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_debug_3_0 {} {
|
||||
mwr -force 0XF8898FB0 0xC5ACCE55
|
||||
mwr -force 0XF8899FB0 0xC5ACCE55
|
||||
mwr -force 0XF8809FB0 0xC5ACCE55
|
||||
}
|
||||
proc ps7_pll_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000110 0x003FFFF0 0x000FA220
|
||||
mask_write 0XF8000100 0x0007F000 0x00028000
|
||||
mask_write 0XF8000100 0x00000010 0x00000010
|
||||
mask_write 0XF8000100 0x00000001 0x00000001
|
||||
mask_write 0XF8000100 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000001
|
||||
mask_write 0XF8000100 0x00000010 0x00000000
|
||||
mask_write 0XF8000120 0x1F003F30 0x1F000200
|
||||
mask_write 0XF8000114 0x003FFFF0 0x0012C220
|
||||
mask_write 0XF8000104 0x0007F000 0x00020000
|
||||
mask_write 0XF8000104 0x00000010 0x00000010
|
||||
mask_write 0XF8000104 0x00000001 0x00000001
|
||||
mask_write 0XF8000104 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x000FA240
|
||||
mask_write 0XF8000108 0x0007F000 0x00036000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000004
|
||||
mask_write 0XF8000108 0x00000010 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_clock_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||
mask_write 0XF800014C 0x00003F31 0x00000901
|
||||
mask_write 0XF8000168 0x00003F31 0x00000901
|
||||
mask_write 0XF8000170 0x03F03F30 0x00300600
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01CC000D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_2_0 {} {
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000084
|
||||
mask_write 0XF8006004 0x1FFFFFFF 0x00081082
|
||||
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
|
||||
mask_write 0XF800600C 0x03FFFFFF 0x02001001
|
||||
mask_write 0XF8006010 0x03FFFFFF 0x00014001
|
||||
mask_write 0XF8006014 0x001FFFFF 0x0004285B
|
||||
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
|
||||
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
|
||||
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
|
||||
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
|
||||
mask_write 0XF8006028 0x00003FFF 0x00002007
|
||||
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
|
||||
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
|
||||
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
|
||||
mask_write 0XF8006038 0x00001FC3 0x00000000
|
||||
mask_write 0XF800603C 0x000FFFFF 0x00000666
|
||||
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
|
||||
mask_write 0XF8006044 0x0FFFFFFF 0x0F555555
|
||||
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
|
||||
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
|
||||
mask_write 0XF8006058 0x0001FFFF 0x00000101
|
||||
mask_write 0XF800605C 0x0000FFFF 0x00005003
|
||||
mask_write 0XF8006060 0x000017FF 0x0000003E
|
||||
mask_write 0XF8006064 0x00021FE0 0x00020000
|
||||
mask_write 0XF8006068 0x03FFFFFF 0x00284141
|
||||
mask_write 0XF800606C 0x0000FFFF 0x00001610
|
||||
mask_write 0XF8006078 0x03FFFFFF 0x00466111
|
||||
mask_write 0XF800607C 0x000FFFFF 0x00032222
|
||||
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
|
||||
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
|
||||
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
|
||||
mask_write 0XF80060AC 0x000001FF 0x000001FE
|
||||
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
|
||||
mask_write 0XF80060B4 0x000007FF 0x00000200
|
||||
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
|
||||
mask_write 0XF80060C4 0x00000003 0x00000000
|
||||
mask_write 0XF80060C8 0x000000FF 0x00000000
|
||||
mask_write 0XF80060DC 0x00000001 0x00000000
|
||||
mask_write 0XF80060F0 0x0000FFFF 0x00000000
|
||||
mask_write 0XF80060F4 0x0000000F 0x00000008
|
||||
mask_write 0XF8006114 0x000000FF 0x00000000
|
||||
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006120 0x7FFFFFFF 0x40000000
|
||||
mask_write 0XF8006124 0x7FFFFFFF 0x40000000
|
||||
mask_write 0XF800612C 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006130 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006134 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006138 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006140 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006144 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006148 0x000FFFFF 0x00000035
|
||||
mask_write 0XF800614C 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006154 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006158 0x000FFFFF 0x00000080
|
||||
mask_write 0XF800615C 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006160 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006168 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800616C 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006170 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006174 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800617C 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006180 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006184 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006188 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
|
||||
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
|
||||
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8006208 0x000F03FF 0x000803FF
|
||||
mask_write 0XF800620C 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006210 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006214 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006218 0x000F03FF 0x000003FF
|
||||
mask_write 0XF800621C 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006220 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006224 0x000F03FF 0x000003FF
|
||||
mask_write 0XF80062A8 0x00000FF7 0x00000000
|
||||
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF80062B0 0x003FFFFF 0x00005125
|
||||
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
|
||||
mask_poll 0XF8000B74 0x00002000
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000085
|
||||
mask_poll 0XF8006054 0x00000007
|
||||
}
|
||||
proc ps7_mio_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B40 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B44 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B48 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B4C 0x00000FFF 0x00000800
|
||||
mask_write 0XF8000B50 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B54 0x00000FFF 0x00000800
|
||||
mask_write 0XF8000B58 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
|
||||
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B6C 0x00007FFF 0x00000220
|
||||
mask_write 0XF8000B70 0x00000021 0x00000021
|
||||
mask_write 0XF8000B70 0x00000021 0x00000020
|
||||
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
|
||||
mask_write 0XF8000704 0x00003FFF 0x00001602
|
||||
mask_write 0XF8000708 0x00003FFF 0x00000602
|
||||
mask_write 0XF800070C 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000710 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000714 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000718 0x00003FFF 0x00000602
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_peripherals_init_data_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B48 0x00000180 0x00000180
|
||||
mask_write 0XF8000B4C 0x00000180 0x00000000
|
||||
mask_write 0XF8000B50 0x00000180 0x00000180
|
||||
mask_write 0XF8000B54 0x00000180 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
mask_write 0XE000D000 0x00080000 0x00080000
|
||||
mask_write 0XF8007000 0x20000000 0x00000000
|
||||
}
|
||||
proc ps7_post_config_2_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000900 0x0000000F 0x0000000F
|
||||
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_debug_2_0 {} {
|
||||
mwr -force 0XF8898FB0 0xC5ACCE55
|
||||
mwr -force 0XF8899FB0 0xC5ACCE55
|
||||
mwr -force 0XF8809FB0 0xC5ACCE55
|
||||
}
|
||||
proc ps7_pll_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000110 0x003FFFF0 0x000FA220
|
||||
mask_write 0XF8000100 0x0007F000 0x00028000
|
||||
mask_write 0XF8000100 0x00000010 0x00000010
|
||||
mask_write 0XF8000100 0x00000001 0x00000001
|
||||
mask_write 0XF8000100 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000001
|
||||
mask_write 0XF8000100 0x00000010 0x00000000
|
||||
mask_write 0XF8000120 0x1F003F30 0x1F000200
|
||||
mask_write 0XF8000114 0x003FFFF0 0x0012C220
|
||||
mask_write 0XF8000104 0x0007F000 0x00020000
|
||||
mask_write 0XF8000104 0x00000010 0x00000010
|
||||
mask_write 0XF8000104 0x00000001 0x00000001
|
||||
mask_write 0XF8000104 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000002
|
||||
mask_write 0XF8000104 0x00000010 0x00000000
|
||||
mask_write 0XF8000124 0xFFF00003 0x0C200003
|
||||
mask_write 0XF8000118 0x003FFFF0 0x000FA240
|
||||
mask_write 0XF8000108 0x0007F000 0x00036000
|
||||
mask_write 0XF8000108 0x00000010 0x00000010
|
||||
mask_write 0XF8000108 0x00000001 0x00000001
|
||||
mask_write 0XF8000108 0x00000001 0x00000000
|
||||
mask_poll 0XF800010C 0x00000004
|
||||
mask_write 0XF8000108 0x00000010 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_clock_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000128 0x03F03F01 0x00700F01
|
||||
mask_write 0XF800014C 0x00003F31 0x00000901
|
||||
mask_write 0XF8000168 0x00003F31 0x00000901
|
||||
mask_write 0XF8000170 0x03F03F30 0x00300600
|
||||
mask_write 0XF80001C4 0x00000001 0x00000001
|
||||
mask_write 0XF800012C 0x01FFCCCD 0x01CC000D
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_ddr_init_data_1_0 {} {
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000084
|
||||
mask_write 0XF8006004 0x1FFFFFFF 0x00081082
|
||||
mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
|
||||
mask_write 0XF800600C 0x03FFFFFF 0x02001001
|
||||
mask_write 0XF8006010 0x03FFFFFF 0x00014001
|
||||
mask_write 0XF8006014 0x001FFFFF 0x0004285B
|
||||
mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3
|
||||
mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5
|
||||
mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
|
||||
mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
|
||||
mask_write 0XF8006028 0x00003FFF 0x00002007
|
||||
mask_write 0XF800602C 0xFFFFFFFF 0x00000008
|
||||
mask_write 0XF8006030 0xFFFFFFFF 0x00040B30
|
||||
mask_write 0XF8006034 0x13FF3FFF 0x000116D4
|
||||
mask_write 0XF8006038 0x00001FC3 0x00000000
|
||||
mask_write 0XF800603C 0x000FFFFF 0x00000666
|
||||
mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000
|
||||
mask_write 0XF8006044 0x0FFFFFFF 0x0F555555
|
||||
mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
|
||||
mask_write 0XF8006050 0xFF0F8FFF 0x77010800
|
||||
mask_write 0XF8006058 0x0001FFFF 0x00000101
|
||||
mask_write 0XF800605C 0x0000FFFF 0x00005003
|
||||
mask_write 0XF8006060 0x000017FF 0x0000003E
|
||||
mask_write 0XF8006064 0x00021FE0 0x00020000
|
||||
mask_write 0XF8006068 0x03FFFFFF 0x00284141
|
||||
mask_write 0XF800606C 0x0000FFFF 0x00001610
|
||||
mask_write 0XF80060A0 0x00FFFFFF 0x00008000
|
||||
mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
|
||||
mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
|
||||
mask_write 0XF80060AC 0x000001FF 0x000001FE
|
||||
mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
|
||||
mask_write 0XF80060B4 0x000007FF 0x00000200
|
||||
mask_write 0XF80060B8 0x01FFFFFF 0x00200066
|
||||
mask_write 0XF80060C4 0x00000003 0x00000000
|
||||
mask_write 0XF80060C8 0x000000FF 0x00000000
|
||||
mask_write 0XF80060DC 0x00000001 0x00000000
|
||||
mask_write 0XF80060F0 0x0000FFFF 0x00000000
|
||||
mask_write 0XF80060F4 0x0000000F 0x00000008
|
||||
mask_write 0XF8006114 0x000000FF 0x00000000
|
||||
mask_write 0XF8006118 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF800611C 0x7FFFFFFF 0x40000001
|
||||
mask_write 0XF8006120 0x7FFFFFFF 0x40000000
|
||||
mask_write 0XF8006124 0x7FFFFFFF 0x40000000
|
||||
mask_write 0XF800612C 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006130 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006134 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006138 0x000FFFFF 0x00029000
|
||||
mask_write 0XF8006140 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006144 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006148 0x000FFFFF 0x00000035
|
||||
mask_write 0XF800614C 0x000FFFFF 0x00000035
|
||||
mask_write 0XF8006154 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006158 0x000FFFFF 0x00000080
|
||||
mask_write 0XF800615C 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006160 0x000FFFFF 0x00000080
|
||||
mask_write 0XF8006168 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800616C 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006170 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF8006174 0x001FFFFF 0x000000F9
|
||||
mask_write 0XF800617C 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006180 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006184 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006188 0x000FFFFF 0x000000C0
|
||||
mask_write 0XF8006190 0xFFFFFFFF 0x10040080
|
||||
mask_write 0XF8006194 0x000FFFFF 0x0001FC82
|
||||
mask_write 0XF8006204 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF8006208 0x000F03FF 0x000803FF
|
||||
mask_write 0XF800620C 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006210 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006214 0x000F03FF 0x000803FF
|
||||
mask_write 0XF8006218 0x000F03FF 0x000003FF
|
||||
mask_write 0XF800621C 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006220 0x000F03FF 0x000003FF
|
||||
mask_write 0XF8006224 0x000F03FF 0x000003FF
|
||||
mask_write 0XF80062A8 0x00000FF7 0x00000000
|
||||
mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
|
||||
mask_write 0XF80062B0 0x003FFFFF 0x00005125
|
||||
mask_write 0XF80062B4 0x0003FFFF 0x000012A8
|
||||
mask_poll 0XF8000B74 0x00002000
|
||||
mask_write 0XF8006000 0x0001FFFF 0x00000085
|
||||
mask_poll 0XF8006054 0x00000007
|
||||
}
|
||||
proc ps7_mio_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B40 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B44 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B48 0x00000FFF 0x00000672
|
||||
mask_write 0XF8000B4C 0x00000FFF 0x00000800
|
||||
mask_write 0XF8000B50 0x00000FFF 0x00000674
|
||||
mask_write 0XF8000B54 0x00000FFF 0x00000800
|
||||
mask_write 0XF8000B58 0x00000FFF 0x00000600
|
||||
mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
|
||||
mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
|
||||
mask_write 0XF8000B6C 0x000073FF 0x00000220
|
||||
mask_write 0XF8000B70 0x00000021 0x00000021
|
||||
mask_write 0XF8000B70 0x00000021 0x00000020
|
||||
mask_write 0XF8000B70 0x07FFFFFF 0x00000823
|
||||
mask_write 0XF8000704 0x00003FFF 0x00001602
|
||||
mask_write 0XF8000708 0x00003FFF 0x00000602
|
||||
mask_write 0XF800070C 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000710 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000714 0x00003FFF 0x00000602
|
||||
mask_write 0XF8000718 0x00003FFF 0x00000602
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_peripherals_init_data_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000B48 0x00000180 0x00000180
|
||||
mask_write 0XF8000B4C 0x00000180 0x00000000
|
||||
mask_write 0XF8000B50 0x00000180 0x00000180
|
||||
mask_write 0XF8000B54 0x00000180 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
mask_write 0XE000D000 0x00080000 0x00080000
|
||||
mask_write 0XF8007000 0x20000000 0x00000000
|
||||
}
|
||||
proc ps7_post_config_1_0 {} {
|
||||
mwr -force 0XF8000008 0x0000DF0D
|
||||
mask_write 0XF8000900 0x0000000F 0x0000000F
|
||||
mask_write 0XF8000240 0xFFFFFFFF 0x00000000
|
||||
mwr -force 0XF8000004 0x0000767B
|
||||
}
|
||||
proc ps7_debug_1_0 {} {
|
||||
mwr -force 0XF8898FB0 0xC5ACCE55
|
||||
mwr -force 0XF8899FB0 0xC5ACCE55
|
||||
mwr -force 0XF8809FB0 0xC5ACCE55
|
||||
}
|
||||
set PCW_SILICON_VER_1_0 "0x0"
|
||||
set PCW_SILICON_VER_2_0 "0x1"
|
||||
set PCW_SILICON_VER_3_0 "0x2"
|
||||
set APU_FREQ 666666666
|
||||
|
||||
|
||||
|
||||
proc mask_poll { addr mask } {
|
||||
set count 1
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval & $mask}]
|
||||
while { $maskedval == 0 } {
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval & $mask}]
|
||||
set count [ expr { $count + 1 } ]
|
||||
if { $count == 100000000 } {
|
||||
puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
|
||||
break
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
proc mask_delay { addr val } {
|
||||
set delay [ get_number_of_cycles_for_delay $val ]
|
||||
perf_reset_and_start_timer
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval < $delay}]
|
||||
while { $maskedval == 1 } {
|
||||
set curval "0x[string range [mrd $addr] end-8 end]"
|
||||
set maskedval [expr {$curval < $delay}]
|
||||
}
|
||||
perf_reset_clock
|
||||
}
|
||||
|
||||
proc ps_version { } {
|
||||
set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
|
||||
set mask_sil_ver "0x[expr {$si_ver >> 28}]"
|
||||
return $mask_sil_ver;
|
||||
}
|
||||
|
||||
proc ps7_post_config {} {
|
||||
set saved_mode [configparams force-mem-accesses]
|
||||
configparams force-mem-accesses 1
|
||||
|
||||
variable PCW_SILICON_VER_1_0
|
||||
variable PCW_SILICON_VER_2_0
|
||||
variable PCW_SILICON_VER_3_0
|
||||
set sil_ver [ps_version]
|
||||
|
||||
if { $sil_ver == $PCW_SILICON_VER_1_0} {
|
||||
ps7_post_config_1_0
|
||||
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
|
||||
ps7_post_config_2_0
|
||||
} else {
|
||||
ps7_post_config_3_0
|
||||
}
|
||||
configparams force-mem-accesses $saved_mode
|
||||
}
|
||||
|
||||
proc ps7_debug {} {
|
||||
variable PCW_SILICON_VER_1_0
|
||||
variable PCW_SILICON_VER_2_0
|
||||
variable PCW_SILICON_VER_3_0
|
||||
set sil_ver [ps_version]
|
||||
|
||||
if { $sil_ver == $PCW_SILICON_VER_1_0} {
|
||||
ps7_debug_1_0
|
||||
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
|
||||
ps7_debug_2_0
|
||||
} else {
|
||||
ps7_debug_3_0
|
||||
}
|
||||
}
|
||||
proc ps7_init {} {
|
||||
variable PCW_SILICON_VER_1_0
|
||||
variable PCW_SILICON_VER_2_0
|
||||
variable PCW_SILICON_VER_3_0
|
||||
set sil_ver [ps_version]
|
||||
if { $sil_ver == $PCW_SILICON_VER_1_0} {
|
||||
ps7_mio_init_data_1_0
|
||||
ps7_pll_init_data_1_0
|
||||
ps7_clock_init_data_1_0
|
||||
ps7_ddr_init_data_1_0
|
||||
ps7_peripherals_init_data_1_0
|
||||
#puts "PCW Silicon Version : 1.0"
|
||||
} elseif { $sil_ver == $PCW_SILICON_VER_2_0 } {
|
||||
ps7_mio_init_data_2_0
|
||||
ps7_pll_init_data_2_0
|
||||
ps7_clock_init_data_2_0
|
||||
ps7_ddr_init_data_2_0
|
||||
ps7_peripherals_init_data_2_0
|
||||
#puts "PCW Silicon Version : 2.0"
|
||||
} else {
|
||||
ps7_mio_init_data_3_0
|
||||
ps7_pll_init_data_3_0
|
||||
ps7_clock_init_data_3_0
|
||||
ps7_ddr_init_data_3_0
|
||||
ps7_peripherals_init_data_3_0
|
||||
#puts "PCW Silicon Version : 3.0"
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
# For delay calculation using global timer
|
||||
|
||||
# start timer
|
||||
proc perf_start_clock { } {
|
||||
|
||||
#writing SCU_GLOBAL_TIMER_CONTROL register
|
||||
|
||||
mask_write 0xF8F00208 0x00000109 0x00000009
|
||||
}
|
||||
|
||||
# stop timer and reset timer count regs
|
||||
proc perf_reset_clock { } {
|
||||
perf_disable_clock
|
||||
mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
|
||||
mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
|
||||
}
|
||||
|
||||
# Compute mask for given delay in miliseconds
|
||||
proc get_number_of_cycles_for_delay { delay } {
|
||||
|
||||
# GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
|
||||
variable APU_FREQ
|
||||
return [ expr ($delay * $APU_FREQ /(2 * 1000))]
|
||||
}
|
||||
|
||||
|
||||
# stop timer
|
||||
proc perf_disable_clock {} {
|
||||
mask_write 0xF8F00208 0xFFFFFFFF 0x00000000
|
||||
}
|
||||
|
||||
proc perf_reset_and_start_timer {} {
|
||||
perf_reset_clock
|
||||
perf_start_clock
|
||||
}
|
||||
|
||||
|
||||
+11
@@ -0,0 +1,11 @@
|
||||
<?xml version="1.0" encoding="ASCII"?>
|
||||
<sdkproject:SdkProject xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:sdkproject="http://www.xilinx.com/sdkproject" name="duifei_cmos_48m" location="/home/josh/Workspace/vivado/vivado_pvt/projects/duifei/duifei_cal_coarse/vitis/duifei_cmos_48m" platform="/home/josh/Workspace/vivado/vivado_pvt/projects/duifei/duifei_cal_coarse/vitis/duifei_platform/export/duifei_platform/duifei_platform.xpfm" platformUID="xilinx:::0.0(custom)" systemProject="duifei_cmos_48m_system" sysConfig="duifei_platform" runtime="C/C++" cpu="standalone_domain" cpuInstance="ps7_cortexa9_0" os="standalone" mssSignature="a06fc5f50fb58e7be39c2e24b733999d">
|
||||
<configuration name="Debug" id="xilinx.gnu.armv7.exe.debug.2088626454">
|
||||
<configBuildOptions xsi:type="sdkproject:SdkOptions"/>
|
||||
<lastBuildOptions xsi:type="sdkproject:SdkOptions"/>
|
||||
</configuration>
|
||||
<configuration name="Release" id="xilinx.gnu.armv7.exe.release.1419668598" dirty="true">
|
||||
<configBuildOptions xsi:type="sdkproject:SdkOptions"/>
|
||||
</configuration>
|
||||
<template appTemplateName="empty_application"/>
|
||||
</sdkproject:SdkProject>
|
||||
@@ -0,0 +1 @@
|
||||
Empty application. Add your own sources.
|
||||
@@ -0,0 +1,2 @@
|
||||
*startfile:
|
||||
crti%O%s crtbegin%O%s
|
||||
+128
@@ -0,0 +1,128 @@
|
||||
/***************************************************************************//**
|
||||
* @file ad9694.c
|
||||
* @brief Implementation of AD9680 Driver.
|
||||
* @author DBogdan (dragos.bogdan@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2014-2016(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
#include <stdlib.h>
|
||||
#include <stdio.h>
|
||||
#include "ad9694.h"
|
||||
#include "../../../include/error.h"
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief ad9694_read
|
||||
*******************************************************************************/
|
||||
int32_t ad9694_read(struct ad9694_dev *dev,
|
||||
uint16_t reg_addr,
|
||||
uint8_t *reg_data)
|
||||
{
|
||||
uint8_t tx_buf[2];
|
||||
uint8_t rx_buf[1];
|
||||
int32_t ret;
|
||||
|
||||
tx_buf[0] = 0x80 | (reg_addr >> 8);
|
||||
tx_buf[1] = reg_addr & 0xFF;
|
||||
|
||||
|
||||
ret = spi_write_and_read_3wire(dev->spi_desc,
|
||||
tx_buf, rx_buf, 2, 1);
|
||||
|
||||
*reg_data = rx_buf[0];
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief ad9694_write
|
||||
*******************************************************************************/
|
||||
int32_t ad9694_write(struct ad9694_dev *dev,
|
||||
uint16_t reg_addr,
|
||||
uint8_t reg_data)
|
||||
{
|
||||
uint8_t buf[3];
|
||||
|
||||
int32_t ret;
|
||||
|
||||
buf[0] = reg_addr >> 8;
|
||||
buf[1] = reg_addr & 0xFF;
|
||||
buf[2] = reg_data;
|
||||
|
||||
ret = spi_write_and_read_3wire(dev->spi_desc,
|
||||
buf, NULL, 3, 0);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief ad9694_init
|
||||
*******************************************************************************/
|
||||
int32_t ad9694_init(struct ad9694_dev **device,
|
||||
const struct ad9694_init_param *init_param)
|
||||
{
|
||||
int ret = SUCCESS;
|
||||
struct ad9694_dev *dev;
|
||||
|
||||
dev = (struct ad9694_dev *)malloc(sizeof(*dev));
|
||||
if (!dev)
|
||||
return FAILURE;
|
||||
|
||||
/* SPI */
|
||||
ret = spi_init(&dev->spi_desc, init_param->spi_init);
|
||||
|
||||
*device = dev;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief Free the resources allocated by ad9694_setup().
|
||||
*
|
||||
* @param dev - The device structure.
|
||||
*
|
||||
* @return SUCCESS in case of success, negative error code otherwise.
|
||||
*******************************************************************************/
|
||||
int32_t ad9694_remove(struct ad9694_dev *dev)
|
||||
{
|
||||
int32_t ret;
|
||||
|
||||
ret = spi_remove(dev->spi_desc);
|
||||
|
||||
free(dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
+231
@@ -0,0 +1,231 @@
|
||||
/***************************************************************************//**
|
||||
* @file ad9694.h
|
||||
* @brief Header file of AD9694 Driver.
|
||||
* @author DBogdan (dragos.bogdan@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2014-2016(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
#ifndef AD9694_H_
|
||||
#define AD9694_H_
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
#include <stdint.h>
|
||||
#include "../../../include/delay.h"
|
||||
#include "../../../include/spi.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/********************** Macros and Constants Definitions **********************/
|
||||
/******************************************************************************/
|
||||
#define AD9694_REG_GLOBAL_MAP_SPI_CONF_A 0x0000
|
||||
#define AD9694_REG_GLOBAL_MAP_SPI_CONF_B 0x0001
|
||||
#define AD9694_REG_CH_MAP_CHIP_CONF 0x0002
|
||||
#define AD9694_REG_PAIR_MAP_CHIP_TYPE 0x0003
|
||||
#define AD9694_REG_PAIR_MAP_CHIP_ID_LSB 0x0004
|
||||
#define AD9694_REG_PAIR_MAP_CHIP_GRADE 0x0006
|
||||
#define AD9694_REG_PAIR_MAP_DEV_INDEX 0x0008
|
||||
#define AD9694_REG_GLOBAL_MAP_PAIR_INDEX 0x0009
|
||||
#define AD9694_REG_PAIR_MAP_SCRATCH_PAD 0x000A
|
||||
#define AD9694_REG_PAIR_MAP_SPI_REVISION 0x000B
|
||||
#define AD9694_REG_PAIR_MAP_VENDOR_ID_LSB 0x000C
|
||||
#define AD9694_REG_PAIR_MAP_VENDOR_ID_MSB 0x000D
|
||||
#define AD9694_REG_CH_MAP_CHIP_PD_PIN 0x003F
|
||||
#define AD9694_REG_PAIR_MAP_CHIP_PIN_CTRL_1 0x0040
|
||||
#define AD9694_REG_PAIR_MAP_CLK_DIV_CTRL 0x0108
|
||||
#define AD9694_REG_CH_MAP_CLK_DIV_PHASE 0x0109
|
||||
#define AD9694_REG_PAIR_MAP_CLK_DIV_SYSREF_CTRL 0x010A
|
||||
#define AD9694_REG_PAIR_MAP_CLK_DELAY_CTRL 0x0110
|
||||
#define AD9694_REG_CH_MAP_CLK_SUPER_FINE_DELAY 0x0111
|
||||
#define AD9694_REG_CH_MAP_CLK_FINE_DELAY 0x0112
|
||||
#define AD9694_REG_CLK_DETN_CTRL 0x011A
|
||||
#define AD9694_REG_PAIR_MAP_CLK_STAT 0x011B
|
||||
#define AD9694_REG_CLK_DCS_CTRL_1 0x011C
|
||||
#define AD9694_REG_CLK_DCS_CTRL_2 0x011E
|
||||
#define AD9694_REG_CLK_DCS_CTRL_3 0x011F
|
||||
#define AD9694_REG_PAIR_MAP_SYSREF_CTRL_1 0x0120
|
||||
#define AD9694_REG_PAIR_MAP_SYSREF_CTRL_2 0x0121
|
||||
#define AD9694_REG_PAIR_MAP_SYSREF_CTRL_4 0x0123
|
||||
#define AD9694_REG_PAIR_MAP_SYSREF_STAT_1 0x0128
|
||||
#define AD9694_REG_PAIR_MAP_SYSREF_STAT_2 0x0129
|
||||
#define AD9694_REG_PAIR_MAP_SYSREF_STAT_3 0x012A
|
||||
#define AD9694_REG_PAIR_MAP_CHIP_SYNC 0x01FF
|
||||
#define AD9694_REG_PAIR_MAP_CHIP_MODE 0x0200
|
||||
#define AD9694_REG_PAIR_MAP_CHIP_DEC_RATIO 0x0201
|
||||
#define AD9694_REG_CH_MAP_CUSTOM_OFFSET 0x0228
|
||||
#define AD9694_REG_CH_MAP_FD_CTRL 0x0245
|
||||
#define AD9694_REG_CH_MAP_FD_UT_LSB 0x0247
|
||||
#define AD9694_REG_CH_MAP_FD_UT_MSB 0x0248
|
||||
#define AD9694_REG_CH_MAP_FD_LT_LSB 0x0249
|
||||
#define AD9694_REG_CH_MAP_FD_LT_MSB 0x024A
|
||||
#define AD9694_REG_CH_MAP_FD_DWELL_TIME_LSB 0x024B
|
||||
#define AD9694_REG_CH_MAP_FD_DWELL_TIME_MSB 0x024C
|
||||
#define AD9694_REG_PAIR_MAP_SIG_MON_SYNC_CTRL 0x026F
|
||||
#define AD9694_REG_CH_MAP_SIG_MON_CTRL 0x0270
|
||||
#define AD9694_REG_CH_MAP_SIG_MON_PERIOD_0 0x0271
|
||||
#define AD9694_REG_CH_MAP_SIG_MON_PERIOD_1 0x0272
|
||||
#define AD9694_REG_CH_MAP_SIG_MON_PERIOD_2 0x0273
|
||||
#define AD9694_REG_CH_MAP_SIG_MON_STAT_CTRL 0x0274
|
||||
#define AD9694_REG_CH_MAP_SIG_MON_STAT_0 0x0275
|
||||
#define AD9694_REG_CH_MAP_SIG_MON_STAT_1 0x0276
|
||||
#define AD9694_REG_CH_MAP_SIG_MON_STAT_2 0x0277
|
||||
#define AD9694_REG_CH_MAP_SIG_MON_STAT_FRAME_CNT 0x0278
|
||||
#define AD9694_REG_CH_MAP_SIG_MON_SERIAL_FRAMER_CTRL 0x0279
|
||||
#define AD9694_REG_SPORT_OVER_JESD204B_INPUT_SEL 0x027A
|
||||
#define AD9694_REG_PAIR_MAP_DDC_SYNC_CTRL 0x0300
|
||||
#define AD9694_REG_PAIR_MAP_DDC_0_CTRL 0x0310
|
||||
#define AD9694_REG_PAIR_MAP_DDC_0_INPUT_SEL 0x0311
|
||||
#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_0 0x0314
|
||||
#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_1 0x0315
|
||||
#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_2 0x0316
|
||||
#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_3 0x0317
|
||||
#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_4 0x0318
|
||||
#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_INC_5 0x031A
|
||||
#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_0 0x031D
|
||||
#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_1 0x031E
|
||||
#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_2 0x031F
|
||||
#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_3 0x0320
|
||||
#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_4 0x0321
|
||||
#define AD9694_REG_PAIR_MAP_DDC_0_PHASE_OFFSET_5 0x0322
|
||||
#define AD9694_REG_PAIR_MAP_DDC_0_TEST_ENABLE 0x0327
|
||||
#define AD9694_REG_PAIR_MAP_DDC_1_CTRL 0x0330
|
||||
#define AD9694_REG_PAIR_MAP_DDC_1_INPUT_SEL 0x0331
|
||||
#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_0 0x0334
|
||||
#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_1 0x0335
|
||||
#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_2 0x0336
|
||||
#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_3 0x0337
|
||||
#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_4 0x0338
|
||||
#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_INC_5 0x033A
|
||||
#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_0 0x033D
|
||||
#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_1 0x033E
|
||||
#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_2 0x033F
|
||||
#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_3 0x0340
|
||||
#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_4 0x0341
|
||||
#define AD9694_REG_PAIR_MAP_DDC_1_PHASE_OFFSET_5 0x0342
|
||||
#define AD9694_REG_PAIR_MAP_DDC_1_TEST_ENABLE 0x0347
|
||||
#define AD9694_REG_CH_MAP_TEST_MODE_CTRL 0x0550
|
||||
#define AD9694_REG_PAIR_MAP_USER_PATTERN_1_LSB 0x0551
|
||||
#define AD9694_REG_PAIR_MAP_USER_PATTERN_1_MSB 0x0552
|
||||
#define AD9694_REG_PAIR_MAP_USER_PATTERN_2_LSB 0x0553
|
||||
#define AD9694_REG_PAIR_MAP_USER_PATTERN_2_MSB 0x0554
|
||||
#define AD9694_REG_PAIR_MAP_USER_PATTERN_3_LSB 0x0555
|
||||
#define AD9694_REG_PAIR_MAP_USER_PATTERN_3_MSB 0x0556
|
||||
#define AD9694_REG_PAIR_MAP_USER_PATTERN_4_LSB 0x0557
|
||||
#define AD9694_REG_PAIR_MAP_USER_PATTERN_4_MSB 0x0558
|
||||
#define AD9694_REG_PAIR_MAP_OUTPUT_CTRL_MODE_0 0x0559
|
||||
#define AD9694_REG_PAIR_MAP_OUTPUT_CTRL_MODE_1 0x055A
|
||||
#define AD9694_REG_PAIR_MAP_OUTPUT_SAMPLE_MODE 0x0561
|
||||
#define AD9694_REG_PAIR_MAP_OUTPUT_CH_SEL 0x0564
|
||||
#define AD9694_REG_JESD204B_MAP_PLL_CTRL 0x056E
|
||||
#define AD9694_REG_JESD204B_MAP_PLL_STAT 0x056F
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_QUICK_CONF 0x0570
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_LINK_CTRL_1 0x0571
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_LINK_CTRL_2 0x0572
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_LINK_CTRL_3 0x0573
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_LINK_CTRL_4 0x0574
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_LMFC_OFFSET 0x0578
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_DID_CONF 0x0580
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_BID_CONF 0x0581
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_LID_0_CONF 0x0583
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_LID_1_CONF 0x0585
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_SCR_L_CONF 0x058B
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_F_CONF 0x058C
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_K_CONF 0x058D
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_M_CONF 0x058E
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_CS_N_CONF 0x058F
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_SUBCLASS_CONF 0x0590
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_S_CONF 0x0591
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_HD_CF_CONF 0x0592
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_CHECKSUM_0_CONF 0x05A0
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_CHECKSUM_1_CONF 0x05A1
|
||||
#define AD9694_REG_SERDOUTX0_SERDOUTX1_LANE_PD 0x05B0
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_LANE_ASSIGN_1 0x05B2
|
||||
#define AD9694_REG_JESD204B_MAP_JTX_LANE_ASSIGN_2 0x05B3
|
||||
#define AD9694_REG_JESD204B_MAP_SERD_ADJUST_0 0x05C0
|
||||
#define AD9694_REG_JESD204B_MAP_SERD_ADJUST_1 0x05C1
|
||||
#define AD9694_REG_JESD204B_SER_PE_SEL_LANE_0 0x05C4
|
||||
#define AD9694_REG_JESD204B_SER_PE_SEL_LANE_1 0x05C6
|
||||
#define AD9694_REG_LARGE_DITHER_CTRL 0x0922
|
||||
#define AD9694_REG_PLL_CAL 0x1222
|
||||
#define AD9694_REG_JESD204B_STARTUP_CIRCUIT_RST 0x1228
|
||||
#define AD9694_REG_PLL_LOSS_OF_LOCK_CTRL 0x1262
|
||||
#define AD9694_REG_DC_OFFSET_CAL_CTRL 0x0701
|
||||
#define AD9694_REG_DC_OFFSET_CAL_CTRL_2 0x073B
|
||||
#define AD9694_REG_PAIR_MAP_VREF_CTRL 0x18A6
|
||||
#define AD9694_REG_EXT_VCM_BUF_CTRL_1 0x18E0
|
||||
#define AD9694_REG_EXT_VCM_BUF_CTRL_2 0x18E1
|
||||
#define AD9694_REG_EXT_VCM_BUF_CTRL_3 0x18E2
|
||||
#define AD9694_REG_EXT_VCM_BUF_CTRL 0x18E3
|
||||
#define AD9694_REG_TEMP_DIODE_EXPORT 0x18E6
|
||||
#define AD9694_REG_CH_MAP_ANALOG_INPUT_CTRL 0x1908
|
||||
#define AD9694_REG_CH_MAP_INPUT_FULLSCALE_RANGE 0x1910
|
||||
#define AD9694_REG_CH_MAP_BUF_CTRL_1 0x1A4C
|
||||
#define AD9694_REG_CH_MAP_BUF_CTRL_2 0x1A4D
|
||||
|
||||
/******************************************************************************/
|
||||
/*************************** Types Declarations *******************************/
|
||||
/******************************************************************************/
|
||||
struct ad9694_dev {
|
||||
/* SPI */
|
||||
spi_desc *spi_desc;
|
||||
};
|
||||
|
||||
struct ad9694_init_param {
|
||||
/* SPI */
|
||||
spi_init_param *spi_init;
|
||||
};
|
||||
|
||||
struct ad9694_config {
|
||||
uint16_t addr;
|
||||
uint8_t value;
|
||||
};
|
||||
|
||||
/******************************************************************************/
|
||||
/************************ Functions Declarations ******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
int32_t ad9694_read(struct ad9694_dev *dev,
|
||||
uint16_t reg_addr,
|
||||
uint8_t *reg_data);
|
||||
|
||||
int32_t ad9694_write(struct ad9694_dev *dev,
|
||||
uint16_t reg_addr,
|
||||
uint8_t reg_data);
|
||||
|
||||
int32_t ad9694_init(struct ad9694_dev **device,
|
||||
const struct ad9694_init_param *init_param);
|
||||
|
||||
int32_t ad9694_remove(struct ad9694_dev *dev);
|
||||
|
||||
#endif
|
||||
+184
@@ -0,0 +1,184 @@
|
||||
/***************************************************************************//**
|
||||
* @file gpio.c
|
||||
* @brief Implementation of the GPIO Interface
|
||||
* @author Antoniu Miclaus (antoniu.miclaus@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2020(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
#include <inttypes.h>
|
||||
#include <stdlib.h>
|
||||
#include "../../include/gpio.h"
|
||||
#include "../../include/error.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/************************ Functions Definitions *******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief Obtain the GPIO decriptor.
|
||||
* @param desc - The GPIO descriptor.
|
||||
* @param param - GPIO Initialization parameters.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t gpio_get(struct gpio_desc **desc,
|
||||
const struct gpio_init_param *param)
|
||||
{
|
||||
if (!param)
|
||||
return FAILURE;
|
||||
|
||||
if ((param->platform_ops->gpio_ops_get(desc, param)))
|
||||
return FAILURE;
|
||||
|
||||
(*desc)->platform_ops = param->platform_ops;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the value of an optional GPIO.
|
||||
* @param desc - The GPIO descriptor.
|
||||
* @param param - GPIO Initialization parameters.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t gpio_get_optional(struct gpio_desc **desc,
|
||||
const struct gpio_init_param *param)
|
||||
{
|
||||
if (!param || (param->number == -1)) {
|
||||
*desc = NULL;
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
if ((param->platform_ops->gpio_ops_get_optional(desc, param)))
|
||||
return FAILURE;
|
||||
|
||||
(*desc)->platform_ops = param->platform_ops;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
/**
|
||||
* @brief Free the resources allocated by gpio_get().
|
||||
* @param desc - The GPIO descriptor.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t gpio_remove(struct gpio_desc *desc)
|
||||
{
|
||||
if (desc)
|
||||
return desc->platform_ops->gpio_ops_remove(desc);
|
||||
else
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the input direction of the specified GPIO.
|
||||
* @param desc - The GPIO descriptor.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t gpio_direction_input(struct gpio_desc *desc)
|
||||
{
|
||||
if (desc)
|
||||
return desc->platform_ops->gpio_ops_direction_input(desc);
|
||||
else
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the output direction of the specified GPIO.
|
||||
* @param desc - The GPIO descriptor.
|
||||
* @param value - The value.
|
||||
* Example: GPIO_HIGH
|
||||
* GPIO_LOW
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t gpio_direction_output(struct gpio_desc *desc,
|
||||
uint8_t value)
|
||||
{
|
||||
if (desc)
|
||||
return desc->platform_ops->
|
||||
gpio_ops_direction_output(desc, value);
|
||||
else
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the direction of the specified GPIO.
|
||||
* @param desc - The GPIO descriptor.
|
||||
* @param direction - The direction.
|
||||
* Example: GPIO_OUT
|
||||
* GPIO_IN
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t gpio_get_direction(struct gpio_desc *desc,
|
||||
uint8_t *direction)
|
||||
{
|
||||
if (desc)
|
||||
return desc->platform_ops->
|
||||
gpio_ops_get_direction(desc, direction);
|
||||
else
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the value of the specified GPIO.
|
||||
* @param desc - The GPIO descriptor.
|
||||
* @param value - The value.
|
||||
* Example: GPIO_HIGH
|
||||
* GPIO_LOW
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t gpio_set_value(struct gpio_desc *desc,
|
||||
uint8_t value)
|
||||
{
|
||||
if (desc)
|
||||
return desc->platform_ops->gpio_ops_set_value(desc, value);
|
||||
else
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the value of the specified GPIO.
|
||||
* @param desc - The GPIO descriptor.
|
||||
* @param value - The value.
|
||||
* Example: GPIO_HIGH
|
||||
* GPIO_LOW
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t gpio_get_value(struct gpio_desc *desc,
|
||||
uint8_t *value)
|
||||
{
|
||||
if (desc)
|
||||
return desc->platform_ops->gpio_ops_get_value(desc, value);
|
||||
else
|
||||
return SUCCESS;
|
||||
}
|
||||
+153
@@ -0,0 +1,153 @@
|
||||
/***************************************************************************//**
|
||||
* @file irq.c
|
||||
* @brief Implementation of the IRQ Interface
|
||||
* @author Andrei Porumb (andrei.porumb@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2021(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
#include <inttypes.h>
|
||||
#include <stdlib.h>
|
||||
#include "../../include/irq.h"
|
||||
#include "../../include/error.h"
|
||||
|
||||
/**
|
||||
* @brief Initialize the IRQ interrupts.
|
||||
* @param desc - The IRQ descriptor.
|
||||
* @param param - The structure that contains the IRQ parameters.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t irq_ctrl_init(struct irq_ctrl_desc **desc,
|
||||
const struct irq_init_param *param)
|
||||
{
|
||||
if (!param)
|
||||
return FAILURE;
|
||||
|
||||
if ((param->platform_ops->init(desc, param)))
|
||||
return FAILURE;
|
||||
|
||||
(*desc)->platform_ops = param->platform_ops;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Free the resources allocated by irq_ctrl_init().
|
||||
* @param desc - The SPI descriptor.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t irq_ctrl_remove(struct irq_ctrl_desc *desc)
|
||||
{
|
||||
return desc->platform_ops->remove(desc);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Register a callback to handle the irq events.
|
||||
* @param desc - The IRQ controller descriptor.
|
||||
* @param irq_id - Interrupt identifier.
|
||||
* @param callback_desc - Callback descriptor
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t irq_register_callback(struct irq_ctrl_desc *desc, uint32_t irq_id,
|
||||
struct callback_desc *callback_desc)
|
||||
{
|
||||
return desc->platform_ops->register_callback(desc, irq_id, callback_desc);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Unregisters a generic IRQ handling function.
|
||||
* @param desc - The IRQ controller descriptor.
|
||||
* @param irq_id - Interrupt identifier.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t irq_unregister(struct irq_ctrl_desc *desc, uint32_t irq_id)
|
||||
{
|
||||
return desc->platform_ops->unregister(desc, irq_id);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable global interrupts.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t irq_global_enable(struct irq_ctrl_desc *desc)
|
||||
{
|
||||
return desc->platform_ops->global_enable(desc);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable global interrupts.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t irq_global_disable(struct irq_ctrl_desc *desc)
|
||||
{
|
||||
return desc->platform_ops->global_disable(desc);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set interrupt trigger level.
|
||||
* @param desc - The IRQ controller descriptor.
|
||||
* @param irq_id - Interrupt identifier.
|
||||
* @param trig - New trigger level for the interrupt.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t irq_trigger_level_set(struct irq_ctrl_desc *desc, uint32_t irq_id,
|
||||
enum irq_trig_level trig)
|
||||
{
|
||||
if(desc->platform_ops->trigger_level_set)
|
||||
return desc->platform_ops->trigger_level_set(desc, irq_id, trig);
|
||||
else
|
||||
return ENOSYS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable specific interrupt.
|
||||
* @param desc - The IRQ controller descriptor.
|
||||
* @param irq_id - Interrupt identifier.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t irq_enable(struct irq_ctrl_desc *desc, uint32_t irq_id)
|
||||
{
|
||||
return desc->platform_ops->enable(desc, irq_id);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable specific interrupt.
|
||||
* @param desc - The IRQ controller descriptor.
|
||||
* @param irq_id - Interrupt identifier.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t irq_disable(struct irq_ctrl_desc *desc, uint32_t irq_id)
|
||||
{
|
||||
return desc->platform_ops->disable(desc, irq_id);
|
||||
}
|
||||
+144
@@ -0,0 +1,144 @@
|
||||
/***************************************************************************//**
|
||||
* @file spi.c
|
||||
* @brief Implementation of the SPI Interface
|
||||
* @author Antoniu Miclaus (antoniu.miclaus@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2020(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
#include <inttypes.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include "../../include/spi.h"
|
||||
#include "../../include/error.h"
|
||||
|
||||
/**
|
||||
* @brief Initialize the SPI communication peripheral.
|
||||
* @param desc - The SPI descriptor.
|
||||
* @param param - The structure that contains the SPI parameters.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t spi_init(struct spi_desc **desc,
|
||||
const struct spi_init_param *param)
|
||||
{
|
||||
if (!param)
|
||||
return FAILURE;
|
||||
|
||||
if ((param->platform_ops->init(desc, param)))
|
||||
return FAILURE;
|
||||
|
||||
(*desc)->platform_ops = param->platform_ops;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Free the resources allocated by spi_init().
|
||||
* @param desc - The SPI descriptor.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t spi_remove(struct spi_desc *desc)
|
||||
{
|
||||
return desc->platform_ops->remove(desc);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write and read data to/from SPI.
|
||||
* @param desc - The SPI descriptor.
|
||||
* @param data - The buffer with the transmitted/received data.
|
||||
* @param bytes_number - Number of bytes to write/read.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t spi_write_and_read(struct spi_desc *desc,
|
||||
uint8_t *data,
|
||||
uint16_t bytes_number)
|
||||
{
|
||||
return desc->platform_ops->write_and_read(desc, data, bytes_number);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write and read data to/from SPI in 3 wire mode.
|
||||
* @param desc - The SPI descriptor.
|
||||
* @param write_data - The buffer with the transmitted data.
|
||||
* @param read_data - The buffer with the received data.
|
||||
* @param write_bytes_number - Number of bytes to write.
|
||||
* @param read_bytes_number - Number of bytes to read.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t spi_write_and_read_3wire(struct spi_desc *desc,
|
||||
uint8_t *write_data,
|
||||
uint8_t *read_data,
|
||||
uint16_t write_bytes_number,
|
||||
uint16_t read_bytes_number)
|
||||
{
|
||||
int ret;
|
||||
if(desc->platform_ops->write_and_read_3wire != NULL){
|
||||
return desc->platform_ops->write_and_read_3wire(desc, write_data, read_data,
|
||||
write_bytes_number, read_bytes_number);
|
||||
}
|
||||
else{
|
||||
return FAILURE;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Iterate over head list and send all spi messages
|
||||
* @param desc - The SPI descriptor.
|
||||
* @param msgs - Array of messages.
|
||||
* @param len - Number of messages in the array.
|
||||
* @return SUCCESS in case of success, negativ error code otherwise.
|
||||
*/
|
||||
int32_t spi_transfer(struct spi_desc *desc, struct spi_msg *msgs, uint32_t len)
|
||||
{
|
||||
int32_t ret;
|
||||
uint32_t i;
|
||||
|
||||
if (!desc || !desc->platform_ops)
|
||||
return -EINVAL;
|
||||
|
||||
if (desc->platform_ops->transfer)
|
||||
return desc->platform_ops->transfer(desc, msgs, len);
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
if (msgs[i].rx_buff != msgs[i].tx_buff || !msgs[i].tx_buff)
|
||||
return -EINVAL;
|
||||
ret = spi_write_and_read(desc, msgs[i].rx_buff,
|
||||
msgs[i].bytes_number);
|
||||
if (IS_ERR_VALUE(ret))
|
||||
return ret;
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
+328
@@ -0,0 +1,328 @@
|
||||
/***************************************************************************//**
|
||||
* @file axi_dmac.c
|
||||
* @brief Driver for the Analog Devices AXI-DMAC core.
|
||||
* @author DBogdan (dragos.bogdan@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2018(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
#include <stdlib.h>
|
||||
#include <stdio.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include "../../../include/axi_io.h"
|
||||
#include "../../../include/error.h"
|
||||
#include "../axi_dmac/axi_dmac.h"
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief dma_isr
|
||||
*******************************************************************************/
|
||||
void axi_dmac_default_isr(void *instance)
|
||||
{
|
||||
struct axi_dmac *dmac = (struct axi_dmac *)instance;
|
||||
uint32_t remaining_size, burst_size;
|
||||
uint32_t reg_val;
|
||||
|
||||
/* Get interrupt sources and clear interrupts. */
|
||||
axi_dmac_read(dmac, AXI_DMAC_REG_IRQ_PENDING, ®_val);
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_PENDING, reg_val);
|
||||
|
||||
if ((reg_val & AXI_DMAC_IRQ_SOT) && (dmac->big_transfer.size != 0)) {
|
||||
remaining_size = dmac->big_transfer.size -
|
||||
dmac->big_transfer.size_done;
|
||||
burst_size = (remaining_size <= dmac->transfer_max_size) ?
|
||||
remaining_size : dmac->transfer_max_size;
|
||||
|
||||
dmac->big_transfer.size_done += burst_size;
|
||||
dmac->big_transfer.address += burst_size;
|
||||
switch (dmac->direction) {
|
||||
case DMA_DEV_TO_MEM:
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS,
|
||||
dmac->big_transfer.address);
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_DEST_STRIDE, 0x0);
|
||||
break;
|
||||
case DMA_MEM_TO_DEV:
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS,
|
||||
dmac->big_transfer.address);
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_SRC_STRIDE, 0x0);
|
||||
break;
|
||||
default:
|
||||
return; // Other directions are not supported yet
|
||||
}
|
||||
/* The current transfer was started and a new one is queued. */
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH,
|
||||
burst_size);
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0);
|
||||
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1);
|
||||
}
|
||||
if (reg_val & AXI_DMAC_IRQ_EOT) {
|
||||
dmac->big_transfer.transfer_done = true;
|
||||
dmac->big_transfer.address = 0;
|
||||
dmac->big_transfer.size = 0;
|
||||
dmac->big_transfer.size_done = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief axi_dmac_read
|
||||
*******************************************************************************/
|
||||
int32_t axi_dmac_read(struct axi_dmac *dmac,
|
||||
uint32_t reg_addr,
|
||||
uint32_t *reg_data)
|
||||
{
|
||||
axi_io_read(dmac->base, reg_addr, reg_data);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief axi_dmac_write
|
||||
*******************************************************************************/
|
||||
int32_t axi_dmac_write(struct axi_dmac *dmac,
|
||||
uint32_t reg_addr,
|
||||
uint32_t reg_data)
|
||||
{
|
||||
axi_io_write(dmac->base, reg_addr, reg_data);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief axi_dmac_transfer_nonblock
|
||||
*******************************************************************************/
|
||||
int32_t axi_dmac_transfer_nonblocking(struct axi_dmac *dmac,
|
||||
uint32_t address, uint32_t size)
|
||||
{
|
||||
uint32_t reg_val;
|
||||
|
||||
if (size == 0)
|
||||
return SUCCESS; /* nothing to do */
|
||||
|
||||
axi_dmac_read(dmac, AXI_DMAC_REG_CTRL, ®_val);
|
||||
if (!(reg_val & AXI_DMAC_CTRL_ENABLE)) {
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, 0x0);
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, AXI_DMAC_CTRL_ENABLE);
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_MASK, 0x0);
|
||||
}
|
||||
|
||||
axi_dmac_read(dmac, AXI_DMAC_REG_START_TRANSFER, ®_val);
|
||||
if (!(reg_val & 1)) {
|
||||
switch (dmac->direction) {
|
||||
case DMA_DEV_TO_MEM:
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS, address);
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_DEST_STRIDE, 0x0);
|
||||
break;
|
||||
case DMA_MEM_TO_DEV:
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS, address);
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_SRC_STRIDE, 0x0);
|
||||
break;
|
||||
default:
|
||||
return FAILURE; // Other directions are not supported yet
|
||||
}
|
||||
if ((size - 1) > dmac->transfer_max_size) {
|
||||
dmac->big_transfer.address = address;
|
||||
dmac->big_transfer.size = size - 1;
|
||||
dmac->big_transfer.size_done = dmac->transfer_max_size;
|
||||
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH,
|
||||
dmac->transfer_max_size);
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0);
|
||||
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, dmac->flags);
|
||||
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1);
|
||||
} else {
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH,
|
||||
size - 1);
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0);
|
||||
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, dmac->flags);
|
||||
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1);
|
||||
}
|
||||
} else {
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief axi_dmac_is_transfer_ready
|
||||
*******************************************************************************/
|
||||
int32_t axi_dmac_is_transfer_ready(struct axi_dmac *dmac, bool *rdy)
|
||||
{
|
||||
*rdy = dmac->big_transfer.transfer_done;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief axi_dmac_transfer
|
||||
*******************************************************************************/
|
||||
int32_t axi_dmac_transfer(struct axi_dmac *dmac,
|
||||
uint32_t address, uint32_t size)
|
||||
{
|
||||
uint32_t transfer_id;
|
||||
uint32_t reg_val;
|
||||
uint32_t timeout = 0;
|
||||
|
||||
if (size == 0)
|
||||
return SUCCESS; /* nothing to do */
|
||||
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, 0x0);
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_CTRL, AXI_DMAC_CTRL_ENABLE);
|
||||
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_MASK, 0x0);
|
||||
|
||||
axi_dmac_read(dmac, AXI_DMAC_REG_TRANSFER_ID, &transfer_id);
|
||||
axi_dmac_read(dmac, AXI_DMAC_REG_IRQ_PENDING, ®_val);
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_PENDING, reg_val);
|
||||
|
||||
switch (dmac->direction) {
|
||||
case DMA_DEV_TO_MEM:
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_DEST_ADDRESS, address);
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_DEST_STRIDE, 0x0);
|
||||
break;
|
||||
case DMA_MEM_TO_DEV:
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_SRC_ADDRESS, address);
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_SRC_STRIDE, 0x0);
|
||||
break;
|
||||
default:
|
||||
return FAILURE; // Other directions are not supported yet
|
||||
}
|
||||
|
||||
if ((size - 1) > dmac->transfer_max_size) {
|
||||
dmac->big_transfer.address = address;
|
||||
dmac->big_transfer.size = size - 1;
|
||||
dmac->big_transfer.size_done = dmac->transfer_max_size;
|
||||
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH,
|
||||
dmac->transfer_max_size);
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0);
|
||||
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, dmac->flags);
|
||||
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1);
|
||||
|
||||
while(!dmac->big_transfer.transfer_done) {
|
||||
timeout++;
|
||||
if (timeout == UINT32_MAX)
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
dmac->big_transfer.address = 0;
|
||||
dmac->big_transfer.size = 0;
|
||||
dmac->big_transfer.size_done = 0;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, size - 1);
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_Y_LENGTH, 0x0);
|
||||
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_FLAGS, dmac->flags);
|
||||
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_START_TRANSFER, 0x1);
|
||||
|
||||
if (dmac->flags & DMA_CYCLIC)
|
||||
return SUCCESS;
|
||||
|
||||
/* Wait until the new transfer is queued. */
|
||||
do {
|
||||
axi_dmac_read(dmac, AXI_DMAC_REG_START_TRANSFER, ®_val);
|
||||
} while(reg_val == 1);
|
||||
|
||||
/* Wait until the current transfer is completed. */
|
||||
do {
|
||||
axi_dmac_read(dmac, AXI_DMAC_REG_IRQ_PENDING, ®_val);
|
||||
if (reg_val == (AXI_DMAC_IRQ_SOT | AXI_DMAC_IRQ_EOT))
|
||||
break;
|
||||
} while(!dmac->big_transfer.transfer_done);
|
||||
if (reg_val != (AXI_DMAC_IRQ_SOT | AXI_DMAC_IRQ_EOT))
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_IRQ_PENDING, reg_val);
|
||||
|
||||
/* Wait until the transfer with the ID transfer_id is completed. */
|
||||
do {
|
||||
axi_dmac_read(dmac, AXI_DMAC_REG_TRANSFER_DONE, ®_val);
|
||||
} while((reg_val & (1u << transfer_id)) != (1u << transfer_id));
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief axi_dmac_init
|
||||
*******************************************************************************/
|
||||
int32_t axi_dmac_init(struct axi_dmac **dmac_core,
|
||||
const struct axi_dmac_init *init)
|
||||
{
|
||||
struct axi_dmac *dmac;
|
||||
|
||||
dmac = (struct axi_dmac *)malloc(sizeof(*dmac));
|
||||
if (!dmac)
|
||||
return FAILURE;
|
||||
|
||||
dmac->name = init->name;
|
||||
dmac->base = init->base;
|
||||
dmac->direction = init->direction;
|
||||
dmac->flags = init->flags;
|
||||
dmac->transfer_max_size = -1;
|
||||
dmac->big_transfer.address = 0;
|
||||
dmac->big_transfer.size = 0;
|
||||
dmac->big_transfer.size_done = 0;
|
||||
|
||||
axi_dmac_write(dmac, AXI_DMAC_REG_X_LENGTH, dmac->transfer_max_size);
|
||||
axi_dmac_read(dmac, AXI_DMAC_REG_X_LENGTH, &dmac->transfer_max_size);
|
||||
|
||||
*dmac_core = dmac;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief axi_dmac_remove
|
||||
*******************************************************************************/
|
||||
int32_t axi_dmac_remove(struct axi_dmac *dmac)
|
||||
{
|
||||
if(!dmac)
|
||||
return FAILURE;
|
||||
|
||||
free(dmac);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
+124
@@ -0,0 +1,124 @@
|
||||
/***************************************************************************//**
|
||||
* @file axi_dmac.h
|
||||
* @brief Driver for the Analog Devices AXI-DMAC core.
|
||||
* @author DBogdan (dragos.bogdan@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2018(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
#ifndef AXI_DMAC_H_
|
||||
#define AXI_DMAC_H_
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
#include <stdint.h>
|
||||
#include "../../../include/util.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/********************** Macros and Constants Definitions **********************/
|
||||
/******************************************************************************/
|
||||
#define AXI_DMAC_REG_IRQ_MASK 0x80
|
||||
#define AXI_DMAC_REG_IRQ_PENDING 0x84
|
||||
#define AXI_DMAC_IRQ_SOT BIT(0)
|
||||
#define AXI_DMAC_IRQ_EOT BIT(1)
|
||||
|
||||
#define AXI_DMAC_REG_CTRL 0x400
|
||||
#define AXI_DMAC_CTRL_ENABLE BIT(0)
|
||||
#define AXI_DMAC_CTRL_PAUSE BIT(1)
|
||||
|
||||
#define AXI_DMAC_REG_TRANSFER_ID 0x404
|
||||
#define AXI_DMAC_REG_START_TRANSFER 0x408
|
||||
#define AXI_DMAC_REG_FLAGS 0x40c
|
||||
#define AXI_DMAC_REG_DEST_ADDRESS 0x410
|
||||
#define AXI_DMAC_REG_SRC_ADDRESS 0x414
|
||||
#define AXI_DMAC_REG_X_LENGTH 0x418
|
||||
#define AXI_DMAC_REG_Y_LENGTH 0x41c
|
||||
#define AXI_DMAC_REG_DEST_STRIDE 0x420
|
||||
#define AXI_DMAC_REG_SRC_STRIDE 0x424
|
||||
#define AXI_DMAC_REG_TRANSFER_DONE 0x428
|
||||
|
||||
/******************************************************************************/
|
||||
/*************************** Types Declarations *******************************/
|
||||
/******************************************************************************/
|
||||
enum dma_direction {
|
||||
DMA_DEV_TO_MEM,
|
||||
DMA_MEM_TO_DEV
|
||||
};
|
||||
|
||||
enum dma_flags {
|
||||
DMA_CYCLIC = 1,
|
||||
DMA_LAST = 2
|
||||
};
|
||||
|
||||
struct axi_dma_transfer {
|
||||
uint32_t size;
|
||||
uint32_t address;
|
||||
uint32_t size_done;
|
||||
volatile bool transfer_done;
|
||||
};
|
||||
|
||||
struct axi_dmac {
|
||||
const char *name;
|
||||
uint32_t base;
|
||||
enum dma_direction direction;
|
||||
uint32_t flags;
|
||||
uint32_t transfer_max_size;
|
||||
volatile struct axi_dma_transfer big_transfer;
|
||||
};
|
||||
|
||||
struct axi_dmac_init {
|
||||
const char *name;
|
||||
uint32_t base;
|
||||
enum dma_direction direction;
|
||||
uint32_t flags;
|
||||
};
|
||||
|
||||
/******************************************************************************/
|
||||
/************************ Functions Declarations ******************************/
|
||||
/******************************************************************************/
|
||||
void axi_dmac_default_isr(void *instance);
|
||||
int32_t axi_dmac_read(struct axi_dmac *dmac, uint32_t reg_addr,
|
||||
uint32_t *reg_data);
|
||||
int32_t axi_dmac_write(struct axi_dmac *dmac, uint32_t reg_addr,
|
||||
uint32_t reg_data);
|
||||
int32_t axi_dmac_transfer_nonblocking(struct axi_dmac *dmac,
|
||||
uint32_t address, uint32_t size);
|
||||
int32_t axi_dmac_is_transfer_ready(struct axi_dmac *dmac, bool *rdy);
|
||||
int32_t axi_dmac_transfer(struct axi_dmac *dmac,
|
||||
uint32_t address, uint32_t size);
|
||||
int32_t axi_dmac_init(struct axi_dmac **adc_core,
|
||||
const struct axi_dmac_init *init);
|
||||
int32_t axi_dmac_remove(struct axi_dmac *dmac);
|
||||
|
||||
#endif
|
||||
+978
@@ -0,0 +1,978 @@
|
||||
/*******************************************************************************
|
||||
* @file spi_engine.c
|
||||
* @brief Core implementation of the SPI Engine Driver.
|
||||
* @author Sergiu Cuciurean (sergiu.cuciurean@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2019(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/* In debug mode the printf function used in displaying the messages is causing
|
||||
significant delays */
|
||||
//#define DEBUG_LEVEL 2
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <sleep.h>
|
||||
#include <inttypes.h>
|
||||
|
||||
#include "spi_engine.h"
|
||||
#include "../axi_dmac/axi_dmac.h"
|
||||
#include "../../../include/axi_io.h"
|
||||
#include "../../../include/error.h"
|
||||
|
||||
/**
|
||||
* @brief Spi engine platform specific SPI platform ops structure
|
||||
*/
|
||||
const struct spi_platform_ops spi_eng_platform_ops = {
|
||||
.init = &spi_engine_init,
|
||||
.write_and_read = &spi_engine_spi_write_and_read,
|
||||
.write_and_read_3wire = &spi_engine_spi_write_and_read_3wire,
|
||||
.remove = &spi_engine_remove
|
||||
};
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Static variables *******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief Static variable used to sync transfers
|
||||
*
|
||||
*/
|
||||
static uint8_t _sync_id = 0x01;
|
||||
|
||||
/******************************************************************************/
|
||||
/************************** Functions Implementation **************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief Write SPI Engine's axi registers
|
||||
*
|
||||
* @param desc Decriptor containing SPI Engine's parameters
|
||||
* @param reg_addr The address of the SPI Engine's axi register where the data
|
||||
* will be written
|
||||
* @param reg_data Data that will be written
|
||||
* @return int32_t This function allways returns SUCCESS
|
||||
*/
|
||||
int32_t spi_engine_write(struct spi_engine_desc *desc,
|
||||
uint32_t reg_addr,
|
||||
uint32_t reg_data)
|
||||
{
|
||||
axi_io_write(desc->spi_engine_baseaddr, reg_addr, reg_data);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read SPI Engine's axi registers
|
||||
*
|
||||
* @param desc Decriptor containing SPI Engine's parameters
|
||||
* @param reg_addr The address of the SPI Engine's axi register from where the
|
||||
* data where the data will be read
|
||||
* @param reg_data Pointer where the read that will be stored
|
||||
* @return int32_t This function allways returns SUCCESS
|
||||
*/
|
||||
int32_t spi_engine_read(struct spi_engine_desc *desc,
|
||||
uint32_t reg_addr,
|
||||
uint32_t *reg_data)
|
||||
{
|
||||
axi_io_read(desc->spi_engine_baseaddr, reg_addr, reg_data);
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set width of the transferred word over SPI
|
||||
*
|
||||
* @param desc Decriptor containing SPI interface parameters
|
||||
* @param data_width The desired data width
|
||||
* The supported values are:
|
||||
* - 8
|
||||
* - 16
|
||||
* - 24
|
||||
* - 32
|
||||
*/
|
||||
int32_t spi_engine_set_transfer_width(struct spi_desc *desc,
|
||||
uint8_t data_width)
|
||||
{
|
||||
struct spi_engine_desc *desc_extra;
|
||||
|
||||
desc_extra = desc->extra;
|
||||
|
||||
if (data_width > desc_extra->max_data_width)
|
||||
desc_extra->data_width = desc_extra->max_data_width;
|
||||
else
|
||||
desc_extra->data_width = data_width;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set SPI engine clock frequency
|
||||
*
|
||||
* @param desc Decriptor containing SPI Engine's parameters
|
||||
* @param speed_hz SPI engine transfer speed
|
||||
*/
|
||||
void spi_engine_set_speed(struct spi_desc *desc,
|
||||
uint32_t speed_hz)
|
||||
{
|
||||
struct spi_engine_desc *desc_extra;
|
||||
|
||||
desc_extra = desc->extra;
|
||||
|
||||
desc_extra->clk_div = desc_extra->ref_clk_hz /
|
||||
(2 * speed_hz) - 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the number of words transferred in a single transaction
|
||||
*
|
||||
* @param desc Decriptor containing SPI Engine's parameters
|
||||
* @param bytes_number The number of bytes to be converted
|
||||
* @return uint8_t A number of words in which bytes_number can be grouped
|
||||
*/
|
||||
static uint8_t spi_get_words_number(struct spi_engine_desc *desc,
|
||||
uint8_t bytes_number)
|
||||
{
|
||||
uint8_t xfer_word_len;
|
||||
uint8_t words_number;
|
||||
|
||||
xfer_word_len = desc->data_width / 8;
|
||||
words_number = bytes_number / xfer_word_len;
|
||||
|
||||
if ((bytes_number % xfer_word_len) != 0)
|
||||
words_number++;
|
||||
|
||||
return words_number;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the word length in bytes
|
||||
*
|
||||
* @param desc Decriptor containing SPI Engine's parameters
|
||||
* @return uint8_t Number of bytes that fit in one word
|
||||
*/
|
||||
static uint8_t spi_get_word_length(struct spi_engine_desc *desc)
|
||||
{
|
||||
uint8_t word_length;
|
||||
|
||||
word_length = desc->data_width / 8;
|
||||
|
||||
return word_length;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Compute the prescaler used to set the sleep period.
|
||||
*
|
||||
* @param desc Decriptor containing SPI interface parameters
|
||||
* @param sleep_time_ns The amount of time where the transfer hangs
|
||||
* @param sleep_div Clock prescaler
|
||||
* @return int32_t This function allways returns SUCCESS
|
||||
*/
|
||||
static int32_t spi_get_sleep_div(struct spi_desc *desc,
|
||||
uint32_t sleep_time_ns,
|
||||
uint32_t *sleep_div)
|
||||
{
|
||||
struct spi_engine_desc *eng_desc;
|
||||
|
||||
eng_desc = desc->extra;
|
||||
|
||||
/*
|
||||
* Engine Wiki:
|
||||
*
|
||||
* The frequency of the SCLK signal is derived from the
|
||||
* module clock frequency using the following formula:
|
||||
* f_sclk = f_clk / ((div + 1) * 2)
|
||||
*/
|
||||
|
||||
*sleep_div = (desc->max_speed_hz / 1000000 * sleep_time_ns / 1000) /
|
||||
((eng_desc->clk_div + 1) * 2) - 1;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Create a new commands queue used in a spi transfer
|
||||
*
|
||||
* @param fifo Command buffer, usually used in fifo mode
|
||||
* @param cmd Command with witch the buffer will be initiated
|
||||
* @return int32_t Failure if the memory allocation failed
|
||||
*/
|
||||
static int32_t spi_engine_queue_new_cmd(struct spi_engine_cmd_queue **fifo,
|
||||
uint32_t cmd)
|
||||
{
|
||||
struct spi_engine_cmd_queue *local_fifo;
|
||||
|
||||
local_fifo = (spi_engine_cmd_queue*)malloc(sizeof(*local_fifo));
|
||||
|
||||
if(!local_fifo)
|
||||
return FAILURE;
|
||||
|
||||
local_fifo->cmd = cmd;
|
||||
local_fifo->next = NULL;
|
||||
*fifo = local_fifo;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Add a command at the end of an existing queue
|
||||
*
|
||||
* @param fifo Command buffer, usually used in fifo mode
|
||||
* @param cmd Command to be added
|
||||
*/
|
||||
static void spi_engine_queue_add_cmd(struct spi_engine_cmd_queue **fifo,
|
||||
uint32_t cmd)
|
||||
{
|
||||
struct spi_engine_cmd_queue *to_add = NULL;
|
||||
struct spi_engine_cmd_queue *local_fifo;
|
||||
|
||||
local_fifo = *fifo;
|
||||
while (local_fifo->next != NULL) {
|
||||
// Get the last element
|
||||
local_fifo = local_fifo->next;
|
||||
}
|
||||
|
||||
// Create a new element
|
||||
spi_engine_queue_new_cmd(&to_add, cmd);
|
||||
// Add as the next element
|
||||
local_fifo->next = to_add;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Add a command at the beginning of an existing queue
|
||||
*
|
||||
* @param fifo Command buffer, usually used in fifo mode
|
||||
* @param cmd Command to be added
|
||||
*/
|
||||
static void spi_engine_queue_append_cmd(struct spi_engine_cmd_queue **fifo,
|
||||
uint32_t cmd)
|
||||
{
|
||||
struct spi_engine_cmd_queue *to_add = NULL;
|
||||
|
||||
// Create a new element
|
||||
spi_engine_queue_new_cmd(&to_add, cmd);
|
||||
// Interchange the addresses
|
||||
to_add->next = *fifo;
|
||||
*fifo = to_add;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get the command from the beginning of the queue
|
||||
*
|
||||
* @param fifo Command buffer, usually used in fifo mode
|
||||
* @param cmd Value of the command that was extracted
|
||||
* @return int32_t Return FAILURE if the queue is empty
|
||||
*/
|
||||
static int32_t spi_engine_queue_get_cmd(struct spi_engine_cmd_queue **fifo,
|
||||
uint32_t *cmd)
|
||||
{
|
||||
struct spi_engine_cmd_queue *local_fifo;
|
||||
|
||||
if (!*fifo)
|
||||
return FAILURE;
|
||||
|
||||
local_fifo = *fifo;
|
||||
*cmd = local_fifo->cmd;
|
||||
if ((*fifo)->next) {
|
||||
*fifo = local_fifo->next;
|
||||
free(local_fifo);
|
||||
} else {
|
||||
free(*fifo);
|
||||
*fifo = NULL;
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Free the memory allocated by a queue
|
||||
*
|
||||
* @param fifo The queue that needs it's memory freed
|
||||
* @return int32_t This function allways return SUCCESS
|
||||
*/
|
||||
static int32_t spi_engine_queue_free(struct spi_engine_cmd_queue **fifo)
|
||||
{
|
||||
if(*fifo && (*fifo)->next)
|
||||
spi_engine_queue_free(&(*fifo)->next);
|
||||
if((*fifo) != NULL) {
|
||||
free(*fifo);
|
||||
*fifo = NULL;
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write the SPI engine's command fifo
|
||||
*
|
||||
* @param desc Decriptor containing SPI Engine's parameters
|
||||
* @param cmd The command that will be written
|
||||
* @return int32_t Returns FAILURE if the the axi transfer failed
|
||||
*/
|
||||
static int32_t spi_engine_write_cmd_reg(struct spi_engine_desc *desc,
|
||||
uint32_t cmd)
|
||||
{
|
||||
int32_t ret;
|
||||
|
||||
/* Check if offload is enabled */
|
||||
if(desc->offload_config & (OFFLOAD_TX_EN | OFFLOAD_RX_EN)) {
|
||||
ret = spi_engine_write(desc,
|
||||
SPI_ENGINE_REG_OFFLOAD_CMD_MEM(0),
|
||||
cmd);
|
||||
|
||||
} else {
|
||||
ret = spi_engine_write(desc,
|
||||
SPI_ENGINE_REG_CMD_FIFO,
|
||||
cmd);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write a transfer command to the SPI engine's command fifo
|
||||
*
|
||||
* @param desc Decriptor containing SPI Engine's parameters
|
||||
* @param read_write Read/Write operation flag
|
||||
* @param bytes_number Number of bytes to transfer
|
||||
* @return int32_t This function allways returns SUCCESS
|
||||
*/
|
||||
static int32_t spi_engine_transfer(struct spi_engine_desc *desc,
|
||||
uint8_t read_write,
|
||||
uint8_t bytes_number)
|
||||
{
|
||||
uint8_t words_number;
|
||||
|
||||
words_number = spi_get_words_number(desc, bytes_number);
|
||||
|
||||
desc->offload_tx_len += words_number;
|
||||
|
||||
/*
|
||||
* Engine Wiki:
|
||||
*
|
||||
* https://wiki.analog.com/resources/fpga/peripherals/spi_engine
|
||||
*
|
||||
* The words number is zero based
|
||||
*/
|
||||
|
||||
spi_engine_write_cmd_reg(desc,
|
||||
SPI_ENGINE_CMD_TRANSFER(read_write,
|
||||
words_number - 1));
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Change the state of the chip select port
|
||||
*
|
||||
* @param desc Decriptor containing SPI interface parameters
|
||||
* @param assert Chip select state.
|
||||
* The supported values are :
|
||||
* -true (HIGH)
|
||||
* -false (LOW)
|
||||
*/
|
||||
static void spi_engine_set_cs(struct spi_desc *desc,
|
||||
bool assert)
|
||||
{
|
||||
uint8_t mask;
|
||||
struct spi_engine_desc *eng_desc;
|
||||
|
||||
eng_desc = desc->extra;
|
||||
|
||||
mask = 0xFF;
|
||||
/* Switch the state only of the selected chip select */
|
||||
if (!assert)
|
||||
mask ^= BIT(desc->chip_select);
|
||||
|
||||
spi_engine_write_cmd_reg(eng_desc,
|
||||
SPI_ENGINE_CMD_ASSERT(eng_desc->cs_delay,
|
||||
mask));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Add a delay between the engine commands
|
||||
*
|
||||
* @param desc Decriptor containing SPI interface parameters
|
||||
* @param sleep_time_ns Number of nanoseconds to sleep between commands
|
||||
*/
|
||||
static void spi_gen_sleep_ns(struct spi_desc *desc,
|
||||
uint32_t sleep_time_ns)
|
||||
{
|
||||
uint32_t sleep_div;
|
||||
struct spi_engine_desc *eng_desc;
|
||||
|
||||
eng_desc = desc->extra;
|
||||
|
||||
spi_get_sleep_div(desc, sleep_time_ns, &sleep_div);
|
||||
|
||||
spi_engine_write_cmd_reg(eng_desc, SPI_ENGINE_CMD_SLEEP(sleep_div));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Spi engine command interpreter
|
||||
*
|
||||
* @param desc Decriptor containing SPI interface parameters
|
||||
* @param cmd Command to send to the engine
|
||||
* @return int32_t - SUCCESS if the command is transferred
|
||||
* - FAILURE if the command format is invalid
|
||||
*/
|
||||
static int32_t spi_engine_write_cmd(struct spi_desc *desc,
|
||||
uint32_t cmd)
|
||||
{
|
||||
uint8_t engine_command;
|
||||
uint8_t parameter;
|
||||
uint8_t modifier;
|
||||
struct spi_engine_desc *desc_extra;
|
||||
|
||||
desc_extra = desc->extra;
|
||||
|
||||
engine_command = (cmd >> 12) & 0x0F;
|
||||
modifier = (cmd >> 8) & 0x0F;
|
||||
parameter = cmd & 0xFF;
|
||||
|
||||
switch(engine_command) {
|
||||
case SPI_ENGINE_INST_TRANSFER:
|
||||
spi_engine_transfer(desc_extra, modifier, parameter);
|
||||
break;
|
||||
|
||||
case SPI_ENGINE_INST_ASSERT:
|
||||
if(parameter == 0xFF) {
|
||||
/* Set the CS HIGH */
|
||||
spi_engine_set_cs(desc, true);
|
||||
} else if(parameter == 0x00) {
|
||||
/* Set the CS LOW */
|
||||
spi_engine_set_cs(desc, false);
|
||||
}
|
||||
break;
|
||||
|
||||
/* The SYNC and SLEEP commands got the same value but different
|
||||
modifier */
|
||||
case SPI_ENGINE_INST_SYNC_SLEEP:
|
||||
/* SYNC instruction */
|
||||
if(modifier == 0x00) {
|
||||
spi_engine_write_cmd_reg(desc_extra, cmd);
|
||||
} else if(modifier == 0x01) {
|
||||
spi_gen_sleep_ns(desc, parameter);
|
||||
}
|
||||
break;
|
||||
case SPI_ENGINE_INST_CONFIG:
|
||||
spi_engine_write_cmd_reg(desc_extra, cmd);
|
||||
|
||||
break;
|
||||
|
||||
default:
|
||||
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Prepare the command queue before sending it to the engine
|
||||
*
|
||||
* @param desc Decriptor containing SPI interface parameters
|
||||
* @param msg Structure used to store the transfer messages
|
||||
* @return int32_t This function allways returns SUCCESS
|
||||
*/
|
||||
static int32_t spi_engine_compile_message(struct spi_desc *desc,
|
||||
struct spi_engine_msg *msg)
|
||||
{
|
||||
struct spi_engine_desc *desc_extra;
|
||||
|
||||
desc_extra = desc->extra;
|
||||
|
||||
/* Configure the prescaler */
|
||||
spi_engine_queue_append_cmd(&msg->cmds,
|
||||
SPI_ENGINE_CMD_CONFIG(
|
||||
SPI_ENGINE_CMD_REG_CLK_DIV,
|
||||
desc_extra->clk_div));
|
||||
|
||||
/* Set the data transfer length */
|
||||
spi_engine_queue_append_cmd(&msg->cmds,
|
||||
SPI_ENGINE_CMD_CONFIG(
|
||||
SPI_ENGINE_CMD_DATA_TRANSFER_LEN,
|
||||
desc_extra->data_width));
|
||||
/*
|
||||
* Configure the spi mode :
|
||||
* - 3 wire
|
||||
* - CPOL
|
||||
* - CPHA
|
||||
*/
|
||||
spi_engine_queue_append_cmd(&msg->cmds,
|
||||
SPI_ENGINE_CMD_CONFIG(
|
||||
SPI_ENGINE_CMD_REG_CONFIG,
|
||||
desc->mode));
|
||||
|
||||
/* Add a sync command to signal that the transfer has finished */
|
||||
spi_engine_queue_add_cmd(&msg->cmds, SPI_ENGINE_CMD_SYNC(_sync_id));
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initiate a spi transfer (Blocking)
|
||||
*
|
||||
* @param desc Decriptor containing SPI interface parameters
|
||||
* @param msg Structure used to store the transfer messages
|
||||
* @return int32_t - SUCCESS if the transfer finished
|
||||
* - FAILURE if the memory allocation failed
|
||||
*/
|
||||
static int32_t spi_engine_transfer_message(struct spi_desc *desc,
|
||||
struct spi_engine_msg *msg)
|
||||
{
|
||||
uint32_t i;
|
||||
uint32_t data;
|
||||
uint32_t sync_id;
|
||||
bool offload_en;
|
||||
struct spi_engine_desc *desc_extra;
|
||||
|
||||
desc_extra = desc->extra;
|
||||
|
||||
spi_engine_compile_message(desc, msg);
|
||||
|
||||
offload_en = (desc_extra->offload_config & OFFLOAD_TX_EN) |
|
||||
(desc_extra->offload_config & OFFLOAD_RX_EN);
|
||||
|
||||
/* Write the command fifo buffer */
|
||||
while(msg->cmds != NULL) {
|
||||
spi_engine_queue_get_cmd(&msg->cmds, &data);
|
||||
spi_engine_write_cmd(desc, data);
|
||||
}
|
||||
|
||||
/* Write a number of tx_length WORDS on the SDO line */
|
||||
if(offload_en) {
|
||||
for(i = 0; i < desc_extra->offload_tx_len; i++)
|
||||
spi_engine_write(desc_extra,
|
||||
SPI_ENGINE_REG_OFFLOAD_SDO_MEM(0),
|
||||
msg->tx_buf[i]);
|
||||
|
||||
} else {
|
||||
if(msg->tx_buf != NULL){
|
||||
for(i = 0; i < msg->tx_length; i++)
|
||||
spi_engine_write(desc_extra,
|
||||
SPI_ENGINE_REG_SDO_DATA_FIFO,
|
||||
msg->tx_buf[i]);
|
||||
}
|
||||
do {
|
||||
spi_engine_read(desc_extra,
|
||||
SPI_ENGINE_REG_SYNC_ID,
|
||||
&sync_id);
|
||||
}
|
||||
/* Wait for the end sync signal */
|
||||
while(sync_id != _sync_id);
|
||||
_sync_id++;
|
||||
|
||||
/* Read a number of rx_length WORDS from the SDI line and store
|
||||
them */
|
||||
for(i = 0; i < msg->rx_length; i++) {
|
||||
spi_engine_read(desc_extra,
|
||||
SPI_ENGINE_REG_SDI_DATA_FIFO,
|
||||
&data);
|
||||
/* Store the rx data if rx buffer valid, flush sdi_fifo if
|
||||
rx buffer is invalid.*/
|
||||
if(msg->rx_buf != NULL){
|
||||
msg->rx_buf[i] = data;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the spi engine
|
||||
*
|
||||
* @param desc Decriptor containing SPI interface parameters
|
||||
* @param param Structure containing the spi init parameters
|
||||
* @return int32_t - SUCCESS if the transfer finished
|
||||
* - FAILURE if the memory allocation failed
|
||||
*/
|
||||
int32_t spi_engine_init(struct spi_desc **desc,
|
||||
const struct spi_init_param *param)
|
||||
{
|
||||
uint32_t data_width = 0;
|
||||
uint32_t spi_engine_version = 0;
|
||||
struct spi_engine_desc *eng_desc;
|
||||
struct spi_engine_init_param *spi_engine_init;
|
||||
|
||||
if (!param) {
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
*desc = malloc(sizeof(**desc));
|
||||
if(! *desc) {
|
||||
free(*desc);
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
eng_desc = (struct spi_engine_desc*)malloc(sizeof(*eng_desc));
|
||||
|
||||
if (!eng_desc)
|
||||
return FAILURE;
|
||||
|
||||
spi_engine_init = param->extra;
|
||||
|
||||
(*desc)->max_speed_hz = param->max_speed_hz;
|
||||
(*desc)->chip_select = param->chip_select;
|
||||
(*desc)->mode = param->mode;
|
||||
(*desc)->extra = eng_desc;
|
||||
|
||||
eng_desc->offload_config = OFFLOAD_DISABLED;
|
||||
eng_desc->spi_engine_baseaddr = spi_engine_init->spi_engine_baseaddr;
|
||||
eng_desc->type = spi_engine_init->type;
|
||||
eng_desc->cs_delay = spi_engine_init->cs_delay;
|
||||
eng_desc->ref_clk_hz = spi_engine_init->ref_clk_hz;
|
||||
eng_desc->clk_div = eng_desc->ref_clk_hz /
|
||||
(2 * param->max_speed_hz) - 1;
|
||||
|
||||
/* Perform a reset */
|
||||
spi_engine_write(eng_desc, SPI_ENGINE_REG_RESET, 0x01);
|
||||
usleep(1000);
|
||||
spi_engine_write(eng_desc, SPI_ENGINE_REG_RESET, 0x00);
|
||||
|
||||
/* Get current data width */
|
||||
spi_engine_read(eng_desc, SPI_ENGINE_REG_DATA_WIDTH, &data_width);
|
||||
eng_desc->max_data_width = data_width;
|
||||
|
||||
spi_engine_set_transfer_width(*desc, spi_engine_init->data_width);
|
||||
|
||||
/* Get spi engine version */
|
||||
spi_engine_read(eng_desc, SPI_ENGINE_REG_VERSION, &spi_engine_version);
|
||||
|
||||
printf("Spi engine v%"PRIu32".%"PRIu32".%"PRIu32" successfully initialized.\n",
|
||||
(spi_engine_version >> 16),
|
||||
((spi_engine_version >> 8) & 0xFF),
|
||||
(spi_engine_version & 0xFF));
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write and read on the spi interface in 4-wire mode (full-duplex)
|
||||
*
|
||||
* @param desc Decriptor containing SPI interface parameters
|
||||
* @param data Pointer to data buffer
|
||||
* @param bytes_number Number of bytes to transfer
|
||||
* @return int32_t - SUCCESS if the transfer finished
|
||||
* - FAILURE if the memory allocation or transfer failed
|
||||
*/
|
||||
int32_t spi_engine_spi_write_and_read(struct spi_desc *desc,
|
||||
uint8_t *data,
|
||||
uint16_t bytes_number)
|
||||
{
|
||||
uint8_t word_len;
|
||||
uint8_t words_number;
|
||||
int32_t ret;
|
||||
struct spi_engine_msg msg;
|
||||
struct spi_engine_desc *desc_extra;
|
||||
|
||||
desc_extra = desc->extra;
|
||||
|
||||
/* If we want to access SPI interface and SPI engine offload module was
|
||||
* activated, we need to disable it
|
||||
* This is set in spi_engine_offload_init() */
|
||||
desc_extra->offload_config = OFFLOAD_DISABLED;
|
||||
/* This is set in spi_engine_offload_transfer() */
|
||||
spi_engine_write(desc_extra, SPI_ENGINE_REG_OFFLOAD_CTRL(0), 0);
|
||||
|
||||
words_number = spi_get_words_number(desc_extra, bytes_number);
|
||||
|
||||
msg.cmds = (spi_engine_cmd_queue*)malloc(sizeof(*msg.cmds));
|
||||
if (!msg.cmds)
|
||||
return FAILURE;
|
||||
|
||||
msg.tx_buf =(uint32_t*)calloc(words_number, sizeof(msg.tx_buf[0]));
|
||||
msg.rx_buf =(uint32_t*)calloc(words_number, sizeof(msg.rx_buf[0]));
|
||||
msg.tx_length = words_number;
|
||||
msg.rx_length = words_number;
|
||||
|
||||
/* Get the length of transferred word */
|
||||
word_len = spi_get_word_length(desc_extra);
|
||||
|
||||
/* Make sure the CS is HIGH before starting a transaction */
|
||||
msg.cmds->next = NULL;
|
||||
msg.cmds->cmd = CS_HIGH;
|
||||
// Assert select.
|
||||
spi_engine_queue_add_cmd(&msg.cmds, CS_LOW);
|
||||
// add read/write command
|
||||
spi_engine_queue_add_cmd(&msg.cmds, WRITE_READ(bytes_number));
|
||||
// Disable select.
|
||||
spi_engine_queue_add_cmd(&msg.cmds, CS_HIGH);
|
||||
|
||||
/* Pack the bytes into engine WORDS */
|
||||
for (int i = 0; i < bytes_number; i++)
|
||||
msg.tx_buf[i / word_len] |= data[i] << (desc_extra->data_width-
|
||||
(i % word_len + 1) * 8);
|
||||
|
||||
ret = spi_engine_transfer_message(desc, &msg);
|
||||
|
||||
for (int i = 0; i < bytes_number; i++)
|
||||
data[i] = msg.rx_buf[(i) / word_len] >>
|
||||
(desc_extra->data_width -
|
||||
((i) % word_len + 1) * 8);
|
||||
|
||||
spi_engine_queue_free(&msg.cmds);
|
||||
free(msg.tx_buf);
|
||||
free(msg.rx_buf);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write and read on the spi interface in 3-wire mode (half-duplex)
|
||||
*
|
||||
* @param desc Decriptor containing SPI interface parameters
|
||||
* @param data Pointer to data buffer
|
||||
* @param bytes_number Number of bytes to transfer
|
||||
* @return int32_t - SUCCESS if the transfer finished
|
||||
* - FAILURE if the memory allocation or transfer failed
|
||||
*/
|
||||
int32_t spi_engine_spi_write_and_read_3wire(struct spi_desc *desc,
|
||||
uint8_t *write_data,
|
||||
uint8_t *read_data,
|
||||
uint16_t write_bytes_number,
|
||||
uint16_t read_bytes_number)
|
||||
{
|
||||
uint8_t word_len;
|
||||
uint8_t wr_words_number;
|
||||
uint8_t rd_words_number;
|
||||
int32_t ret;
|
||||
struct spi_engine_msg msg;
|
||||
struct spi_engine_desc *desc_extra;
|
||||
|
||||
desc_extra = desc->extra;
|
||||
|
||||
/* If we want to access SPI interface and SPI engine offload module was
|
||||
* activated, we need to disable it
|
||||
* This is set in spi_engine_offload_init() */
|
||||
desc_extra->offload_config = OFFLOAD_DISABLED;
|
||||
/* This is set in spi_engine_offload_transfer() */
|
||||
spi_engine_write(desc_extra, SPI_ENGINE_REG_OFFLOAD_CTRL(0), 0);
|
||||
|
||||
wr_words_number = spi_get_words_number(desc_extra, write_bytes_number);
|
||||
rd_words_number = spi_get_words_number(desc_extra, read_bytes_number);
|
||||
|
||||
msg.cmds = (spi_engine_cmd_queue*)malloc(sizeof(*msg.cmds));
|
||||
if (!msg.cmds)
|
||||
return FAILURE;
|
||||
|
||||
msg.tx_buf =(wr_words_number>0)?(uint32_t*)calloc(wr_words_number, sizeof(msg.tx_buf[0])):NULL;
|
||||
msg.rx_buf =(rd_words_number>0)?(uint32_t*)calloc(rd_words_number, sizeof(msg.rx_buf[0])):NULL;
|
||||
msg.tx_length = wr_words_number;
|
||||
msg.rx_length = rd_words_number;
|
||||
|
||||
/* Get the length of transferred word */
|
||||
word_len = spi_get_word_length(desc_extra);
|
||||
|
||||
/* Make sure the CS is HIGH before starting a transaction */
|
||||
msg.cmds->next = NULL;
|
||||
msg.cmds->cmd = CS_HIGH;
|
||||
|
||||
// Assert select.
|
||||
spi_engine_queue_add_cmd(&msg.cmds, CS_LOW);
|
||||
|
||||
// add read/write command
|
||||
if(write_bytes_number > 0)
|
||||
spi_engine_queue_add_cmd(&msg.cmds, WRITE(write_bytes_number));
|
||||
if(read_bytes_number > 0)
|
||||
spi_engine_queue_add_cmd(&msg.cmds, READ(read_bytes_number));
|
||||
|
||||
// Disable select.
|
||||
spi_engine_queue_add_cmd(&msg.cmds, CS_HIGH);
|
||||
|
||||
/* Pack the bytes into engine WORDS */
|
||||
for (int i = 0; i < write_bytes_number; i++)
|
||||
msg.tx_buf[i / word_len] |= write_data[i] << (desc_extra->data_width-
|
||||
(i % word_len + 1) * 8);
|
||||
|
||||
ret = spi_engine_transfer_message(desc, &msg);
|
||||
|
||||
for (int i = 0; i < read_bytes_number; i++)
|
||||
read_data[i] = msg.rx_buf[(i) / word_len] >>
|
||||
(desc_extra->data_width -
|
||||
((i) % word_len + 1) * 8);
|
||||
|
||||
spi_engine_queue_free(&msg.cmds);
|
||||
free(msg.tx_buf);
|
||||
free(msg.rx_buf);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the SPI engine's offload module
|
||||
*
|
||||
* @param desc Decriptor containing SPI interface parameters
|
||||
* @param param Structure containing the offload init parameters
|
||||
* @return int32_t This function allways returns SUCCESS
|
||||
*/
|
||||
int32_t spi_engine_offload_init(struct spi_desc *desc,
|
||||
const struct spi_engine_offload_init_param *param)
|
||||
{
|
||||
struct spi_engine_desc *eng_desc;
|
||||
struct axi_dmac_init dmac_init;
|
||||
uint32_t dma_flags;
|
||||
|
||||
eng_desc = desc->extra;
|
||||
|
||||
eng_desc->offload_config = param->offload_config;
|
||||
|
||||
if(!(param->dma_flags))
|
||||
dma_flags = DMA_CYCLIC;
|
||||
else
|
||||
dma_flags = *(param->dma_flags);
|
||||
|
||||
if(param->offload_config & OFFLOAD_TX_EN) {
|
||||
dmac_init.name = "DAC DMAC";
|
||||
dmac_init.base = param->tx_dma_baseaddr;
|
||||
dmac_init.direction = DMA_MEM_TO_DEV;
|
||||
dmac_init.flags = dma_flags;
|
||||
axi_dmac_init(&eng_desc->offload_tx_dma, &dmac_init);
|
||||
if(!eng_desc->offload_tx_dma)
|
||||
return FAILURE;
|
||||
}
|
||||
if(param->offload_config & OFFLOAD_RX_EN) {
|
||||
dmac_init.name = "ADC DMAC";
|
||||
dmac_init.base = param->rx_dma_baseaddr;
|
||||
dmac_init.direction = DMA_DEV_TO_MEM;
|
||||
dmac_init.flags = dma_flags;
|
||||
axi_dmac_init(&eng_desc->offload_rx_dma, &dmac_init);
|
||||
if(!eng_desc->offload_rx_dma)
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initiate a SPI transfer in offload mode
|
||||
*
|
||||
* @param desc Decriptor containing SPI interface parameters
|
||||
* @param msg Offload message that get's to be transferred
|
||||
* @param no_samples Number of time the messages will be transferred
|
||||
* @return int32_t This function allways returns SUCCESS
|
||||
*/
|
||||
int32_t spi_engine_offload_transfer(struct spi_desc *desc,
|
||||
struct spi_engine_offload_message msg,
|
||||
uint32_t no_samples)
|
||||
{
|
||||
struct spi_engine_msg transfer;
|
||||
struct spi_engine_desc *eng_desc;
|
||||
uint32_t i;
|
||||
uint8_t word_length;
|
||||
|
||||
eng_desc = desc->extra;
|
||||
|
||||
/* Check if offload is disabled */
|
||||
if(!((eng_desc->offload_config & OFFLOAD_TX_EN) |
|
||||
(eng_desc->offload_config & OFFLOAD_RX_EN)))
|
||||
return FAILURE;
|
||||
|
||||
spi_engine_write(eng_desc, SPI_ENGINE_REG_OFFLOAD_RESET(0), 1);
|
||||
spi_engine_write(eng_desc, SPI_ENGINE_REG_OFFLOAD_RESET(0), 0);
|
||||
|
||||
eng_desc->offload_tx_len = 0;
|
||||
eng_desc->offload_rx_len = 0;
|
||||
|
||||
transfer.cmds = (spi_engine_cmd_queue*)malloc(sizeof(*transfer.cmds));
|
||||
|
||||
if (!transfer.cmds)
|
||||
return FAILURE;
|
||||
|
||||
transfer.tx_buf = msg.commands_data;
|
||||
|
||||
/* Load the commands into the message */
|
||||
transfer.cmds->next = NULL;
|
||||
transfer.cmds->cmd = msg.commands[0];
|
||||
i = 1;
|
||||
while(i < msg.no_commands) {
|
||||
spi_engine_queue_add_cmd(&transfer.cmds, msg.commands[i++]);
|
||||
|
||||
}
|
||||
|
||||
spi_engine_transfer_message(desc, &transfer);
|
||||
|
||||
/* Start transfer */
|
||||
spi_engine_write(eng_desc, SPI_ENGINE_REG_OFFLOAD_CTRL(0), 0x0001);
|
||||
|
||||
word_length = spi_get_word_length(eng_desc);
|
||||
if(eng_desc->offload_config & OFFLOAD_TX_EN) {
|
||||
axi_dmac_transfer(eng_desc->offload_tx_dma,
|
||||
msg.tx_addr,
|
||||
word_length * eng_desc->offload_tx_len *
|
||||
no_samples);
|
||||
}
|
||||
|
||||
if(eng_desc->offload_config & OFFLOAD_RX_EN) {
|
||||
axi_dmac_transfer(eng_desc->offload_rx_dma,
|
||||
msg.rx_addr,
|
||||
word_length * eng_desc->offload_tx_len *
|
||||
no_samples);
|
||||
}
|
||||
|
||||
usleep(1000);
|
||||
|
||||
spi_engine_queue_free(&transfer.cmds);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Free the resources allocated by spi_init().
|
||||
*
|
||||
* @param desc Decriptor containing SPI interface parameters
|
||||
* @return int32_t This function allways returns SUCCESS
|
||||
*/
|
||||
int32_t spi_engine_remove(struct spi_desc *desc)
|
||||
{
|
||||
struct spi_engine_desc *eng_desc;
|
||||
|
||||
eng_desc = desc->extra;
|
||||
|
||||
if(eng_desc->offload_config & OFFLOAD_TX_EN)
|
||||
axi_dmac_remove(eng_desc->offload_tx_dma);
|
||||
if(eng_desc->offload_config & OFFLOAD_RX_EN)
|
||||
axi_dmac_remove(eng_desc->offload_rx_dma);
|
||||
free(desc->extra);
|
||||
free(desc);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
+231
@@ -0,0 +1,231 @@
|
||||
/*******************************************************************************
|
||||
* @file spi_engine.h
|
||||
* @brief Header file of SPI Engine core features.
|
||||
* @author Sergiu Cuciurean (sergiu.cuciurean@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2019(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef SPI_ENGINE_H
|
||||
#define SPI_ENGINE_H
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include "spi_engine_private.h"
|
||||
#include "../../platform/spi_extra.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/********************** Macros and Constants Definitions **********************/
|
||||
/******************************************************************************/
|
||||
|
||||
#define OFFLOAD_DISABLED 0x00
|
||||
#define OFFLOAD_TX_EN BIT(0)
|
||||
#define OFFLOAD_RX_EN BIT(1)
|
||||
#define OFFLOAD_TX_RX_EN OFFLOAD_TX_EN | OFFLOAD_RX_EN
|
||||
|
||||
#define SPI_ENGINE_MSG_QUEUE_END 0xFFFFFFFF
|
||||
|
||||
/* Spi engine commands */
|
||||
#define WRITE_OR_READ(mode, no_bytes) ((SPI_ENGINE_INST_TRANSFER << 12) |\
|
||||
((mode) << 8) | (no_bytes))
|
||||
|
||||
#define WRITE(no_bytes) ((SPI_ENGINE_INST_TRANSFER << 12) |\
|
||||
(SPI_ENGINE_INSTRUCTION_TRANSFER_W << 8) | (no_bytes))
|
||||
|
||||
#define READ(no_bytes) ((SPI_ENGINE_INST_TRANSFER << 12) |\
|
||||
(SPI_ENGINE_INSTRUCTION_TRANSFER_R << 8) | (no_bytes))
|
||||
|
||||
#define WRITE_READ(no_bytes) ((SPI_ENGINE_INST_TRANSFER << 12) |\
|
||||
(SPI_ENGINE_INSTRUCTION_TRANSFER_RW << 8) | (no_bytes))
|
||||
|
||||
|
||||
|
||||
#define SLEEP(time) SPI_ENGINE_CMD_SLEEP(time & 0xF)
|
||||
|
||||
/* The delay and chip select parmeters are passed over the engine descriptor
|
||||
and will be used inside the function call */
|
||||
#define CS_HIGH SPI_ENGINE_CMD_ASSERT(0x00, 0xFF)
|
||||
#define CS_LOW SPI_ENGINE_CMD_ASSERT(0x00, 0x00)
|
||||
|
||||
/******************************************************************************/
|
||||
/*************************** Types Declarations *******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @struct spi_engine_init_param
|
||||
* @brief Structure containing the init parameters needed by the SPI engine
|
||||
*/
|
||||
struct spi_engine_init_param {
|
||||
/** SPI engine reference clock */
|
||||
uint32_t ref_clk_hz;
|
||||
/** Type of implementation */
|
||||
enum xil_spi_type type;
|
||||
/** Base address where the HDL core is situated */
|
||||
uint32_t spi_engine_baseaddr;
|
||||
/** Delay between the CS toggle and the start of SCLK */
|
||||
uint32_t cs_delay;
|
||||
/** Data with of one SPI transfer ( in bits ) */
|
||||
uint8_t data_width;
|
||||
};
|
||||
|
||||
|
||||
/**
|
||||
* @struct spi_engine_desc
|
||||
* @brief Structure representing an SPI engine device
|
||||
*/
|
||||
struct spi_engine_desc {
|
||||
/** SPI engine reference clock */
|
||||
uint32_t ref_clk_hz;
|
||||
/** Type of implementation */
|
||||
enum xil_spi_type type;
|
||||
/** Pointer to a DMAC used in transmission */
|
||||
struct axi_dmac *offload_tx_dma;
|
||||
/** Pointer to a DMAC used in reception */
|
||||
struct axi_dmac *offload_rx_dma;
|
||||
/** Offload's module transfer direction : TX, RX or both */
|
||||
uint8_t offload_config;
|
||||
/** Number of words that the module has to send */
|
||||
uint8_t offload_tx_len;
|
||||
/** Number of words that the module has to receive */
|
||||
uint8_t offload_rx_len;
|
||||
/** Base address where the HDL core is situated */
|
||||
uint32_t spi_engine_baseaddr;
|
||||
/** Base address where the RX DMAC core is situated */
|
||||
uint32_t rx_dma_baseaddr;
|
||||
/** Base address where the TX DMAC core is situated */
|
||||
uint32_t tx_dma_baseaddr;
|
||||
/** Delay between the CS toggle and the start of SCLK */
|
||||
uint8_t cs_delay;
|
||||
/** Clock divider used in transmission delays */
|
||||
uint32_t clk_div;
|
||||
/** Data with of one SPI transfer ( in bits ) */
|
||||
uint8_t data_width;
|
||||
/** The maximum data width supported by the engine */
|
||||
uint8_t max_data_width;
|
||||
};
|
||||
|
||||
|
||||
/**
|
||||
* @struct spi_engine_offload_init_param
|
||||
* @brief Structure containing the init parameters needed by the offload module
|
||||
*/
|
||||
struct spi_engine_offload_init_param {
|
||||
/** Base address where the RX DMAC core is situated */
|
||||
uint32_t rx_dma_baseaddr;
|
||||
/** Base address where the TX DMAC core is situated */
|
||||
uint32_t tx_dma_baseaddr;
|
||||
/** DMAC flags - if not initialized, the default value is DMA_CYCLIC */
|
||||
uint32_t *dma_flags;
|
||||
/** Offload's module transfer direction : TX, RX or both */
|
||||
uint8_t offload_config;
|
||||
};
|
||||
|
||||
/**
|
||||
* @struct spi_engine_offload_message
|
||||
* @brief Structure representing an offload message
|
||||
*/
|
||||
struct spi_engine_offload_message {
|
||||
/** Pointer to the SPI engine commands buffer that will be sent.
|
||||
* The available commands can be found at:
|
||||
* https://wiki.analog.com/resources/fpga/peripherals/spi_engine/
|
||||
*/
|
||||
uint32_t *commands;
|
||||
/** Length of the SPI engine commands buffer */
|
||||
uint32_t no_commands;
|
||||
/** Pointer of the data that will be sent over spi */
|
||||
uint32_t *commands_data;
|
||||
/** The address where the data that will be transmitted is situated */
|
||||
uint32_t tx_addr;
|
||||
/** The address where the data that will be received is situated */
|
||||
uint32_t rx_addr;
|
||||
};
|
||||
|
||||
/******************************************************************************/
|
||||
/************************ Functions Declarations ******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief Spi engine platform specific SPI platform ops structure
|
||||
*/
|
||||
extern const struct spi_platform_ops xil_spi_ops;
|
||||
|
||||
/* Write SPI Engine's axi registers */
|
||||
int32_t spi_engine_write(struct spi_engine_desc *desc,
|
||||
uint32_t reg_addr,
|
||||
uint32_t reg_data);
|
||||
|
||||
/* Read SPI Engine's axi registers */
|
||||
int32_t spi_engine_read(struct spi_engine_desc *desc,
|
||||
uint32_t reg_addr,
|
||||
uint32_t *reg_data);
|
||||
/* Initialize the SPI engine device */
|
||||
int32_t spi_engine_init(struct spi_desc **desc,
|
||||
const struct spi_init_param *param);
|
||||
|
||||
/* Write and read data over SPI using the SPI engine */
|
||||
int32_t spi_engine_spi_write_and_read(struct spi_desc *desc,
|
||||
uint8_t *data,
|
||||
uint16_t bytes_number);
|
||||
|
||||
/* Write and read data over SPI using the SPI engine in 3-wire mode */
|
||||
int32_t spi_engine_spi_write_and_read_3wire(struct spi_desc *desc,
|
||||
uint8_t *write_data,
|
||||
uint8_t *read_data,
|
||||
uint16_t write_bytes_number,
|
||||
uint16_t read_bytes_number);
|
||||
/* Free the resources used by the SPI engine device */
|
||||
int32_t spi_engine_remove(struct spi_desc *desc);
|
||||
|
||||
/* Initialize the SPI engine offload module */
|
||||
int32_t spi_engine_offload_init(struct spi_desc *desc,
|
||||
const struct spi_engine_offload_init_param *param);
|
||||
|
||||
/* Write and read data over SPI using the offload module */
|
||||
int32_t spi_engine_offload_transfer(struct spi_desc *desc,
|
||||
struct spi_engine_offload_message msg,
|
||||
uint32_t no_samples);
|
||||
|
||||
/* Set SPI transfer width */
|
||||
int32_t spi_engine_set_transfer_width(struct spi_desc *desc,
|
||||
uint8_t data_wdith);
|
||||
|
||||
/* Set SPI transfer speed */
|
||||
void spi_engine_set_speed(struct spi_desc *desc,
|
||||
uint32_t speed_hz);
|
||||
|
||||
#endif // SPI_ENGINE_H
|
||||
+154
@@ -0,0 +1,154 @@
|
||||
/*******************************************************************************
|
||||
* @file spi_engine_private.h
|
||||
* @brief Private definitions of the SPI Engine
|
||||
* @author Sergiu Cuciurean (sergiu.cuciurean@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2019(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef SPI_ENGINE_PRIVATE_H
|
||||
#define SPI_ENGINE_PRIVATE_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "../../../include/spi.h"
|
||||
#include "../../../include/util.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/*************************** Spi Engine registers *****************************/
|
||||
/******************************************************************************/
|
||||
|
||||
#define SPI_ENGINE_REG_VERSION 0x00
|
||||
#define SPI_ENGINE_REG_DATA_WIDTH 0x0C
|
||||
#define SPI_ENGINE_REG_RESET 0x40
|
||||
#define SPI_ENGINE_REG_INT_ENABLE 0x80
|
||||
#define SPI_ENGINE_REG_INT_PENDING 0x84
|
||||
#define SPI_ENGINE_REG_INT_SOURCE 0x88
|
||||
#define SPI_ENGINE_REG_SYNC_ID 0xC0
|
||||
#define SPI_ENGINE_REG_CMD_FIFO_ROOM 0xD0
|
||||
#define SPI_ENGINE_REG_SDO_FIFO_ROOM 0xD4
|
||||
#define SPI_ENGINE_REG_SDI_FIFO_LEVEL 0xD8
|
||||
#define SPI_ENGINE_REG_CMD_FIFO 0xE0
|
||||
#define SPI_ENGINE_REG_SDO_DATA_FIFO 0xE4
|
||||
#define SPI_ENGINE_REG_SDI_DATA_FIFO 0xE8
|
||||
#define SPI_ENGINE_REG_SDI_DATA_FIFO_PEEK 0xEC
|
||||
|
||||
/******************************************************************************/
|
||||
/************************ Spi Engine register parameters **********************/
|
||||
/******************************************************************************/
|
||||
|
||||
#define SPI_ENGINE_INST_TRANSFER 0x00
|
||||
#define SPI_ENGINE_INST_ASSERT 0x01
|
||||
#define SPI_ENGINE_INST_CONFIG 0x02
|
||||
#define SPI_ENGINE_INST_SYNC_SLEEP 0x03
|
||||
#define SPI_ENGINE_INST_MISC 0x03
|
||||
#define SPI_ENGINE_CMD_REG_CLK_DIV 0x00
|
||||
#define SPI_ENGINE_CMD_REG_CONFIG 0x01
|
||||
#define SPI_ENGINE_CMD_DATA_TRANSFER_LEN 0x02
|
||||
#define SPI_ENGINE_MISC_SYNC 0x00
|
||||
#define SPI_ENGINE_MISC_SLEEP 0x01
|
||||
#define SPI_ENGINE_SYNC_TRANSFER_BEGIN BIT(1)
|
||||
#define SPI_ENGINE_SYNC_TRANSFER_END BIT(2)
|
||||
#define SPI_ENGINE_INT_CMD_ALMOST_EMPTY BIT(0)
|
||||
#define SPI_ENGINE_INT_SDO_ALMOST_EMPTY BIT(1)
|
||||
#define SPI_ENGINE_INT_SDI_ALMOST_FULL BIT(2)
|
||||
#define SPI_ENGINE_INT_SYNC BIT(3)
|
||||
#define SPI_ENGINE_OFFLOAD_CTRL_ENABLE BIT(0)
|
||||
#define SPI_ENGINE_OFFLOAD_STATUS_ENABLED BIT(0)
|
||||
#define SPI_ENGINE_CONFIG_CPHA BIT(0)
|
||||
#define SPI_ENGINE_CONFIG_CPOL BIT(1)
|
||||
#define SPI_ENGINE_CONFIG_3WIRE BIT(2)
|
||||
#define SPI_ENGINE_VERSION_MAJOR(x) ((x >> 16) & 0xff)
|
||||
#define SPI_ENGINE_VERSION_MINOR(x) ((x >> 8) & 0xff)
|
||||
#define SPI_ENGINE_VERSION_PATCH(x) (x & 0xff)
|
||||
|
||||
/******************************************************************************/
|
||||
/**************************** Spi Engine commands *****************************/
|
||||
/******************************************************************************/
|
||||
|
||||
#define SPI_ENGINE_INSTRUCTION_TRANSFER_W 0x01
|
||||
#define SPI_ENGINE_INSTRUCTION_TRANSFER_R 0x02
|
||||
#define SPI_ENGINE_INSTRUCTION_TRANSFER_RW 0x03
|
||||
|
||||
#define SPI_ENGINE_REG_OFFLOAD_CTRL(x) (0x100 + (0x20 * x))
|
||||
#define SPI_ENGINE_REG_OFFLOAD_STATUS(x) (0x104 + (0x20 * x))
|
||||
#define SPI_ENGINE_REG_OFFLOAD_RESET(x) (0x108 + (0x20 * x))
|
||||
#define SPI_ENGINE_REG_OFFLOAD_CMD_MEM(x) (0x110 + (0x20 * x))
|
||||
#define SPI_ENGINE_REG_OFFLOAD_SDO_MEM(x) (0x114 + (0x20 * x))
|
||||
|
||||
#define SPI_ENGINE_CMD(inst, arg1, arg2) \
|
||||
(((inst & 0x03) << 12) | \
|
||||
((arg1 & 0x03) << 8) | arg2 )
|
||||
|
||||
#define SPI_ENGINE_CMD_TRANSFER(readwrite, n) \
|
||||
SPI_ENGINE_CMD(SPI_ENGINE_INST_TRANSFER, \
|
||||
(readwrite), (n))
|
||||
|
||||
#define SPI_ENGINE_CMD_ASSERT(delay, cs) \
|
||||
SPI_ENGINE_CMD(SPI_ENGINE_INST_ASSERT, \
|
||||
(delay), (cs))
|
||||
|
||||
#define SPI_ENGINE_CMD_CONFIG(reg, val) \
|
||||
SPI_ENGINE_CMD(SPI_ENGINE_INST_CONFIG, \
|
||||
(reg), (val))
|
||||
|
||||
#define SPI_ENGINE_CMD_SLEEP(delay) \
|
||||
SPI_ENGINE_CMD(SPI_ENGINE_INST_MISC, \
|
||||
SPI_ENGINE_MISC_SLEEP, \
|
||||
(delay))
|
||||
|
||||
#define SPI_ENGINE_CMD_SYNC(id) \
|
||||
SPI_ENGINE_CMD(SPI_ENGINE_INST_MISC, \
|
||||
SPI_ENGINE_MISC_SYNC, \
|
||||
(id))
|
||||
|
||||
/******************************************************************************/
|
||||
/*************************** Types Declarations *******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
typedef struct spi_engine_cmd_queue {
|
||||
uint32_t cmd;
|
||||
struct spi_engine_cmd_queue *next;
|
||||
} spi_engine_cmd_queue;
|
||||
|
||||
typedef struct spi_engine_msg {
|
||||
uint32_t *tx_buf;
|
||||
uint32_t *rx_buf;
|
||||
uint32_t tx_length;
|
||||
uint32_t rx_length;
|
||||
struct spi_engine_cmd_queue *cmds;
|
||||
} spi_engine_msg;
|
||||
|
||||
#endif // SPI_ENGINE_PRIVATE_H
|
||||
+928
@@ -0,0 +1,928 @@
|
||||
/***************************************************************************//**
|
||||
* @file hmc7044.c
|
||||
* @brief Implementation of HMC7044, HMC7043 Driver.
|
||||
* @author DBogdan (dragos.bogdan@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2018-2020(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
#include <stdlib.h>
|
||||
#include <stdio.h>
|
||||
#include "hmc7044.h"
|
||||
#include "../../../include/error.h"
|
||||
#include "../../../include/util.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/********************** Macros and Constants Definitions **********************/
|
||||
/******************************************************************************/
|
||||
#define HMC7044_WRITE (0 << 15)
|
||||
#define HMC7044_READ (1 << 15)
|
||||
#define HMC7044_CNT(x) (((x) - 1) << 13)
|
||||
#define HMC7044_ADDR(x) ((x) & 0xFFF)
|
||||
|
||||
/* Global Control */
|
||||
#define HMC7044_REG_SOFT_RESET 0x0000
|
||||
#define HMC7044_SOFT_RESET BIT(0)
|
||||
|
||||
#define HMC7044_REG_REQ_MODE_0 0x0001
|
||||
#define HMC7044_RESEED_REQ BIT(7)
|
||||
#define HMC7044_HIGH_PERF_DISTRIB_PATH BIT(6)
|
||||
#define HMC7044_HIGH_PERF_PLL_VCO BIT(5)
|
||||
#define HMC7044_FORCE_HOLDOVER BIT(4)
|
||||
#define HMC7044_MUTE_OUT_DIV BIT(3)
|
||||
#define HMC7044_PULSE_GEN_REQ BIT(2)
|
||||
#define HMC7044_RESTART_DIV_FSM BIT(1)
|
||||
#define HMC7044_SLEEP_MODE BIT(0)
|
||||
|
||||
#define HMC7044_REG_REQ_MODE_1 0x0002
|
||||
#define HMC7044_PLL2_AUTOTUNE_TRIG BIT(2)
|
||||
#define HMC7044_SLIP_REQ BIT(1)
|
||||
|
||||
#define HMC7044_REG_EN_CTRL_0 0x0003
|
||||
#define HMC7044_RF_RESEEDER_EN BIT(5)
|
||||
#define HMC7044_VCO_SEL(x) (((x) & 0x3) << 3)
|
||||
#define HMC7044_VCO_EXT 0
|
||||
#define HMC7044_VCO_HIGH 1
|
||||
#define HMC7044_VCO_LOW 2
|
||||
#define HMC7044_SYSREF_TIMER_EN BIT(2)
|
||||
#define HMC7044_PLL2_EN BIT(1)
|
||||
#define HMC7044_PLL1_EN BIT(0)
|
||||
|
||||
#define HMC7044_REG_EN_CTRL_1 0x0004
|
||||
#define HMC7044_SEVEN_PAIRS(x) ((x) & 0x7f)
|
||||
|
||||
#define HMC7044_REG_GLOB_MODE 0x0005
|
||||
#define HMC7044_REF_PATH_EN(x) ((x) & 0xf)
|
||||
#define HMC7044_RFSYNC_EN BIT(4)
|
||||
#define HMC7044_VCOIN_MODE_EN BIT(5)
|
||||
#define HMC7044_SYNC_PIN_MODE(x) (((x) & 0x3) << 6)
|
||||
|
||||
/* PLL1 */
|
||||
#define HMC7044_REG_CLKIN0_BUF_CTRL 0x000A
|
||||
#define HMC7044_REG_CLKIN1_BUF_CTRL 0x000B
|
||||
#define HMC7044_REG_CLKIN2_BUF_CTRL 0x000C
|
||||
#define HMC7044_REG_CLKIN3_BUF_CTRL 0x000D
|
||||
#define HMC7044_REG_OSCIN_BUF_CTRL 0x000E
|
||||
|
||||
#define HMC7044_REG_PLL1_REF_PRIO_CTRL 0x0014
|
||||
|
||||
#define HMC7044_HIGH_Z_EN BIT(4)
|
||||
#define HMC7044_LVPECL_EN BIT(3)
|
||||
#define HMC7044_AC_COUPLING_EN BIT(2)
|
||||
#define HMC7044_100_OHM_EN BIT(1)
|
||||
#define HMC7044_BUF_EN BIT(0)
|
||||
|
||||
#define HMC7044_REG_CLKIN_PRESCALER(x) (0x001C + (x))
|
||||
#define HMC7044_REG_OSCIN_PRESCALER 0x0020
|
||||
|
||||
#define HMC7044_REG_PLL1_R_LSB 0x0021
|
||||
#define HMC7044_R1_LSB(x) ((x) & 0xff)
|
||||
|
||||
#define HMC7044_REG_PLL1_R_MSB 0x0022
|
||||
#define HMC7044_R1_MSB(x) (((x) & 0xff00) >> 8)
|
||||
|
||||
#define HMC7044_REG_PLL1_N_LSB 0x0026
|
||||
#define HMC7044_N1_LSB(x) ((x) & 0xff)
|
||||
|
||||
#define HMC7044_REG_PLL1_N_MSB 0x0027
|
||||
#define HMC7044_N1_MSB(x) (((x) & 0xff00) >> 8)
|
||||
|
||||
#define HMC7044_REG_PLL1_LOCK_DETECT 0x0028
|
||||
#define HMC7044_LOCK_DETECT_SLIP BIT(5)
|
||||
#define HMC7044_LOCK_DETECT_TIMER(x) ((x) & 0x1f)
|
||||
|
||||
/* PLL2 */
|
||||
#define HMC7044_REG_PLL2_FREQ_DOUBLER 0x0032
|
||||
#define HMC7044_PLL2_FREQ_DOUBLER_DIS BIT(0)
|
||||
|
||||
#define HMC7044_REG_PLL2_R_LSB 0x0033
|
||||
#define HMC7044_R2_LSB(x) ((x) & 0xff)
|
||||
|
||||
#define HMC7044_REG_PLL2_R_MSB 0x0034
|
||||
#define HMC7044_R2_MSB(x) (((x) & 0xf00) >> 8)
|
||||
|
||||
#define HMC7044_REG_PLL2_N_LSB 0x0035
|
||||
#define HMC7044_N2_LSB(x) ((x) & 0xff)
|
||||
|
||||
#define HMC7044_REG_PLL2_N_MSB 0x0036
|
||||
#define HMC7044_N2_MSB(x) (((x) & 0xff00) >> 8)
|
||||
|
||||
#define HMC7044_REG_OSCOUT_PATH 0x0039
|
||||
#define HMC7044_REG_OSCOUT_DRIVER_0 0x003A
|
||||
#define HMC7044_REG_OSCOUT_DRIVER_1 0x003B
|
||||
|
||||
/* GPIO/SDATA Control */
|
||||
#define HMC7044_REG_GPI_CTRL(x) (0x0046 + (x))
|
||||
#define HMC7044_REG_GPI_SEL(x) ((x) & 0xf)
|
||||
|
||||
#define HMC7044_REG_GPO_CTRL(x) (0x0050 + (x))
|
||||
#define HMC7044_GPO_SEL(x) (((x) & 0x3f) << 2)
|
||||
#define HMC7044_GPO_MODE BIT(1)
|
||||
#define HMC7044_GPO_EN BIT(0)
|
||||
|
||||
/* SYSREF/SYNC Control */
|
||||
#define HMC7044_REG_PULSE_GEN 0x005A
|
||||
#define HMC7044_PULSE_GEN_MODE(x) ((x) & 0x7)
|
||||
|
||||
#define HMC7044_REG_SYNC 0x005B
|
||||
#define HMC7044_SYNC_RETIME BIT(2)
|
||||
#define HMC7044_SYNC_THROUGH_PLL2 BIT(1)
|
||||
#define HMC7044_SYNC_POLARITY BIT(0)
|
||||
|
||||
#define HMC7044_REG_SYSREF_TIMER_LSB 0x005C
|
||||
#define HMC7044_SYSREF_TIMER_LSB(x) ((x) & 0xff)
|
||||
|
||||
#define HMC7044_REG_SYSREF_TIMER_MSB 0x005D
|
||||
#define HMC7044_SYSREF_TIMER_MSB(x) (((x) & 0xf00) >> 8)
|
||||
|
||||
#define HMC7044_CLK_INPUT_CTRL 0x0064
|
||||
#define HMC7044_LOW_FREQ_INPUT_MODE BIT(0)
|
||||
#define HMC7044_DIV_2_INPUT_MODE BIT(1)
|
||||
|
||||
/* Status and Alarm readback */
|
||||
#define HMC7044_REG_ALARM_READBACK 0x007D
|
||||
#define HMC7044_REG_PLL1_STATUS 0x0082
|
||||
|
||||
#define HMC7044_PLL1_FSM_STATE(x) ((x) & 0x7)
|
||||
#define HMC7044_PLL1_ACTIVE_CLKIN(x) (((x) >> 3) & 0x3)
|
||||
|
||||
#define HMC7044_PLL2_LOCK_DETECT(x) ((x) & 0x1)
|
||||
#define HMC7044_SYSREF_SYNC_STAT(x) ((x) & 0x2)
|
||||
#define HMC7044_CLK_OUT_PH_STATUS(x) ((x) & 0x4)
|
||||
#define HMC7044_PLL1_PLL2_LOCK_STAT(x) ((x) & 0x8)
|
||||
#define HMC7044_SYNC_REQ_STATUS(x) ((x) & 0x10)
|
||||
|
||||
/* Other Controls */
|
||||
#define HMC7044_REG_CLK_OUT_DRV_LOW_PW 0x009F
|
||||
#define HMC7044_REG_CLK_OUT_DRV_HIGH_PW 0x00A0
|
||||
#define HMC7044_REG_PLL1_DELAY 0x00A5
|
||||
#define HMC7044_REG_PLL1_HOLDOVER 0x00A8
|
||||
#define HMC7044_REG_VTUNE_PRESET 0x00B0
|
||||
|
||||
/* Clock Distribution */
|
||||
#define HMC7044_REG_CH_OUT_CRTL_0(ch) (0x00C8 + 0xA * (ch))
|
||||
#define HMC7044_HI_PERF_MODE BIT(7)
|
||||
#define HMC7044_SYNC_EN BIT(6)
|
||||
#define HMC7044_CH_EN BIT(0)
|
||||
#define HMC7044_START_UP_MODE_DYN_EN (BIT(3) | BIT(2))
|
||||
|
||||
#define HMC7044_REG_CH_OUT_CRTL_1(ch) (0x00C9 + 0xA * (ch))
|
||||
#define HMC7044_DIV_LSB(x) ((x) & 0xFF)
|
||||
|
||||
#define HMC7044_REG_CH_OUT_CRTL_2(ch) (0x00CA + 0xA * (ch))
|
||||
#define HMC7044_DIV_MSB(x) (((x) >> 8) & 0xFF)
|
||||
|
||||
#define HMC7044_REG_CH_OUT_CRTL_3(ch) (0x00CB + 0xA * (ch))
|
||||
#define HMC7044_REG_CH_OUT_CRTL_4(ch) (0x00CC + 0xA * (ch))
|
||||
#define HMC7044_REG_CH_OUT_CRTL_5(ch) (0x00CD + 0xA * (ch))
|
||||
#define HMC7044_REG_CH_OUT_CRTL_6(ch) (0x00CE + 0xA * (ch))
|
||||
#define HMC7044_REG_CH_OUT_CRTL_7(ch) (0x00CF + 0xA * (ch))
|
||||
|
||||
#define HMC7044_REG_CH_OUT_CRTL_8(ch) (0x00D0 + 0xA * (ch))
|
||||
#define HMC7044_DRIVER_MODE(x) (((x) & 0x3) << 3)
|
||||
#define HMC7044_DRIVER_Z_MODE(x) (((x) & 0x3) << 0)
|
||||
#define HMC7044_DYN_DRIVER_EN BIT(5)
|
||||
#define HMC7044_FORCE_MUTE_EN BIT(7)
|
||||
|
||||
#define HMC7044_NUM_CHAN 14
|
||||
|
||||
#define HMC7044_LOW_VCO_MIN 2150000
|
||||
#define HMC7044_LOW_VCO_MAX 2880000
|
||||
#define HMC7044_HIGH_VCO_MIN 2650000
|
||||
#define HMC7044_HIGH_VCO_MAX 3200000
|
||||
|
||||
#define HMC7044_RECOMM_LCM_MIN 30000
|
||||
#define HMC7044_RECOMM_LCM_MAX 70000
|
||||
#define HMC7044_RECOMM_FPD1 10000
|
||||
|
||||
#define HMC7044_R1_MAX 65535
|
||||
#define HMC7044_N1_MAX 65535
|
||||
|
||||
#define HMC7044_R2_MIN 1
|
||||
#define HMC7044_R2_MAX 4095
|
||||
#define HMC7044_N2_MIN 8
|
||||
#define HMC7044_N2_MAX 65535
|
||||
|
||||
#define HMC7044_OUT_DIV_MIN 1
|
||||
#define HMC7044_OUT_DIV_MAX 4094
|
||||
|
||||
/******************************************************************************/
|
||||
/************************** Functions Implementation **************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* SPI register write to device.
|
||||
* @param dev - The device structure.
|
||||
* @param reg - The register address.
|
||||
* @param val - The register data.
|
||||
* @return SUCCESS in case of success, negative error code otherwise.
|
||||
*/
|
||||
int32_t hmc7044_write(struct hmc7044_dev *dev,
|
||||
uint16_t reg,
|
||||
uint8_t val)
|
||||
{
|
||||
uint8_t buf[3];
|
||||
uint16_t cmd;
|
||||
|
||||
cmd = HMC7044_WRITE | HMC7044_CNT(1) | HMC7044_ADDR(reg);
|
||||
buf[0] = cmd >> 8;
|
||||
buf[1] = cmd & 0xFF;
|
||||
buf[2] = val;
|
||||
return spi_write_and_read_3wire(dev->spi_desc, buf, NULL,
|
||||
ARRAY_SIZE(buf), 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* SPI register read from device.
|
||||
* @param dev - The device structure.
|
||||
* @param reg - The register address.
|
||||
* @param val - The register data.
|
||||
* @return SUCCESS in case of success, negative error code otherwise.
|
||||
*/
|
||||
|
||||
int32_t hmc7044_read(struct hmc7044_dev *dev, uint16_t reg, uint8_t *val)
|
||||
{
|
||||
uint8_t wr_buf[2];
|
||||
uint8_t rd_data[1];
|
||||
uint16_t cmd;
|
||||
int ret;
|
||||
|
||||
cmd = HMC7044_READ | HMC7044_CNT(1) | HMC7044_ADDR(reg);
|
||||
wr_buf[0] = cmd >> 8;
|
||||
wr_buf[1] = cmd & 0xFF;
|
||||
|
||||
ret = spi_write_and_read_3wire(dev->spi_desc, wr_buf, rd_data,
|
||||
ARRAY_SIZE(wr_buf), ARRAY_SIZE(rd_data));
|
||||
if (ret != SUCCESS)
|
||||
return ret;
|
||||
|
||||
*val = rd_data[0];
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* Calculate the output channel divider.
|
||||
* @param rate - The desired rate.
|
||||
* @param parent_rate - The parent rate.
|
||||
* @return The output divider.
|
||||
*/
|
||||
uint32_t hmc7044_calc_out_div(uint32_t rate,
|
||||
uint32_t parent_rate)
|
||||
{
|
||||
uint32_t div;
|
||||
|
||||
div = DIV_ROUND_CLOSEST(parent_rate, rate);
|
||||
|
||||
/* Supported odd divide ratios are 1, 3, and 5 */
|
||||
if ((div != 1) && (div != 3) && (div != 5) && (div % 2))
|
||||
div = DIV_ROUND_CLOSEST(parent_rate, rate * 2) * 2;
|
||||
|
||||
div = clamp_t(unsigned int,
|
||||
div,
|
||||
HMC7044_OUT_DIV_MIN,
|
||||
HMC7044_OUT_DIV_MAX);
|
||||
|
||||
return div;
|
||||
}
|
||||
|
||||
/**
|
||||
* Recalculate rate corresponding to a channel.
|
||||
* @param dev - The device structure.
|
||||
* @param chan_num - Channel number.
|
||||
* @param rate - Channel rate.
|
||||
* @return SUCCESS in case of success, negative error code otherwise.
|
||||
*/
|
||||
int32_t hmc7044_clk_recalc_rate(struct hmc7044_dev *dev, uint32_t chan_num,
|
||||
uint64_t *rate)
|
||||
{
|
||||
int i;
|
||||
struct hmc7044_chan_spec *chan = NULL;
|
||||
|
||||
/* Find the reqested channel number */
|
||||
for (i = 0; i < dev->num_channels; i++) {
|
||||
if (dev->channels[i].num == chan_num) {
|
||||
chan = &dev->channels[i];
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (chan == NULL )
|
||||
return FAILURE;
|
||||
|
||||
*rate = dev->pll2_freq / chan->divider;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* Calculate closest possible rate
|
||||
* @param dev - The device structure
|
||||
* @param rate - The desired rate.
|
||||
* @param rounded_rate - The closest possible rate of desired rate.
|
||||
* @return SUCCESS in case of success, negative error code otherwise.
|
||||
*/
|
||||
int32_t hmc7044_clk_round_rate(struct hmc7044_dev *dev, uint32_t rate,
|
||||
uint64_t *rounded_rate)
|
||||
{
|
||||
uint32_t div = hmc7044_calc_out_div(rate, dev->pll2_freq);
|
||||
|
||||
*rounded_rate = DIV_ROUND_CLOSEST(dev->pll2_freq, div);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set channel rate.
|
||||
* @param dev - The device structure.
|
||||
* @param chan_num - Channel number.
|
||||
* @param rate - Channel rate.
|
||||
* @return SUCCESS in case of success, negative error code otherwise.
|
||||
*/
|
||||
int32_t hmc7044_clk_set_rate(struct hmc7044_dev *dev, uint32_t chan_num,
|
||||
uint64_t rate)
|
||||
{
|
||||
uint32_t div;
|
||||
int32_t ret;
|
||||
int i;
|
||||
struct hmc7044_chan_spec *chan = NULL;
|
||||
|
||||
/* Find the reqested channel number */
|
||||
for (i = 0; i < dev->num_channels; i++) {
|
||||
if (dev->channels[i].num == chan_num) {
|
||||
chan = &dev->channels[i];
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (chan == NULL )
|
||||
return FAILURE;
|
||||
|
||||
div = hmc7044_calc_out_div(rate, dev->pll2_freq);
|
||||
chan->divider = div;
|
||||
|
||||
ret = hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_1(chan->num),
|
||||
HMC7044_DIV_LSB(div));
|
||||
if(ret < 0)
|
||||
return ret;
|
||||
|
||||
return hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_2(chan->num),
|
||||
HMC7044_DIV_MSB(div));
|
||||
}
|
||||
|
||||
/**
|
||||
* Setup the device.
|
||||
* @param dev - The device structure.
|
||||
* @return SUCCESS in case of success, negative error code otherwise.
|
||||
*/
|
||||
static int32_t hmc7044_setup(struct hmc7044_dev *dev)
|
||||
{
|
||||
struct hmc7044_chan_spec *chan;
|
||||
bool high_vco_en;
|
||||
bool pll2_freq_doubler_en;
|
||||
uint32_t vcxo_freq, pll2_freq;
|
||||
uint32_t clkin_freq[4];
|
||||
uint32_t lcm_freq;
|
||||
uint32_t in_prescaler[5];
|
||||
uint32_t pll1_lock_detect;
|
||||
uint32_t n1, r1;
|
||||
uint32_t pfd1_freq;
|
||||
uint32_t vco_limit;
|
||||
uint32_t n2[2], r2[2];
|
||||
uint32_t i, ref_en = 0;
|
||||
|
||||
vcxo_freq = dev->vcxo_freq / 1000;
|
||||
pll2_freq = dev->pll2_freq / 1000;
|
||||
|
||||
lcm_freq = vcxo_freq;
|
||||
for (i = 0; i < ARRAY_SIZE(clkin_freq); i++) {
|
||||
if (dev->clkin_freq_ccf[i])
|
||||
clkin_freq[i] = dev->clkin_freq_ccf[i] / 1000;
|
||||
else
|
||||
clkin_freq[i] = dev->clkin_freq[i] / 1000;
|
||||
|
||||
if (clkin_freq[i]) {
|
||||
lcm_freq = greatest_common_divisor(clkin_freq[i], lcm_freq);
|
||||
ref_en |= BIT(i);
|
||||
}
|
||||
}
|
||||
|
||||
while (lcm_freq > HMC7044_RECOMM_LCM_MAX)
|
||||
lcm_freq /= 2;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clkin_freq); i++) {
|
||||
if (clkin_freq[i])
|
||||
in_prescaler[i] = clkin_freq[i] / lcm_freq;
|
||||
else
|
||||
in_prescaler[i] = 1;
|
||||
}
|
||||
in_prescaler[4] = vcxo_freq / lcm_freq;
|
||||
|
||||
pll1_lock_detect = log_base_2((lcm_freq * 4000) / dev->pll1_loop_bw);
|
||||
|
||||
/* fVCXO / N1 = fLCM / R1 */
|
||||
rational_best_approximation(vcxo_freq, lcm_freq,
|
||||
HMC7044_N1_MAX, HMC7044_R1_MAX,
|
||||
&n1, &r1);
|
||||
|
||||
pfd1_freq = vcxo_freq / n1;
|
||||
while ((pfd1_freq > HMC7044_RECOMM_FPD1) &&
|
||||
(n1 <= HMC7044_N1_MAX / 2) &&
|
||||
(r1 <= HMC7044_R1_MAX / 2)) {
|
||||
pfd1_freq /= 2;
|
||||
n1 *= 2;
|
||||
r1 *= 2;
|
||||
}
|
||||
|
||||
dev->pll1_pfd = pfd1_freq;
|
||||
|
||||
if (pll2_freq < HMC7044_LOW_VCO_MIN ||
|
||||
pll2_freq > HMC7044_HIGH_VCO_MAX)
|
||||
return FAILURE;
|
||||
|
||||
vco_limit = (HMC7044_LOW_VCO_MAX + HMC7044_HIGH_VCO_MIN) / 2;
|
||||
if (pll2_freq >= vco_limit)
|
||||
high_vco_en = true;
|
||||
else
|
||||
high_vco_en = false;
|
||||
|
||||
/* fVCO / N2 = fVCXO * doubler / R2 */
|
||||
pll2_freq_doubler_en = true;
|
||||
rational_best_approximation(pll2_freq, vcxo_freq * 2,
|
||||
HMC7044_N2_MAX, HMC7044_R2_MAX,
|
||||
&n2[0], &r2[0]);
|
||||
|
||||
if (pll2_freq != vcxo_freq * n2[0] / r2[0]) {
|
||||
rational_best_approximation(pll2_freq, vcxo_freq,
|
||||
HMC7044_N2_MAX, HMC7044_R2_MAX,
|
||||
&n2[1], &r2[1]);
|
||||
|
||||
if (abs((int)pll2_freq - (int)(vcxo_freq * 2 * n2[0] / r2[0])) >
|
||||
abs((int)pll2_freq - (int)(vcxo_freq * n2[1] / r2[1]))) {
|
||||
n2[0] = n2[1];
|
||||
r2[0] = r2[1];
|
||||
pll2_freq_doubler_en = false;
|
||||
}
|
||||
}
|
||||
|
||||
while ((n2[0] < HMC7044_N2_MIN) && (r2[0] <= HMC7044_R2_MAX / 2)) {
|
||||
n2[0] *= 2;
|
||||
r2[0] *= 2;
|
||||
}
|
||||
if (n2[0] < HMC7044_N2_MIN)
|
||||
return -FAILURE;
|
||||
|
||||
/* Resets all registers to default values */
|
||||
hmc7044_write(dev, HMC7044_REG_SOFT_RESET, HMC7044_SOFT_RESET);
|
||||
mdelay(10);
|
||||
hmc7044_write(dev, HMC7044_REG_SOFT_RESET, 0);
|
||||
mdelay(10);
|
||||
|
||||
/* Disable all channels */
|
||||
for (i = 0; i < HMC7044_NUM_CHAN; i++)
|
||||
hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_0(i), 0);
|
||||
|
||||
/* Load the configuration updates (provided by Analog Devices) */
|
||||
hmc7044_write(dev, HMC7044_REG_CLK_OUT_DRV_LOW_PW, 0x4d);
|
||||
hmc7044_write(dev, HMC7044_REG_CLK_OUT_DRV_HIGH_PW, 0xdf);
|
||||
hmc7044_write(dev, HMC7044_REG_PLL1_DELAY, 0x06);
|
||||
hmc7044_write(dev, HMC7044_REG_PLL1_HOLDOVER, 0x06);
|
||||
hmc7044_write(dev, HMC7044_REG_VTUNE_PRESET, 0x04);
|
||||
|
||||
uint8_t rd_back;
|
||||
hmc7044_read(dev, HMC7044_REG_CLK_OUT_DRV_LOW_PW, &rd_back);
|
||||
hmc7044_read(dev, HMC7044_REG_CLK_OUT_DRV_HIGH_PW, &rd_back);
|
||||
hmc7044_read(dev, HMC7044_REG_PLL1_DELAY, &rd_back);
|
||||
hmc7044_read(dev, HMC7044_REG_PLL1_HOLDOVER, &rd_back);
|
||||
hmc7044_read(dev, HMC7044_REG_VTUNE_PRESET, &rd_back);
|
||||
|
||||
|
||||
hmc7044_write(dev, HMC7044_REG_GLOB_MODE,
|
||||
HMC7044_SYNC_PIN_MODE(dev->sync_pin_mode) |
|
||||
(dev->clkin0_rfsync_en ? HMC7044_RFSYNC_EN : 0) |
|
||||
(dev->clkin1_vcoin_en ? HMC7044_VCOIN_MODE_EN : 0) |
|
||||
HMC7044_REF_PATH_EN(ref_en));
|
||||
|
||||
/* Program PLL2 */
|
||||
|
||||
/* Select the VCO range */
|
||||
hmc7044_write(dev, HMC7044_REG_EN_CTRL_0,
|
||||
(dev->rf_reseeder_en ? HMC7044_RF_RESEEDER_EN : 0) |
|
||||
HMC7044_VCO_SEL(high_vco_en ?
|
||||
HMC7044_VCO_HIGH :
|
||||
HMC7044_VCO_LOW) |
|
||||
HMC7044_SYSREF_TIMER_EN | HMC7044_PLL2_EN |
|
||||
HMC7044_PLL1_EN);
|
||||
|
||||
/* Program the dividers */
|
||||
hmc7044_write(dev, HMC7044_REG_PLL2_R_LSB,
|
||||
HMC7044_R2_LSB(r2[0]));
|
||||
hmc7044_write(dev, HMC7044_REG_PLL2_R_MSB,
|
||||
HMC7044_R2_MSB(r2[0]));
|
||||
hmc7044_write(dev, HMC7044_REG_PLL2_N_LSB,
|
||||
HMC7044_N2_LSB(n2[0]));
|
||||
hmc7044_write(dev, HMC7044_REG_PLL2_N_MSB,
|
||||
HMC7044_N2_MSB(n2[0]));
|
||||
|
||||
/* Program the reference doubler */
|
||||
hmc7044_write(dev, HMC7044_REG_PLL2_FREQ_DOUBLER,
|
||||
pll2_freq_doubler_en ? 0 : HMC7044_PLL2_FREQ_DOUBLER_DIS);
|
||||
|
||||
/* Program PLL1 */
|
||||
|
||||
/* Set the lock detect timer threshold */
|
||||
hmc7044_write(dev, HMC7044_REG_PLL1_LOCK_DETECT,
|
||||
HMC7044_LOCK_DETECT_TIMER(pll1_lock_detect));
|
||||
|
||||
/* Set the LCM */
|
||||
for (i = 0; i < ARRAY_SIZE(clkin_freq); i++) {
|
||||
hmc7044_write(dev, HMC7044_REG_CLKIN_PRESCALER(i),
|
||||
in_prescaler[i]);
|
||||
}
|
||||
hmc7044_write(dev, HMC7044_REG_OSCIN_PRESCALER,
|
||||
in_prescaler[4]);
|
||||
|
||||
/* Program the dividers */
|
||||
hmc7044_write(dev, HMC7044_REG_PLL1_R_LSB,
|
||||
HMC7044_R2_LSB(r1));
|
||||
hmc7044_write(dev, HMC7044_REG_PLL1_R_MSB,
|
||||
HMC7044_R2_MSB(r1));
|
||||
hmc7044_write(dev, HMC7044_REG_PLL1_N_LSB,
|
||||
HMC7044_N2_LSB(n1));
|
||||
hmc7044_write(dev, HMC7044_REG_PLL1_N_MSB,
|
||||
HMC7044_N2_MSB(n1));
|
||||
|
||||
hmc7044_write(dev, HMC7044_REG_PLL1_REF_PRIO_CTRL,
|
||||
dev->pll1_ref_prio_ctrl);
|
||||
|
||||
/* Program the SYSREF timer */
|
||||
|
||||
/* Set the divide ratio */
|
||||
hmc7044_write(dev, HMC7044_REG_SYSREF_TIMER_LSB,
|
||||
HMC7044_SYSREF_TIMER_LSB(dev->sysref_timer_div));
|
||||
hmc7044_write(dev, HMC7044_REG_SYSREF_TIMER_MSB,
|
||||
HMC7044_SYSREF_TIMER_MSB(dev->sysref_timer_div));
|
||||
|
||||
/* Set the pulse generator mode configuration */
|
||||
hmc7044_write(dev, HMC7044_REG_PULSE_GEN,
|
||||
HMC7044_PULSE_GEN_MODE(dev->pulse_gen_mode));
|
||||
|
||||
/* Enable the input buffers */
|
||||
hmc7044_write(dev, HMC7044_REG_CLKIN0_BUF_CTRL,
|
||||
dev->in_buf_mode[0]);
|
||||
hmc7044_write(dev, HMC7044_REG_CLKIN1_BUF_CTRL,
|
||||
dev->in_buf_mode[1]);
|
||||
hmc7044_write(dev, HMC7044_REG_CLKIN2_BUF_CTRL,
|
||||
dev->in_buf_mode[2]);
|
||||
hmc7044_write(dev, HMC7044_REG_CLKIN3_BUF_CTRL,
|
||||
dev->in_buf_mode[3]);
|
||||
hmc7044_write(dev, HMC7044_REG_OSCIN_BUF_CTRL,
|
||||
dev->in_buf_mode[4]);
|
||||
|
||||
/* Set GPIOs */
|
||||
for (i = 0; i < ARRAY_SIZE(dev->gpi_ctrl); i++) {
|
||||
hmc7044_write(dev, HMC7044_REG_GPI_CTRL(i),
|
||||
dev->gpi_ctrl[i]);
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(dev->gpo_ctrl); i++) {
|
||||
hmc7044_write(dev, HMC7044_REG_GPO_CTRL(i),
|
||||
dev->gpo_ctrl[i]);
|
||||
}
|
||||
|
||||
mdelay(10);
|
||||
|
||||
/* Program the output channels */
|
||||
for (i = 0; i < dev->num_channels; i++) {
|
||||
chan = &dev->channels[i];
|
||||
if (chan->num >= HMC7044_NUM_CHAN || chan->disable)
|
||||
continue;
|
||||
|
||||
hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_1(chan->num),
|
||||
HMC7044_DIV_LSB(chan->divider));
|
||||
hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_2(chan->num),
|
||||
HMC7044_DIV_MSB(chan->divider));
|
||||
hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_8(chan->num),
|
||||
HMC7044_DRIVER_MODE(chan->driver_mode) |
|
||||
HMC7044_DRIVER_Z_MODE(chan->driver_impedance) |
|
||||
(chan->dynamic_driver_enable ?
|
||||
HMC7044_DYN_DRIVER_EN : 0) |
|
||||
(chan->force_mute_enable ?
|
||||
HMC7044_FORCE_MUTE_EN : 0));
|
||||
|
||||
hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_3(chan->num),
|
||||
chan->fine_delay & 0x1F);
|
||||
hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_4(chan->num),
|
||||
chan->coarse_delay & 0x1F);
|
||||
hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_7(chan->num),
|
||||
chan->out_mux_mode & 0x3);
|
||||
|
||||
hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_0(chan->num),
|
||||
(chan->start_up_mode_dynamic_enable ?
|
||||
HMC7044_START_UP_MODE_DYN_EN : 0) |
|
||||
(chan->output_control0_rb4_enable ? BIT(4) : 0) |
|
||||
(chan->high_performance_mode_dis ?
|
||||
0 : HMC7044_HI_PERF_MODE) | HMC7044_SYNC_EN |
|
||||
HMC7044_CH_EN);
|
||||
}
|
||||
mdelay(10);
|
||||
|
||||
/* Do a restart to reset the system and initiate calibration */
|
||||
hmc7044_write(dev, HMC7044_REG_REQ_MODE_0,
|
||||
HMC7044_RESTART_DIV_FSM);
|
||||
mdelay(1);
|
||||
hmc7044_write(dev, HMC7044_REG_REQ_MODE_0,
|
||||
(dev->high_performance_mode_clock_dist_en ?
|
||||
HMC7044_HIGH_PERF_DISTRIB_PATH : 0));
|
||||
mdelay(1);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* Setup the device.
|
||||
* @param dev - The device structure.
|
||||
* @return SUCCESS in case of success, negative error code otherwise.
|
||||
*/
|
||||
static int32_t hmc7043_setup(struct hmc7044_dev *dev)
|
||||
{
|
||||
struct hmc7044_chan_spec *chan;
|
||||
uint32_t i;
|
||||
|
||||
if (dev->clkin_freq_ccf[0])
|
||||
dev->pll2_freq = dev->clkin_freq_ccf[0];
|
||||
else
|
||||
dev->pll2_freq = dev->clkin_freq[0];
|
||||
|
||||
if (!dev->pll2_freq) {
|
||||
printf("%s: Failed to get valid parent rate\n", __func__);
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
/* Resets all registers to default values */
|
||||
hmc7044_write(dev, HMC7044_REG_SOFT_RESET, HMC7044_SOFT_RESET);
|
||||
mdelay(10);
|
||||
hmc7044_write(dev, HMC7044_REG_SOFT_RESET, 0);
|
||||
mdelay(10);
|
||||
|
||||
/* Load the configuration updates (provided by Analog Devices) */
|
||||
hmc7044_write(dev, HMC7044_REG_CLK_OUT_DRV_LOW_PW, 0x4d);
|
||||
hmc7044_write(dev, HMC7044_REG_CLK_OUT_DRV_HIGH_PW, 0xdf);
|
||||
|
||||
/* Disable all channels */
|
||||
for (i = 0; i < HMC7044_NUM_CHAN; i++)
|
||||
hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_0(i), 0);
|
||||
|
||||
if (dev->pll2_freq < 1000000000U)
|
||||
hmc7044_write(dev, HMC7044_CLK_INPUT_CTRL,
|
||||
HMC7044_LOW_FREQ_INPUT_MODE);
|
||||
|
||||
hmc7044_write(dev, HMC7044_REG_EN_CTRL_0,
|
||||
(dev->rf_reseeder_en ? HMC7044_RF_RESEEDER_EN : 0) |
|
||||
HMC7044_SYSREF_TIMER_EN);
|
||||
|
||||
/* Program the SYSREF timer */
|
||||
|
||||
/* Set the divide ratio */
|
||||
hmc7044_write(dev, HMC7044_REG_SYSREF_TIMER_LSB,
|
||||
HMC7044_SYSREF_TIMER_LSB(dev->sysref_timer_div));
|
||||
hmc7044_write(dev, HMC7044_REG_SYSREF_TIMER_MSB,
|
||||
HMC7044_SYSREF_TIMER_MSB(dev->sysref_timer_div));
|
||||
|
||||
/* Set the pulse generator mode configuration */
|
||||
hmc7044_write(dev, HMC7044_REG_PULSE_GEN,
|
||||
HMC7044_PULSE_GEN_MODE(dev->pulse_gen_mode));
|
||||
|
||||
/* Enable the input buffers */
|
||||
hmc7044_write(dev, HMC7044_REG_CLKIN0_BUF_CTRL,
|
||||
dev->in_buf_mode[0]);
|
||||
hmc7044_write(dev, HMC7044_REG_CLKIN1_BUF_CTRL,
|
||||
dev->in_buf_mode[1]);
|
||||
|
||||
/* Set GPIOs */
|
||||
hmc7044_write(dev, HMC7044_REG_GPI_CTRL(0),
|
||||
dev->gpi_ctrl[0]);
|
||||
|
||||
hmc7044_write(dev, HMC7044_REG_GPO_CTRL(0),
|
||||
dev->gpo_ctrl[0]);
|
||||
|
||||
/* Program the output channels */
|
||||
for (i = 0; i < dev->num_channels; i++) {
|
||||
chan = &dev->channels[i];
|
||||
|
||||
if (chan->num >= HMC7044_NUM_CHAN || chan->disable)
|
||||
continue;
|
||||
|
||||
hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_1(chan->num),
|
||||
HMC7044_DIV_LSB(chan->divider));
|
||||
hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_2(chan->num),
|
||||
HMC7044_DIV_MSB(chan->divider));
|
||||
hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_8(chan->num),
|
||||
HMC7044_DRIVER_MODE(chan->driver_mode) |
|
||||
HMC7044_DRIVER_Z_MODE(chan->driver_impedance) |
|
||||
(chan->dynamic_driver_enable ?
|
||||
HMC7044_DYN_DRIVER_EN : 0) |
|
||||
(chan->force_mute_enable ?
|
||||
HMC7044_FORCE_MUTE_EN : 0));
|
||||
|
||||
hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_3(chan->num),
|
||||
chan->fine_delay & 0x1F);
|
||||
hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_4(chan->num),
|
||||
chan->coarse_delay & 0x1F);
|
||||
hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_7(chan->num),
|
||||
chan->out_mux_mode & 0x3);
|
||||
|
||||
hmc7044_write(dev, HMC7044_REG_CH_OUT_CRTL_0(chan->num),
|
||||
(chan->start_up_mode_dynamic_enable ?
|
||||
HMC7044_START_UP_MODE_DYN_EN : 0) |
|
||||
(chan->output_control0_rb4_enable ? BIT(4) : 0) |
|
||||
(chan->high_performance_mode_dis ?
|
||||
0 : HMC7044_HI_PERF_MODE) | HMC7044_SYNC_EN |
|
||||
HMC7044_CH_EN);
|
||||
}
|
||||
mdelay(10);
|
||||
|
||||
|
||||
/* Do a restart to reset the system and initiate calibration */
|
||||
hmc7044_write(dev, HMC7044_REG_REQ_MODE_0,
|
||||
HMC7044_RESTART_DIV_FSM);
|
||||
mdelay(1);
|
||||
hmc7044_write(dev, HMC7044_REG_REQ_MODE_0,
|
||||
(dev->high_performance_mode_clock_dist_en ?
|
||||
HMC7044_HIGH_PERF_DISTRIB_PATH : 0));
|
||||
mdelay(1);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief hmc7044_reg_init
|
||||
*******************************************************************************/
|
||||
int32_t hmc7044_reg_init(struct hmc7044_dev **device,
|
||||
const struct hmc7044_init_param *init_param)
|
||||
{
|
||||
int ret = SUCCESS;
|
||||
struct hmc7044_dev *dev;
|
||||
|
||||
dev = (struct hmc7044_dev *)malloc(sizeof(*dev));
|
||||
if (!dev)
|
||||
return FAILURE;
|
||||
|
||||
/* SPI */
|
||||
ret = spi_init(&dev->spi_desc, init_param->spi_init);
|
||||
|
||||
*device = dev;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize the device.
|
||||
* @param device - The device structure.
|
||||
* @param init_param - The structure that contains the device initial
|
||||
* parameters.
|
||||
* @return SUCCESS in case of success, negative error code otherwise.
|
||||
*/
|
||||
int32_t hmc7044_init(struct hmc7044_dev **device,
|
||||
const struct hmc7044_init_param *init_param)
|
||||
{
|
||||
struct hmc7044_dev *dev;
|
||||
int32_t ret;
|
||||
unsigned int i;
|
||||
|
||||
dev = (struct hmc7044_dev *)malloc(sizeof(*dev));
|
||||
if (!dev)
|
||||
return FAILURE;
|
||||
|
||||
ret = spi_init(&dev->spi_desc, init_param->spi_init);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
dev->is_hmc7043 = init_param->is_hmc7043;
|
||||
|
||||
dev->clkin_freq[0] = init_param->clkin_freq[0];
|
||||
dev->clkin_freq[1] = init_param->clkin_freq[1];
|
||||
dev->clkin_freq[2] = init_param->clkin_freq[2];
|
||||
dev->clkin_freq[3] = init_param->clkin_freq[3];
|
||||
|
||||
dev->clkin_freq_ccf[0] = init_param->clkin_freq_ccf[0];
|
||||
dev->clkin_freq_ccf[1] = init_param->clkin_freq_ccf[1];
|
||||
dev->clkin_freq_ccf[2] = init_param->clkin_freq_ccf[2];
|
||||
dev->clkin_freq_ccf[3] = init_param->clkin_freq_ccf[3];
|
||||
|
||||
dev->vcxo_freq = init_param->vcxo_freq;
|
||||
dev->pll1_pfd = init_param->pll1_pfd;
|
||||
dev->pll2_freq = init_param->pll2_freq;
|
||||
dev->pll1_loop_bw = init_param->pll1_loop_bw;
|
||||
|
||||
dev->sysref_timer_div = init_param->sysref_timer_div;
|
||||
dev->pll1_ref_prio_ctrl = init_param->pll1_ref_prio_ctrl;
|
||||
dev->clkin0_rfsync_en = init_param->clkin0_rfsync_en;
|
||||
dev->clkin1_vcoin_en = init_param->clkin1_vcoin_en;
|
||||
dev->high_performance_mode_clock_dist_en =
|
||||
init_param->high_performance_mode_clock_dist_en;
|
||||
dev->rf_reseeder_en = !init_param->rf_reseeder_disable;
|
||||
dev->sync_pin_mode = init_param->sync_pin_mode;
|
||||
dev->pulse_gen_mode = init_param->pulse_gen_mode;
|
||||
|
||||
dev->in_buf_mode[0] = init_param->in_buf_mode[0];
|
||||
dev->in_buf_mode[1] = init_param->in_buf_mode[1];
|
||||
dev->in_buf_mode[2] = init_param->in_buf_mode[2];
|
||||
dev->in_buf_mode[3] = init_param->in_buf_mode[3];
|
||||
dev->in_buf_mode[4] = init_param->in_buf_mode[4];
|
||||
|
||||
dev->gpi_ctrl[0] = init_param->gpi_ctrl[0];
|
||||
dev->gpi_ctrl[1] = init_param->gpi_ctrl[1];
|
||||
dev->gpi_ctrl[2] = init_param->gpi_ctrl[2];
|
||||
dev->gpi_ctrl[3] = init_param->gpi_ctrl[3];
|
||||
|
||||
dev->gpo_ctrl[0] = init_param->gpo_ctrl[0];
|
||||
dev->gpo_ctrl[1] = init_param->gpo_ctrl[1];
|
||||
dev->gpo_ctrl[2] = init_param->gpo_ctrl[2];
|
||||
dev->gpo_ctrl[3] = init_param->gpo_ctrl[3];
|
||||
|
||||
dev->num_channels = init_param->num_channels;
|
||||
dev->channels = (struct hmc7044_chan_spec *)
|
||||
malloc(sizeof(*dev->channels) * dev->num_channels);
|
||||
|
||||
for (i = 0; i < dev->num_channels; i++) {
|
||||
dev->channels[i].num = init_param->channels[i].num;
|
||||
dev->channels[i].disable = init_param->channels[i].disable;
|
||||
dev->channels[i].divider = init_param->channels[i].divider;
|
||||
dev->channels[i].driver_mode =
|
||||
init_param->channels[i].driver_mode;
|
||||
dev->channels[i].high_performance_mode_dis =
|
||||
init_param->channels[i].high_performance_mode_dis;
|
||||
dev->channels[i].start_up_mode_dynamic_enable =
|
||||
init_param->channels[i].start_up_mode_dynamic_enable;
|
||||
dev->channels[i].dynamic_driver_enable =
|
||||
init_param->channels[i].dynamic_driver_enable;
|
||||
dev->channels[i].output_control0_rb4_enable =
|
||||
init_param->channels[i].output_control0_rb4_enable;
|
||||
dev->channels[i].force_mute_enable =
|
||||
init_param->channels[i].force_mute_enable;
|
||||
dev->channels[i].driver_impedance =
|
||||
init_param->channels[i].driver_impedance;
|
||||
dev->channels[i].coarse_delay =
|
||||
init_param->channels[i].coarse_delay;
|
||||
dev->channels[i].fine_delay =
|
||||
init_param->channels[i].fine_delay;
|
||||
dev->channels[i].out_mux_mode =
|
||||
init_param->channels[i].out_mux_mode;
|
||||
}
|
||||
|
||||
*device = dev;
|
||||
|
||||
if (!dev->is_hmc7043)
|
||||
return hmc7044_setup(dev);
|
||||
else
|
||||
return hmc7043_setup(dev);
|
||||
}
|
||||
|
||||
/**
|
||||
* Remove the device - release resources.
|
||||
* @param device - The device structure.
|
||||
* @return SUCCESS in case of success, negative error code otherwise.
|
||||
*/
|
||||
int32_t hmc7044_remove(struct hmc7044_dev *device)
|
||||
{
|
||||
int32_t ret;
|
||||
|
||||
ret = spi_remove(device->spi_desc);
|
||||
free(device->channels);
|
||||
free(device);
|
||||
|
||||
return ret;
|
||||
}
|
||||
+276
@@ -0,0 +1,276 @@
|
||||
/***************************************************************************//**
|
||||
* @file hmc7044.h
|
||||
* @brief Header file of HMC7044, HMC7043 Driver.
|
||||
* @author DBogdan (dragos.bogdan@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2018-2020(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
#ifndef HMC7044_H_
|
||||
#define HMC7044_H_
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include "../../../include/delay.h"
|
||||
#include "../../../include/spi.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/*************************** Types Declarations *******************************/
|
||||
/******************************************************************************/
|
||||
// Enum to select SYNC pin configuration with respect to PLL2 (0x0005)
|
||||
typedef enum
|
||||
{
|
||||
SYNC_DISABLED = 0,
|
||||
SYNC_MULTICHIP = 1,
|
||||
SYNC_PULSE_GEN = 2,
|
||||
SYNC_ALARM = 3
|
||||
} hmc7044SyncPinModeSelect_t;
|
||||
|
||||
// Enum to select input buffer mode (0x000A, 0x000B, 0x000C, 0x000D, 0x000E)
|
||||
typedef enum
|
||||
{
|
||||
BUFFER_ENABLE = (1) << 0,
|
||||
BUFFER_DISABLE = (0) << 0,
|
||||
ENABLE_INTERNAL_TERM = (1) << 1,
|
||||
ENABLE_AC_COUPLE = (1) << 2,
|
||||
ENABLE_LVPECL = (1) << 3,
|
||||
ENABLE_HIGH_Z = (1) << 4
|
||||
} hmc7044InputBufferMode_t;
|
||||
|
||||
// Enum to select output driver mode (0x003A, 0x003B, 0x00D0, 0x00DA, 0x00E4,
|
||||
// 0x00EE, 0x00F8, 0x0102, 0x010C, 0x0116, 0x0120, 0x012A, 0x0134, 0x013E,
|
||||
// 0x0148, 0x0152)
|
||||
typedef enum
|
||||
{
|
||||
CML = 0,
|
||||
LVPECL = 1,
|
||||
LVDS = 2,
|
||||
CMOS = 3
|
||||
} hmc7044DriverMode_t;
|
||||
|
||||
// Enum to select the GPIx functionality. (0x0046, 0x0047, 0x0048, 0x0049)
|
||||
typedef enum
|
||||
{
|
||||
GPI_ENABLE = (1) << 0,
|
||||
GPI_DISABLE = (0) << 0,
|
||||
FORCE_PLL1_HOLDOVER = (0x01) << 1 | GPI_ENABLE,
|
||||
SELECT_PLL1_REF_BIT1 = (0x02) << 1 | GPI_ENABLE,
|
||||
SELECT_PLL1_REF_BIT2 = (0x03) << 1 | GPI_ENABLE,
|
||||
CHIP_SLEEP_MODE = (0x04) << 1 | GPI_ENABLE,
|
||||
MUTE_REQUSET = (0x05) << 1 | GPI_ENABLE,
|
||||
SELECT_INTERNAL_VCO_TYPE = (0x06) << 1 | GPI_ENABLE,
|
||||
SELECT_HI_PERF_MODE = (0x07) << 1 | GPI_ENABLE,
|
||||
PULSE_GEN_REQUSET = (0x08) << 1 | GPI_ENABLE,
|
||||
RESEED_REQUEST = (0x09) << 1 | GPI_ENABLE,
|
||||
RESTART_REQUSET = (0x0A) << 1 | GPI_ENABLE,
|
||||
FORCE_FANOUT_MODE = (0x0B) << 1 | GPI_ENABLE,
|
||||
SLIP_REQUEST = (0x0D) << 1 | GPI_ENABLE,
|
||||
} hmc7044GPIControl_t;
|
||||
|
||||
// Enum to select the GPOx functionality. (0x0050, 0x0051, 0x0052, 0x0053)
|
||||
typedef enum
|
||||
{
|
||||
GPO_ENABLE = (1) << 0,
|
||||
GPO_DISABLE = (0) << 0,
|
||||
GPO_CMOS_MODE = (1) << 1,
|
||||
GPO_OPEN_DRAIN_MODE = (0) << 1,
|
||||
ALARM_SIGNAL = (0x00) << 3 | GPO_ENABLE,
|
||||
SPI_SDATA = (0x01) << 3 | GPO_ENABLE,
|
||||
CLKIN3_SIGNAL_LOSS = (0x02) << 3 | GPO_ENABLE,
|
||||
CLKIN2_SIGNAL_LOSS = (0x03) << 3 | GPO_ENABLE,
|
||||
CLKIN1_SIGNAL_LOSS = (0x04) << 3 | GPO_ENABLE,
|
||||
CLKIN0_SIGNAL_LOSS = (0x05) << 3 | GPO_ENABLE,
|
||||
PLL1_HOLDOVER_ENABLE = (0x06) << 3 | GPO_ENABLE,
|
||||
PLL1_LOCK_DETECT = (0x07) << 3 | GPO_ENABLE,
|
||||
PLL1_ACQUIRING_LOCK = (0x08) << 3 | GPO_ENABLE,
|
||||
PLL1_NEAR_CLOCK_ACQ_STAT = (0x09) << 3 | GPO_ENABLE,
|
||||
PLL2_LOCK_DETECT = (0x0A) << 3 | GPO_ENABLE,
|
||||
PLL2_SYSREF_SYNC = (0x0B) << 3 | GPO_ENABLE,
|
||||
CLOCK_OUTPUT_PHASE_STAT = (0x0C) << 3 | GPO_ENABLE,
|
||||
PLL1_PLL2_LOCKED = (0x0D) << 3 | GPO_ENABLE,
|
||||
SYNC_REQUSRT_STAT = (0x0E) << 3 | GPO_ENABLE,
|
||||
PLL1_ACTIVE_CLKIN0 = (0x0F) << 3 | GPO_ENABLE,
|
||||
PLL1_ACTIVE_CLKIN1 = (0x10) << 3 | GPO_ENABLE,
|
||||
PLL1_HOLDOVER_IN_RANGE_STAT = (0x11) << 3 | GPO_ENABLE,
|
||||
PLL1_HOLDOVER_IN_STAT = (0x12) << 3 | GPO_ENABLE,
|
||||
PLL1_VCXO_STAT = (0x13) << 3 | GPO_ENABLE,
|
||||
PLL1_ACTIVE_CLKINx_STAT = (0x14) << 3 | GPO_ENABLE,
|
||||
PLL1_FSM_BIT0 = (0x15) << 3 | GPO_ENABLE,
|
||||
PLL1_FSM_BIT1 = (0x16) << 3 | GPO_ENABLE,
|
||||
PLL1_FSM_BIT2 = (0x17) << 3 | GPO_ENABLE,
|
||||
PLL1_HOLDOVER_EXIT_PHASE_BIT0 = (0x18) << 3 | GPO_ENABLE,
|
||||
PLL1_HOLDOVER_EXIT_PHASE_BIT1 = (0x19) << 3 | GPO_ENABLE,
|
||||
CHANNEL_OUTPUT_FSM_BUSY = (0x1A) << 3 | GPO_ENABLE,
|
||||
SYSREF_FSM_STAT_BIT0 = (0x1B) << 3 | GPO_ENABLE,
|
||||
SYSREF_FSM_STAT_BIT1 = (0x1C) << 3 | GPO_ENABLE,
|
||||
SYSREF_FSM_STAT_BIT2 = (0x1D) << 3 | GPO_ENABLE,
|
||||
SYSREF_FSM_STAT_BIT3 = (0x1E) << 3 | GPO_ENABLE,
|
||||
FORCE_LOGIC_1 = (0x1F) << 3 | GPO_ENABLE,
|
||||
FORCE_LOGIC_0 = (0x20) << 3 | GPO_ENABLE,
|
||||
PLL1_HOLDOVER_AVG_VALUE_BIT0 = (0x27) << 3 | GPO_ENABLE,
|
||||
PLL1_HOLDOVER_AVG_VALUE_BIT1 = (0x28) << 3 | GPO_ENABLE,
|
||||
PLL1_HOLDOVER_AVG_VALUE_BIT2 = (0x29) << 3 | GPO_ENABLE,
|
||||
PLL1_HOLDOVER_AVG_VALUE_BIT3 = (0x2A) << 3 | GPO_ENABLE,
|
||||
PLL1_HOLDOVER_CURR_VALUE_BIT0 = (0x2B) << 3 | GPO_ENABLE,
|
||||
PLL1_HOLDOVER_CURR_VALUE_BIT1 = (0x2C) << 3 | GPO_ENABLE,
|
||||
PLL1_HOLDOVER_CURR_VALUE_BIT2 = (0x2D) << 3 | GPO_ENABLE,
|
||||
PLL1_HOLDOVER_CURR_VALUE_BIT3 = (0x2E) << 3 | GPO_ENABLE
|
||||
} hmc7044GPOControl_t;
|
||||
|
||||
// Enum to select output channel (0x00CF, 0x00D9, 0x00E3, 0x00ED, 0x00F7,
|
||||
// 0x0101, 0x010B, 0x0115, 0x011F, 0x0129, 0x0133, 0x013D, 0x0147, 0x0151
|
||||
typedef enum
|
||||
{
|
||||
CHANNEL_DIV = 0,
|
||||
ANALOG_DELAY = 1,
|
||||
OTHER_CHANNEL = 2,
|
||||
VCO_CLOCK = 3
|
||||
} hmc7044OutputMuxSelect_t;
|
||||
|
||||
// Enum to select output driver impedance selection for CML mode (0x00D0,
|
||||
// 0x00DA, 0x00E4, 0x00EE, 0x00F8, 0x0102, 0x010C, 0x0116, 0x0120, 0x012A,
|
||||
// 0x0134, 0x013E, 0x0148, 0x0152)
|
||||
typedef enum
|
||||
{
|
||||
INTERNAL_RES_DISABLE = 0,
|
||||
INTERNAL_100OHM_PER_PIN = 1,
|
||||
// INTERNAL_RES_RESERVED = 2,
|
||||
INTERNAL_50OHM_PER_PIN = 3
|
||||
} hmc7044DriverImpedance_t;
|
||||
|
||||
// Enum to select pulse generator mode (0x005A)
|
||||
typedef enum
|
||||
{
|
||||
PULSE_LEVEL_SENSITIVE = 0,
|
||||
PULSE_ONE = 1,
|
||||
PULSE_TWO = 2,
|
||||
PULSE_FOUR = 3,
|
||||
PULSE_EIGHT = 4,
|
||||
PULSE_SIXTEEN = 5,
|
||||
// PULSE_SIXTEEN = 6,
|
||||
PULSE_CONTINOUS = 7
|
||||
} hmc7044SyncPulseGenControl_t;
|
||||
|
||||
struct hmc7044_chan_spec {
|
||||
unsigned int num;
|
||||
bool disable;
|
||||
bool high_performance_mode_dis;
|
||||
bool start_up_mode_dynamic_enable;
|
||||
bool dynamic_driver_enable;
|
||||
bool output_control0_rb4_enable;
|
||||
bool force_mute_enable;
|
||||
unsigned int divider;
|
||||
unsigned int coarse_delay;
|
||||
unsigned int fine_delay;
|
||||
hmc7044DriverMode_t driver_mode;
|
||||
hmc7044DriverImpedance_t driver_impedance;
|
||||
hmc7044OutputMuxSelect_t out_mux_mode;
|
||||
};
|
||||
|
||||
struct hmc7044_config {
|
||||
uint16_t addr;
|
||||
uint8_t value;
|
||||
};
|
||||
|
||||
struct hmc7044_dev {
|
||||
spi_desc *spi_desc;
|
||||
bool is_hmc7043;
|
||||
uint32_t clkin_freq[4];
|
||||
uint32_t clkin_freq_ccf[4];
|
||||
uint32_t vcxo_freq;
|
||||
uint32_t pll1_pfd;
|
||||
uint32_t pll2_freq;
|
||||
uint32_t pll1_loop_bw;
|
||||
uint32_t sysref_timer_div;
|
||||
unsigned int pll1_ref_prio_ctrl;
|
||||
bool clkin0_rfsync_en;
|
||||
bool clkin1_vcoin_en;
|
||||
bool high_performance_mode_clock_dist_en;
|
||||
bool rf_reseeder_en;
|
||||
hmc7044SyncPinModeSelect_t sync_pin_mode;
|
||||
hmc7044SyncPulseGenControl_t pulse_gen_mode;
|
||||
uint32_t in_buf_mode[5];
|
||||
uint32_t gpi_ctrl[4];
|
||||
uint32_t gpo_ctrl[4];
|
||||
uint32_t num_channels;
|
||||
struct hmc7044_chan_spec *channels;
|
||||
};
|
||||
|
||||
struct hmc7044_init_param {
|
||||
spi_init_param *spi_init;
|
||||
bool is_hmc7043;
|
||||
uint32_t clkin_freq[4];
|
||||
uint32_t clkin_freq_ccf[4];
|
||||
uint32_t vcxo_freq;
|
||||
uint32_t pll1_pfd;
|
||||
uint32_t pll2_freq;
|
||||
uint32_t pll1_loop_bw;
|
||||
uint32_t sysref_timer_div;
|
||||
unsigned int pll1_ref_prio_ctrl;
|
||||
bool clkin0_rfsync_en;
|
||||
bool clkin1_vcoin_en;
|
||||
bool high_performance_mode_clock_dist_en;
|
||||
bool rf_reseeder_disable;
|
||||
hmc7044SyncPinModeSelect_t sync_pin_mode;
|
||||
hmc7044SyncPulseGenControl_t pulse_gen_mode;
|
||||
uint32_t in_buf_mode[5];
|
||||
uint32_t gpi_ctrl[4];
|
||||
uint32_t gpo_ctrl[4];
|
||||
uint32_t num_channels;
|
||||
struct hmc7044_chan_spec *channels;
|
||||
};
|
||||
|
||||
/******************************************************************************/
|
||||
/************************ Functions Declarations ******************************/
|
||||
/******************************************************************************/
|
||||
/* Initialize the device. */
|
||||
int32_t hmc7044_reg_init(struct hmc7044_dev **device,
|
||||
const struct hmc7044_init_param *init_param);
|
||||
int32_t hmc7044_init(struct hmc7044_dev **device,
|
||||
const struct hmc7044_init_param *init_param);
|
||||
/* Remove the device. */
|
||||
int32_t hmc7044_remove(struct hmc7044_dev *device);
|
||||
int32_t hmc7044_write(struct hmc7044_dev *dev,
|
||||
uint16_t reg, uint8_t val);
|
||||
int32_t hmc7044_read(struct hmc7044_dev *dev, uint16_t reg, uint8_t *val);
|
||||
int32_t hmc7044_clk_recalc_rate(struct hmc7044_dev *dev, uint32_t chan_num,
|
||||
uint64_t *rate);
|
||||
int32_t hmc7044_clk_round_rate(struct hmc7044_dev *dev, uint32_t rate,
|
||||
uint64_t *rounded_rate);
|
||||
int32_t hmc7044_clk_set_rate(struct hmc7044_dev *dev, uint32_t chan_num,
|
||||
uint64_t rate);
|
||||
|
||||
#endif // HMC7044_H_
|
||||
+79
@@ -0,0 +1,79 @@
|
||||
/***************************************************************************//**
|
||||
* @file xilinx/axi_io.c
|
||||
* @brief Implementation of Xilinx AXI IO.
|
||||
* @author Antoniu Miclaus (antoniu.miclaus@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2019(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
|
||||
#include <xil_io.h>
|
||||
#include "../../include/error.h"
|
||||
#include "../../include/axi_io.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/************************ Functions Definitions *******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief AXI IO Xilinx specific read function.
|
||||
* @param base - Base address
|
||||
* @param offset - Address offset
|
||||
* @param data - variable where returned data is stored
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t axi_io_read(uint32_t base, uint32_t offset, uint32_t *data)
|
||||
{
|
||||
*data = Xil_In32(base + offset);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief AXI IO Xilinx specific write function.
|
||||
* @param base - Base address
|
||||
* @param offset - Address offset
|
||||
* @param data - data to be written.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t axi_io_write(uint32_t base, uint32_t offset, uint32_t data)
|
||||
{
|
||||
Xil_Out32(base + offset, data);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
+77
@@ -0,0 +1,77 @@
|
||||
/***************************************************************************//**
|
||||
* @file xilinx/delay.c
|
||||
* @brief Implementation of Xilinx Delay Functions.
|
||||
* @author Antoniu Miclaus (antoniu.miclaus@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2019(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
|
||||
#include "../../include/delay.h"
|
||||
#include <sleep.h>
|
||||
|
||||
/******************************************************************************/
|
||||
/************************ Functions Definitions *******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief Generate microseconds delay.
|
||||
* @param usecs - Delay in microseconds.
|
||||
* @return None.
|
||||
*/
|
||||
void udelay(uint32_t usecs)
|
||||
{
|
||||
#ifdef _XPARAMETERS_PS_H_
|
||||
usleep(usecs);
|
||||
#else
|
||||
usleep(usecs / 20); // FIXME
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Generate miliseconds delay.
|
||||
* @param msecs - Delay in miliseconds.
|
||||
* @return None.
|
||||
*/
|
||||
void mdelay(uint32_t msecs)
|
||||
{
|
||||
#ifdef _XPARAMETERS_PS_H_
|
||||
usleep(msecs * 1000);
|
||||
#else
|
||||
usleep(msecs * 50); // FIXME
|
||||
#endif
|
||||
}
|
||||
+95
@@ -0,0 +1,95 @@
|
||||
/*******************************************************************************
|
||||
* @file xilinx/gpio_extra.h
|
||||
* @brief Header containing extra types used in the gpio driver
|
||||
* @author scuciurean (sergiu.cuciurean@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2019(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef GPIO_EXTRA_H_
|
||||
#define GPIO_EXTRA_H_
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
/******************************************************************************/
|
||||
/*************************** Types Declarations *******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @enum xil_gpio_type
|
||||
* @brief Xilinx platform architecture sections
|
||||
*/
|
||||
typedef enum xil_gpio_type {
|
||||
/** Programmable Logic */
|
||||
GPIO_PL,
|
||||
/** Processing System */
|
||||
GPIO_PS
|
||||
} xil_gpio_type;
|
||||
|
||||
/**
|
||||
* @struct xil_gpio_init_param
|
||||
* @brief Structure holding the initialization parameters for Xilinx platform
|
||||
* specific GPIO parameters.
|
||||
*/
|
||||
typedef struct xil_gpio_init_param {
|
||||
/** Xilinx architecture */
|
||||
enum xil_gpio_type type;
|
||||
/** Device ID */
|
||||
uint32_t device_id;
|
||||
} xil_gpio_init_param;
|
||||
|
||||
/**
|
||||
* @struct xil_gpio_desc
|
||||
* @brief Xilinx platform specific GPIO descriptor
|
||||
*/
|
||||
typedef struct xil_gpio_desc {
|
||||
/** Xilinx architecture */
|
||||
enum xil_gpio_type type;
|
||||
/** Xilinx GPIO configuration */
|
||||
void *config;
|
||||
/** Xilinx GPIO Instance */
|
||||
void *instance;
|
||||
} xil_gpio_desc;
|
||||
|
||||
/**
|
||||
* @brief Xilinx platform specific gpio platform ops structure
|
||||
*/
|
||||
extern const struct gpio_platform_ops xil_gpio_ops;
|
||||
|
||||
#endif
|
||||
+91
@@ -0,0 +1,91 @@
|
||||
/*******************************************************************************
|
||||
* @file irq_extra.h
|
||||
* @brief Header containing types used in the irq driver.
|
||||
* @author Cristian Pop (cristian.pop@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2019(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef IRQ_EXTRA_H_
|
||||
#define IRQ_EXTRA_H_
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "../../include/irq.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/*************************** Types Declarations *******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @enum xil_irq_type
|
||||
* @brief Xilinx platform architecture sections
|
||||
*/
|
||||
enum xil_irq_type {
|
||||
/** Programmable Logic */
|
||||
IRQ_PL,
|
||||
/** Processing System */
|
||||
IRQ_PS
|
||||
};
|
||||
|
||||
/**
|
||||
* @struct xil_irq_init_param
|
||||
* @brief Structure holding the initialization parameters for Xilinx platform
|
||||
* specific IRQ parameters.
|
||||
*/
|
||||
struct xil_irq_init_param {
|
||||
/** Xilinx architecture */
|
||||
enum xil_irq_type type;
|
||||
};
|
||||
|
||||
/**
|
||||
* @struct xil_irq_desc
|
||||
* @brief Xilinx platform specific IRQ descriptor
|
||||
*/
|
||||
struct xil_irq_desc {
|
||||
/** Xilinx architecture */
|
||||
enum xil_irq_type type;
|
||||
/** Xilinx IRQ Instance */
|
||||
void *instance;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Xilinx specific IRQ platform ops structure
|
||||
*/
|
||||
extern const struct irq_platform_ops xil_irq_ops;
|
||||
|
||||
#endif
|
||||
+115
@@ -0,0 +1,115 @@
|
||||
/*******************************************************************************
|
||||
* @file xilinx/spi_extra.h
|
||||
* @brief Header containing extra types used in the spi driver.
|
||||
* @author scuciurean (sergiu.cuciurean@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2019(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
#ifndef SPI_EXTRA_H_
|
||||
#define SPI_EXTRA_H_
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "../../include/spi.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/********************** Macros and Constants Definitions **********************/
|
||||
/******************************************************************************/
|
||||
|
||||
#define SPI_CS_DECODE 0x01
|
||||
#define SPI_DEASSERT_CURRENT_SS 0x0F
|
||||
|
||||
/******************************************************************************/
|
||||
/*************************** Types Declarations *******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @enum xil_spi_type
|
||||
* @brief Xilinx platform architecture sections
|
||||
*/
|
||||
enum xil_spi_type {
|
||||
/** Programmable Logic */
|
||||
SPI_PL,
|
||||
/** Processing System */
|
||||
SPI_PS,
|
||||
/** SPI Engine */
|
||||
SPI_ENGINE
|
||||
};
|
||||
|
||||
/**
|
||||
* @struct xil_spi_init_param
|
||||
* @brief Structure holding the initialization parameters for Xilinx platform
|
||||
* specific SPI parameters when using xil_spi_ops.
|
||||
*/
|
||||
typedef struct xil_spi_init_param {
|
||||
/** Xilinx architecture */
|
||||
enum xil_spi_type type;
|
||||
/** SPI flags */
|
||||
uint32_t flags;
|
||||
} xil_spi_init_param;
|
||||
|
||||
/**
|
||||
* @struct xil_spi_desc
|
||||
* @brief Xilinx platform specific SPI descriptor
|
||||
*/
|
||||
typedef struct xil_spi_desc {
|
||||
/** Xilinx architecture */
|
||||
enum xil_spi_type type;
|
||||
/** SPI flags */
|
||||
uint32_t flags;
|
||||
/** SPI configuration */
|
||||
void *config;
|
||||
/** SPI instance */
|
||||
void *instance;
|
||||
} xil_spi_desc;
|
||||
|
||||
/**
|
||||
* @brief SPI engine platform ops structure
|
||||
*/
|
||||
extern const struct spi_platform_ops spi_eng_platform_ops;
|
||||
|
||||
/**
|
||||
* @brief Xilinx specific SPI platform ops structure
|
||||
*/
|
||||
extern const struct spi_platform_ops xil_spi_ops;
|
||||
|
||||
/**
|
||||
* @brief Xilinx SPI PS register functions. No extra param needed
|
||||
*/
|
||||
extern const struct spi_platform_ops xil_spi_reg_ops_pl;
|
||||
|
||||
#endif // SPI_EXTRA_H_
|
||||
+107
@@ -0,0 +1,107 @@
|
||||
/*******************************************************************************
|
||||
* @file xilinx/uart_extra.h
|
||||
* @brief Header containing types used in the uart driver.
|
||||
* @author Cristian Pop (cristian.pop@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2019(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef UART_EXTRA_H_
|
||||
#define UART_EXTRA_H_
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/********************** Macros and Constants Definitions **********************/
|
||||
/******************************************************************************/
|
||||
|
||||
#define UART_BUFF_LENGTH 256
|
||||
|
||||
/******************************************************************************/
|
||||
/*************************** Types Declarations *******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @enum xil_uart_type
|
||||
* @brief Xilinx platform architecture sections
|
||||
*/
|
||||
enum xil_uart_type {
|
||||
/** Programmable Logic */
|
||||
UART_PL,
|
||||
/** Processing System */
|
||||
UART_PS
|
||||
};
|
||||
|
||||
/**
|
||||
* @struct xil_uart_init_param
|
||||
* @brief Structure holding the initialization parameters for Xilinx platform
|
||||
* specific UART parameters.
|
||||
*/
|
||||
struct xil_uart_init_param {
|
||||
/** Xilinx architecture */
|
||||
enum xil_uart_type type;
|
||||
/** Interrupt Request ID */
|
||||
uint32_t irq_id;
|
||||
/** Interrupt Request Descriptor */
|
||||
struct irq_ctrl_desc *irq_desc;
|
||||
};
|
||||
|
||||
/**
|
||||
* @struct xil_uart_desc
|
||||
* @brief Xilinx platform specific UART descriptor
|
||||
*/
|
||||
struct xil_uart_desc {
|
||||
/** Xilinx architecture */
|
||||
enum xil_uart_type type;
|
||||
/** Interrupt Request ID */
|
||||
uint32_t irq_id;
|
||||
/** Interrupt Request Descriptor */
|
||||
struct irq_ctrl_desc *irq_desc;
|
||||
/** FIFO */
|
||||
struct fifo_element *fifo;
|
||||
/** FIFO read offset */
|
||||
uint32_t fifo_read_offset;
|
||||
/** UART Buffer */
|
||||
char buff[UART_BUFF_LENGTH];
|
||||
/** Number of bytes received */
|
||||
uint32_t bytes_received;
|
||||
/** Total number of errors */
|
||||
uint32_t total_error_count;
|
||||
/** UART Instance */
|
||||
void *instance;
|
||||
};
|
||||
|
||||
#endif
|
||||
+464
@@ -0,0 +1,464 @@
|
||||
/***************************************************************************//**
|
||||
* @file xilinx/xilinx_gpio.c
|
||||
* @brief Implementation of Xilinx GPIO Generic Driver.
|
||||
* @author Antoniu Miclaus (antoniu.miclaus@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2019(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
|
||||
#include <stdlib.h>
|
||||
|
||||
#include <xparameters.h>
|
||||
#ifdef XPAR_XGPIO_NUM_INSTANCES
|
||||
#include <xgpio.h>
|
||||
#endif
|
||||
#ifdef XPAR_XGPIOPS_NUM_INSTANCES
|
||||
#include <xgpiops.h>
|
||||
#endif
|
||||
|
||||
#include "gpio_extra.h"
|
||||
#include "../../include/error.h"
|
||||
#include "../../include/gpio.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/************************ Functions Definitions *******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief Prepare the GPIO decriptor.
|
||||
* @param desc - The GPIO descriptor.
|
||||
* @param param - The structure that contains the GPIO parameters.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t _gpio_init(struct gpio_desc *desc,
|
||||
const struct gpio_init_param *param)
|
||||
{
|
||||
int32_t ret;
|
||||
struct xil_gpio_desc *xdesc;
|
||||
struct xil_gpio_init_param *xinit;
|
||||
|
||||
ret = FAILURE;
|
||||
|
||||
xdesc = desc->extra;
|
||||
xinit = param->extra;
|
||||
|
||||
xdesc->type = xinit->type;
|
||||
desc->number = param->number;
|
||||
|
||||
switch (xinit->type) {
|
||||
case GPIO_PL:
|
||||
#ifdef XGPIO_H
|
||||
xdesc->instance = (XGpio *)malloc(sizeof(XGpio));
|
||||
if(!xdesc->instance)
|
||||
goto pl_error;
|
||||
|
||||
xdesc->config = XGpio_LookupConfig(xinit->device_id);
|
||||
if(xdesc->config == NULL)
|
||||
goto pl_error;
|
||||
|
||||
ret = XGpio_CfgInitialize(xdesc->instance,
|
||||
xdesc->config,
|
||||
((XGpio_Config*)xdesc->config)
|
||||
->BaseAddress);
|
||||
if(ret < 0)
|
||||
goto pl_error;
|
||||
|
||||
break;
|
||||
pl_error:
|
||||
free(xdesc->instance);
|
||||
#endif
|
||||
goto error;
|
||||
case GPIO_PS:
|
||||
#ifdef XGPIOPS_H
|
||||
xdesc->instance = (XGpioPs *)malloc(sizeof(XGpioPs));
|
||||
if(!xdesc->instance)
|
||||
goto ps_error;
|
||||
|
||||
xdesc->config = XGpioPs_LookupConfig(xinit->device_id);
|
||||
if(xdesc->config == NULL)
|
||||
goto ps_error;
|
||||
|
||||
ret = XGpioPs_CfgInitialize(xdesc->instance,
|
||||
xdesc->config,
|
||||
((XGpioPs_Config*)xdesc->config)->BaseAddr);
|
||||
if(ret < 0)
|
||||
goto ps_error;
|
||||
break;
|
||||
ps_error:
|
||||
free(xdesc->instance);
|
||||
#endif
|
||||
goto error;
|
||||
error:
|
||||
default:
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Obtain the GPIO decriptor.
|
||||
* @param desc - The GPIO descriptor.
|
||||
* @param param - GPIO initialization parameters
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t xil_gpio_get(struct gpio_desc **desc,
|
||||
const struct gpio_init_param *param)
|
||||
{
|
||||
struct gpio_desc *descriptor;
|
||||
struct xil_gpio_desc *extra;
|
||||
int32_t ret;
|
||||
|
||||
descriptor = (struct gpio_desc *)malloc(sizeof(*descriptor));
|
||||
extra = (struct xil_gpio_desc*)malloc(sizeof(*extra));
|
||||
|
||||
if (!descriptor || !extra)
|
||||
return FAILURE;
|
||||
|
||||
descriptor->extra = extra;
|
||||
ret = _gpio_init(descriptor, param);
|
||||
|
||||
if(ret != SUCCESS)
|
||||
goto error;
|
||||
|
||||
*desc = descriptor;
|
||||
|
||||
return SUCCESS;
|
||||
error:
|
||||
free(extra);
|
||||
free(descriptor);
|
||||
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the value of an optional GPIO.
|
||||
* @param desc - The GPIO descriptor.
|
||||
* @param param - GPIO Initialization parameters.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t xil_gpio_get_optional(struct gpio_desc **desc,
|
||||
const struct gpio_init_param *param)
|
||||
{
|
||||
if(param == NULL) {
|
||||
*desc = NULL;
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
return xil_gpio_get(desc, param);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Free the resources allocated by gpio_get().
|
||||
* @param desc - The GPIO descriptor.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t xil_gpio_remove(struct gpio_desc *desc)
|
||||
{
|
||||
if (desc != NULL) {
|
||||
free(((xil_gpio_desc *)(desc->extra))->instance);
|
||||
free(desc->extra);
|
||||
free(desc);
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the input direction of the specified GPIO.
|
||||
* @param desc - The GPIO descriptor.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t xil_gpio_direction_input(struct gpio_desc *desc)
|
||||
{
|
||||
struct xil_gpio_desc *extra;
|
||||
#ifdef XGPIO_H
|
||||
uint8_t pin = desc->number;
|
||||
uint32_t channel = 1;
|
||||
uint32_t config = 0;
|
||||
#endif
|
||||
extra = desc->extra;
|
||||
|
||||
switch (extra->type) {
|
||||
case GPIO_PL:
|
||||
#ifdef XGPIO_H
|
||||
/* We assume that pin 32 is the first pin from channel 2 */
|
||||
if (pin >= 32) {
|
||||
channel = 2;
|
||||
pin -= 32;
|
||||
}
|
||||
|
||||
config = XGpio_GetDataDirection((XGpio *)extra->instance,
|
||||
channel);
|
||||
config |= (1 << pin);
|
||||
XGpio_SetDataDirection((XGpio *)extra->instance,
|
||||
channel,
|
||||
config);
|
||||
#endif
|
||||
break;
|
||||
case GPIO_PS:
|
||||
#ifdef XGPIOPS_H
|
||||
XGpioPs_SetDirectionPin(extra->instance,
|
||||
desc->number,
|
||||
GPIO_IN);
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the output direction of the specified GPIO.
|
||||
* @param desc - The GPIO descriptor.
|
||||
* @param value - The value.
|
||||
* Example: GPIO_HIGH
|
||||
* GPIO_LOW
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t xil_gpio_direction_output(struct gpio_desc *desc,
|
||||
uint8_t value)
|
||||
{
|
||||
struct xil_gpio_desc *extra;
|
||||
#ifdef XGPIO_H
|
||||
uint8_t pin = desc->number;
|
||||
uint8_t channel;
|
||||
uint32_t reg_val;
|
||||
#endif
|
||||
extra = desc->extra;
|
||||
|
||||
switch (extra->type) {
|
||||
case GPIO_PL:
|
||||
#ifdef XGPIO_H
|
||||
if (pin >= 32) {
|
||||
channel = 2;
|
||||
pin -= 32;
|
||||
} else
|
||||
channel = 1;
|
||||
|
||||
reg_val = XGpio_GetDataDirection(extra->instance,
|
||||
channel);
|
||||
reg_val &= ~(1 << pin);
|
||||
XGpio_SetDataDirection(extra->instance,
|
||||
channel,
|
||||
reg_val);
|
||||
reg_val = XGpio_DiscreteRead(extra->instance,
|
||||
channel);
|
||||
if(value)
|
||||
reg_val |= (1 << pin);
|
||||
else
|
||||
reg_val &= ~(1 << pin);
|
||||
XGpio_DiscreteWrite(extra->instance,
|
||||
channel,
|
||||
reg_val);
|
||||
#endif
|
||||
break;
|
||||
case GPIO_PS:
|
||||
#ifdef XGPIOPS_H
|
||||
XGpioPs_SetDirectionPin(extra->instance,
|
||||
desc->number,
|
||||
GPIO_OUT);
|
||||
XGpioPs_SetOutputEnablePin(extra->instance,
|
||||
desc->number,
|
||||
GPIO_OUT);
|
||||
XGpioPs_WritePin(extra->instance,
|
||||
desc->number,
|
||||
value);
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the direction of the specified GPIO.
|
||||
* @param desc - The GPIO descriptor.
|
||||
* @param direction - The direction.
|
||||
* Example: GPIO_OUT
|
||||
* GPIO_IN
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t xil_gpio_get_direction(struct gpio_desc *desc,
|
||||
uint8_t *direction)
|
||||
{
|
||||
if (!desc)
|
||||
return FAILURE;
|
||||
|
||||
struct xil_gpio_desc *extra;
|
||||
uint8_t pin = desc->number;
|
||||
|
||||
#ifdef XGPIO_H
|
||||
uint8_t channel;
|
||||
#endif
|
||||
extra = desc->extra;
|
||||
|
||||
switch (extra->type) {
|
||||
case GPIO_PL:
|
||||
#ifdef XGPIO_H
|
||||
if (pin >= 32) {
|
||||
channel = 2;
|
||||
pin -= 32;
|
||||
} else
|
||||
channel = 1;
|
||||
*direction = ((XGpio_GetDataDirection(extra->instance,
|
||||
channel) >> pin) & 0x1) ^ 0x1;
|
||||
#endif
|
||||
break;
|
||||
case GPIO_PS:
|
||||
#ifdef XGPIOPS_H
|
||||
*direction = XGpioPs_GetDirectionPin(extra->instance, pin);
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the value of the specified GPIO.
|
||||
* @param desc - The GPIO descriptor.
|
||||
* @param value - The value.
|
||||
* Example: GPIO_HIGH
|
||||
* GPIO_LOW
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t xil_gpio_set_value(struct gpio_desc *desc,
|
||||
uint8_t value)
|
||||
{
|
||||
struct xil_gpio_desc *extra;
|
||||
#ifdef XGPIO_H
|
||||
uint8_t pin = desc->number;
|
||||
uint8_t channel;
|
||||
uint32_t reg_val;
|
||||
#endif
|
||||
extra = desc->extra;
|
||||
|
||||
switch (extra->type) {
|
||||
case GPIO_PL:
|
||||
#ifdef XGPIO_H
|
||||
if (pin >= 32) {
|
||||
channel = 2;
|
||||
pin -= 32;
|
||||
} else
|
||||
channel = 1;
|
||||
|
||||
reg_val = XGpio_DiscreteRead(extra->instance, channel);
|
||||
if(value)
|
||||
reg_val |= (1 << pin);
|
||||
else
|
||||
reg_val &= ~(1 << pin);
|
||||
XGpio_DiscreteWrite(extra->instance, channel, reg_val);
|
||||
#endif
|
||||
break;
|
||||
case GPIO_PS:
|
||||
#ifdef XGPIOPS_H
|
||||
XGpioPs_WritePin(extra->instance, desc->number, value);
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the value of the specified GPIO.
|
||||
* @param desc - The GPIO descriptor.
|
||||
* @param value - The value.
|
||||
* Example: GPIO_HIGH
|
||||
* GPIO_LOW
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t xil_gpio_get_value(struct gpio_desc *desc,
|
||||
uint8_t *value)
|
||||
{
|
||||
if (!desc)
|
||||
return FAILURE;
|
||||
|
||||
struct xil_gpio_desc *extra;
|
||||
uint8_t pin = desc->number;
|
||||
|
||||
#ifdef XGPIO_H
|
||||
uint8_t channel;
|
||||
#endif
|
||||
extra = desc->extra;
|
||||
|
||||
switch (extra->type) {
|
||||
case GPIO_PL:
|
||||
#ifdef XGPIO_H
|
||||
if (pin >= 32) {
|
||||
channel = 2;
|
||||
pin -= 32;
|
||||
} else
|
||||
channel = 1;
|
||||
*value = (XGpio_DiscreteRead(extra->instance, channel) >> pin) & 0x01;
|
||||
#endif
|
||||
break;
|
||||
case GPIO_PS:
|
||||
#ifdef XGPIOPS_H
|
||||
*value = XGpioPs_ReadPin(extra->instance, pin);
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Xilinx platform specific GPIO platform ops structure
|
||||
*/
|
||||
const struct gpio_platform_ops xil_gpio_ops = {
|
||||
.gpio_ops_get = &xil_gpio_get,
|
||||
.gpio_ops_get_optional = &xil_gpio_get_optional,
|
||||
.gpio_ops_remove = &xil_gpio_remove,
|
||||
.gpio_ops_direction_input = &xil_gpio_direction_input,
|
||||
.gpio_ops_direction_output = &xil_gpio_direction_output,
|
||||
.gpio_ops_get_direction = &xil_gpio_get_direction,
|
||||
.gpio_ops_set_value = &xil_gpio_set_value,
|
||||
.gpio_ops_get_value = &xil_gpio_get_value,
|
||||
};
|
||||
+384
@@ -0,0 +1,384 @@
|
||||
/***************************************************************************//**
|
||||
* @file xilinx/xilinx_irq.c
|
||||
* @brief Implementation of Xilinx IRQ Generic Driver.
|
||||
* @author Cristian Pop (cristian.pop@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2019(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
|
||||
#include <xparameters.h>
|
||||
#include <stdlib.h>
|
||||
#include "irq_extra.h"
|
||||
#include "../../include/irq.h"
|
||||
#include "../../include/error.h"
|
||||
#ifdef XPAR_XSCUGIC_NUM_INSTANCES
|
||||
#include <xscugic.h>
|
||||
#endif
|
||||
#ifdef XPAR_XINTC_NUM_INSTANCES
|
||||
#include <xintc.h>
|
||||
#endif
|
||||
#ifdef XPAR_XTMRCTR_NUM_INSTANCES
|
||||
#include <xtmrctr.h>
|
||||
#endif
|
||||
|
||||
/******************************************************************************/
|
||||
/************************ Functions Definitions *******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief Initialize the IRQ interrupts.
|
||||
* @param desc - The IRQ controller descriptor.
|
||||
* @param param - The structure that contains the IRQ parameters.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t xil_irq_ctrl_init(struct irq_ctrl_desc **desc,
|
||||
const struct irq_init_param *param)
|
||||
{
|
||||
int32_t status;
|
||||
struct irq_ctrl_desc *descriptor;
|
||||
struct xil_irq_desc *xil_dev;
|
||||
#ifdef XSCUGIC_H
|
||||
void *config;
|
||||
#endif
|
||||
|
||||
descriptor = (struct irq_ctrl_desc *)calloc(1, sizeof *descriptor);
|
||||
if(!descriptor)
|
||||
return FAILURE;
|
||||
xil_dev = (struct xil_irq_desc *)calloc(1, sizeof *xil_dev);
|
||||
if(!xil_dev) {
|
||||
free(descriptor);
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
Xil_ExceptionInit();
|
||||
|
||||
descriptor->irq_ctrl_id = param->irq_ctrl_id;
|
||||
descriptor->extra = xil_dev;
|
||||
xil_dev->type = ((struct xil_irq_init_param *)param->extra)->type;
|
||||
|
||||
switch(xil_dev->type) {
|
||||
case IRQ_PS:
|
||||
#ifdef XSCUGIC_H
|
||||
xil_dev->instance = calloc(1, sizeof(XScuGic));
|
||||
if(!xil_dev->instance)
|
||||
goto error;
|
||||
|
||||
config = XScuGic_LookupConfig(descriptor->irq_ctrl_id);
|
||||
if(!config)
|
||||
goto ps_error;
|
||||
|
||||
status = XScuGic_CfgInitialize(xil_dev->instance, config,
|
||||
((XScuGic_Config *)config)->CpuBaseAddress);
|
||||
if (status != SUCCESS)
|
||||
goto ps_error;
|
||||
|
||||
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
|
||||
(Xil_ExceptionHandler)XScuGic_InterruptHandler,
|
||||
xil_dev->instance);
|
||||
|
||||
break;
|
||||
ps_error:
|
||||
free(xil_dev->instance);
|
||||
#endif
|
||||
goto error;
|
||||
case IRQ_PL:
|
||||
#ifdef XINTC_H
|
||||
xil_dev->instance = calloc(1, sizeof(XIntc));
|
||||
if(!xil_dev->instance)
|
||||
goto error;
|
||||
|
||||
status = XIntc_Initialize(xil_dev->instance, descriptor->irq_ctrl_id);
|
||||
if(status != SUCCESS)
|
||||
goto pl_error;
|
||||
|
||||
status = XIntc_Start(xil_dev->instance, XIN_REAL_MODE);
|
||||
if(status != SUCCESS)
|
||||
goto pl_error;
|
||||
|
||||
break;
|
||||
pl_error:
|
||||
free(xil_dev->instance);
|
||||
#endif
|
||||
goto error;
|
||||
default:
|
||||
goto error;
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
*desc = descriptor;
|
||||
|
||||
return SUCCESS;
|
||||
|
||||
error:
|
||||
free(xil_dev);
|
||||
free(descriptor);
|
||||
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable global interrupts.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t xil_irq_global_enable(struct irq_ctrl_desc *desc)
|
||||
{
|
||||
/* Enable interrupts */
|
||||
Xil_ExceptionEnable();
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable global interrupts.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t xil_irq_global_disable(struct irq_ctrl_desc *desc)
|
||||
{
|
||||
/* Disable interrupts */
|
||||
Xil_ExceptionDisable();
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable specific interrupt.
|
||||
* @param desc - The IRQ controller descriptor.
|
||||
* @param irq_id - Interrupt identifier.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t xil_irq_enable(struct irq_ctrl_desc *desc, uint32_t irq_id)
|
||||
{
|
||||
struct xil_irq_desc *xil_dev = desc->extra;
|
||||
|
||||
switch(xil_dev->type) {
|
||||
case IRQ_PS:
|
||||
#ifdef XSCUGIC_H
|
||||
XScuGic_Enable(xil_dev->instance, irq_id);
|
||||
#endif
|
||||
break;
|
||||
case IRQ_PL:
|
||||
#ifdef XINTC_H
|
||||
XIntc_Enable(xil_dev->instance, irq_id);
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable specific interrupt.
|
||||
* @param desc - The IRQ controller descriptor.
|
||||
* @param irq_id - Interrupt identifier.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t xil_irq_disable(struct irq_ctrl_desc *desc, uint32_t irq_id)
|
||||
{
|
||||
struct xil_irq_desc *xil_dev = desc->extra;
|
||||
|
||||
switch(xil_dev->type) {
|
||||
case IRQ_PS:
|
||||
#ifdef XSCUGIC_H
|
||||
XScuGic_Disable(xil_dev->instance, irq_id);
|
||||
#endif
|
||||
break;
|
||||
case IRQ_PL:
|
||||
#ifdef XINTC_H
|
||||
XIntc_Disable(xil_dev->instance, irq_id);
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Register a callback to handle the irq events.
|
||||
* @param desc - The IRQ controller descriptor.
|
||||
* @param irq_id - Interrupt identifier.
|
||||
* @param callback_desc - Callback descriptor
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t xil_irq_register_callback(struct irq_ctrl_desc *desc, uint32_t irq_id,
|
||||
struct callback_desc *callback_desc)
|
||||
{
|
||||
struct xil_irq_desc *xil_dev = desc->extra;
|
||||
|
||||
switch(xil_dev->type) {
|
||||
case IRQ_PS:
|
||||
#ifdef XSCUGIC_H
|
||||
return XScuGic_Connect(xil_dev->instance, irq_id,
|
||||
(Xil_InterruptHandler) callback_desc->callback,
|
||||
callback_desc->ctx);
|
||||
#endif
|
||||
break;
|
||||
case IRQ_PL:
|
||||
#ifdef XINTC_H
|
||||
if (irq_id == XPAR_AXI_INTC_AXI_TIMER_INTERRUPT_INTR) {
|
||||
int32_t ret;
|
||||
|
||||
ret = XIntc_Connect(xil_dev->instance, irq_id,
|
||||
XTmrCtr_InterruptHandler, callback_desc->config);
|
||||
if (IS_ERR_VALUE(ret))
|
||||
return FAILURE;
|
||||
XTmrCtr_SetHandler(callback_desc->config,
|
||||
(XTmrCtr_Handler)callback_desc->callback,
|
||||
callback_desc->ctx);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
return XIntc_Connect(xil_dev->instance, irq_id,
|
||||
(XInterruptHandler) callback_desc->callback,
|
||||
callback_desc->ctx);
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set interrupt trigger level.
|
||||
* @param desc - The IRQ controller descriptor.
|
||||
* @param irq_id - Interrupt identifier.
|
||||
* @param trig - New trigger level for the interrupt.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t xil_irq_trigger_level_set(struct irq_ctrl_desc *desc, uint32_t irq_id,
|
||||
enum irq_trig_level trig)
|
||||
{
|
||||
struct xil_irq_desc *xil_dev = desc->extra;
|
||||
|
||||
if(trig == IRQ_EDGE_BOTH)
|
||||
return -EINVAL;
|
||||
|
||||
switch(xil_dev->type) {
|
||||
case IRQ_PS:
|
||||
#ifdef XSCUGIC_H
|
||||
;
|
||||
uint8_t priority, trigger;
|
||||
|
||||
XScuGic_GetPriorityTriggerType(xil_dev->instance, irq_id, &priority,
|
||||
&trigger);
|
||||
trigger = trig;
|
||||
XScuGic_SetPriorityTriggerType(xil_dev->instance, irq_id, priority,
|
||||
trigger);
|
||||
|
||||
return SUCCESS;
|
||||
#endif
|
||||
break;
|
||||
case IRQ_PL:
|
||||
#ifdef XINTC_H
|
||||
/* Interrupt trigger determined in hardware. TODO: verify */
|
||||
return SUCCESS;
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Unregisters a generic IRQ handling function.
|
||||
* @param desc - The IRQ controller descriptor.
|
||||
* @param irq_id - Interrupt identifier.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t xil_irq_unregister(struct irq_ctrl_desc *desc, uint32_t irq_id)
|
||||
{
|
||||
struct xil_irq_desc *xil_dev = desc->extra;
|
||||
|
||||
switch(xil_dev->type) {
|
||||
case IRQ_PS:
|
||||
#ifdef XSCUGIC_H
|
||||
XScuGic_Disconnect(xil_dev->instance, irq_id);
|
||||
#endif
|
||||
break;
|
||||
case IRQ_PL:
|
||||
#ifdef XINTC_H
|
||||
XIntc_Disconnect(xil_dev->instance, irq_id);
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Free the resources allocated by irq_ctrl_init().
|
||||
* @param desc - The IRQ control descriptor.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t xil_irq_ctrl_remove(struct irq_ctrl_desc *desc)
|
||||
{
|
||||
struct xil_irq_desc *xil_dev = desc->extra;
|
||||
free(xil_dev->instance);
|
||||
free(desc->extra);
|
||||
free(desc);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Xilinx platform specific IRQ platform ops structure
|
||||
*/
|
||||
const struct irq_platform_ops xil_irq_ops = {
|
||||
.init = &xil_irq_ctrl_init,
|
||||
.register_callback = &xil_irq_register_callback,
|
||||
.unregister = &xil_irq_unregister,
|
||||
.global_enable = &xil_irq_global_enable,
|
||||
.global_disable = &xil_irq_global_disable,
|
||||
.trigger_level_set = &xil_irq_trigger_level_set,
|
||||
.enable = &xil_irq_enable,
|
||||
.disable = &xil_irq_disable,
|
||||
.remove = &xil_irq_ctrl_remove
|
||||
};
|
||||
+461
@@ -0,0 +1,461 @@
|
||||
/***************************************************************************//**
|
||||
* @file xilinx/xilinx_spi.c
|
||||
* @brief Implementation of Xilinx SPI Generic Driver.
|
||||
* @author Antoniu Miclaus (antoniu.miclaus@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2019(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
|
||||
#include <stdlib.h>
|
||||
|
||||
#include <xparameters.h>
|
||||
#ifdef XPAR_XSPI_NUM_INSTANCES
|
||||
#include <xspi.h>
|
||||
#endif
|
||||
#ifdef XPAR_XSPIPS_NUM_INSTANCES
|
||||
#include <xspips.h>
|
||||
#endif
|
||||
|
||||
#include "../../include/error.h"
|
||||
#include "../../include/spi.h"
|
||||
#include "spi_extra.h"
|
||||
|
||||
#if defined(PLATFORM_ZYNQ)
|
||||
#define SPI_CLK_FREQ_HZ(dev) (XPAR_PS7_SPI_ ## dev ## _SPI_CLK_FREQ_HZ)
|
||||
#define SPI_NUM_INSTANCES XPAR_XSPIPS_NUM_INSTANCES
|
||||
#elif defined(PLATFORM_ZYNQMP)
|
||||
#define SPI_CLK_FREQ_HZ(dev) (XPAR_PSU_SPI_ ## dev ## _SPI_CLK_FREQ_HZ)
|
||||
#define SPI_NUM_INSTANCES XPAR_XSPIPS_NUM_INSTANCES
|
||||
#else
|
||||
#define SPI_NUM_INSTANCES 0
|
||||
#endif
|
||||
|
||||
/******************************************************************************/
|
||||
/************************ Functions Definitions *******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief Initialize the hardware SPI peripherial
|
||||
*
|
||||
* @param xdesc Platform specific SPI descriptor
|
||||
* @param xinit Platform specific SPI init param
|
||||
* @return int32_t FAILURE if the device couldn't be found or configured
|
||||
*/
|
||||
static int32_t spi_init_pl(struct spi_desc *desc,
|
||||
const struct spi_init_param *param)
|
||||
{
|
||||
#ifdef XSPI_H
|
||||
int32_t ret;
|
||||
struct xil_spi_desc *xdesc;
|
||||
struct xil_spi_init_param *xinit;
|
||||
|
||||
xdesc = (xil_spi_desc*)malloc(sizeof(xil_spi_desc));
|
||||
if(!xdesc) {
|
||||
free(xdesc);
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
desc->extra = xdesc;
|
||||
xinit = param->extra;
|
||||
xdesc->type = xinit->type;
|
||||
xdesc->flags = xinit->flags;
|
||||
|
||||
xdesc->instance = (XSpi*)calloc(1, sizeof(XSpi));
|
||||
if(!xdesc->instance)
|
||||
goto pl_error;
|
||||
|
||||
xdesc->config = XSpi_LookupConfig(param->device_id);
|
||||
if(xdesc->config == NULL)
|
||||
goto pl_error;
|
||||
|
||||
ret = XSpi_CfgInitialize(xdesc->instance,
|
||||
xdesc->config,
|
||||
((XSpi_Config*)xdesc->config)
|
||||
->BaseAddress);
|
||||
if(ret != SUCCESS)
|
||||
goto pl_error;
|
||||
|
||||
ret = XSpi_Initialize(xdesc->instance, param->device_id);
|
||||
if (ret != SUCCESS)
|
||||
goto pl_error;
|
||||
|
||||
ret = XSpi_SetOptions(xdesc->instance,
|
||||
XSP_MASTER_OPTION |
|
||||
((desc->mode & SPI_CPOL) ?
|
||||
XSP_CLK_ACTIVE_LOW_OPTION : 0) |
|
||||
((desc->mode & SPI_CPHA) ?
|
||||
XSP_CLK_PHASE_1_OPTION : 0));
|
||||
if (ret != SUCCESS)
|
||||
goto pl_error;
|
||||
|
||||
ret = XSpi_Start(xdesc->instance);
|
||||
if (ret != SUCCESS)
|
||||
goto pl_error;
|
||||
|
||||
XSpi_IntrGlobalDisable((XSpi *)(xdesc->instance));
|
||||
|
||||
return SUCCESS;
|
||||
|
||||
pl_error:
|
||||
free(xdesc->instance);
|
||||
free(xdesc);
|
||||
#endif
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the hardware SPI peripherial
|
||||
*
|
||||
* @param xdesc Platform specific SPI descriptor
|
||||
* @param xinit Platform specific SPI init param
|
||||
* @return int32_t FAILURE if the device couldn't be found or configured
|
||||
*/
|
||||
static int32_t spi_init_ps(struct spi_desc *desc,
|
||||
const struct spi_init_param *param)
|
||||
{
|
||||
#ifdef XSPIPS_H
|
||||
int32_t ret;
|
||||
struct xil_spi_desc *xdesc;
|
||||
struct xil_spi_init_param *xinit;
|
||||
const uint32_t prescaler_default = XSPIPS_CLK_PRESCALE_64;
|
||||
const uint32_t prescaler_min = XSPIPS_CLK_PRESCALE_4;
|
||||
const uint32_t prescaler_max = XSPIPS_CLK_PRESCALE_256;
|
||||
uint32_t prescaler = 0u;
|
||||
uint32_t input_clock = 0u;
|
||||
|
||||
xdesc = (xil_spi_desc*)malloc(sizeof(xil_spi_desc));
|
||||
if(!xdesc) {
|
||||
free(xdesc);
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
desc->extra = xdesc;
|
||||
xinit = param->extra;
|
||||
xdesc->type = xinit->type;
|
||||
xdesc->flags = xinit->flags;
|
||||
|
||||
xdesc->instance = (XSpiPs*)malloc(sizeof(XSpiPs));
|
||||
if(!xdesc->instance)
|
||||
goto ps_error;
|
||||
|
||||
xdesc->config = XSpiPs_LookupConfig(param->device_id);
|
||||
if(xdesc->config == NULL)
|
||||
goto ps_error;
|
||||
|
||||
ret = XSpiPs_CfgInitialize(xdesc->instance,
|
||||
xdesc->config,
|
||||
((XSpiPs_Config*)xdesc->config)
|
||||
->BaseAddress);
|
||||
if(ret != SUCCESS)
|
||||
goto ps_error;
|
||||
|
||||
switch (param->device_id) {
|
||||
#if (SPI_NUM_INSTANCES >= 1)
|
||||
case 0:
|
||||
input_clock = SPI_CLK_FREQ_HZ(0);
|
||||
break;
|
||||
#endif
|
||||
#if (SPI_NUM_INSTANCES >= 2)
|
||||
case 1:
|
||||
input_clock = SPI_CLK_FREQ_HZ(1);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
goto ps_error;
|
||||
};
|
||||
|
||||
if (desc->max_speed_hz != 0u) {
|
||||
uint32_t div = input_clock / desc->max_speed_hz;
|
||||
uint32_t rem = input_clock % desc->max_speed_hz;
|
||||
uint32_t po2 = !(div & (div - 1)) && !rem;
|
||||
|
||||
// find the power of two just higher than div and
|
||||
// store the exponent in prescaler
|
||||
while(div) {
|
||||
prescaler += 1;
|
||||
div >>= 1u;
|
||||
}
|
||||
|
||||
// this exponent - 1 is needed because of the way
|
||||
// xilinx stores it into registers
|
||||
if (prescaler)
|
||||
prescaler -= 1;
|
||||
|
||||
// this exponent - 1 is needed when initial div was
|
||||
// precisely a power of two
|
||||
if (prescaler && po2)
|
||||
prescaler -= 1;
|
||||
|
||||
if (prescaler < prescaler_min)
|
||||
prescaler = prescaler_min;
|
||||
|
||||
if (prescaler > prescaler_max)
|
||||
prescaler = prescaler_max;
|
||||
} else
|
||||
prescaler = prescaler_default;
|
||||
|
||||
ret = XSpiPs_SetClkPrescaler(xdesc->instance, prescaler);
|
||||
|
||||
if(ret != SUCCESS)
|
||||
goto ps_error;
|
||||
|
||||
return SUCCESS;
|
||||
|
||||
ps_error:
|
||||
free(xdesc->instance);
|
||||
free(xdesc);
|
||||
#endif
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize the SPI communication peripheral.
|
||||
* @param desc - The SPI descriptor.
|
||||
* @param param - The structure that contains the SPI parameters.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t xil_spi_init(struct spi_desc **desc,
|
||||
const struct spi_init_param *param)
|
||||
{
|
||||
int32_t ret;
|
||||
enum xil_spi_type *spi_type;
|
||||
|
||||
if (!param) {
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
*desc = malloc(sizeof(**desc));
|
||||
if(! *desc) {
|
||||
free(*desc);
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
spi_type = param->extra;
|
||||
|
||||
if(!spi_type)
|
||||
goto init_error;
|
||||
|
||||
(*desc)->max_speed_hz = param->max_speed_hz;
|
||||
(*desc)->mode = param->mode;
|
||||
(*desc)->bit_order = param->bit_order;
|
||||
(*desc)->chip_select = param->chip_select;
|
||||
|
||||
switch (*spi_type) {
|
||||
case SPI_PL:
|
||||
ret = spi_init_pl(*desc, param);
|
||||
break;
|
||||
case SPI_PS:
|
||||
ret = spi_init_ps(*desc, param);
|
||||
break;
|
||||
|
||||
default:
|
||||
goto init_error;
|
||||
break;
|
||||
}
|
||||
|
||||
if (ret != SUCCESS) {
|
||||
init_error:
|
||||
free(*desc);
|
||||
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Free the resources allocated by spi_init().
|
||||
* @param desc - The SPI descriptor.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t xil_spi_remove(struct spi_desc *desc)
|
||||
{
|
||||
#ifdef XSPI_H
|
||||
int32_t ret;
|
||||
#endif
|
||||
struct xil_spi_desc *xdesc = NULL;
|
||||
enum xil_spi_type *spi_type;
|
||||
|
||||
spi_type = desc->extra;
|
||||
|
||||
if(!spi_type)
|
||||
return FAILURE;
|
||||
|
||||
switch (*spi_type ) {
|
||||
case SPI_PL:
|
||||
#ifdef XSPI_H
|
||||
xdesc = desc->extra;
|
||||
|
||||
if(!xdesc)
|
||||
return FAILURE;
|
||||
|
||||
ret = XSpi_Stop((XSpi *)(xdesc->instance));
|
||||
if(ret != SUCCESS)
|
||||
goto error;
|
||||
#endif
|
||||
break;
|
||||
case SPI_PS:
|
||||
#ifdef XSPIPS_H
|
||||
xdesc = desc->extra;
|
||||
|
||||
if(!xdesc)
|
||||
return FAILURE;
|
||||
#endif
|
||||
break;
|
||||
|
||||
/* Intended fallthrough */
|
||||
#ifdef XSPI_H
|
||||
error:
|
||||
#endif
|
||||
default:
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
if(xdesc)
|
||||
free(xdesc->instance);
|
||||
free(desc->extra);
|
||||
free(desc);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write and read data to/from SPI.
|
||||
* @param desc - The SPI descriptor.
|
||||
* @param data - The buffer with the transmitted/received data.
|
||||
* @param bytes_number - Number of bytes to write/read.
|
||||
* @return SUCCESS in case of success, FAILURE otherwise.
|
||||
*/
|
||||
int32_t xil_spi_write_and_read(struct spi_desc *desc,
|
||||
uint8_t *data,
|
||||
uint16_t bytes_number)
|
||||
{
|
||||
int32_t ret;
|
||||
#ifdef XSPI_H
|
||||
uint32_t ctrl_reg;
|
||||
#endif
|
||||
struct xil_spi_desc *xdesc;
|
||||
enum xil_spi_type *spi_type;
|
||||
|
||||
ret = FAILURE;
|
||||
|
||||
spi_type = desc->extra;
|
||||
|
||||
if(!spi_type)
|
||||
return FAILURE;
|
||||
|
||||
xdesc = desc->extra;
|
||||
|
||||
switch (*spi_type) {
|
||||
case SPI_PL:
|
||||
#ifdef XSPI_H
|
||||
ret = XSpi_SetOptions(xdesc->instance,
|
||||
XSP_MASTER_OPTION |
|
||||
((desc->mode & SPI_CPOL) ?
|
||||
XSP_CLK_ACTIVE_LOW_OPTION : 0) |
|
||||
((desc->mode & SPI_CPHA) ?
|
||||
XSP_CLK_PHASE_1_OPTION : 0));
|
||||
if (ret != SUCCESS)
|
||||
goto error;
|
||||
|
||||
ctrl_reg = XSpi_GetControlReg(((XSpi*)xdesc->instance));
|
||||
if (desc->bit_order == SPI_BIT_ORDER_LSB_FIRST)
|
||||
ctrl_reg |= XSP_CR_LSB_MSB_FIRST_MASK;
|
||||
else
|
||||
ctrl_reg &= ~ XSP_CR_LSB_MSB_FIRST_MASK;
|
||||
XSpi_SetControlReg(((XSpi*)xdesc->instance), ctrl_reg);
|
||||
|
||||
ret = XSpi_SetSlaveSelect(xdesc->instance,
|
||||
0x01 << desc->chip_select);
|
||||
if (ret != SUCCESS)
|
||||
goto error;
|
||||
|
||||
ret = XSpi_Transfer(xdesc->instance,
|
||||
data,
|
||||
data,
|
||||
bytes_number);
|
||||
if (ret != SUCCESS)
|
||||
goto error;
|
||||
#endif
|
||||
break;
|
||||
case SPI_PS:
|
||||
#ifdef XSPIPS_H
|
||||
ret = XSpiPs_SetOptions(xdesc->instance,
|
||||
XSPIPS_MASTER_OPTION |
|
||||
((xdesc->flags & SPI_CS_DECODE) ?
|
||||
XSPIPS_DECODE_SSELECT_OPTION : 0) |
|
||||
XSPIPS_FORCE_SSELECT_OPTION |
|
||||
((desc->mode & SPI_CPOL) ?
|
||||
XSPIPS_CLK_ACTIVE_LOW_OPTION : 0) |
|
||||
((desc->mode & SPI_CPHA) ?
|
||||
XSPIPS_CLK_PHASE_1_OPTION : 0));
|
||||
if (ret != SUCCESS)
|
||||
goto error;
|
||||
|
||||
ret = XSpiPs_SetSlaveSelect(xdesc->instance,
|
||||
desc->chip_select);
|
||||
if (ret != SUCCESS)
|
||||
goto error;
|
||||
ret = XSpiPs_PolledTransfer(xdesc->instance,
|
||||
data,
|
||||
data,
|
||||
bytes_number);
|
||||
if (ret != SUCCESS)
|
||||
goto error;
|
||||
ret = XSpiPs_SetSlaveSelect(xdesc->instance, SPI_DEASSERT_CURRENT_SS);
|
||||
if (ret != SUCCESS)
|
||||
goto error;
|
||||
#endif
|
||||
break;
|
||||
error:
|
||||
default:
|
||||
return FAILURE;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Xilinx platform specific SPI platform ops structure
|
||||
*/
|
||||
const struct spi_platform_ops xil_spi_ops = {
|
||||
.init = &xil_spi_init,
|
||||
.write_and_read = &xil_spi_write_and_read,
|
||||
.write_and_read_3wire = NULL, // Not support.
|
||||
.remove = &xil_spi_remove
|
||||
};
|
||||
+531
@@ -0,0 +1,531 @@
|
||||
/*******************************************************************************
|
||||
* @file xilinx/xilinx_spi_pl.c
|
||||
* @brief Driver for spi pl device using registers
|
||||
* @author Mihail Chindris (mihail.chindris@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2021(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
#include <xparameters.h>
|
||||
|
||||
#ifdef XPAR_XSPI_NUM_INSTANCES
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
|
||||
#include <xspi.h>
|
||||
#include <stdlib.h>
|
||||
#include <stdbool.h>
|
||||
#include "spi.h"
|
||||
#include "error.h"
|
||||
#include "delay.h"
|
||||
#include "util.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/********************** Macros and Constants Definitions **********************/
|
||||
/******************************************************************************/
|
||||
|
||||
#define XPS_TYPE_WRITE 0x1
|
||||
#define XPS_TYPE_READ 0x2
|
||||
#define XSP_DEFAULT_SR_VALUE 0x25
|
||||
#define XSP_DUMMY_DATA 0xFF
|
||||
|
||||
/*
|
||||
* Used to store current spi device configuration in order to not update it for
|
||||
* each spi transaction if not needed.
|
||||
*/
|
||||
static struct spi_desc g_spi_desc[XPAR_XSPI_NUM_INSTANCES];
|
||||
|
||||
/******************************************************************************/
|
||||
/*************************** Types Declarations *******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/* Xilinx PL spi specific data */
|
||||
struct xspi_desc {
|
||||
uint32_t base_addr;
|
||||
uint32_t disable_slaves_mask;
|
||||
uint32_t fifo_depth;
|
||||
uint8_t cs_asserted;
|
||||
};
|
||||
|
||||
/* Structure used to iterate over SPI messages */
|
||||
struct msg_iter {
|
||||
struct spi_msg *msgs;
|
||||
uint32_t len;
|
||||
uint32_t i;
|
||||
uint32_t buff_i;
|
||||
uint8_t is_wr;
|
||||
};
|
||||
|
||||
/******************************************************************************/
|
||||
/************************ Functions Definitions *******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
/* Read device register */
|
||||
static inline uint32_t _read(struct xspi_desc *xdesc, uint32_t reg)
|
||||
{
|
||||
return Xil_In32(xdesc->base_addr + reg);
|
||||
}
|
||||
|
||||
/* Write device register */
|
||||
static inline void _write(struct xspi_desc *xdesc, uint32_t reg, uint32_t val)
|
||||
{
|
||||
Xil_Out32(xdesc->base_addr + reg, val);
|
||||
}
|
||||
|
||||
/* Update device register. Only bits set to 1 in mask will be modified */
|
||||
static inline void _wr_mask(struct xspi_desc *xdesc, uint32_t reg,
|
||||
uint32_t val, uint32_t mask)
|
||||
{
|
||||
uint32_t tmp;
|
||||
|
||||
tmp = _read(xdesc, reg);
|
||||
tmp &= ~mask;
|
||||
tmp |= val & mask;
|
||||
_write(xdesc, reg, tmp);
|
||||
}
|
||||
|
||||
/* Update spi device configuration if needed */
|
||||
static void _update_mode(struct spi_desc *desc)
|
||||
{
|
||||
uint32_t val;
|
||||
uint32_t mask;
|
||||
|
||||
if (desc->mode == g_spi_desc[desc->device_id].mode &&
|
||||
desc->bit_order == g_spi_desc[desc->device_id].bit_order)
|
||||
return ;
|
||||
|
||||
/* Update mode */
|
||||
val = desc->mode | SPI_CPOL ? XSP_CR_CLK_POLARITY_MASK : 0;
|
||||
val |= desc->mode | SPI_CPHA ? XSP_CR_CLK_PHASE_MASK : 0;
|
||||
mask = XSP_CR_CLK_POLARITY_MASK | XSP_CR_CLK_PHASE_MASK;
|
||||
|
||||
val |= desc->bit_order == SPI_BIT_ORDER_LSB_FIRST ?
|
||||
XSP_CR_LSB_MSB_FIRST_MASK : 0;
|
||||
mask |= XSP_CR_LSB_MSB_FIRST_MASK;
|
||||
|
||||
_wr_mask(desc->extra, XSP_CR_OFFSET, val, mask);
|
||||
g_spi_desc[desc->device_id] = *desc;
|
||||
}
|
||||
|
||||
/* Configure SPI PL device */
|
||||
static int32_t _xil_spi_init_dev(struct xspi_desc *xdesc)
|
||||
{
|
||||
uint32_t val;
|
||||
|
||||
/* Software reset */
|
||||
_write(xdesc, XSP_SRR_OFFSET, XSP_SRR_RESET_MASK);
|
||||
mdelay(1);
|
||||
|
||||
/* Check if success reset */
|
||||
val = _read(xdesc, XSP_SR_OFFSET);
|
||||
if (val != XSP_DEFAULT_SR_VALUE)
|
||||
return -ENODEV;
|
||||
|
||||
/* Disable interrupts. Drivers only works with pooled mode */
|
||||
_write(xdesc, XSP_IIER_OFFSET, 0);
|
||||
|
||||
/* Deasert chip selects */
|
||||
_write(xdesc, XSP_SSR_OFFSET, 0xFFFFFFFF);
|
||||
|
||||
/* Get fifo depth */
|
||||
while (!(_read(xdesc, XSP_SR_OFFSET) & XSP_SR_TX_FULL_MASK))
|
||||
_write(xdesc, XSP_DTR_OFFSET, XSP_DUMMY_DATA);
|
||||
xdesc->fifo_depth = _read(xdesc, XSP_TFO_OFFSET) + 1;
|
||||
|
||||
/* Configure spi device */
|
||||
val = XSP_CR_ENABLE_MASK |
|
||||
XSP_CR_MANUAL_SS_MASK |
|
||||
XSP_CR_TXFIFO_RESET_MASK |
|
||||
XSP_CR_RXFIFO_RESET_MASK |
|
||||
XSP_CR_MASTER_MODE_MASK |
|
||||
XSP_CR_TRANS_INHIBIT_MASK;
|
||||
|
||||
_write(xdesc, XSP_CR_OFFSET, val);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/* Initialize spi_desc structure and device */
|
||||
static int32_t xil_spi_init_pl(struct spi_desc **desc,
|
||||
const struct spi_init_param *param)
|
||||
{
|
||||
struct spi_desc *ldesc;
|
||||
struct xspi_desc *xdesc;
|
||||
int32_t err;
|
||||
XSpi_Config *cfg;
|
||||
|
||||
if (!desc || !param || param->device_id >= XPAR_XSPI_NUM_INSTANCES)
|
||||
return -EINVAL;
|
||||
|
||||
cfg = XSpi_LookupConfig(param->device_id);
|
||||
if (!cfg)
|
||||
return -EINVAL;
|
||||
|
||||
if (param->chip_select > cfg->NumSlaveBits)
|
||||
return -EINVAL;
|
||||
|
||||
ldesc = (struct spi_desc *)calloc(1, sizeof(*ldesc));
|
||||
if (!ldesc)
|
||||
return -ENOMEM;
|
||||
|
||||
xdesc = (struct xspi_desc *)calloc(1, sizeof(*xdesc));
|
||||
if (!xdesc) {
|
||||
err = -ENOMEM;
|
||||
goto error;
|
||||
}
|
||||
|
||||
ldesc->bit_order = param->bit_order;
|
||||
ldesc->chip_select = param->chip_select;
|
||||
ldesc->mode = param->mode;
|
||||
xdesc->base_addr = cfg->BaseAddress;
|
||||
xdesc->disable_slaves_mask = (1 << cfg->NumSlaveBits) - 1;
|
||||
xdesc->cs_asserted = 0;
|
||||
|
||||
err = _xil_spi_init_dev(xdesc);
|
||||
if (IS_ERR_VALUE(err))
|
||||
goto error;
|
||||
|
||||
ldesc->extra = xdesc;
|
||||
*desc = ldesc;
|
||||
|
||||
return SUCCESS;
|
||||
|
||||
error:
|
||||
free(xdesc);
|
||||
free(ldesc);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
/* Remove allocated resources */
|
||||
static int32_t xil_spi_remove_pl(struct spi_desc *desc)
|
||||
{
|
||||
if (!desc)
|
||||
return -EINVAL;
|
||||
|
||||
free(desc->extra);
|
||||
free(desc);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/*
|
||||
* Fill fifo until fifo is full or no more data available.
|
||||
* Return the number of written bytes.
|
||||
*/
|
||||
static uint32_t _wr_fifo(struct xspi_desc *xdesc, uint8_t *data,
|
||||
uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
uint32_t to_write;
|
||||
uint32_t tx_available;
|
||||
|
||||
tx_available = xdesc->fifo_depth - _read(xdesc, XSP_TFO_OFFSET);
|
||||
to_write = min(tx_available, len);
|
||||
for (i = 0; i < to_write; ++i)
|
||||
if (data)
|
||||
_write(xdesc, XSP_DTR_OFFSET, data[i]);
|
||||
else
|
||||
_write(xdesc, XSP_DTR_OFFSET, XSP_DUMMY_DATA);
|
||||
|
||||
return to_write;
|
||||
}
|
||||
|
||||
/*
|
||||
* Read fifo until fifo is empty or no more buffer available to read into
|
||||
* Returns the number of read bytes
|
||||
*/
|
||||
static uint32_t _rd_fifo(struct xspi_desc *xdesc, uint8_t *data,
|
||||
uint32_t len)
|
||||
{
|
||||
uint32_t rx_available;
|
||||
uint32_t to_read;
|
||||
uint32_t tmp;
|
||||
uint32_t i;
|
||||
|
||||
tmp = _read(xdesc, XSP_SR_OFFSET);
|
||||
if (tmp & XSP_SR_RX_EMPTY_MASK)
|
||||
return 0;
|
||||
|
||||
rx_available = _read(xdesc, XSP_RFO_OFFSET) + 1;
|
||||
to_read = min(rx_available, len);
|
||||
for (i = 0; i < to_read; ++i) {
|
||||
tmp = _read(xdesc, XSP_DRR_OFFSET);
|
||||
if (data)
|
||||
data[i] = tmp;
|
||||
}
|
||||
|
||||
return to_read;
|
||||
}
|
||||
|
||||
/* If start is 0 stop transfer, else start it.
|
||||
* CS will be asserted if needed. If different CS othere than the one needed
|
||||
* is asserted. Deassert it and assert correct one */
|
||||
static void _xil_spi_start_transfer(struct spi_desc *desc, uint8_t start)
|
||||
{
|
||||
struct xspi_desc *xdesc;
|
||||
|
||||
xdesc = desc->extra;
|
||||
if (start) {
|
||||
if (xdesc->cs_asserted) {
|
||||
if (desc->chip_select ==
|
||||
g_spi_desc[desc->device_id].chip_select)
|
||||
return ;
|
||||
else
|
||||
/* Stop transfer to start again with new CS */
|
||||
_xil_spi_start_transfer(desc, 0);
|
||||
}
|
||||
_write(xdesc, XSP_SSR_OFFSET, ~(1 << desc->chip_select));
|
||||
_wr_mask(xdesc, XSP_CR_OFFSET, 0, XSP_CR_TRANS_INHIBIT_MASK);
|
||||
} else {
|
||||
_wr_mask(xdesc, XSP_CR_OFFSET, XSP_CR_TRANS_INHIBIT_MASK,
|
||||
XSP_CR_TRANS_INHIBIT_MASK);
|
||||
_write(xdesc, XSP_SSR_OFFSET, xdesc->disable_slaves_mask);
|
||||
}
|
||||
xdesc->cs_asserted = start;
|
||||
}
|
||||
|
||||
|
||||
/* SPI polled transfer */
|
||||
static int32_t xil_spi_write_and_read_pl(struct spi_desc *desc, uint8_t *data,
|
||||
uint16_t bytes_number)
|
||||
{
|
||||
struct xspi_desc *xdesc;
|
||||
uint32_t rx;
|
||||
uint32_t tx;
|
||||
|
||||
if (!desc || !desc->extra)
|
||||
return -EINVAL;
|
||||
|
||||
xdesc = desc->extra;
|
||||
_update_mode(desc);
|
||||
|
||||
_xil_spi_start_transfer(desc, 1);
|
||||
rx = 0;
|
||||
tx = 0;
|
||||
while (rx < bytes_number) {
|
||||
if (tx < bytes_number)
|
||||
tx += _wr_fifo(xdesc, data + tx, bytes_number - tx);
|
||||
rx += _rd_fifo(xdesc, data + rx, bytes_number - rx);
|
||||
}
|
||||
_xil_spi_start_transfer(desc, 0);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/* Get type of message. It can be READ, WRITE or both */
|
||||
static uint32_t _get_msg_type(struct spi_msg *msg)
|
||||
{
|
||||
uint32_t type;
|
||||
|
||||
type = 0;
|
||||
if (msg->tx_buff)
|
||||
type |= XPS_TYPE_WRITE;
|
||||
if (msg->rx_buff)
|
||||
type |= XPS_TYPE_READ;
|
||||
|
||||
return type;
|
||||
}
|
||||
|
||||
/* Get information based on current iterator position */
|
||||
static void _get_data(struct msg_iter *it, uint8_t **buff, uint32_t *len,
|
||||
uint32_t *type)
|
||||
{
|
||||
struct spi_msg *msg;
|
||||
|
||||
if (it->i == it->len) {
|
||||
*len = 0;
|
||||
return ;
|
||||
}
|
||||
|
||||
msg = it->msgs + it->i;
|
||||
if (it->is_wr)
|
||||
*buff = msg->tx_buff;
|
||||
else
|
||||
*buff = msg->rx_buff;
|
||||
|
||||
if (*buff)
|
||||
*buff += it->buff_i;
|
||||
|
||||
*len = msg->bytes_number - it->buff_i;
|
||||
if (type)
|
||||
*type = _get_msg_type(msg);
|
||||
}
|
||||
|
||||
/*
|
||||
* Increment iterator position with desired length.
|
||||
* If the new position has a different message type, new_type will be set to 1
|
||||
* If a CS change is needed, cs_change is set
|
||||
*/
|
||||
static void _increment_iter(struct msg_iter *it, uint32_t len,
|
||||
uint8_t *cs_change, uint8_t *new_type)
|
||||
{
|
||||
struct spi_msg *msg;
|
||||
uint32_t type;
|
||||
uint32_t extra_len;
|
||||
|
||||
if (!len)
|
||||
return ;
|
||||
|
||||
*cs_change = 0;
|
||||
*new_type = 0;
|
||||
msg = it->msgs + it->i;
|
||||
if (it->buff_i + len > msg->bytes_number)
|
||||
extra_len = it->buff_i + len - msg->bytes_number;
|
||||
else
|
||||
extra_len = 0;
|
||||
len -= extra_len;
|
||||
it->buff_i += len;
|
||||
if (it->buff_i == msg->bytes_number) {
|
||||
type = _get_msg_type(msg);
|
||||
++it->i;
|
||||
it->buff_i = 0;
|
||||
if (cs_change && msg->cs_change)
|
||||
*cs_change = 1;
|
||||
if (new_type)
|
||||
if (it->i == it->len ||
|
||||
type != _get_msg_type(it->msgs + it->i))
|
||||
*new_type = 1;
|
||||
}
|
||||
if (extra_len)
|
||||
_increment_iter(it, extra_len, cs_change, new_type);
|
||||
}
|
||||
|
||||
/*
|
||||
* SPI polling transfer of multiple messages.
|
||||
*/
|
||||
static int32_t xil_spi_transfer_pl(struct spi_desc *desc, struct spi_msg *msgs,
|
||||
uint32_t len)
|
||||
|
||||
{
|
||||
struct xspi_desc *xdesc;
|
||||
uint8_t cs_change;
|
||||
uint8_t new_type;
|
||||
struct msg_iter rx = {.msgs = msgs, .len = len, .is_wr = 0};
|
||||
struct msg_iter tx = {.msgs = msgs, .len = len, .is_wr = 1};
|
||||
uint8_t *buff;
|
||||
uint32_t bytes;
|
||||
uint32_t type;
|
||||
/* Bytes to increment rx when only a write transaction is executed */
|
||||
uint32_t to_inc_rx;
|
||||
/* Difference between rx and tx iterators in bytes */
|
||||
uint32_t tx_advance;
|
||||
/* Save bytes sent during a write loop */
|
||||
uint32_t tx_sent;
|
||||
/* Used to loop if need to empty the RX FIFO */
|
||||
uint32_t loop;
|
||||
|
||||
if (!desc || !desc->extra)
|
||||
return -EINVAL;
|
||||
|
||||
xdesc = desc->extra;
|
||||
_update_mode(desc);
|
||||
|
||||
tx_advance = 0;
|
||||
to_inc_rx = 0;
|
||||
buff = NULL;
|
||||
type = 0;
|
||||
do {
|
||||
_xil_spi_start_transfer(desc, 1);
|
||||
|
||||
tx_sent = 0;
|
||||
/* Writing loop */
|
||||
do {
|
||||
_get_data(&tx, &buff, &bytes, &type);
|
||||
if (type & XPS_TYPE_READ)
|
||||
/*
|
||||
* Do not write more bytes than fifo_depth if
|
||||
* they haven't been read.
|
||||
*/
|
||||
bytes = min(bytes,
|
||||
xdesc->fifo_depth - tx_advance);
|
||||
bytes = _wr_fifo(xdesc, buff, bytes);
|
||||
tx_sent += bytes;
|
||||
_increment_iter(&tx, bytes, &cs_change, &new_type);
|
||||
tx_advance += bytes;
|
||||
} while (!cs_change && !new_type && bytes);
|
||||
|
||||
if (type & XPS_TYPE_READ) {
|
||||
loop = 1;
|
||||
/*
|
||||
* Loop only when no more data to write otherwise read
|
||||
* only available data.
|
||||
*/
|
||||
while (loop) {
|
||||
if (!new_type)
|
||||
loop = 0;
|
||||
_get_data(&rx, &buff, &bytes, NULL);
|
||||
bytes = _rd_fifo(xdesc, buff, bytes);
|
||||
_increment_iter(&rx, bytes, &cs_change, &new_type);
|
||||
tx_advance -= bytes;
|
||||
if (loop && new_type)
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
/* Clean RX FIFO if it was only a WRITE message */
|
||||
to_inc_rx += tx_sent;
|
||||
if (new_type) {
|
||||
/* Wait for TX to be sent */
|
||||
while (!(_read(xdesc, XSP_SR_OFFSET) &
|
||||
XSP_SR_TX_EMPTY_MASK))
|
||||
;
|
||||
/* Reset fifo. Only write was performed */
|
||||
_wr_mask(xdesc, XSP_CR_OFFSET,
|
||||
XSP_CR_RXFIFO_RESET_MASK,
|
||||
XSP_CR_RXFIFO_RESET_MASK);
|
||||
|
||||
_increment_iter(&rx, to_inc_rx, NULL, NULL);
|
||||
tx_advance -= to_inc_rx;
|
||||
to_inc_rx = 0;
|
||||
}
|
||||
}
|
||||
|
||||
if ((cs_change && rx.i != len) || (!cs_change && rx.i == len))
|
||||
_xil_spi_start_transfer(desc, 0);
|
||||
} while (rx.i < len);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
const struct spi_platform_ops xil_spi_reg_ops_pl = {
|
||||
.init = xil_spi_init_pl,
|
||||
.remove = xil_spi_remove_pl,
|
||||
.write_and_read = xil_spi_write_and_read_pl,
|
||||
.write_and_read_3wire = NULL, // Not support.
|
||||
.transfer = xil_spi_transfer_pl
|
||||
};
|
||||
|
||||
#endif // XPAR_XSPI_NUM_INSTANCES
|
||||
+7475
File diff suppressed because it is too large
Load Diff
+3568
File diff suppressed because it is too large
Load Diff
+2157
File diff suppressed because it is too large
Load Diff
+552
@@ -0,0 +1,552 @@
|
||||
/***************************************************************************//**
|
||||
* @file ad9361_api.h
|
||||
* @brief Header file of AD9361 API Driver.
|
||||
* @author DBogdan (dragos.bogdan@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2013(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
#ifndef AD9361_API_H_
|
||||
#define AD9361_API_H_
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
#include "ad9361_util.h"
|
||||
#include "../../../include/gpio.h"
|
||||
#include "../../../include/spi.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/*************************** Types Declarations *******************************/
|
||||
/******************************************************************************/
|
||||
typedef struct {
|
||||
/* Device selection */
|
||||
enum dev_id dev_sel;
|
||||
/* Reference Clock */
|
||||
uint32_t reference_clk_rate;
|
||||
/* Base Configuration */
|
||||
uint8_t two_rx_two_tx_mode_enable; /* adi,2rx-2tx-mode-enable */
|
||||
uint8_t one_rx_one_tx_mode_use_rx_num; /* adi,1rx-1tx-mode-use-rx-num */
|
||||
uint8_t one_rx_one_tx_mode_use_tx_num; /* adi,1rx-1tx-mode-use-tx-num */
|
||||
uint8_t frequency_division_duplex_mode_enable; /* adi,frequency-division-duplex-mode-enable */
|
||||
uint8_t frequency_division_duplex_independent_mode_enable; /* adi,frequency-division-duplex-independent-mode-enable */
|
||||
uint8_t tdd_use_dual_synth_mode_enable; /* adi,tdd-use-dual-synth-mode-enable */
|
||||
uint8_t tdd_skip_vco_cal_enable; /* adi,tdd-skip-vco-cal-enable */
|
||||
uint32_t tx_fastlock_delay_ns; /* adi,tx-fastlock-delay-ns */
|
||||
uint32_t rx_fastlock_delay_ns; /* adi,rx-fastlock-delay-ns */
|
||||
uint8_t rx_fastlock_pincontrol_enable; /* adi,rx-fastlock-pincontrol-enable */
|
||||
uint8_t tx_fastlock_pincontrol_enable; /* adi,tx-fastlock-pincontrol-enable */
|
||||
uint8_t external_rx_lo_enable; /* adi,external-rx-lo-enable */
|
||||
uint8_t external_tx_lo_enable; /* adi,external-tx-lo-enable */
|
||||
uint8_t dc_offset_tracking_update_event_mask; /* adi,dc-offset-tracking-update-event-mask */
|
||||
uint8_t dc_offset_attenuation_high_range; /* adi,dc-offset-attenuation-high-range */
|
||||
uint8_t dc_offset_attenuation_low_range; /* adi,dc-offset-attenuation-low-range */
|
||||
uint8_t dc_offset_count_high_range; /* adi,dc-offset-count-high-range */
|
||||
uint8_t dc_offset_count_low_range; /* adi,dc-offset-count-low-range */
|
||||
uint8_t split_gain_table_mode_enable; /* adi,split-gain-table-mode-enable */
|
||||
uint32_t trx_synthesizer_target_fref_overwrite_hz; /* adi,trx-synthesizer-target-fref-overwrite-hz */
|
||||
uint8_t qec_tracking_slow_mode_enable; /* adi,qec-tracking-slow-mode-enable */
|
||||
/* ENSM Control */
|
||||
uint8_t ensm_enable_pin_pulse_mode_enable; /* adi,ensm-enable-pin-pulse-mode-enable */
|
||||
uint8_t ensm_enable_txnrx_control_enable; /* adi,ensm-enable-txnrx-control-enable */
|
||||
/* LO Control */
|
||||
uint64_t rx_synthesizer_frequency_hz; /* adi,rx-synthesizer-frequency-hz */
|
||||
uint64_t tx_synthesizer_frequency_hz; /* adi,tx-synthesizer-frequency-hz */
|
||||
uint8_t tx_lo_powerdown_managed_enable; /* adi,tx-lo-powerdown-managed-enable */
|
||||
/* Rate & BW Control */
|
||||
uint32_t rx_path_clock_frequencies[6]; /* adi,rx-path-clock-frequencies */
|
||||
uint32_t tx_path_clock_frequencies[6]; /* adi,tx-path-clock-frequencies */
|
||||
uint32_t rf_rx_bandwidth_hz; /* adi,rf-rx-bandwidth-hz */
|
||||
uint32_t rf_tx_bandwidth_hz; /* adi,rf-tx-bandwidth-hz */
|
||||
/* RF Port Control */
|
||||
uint32_t rx_rf_port_input_select; /* adi,rx-rf-port-input-select */
|
||||
uint32_t tx_rf_port_input_select; /* adi,tx-rf-port-input-select */
|
||||
/* TX Attenuation Control */
|
||||
int32_t tx_attenuation_mdB; /* adi,tx-attenuation-mdB */
|
||||
uint8_t update_tx_gain_in_alert_enable; /* adi,update-tx-gain-in-alert-enable */
|
||||
/* Reference Clock Control */
|
||||
uint8_t xo_disable_use_ext_refclk_enable; /* adi,xo-disable-use-ext-refclk-enable */
|
||||
uint32_t dcxo_coarse_and_fine_tune[2]; /* adi,dcxo-coarse-and-fine-tune */
|
||||
uint32_t clk_output_mode_select; /* adi,clk-output-mode-select */
|
||||
/* Gain Control */
|
||||
uint8_t gc_rx1_mode; /* adi,gc-rx1-mode */
|
||||
uint8_t gc_rx2_mode; /* adi,gc-rx2-mode */
|
||||
uint8_t gc_adc_large_overload_thresh; /* adi,gc-adc-large-overload-thresh */
|
||||
uint8_t gc_adc_ovr_sample_size; /* adi,gc-adc-ovr-sample-size */
|
||||
uint8_t gc_adc_small_overload_thresh; /* adi,gc-adc-small-overload-thresh */
|
||||
uint16_t gc_dec_pow_measurement_duration; /* adi,gc-dec-pow-measurement-duration */
|
||||
uint8_t gc_dig_gain_enable; /* adi,gc-dig-gain-enable */
|
||||
uint16_t gc_lmt_overload_high_thresh; /* adi,gc-lmt-overload-high-thresh */
|
||||
uint16_t gc_lmt_overload_low_thresh; /* adi,gc-lmt-overload-low-thresh */
|
||||
uint8_t gc_low_power_thresh; /* adi,gc-low-power-thresh */
|
||||
uint8_t gc_max_dig_gain; /* adi,gc-max-dig-gain */
|
||||
uint8_t gc_use_rx_fir_out_for_dec_pwr_meas_enable; /* adi,gc-use-rx-fir-out-for-dec-pwr-meas-enable */
|
||||
/* Gain MGC Control */
|
||||
uint8_t mgc_dec_gain_step; /* adi,mgc-dec-gain-step */
|
||||
uint8_t mgc_inc_gain_step; /* adi,mgc-inc-gain-step */
|
||||
uint8_t mgc_rx1_ctrl_inp_enable; /* adi,mgc-rx1-ctrl-inp-enable */
|
||||
uint8_t mgc_rx2_ctrl_inp_enable; /* adi,mgc-rx2-ctrl-inp-enable */
|
||||
uint8_t mgc_split_table_ctrl_inp_gain_mode; /* adi,mgc-split-table-ctrl-inp-gain-mode */
|
||||
/* Gain AGC Control */
|
||||
uint8_t agc_adc_large_overload_exceed_counter; /* adi,agc-adc-large-overload-exceed-counter */
|
||||
uint8_t agc_adc_large_overload_inc_steps; /* adi,agc-adc-large-overload-inc-steps - Name is misleading should be dec-steps*/
|
||||
uint8_t agc_adc_lmt_small_overload_prevent_gain_inc_enable; /* adi,agc-adc-lmt-small-overload-prevent-gain-inc-enable */
|
||||
uint8_t agc_adc_small_overload_exceed_counter; /* adi,agc-adc-small-overload-exceed-counter */
|
||||
uint8_t agc_dig_gain_step_size; /* adi,agc-dig-gain-step-size */
|
||||
uint8_t agc_dig_saturation_exceed_counter; /* adi,agc-dig-saturation-exceed-counter */
|
||||
uint32_t agc_gain_update_interval_us; /* adi,agc-gain-update-interval-us */
|
||||
uint8_t agc_immed_gain_change_if_large_adc_overload_enable; /* adi,agc-immed-gain-change-if-large-adc-overload-enable */
|
||||
uint8_t agc_immed_gain_change_if_large_lmt_overload_enable; /* adi,agc-immed-gain-change-if-large-lmt-overload-enable */
|
||||
uint8_t agc_inner_thresh_high; /* adi,agc-inner-thresh-high */
|
||||
uint8_t agc_inner_thresh_high_dec_steps; /* adi,agc-inner-thresh-high-dec-steps */
|
||||
uint8_t agc_inner_thresh_low; /* adi,agc-inner-thresh-low */
|
||||
uint8_t agc_inner_thresh_low_inc_steps; /* adi,agc-inner-thresh-low-inc-steps */
|
||||
uint8_t agc_lmt_overload_large_exceed_counter; /* adi,agc-lmt-overload-large-exceed-counter */
|
||||
uint8_t agc_lmt_overload_large_inc_steps; /* adi,agc-lmt-overload-large-inc-steps */
|
||||
uint8_t agc_lmt_overload_small_exceed_counter; /* adi,agc-lmt-overload-small-exceed-counter */
|
||||
uint8_t agc_outer_thresh_high; /* adi,agc-outer-thresh-high */
|
||||
uint8_t agc_outer_thresh_high_dec_steps; /* adi,agc-outer-thresh-high-dec-steps */
|
||||
uint8_t agc_outer_thresh_low; /* adi,agc-outer-thresh-low */
|
||||
uint8_t agc_outer_thresh_low_inc_steps; /* adi,agc-outer-thresh-low-inc-steps */
|
||||
uint32_t agc_attack_delay_extra_margin_us; /* adi,agc-attack-delay-extra-margin-us */
|
||||
uint8_t agc_sync_for_gain_counter_enable; /* adi,agc-sync-for-gain-counter-enable */
|
||||
/* Fast AGC */
|
||||
uint32_t fagc_dec_pow_measuremnt_duration; /* adi,fagc-dec-pow-measurement-duration */
|
||||
uint32_t fagc_state_wait_time_ns; /* adi,fagc-state-wait-time-ns */
|
||||
/* Fast AGC - Low Power */
|
||||
uint8_t fagc_allow_agc_gain_increase; /* adi,fagc-allow-agc-gain-increase-enable */
|
||||
uint32_t fagc_lp_thresh_increment_time; /* adi,fagc-lp-thresh-increment-time */
|
||||
uint32_t fagc_lp_thresh_increment_steps; /* adi,fagc-lp-thresh-increment-steps */
|
||||
/* Fast AGC - Lock Level (Lock Level is set via slow AGC inner high threshold) */
|
||||
uint8_t fagc_lock_level_lmt_gain_increase_en; /* adi,fagc-lock-level-lmt-gain-increase-enable */
|
||||
uint32_t fagc_lock_level_gain_increase_upper_limit; /* adi,fagc-lock-level-gain-increase-upper-limit */
|
||||
/* Fast AGC - Peak Detectors and Final Settling */
|
||||
uint32_t fagc_lpf_final_settling_steps; /* adi,fagc-lpf-final-settling-steps */
|
||||
uint32_t fagc_lmt_final_settling_steps; /* adi,fagc-lmt-final-settling-steps */
|
||||
uint32_t fagc_final_overrange_count; /* adi,fagc-final-overrange-count */
|
||||
/* Fast AGC - Final Power Test */
|
||||
uint8_t fagc_gain_increase_after_gain_lock_en; /* adi,fagc-gain-increase-after-gain-lock-enable */
|
||||
/* Fast AGC - Unlocking the Gain */
|
||||
uint32_t fagc_gain_index_type_after_exit_rx_mode; /* adi,fagc-gain-index-type-after-exit-rx-mode */
|
||||
uint8_t fagc_use_last_lock_level_for_set_gain_en; /* adi,fagc-use-last-lock-level-for-set-gain-enable */
|
||||
uint8_t fagc_rst_gla_stronger_sig_thresh_exceeded_en; /* adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable */
|
||||
uint32_t fagc_optimized_gain_offset; /* adi,fagc-optimized-gain-offset */
|
||||
uint32_t fagc_rst_gla_stronger_sig_thresh_above_ll; /* adi,fagc-rst-gla-stronger-sig-thresh-above-ll */
|
||||
uint8_t fagc_rst_gla_engergy_lost_sig_thresh_exceeded_en; /* adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable */
|
||||
uint8_t fagc_rst_gla_engergy_lost_goto_optim_gain_en; /* adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable */
|
||||
uint32_t fagc_rst_gla_engergy_lost_sig_thresh_below_ll; /* adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll */
|
||||
uint32_t fagc_energy_lost_stronger_sig_gain_lock_exit_cnt; /* adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt */
|
||||
uint8_t fagc_rst_gla_large_adc_overload_en; /* adi,fagc-rst-gla-large-adc-overload-enable */
|
||||
uint8_t fagc_rst_gla_large_lmt_overload_en; /* adi,fagc-rst-gla-large-lmt-overload-enable */
|
||||
uint8_t fagc_rst_gla_en_agc_pulled_high_en; /* adi,fagc-rst-gla-en-agc-pulled-high-enable */
|
||||
uint32_t fagc_rst_gla_if_en_agc_pulled_high_mode; /* adi,fagc-rst-gla-if-en-agc-pulled-high-mode */
|
||||
uint32_t fagc_power_measurement_duration_in_state5; /* adi,fagc-power-measurement-duration-in-state5 */
|
||||
uint32_t fagc_large_overload_inc_steps; /* adi,fagc-adc-large-overload-inc-steps - Name is misleading should be dec-steps */
|
||||
/* RSSI Control */
|
||||
uint32_t rssi_delay; /* adi,rssi-delay */
|
||||
uint32_t rssi_duration; /* adi,rssi-duration */
|
||||
uint8_t rssi_restart_mode; /* adi,rssi-restart-mode */
|
||||
uint8_t rssi_unit_is_rx_samples_enable; /* adi,rssi-unit-is-rx-samples-enable */
|
||||
uint32_t rssi_wait; /* adi,rssi-wait */
|
||||
/* Aux ADC Control */
|
||||
uint32_t aux_adc_decimation; /* adi,aux-adc-decimation */
|
||||
uint32_t aux_adc_rate; /* adi,aux-adc-rate */
|
||||
/* AuxDAC Control */
|
||||
uint8_t aux_dac_manual_mode_enable; /* adi,aux-dac-manual-mode-enable */
|
||||
uint32_t aux_dac1_default_value_mV; /* adi,aux-dac1-default-value-mV */
|
||||
uint8_t aux_dac1_active_in_rx_enable; /* adi,aux-dac1-active-in-rx-enable */
|
||||
uint8_t aux_dac1_active_in_tx_enable; /* adi,aux-dac1-active-in-tx-enable */
|
||||
uint8_t aux_dac1_active_in_alert_enable; /* adi,aux-dac1-active-in-alert-enable */
|
||||
uint32_t aux_dac1_rx_delay_us; /* adi,aux-dac1-rx-delay-us */
|
||||
uint32_t aux_dac1_tx_delay_us; /* adi,aux-dac1-tx-delay-us */
|
||||
uint32_t aux_dac2_default_value_mV; /* adi,aux-dac2-default-value-mV */
|
||||
uint8_t aux_dac2_active_in_rx_enable; /* adi,aux-dac2-active-in-rx-enable */
|
||||
uint8_t aux_dac2_active_in_tx_enable; /* adi,aux-dac2-active-in-tx-enable */
|
||||
uint8_t aux_dac2_active_in_alert_enable; /* adi,aux-dac2-active-in-alert-enable */
|
||||
uint32_t aux_dac2_rx_delay_us; /* adi,aux-dac2-rx-delay-us */
|
||||
uint32_t aux_dac2_tx_delay_us; /* adi,aux-dac2-tx-delay-us */
|
||||
/* Temperature Sensor Control */
|
||||
uint32_t temp_sense_decimation; /* adi,temp-sense-decimation */
|
||||
uint16_t temp_sense_measurement_interval_ms; /* adi,temp-sense-measurement-interval-ms */
|
||||
int8_t temp_sense_offset_signed; /* adi,temp-sense-offset-signed */
|
||||
uint8_t temp_sense_periodic_measurement_enable; /* adi,temp-sense-periodic-measurement-enable */
|
||||
/* Control Out Setup */
|
||||
uint8_t ctrl_outs_enable_mask; /* adi,ctrl-outs-enable-mask */
|
||||
uint8_t ctrl_outs_index; /* adi,ctrl-outs-index */
|
||||
/* External LNA Control */
|
||||
uint32_t elna_settling_delay_ns; /* adi,elna-settling-delay-ns */
|
||||
uint32_t elna_gain_mdB; /* adi,elna-gain-mdB */
|
||||
uint32_t elna_bypass_loss_mdB; /* adi,elna-bypass-loss-mdB */
|
||||
uint8_t elna_rx1_gpo0_control_enable; /* adi,elna-rx1-gpo0-control-enable */
|
||||
uint8_t elna_rx2_gpo1_control_enable; /* adi,elna-rx2-gpo1-control-enable */
|
||||
uint8_t elna_gaintable_all_index_enable; /* adi,elna-gaintable-all-index-enable */
|
||||
/* Digital Interface Control */
|
||||
uint8_t digital_interface_tune_skip_mode; /* adi,digital-interface-tune-skip-mode */
|
||||
uint8_t digital_interface_tune_fir_disable; /* adi,digital-interface-tune-fir-disable */
|
||||
uint8_t pp_tx_swap_enable; /* adi,pp-tx-swap-enable */
|
||||
uint8_t pp_rx_swap_enable; /* adi,pp-rx-swap-enable */
|
||||
uint8_t tx_channel_swap_enable; /* adi,tx-channel-swap-enable */
|
||||
uint8_t rx_channel_swap_enable; /* adi,rx-channel-swap-enable */
|
||||
uint8_t rx_frame_pulse_mode_enable; /* adi,rx-frame-pulse-mode-enable */
|
||||
uint8_t two_t_two_r_timing_enable; /* adi,2t2r-timing-enable */
|
||||
uint8_t invert_data_bus_enable; /* adi,invert-data-bus-enable */
|
||||
uint8_t invert_data_clk_enable; /* adi,invert-data-clk-enable */
|
||||
uint8_t fdd_alt_word_order_enable; /* adi,fdd-alt-word-order-enable */
|
||||
uint8_t invert_rx_frame_enable; /* adi,invert-rx-frame-enable */
|
||||
uint8_t fdd_rx_rate_2tx_enable; /* adi,fdd-rx-rate-2tx-enable */
|
||||
uint8_t swap_ports_enable; /* adi,swap-ports-enable */
|
||||
uint8_t single_data_rate_enable; /* adi,single-data-rate-enable */
|
||||
uint8_t lvds_mode_enable; /* adi,lvds-mode-enable */
|
||||
uint8_t half_duplex_mode_enable; /* adi,half-duplex-mode-enable */
|
||||
uint8_t single_port_mode_enable; /* adi,single-port-mode-enable */
|
||||
uint8_t full_port_enable; /* adi,full-port-enable */
|
||||
uint8_t full_duplex_swap_bits_enable; /* adi,full-duplex-swap-bits-enable */
|
||||
uint32_t delay_rx_data; /* adi,delay-rx-data */
|
||||
uint32_t rx_data_clock_delay; /* adi,rx-data-clock-delay */
|
||||
uint32_t rx_data_delay; /* adi,rx-data-delay */
|
||||
uint32_t tx_fb_clock_delay; /* adi,tx-fb-clock-delay */
|
||||
uint32_t tx_data_delay; /* adi,tx-data-delay */
|
||||
uint32_t lvds_bias_mV; /* adi,lvds-bias-mV */
|
||||
uint8_t lvds_rx_onchip_termination_enable; /* adi,lvds-rx-onchip-termination-enable */
|
||||
uint8_t rx1rx2_phase_inversion_en; /* adi,rx1-rx2-phase-inversion-enable */
|
||||
uint8_t lvds_invert1_control; /* adi,lvds-invert1-control */
|
||||
uint8_t lvds_invert2_control; /* adi,lvds-invert2-control */
|
||||
/* GPO Control */
|
||||
uint8_t gpo_manual_mode_enable; /* adi,gpo-manual-mode-enable */
|
||||
uint32_t gpo_manual_mode_enable_mask; /* adi,gpo-manual-mode-enable-mask */
|
||||
uint8_t gpo0_inactive_state_high_enable; /* adi,gpo0-inactive-state-high-enable */
|
||||
uint8_t gpo1_inactive_state_high_enable; /* adi,gpo1-inactive-state-high-enable */
|
||||
uint8_t gpo2_inactive_state_high_enable; /* adi,gpo2-inactive-state-high-enable */
|
||||
uint8_t gpo3_inactive_state_high_enable; /* adi,gpo3-inactive-state-high-enable */
|
||||
uint8_t gpo0_slave_rx_enable; /* adi,gpo0-slave-rx-enable */
|
||||
uint8_t gpo0_slave_tx_enable; /* adi,gpo0-slave-tx-enable */
|
||||
uint8_t gpo1_slave_rx_enable; /* adi,gpo1-slave-rx-enable */
|
||||
uint8_t gpo1_slave_tx_enable; /* adi,gpo1-slave-tx-enable */
|
||||
uint8_t gpo2_slave_rx_enable; /* adi,gpo2-slave-rx-enable */
|
||||
uint8_t gpo2_slave_tx_enable; /* adi,gpo2-slave-tx-enable */
|
||||
uint8_t gpo3_slave_rx_enable; /* adi,gpo3-slave-rx-enable */
|
||||
uint8_t gpo3_slave_tx_enable; /* adi,gpo3-slave-tx-enable */
|
||||
uint8_t gpo0_rx_delay_us; /* adi,gpo0-rx-delay-us */
|
||||
uint8_t gpo0_tx_delay_us; /* adi,gpo0-tx-delay-us */
|
||||
uint8_t gpo1_rx_delay_us; /* adi,gpo1-rx-delay-us */
|
||||
uint8_t gpo1_tx_delay_us; /* adi,gpo1-tx-delay-us */
|
||||
uint8_t gpo2_rx_delay_us; /* adi,gpo2-rx-delay-us */
|
||||
uint8_t gpo2_tx_delay_us; /* adi,gpo2-tx-delay-us */
|
||||
uint8_t gpo3_rx_delay_us; /* adi,gpo3-rx-delay-us */
|
||||
uint8_t gpo3_tx_delay_us; /* adi,gpo3-tx-delay-us */
|
||||
/* Tx Monitor Control */
|
||||
uint32_t low_high_gain_threshold_mdB; /* adi,txmon-low-high-thresh */
|
||||
uint32_t low_gain_dB; /* adi,txmon-low-gain */
|
||||
uint32_t high_gain_dB; /* adi,txmon-high-gain */
|
||||
uint8_t tx_mon_track_en; /* adi,txmon-dc-tracking-enable */
|
||||
uint8_t one_shot_mode_en; /* adi,txmon-one-shot-mode-enable */
|
||||
uint32_t tx_mon_delay; /* adi,txmon-delay */
|
||||
uint32_t tx_mon_duration; /* adi,txmon-duration */
|
||||
uint32_t tx1_mon_front_end_gain; /* adi,txmon-1-front-end-gain */
|
||||
uint32_t tx2_mon_front_end_gain; /* adi,txmon-2-front-end-gain */
|
||||
uint32_t tx1_mon_lo_cm; /* adi,txmon-1-lo-cm */
|
||||
uint32_t tx2_mon_lo_cm; /* adi,txmon-2-lo-cm */
|
||||
/* GPIO definitions */
|
||||
struct gpio_init_param gpio_resetb; /* reset-gpios */
|
||||
/* MCS Sync */
|
||||
struct gpio_init_param gpio_sync; /* sync-gpios */
|
||||
struct gpio_init_param gpio_cal_sw1; /* cal-sw1-gpios */
|
||||
struct gpio_init_param gpio_cal_sw2; /* cal-sw2-gpios */
|
||||
|
||||
struct spi_init_param spi_param;
|
||||
|
||||
/* External LO clocks */
|
||||
uint32_t (*ad9361_rfpll_ext_recalc_rate)(struct refclk_scale *clk_priv);
|
||||
int32_t (*ad9361_rfpll_ext_round_rate)(struct refclk_scale *clk_priv,
|
||||
uint32_t rate);
|
||||
int32_t (*ad9361_rfpll_ext_set_rate)(struct refclk_scale *clk_priv,
|
||||
uint32_t rate);
|
||||
|
||||
} AD9361_InitParam;
|
||||
|
||||
typedef struct {
|
||||
uint32_t rx; /* 1, 2, 3(both) */
|
||||
int32_t rx_gain; /* -12, -6, 0, 6 */
|
||||
uint32_t rx_dec; /* 1, 2, 4 */
|
||||
int16_t rx_coef[128];
|
||||
uint8_t rx_coef_size;
|
||||
uint32_t rx_path_clks[6];
|
||||
uint32_t rx_bandwidth;
|
||||
} AD9361_RXFIRConfig;
|
||||
|
||||
typedef struct {
|
||||
uint32_t tx; /* 1, 2, 3(both) */
|
||||
int32_t tx_gain; /* -6, 0 */
|
||||
uint32_t tx_int; /* 1, 2, 4 */
|
||||
int16_t tx_coef[128];
|
||||
uint8_t tx_coef_size;
|
||||
uint32_t tx_path_clks[6];
|
||||
uint32_t tx_bandwidth;
|
||||
} AD9361_TXFIRConfig;
|
||||
|
||||
enum ad9361_ensm_mode {
|
||||
ENSM_MODE_TX,
|
||||
ENSM_MODE_RX,
|
||||
ENSM_MODE_ALERT,
|
||||
ENSM_MODE_FDD,
|
||||
ENSM_MODE_WAIT,
|
||||
ENSM_MODE_SLEEP,
|
||||
ENSM_MODE_PINCTRL,
|
||||
ENSM_MODE_PINCTRL_FDD_INDEP,
|
||||
};
|
||||
|
||||
#define ENABLE 1
|
||||
#define DISABLE 0
|
||||
|
||||
#define RX1 0
|
||||
#define RX2 1
|
||||
|
||||
#define TX1 0
|
||||
#define TX2 1
|
||||
|
||||
#define A_BALANCED 0
|
||||
#define B_BALANCED 1
|
||||
#define C_BALANCED 2
|
||||
#define A_N 3
|
||||
#define A_P 4
|
||||
#define B_N 5
|
||||
#define B_P 6
|
||||
#define C_N 7
|
||||
#define C_P 8
|
||||
#define TX_MON1 9
|
||||
#define TX_MON2 10
|
||||
#define TX_MON1_2 11
|
||||
|
||||
#define TXA 0
|
||||
#define TXB 1
|
||||
|
||||
#define MODE_1x1 1
|
||||
#define MODE_2x2 2
|
||||
|
||||
#define HIGHEST_OSR 0
|
||||
#define NOMINAL_OSR 1
|
||||
|
||||
#define INT_LO 0
|
||||
#define EXT_LO 1
|
||||
|
||||
#define ON 0
|
||||
#define OFF 1
|
||||
|
||||
/******************************************************************************/
|
||||
/************************ Functions Declarations ******************************/
|
||||
/******************************************************************************/
|
||||
/* Initialize the AD9361 part. */
|
||||
int32_t ad9361_init (struct ad9361_rf_phy **ad9361_phy,
|
||||
AD9361_InitParam *init_param);
|
||||
/* Free the allocated resources. */
|
||||
int32_t ad9361_remove(struct ad9361_rf_phy *phy);
|
||||
/* Set the Enable State Machine (ENSM) mode. */
|
||||
int32_t ad9361_set_en_state_machine_mode (struct ad9361_rf_phy *phy,
|
||||
uint32_t mode);
|
||||
/* Get the Enable State Machine (ENSM) mode. */
|
||||
int32_t ad9361_get_en_state_machine_mode (struct ad9361_rf_phy *phy,
|
||||
uint32_t *mode);
|
||||
/* Set the receive RF gain for the selected channel. */
|
||||
int32_t ad9361_set_rx_rf_gain (struct ad9361_rf_phy *phy, uint8_t ch,
|
||||
int32_t gain_db);
|
||||
/* Get current receive RF gain for the selected channel. */
|
||||
int32_t ad9361_get_rx_rf_gain (struct ad9361_rf_phy *phy, uint8_t ch,
|
||||
int32_t *gain_db);
|
||||
/* Set the RX RF bandwidth. */
|
||||
int32_t ad9361_set_rx_rf_bandwidth (struct ad9361_rf_phy *phy,
|
||||
uint32_t bandwidth_hz);
|
||||
/* Get the RX RF bandwidth. */
|
||||
int32_t ad9361_get_rx_rf_bandwidth (struct ad9361_rf_phy *phy,
|
||||
uint32_t *bandwidth_hz);
|
||||
/* Set the RX sampling frequency. */
|
||||
int32_t ad9361_set_rx_sampling_freq (struct ad9361_rf_phy *phy,
|
||||
uint32_t sampling_freq_hz);
|
||||
/* Get current RX sampling frequency. */
|
||||
int32_t ad9361_get_rx_sampling_freq (struct ad9361_rf_phy *phy,
|
||||
uint32_t *sampling_freq_hz);
|
||||
/* Set the RX LO frequency. */
|
||||
int32_t ad9361_set_rx_lo_freq (struct ad9361_rf_phy *phy, uint64_t lo_freq_hz);
|
||||
/* Get current RX LO frequency. */
|
||||
int32_t ad9361_get_rx_lo_freq (struct ad9361_rf_phy *phy, uint64_t *lo_freq_hz);
|
||||
/* Switch between internal and external LO. */
|
||||
int32_t ad9361_set_rx_lo_int_ext(struct ad9361_rf_phy *phy, uint8_t int_ext);
|
||||
/* Get the RSSI for the selected channel. */
|
||||
int32_t ad9361_get_rx_rssi (struct ad9361_rf_phy *phy, uint8_t ch,
|
||||
struct rf_rssi *rssi);
|
||||
/* Set the gain control mode for the selected channel. */
|
||||
int32_t ad9361_set_rx_gain_control_mode (struct ad9361_rf_phy *phy, uint8_t ch,
|
||||
uint8_t gc_mode);
|
||||
/* Get the gain control mode for the selected channel. */
|
||||
int32_t ad9361_get_rx_gain_control_mode (struct ad9361_rf_phy *phy, uint8_t ch,
|
||||
uint8_t *gc_mode);
|
||||
/* Set the RX FIR filter configuration. */
|
||||
int32_t ad9361_set_rx_fir_config (struct ad9361_rf_phy *phy,
|
||||
AD9361_RXFIRConfig fir_cfg);
|
||||
/* Get the RX FIR filter configuration. */
|
||||
int32_t ad9361_get_rx_fir_config(struct ad9361_rf_phy *phy, uint8_t rx_ch,
|
||||
AD9361_RXFIRConfig *fir_cfg);
|
||||
/* Enable/disable the RX FIR filter. */
|
||||
int32_t ad9361_set_rx_fir_en_dis (struct ad9361_rf_phy *phy, uint8_t en_dis);
|
||||
/* Get the status of the RX FIR filter. */
|
||||
int32_t ad9361_get_rx_fir_en_dis (struct ad9361_rf_phy *phy, uint8_t *en_dis);
|
||||
/* Enable/disable the RX RFDC Tracking. */
|
||||
int32_t ad9361_set_rx_rfdc_track_en_dis (struct ad9361_rf_phy *phy,
|
||||
uint8_t en_dis);
|
||||
/* Get the status of the RX RFDC Tracking. */
|
||||
int32_t ad9361_get_rx_rfdc_track_en_dis (struct ad9361_rf_phy *phy,
|
||||
uint8_t *en_dis);
|
||||
/* Enable/disable the RX BasebandDC Tracking. */
|
||||
int32_t ad9361_set_rx_bbdc_track_en_dis (struct ad9361_rf_phy *phy,
|
||||
uint8_t en_dis);
|
||||
/* Get the status of the RX BasebandDC Tracking. */
|
||||
int32_t ad9361_get_rx_bbdc_track_en_dis (struct ad9361_rf_phy *phy,
|
||||
uint8_t *en_dis);
|
||||
/* Enable/disable the RX Quadrature Tracking. */
|
||||
int32_t ad9361_set_rx_quad_track_en_dis (struct ad9361_rf_phy *phy,
|
||||
uint8_t en_dis);
|
||||
/* Get the status of the RX Quadrature Tracking. */
|
||||
int32_t ad9361_get_rx_quad_track_en_dis (struct ad9361_rf_phy *phy,
|
||||
uint8_t *en_dis);
|
||||
/* Set the RX RF input port. */
|
||||
int32_t ad9361_set_rx_rf_port_input (struct ad9361_rf_phy *phy, uint32_t mode);
|
||||
/* Get the selected RX RF input port. */
|
||||
int32_t ad9361_get_rx_rf_port_input (struct ad9361_rf_phy *phy, uint32_t *mode);
|
||||
/* Store RX fastlock profile. */
|
||||
int32_t ad9361_rx_fastlock_store(struct ad9361_rf_phy *phy, uint32_t profile);
|
||||
/* Recall RX fastlock profile. */
|
||||
int32_t ad9361_rx_fastlock_recall(struct ad9361_rf_phy *phy, uint32_t profile);
|
||||
/* Load RX fastlock profile. */
|
||||
int32_t ad9361_rx_fastlock_load(struct ad9361_rf_phy *phy, uint32_t profile,
|
||||
uint8_t *values);
|
||||
/* Save RX fastlock profile. */
|
||||
int32_t ad9361_rx_fastlock_save(struct ad9361_rf_phy *phy, uint32_t profile,
|
||||
uint8_t *values);
|
||||
/* Power down the RX Local Oscillator. */
|
||||
int32_t ad9361_rx_lo_powerdown(struct ad9361_rf_phy *phy, uint8_t option);
|
||||
/* Get the RX Local Oscillator power status. */
|
||||
int32_t ad9361_get_rx_lo_power(struct ad9361_rf_phy *phy, uint8_t *option);
|
||||
/* Set the transmit attenuation for the selected channel. */
|
||||
int32_t ad9361_set_tx_attenuation (struct ad9361_rf_phy *phy, uint8_t ch,
|
||||
uint32_t attenuation_mdb);
|
||||
/* Get current transmit attenuation for the selected channel. */
|
||||
int32_t ad9361_get_tx_attenuation (struct ad9361_rf_phy *phy, uint8_t ch,
|
||||
uint32_t *attenuation_mdb);
|
||||
/* Set the TX RF bandwidth. */
|
||||
int32_t ad9361_set_tx_rf_bandwidth (struct ad9361_rf_phy *phy,
|
||||
uint32_t bandwidth_hz);
|
||||
/* Get the TX RF bandwidth. */
|
||||
int32_t ad9361_get_tx_rf_bandwidth (struct ad9361_rf_phy *phy,
|
||||
uint32_t *bandwidth_hz);
|
||||
/* Set the TX sampling frequency. */
|
||||
int32_t ad9361_set_tx_sampling_freq (struct ad9361_rf_phy *phy,
|
||||
uint32_t sampling_freq_hz);
|
||||
/* Get current TX sampling frequency. */
|
||||
int32_t ad9361_get_tx_sampling_freq (struct ad9361_rf_phy *phy,
|
||||
uint32_t *sampling_freq_hz);
|
||||
/* Set the TX LO frequency. */
|
||||
int32_t ad9361_set_tx_lo_freq (struct ad9361_rf_phy *phy, uint64_t lo_freq_hz);
|
||||
/* Get current TX LO frequency. */
|
||||
int32_t ad9361_get_tx_lo_freq (struct ad9361_rf_phy *phy, uint64_t *lo_freq_hz);
|
||||
/* Switch between internal and external LO. */
|
||||
int32_t ad9361_set_tx_lo_int_ext(struct ad9361_rf_phy *phy, uint8_t int_ext);
|
||||
/* Set the TX FIR filter configuration. */
|
||||
int32_t ad9361_set_tx_fir_config (struct ad9361_rf_phy *phy,
|
||||
AD9361_TXFIRConfig fir_cfg);
|
||||
/* Get the TX FIR filter configuration. */
|
||||
int32_t ad9361_get_tx_fir_config(struct ad9361_rf_phy *phy, uint8_t tx_ch,
|
||||
AD9361_TXFIRConfig *fir_cfg);
|
||||
/* Enable/disable the TX FIR filter. */
|
||||
int32_t ad9361_set_tx_fir_en_dis (struct ad9361_rf_phy *phy, uint8_t en_dis);
|
||||
/* Get the status of the TX FIR filter. */
|
||||
int32_t ad9361_get_tx_fir_en_dis (struct ad9361_rf_phy *phy, uint8_t *en_dis);
|
||||
/* Get the TX RSSI for the selected channel. */
|
||||
int32_t ad9361_get_tx_rssi (struct ad9361_rf_phy *phy, uint8_t ch,
|
||||
uint32_t *rssi_db_x_1000);
|
||||
/* Set the TX RF output port. */
|
||||
int32_t ad9361_set_tx_rf_port_output (struct ad9361_rf_phy *phy, uint32_t mode);
|
||||
/* Get the selected TX RF output port. */
|
||||
int32_t ad9361_get_tx_rf_port_output (struct ad9361_rf_phy *phy,
|
||||
uint32_t *mode);
|
||||
/* Enable/disable the auto calibration. */
|
||||
int32_t ad9361_set_tx_auto_cal_en_dis (struct ad9361_rf_phy *phy,
|
||||
uint8_t en_dis);
|
||||
/* Get the status of the auto calibration flag. */
|
||||
int32_t ad9361_get_tx_auto_cal_en_dis (struct ad9361_rf_phy *phy,
|
||||
uint8_t *en_dis);
|
||||
/* Store TX fastlock profile. */
|
||||
int32_t ad9361_tx_fastlock_store(struct ad9361_rf_phy *phy, uint32_t profile);
|
||||
/* Recall TX fastlock profile. */
|
||||
int32_t ad9361_tx_fastlock_recall(struct ad9361_rf_phy *phy, uint32_t profile);
|
||||
/* Load TX fastlock profile. */
|
||||
int32_t ad9361_tx_fastlock_load(struct ad9361_rf_phy *phy, uint32_t profile,
|
||||
uint8_t *values);
|
||||
/* Save TX fastlock profile. */
|
||||
int32_t ad9361_tx_fastlock_save(struct ad9361_rf_phy *phy, uint32_t profile,
|
||||
uint8_t *values);
|
||||
/* Power down the TX Local Oscillator. */
|
||||
int32_t ad9361_tx_lo_powerdown(struct ad9361_rf_phy *phy, uint8_t option);
|
||||
/* Get the TX Local Oscillator power status. */
|
||||
int32_t ad9361_get_tx_lo_power(struct ad9361_rf_phy *phy, uint8_t *option);
|
||||
/* Set the RX and TX path rates. */
|
||||
int32_t ad9361_set_trx_path_clks(struct ad9361_rf_phy *phy,
|
||||
uint32_t *rx_path_clks, uint32_t *tx_path_clks);
|
||||
/* Get the RX and TX path rates. */
|
||||
int32_t ad9361_get_trx_path_clks(struct ad9361_rf_phy *phy,
|
||||
uint32_t *rx_path_clks, uint32_t *tx_path_clks);
|
||||
/* Set the number of channels mode. */
|
||||
int32_t ad9361_set_no_ch_mode(struct ad9361_rf_phy *phy, uint8_t no_ch_mode);
|
||||
/* Do multi chip synchronization. */
|
||||
int32_t ad9361_do_mcs(struct ad9361_rf_phy *phy_master,
|
||||
struct ad9361_rf_phy *phy_slave);
|
||||
/* Enable/disable the TRX FIR filters. */
|
||||
int32_t ad9361_set_trx_fir_en_dis (struct ad9361_rf_phy *phy, uint8_t en_dis);
|
||||
/* Set the OSR rate governor. */
|
||||
int32_t ad9361_set_trx_rate_gov (struct ad9361_rf_phy *phy, uint32_t rate_gov);
|
||||
/* Get the OSR rate governor. */
|
||||
int32_t ad9361_get_trx_rate_gov (struct ad9361_rf_phy *phy, uint32_t *rate_gov);
|
||||
/* Perform the selected calibration. */
|
||||
int32_t ad9361_do_calib(struct ad9361_rf_phy *phy, uint32_t cal, int32_t arg);
|
||||
/* Load and enable TRX FIR filters configurations. */
|
||||
int32_t ad9361_trx_load_enable_fir(struct ad9361_rf_phy *phy,
|
||||
AD9361_RXFIRConfig rx_fir_cfg,
|
||||
AD9361_TXFIRConfig tx_fir_cfg);
|
||||
/* Do DCXO coarse tuning. */
|
||||
int32_t ad9361_do_dcxo_tune_coarse(struct ad9361_rf_phy *phy,
|
||||
uint32_t coarse);
|
||||
/* Do DCXO fine tuning. */
|
||||
int32_t ad9361_do_dcxo_tune_fine(struct ad9361_rf_phy *phy,
|
||||
uint32_t fine);
|
||||
/* Get the temperature. */
|
||||
int32_t ad9361_get_temperature(struct ad9361_rf_phy *phy,
|
||||
int32_t *temp);
|
||||
#endif
|
||||
+86
@@ -0,0 +1,86 @@
|
||||
|
||||
/***************************************************************************//**
|
||||
* @file ad9361_conv.c
|
||||
* @brief Implementation of AD9361 Conv Driver.
|
||||
********************************************************************************
|
||||
* Copyright 2014-2015(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
#include <inttypes.h>
|
||||
#include <string.h>
|
||||
#include "ad9361.h"
|
||||
#include "ad9361_util.h"
|
||||
#include "../../../../app_config.h"
|
||||
#include "../../../include/delay.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/********************** Macros and Constants Definitions **********************/
|
||||
/******************************************************************************/
|
||||
|
||||
/**
|
||||
* HDL loopback enable/disable.
|
||||
* @param phy The AD9361 state structure.
|
||||
* @param enable Enable/disable option.
|
||||
* @return 0 in case of success, negative error code otherwise.
|
||||
*/
|
||||
int32_t ad9361_hdl_loopback(struct ad9361_rf_phy *phy, bool enable)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/**
|
||||
* Digital tune.
|
||||
* @param phy The AD9361 state structure.
|
||||
* @param max_freq Maximum frequency.
|
||||
* @param flags Flags: BE_VERBOSE, BE_MOREVERBOSE, DO_IDELAY, DO_ODELAY.
|
||||
* @return 0 in case of success, negative error code otherwise.
|
||||
*/
|
||||
int32_t ad9361_dig_tune(struct ad9361_rf_phy *phy, uint32_t max_freq,
|
||||
enum dig_tune_flags flags)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Setup the AD9361 device.
|
||||
* @param phy The AD9361 state structure.
|
||||
* @return 0 in case of success, negative error code otherwise.
|
||||
*/
|
||||
int32_t ad9361_post_setup(struct ad9361_rf_phy *phy)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
+335
@@ -0,0 +1,335 @@
|
||||
/***************************************************************************//**
|
||||
* @file ad9361_util.c
|
||||
* @brief AD9361 Implementation of Util Driver.
|
||||
* @author DBogdan (dragos.bogdan@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2013(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
#include <string.h>
|
||||
#include "ad9361_util.h"
|
||||
#include "../../../include/delay.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/*************************** Macros Definitions *******************************/
|
||||
/******************************************************************************/
|
||||
#define BITS_PER_LONG 32
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief clk_prepare_enable
|
||||
*******************************************************************************/
|
||||
int32_t clk_prepare_enable(struct clk *clk)
|
||||
{
|
||||
if (clk) {
|
||||
// Unused variable - fix compiler warning
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief clk_get_rate
|
||||
*******************************************************************************/
|
||||
uint32_t clk_get_rate(struct ad9361_rf_phy *phy,
|
||||
struct refclk_scale *clk_priv)
|
||||
{
|
||||
uint32_t rate = 0;
|
||||
uint32_t source;
|
||||
|
||||
source = clk_priv->source;
|
||||
|
||||
switch (source) {
|
||||
case TX_REFCLK:
|
||||
case RX_REFCLK:
|
||||
case BB_REFCLK:
|
||||
rate = ad9361_clk_factor_recalc_rate(clk_priv,
|
||||
phy->clk_refin->rate);
|
||||
break;
|
||||
case TX_RFPLL_INT:
|
||||
case RX_RFPLL_INT:
|
||||
rate = ad9361_rfpll_int_recalc_rate(clk_priv,
|
||||
phy->clks[clk_priv->parent_source]->rate);
|
||||
break;
|
||||
case RX_RFPLL_DUMMY:
|
||||
case TX_RFPLL_DUMMY:
|
||||
rate = ad9361_rfpll_dummy_recalc_rate(clk_priv);
|
||||
break;
|
||||
case TX_RFPLL:
|
||||
case RX_RFPLL:
|
||||
rate = ad9361_rfpll_recalc_rate(clk_priv);
|
||||
break;
|
||||
case BBPLL_CLK:
|
||||
rate = ad9361_bbpll_recalc_rate(clk_priv,
|
||||
phy->clks[clk_priv->parent_source]->rate);
|
||||
break;
|
||||
case ADC_CLK:
|
||||
case R2_CLK:
|
||||
case R1_CLK:
|
||||
case CLKRF_CLK:
|
||||
case RX_SAMPL_CLK:
|
||||
case DAC_CLK:
|
||||
case T2_CLK:
|
||||
case T1_CLK:
|
||||
case CLKTF_CLK:
|
||||
case TX_SAMPL_CLK:
|
||||
rate = ad9361_clk_factor_recalc_rate(clk_priv,
|
||||
phy->clks[clk_priv->parent_source]->rate);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return rate;
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief clk_set_rate
|
||||
*******************************************************************************/
|
||||
int32_t clk_set_rate(struct ad9361_rf_phy *phy,
|
||||
struct refclk_scale *clk_priv,
|
||||
uint32_t rate)
|
||||
{
|
||||
uint32_t source;
|
||||
int32_t i;
|
||||
uint32_t round_rate;
|
||||
|
||||
source = clk_priv->source;
|
||||
if(phy->clks[source]->rate != rate)
|
||||
{
|
||||
switch (source) {
|
||||
case TX_REFCLK:
|
||||
case RX_REFCLK:
|
||||
case BB_REFCLK:
|
||||
round_rate = ad9361_clk_factor_round_rate(clk_priv, rate,
|
||||
&phy->clk_refin->rate);
|
||||
ad9361_clk_factor_set_rate(clk_priv, round_rate,
|
||||
phy->clk_refin->rate);
|
||||
phy->clks[source]->rate = ad9361_clk_factor_recalc_rate(clk_priv,
|
||||
phy->clk_refin->rate);
|
||||
break;
|
||||
case TX_RFPLL_INT:
|
||||
case RX_RFPLL_INT:
|
||||
round_rate = ad9361_rfpll_int_round_rate(clk_priv, rate,
|
||||
&phy->clks[clk_priv->parent_source]->rate);
|
||||
ad9361_rfpll_int_set_rate(clk_priv, round_rate,
|
||||
phy->clks[clk_priv->parent_source]->rate);
|
||||
phy->clks[source]->rate = ad9361_rfpll_int_recalc_rate(clk_priv,
|
||||
phy->clks[clk_priv->parent_source]->rate);
|
||||
break;
|
||||
case RX_RFPLL_DUMMY:
|
||||
case TX_RFPLL_DUMMY:
|
||||
ad9361_rfpll_dummy_set_rate(clk_priv, rate);
|
||||
break;
|
||||
case TX_RFPLL:
|
||||
case RX_RFPLL:
|
||||
round_rate = ad9361_rfpll_round_rate(clk_priv, rate);
|
||||
ad9361_rfpll_set_rate(clk_priv, round_rate);
|
||||
phy->clks[source]->rate = ad9361_rfpll_recalc_rate(clk_priv);
|
||||
break;
|
||||
case BBPLL_CLK:
|
||||
round_rate = ad9361_bbpll_round_rate(clk_priv, rate,
|
||||
&phy->clks[clk_priv->parent_source]->rate);
|
||||
ad9361_bbpll_set_rate(clk_priv, round_rate,
|
||||
phy->clks[clk_priv->parent_source]->rate);
|
||||
phy->clks[source]->rate = ad9361_bbpll_recalc_rate(clk_priv,
|
||||
phy->clks[clk_priv->parent_source]->rate);
|
||||
phy->bbpll_initialized = true;
|
||||
break;
|
||||
case ADC_CLK:
|
||||
case R2_CLK:
|
||||
case R1_CLK:
|
||||
case CLKRF_CLK:
|
||||
case RX_SAMPL_CLK:
|
||||
case DAC_CLK:
|
||||
case T2_CLK:
|
||||
case T1_CLK:
|
||||
case CLKTF_CLK:
|
||||
case TX_SAMPL_CLK:
|
||||
round_rate = ad9361_clk_factor_round_rate(clk_priv, rate,
|
||||
&phy->clks[clk_priv->parent_source]->rate);
|
||||
ad9361_clk_factor_set_rate(clk_priv, round_rate,
|
||||
phy->clks[clk_priv->parent_source]->rate);
|
||||
phy->clks[source]->rate = ad9361_clk_factor_recalc_rate(clk_priv,
|
||||
phy->clks[clk_priv->parent_source]->rate);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
for(i = BB_REFCLK; i < BBPLL_CLK; i++)
|
||||
{
|
||||
phy->clks[i]->rate = ad9361_clk_factor_recalc_rate(phy->ref_clk_scale[i],
|
||||
phy->clk_refin->rate);
|
||||
}
|
||||
phy->clks[BBPLL_CLK]->rate = ad9361_bbpll_recalc_rate(phy->ref_clk_scale[BBPLL_CLK],
|
||||
phy->clks[phy->ref_clk_scale[BBPLL_CLK]->parent_source]->rate);
|
||||
for(i = ADC_CLK; i < RX_RFPLL_INT; i++)
|
||||
{
|
||||
phy->clks[i]->rate = ad9361_clk_factor_recalc_rate(phy->ref_clk_scale[i],
|
||||
phy->clks[phy->ref_clk_scale[i]->parent_source]->rate);
|
||||
}
|
||||
for(i = RX_RFPLL_INT; i < RX_RFPLL_DUMMY; i++)
|
||||
{
|
||||
phy->clks[i]->rate = ad9361_rfpll_int_recalc_rate(phy->ref_clk_scale[i],
|
||||
phy->clks[phy->ref_clk_scale[i]->parent_source]->rate);
|
||||
}
|
||||
for(i = RX_RFPLL_DUMMY; i < RX_RFPLL; i++)
|
||||
{
|
||||
phy->clks[i]->rate = ad9361_rfpll_dummy_recalc_rate(phy->ref_clk_scale[i]);
|
||||
}
|
||||
for(i = RX_RFPLL; i < NUM_AD9361_CLKS; i++)
|
||||
{
|
||||
phy->clks[i]->rate = ad9361_rfpll_recalc_rate(phy->ref_clk_scale[i]);
|
||||
}
|
||||
} else {
|
||||
if ((source == BBPLL_CLK) && !phy->bbpll_initialized) {
|
||||
round_rate = ad9361_bbpll_round_rate(clk_priv, rate,
|
||||
&phy->clks[clk_priv->parent_source]->rate);
|
||||
ad9361_bbpll_set_rate(clk_priv, round_rate,
|
||||
phy->clks[clk_priv->parent_source]->rate);
|
||||
phy->clks[source]->rate = ad9361_bbpll_recalc_rate(clk_priv,
|
||||
phy->clks[clk_priv->parent_source]->rate);
|
||||
phy->bbpll_initialized = true;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief int_sqrt
|
||||
*******************************************************************************/
|
||||
uint32_t int_sqrt(uint32_t x)
|
||||
{
|
||||
uint32_t b, m, y = 0;
|
||||
|
||||
if (x <= 1)
|
||||
return x;
|
||||
|
||||
m = 1UL << (BITS_PER_LONG - 2);
|
||||
while (m != 0) {
|
||||
b = y + m;
|
||||
y >>= 1;
|
||||
|
||||
if (x >= b) {
|
||||
x -= b;
|
||||
y += m;
|
||||
}
|
||||
m >>= 2;
|
||||
}
|
||||
|
||||
return y;
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief ilog2
|
||||
*******************************************************************************/
|
||||
int32_t ilog2(int32_t x)
|
||||
{
|
||||
int32_t A = !(!(x >> 16));
|
||||
int32_t count = 0;
|
||||
int32_t x_copy = x;
|
||||
|
||||
count = count + (A << 4);
|
||||
|
||||
x_copy = (((~A + 1) & (x >> 16)) + (~(~A + 1) & x));
|
||||
|
||||
A = !(!(x_copy >> 8));
|
||||
count = count + (A << 3);
|
||||
x_copy = (((~A + 1) & (x_copy >> 8)) + (~(~A + 1) & x_copy));
|
||||
|
||||
A = !(!(x_copy >> 4));
|
||||
count = count + (A << 2);
|
||||
x_copy = (((~A + 1) & (x_copy >> 4)) + (~(~A + 1) & x_copy));
|
||||
|
||||
A = !(!(x_copy >> 2));
|
||||
count = count + (A << 1);
|
||||
x_copy = (((~A + 1) & (x_copy >> 2)) + (~(~A + 1) & x_copy));
|
||||
|
||||
A = !(!(x_copy >> 1));
|
||||
count = count + A;
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief find_first_bit
|
||||
*******************************************************************************/
|
||||
uint32_t find_first_bit(uint32_t word)
|
||||
{
|
||||
int32_t num = 0;
|
||||
|
||||
if ((word & 0xffff) == 0) {
|
||||
num += 16;
|
||||
word >>= 16;
|
||||
}
|
||||
if ((word & 0xff) == 0) {
|
||||
num += 8;
|
||||
word >>= 8;
|
||||
}
|
||||
if ((word & 0xf) == 0) {
|
||||
num += 4;
|
||||
word >>= 4;
|
||||
}
|
||||
if ((word & 0x3) == 0) {
|
||||
num += 2;
|
||||
word >>= 2;
|
||||
}
|
||||
if ((word & 0x1) == 0)
|
||||
num += 1;
|
||||
return num;
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief ERR_PTR
|
||||
*******************************************************************************/
|
||||
void * ERR_PTR(long error)
|
||||
{
|
||||
return (void *) error;
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief zmalloc
|
||||
*******************************************************************************/
|
||||
void *zmalloc(size_t size)
|
||||
{
|
||||
void *ptr = malloc(size);
|
||||
if (ptr)
|
||||
memset(ptr, 0, size);
|
||||
mdelay(1);
|
||||
|
||||
return ptr;
|
||||
}
|
||||
+121
@@ -0,0 +1,121 @@
|
||||
/***************************************************************************//**
|
||||
* @file ad9361_util.h
|
||||
* @brief AD9361 Header file of Util driver.
|
||||
* @author DBogdan (dragos.bogdan@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2013(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
#ifndef __AD9361_UTIL_H__
|
||||
#define __AD9361_UTIL_H__
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
#include <limits.h>
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include "ad9361.h"
|
||||
#include "common.h"
|
||||
#include "../../../../app_config.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/********************** Macros and Constants Definitions **********************/
|
||||
/******************************************************************************/
|
||||
#define CLK_IGNORE_UNUSED BIT(3)
|
||||
#define CLK_GET_RATE_NOCACHE BIT(6)
|
||||
|
||||
#if defined(HAVE_VERBOSE_MESSAGES)
|
||||
#define dev_err(dev, format, ...) ({printf(format, ## __VA_ARGS__);printf("\n"); })
|
||||
#define dev_warn(dev, format, ...) ({printf(format, ## __VA_ARGS__);printf("\n"); })
|
||||
#if defined(HAVE_DEBUG_MESSAGES)
|
||||
#define dev_dbg(dev, format, ...) ({printf(format, ## __VA_ARGS__);printf("\n"); })
|
||||
#else
|
||||
#define dev_dbg(dev, format, ...) ({ if (0) printf(format, ## __VA_ARGS__); })
|
||||
#endif
|
||||
#define printk(format, ...) printf(format, ## __VA_ARGS__)
|
||||
#else
|
||||
#define dev_err(dev, format, ...) ({ if (0) printf(format, ## __VA_ARGS__); })
|
||||
#define dev_warn(dev, format, ...) ({ if (0) printf(format, ## __VA_ARGS__); })
|
||||
#define dev_dbg(dev, format, ...) ({ if (0) printf(format, ## __VA_ARGS__); })
|
||||
#define printk(format, ...) ({ if (0) printf(format, ## __VA_ARGS__); })
|
||||
#endif
|
||||
|
||||
struct device {
|
||||
};
|
||||
|
||||
struct spi_device {
|
||||
struct device dev;
|
||||
uint8_t id_no;
|
||||
};
|
||||
|
||||
struct axiadc_state {
|
||||
struct ad9361_rf_phy *phy;
|
||||
uint32_t pcore_version;
|
||||
};
|
||||
|
||||
struct axiadc_chip_info {
|
||||
char *name;
|
||||
int32_t num_channels;
|
||||
};
|
||||
|
||||
struct axiadc_converter {
|
||||
struct axiadc_chip_info *chip_info;
|
||||
uint32_t scratch_reg[16];
|
||||
};
|
||||
|
||||
#ifdef WIN32
|
||||
#include "basetsd.h"
|
||||
typedef SSIZE_T ssize_t;
|
||||
#define strsep(s, ct) 0
|
||||
#define snprintf(s, n, format, ...) 0
|
||||
#define __func__ __FUNCTION__
|
||||
#endif
|
||||
|
||||
/******************************************************************************/
|
||||
/************************ Functions Declarations ******************************/
|
||||
/******************************************************************************/
|
||||
int32_t clk_prepare_enable(struct clk *clk);
|
||||
uint32_t clk_get_rate(struct ad9361_rf_phy *phy,
|
||||
struct refclk_scale *clk_priv);
|
||||
int32_t clk_set_rate(struct ad9361_rf_phy *phy,
|
||||
struct refclk_scale *clk_priv,
|
||||
uint32_t rate);
|
||||
uint32_t int_sqrt(uint32_t x);
|
||||
int32_t ilog2(int32_t x);
|
||||
uint32_t find_first_bit(uint32_t word);
|
||||
void * ERR_PTR(long error);
|
||||
void *zmalloc(size_t size);
|
||||
|
||||
#endif
|
||||
+66
@@ -0,0 +1,66 @@
|
||||
/***************************************************************************//**
|
||||
* @file common.h
|
||||
* @brief Header file of Common Driver.
|
||||
* @author DBogdan (dragos.bogdan@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2013(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
#ifndef COMMON_H_
|
||||
#define COMMON_H_
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
#include <stdint.h>
|
||||
#include "../../../include/error.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/*************************** Types Declarations *******************************/
|
||||
/******************************************************************************/
|
||||
#if defined (__STDC__) && (__STDC_VERSION__ >= 199901L)
|
||||
#include <stdbool.h>
|
||||
#else
|
||||
typedef enum { false, true } bool;
|
||||
#endif
|
||||
|
||||
struct clk {
|
||||
const char *name;
|
||||
uint32_t rate;
|
||||
};
|
||||
|
||||
struct clk_hw {
|
||||
struct clk *clk;
|
||||
};
|
||||
|
||||
#endif
|
||||
+151
@@ -0,0 +1,151 @@
|
||||
/***************************************************************************//**
|
||||
* @file ad9361_reg.c
|
||||
* @brief Implementation of AD9680 Driver.
|
||||
* @author DBogdan (dragos.bogdan@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2014-2016(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
#include "ad9361_reg.h"
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <stdio.h>
|
||||
#include "../../../include/error.h"
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief ad9361_reg_read
|
||||
*******************************************************************************/
|
||||
int32_t ad9361_reg_read(struct ad9361_reg_dev *dev,
|
||||
uint16_t reg_addr,
|
||||
uint8_t *reg_data)
|
||||
{
|
||||
uint8_t tx_buf[2];
|
||||
uint8_t rx_buf[1];
|
||||
int32_t ret;
|
||||
|
||||
tx_buf[0] = reg_addr >> 8;
|
||||
tx_buf[1] = reg_addr & 0xFF;
|
||||
|
||||
|
||||
ret = spi_write_and_read_3wire(dev->spi_desc,
|
||||
tx_buf, rx_buf, 2, 1);
|
||||
|
||||
*reg_data = rx_buf[0];
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief ad9361_reg_write
|
||||
*******************************************************************************/
|
||||
int32_t ad9361_reg_write(struct ad9361_reg_dev *dev,
|
||||
uint16_t reg_addr,
|
||||
uint8_t reg_data)
|
||||
{
|
||||
uint8_t buf[3];
|
||||
|
||||
int32_t ret;
|
||||
|
||||
buf[0] = 0x80 | reg_addr >> 8;
|
||||
buf[1] = reg_addr & 0xFF;
|
||||
buf[2] = reg_data;
|
||||
|
||||
ret = spi_write_and_read_3wire(dev->spi_desc,
|
||||
buf, NULL, 3, 0);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief ad9361_reg_init
|
||||
*******************************************************************************/
|
||||
int32_t ad9361_reg_init(struct ad9361_reg_dev **device,
|
||||
const struct ad9361_reg_init_param *init_param)
|
||||
{
|
||||
int ret = SUCCESS;
|
||||
struct ad9361_reg_dev *dev;
|
||||
|
||||
dev = (struct ad9361_reg_dev *)malloc(sizeof(*dev));
|
||||
if (!dev)
|
||||
return FAILURE;
|
||||
|
||||
/* SPI */
|
||||
ret = spi_init(&dev->spi_desc, init_param->spi_init);
|
||||
ret |= gpio_get(&dev->gpio_desc_resetb, init_param->gpio_resetb);
|
||||
|
||||
gpio_direction_output(dev->gpio_desc_resetb, 0);
|
||||
|
||||
ad9361_reg_reset(dev);
|
||||
|
||||
*device = dev;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* AD9361 Device Reset
|
||||
* @param phy The AD9361 state structure.
|
||||
* @return 0 in case of success, negative error code otherwise.
|
||||
*/
|
||||
int32_t ad9361_reg_reset(struct ad9361_reg_dev *dev)
|
||||
{
|
||||
if (dev->gpio_desc_resetb) {
|
||||
gpio_set_value(dev->gpio_desc_resetb, 0);
|
||||
mdelay(10);
|
||||
gpio_set_value(dev->gpio_desc_resetb, 1);
|
||||
mdelay(10);
|
||||
return 0;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/***************************************************************************//**
|
||||
* @brief Free the resources allocated by ad9361_reg_setup().
|
||||
*
|
||||
* @param dev - The device structure.
|
||||
*
|
||||
* @return SUCCESS in case of success, negative error code otherwise.
|
||||
*******************************************************************************/
|
||||
int32_t ad9361_reg_remove(struct ad9361_reg_dev *dev)
|
||||
{
|
||||
int32_t ret;
|
||||
|
||||
ret = spi_remove(dev->spi_desc);
|
||||
|
||||
free(dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
+104
@@ -0,0 +1,104 @@
|
||||
/***************************************************************************//**
|
||||
* @file ad9361_reg.h
|
||||
* @brief Header file of ad9361_reg Driver.
|
||||
* @author DBogdan (dragos.bogdan@analog.com)
|
||||
********************************************************************************
|
||||
* Copyright 2014-2016(c) Analog Devices, Inc.
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
* - The use of this software may or may not infringe the patent rights
|
||||
* of one or more patent holders. This license does not release you
|
||||
* from the requirement that you obtain separate licenses from these
|
||||
* patent holders to use this software.
|
||||
* - Use of the software either in source or binary form, must be run
|
||||
* on or directly connected to an Analog Devices Inc. component.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*******************************************************************************/
|
||||
#ifndef ad9361_reg_H_
|
||||
#define ad9361_reg_H_
|
||||
|
||||
/******************************************************************************/
|
||||
/***************************** Include Files **********************************/
|
||||
/******************************************************************************/
|
||||
#include <stdint.h>
|
||||
#include "../../../include/delay.h"
|
||||
#include "../../../include/spi.h"
|
||||
#include "../../../include/gpio.h"
|
||||
|
||||
/******************************************************************************/
|
||||
/********************** Macros and Constants Definitions **********************/
|
||||
/******************************************************************************/
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/*************************** Types Declarations *******************************/
|
||||
/******************************************************************************/
|
||||
struct ad9361_reg_dev {
|
||||
/* SPI */
|
||||
spi_desc *spi_desc;
|
||||
gpio_desc *gpio_desc_resetb;
|
||||
};
|
||||
|
||||
struct ad9361_reg_init_param {
|
||||
/* SPI */
|
||||
spi_init_param *spi_init;
|
||||
gpio_init_param *gpio_resetb;
|
||||
};
|
||||
|
||||
enum Operation_Type{
|
||||
AD9361_WRITE,
|
||||
AD9361_READ,
|
||||
AD9361_WAIT,
|
||||
AD9361_WHEN
|
||||
};
|
||||
|
||||
struct ad9361_reg_config {
|
||||
int operation;
|
||||
uint16_t val1;
|
||||
uint16_t val2;
|
||||
};
|
||||
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/************************ Functions Declarations ******************************/
|
||||
/******************************************************************************/
|
||||
|
||||
int32_t ad9361_reg_read(struct ad9361_reg_dev *dev,
|
||||
uint16_t reg_addr,
|
||||
uint8_t *reg_data);
|
||||
|
||||
int32_t ad9361_reg_write(struct ad9361_reg_dev *dev,
|
||||
uint16_t reg_addr,
|
||||
uint8_t reg_data);
|
||||
|
||||
int32_t ad9361_reg_init(struct ad9361_reg_dev **device,
|
||||
const struct ad9361_reg_init_param *init_param);
|
||||
|
||||
int32_t ad9361_reg_reset(struct ad9361_reg_dev *dev);
|
||||
|
||||
int32_t ad9361_reg_remove(struct ad9361_reg_dev *dev);
|
||||
|
||||
#endif
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user