add sjl_basic

happy new year! microblaze memory is enlarged to 256k

vivado_pvt/.gitattributes

@@ -1,3 +1,4 @@
 *.xsa filter=lfs diff=lfs merge=lfs -text
 *.csv filter=lfs diff=lfs merge=lfs -text
 *.bit filter=lfs diff=lfs merge=lfs -text
+*.dcp filter=lfs diff=lfs merge=lfs -text

vivado_pvt/.gitignore

@@ -57,37 +57,37 @@
 ################################################################################
 
 # include sdk directory and everything in it
-!/projects/*/*/vitis/
+!/projects/*/*/vitis*/
-!/projects/*/*/vitis/**
+!/projects/*/*/vitis*/**
-/projects/*/*/vitis/**.log
+/projects/*/*/vitis*/**.log
-/projects/*/*/vitis/.analytics
+/projects/*/*/vitis*/.analytics
 
 # exclude some obscure hidden SDK folders
-/projects/*/*/vitis/.metadata/
+/projects/*/*/vitis*/.metadata/
-/projects/*/*/vitis/.sdk/
+/projects/*/*/vitis*/.sdk/
-/projects/*/*/vitis/RemoteSystemsTempFiles/
+/projects/*/*/vitis*/RemoteSystemsTempFiles/
-/projects/*/*/vitis/webtalk/
+/projects/*/*/vitis*/webtalk/
 
 # hw_platform: exclude the entire hw_platform folder, as everything can be
 # generated from the .hdf file. Make sure to include the bitstream in the .hdf
 # file when exporting from Vivado!
-/projects/*/*/vitis/*_hw_platform_*/
+/projects/*/*/vitis*/*_hw_platform_*/
 
 # BSP: only keep `.cproject`, `.project`, `.sdkproject`, `.system.mss` and
 # Makefile, ps lib files are regenerated automatically
-/projects/*/*/vitis/*_bsp/*
+/projects/*/*/vitis*/*_bsp/*
-!/projects/*/*/vitis/*_bsp/*.cproject
+!/projects/*/*/vitis*/*_bsp/*.cproject
-!/projects/*/*/vitis/*_bsp/*.project
+!/projects/*/*/vitis*/*_bsp/*.project
-!/projects/*/*/vitis/*_bsp/*.sdkproject
+!/projects/*/*/vitis*/*_bsp/*.sdkproject
-!/projects/*/*/vitis/*_bsp/system.mss
+!/projects/*/*/vitis*/*_bsp/system.mss
-!/projects/*/*/vitis/*_bsp/Makefile
+!/projects/*/*/vitis*/*_bsp/Makefile
 
 # Application: ignored file patterns, exclude Debug & Release folders
-/projects/*/*/vitis/**/*.o
+/projects/*/*/vitis*/**/*.o
-/projects/*/*/vitis/**/*.d
+/projects/*/*/vitis*/**/*.d
-/projects/*/*/vitis/**/*.a
+/projects/*/*/vitis*/**/*.a
-/projects/*/*/vitis/*/Debug/
+/projects/*/*/vitis*/*/Debug/
-/projects/*/*/vitis/*/Release/
+/projects/*/*/vitis*/*/Release/
 
 
 ################################################################################

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.runs/impl_1/system_top.bit

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:c9cea2b093495440187776aa3b2f6ed204eb52d690e7500081f94955d5722d63
+size 9326271

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/constrs_1/new/k7401t_ad9516_2ad9361_physical.xdc

@@ -0,0 +1,220 @@
+# smq7k410t_b9361
+
+## Timing Assertions Section
+
+## Physical Constraints Section
+
+# Clocks
+set_property  -dict  {PACKAGE_PIN L25   IOSTANDARD LVCMOS33}  [get_ports clk_25m                ] ;# CLK_25M
+set_property  -dict  {PACKAGE_PIN F20   IOSTANDARD LVDS_25 }  [get_ports clk_250m_p             ] ;# CLK_250M_P
+set_property  -dict  {PACKAGE_PIN D26   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_buffer_clk    ] ;# B9361_1_CLK_OUT
+set_property  -dict  {PACKAGE_PIN H14   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_buffer_clk    ] ;# B9361_2_CLK_OUT
+
+# HMC7044-1 Interface
+set_property  -dict  {PACKAGE_PIN J23   IOSTANDARD LVCMOS33}  [get_ports ad9516_spi_clk         ] ;# GM4526C_SPI_SCLK
+set_property  -dict  {PACKAGE_PIN M19   IOSTANDARD LVCMOS33}  [get_ports ad9516_spi_csn         ] ;# GM4526C_SPI_CSB
+set_property  -dict  {PACKAGE_PIN L21   IOSTANDARD LVCMOS33}  [get_ports ad9516_spi_mosi        ] ;# GM4526C_SPI_SDIO
+set_property  -dict  {PACKAGE_PIN K23   IOSTANDARD LVCMOS33}  [get_ports ad9516_spi_miso        ] ;# GM4526C_SPI_SDO
+
+set_property  -dict  {PACKAGE_PIN L23   IOSTANDARD LVCMOS33}  [get_ports ad9516_refmon          ] ;# GM4526C_REFMON
+set_property  -dict  {PACKAGE_PIN K24   IOSTANDARD LVCMOS33}  [get_ports ad9516_ld              ] ;# GM4526C_LD
+set_property  -dict  {PACKAGE_PIN J24   IOSTANDARD LVCMOS33}  [get_ports ad9516_status          ] ;# GM4526C_STATUS
+set_property  -dict  {PACKAGE_PIN K21   IOSTANDARD LVCMOS33}  [get_ports ad9516_pd_b            ] ;# GM4526C_PDB
+set_property  -dict  {PACKAGE_PIN L22   IOSTANDARD LVCMOS33}  [get_ports ad9516_reset_b         ] ;# GM4526C_RESETB
+set_property  -dict  {PACKAGE_PIN J21   IOSTANDARD LVCMOS33}  [get_ports ad9516_sync_b          ] ;# GM4526C_SYNCB
+
+# AD9361-1 Interface
+set_property  -dict  {PACKAGE_PIN D27   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_rx_data_clk   ] ;# B9361_1_DATA_CLK
+set_property  -dict  {PACKAGE_PIN B27   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_rx_frame      ] ;# B9361_1_RX_FRAME
+set_property  -dict  {PACKAGE_PIN A23   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_rx_data[0]    ] ;# B9361_1_P0_00_TX0_N
+set_property  -dict  {PACKAGE_PIN B23   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_rx_data[1]    ] ;# B9361_1_P0_01_TX0_P
+set_property  -dict  {PACKAGE_PIN D23   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_rx_data[2]    ] ;# B9361_1_P0_02_TX1_N
+set_property  -dict  {PACKAGE_PIN E23   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_rx_data[3]    ] ;# B9361_1_P0_03_TX1_P
+set_property  -dict  {PACKAGE_PIN D24   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_rx_data[4]    ] ;# B9361_1_P0_04_TX2_N
+set_property  -dict  {PACKAGE_PIN E24   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_rx_data[5]    ] ;# B9361_1_P0_05_TX2_P
+set_property  -dict  {PACKAGE_PIN E25   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_rx_data[6]    ] ;# B9361_1_P0_06_TX3_N
+set_property  -dict  {PACKAGE_PIN F25   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_rx_data[7]    ] ;# B9361_1_P0_07_TX3_P
+set_property  -dict  {PACKAGE_PIN E26   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_rx_data[8]    ] ;# B9361_1_P0_08_TX4_N
+set_property  -dict  {PACKAGE_PIN F26   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_rx_data[9]    ] ;# B9361_1_P0_09_TX4_P
+set_property  -dict  {PACKAGE_PIN G24   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_rx_data[10]   ] ;# B9361_1_P0_10_TX5_N
+set_property  -dict  {PACKAGE_PIN G23   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_rx_data[11]   ] ;# B9361_1_P0_11_TX5_P
+
+set_property  -dict  {PACKAGE_PIN E28   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_tx_fb_clk     ] ;# B9361_1_FB_CLK
+set_property  -dict  {PACKAGE_PIN G27   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_tx_frame      ] ;# B9361_1_TX_FRAME
+set_property  -dict  {PACKAGE_PIN E30   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_tx_data[0]    ] ;# B9361_1_P1_00_RX0_N
+set_property  -dict  {PACKAGE_PIN E29   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_tx_data[1]    ] ;# B9361_1_P1_01_RX0_P
+set_property  -dict  {PACKAGE_PIN C30   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_tx_data[2]    ] ;# B9361_1_P1_02_RX1_N
+set_property  -dict  {PACKAGE_PIN D29   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_tx_data[3]    ] ;# B9361_1_P1_03_RX1_P
+set_property  -dict  {PACKAGE_PIN A30   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_tx_data[4]    ] ;# B9361_1_P1_04_RX2_N
+set_property  -dict  {PACKAGE_PIN B30   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_tx_data[5]    ] ;# B9361_1_P1_05_RX2_P
+set_property  -dict  {PACKAGE_PIN B29   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_tx_data[6]    ] ;# B9361_1_P1_06_RX3_N
+set_property  -dict  {PACKAGE_PIN C29   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_tx_data[7]    ] ;# B9361_1_P1_07_RX3_P
+set_property  -dict  {PACKAGE_PIN F28   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_tx_data[8]    ] ;# B9361_1_P1_08_RX4_N
+set_property  -dict  {PACKAGE_PIN G28   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_tx_data[9]    ] ;# B9361_1_P1_09_RX4_P
+set_property  -dict  {PACKAGE_PIN H25   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_tx_data[10]   ] ;# B9361_1_P1_10_RX5_N
+set_property  -dict  {PACKAGE_PIN H24   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_tx_data[11]   ] ;# B9361_1_P1_11_RX5_P
+
+set_property  -dict  {PACKAGE_PIN H20   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_spi_clk       ] ;# B9361_1_SPI_CLK
+set_property  -dict  {PACKAGE_PIN J18   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_spi_csn       ] ;# B9361_1_SPI_ENB
+set_property  -dict  {PACKAGE_PIN G20   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_spi_mosi      ] ;# B9361_1_SPI_DI
+set_property  -dict  {PACKAGE_PIN G19   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_spi_miso      ] ;# B9361_1_SPI_DO
+
+set_property  -dict  {PACKAGE_PIN K18   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_reset_b       ] ;# B9361_1_RESETB
+set_property  -dict  {PACKAGE_PIN J17   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_en_agc        ] ;# B9361_1_EN_AGC
+set_property  -dict  {PACKAGE_PIN H17   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_enable        ] ;# B9361_1_ENABLE
+set_property  -dict  {PACKAGE_PIN A27   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_txnrx         ] ;# B9361_1_TXNRX
+
+set_property  -dict  {PACKAGE_PIN L18   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_ctrl_in[0]    ] ;# B9361_1_CTRL_IN0
+set_property  -dict  {PACKAGE_PIN H19   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_ctrl_in[1]    ] ;# B9361_1_CTRL_IN1
+set_property  -dict  {PACKAGE_PIN J19   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_ctrl_in[2]    ] ;# B9361_1_CTRL_IN2
+set_property  -dict  {PACKAGE_PIN L17   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_ctrl_in[3]    ] ;# B9361_1_CTRL_IN3
+
+set_property  -dict  {PACKAGE_PIN H21   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_ctrl_out[0]   ] ;# B9361_1_CTRL_OUT0
+set_property  -dict  {PACKAGE_PIN K20   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_ctrl_out[1]   ] ;# B9361_1_CTRL_OUT1
+set_property  -dict  {PACKAGE_PIN H22   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_ctrl_out[2]   ] ;# B9361_1_CTRL_OUT2
+set_property  -dict  {PACKAGE_PIN G22   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_ctrl_out[3]   ] ;# B9361_1_CTRL_OUT3
+set_property  -dict  {PACKAGE_PIN C21   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_ctrl_out[4]   ] ;# B9361_1_CTRL_OUT4
+set_property  -dict  {PACKAGE_PIN F22   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_ctrl_out[5]   ] ;# B9361_1_CTRL_OUT5
+set_property  -dict  {PACKAGE_PIN K19   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_ctrl_out[6]   ] ;# B9361_1_CTRL_OUT6
+set_property  -dict  {PACKAGE_PIN D21   IOSTANDARD LVCMOS18}  [get_ports ad9361_1_ctrl_out[7]   ] ;# B9361_1_CTRL_OUT7
+set_property  -dict  {PACKAGE_PIN D22   IOSTANDARD LVCMOS18}  [get_ports ad9361_sync            ] ;# B9361_SYNC
+
+# AD9361-2 Interface
+set_property  -dict  {PACKAGE_PIN D12   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_rx_data_clk   ] ;# B9361_2_DATA_CLK
+set_property  -dict  {PACKAGE_PIN H15   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_rx_frame      ] ;# B9361_2_RX_FRAME
+set_property  -dict  {PACKAGE_PIN L13   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_rx_data[0]    ] ;# B9361_2_P0_00_TX0_N
+set_property  -dict  {PACKAGE_PIN L12   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_rx_data[1]    ] ;# B9361_2_P0_01_TX0_P
+set_property  -dict  {PACKAGE_PIN K11   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_rx_data[2]    ] ;# B9361_2_P0_02_TX1_N
+set_property  -dict  {PACKAGE_PIN L11   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_rx_data[3]    ] ;# B9361_2_P0_03_TX1_P
+set_property  -dict  {PACKAGE_PIN J13   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_rx_data[4]    ] ;# B9361_2_P0_04_TX2_N
+set_property  -dict  {PACKAGE_PIN K13   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_rx_data[5]    ] ;# B9361_2_P0_05_TX2_P
+set_property  -dict  {PACKAGE_PIN J14   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_rx_data[6]    ] ;# B9361_2_P0_06_TX3_N
+set_property  -dict  {PACKAGE_PIN K14   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_rx_data[7]    ] ;# B9361_2_P0_07_TX3_P
+set_property  -dict  {PACKAGE_PIN K15   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_rx_data[8]    ] ;# B9361_2_P0_08_TX4_N
+set_property  -dict  {PACKAGE_PIN L15   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_rx_data[9]    ] ;# B9361_2_P0_09_TX4_P
+set_property  -dict  {PACKAGE_PIN K16   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_rx_data[10]   ] ;# B9361_2_P0_10_TX5_N
+set_property  -dict  {PACKAGE_PIN L16   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_rx_data[11]   ] ;# B9361_2_P0_11_TX5_P
+
+set_property  -dict  {PACKAGE_PIN F12   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_tx_fb_clk     ] ;# B9361_2_FB_CLK
+set_property  -dict  {PACKAGE_PIN D14   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_tx_frame      ] ;# B9361_2_TX_FRAME
+set_property  -dict  {PACKAGE_PIN E16   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_tx_data[0]    ] ;# B9361_2_P1_00_RX0_N
+set_property  -dict  {PACKAGE_PIN F15   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_tx_data[1]    ] ;# B9361_2_P1_01_RX0_P
+set_property  -dict  {PACKAGE_PIN E15   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_tx_data[2]    ] ;# B9361_2_P1_02_RX1_N
+set_property  -dict  {PACKAGE_PIN E14   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_tx_data[3]    ] ;# B9361_2_P1_03_RX1_P
+set_property  -dict  {PACKAGE_PIN B12   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_tx_data[4]    ] ;# B9361_2_P1_04_RX2_N
+set_property  -dict  {PACKAGE_PIN C12   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_tx_data[5]    ] ;# B9361_2_P1_05_RX2_P
+set_property  -dict  {PACKAGE_PIN A12   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_tx_data[6]    ] ;# B9361_2_P1_06_RX3_N
+set_property  -dict  {PACKAGE_PIN A11   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_tx_data[7]    ] ;# B9361_2_P1_07_RX3_P
+set_property  -dict  {PACKAGE_PIN C11   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_tx_data[8]    ] ;# B9361_2_P1_08_RX4_N
+set_property  -dict  {PACKAGE_PIN D11   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_tx_data[9]    ] ;# B9361_2_P1_09_RX4_P
+set_property  -dict  {PACKAGE_PIN E11   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_tx_data[10]   ] ;# B9361_2_P1_10_RX5_N
+set_property  -dict  {PACKAGE_PIN F11   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_tx_data[11]   ] ;# B9361_2_P1_11_RX5_P
+
+set_property  -dict  {PACKAGE_PIN C16   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_spi_clk       ] ;# B9361_2_SPI_CLK
+set_property  -dict  {PACKAGE_PIN D16   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_spi_csn       ] ;# B9361_2_SPI_ENB
+set_property  -dict  {PACKAGE_PIN C17   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_spi_mosi      ] ;# B9361_2_SPI_DI
+set_property  -dict  {PACKAGE_PIN F18   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_spi_miso      ] ;# B9361_2_SPI_DO
+
+set_property  -dict  {PACKAGE_PIN G18   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_reset_b       ] ;# B9361_2_RESETB
+set_property  -dict  {PACKAGE_PIN D19   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_en_agc        ] ;# B9361_2_EN_AGC
+set_property  -dict  {PACKAGE_PIN E19   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_enable        ] ;# B9361_2_ENABLE
+set_property  -dict  {PACKAGE_PIN G15   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_txnrx         ] ;# B9361_2_TXNRX
+
+set_property  -dict  {PACKAGE_PIN C20   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_ctrl_in[0]    ] ;# B9361_2_CTRL_IN0
+set_property  -dict  {PACKAGE_PIN B17   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_ctrl_in[1]    ] ;# B9361_2_CTRL_IN1
+set_property  -dict  {PACKAGE_PIN G17   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_ctrl_in[2]    ] ;# B9361_2_CTRL_IN2
+set_property  -dict  {PACKAGE_PIN F17   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_ctrl_in[3]    ] ;# B9361_2_CTRL_IN3
+
+set_property  -dict  {PACKAGE_PIN B20   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_ctrl_out[0]   ] ;# B9361_2_CTRL_OUT0
+set_property  -dict  {PACKAGE_PIN A20   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_ctrl_out[1]   ] ;# B9361_2_CTRL_OUT1
+set_property  -dict  {PACKAGE_PIN B18   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_ctrl_out[2]   ] ;# B9361_2_CTRL_OUT2
+set_property  -dict  {PACKAGE_PIN A17   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_ctrl_out[3]   ] ;# B9361_2_CTRL_OUT3
+set_property  -dict  {PACKAGE_PIN A16   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_ctrl_out[4]   ] ;# B9361_2_CTRL_OUT4
+set_property  -dict  {PACKAGE_PIN A18   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_ctrl_out[5]   ] ;# B9361_2_CTRL_OUT5
+set_property  -dict  {PACKAGE_PIN A21   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_ctrl_out[6]   ] ;# B9361_2_CTRL_OUT6
+set_property  -dict  {PACKAGE_PIN B22   IOSTANDARD LVCMOS18}  [get_ports ad9361_2_ctrl_out[7]   ] ;# B9361_2_CTRL_OUT7
+
+# Phased-Array Control
+set_property  -dict  {PACKAGE_PIN T26   IOSTANDARD LVTTL   }  [get_ports ant_cin                ] ;# ANT_CIN0
+set_property  -dict  {PACKAGE_PIN T25   IOSTANDARD LVTTL   }  [get_ports ant_din0               ] ;# ANT_DIN0
+set_property  -dict  {PACKAGE_PIN U25   IOSTANDARD LVTTL   }  [get_ports ant_din1               ] ;# ANT_DIN1
+set_property  -dict  {PACKAGE_PIN U27   IOSTANDARD LVTTL   }  [get_ports ant_cout               ] ;# ANT_COUT0
+set_property  -dict  {PACKAGE_PIN U29   IOSTANDARD LVTTL   }  [get_ports ant_dout0              ] ;# ANT_DOUT0
+set_property  -dict  {PACKAGE_PIN U30   IOSTANDARD LVTTL   }  [get_ports ant_dout1              ] ;# ANT_DOUT1
+set_property  -dict  {PACKAGE_PIN V26   IOSTANDARD LVTTL   }  [get_ports ant_tr                 ] ;# ANT_TR_IN
+set_property  -dict  {PACKAGE_PIN V27   IOSTANDARD LVTTL   }  [get_ports ant_dary               ] ;# ANT_DARY_IN
+
+# RF Synthesizer Control
+set_property  -dict  {PACKAGE_PIN AK29  IOSTANDARD LVTTL   }  [get_ports rf_standby             ] ;# RF_STANDBY
+set_property  -dict  {PACKAGE_PIN AJ28  IOSTANDARD LVTTL   }  [get_ports rf_sw_pll              ] ;# RF_SW_PLL
+set_property  -dict  {PACKAGE_PIN AK30  IOSTANDARD LVTTL   }  [get_ports rf_t                   ] ;# RF_T
+set_property  -dict  {PACKAGE_PIN AG29  IOSTANDARD LVTTL   }  [get_ports rf_r                   ] ;# RF_R
+set_property  -dict  {PACKAGE_PIN AB25  IOSTANDARD LVTTL   }  [get_ports rf_sw_bpf              ] ;# RF_SW_BPF
+set_property  -dict  {PACKAGE_PIN AE28  IOSTANDARD LVTTL   }  [get_ports rf_sclk1               ] ;# RF_SCLK1
+set_property  -dict  {PACKAGE_PIN AA26  IOSTANDARD LVTTL   }  [get_ports rf_sdio1               ] ;# RF_SDIO1
+set_property  -dict  {PACKAGE_PIN AE30  IOSTANDARD LVTTL   }  [get_ports rf_cs1                 ] ;# RF_CS1
+set_property  -dict  {PACKAGE_PIN AH29  IOSTANDARD LVTTL   }  [get_ports rf_ld1                 ] ;# RF_LD1
+set_property  -dict  {PACKAGE_PIN AD28  IOSTANDARD LVTTL   }  [get_ports rf_sclk2               ] ;# RF_SCLK2
+set_property  -dict  {PACKAGE_PIN AD27  IOSTANDARD LVTTL   }  [get_ports rf_sdio2               ] ;# RF_SDIO2
+set_property  -dict  {PACKAGE_PIN AB27  IOSTANDARD LVTTL   }  [get_ports rf_cs2                 ] ;# RF_CS2
+set_property  -dict  {PACKAGE_PIN AC27  IOSTANDARD LVTTL   }  [get_ports rf_ld2                 ] ;# RF_LD2
+set_property  -dict  {PACKAGE_PIN AC30  IOSTANDARD LVTTL   }  [get_ports rf_sclk3               ] ;# RF_SCLK3
+set_property  -dict  {PACKAGE_PIN AE29  IOSTANDARD LVTTL   }  [get_ports rf_sdio3               ] ;# RF_SDIO3
+set_property  -dict  {PACKAGE_PIN AB28  IOSTANDARD LVTTL   }  [get_ports rf_cs3                 ] ;# RF_CS3
+set_property  -dict  {PACKAGE_PIN AD29  IOSTANDARD LVTTL   }  [get_ports rf_ld3                 ] ;# RF_LD3
+set_property  -dict  {PACKAGE_PIN AB30  IOSTANDARD LVTTL   }  [get_ports rf_tmgc_16             ] ;# RF_TMGC_16
+set_property  -dict  {PACKAGE_PIN AC29  IOSTANDARD LVTTL   }  [get_ports rf_tmgc_8              ] ;# RF_TMGC_8
+set_property  -dict  {PACKAGE_PIN AA27  IOSTANDARD LVTTL   }  [get_ports rf_tmgc_4              ] ;# RF_TMGC_4
+set_property  -dict  {PACKAGE_PIN AB29  IOSTANDARD LVTTL   }  [get_ports rf_tmgc_2              ] ;# RF_TMGC_2
+set_property  -dict  {PACKAGE_PIN AA30  IOSTANDARD LVTTL   }  [get_ports rf_tmgc_1              ] ;# RF_TMGC_1
+set_property  -dict  {PACKAGE_PIN AA28  IOSTANDARD LVTTL   }  [get_ports rf_rmgc_16             ] ;# RF_RMGC_16
+set_property  -dict  {PACKAGE_PIN Y28   IOSTANDARD LVTTL   }  [get_ports rf_rmgc_8              ] ;# RF_RMGC_8
+set_property  -dict  {PACKAGE_PIN Y29   IOSTANDARD LVTTL   }  [get_ports rf_rmgc_4              ] ;# RF_RMGC_4
+set_property  -dict  {PACKAGE_PIN Y30   IOSTANDARD LVTTL   }  [get_ports rf_rmgc_2              ] ;# RF_RMGC_2
+set_property  -dict  {PACKAGE_PIN Y26   IOSTANDARD LVTTL   }  [get_ports rf_rmgc_1              ] ;# RF_RMGC_1
+set_property  -dict  {PACKAGE_PIN W28   IOSTANDARD LVTTL   }  [get_ports rf_enable              ] ;# RF_ENABLE
+set_property  -dict  {PACKAGE_PIN AA25  IOSTANDARD LVTTL   }  [get_ports rf_sc                  ] ;# RF_SC
+set_property  -dict  {PACKAGE_PIN W29   IOSTANDARD LVTTL   }  [get_ports rf_sd                  ] ;# RF_SD
+set_property  -dict  {PACKAGE_PIN Y25   IOSTANDARD LVTTL   }  [get_ports rf_endsyn              ] ;# RF_END_SYN
+set_property  -dict  {PACKAGE_PIN W27   IOSTANDARD LVTTL   }  [get_ports rf_sdout               ] ;# RF_SDOUT
+set_property  -dict  {PACKAGE_PIN AF28  IOSTANDARD LVTTL   }  [get_ports rf_dq_wd               ] ;# RF_DQ_WD
+set_property  -dict  {PACKAGE_PIN AF30  IOSTANDARD LVTTL   }  [get_ports rf_sw_rx               ] ;# RF_SW_RX
+
+# LVDS for Time Synchronization
+set_property  -dict  {PACKAGE_PIN J22   IOSTANDARD LVCMOS33}  [get_ports lvds_in_1              ] ;# LVDS_IN1
+set_property  -dict  {PACKAGE_PIN L20   IOSTANDARD LVCMOS33}  [get_ports lvds_out_1             ] ;# LVDS_OUT1
+
+set_property  -dict  {PACKAGE_PIN M20   IOSTANDARD LVCMOS33}  [get_ports lvds_in_2              ] ;# LVDS_IN2
+set_property  -dict  {PACKAGE_PIN J29   IOSTANDARD LVCMOS33}  [get_ports lvds_out_2             ] ;# LVDS_OUT2
+
+# Debug IO
+set_property  -dict  {PACKAGE_PIN U22   IOSTANDARD LVCMOS33}  [get_ports uart1_txd              ] ;# UART_1_TXD
+set_property  -dict  {PACKAGE_PIN V19   IOSTANDARD LVCMOS33}  [get_ports uart1_rxd              ] ;# UART_1_RXD
+set_property  -dict  {PACKAGE_PIN U23   IOSTANDARD LVCMOS33}  [get_ports uart2_txd              ] ;# UART_2_TXD
+set_property  -dict  {PACKAGE_PIN V20   IOSTANDARD LVCMOS33}  [get_ports uart2_rxd              ] ;# UART_2_RXD
+set_property  -dict  {PACKAGE_PIN U24   IOSTANDARD LVCMOS33}  [get_ports uart3_txd              ] ;# UART_3_TXD
+set_property  -dict  {PACKAGE_PIN V21   IOSTANDARD LVCMOS33}  [get_ports uart3_rxd              ] ;# UART_3_RXD
+
+set_property  -dict  {PACKAGE_PIN V25   IOSTANDARD LVCMOS33}  [get_ports debug_io_1             ] ;# DEBUG_IO_1
+set_property  -dict  {PACKAGE_PIN W21   IOSTANDARD LVCMOS33}  [get_ports debug_io_2             ] ;# DEBUG_IO_2
+set_property  -dict  {PACKAGE_PIN W26   IOSTANDARD LVCMOS33}  [get_ports debug_io_3             ] ;# DEBUG_IO_3
+set_property  -dict  {PACKAGE_PIN V22   IOSTANDARD LVCMOS33}  [get_ports debug_io_4             ] ;# DEBUG_IO_4
+set_property  -dict  {PACKAGE_PIN V24   IOSTANDARD LVCMOS33}  [get_ports debug_io_5             ] ;# DEBUG_IO_5
+set_property  -dict  {PACKAGE_PIN W22   IOSTANDARD LVCMOS33}  [get_ports debug_io_6             ] ;# DEBUG_IO_6
+set_property  -dict  {PACKAGE_PIN W24   IOSTANDARD LVCMOS33}  [get_ports debug_io_7             ] ;# DEBUG_IO_7
+set_property  -dict  {PACKAGE_PIN W23   IOSTANDARD LVCMOS33}  [get_ports debug_io_8             ] ;# DEBUG_IO_8
+
+set_property  -dict  {PACKAGE_PIN Y23   IOSTANDARD LVDS_25 }  [get_ports debug_io_00_p          ] ;# DEBUG_IO_00_P
+set_property  -dict  {PACKAGE_PIN Y21   IOSTANDARD LVDS_25 }  [get_ports debug_io_01_p          ] ;# DEBUG_IO_01_P
+set_property  -dict  {PACKAGE_PIN AA20  IOSTANDARD LVDS_25 }  [get_ports debug_io_02_p          ] ;# DEBUG_IO_02_P
+set_property  -dict  {PACKAGE_PIN AA22  IOSTANDARD LVDS_25 }  [get_ports debug_io_03_p          ] ;# DEBUG_IO_03_P
+set_property  -dict  {PACKAGE_PIN AC20  IOSTANDARD LVDS_25 }  [get_ports debug_io_04_p          ] ;# DEBUG_IO_04_P
+set_property  -dict  {PACKAGE_PIN AD21  IOSTANDARD LVDS_25 }  [get_ports debug_io_05_p          ] ;# DEBUG_IO_05_P
+set_property  -dict  {PACKAGE_PIN AC22  IOSTANDARD LVDS_25 }  [get_ports debug_io_06_p          ] ;# DEBUG_IO_06_P
+set_property  -dict  {PACKAGE_PIN AB22  IOSTANDARD LVDS_25 }  [get_ports debug_io_07_p          ] ;# DEBUG_IO_07_P
+set_property  -dict  {PACKAGE_PIN AC24  IOSTANDARD LVDS_25 }  [get_ports debug_io_08_p          ] ;# DEBUG_IO_08_P
+
+# FLASH
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
+set_property CONFIG_MODE SPIx4 [current_design]

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/constrs_1/new/k7410t_ad9516_2ad9361_timing.xdc

@@ -0,0 +1,4 @@
+set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[9]/C}] -to [get_pins u_rx_pre_process/u_ad9361_phase_cal/ad9361_2_cal_start_d1_reg/D]
+set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[7]/C}] -to [get_pins u_tx_pre_process/ad9361_tx_switch_d1_reg/D]
+set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[10]/C}] -to [get_pins u_rx_pre_process/u_ad9361_phase_cal/ad9361_1_cal_start_d1_reg/D]
+set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[8]/C}] -to [get_pins u_rx_pre_process/u_ad9361_phase_cal/ad9361_recal_d1_reg/D]

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sim_1/new/out_imag.csv

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:608698bb466222716a943421803cceb8633aab062e2e0e22f371400e3366d24a
+size 743640

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sim_1/new/out_real.csv

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:ca7f4f48ab8b2d4f82ad8f3beb225bd6cf5102221db57e7318ff96f6754d9d8e
+size 743640

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sim_1/new/tb_accum.v

@@ -0,0 +1,160 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+//
+// Create Date: 2022/10/30 20:46:26
+// Last Simulate Data: 2023/07/17 15:51
+// Design Name:
+// Module Name: tb_accum
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description: Testbench for [accum_cmplx_mat]
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+// -------------------------------
+// MATLAB Code for data generation
+// -------------------------------
+// COLUMN_NUM = 4;
+// DATA_I_WIDTH = 12;
+// ACC_NUM = 10;
+
+// rng(0);
+// data = rand(4,2)*2-1;
+// d_12b = round(data.*(2^(DATA_I_WIDTH-1)-1));
+// d_12b_cmplx = d_12b(:,1) + 1i*d_12b(:,2);
+// d_12b_cmplx = d_12b_cmplx(end:-1:1,:);
+// d_12b_acorr = d_12b_cmplx*d_12b_cmplx';
+// d_12b_acorr_real_sim = reshape(flip(reshape(real(d_12b_acorr)',1,16)),4,4);
+// d_12b_acorr_imag_sim = reshape(flip(reshape(imag(d_12b_acorr)',1,16)),4,4);
+// d_12b_acorr_real_sim_sum = ACC_NUM*d_12b_acorr_real_sim;
+// d_12b_acorr_imag_sim_sum = ACC_NUM*d_12b_acorr_imag_sim;
+
+
+module tb_accum;
+
+localparam DATA_I_WIDTH  = 24;
+localparam DATA_O_WIDTH = 32;
+localparam ROW_NUM  = 4;
+localparam COL_NUM  = 4;
+localparam ACC_NUM  = 2048;
+
+reg acc_rst = 1'b0;
+
+reg clk = 1'b1;
+reg rst = 1'b1;
+reg din_valid = 'b0;
+
+// reg [ROW_NUM*COL_NUM*DATA_I_WIDTH-1:0] din_real = {
+//  24'd1952708,     24'd1246152,    -24'd2458370,     24'd2283360,
+//  24'd1246152,     24'd5474825,    -24'd1041611,     24'd2493996,
+// -24'd2458370,    -24'd1041611,     24'd3154378,    -24'd2757828,
+//  24'd2283360,     24'd2493996,    -24'd2757828,     24'd2899728
+//  };
+
+//  reg [ROW_NUM*COL_NUM*DATA_I_WIDTH-1:0] din_real = {
+//        24'd0,    -24'd3022886,     -24'd340582,     -24'd669768,
+//  24'd3022886,           24'd0,    -24'd4023023,     24'd3107328,
+//   24'd340582,     24'd4023023,           24'd0,     24'd1241460,
+//   24'd669768,    -24'd3107328,    -24'd1241460,           24'd0
+//  };
+
+
+reg [ROW_NUM*COL_NUM*DATA_I_WIDTH-1:0] din_real = {
+     24'd1952708,     24'd1246152,    -24'd2458370,     24'd2283360,
+     24'd1246152,     24'd5474825,    -24'd1041611,     24'd2493996,
+    -24'd2458370,    -24'd1041611,     24'd3154378,     24'h7F_FFFF,
+     24'd2283360,     24'd2493996,    -24'd2757828,     24'h80_0000
+     };
+
+reg [ROW_NUM*COL_NUM*DATA_I_WIDTH-1:0] din_imag = {
+           24'd0,    -24'd3022886,     -24'd340582,     -24'd669768,
+     24'd3022886,           24'd0,    -24'd4023023,     24'd3107328,
+      24'd340582,     24'd4023023,           24'd0,     24'd1241460,
+      24'd669768,    -24'd3107328,    -24'd1241460,           24'd0
+     };
+
+wire dout_valid;
+wire [ROW_NUM*COL_NUM*DATA_O_WIDTH-1:0] dout_real, dout_imag;
+
+accum_cmplx_mat #(
+    .ROW_NUM        (ROW_NUM),
+    .COL_NUM        (COL_NUM),
+    .DATA_I_WIDTH   (DATA_I_WIDTH),
+    .DATA_O_WIDTH   (DATA_O_WIDTH),
+    .ACC_NUM        (ACC_NUM)
+) u_accum_cmplx_mat
+(
+    // clock & reset
+    .clk        (clk        ),
+    .rst        (rst        ),
+    .acc_rst    (acc_rst    ), // [acc_rst] should assert before accumulation starts
+
+    // input data
+    .din_valid  (din_valid  ),
+    .din_real   (din_real   ),
+    .din_imag   (din_imag   ),
+
+    // output data
+    .dout_valid (dout_valid ),
+    .dout_real  (dout_real  ),
+    .dout_imag  (dout_imag  )
+);
+
+
+initial begin
+    #102
+    rst = 1'b0;
+
+    // reset
+    #222
+    acc_rst = 1'b1;
+    #20
+    acc_rst = 1'b0;
+
+    // input data valid lasts [ACC_NUM] clock cycles
+    #222
+    @(posedge clk)
+    #1
+    din_valid = 1'b1;
+
+    #(20*ACC_NUM)
+    din_valid = 1'b0;
+
+    // reset
+    #222
+    acc_rst = 1'b1;
+    #20
+    acc_rst = 1'b0;
+
+    // input data valid lasts [ACC_NUM] clock cycles
+    #222
+    @(posedge clk)
+    #1
+    din_valid = 1'b1;
+
+    #(20*ACC_NUM)
+    din_valid = 1'b0;
+
+    #222
+    $stop;
+end
+
+always #10 clk = ~clk;
+
+
+endmodule

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sim_1/new/tb_acorr.v

@@ -0,0 +1,105 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+//
+// Create Date: 2022/10/30 20:46:26
+// Design Name:
+// Module Name: acorr_tb
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description: Testbench for [acorr_cmplx_col_vec]
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module tb_acorr;
+
+localparam ROW_NUM  = 1;
+localparam COL_NUM  = 4;
+localparam DATA_I_WIDTH  = 12;
+localparam DATA_O_WIDTH  = 23;
+
+reg acc_rst = 1'b0;
+
+reg clk = 1'b1;
+reg rst = 1'b1;
+reg din_valid = 'b0;
+reg [COL_NUM*DATA_I_WIDTH-1:0] din_real = 'b0, din_imag = 'b0;
+
+wire dout_valid;
+wire [COL_NUM*COL_NUM*DATA_O_WIDTH-1:0] dout_real, dout_imag;
+
+acorr_cmplx_col_vec #(
+    .COL_NUM        (COL_NUM),
+    .DATA_I_WIDTH   (DATA_I_WIDTH),
+    .DATA_O_WIDTH   (DATA_O_WIDTH)
+) u_acorr_cmplx_col_vec
+(
+    // clock & reset
+    .clk        (clk        ),
+    .rst        (rst        ),
+
+    // input data
+    .din_valid  (din_valid  ),
+    .din_real   (din_real   ),
+    .din_imag   (din_imag   ),
+
+    // output data
+    .dout_valid (dout_valid ),
+    .dout_real  (dout_real  ),
+    .dout_imag  (dout_imag  )
+);
+
+
+initial begin
+    #102 rst = 1'b0;
+    #222;
+    @(posedge clk)
+    din_valid = 1'b1;
+    din_real = {
+     12'd1351,
+    -12'd1219,
+     12'd1326,
+     12'd1029};
+
+    din_imag = {
+    12'd1538,
+    -12'd1119,
+    12'd1519,
+    12'd1495};
+
+    @(posedge clk)
+    din_valid = 1'b0;
+
+    @(posedge clk)
+    din_valid = 1'b1;
+    din_real = {
+     12'd153 ,
+    -12'd724 ,
+    -12'd1315,
+     12'd433 };
+
+    din_imag = {
+    -12'd1170,
+    12'd981 ,
+    -12'd48  ,
+    12'd1494};
+end
+
+always #10 clk = ~clk;
+
+
+endmodule

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sim_1/new/tb_null_ctrl.v

@@ -0,0 +1,80 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 07/18/2023 11:22:10 AM
+// Design Name:
+// Module Name: tb_null_ctrl
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module tb_null_ctrl;
+
+localparam HOP_CNT_192 = 192*200;
+
+reg clk = 1'b1;
+reg clk_2x = 1'b1;
+reg clk_4x = 1'b1;
+reg rst = 1'b1;
+
+reg hop_flag_in = 1'b0;
+reg sync_flag_phy = 1'b0;
+reg sync_null_en_phy = 1'b1;
+wire hop_flag_out_phy;
+
+null_ctrl u_null_ctrl
+(
+    .clk                (clk                ),
+    .clk_phy            (clk_4x             ),
+    .rst                (rst                ),
+
+    .hop_flag_in_phy    (hop_flag_in        ),
+    .sync_flag_phy      (sync_flag_phy      ),
+    .sync_null_en_phy   (sync_null_en_phy   ),
+    .hop_flag_out_phy   (hop_flag_out_phy   ),
+    .adc_din_valid      (1'b1               )
+);
+
+// clock & reset
+initial begin
+    #102
+    rst = 1'b0;
+end
+
+always #5 clk_4x = ~clk_4x;
+
+always @(posedge clk_4x) begin
+    clk_2x = ~clk_2x;
+end
+
+always @(posedge clk_2x) begin
+    clk = ~clk;
+end
+
+// hop control
+reg [$clog2(HOP_CNT_192)-1 : 0] hop_cnt = 'b0;
+
+always @(posedge clk_4x) begin
+    if (rst) begin
+        hop_cnt <= 'b0;
+        hop_flag_in <= 'b0;
+    end
+    else begin
+        hop_cnt <= (hop_cnt == HOP_CNT_192-1) ? 'b0 : hop_cnt + 1'b1;
+        hop_flag_in <= (hop_cnt == 120) ? 1'b1 : 'b0;
+    end
+end
+
+endmodule

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sim_1/new/tb_rx_pre.m

@@ -0,0 +1,110 @@
+%%%%%%%%%%%%%%%%%%%%%%%%%%
+%本仿真基于以下环境，64元矩形方阵，每若干个阵元通过TR通道和合路器，合成一路子阵信号，然后AD采样进入阵列信号处理单元；
+% - 子阵分割均匀，（16，16，16，16），共有4个子阵
+% - 1个已知方向的期望来波，3个未知方向的干扰信号；
+% - 信干比60dB；
+%θ表示俯仰角（来波与Z轴正向夹角）；φ表示方位角（来波在XOY平面投影与X轴正向夹角）；X轴与阵列每列平行，Y轴与阵列每行平行
+%通过空域滤波得到抑制干扰后的信号
+%%%%%%%%%%%%%%%%%%%%%%%%
+clc;
+clear all;
+Tt=256;%快拍数，用于阵列信号处理的采样点数
+Tmax = 32768;
+t=1:Tmax;
+%%%%%%%%%此处假设来波均为单频信号，可按自身定义修改
+f1=0.1*pi;
+f2=0.2*pi;
+f3=0.3*pi;
+f4=0.4*pi;
+
+%% 通信基带信号
+
+%% 窄带白噪声干扰信号
+filter_name = 'lpf_fs100_fpass5_fstop6.mat';
+%%
+snr=0;%信噪比可根据应用场景确定
+sjr=(60+snr);%干信比
+s1=sqrt(2*10^(snr/10))*exp(1i*f1*t);
+s2=sqrt(2*10^(sjr/10))*exp(1i*f2*t);
+s3=sqrt(2*10^(sjr/10))*exp(1i*f3*t);
+s4=sqrt(2*10^(sjr/10))*exp(1i*f4*t);
+%%%%%%%由信噪比和干信比计算出信号的幅度
+lamuda=1;%当前载频的波长，可根据载频输入实际值d
+d=0.5;%阵元间距，需小于最高工作频率半波长，可根据实际情况输入实际值
+
+theta1=20;%期望来波俯仰角
+phi1=30;%期望来波方位角
+
+theta2=-20;%干扰1俯仰角
+phi2=50;%干扰1方位角
+
+theta3=-40;%干扰2俯仰角
+phi3=80;%干扰2方位角
+
+theta4=-60;%干扰3俯仰角
+phi4=120;%干扰3方位角
+
+%%%%%%%%
+m=8;%列
+n=8;%行
+L=m*n;
+a1=exp(1i*2*pi*d/lamuda*(-(m/2-1/2):1:(m/2-1/2)).'*sin(theta1/180*pi)*sin(phi1/180*pi));
+b1=exp(1i*2*pi*d/lamuda*(-(n/2-1/2):1:(n/2-1/2)).'*sin(theta1/180*pi)*cos(phi1/180*pi));
+A1=kron(b1,a1);
+
+a2=exp(1i*2*pi*d/lamuda*(-(m/2-1/2):1:(m/2-1/2)).'*sin(theta2/180*pi)*sin(phi2/180*pi));
+b2=exp(1i*2*pi*d/lamuda*(-(n/2-1/2):1:(n/2-1/2)).'*sin(theta2/180*pi)*cos(phi2/180*pi));
+A2=kron(b2,a2);
+
+a3=exp(1i*2*pi*d/lamuda*(-(m/2-1/2):1:(m/2-1/2)).'*sin(theta3/180*pi)*sin(phi3/180*pi));
+b3=exp(1i*2*pi*d/lamuda*(-(n/2-1/2):1:(n/2-1/2)).'*sin(theta3/180*pi)*cos(phi3/180*pi));
+A3=kron(b3,a3);
+
+a4=exp(1i*2*pi*d/lamuda*(-(m/2-1/2):1:(m/2-1/2)).'*sin(theta4/180*pi)*sin(phi4/180*pi));
+b4=exp(1i*2*pi*d/lamuda*(-(n/2-1/2):1:(n/2-1/2)).'*sin(theta4/180*pi)*cos(phi4/180*pi));
+A4=kron(b4,a4);
+
+As=[A1,A2,A3,A4];%阵列流型
+rng(0);
+x=As*[s1;s2;s3;s4]+randn(L,Tmax);
+%%%%%%%%%%%%%%%4元子阵
+%
+N1=4;
+C1=zeros(N1,64);
+D1=zeros(N1,64);
+for kk=0:3
+    C1(1,(kk*8+1):(kk*8+4))=ones(1,4);
+    C1(2,(kk*8+5):(kk*8+8))=ones(1,4);
+    C1(3,(kk*8+33):(kk*8+36))=ones(1,4);
+    C1(4,(kk*8+37):(kk*8+40))=ones(1,4);
+end
+%}
+%%%%%%%%%%%%%%%%%%%%%%
+D1=C1*diag(A1');%4元  阵元通道移相后，每16路合路为一个子阵
+% D2=C2*diag(A1');%6元 阵元通道移相后，每(16,8)路合路为一个子阵
+% D3=C3*diag(A1');%8元  阵元通道移相后，每8路合路为一个子阵
+% %%%%%%%%%%%%%%%%%
+xs1=D1*x(:,1:Tt);
+Rx1=xs1*xs1';%4元子阵协方差矩阵
+Ax1=D1*A1;%期望来波方向的子阵导向矢量
+wx1=inv(Rx1)*Ax1/(Ax1'*inv(Rx1)*Ax1);%4子阵的LCMV权值
+
+xs1_long = D1*x;
+s_new1=wx1'*xs1_long;%4子阵情况下的空域滤波后的信号
+% s_new1=[1,1,1,1]*xs1;
+
+%% 数据导出
+xs1_long_12b = round(xs1_long/max(max(abs(xs1_long)))*(2^11-1));
+xs1_real_12b = real(xs1_long_12b);
+xs1_imag_12b = imag(xs1_long_12b);
+
+% writematrix(xs1_real_12b,'./xs1_real.csv');
+% writematrix(xs1_imag_12b,'./xs1_imag.csv');
+
+tb_snap = xs1_long_12b(:,(0:255)+54);
+tb_acorr = tb_snap*tb_snap';
+
+wx1_32b = round(wx1/max(abs(wx1))*(2^31-1));
+wx1_16b = floor(wx1_32b/2^16);
+s_new1_30b = wx1_16b'*xs1_long_12b;
+s_new1_12b = s_new1_30b/2^18;

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sim_1/new/tb_rx_pre.v

@@ -0,0 +1,285 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+//
+// Create Date: 2022/09/15 11:12:45
+// Last Modified Data: 2022/11/02
+// Design Name:
+// Module Name: tb_ad9361_cal
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description: testbench for [rx_pre_process]
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module tb_rx_pre;
+
+localparam COL_NUM = 4;
+localparam PS_PL_WIDTH = 32;
+localparam OUTPUT_DATA_WIDTH = 30;
+
+localparam FRAME_HEAD = 32'h7E7E7E7E;
+localparam FRAME_BITS = (2+COL_NUM*2)*PS_PL_WIDTH;
+
+reg [FRAME_BITS-1 : 0] weight_stream_buf =
+{
+    FRAME_HEAD, 32'd40,
+    -32'd1145474114,  32'd1816473250 ,
+     32'd2059208152, -32'd254581925  ,
+     32'd2062565030,  32'd244279278  ,
+    -32'd1154406364, -32'd1806170603
+};
+
+reg  sys_clk = 1'b1;
+reg  sys_clk_4x = 1'b1;
+reg  sys_rst = 1'b1;
+reg  clk_96m = 1'b1;
+reg  ant_rst = 1'b1;
+
+reg  ad9361_1_cal_start = 'b0;
+wire ad9361_1_cal_done ;
+reg  ad9361_2_cal_start = 'b0;
+wire ad9361_2_cal_done ;
+wire ad9361_cal_result ;
+wire ad9361_cal_valid  ;
+reg  ad9361_recal       = 'b0;
+
+// phase difference of 0 degree
+wire [11:0] rx_ch1_i;
+wire [11:0] rx_ch1_q;
+wire [11:0] rx_ch2_i;
+wire [11:0] rx_ch2_q;
+wire [11:0] rx_ch3_q;
+wire [11:0] rx_ch3_i;
+wire [11:0] rx_ch4_i;
+wire [11:0] rx_ch4_q;
+
+reg  hop_start_flag = 1'b0;
+wire hop_flag_out;
+wire accor_stream_valid;
+wire accor_stream_data;
+wire weight_stream_data;
+wire rx_data_valid;
+wire [OUTPUT_DATA_WIDTH-1:0] rx_data_i, rx_data_q;
+
+rx_pre_process #(
+    .OUTPUT_WIDTH       (OUTPUT_DATA_WIDTH  ),
+    .SYNC_HOP_INTVL     (48*200             )
+) u_rx_pre_process
+(
+    // clock & reset
+    .sys_clk            (sys_clk            ), // input           sys_clk
+    .sys_clk_phy        (sys_clk_4x         ), // input           sys_clk_4x
+    .sys_rst            (sys_rst            ), // input           sys_rst
+    .clk_96m            (clk_96m            ), // input           clk_96m
+    .ant_rst            (ant_rst            ), // input           ant_rst
+    // input data interface
+    .rx_ch1_i           (rx_ch1_i           ), // input   [11:0]  rx_ch1_i
+    .rx_ch1_q           (rx_ch1_q           ), // input   [11:0]  rx_ch1_q
+    .rx_ch2_i           (-rx_ch2_i          ), // input   [11:0]  rx_ch2_i
+    .rx_ch2_q           (-rx_ch2_q          ), // input   [11:0]  rx_ch2_q
+    .rx_ch3_i           (rx_ch3_i           ), // input   [11:0]  rx_ch3_i
+    .rx_ch3_q           (rx_ch3_q           ), // input   [11:0]  rx_ch3_q
+    .rx_ch4_i           (-rx_ch4_i          ), // input   [11:0]  rx_ch4_i
+    .rx_ch4_q           (-rx_ch4_q          ), // input   [11:0]  rx_ch4_q
+    // input channel phase
+    .phase_ch1          ('b0                ),
+    .phase_ch2          ('b0                ),
+    .phase_ch3          ('b0                ),
+    .phase_ch4          ('b0                ),
+    // ad9361 calibration interface
+    .ad9361_1_cal_start (ad9361_1_cal_start ), // input           ad9361_1_cal_start
+    .ad9361_1_cal_done  (ad9361_1_cal_done  ), // output          ad9361_1_cal_done
+    .ad9361_2_cal_start (ad9361_2_cal_start ), // input           ad9361_2_cal_start
+    .ad9361_2_cal_done  (ad9361_2_cal_done  ), // output          ad9361_2_cal_done
+    .ad9361_cal_result  (ad9361_cal_result  ), // output          ad9361_cal_result
+    .ad9361_cal_valid   (ad9361_cal_valid   ), // output          ad9361_cal_valid
+    .ad9361_recal       (ad9361_recal       ), // input           ad9361_recal
+    // nulling algotithm interface
+    .hop_flag_in_phy    (hop_start_flag     ), // input           hop_start_flag
+    .sync_flag_phy      (1'b0               ),
+    .lcmv_en_phy        (1'b1               ),
+    .hop_flag_out       (hop_flag_out       ),
+
+    .accor_stream_valid (accor_stream_valid ), // output          accor_stream_valid
+    .accor_stream_data  (accor_stream_data  ), // output          accor_stream_data
+    .weight_stream_data (weight_stream_data ), // input           weight_stream_data
+    .rx_data_valid      (rx_data_valid      ),
+    .rx_data_i          (rx_data_i          ),
+    .rx_data_q          (rx_data_q          )
+);
+
+// system clock generation
+always begin
+    #6;
+    sys_clk = ~sys_clk;
+    #14;
+end
+
+always begin
+    #5 sys_clk_4x = ~sys_clk_4x;
+end
+
+always begin
+    #7;
+    clk_96m = ~clk_96m;
+    #3;
+end
+
+initial begin
+    #102
+    sys_rst = 1'b0;
+    ant_rst = 1'b0;
+    #100
+    ad9361_1_cal_start = 1'b1;
+end
+
+always @(posedge sys_clk) begin
+    if (ad9361_1_cal_done) begin
+        ad9361_2_cal_start <= 1'b1;
+    end
+    else begin
+        ad9361_2_cal_start <= 1'b0;
+    end
+end
+
+integer r_file_real;
+integer r_file_imag;
+integer w_file_real;
+integer w_file_imag;
+
+reg signed [11:0] rx_ch1_i_data = 'b0, rx_ch1_q_data = 'b0;
+reg signed [11:0] rx_ch2_i_data = 'b0, rx_ch2_q_data = 'b0;
+reg signed [11:0] rx_ch3_i_data = 'b0, rx_ch3_q_data = 'b0;
+reg signed [11:0] rx_ch4_i_data = 'b0, rx_ch4_q_data = 'b0;
+
+reg [11:0] rx_ch1_i_cal  = 12'd2047;
+reg [11:0] rx_ch1_q_cal  = 12'd2047;
+reg [11:0] rx_ch2_i_cal  = -12'd2047;
+reg [11:0] rx_ch2_q_cal  = -12'd2047;
+reg [11:0] rx_ch3_q_cal  = 12'd2047;
+reg [11:0] rx_ch3_i_cal  = 12'd2047;
+reg [11:0] rx_ch4_i_cal  = -12'd2047;
+reg [11:0] rx_ch4_q_cal  = -12'd2047;
+
+assign rx_ch1_i = ad9361_cal_valid ? rx_ch1_i_data : rx_ch1_i_cal;
+assign rx_ch1_q = ad9361_cal_valid ? rx_ch1_q_data : rx_ch1_q_cal;
+assign rx_ch2_i = ad9361_cal_valid ? rx_ch2_i_data : rx_ch2_i_cal;
+assign rx_ch2_q = ad9361_cal_valid ? rx_ch2_q_data : rx_ch2_q_cal;
+assign rx_ch3_i = ad9361_cal_valid ? rx_ch3_i_data : rx_ch3_i_cal;
+assign rx_ch3_q = ad9361_cal_valid ? rx_ch3_q_data : rx_ch3_q_cal;
+assign rx_ch4_i = ad9361_cal_valid ? rx_ch4_i_data : rx_ch4_i_cal;
+assign rx_ch4_q = ad9361_cal_valid ? rx_ch4_q_data : rx_ch4_q_cal;
+
+initial begin
+    forever begin
+        @(posedge sys_clk)
+        // 校准数据
+        #720
+        rx_ch1_i_cal = ~rx_ch1_i_cal;
+        rx_ch2_i_cal = ~rx_ch2_i_cal;
+        rx_ch3_i_cal = ~rx_ch3_i_cal;
+        rx_ch4_i_cal = ~rx_ch4_i_cal;
+        #240
+        rx_ch1_q_cal = ~rx_ch1_q_cal;
+        rx_ch2_q_cal = ~rx_ch2_q_cal;
+        rx_ch3_q_cal = ~rx_ch3_q_cal;
+        rx_ch4_q_cal = ~rx_ch4_q_cal;
+    end
+end
+
+initial begin
+    r_file_real = $fopen("../../../../dl814_k7_cal_coarse.srcs/sim_1/new/xs1_real.csv","r");
+    r_file_imag = $fopen("../../../../dl814_k7_cal_coarse.srcs/sim_1/new/xs1_imag.csv","r");
+
+    w_file_real = $fopen("../../../../dl814_k7_cal_coarse.srcs/sim_1/new/out_real.csv","w");
+    w_file_imag = $fopen("../../../../dl814_k7_cal_coarse.srcs/sim_1/new/out_imag.csv","w");
+
+    @(posedge ad9361_cal_valid)
+
+    forever begin
+        @(posedge sys_clk)
+        $fscanf(r_file_real,"%d,%d,%d,%d",
+            rx_ch1_i_data,
+            rx_ch2_i_data,
+            rx_ch3_i_data,
+            rx_ch4_i_data);
+        $fscanf(r_file_imag,"%d,%d,%d,%d",
+            rx_ch1_q_data,
+            rx_ch2_q_data,
+            rx_ch3_q_data,
+            rx_ch4_q_data);
+        $fdisplay(w_file_real,"%d,%d,%d,%d,%d",
+            $signed(u_rx_pre_process.rx_comp_ch1_i),
+            $signed(u_rx_pre_process.rx_comp_ch2_i),
+            $signed(u_rx_pre_process.rx_comp_ch3_i),
+            $signed(u_rx_pre_process.rx_comp_ch4_i),
+            $signed(rx_data_i));
+        $fdisplay(w_file_imag,"%d,%d,%d,%d,%d",
+            $signed(u_rx_pre_process.rx_comp_ch1_q),
+            $signed(u_rx_pre_process.rx_comp_ch2_q),
+            $signed(u_rx_pre_process.rx_comp_ch3_q),
+            $signed(u_rx_pre_process.rx_comp_ch4_q),
+            $signed(rx_data_q));
+    end
+end
+
+// hop flag counter
+reg [$clog2(38400)-1 : 0] hop_cnt = 'b0;
+
+always @(posedge sys_clk_4x) begin
+    if (sys_rst) begin
+        hop_cnt <= 'b0;
+        hop_start_flag <= 1'b0;
+    end
+    else if (ad9361_cal_valid) begin
+        hop_cnt <= (hop_cnt == 200*48*4-1) ? 'b0 : hop_cnt + 1'b1;
+        hop_start_flag <= (hop_cnt == 127) ? 1'b1 : 1'b0;
+    end
+    else begin
+        hop_cnt <= hop_cnt;
+        hop_start_flag <= hop_start_flag;
+    end
+end
+
+//
+reg weight_stream_valid = 'b0;
+
+always @(negedge accor_stream_valid) begin
+    if (~sys_rst) begin
+        #((48*50)*40+18); // 50us of 48M clock
+        weight_stream_valid = 'b1;
+        #(FRAME_BITS*20);
+        weight_stream_valid = 'b0;
+    end
+end
+
+reg [$clog2(FRAME_BITS)-1 : 0] weight_stream_cnt;
+
+always @(posedge clk_96m) begin
+    if (sys_rst) begin
+        weight_stream_cnt <= 'b0;
+    end
+    else begin
+        weight_stream_cnt <= (weight_stream_valid & ~(weight_stream_cnt == FRAME_BITS - 1)) ? weight_stream_cnt + 1'b1 : 'b0;
+    end
+end
+
+assign weight_stream_data = weight_stream_buf[FRAME_BITS-1-weight_stream_cnt];
+
+endmodule
+

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sim_1/new/tb_rx_pre_test.v

@@ -0,0 +1,278 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+//
+// Create Date: 2022/11/16 15:58:28
+// Design Name:
+// Module Name: tb_rx_pre_test
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description: Co-simulation testbench for [rx_pre_process] and [rx_pre_test]
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module tb_rx_pre_test;
+
+localparam COL_NUM = 4;
+localparam PS_PL_WIDTH = 32;
+
+localparam FRAME_HEAD = 32'h7E7E7E7E;
+localparam FRAME_BITS = (2+COL_NUM*2)*PS_PL_WIDTH;
+
+reg [FRAME_BITS-1 : 0] weight_stream_buf =
+{
+    FRAME_HEAD, 32'd40,
+    -32'd1145474114,  32'd1816473250,
+     32'd2059208152, -32'd254581925 ,
+     32'd2062565030,  32'd244279278 ,
+    -32'd1154406364, -32'd1806170603
+};
+
+reg  sys_clk = 1'b1;
+reg  sys_clk_2x = 1'b1;
+reg  sys_clk_4x = 1'b1;
+reg  sys_rst = 1'b1;
+wire clk_96m;
+wire ant_rst;
+
+reg  ad9361_1_cal_start = 'b0;
+wire ad9361_1_cal_done ;
+reg  ad9361_2_cal_start = 'b0;
+wire ad9361_2_cal_done ;
+wire ad9361_cal_result ;
+wire ad9361_cal_valid  ;
+reg  ad9361_recal       = 'b0;
+
+// phase difference of 0 degree
+reg [11:0] rx_ch1_i = 0, rx_ch1_q = 0;
+reg [11:0] rx_ch2_i = 0, rx_ch2_q = 0;
+reg [11:0] rx_ch3_i = 0, rx_ch3_q = 0;
+reg [11:0] rx_ch4_i = 0, rx_ch4_q = 0;
+
+wire [11:0] rx_ch1_i_test, rx_ch1_q_test;
+wire [11:0] rx_ch2_i_test, rx_ch2_q_test;
+wire [11:0] rx_ch3_i_test, rx_ch3_q_test;
+wire [11:0] rx_ch4_i_test, rx_ch4_q_test;
+
+reg [11:0] rx_ch1_i_cal  = 12'd2047;
+reg [11:0] rx_ch1_q_cal  = 12'd2047;
+reg [11:0] rx_ch2_i_cal  = -12'd2047;
+reg [11:0] rx_ch2_q_cal  = -12'd2047;
+reg [11:0] rx_ch3_q_cal  = 12'd2047;
+reg [11:0] rx_ch3_i_cal  = 12'd2047;
+reg [11:0] rx_ch4_i_cal  = -12'd2047;
+reg [11:0] rx_ch4_q_cal  = -12'd2047;
+
+wire hop_start_flag;
+wire hop_flag_out;
+wire accor_stream_valid;
+wire accor_stream_data;
+wire weight_stream_data;
+wire rx_data_valid;
+wire [29:0] rx_data_i, rx_data_q;
+
+reg hop_trigger = 1'b0;
+
+////////////////////////////////////////////////////////////////////////////////
+/////////////////////////////// Clock Generation ///////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+always #5 sys_clk_4x = ~sys_clk_4x;
+
+always @(posedge sys_clk_4x) begin
+    sys_clk_2x <= ~sys_clk_2x;
+end
+
+always @(posedge sys_clk_2x) begin
+    sys_clk <= ~sys_clk;
+end
+
+assign #3 clk_96m = sys_clk_2x;
+assign #3 ant_rst = sys_rst;
+
+////////////////////////////////////////////////////////////////////////////////
+///////////////////////////// Stimulus Generation //////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+initial begin
+    #102
+    sys_rst = 1'b0;
+    #100
+    ad9361_1_cal_start = 1'b1;
+    wait(ad9361_cal_valid);
+    #1000
+    hop_trigger = 1'b1;
+
+    #(192*200*10) // after 200us, trig again
+    hop_trigger = 1'b0;
+
+    #(192*200*10) // after 200us, trig again
+    hop_trigger = 1'b1;
+
+    #(192*200*10) // after 200us, trig again
+    hop_trigger = 1'b0;
+
+    #(192*200*10) // after 200us, trig again
+    hop_trigger = 1'b1;
+
+    #(192*200*10) // after 200us, trig again
+    hop_trigger = 1'b0;
+
+    #(192*200*10) // after 200us, trig again
+    hop_trigger = 1'b1;
+end
+
+always @(posedge sys_clk) begin
+    if (ad9361_1_cal_done) begin
+        ad9361_2_cal_start <= 1'b1;
+    end
+    else begin
+        ad9361_2_cal_start <= 1'b0;
+    end
+end
+
+always @(posedge sys_clk) begin
+    if (ad9361_cal_valid) begin
+        rx_ch1_i <= rx_ch1_i_test;
+        rx_ch1_q <= rx_ch1_q_test;
+        rx_ch2_i <= rx_ch2_i_test;
+        rx_ch2_q <= rx_ch2_q_test;
+        rx_ch3_i <= rx_ch3_i_test;
+        rx_ch3_q <= rx_ch3_q_test;
+        rx_ch4_i <= rx_ch4_i_test;
+        rx_ch4_q <= rx_ch4_q_test;
+    end
+    else begin
+        rx_ch1_i <= rx_ch1_i_cal;
+        rx_ch1_q <= rx_ch1_q_cal;
+        rx_ch2_i <= rx_ch2_i_cal;
+        rx_ch2_q <= rx_ch2_q_cal;
+        rx_ch3_i <= rx_ch3_i_cal;
+        rx_ch3_q <= rx_ch3_q_cal;
+        rx_ch4_i <= rx_ch4_i_cal;
+        rx_ch4_q <= rx_ch4_q_cal;
+    end
+end
+
+// 校准数据
+always @(posedge sys_clk) begin
+    rx_ch1_i_cal = ~rx_ch1_i_cal;
+    rx_ch1_q_cal = ~rx_ch1_q_cal;
+    rx_ch2_i_cal = ~rx_ch2_i_cal;
+    rx_ch2_q_cal = ~rx_ch2_q_cal;
+    rx_ch3_i_cal = ~rx_ch3_i_cal;
+    rx_ch3_q_cal = ~rx_ch3_q_cal;
+    rx_ch4_i_cal = ~rx_ch4_i_cal;
+    rx_ch4_q_cal = ~rx_ch4_q_cal;
+end
+
+reg weight_stream_valid = 'b0;
+
+always @(negedge accor_stream_valid) begin
+    #((48*50)*40+18); // 50us of 48M clock
+    weight_stream_valid = 'b1;
+    #(FRAME_BITS*20);
+    weight_stream_valid = 'b0;
+end
+
+reg [$clog2(FRAME_BITS)-1 : 0] weight_stream_cnt = FRAME_BITS - 1;
+
+always @(posedge clk_96m) begin
+    if (sys_rst) begin
+        weight_stream_cnt <= FRAME_BITS - 1;
+    end
+    else begin
+        weight_stream_cnt <= (weight_stream_valid & ~(weight_stream_cnt == FRAME_BITS - 1)) ? weight_stream_cnt + 1'b1 : 'b0;
+    end
+end
+
+assign weight_stream_data = weight_stream_buf[FRAME_BITS-1-weight_stream_cnt];
+
+////////////////////////////////////////////////////////////////////////////////
+/////////////////////// Simulation Module Instantiation ////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+
+rx_pre_process #(
+    .OUTPUT_WIDTH       (30                 ),
+    .SYNC_HOP_INTVL     (48*200             )
+) u_rx_pre_process
+(
+    // clock & reset
+    .sys_clk            (sys_clk            ), // sync to adc data
+    .sys_clk_phy        (sys_clk_4x         ), // sync to physical layer
+    .sys_rst            (sys_rst            ), // sync to [sys_clk]
+    .clk_96m            (clk_96m            ), // sync to c2c data
+    .ant_rst            (ant_rst            ), // sync to [clk_96m]
+    // input data interface
+    .rx_ch1_i           (rx_ch1_i           ),
+    .rx_ch1_q           (rx_ch1_q           ),
+    .rx_ch2_i           (rx_ch2_i           ),
+    .rx_ch2_q           (rx_ch2_q           ),
+    .rx_ch3_i           (rx_ch3_i           ),
+    .rx_ch3_q           (rx_ch3_q           ),
+    .rx_ch4_i           (rx_ch4_i           ),
+    .rx_ch4_q           (rx_ch4_q           ),
+    // input channel phase
+    .phase_ch1          ('b0                ),
+    .phase_ch2          ('b0                ),
+    .phase_ch3          ('b0                ),
+    .phase_ch4          ('b0                ),
+    // ad9361 calibration interface
+    .ad9361_1_cal_start (ad9361_1_cal_start ),
+    .ad9361_1_cal_done  (ad9361_1_cal_done  ),
+    .ad9361_2_cal_start (ad9361_2_cal_start ),
+    .ad9361_2_cal_done  (ad9361_2_cal_done  ),
+    .ad9361_cal_result  (ad9361_cal_result  ),
+    .ad9361_cal_valid   (ad9361_cal_valid   ),
+    .ad9361_recal       (ad9361_recal       ),
+    // nulling algotithm interface
+    .hop_flag_in_phy    (hop_start_flag     ), // input           hop_start_flag
+    .sync_flag_phy      (1'b0               ),
+    .lcmv_en_phy        (1'b1               ),
+    .hop_flag_out       (hop_flag_out       ),
+
+    .accor_stream_valid (accor_stream_valid ), // output          accor_stream_valid
+    .accor_stream_data  (accor_stream_data  ), // output          accor_stream_data
+    .weight_stream_data (weight_stream_data ), // input           weight_stream_data
+    .rx_data_valid      (rx_data_valid      ),
+    .rx_data_i          (rx_data_i          ),
+    .rx_data_q          (rx_data_q          )
+);
+
+// temporary test cases
+rx_pre_test u_rx_pre_test
+(
+    // clock & reset
+    .clk                (sys_clk            ),
+    .rst                (sys_rst            ),
+    .clk_phy            (sys_clk_4x         ),
+    .hop_trigger        (hop_trigger        ),
+    .hop_trigger_en     (1'b1               ),
+    // calc result
+    .ad9361_cal_result  (ad9361_cal_result  ),
+    .ad9361_cal_valid   (ad9361_cal_valid   ),
+    // output test data
+    .rx_ch1_i           (rx_ch1_i_test      ),
+    .rx_ch1_q           (rx_ch1_q_test      ),
+    .rx_ch2_i           (rx_ch2_i_test      ),
+    .rx_ch2_q           (rx_ch2_q_test      ),
+    .rx_ch3_i           (rx_ch3_i_test      ),
+    .rx_ch3_q           (rx_ch3_q_test      ),
+    .rx_ch4_i           (rx_ch4_i_test      ),
+    .rx_ch4_q           (rx_ch4_q_test      ),
+    .hop_start_flag     (hop_start_flag     )
+);
+
+endmodule

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sim_1/new/tb_rx_test.m

@@ -0,0 +1,115 @@
+%%%%%%%%%%%%%%%%%%%%%%%%%%
+%本仿真基于以下环境，64元矩形方阵，每若干个阵元通过TR通道和合路器，合成一路子阵信号，然后AD采样进入阵列信号处理单元；
+% - 子阵分割均匀，（16，16，16，16），共有4个子阵
+% - 1个已知方向的期望来波，3个未知方向的干扰信号；
+% - 信干比60dB；
+%θ表示俯仰角（来波与Z轴正向夹角）；φ表示方位角（来波在XOY平面投影与X轴正向夹角）；X轴与阵列每列平行，Y轴与阵列每行平行
+%通过空域滤波得到抑制干扰后的信号
+%%%%%%%%%%%%%%%%%%%%%%%%
+clc;
+clear all;
+Tt=256;%快拍数，用于阵列信号处理的采样点数
+Tmax = 32768;
+t=1:Tmax;
+%%%%%%%%%此处假设来波均为单频信号，可按自身定义修改
+f1=0.1*pi;
+f2=0.2*pi;
+f3=0.3*pi;
+f4=0.4*pi;
+
+%% 通信基带信号
+
+%% 窄带白噪声干扰信号
+filter_name = 'lpf_fs100_fpass5_fstop6.mat';
+%%
+snr=0;%信噪比可根据应用场景确定
+sjr=(60+snr);%干信比
+s1=sqrt(2*10^(snr/10))*exp(1i*f1*t);
+s2=sqrt(2*10^(sjr/10))*exp(1i*f2*t);
+s3=sqrt(2*10^(sjr/10))*exp(1i*f3*t);
+s4=sqrt(2*10^(sjr/10))*exp(1i*f4*t);
+%%%%%%%由信噪比和干信比计算出信号的幅度
+lamuda=1;%当前载频的波长，可根据载频输入实际值d
+d=0.5;%阵元间距，需小于最高工作频率半波长，可根据实际情况输入实际值
+
+theta1=20;%期望来波俯仰角
+phi1=30;%期望来波方位角
+
+theta2=-20;%干扰1俯仰角
+phi2=50;%干扰1方位角
+
+theta3=-40;%干扰2俯仰角
+phi3=80;%干扰2方位角
+
+theta4=-60;%干扰3俯仰角
+phi4=120;%干扰3方位角
+
+%%%%%%%%
+m=8;%列
+n=8;%行
+L=m*n;
+a1=exp(1i*2*pi*d/lamuda*(-(m/2-1/2):1:(m/2-1/2)).'*sin(theta1/180*pi)*sin(phi1/180*pi));
+b1=exp(1i*2*pi*d/lamuda*(-(n/2-1/2):1:(n/2-1/2)).'*sin(theta1/180*pi)*cos(phi1/180*pi));
+A1=kron(b1,a1);
+
+a2=exp(1i*2*pi*d/lamuda*(-(m/2-1/2):1:(m/2-1/2)).'*sin(theta2/180*pi)*sin(phi2/180*pi));
+b2=exp(1i*2*pi*d/lamuda*(-(n/2-1/2):1:(n/2-1/2)).'*sin(theta2/180*pi)*cos(phi2/180*pi));
+A2=kron(b2,a2);
+
+a3=exp(1i*2*pi*d/lamuda*(-(m/2-1/2):1:(m/2-1/2)).'*sin(theta3/180*pi)*sin(phi3/180*pi));
+b3=exp(1i*2*pi*d/lamuda*(-(n/2-1/2):1:(n/2-1/2)).'*sin(theta3/180*pi)*cos(phi3/180*pi));
+A3=kron(b3,a3);
+
+a4=exp(1i*2*pi*d/lamuda*(-(m/2-1/2):1:(m/2-1/2)).'*sin(theta4/180*pi)*sin(phi4/180*pi));
+b4=exp(1i*2*pi*d/lamuda*(-(n/2-1/2):1:(n/2-1/2)).'*sin(theta4/180*pi)*cos(phi4/180*pi));
+A4=kron(b4,a4);
+
+As=[A1,A2,A3,A4];%阵列流型
+rng(0);
+x=As*[s1;s2;s3;s4]+randn(L,Tmax);
+%%%%%%%%%%%%%%%4元子阵
+%
+N1=4;
+C1=zeros(N1,64);
+D1=zeros(N1,64);
+for kk=0:3
+    C1(1,(kk*8+1):(kk*8+4))=ones(1,4);
+    C1(2,(kk*8+5):(kk*8+8))=ones(1,4);
+    C1(3,(kk*8+33):(kk*8+36))=ones(1,4);
+    C1(4,(kk*8+37):(kk*8+40))=ones(1,4);
+end
+%}
+%%%%%%%%%%%%%%%%%%%%%%
+D1=C1*diag(A1');%4元  阵元通道移相后，每16路合路为一个子阵
+% D2=C2*diag(A1');%6元 阵元通道移相后，每(16,8)路合路为一个子阵
+% D3=C3*diag(A1');%8元  阵元通道移相后，每8路合路为一个子阵
+% %%%%%%%%%%%%%%%%%
+xs1=D1*x(:,1:Tt);
+Rx1=xs1*xs1';%4元子阵协方差矩阵
+Ax1=D1*A1;%期望来波方向的子阵导向矢量
+wx1=inv(Rx1)*Ax1/(Ax1'*inv(Rx1)*Ax1);%4子阵的LCMV权值
+
+xs1_long = D1*x;
+s_new1=wx1'*xs1_long;%4子阵情况下的空域滤波后的信号
+% s_new1=[1,1,1,1]*xs1;
+
+%% 数据导出
+xs1_long_12b = round(xs1_long/max(max(abs(xs1_long)))*(2^11-1));
+xs1_real_12b = real(xs1_long_12b);
+xs1_imag_12b = imag(xs1_long_12b);
+
+xs1_12b_bin_join = strings(9600,96);
+
+for i = 1:9600
+    xs1_real_12b_bin = dec2bin(xs1_real_12b(:,i),16);
+    xs1_real_12b_bin_join_tmp = '';
+    xs1_imag_12b_bin = dec2bin(xs1_imag_12b(:,i),16);
+    xs1_imag_12b_bin_join_tmp = '';
+    for j = 1:4
+        xs1_real_12b_bin_trunc = xs1_real_12b_bin(j,5:16);
+        xs1_real_12b_bin_join_tmp = [xs1_real_12b_bin_join_tmp,xs1_real_12b_bin_trunc];
+        xs1_imag_12b_bin_trunc = xs1_imag_12b_bin(j,5:16);
+        xs1_imag_12b_bin_join_tmp = [xs1_imag_12b_bin_join_tmp,xs1_imag_12b_bin_trunc];
+    end
+    xs1_12b_bin_join(i) = [xs1_real_12b_bin_join_tmp,xs1_imag_12b_bin_join_tmp];
+end

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sim_1/new/tb_rx_test.v

@@ -0,0 +1,85 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+//
+// Create Date: 2022/11/16 15:08:02
+// Design Name:
+// Module Name: tb_rx_test
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description: testbench for [rx_pre_test]
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module tb_rx_test;
+
+reg  sys_clk = 1'b1;
+reg  sys_clk_4x = 1'b1;
+reg  sys_rst = 1'b1;
+reg  hop_trigger = 1'b0;
+
+reg ad9361_cal_result = 1'b0;
+reg ad9361_cal_valid = 1'b0;
+
+wire [11:0] rx_ch1_i;
+wire [11:0] rx_ch1_q;
+wire [11:0] rx_ch2_i;
+wire [11:0] rx_ch2_q;
+wire [11:0] rx_ch3_i;
+wire [11:0] rx_ch3_q;
+wire [11:0] rx_ch4_i;
+wire [11:0] rx_ch4_q;
+wire hop_start_flag;
+
+rx_pre_test u_rx_pre_test
+(
+    // clock & reset
+    .clk                (sys_clk            ),
+    .rst                (sys_rst            ),
+    .hop_trigger        (hop_trigger        ),
+    // calc result
+    .ad9361_cal_result  (ad9361_cal_result  ),
+    .ad9361_cal_valid   (ad9361_cal_valid   ),
+    // output test data
+    .rx_ch1_i           (rx_ch1_i           ),
+    .rx_ch1_q           (rx_ch1_q           ),
+    .rx_ch2_i           (rx_ch2_i           ),
+    .rx_ch2_q           (rx_ch2_q           ),
+    .rx_ch3_i           (rx_ch3_i           ),
+    .rx_ch3_q           (rx_ch3_q           ),
+    .rx_ch4_i           (rx_ch4_i           ),
+    .rx_ch4_q           (rx_ch4_q           ),
+    .hop_start_flag     (hop_start_flag     )
+);
+
+// system clock generation
+always begin
+    #5 sys_clk = ~sys_clk;
+end
+
+initial begin
+    #102
+    sys_rst = 1'b0;
+    #100
+    ad9361_cal_valid = 1'b1;
+    #1000
+    hop_trigger = 1'b1;
+    #100
+    hop_trigger = 1'b0;
+end
+
+endmodule

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sim_1/new/tb_tx_pre_process.v

@@ -0,0 +1,93 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+//
+// Create Date: 2023/02/25 15:50:45
+// Design Name:
+// Module Name: tb_tx_pre_process
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module tb_tx_pre_process;
+
+reg clk = 1'b1;
+reg rst = 1'b1;
+
+reg [11:0] tx_data_ch1_i = 'b0;
+reg [11:0] tx_data_ch1_q = 'b0;
+reg [11:0] tx_data_ch2_i = 'b0;
+reg [11:0] tx_data_ch2_q = 'b0;
+
+reg ad9361_tx_switch = 1'b0;
+
+reg [3:0] bb_rshift = 4'd3;
+
+wire [11:0] tx_ch1_i;
+wire [11:0] tx_ch1_q;
+wire [11:0] tx_ch2_i;
+wire [11:0] tx_ch2_q;
+
+tx_pre_process #(
+    .CAL_MOD_FINE   (1  )
+) u_tx_pre_process
+(
+    // clock & reset
+    .clk                (clk                ),
+    .rst                (rst                ),
+    // input data
+    .tx_data_ch1_i      (tx_data_ch1_i      ),
+    .tx_data_ch1_q      (tx_data_ch1_q      ),
+    .tx_data_ch2_i      (tx_data_ch2_i      ),
+    .tx_data_ch2_q      (tx_data_ch2_q      ),
+    // ad9361 calibration interface
+    .ad9361_tx_switch   (ad9361_tx_switch   ),
+    //
+    .bb_rshift          (bb_rshift          ),
+    // output data
+    .tx_ch1_i           (tx_ch1_i           ),
+    .tx_ch1_q           (tx_ch1_q           ),
+    .tx_ch2_i           (tx_ch2_i           ),
+    .tx_ch2_q           (tx_ch2_q           )
+);
+
+initial begin
+    #102 rst = 1'b0;
+    #100 ad9361_tx_switch = 1'b1;
+    #10000 ad9361_tx_switch = 1'b0;
+end
+
+always #10 clk = ~clk;
+
+always @(posedge clk) begin
+    if (rst) begin
+        tx_data_ch1_i <= 'b0;
+        tx_data_ch1_q <= 'b0;
+        tx_data_ch2_i <= 'b0;
+        tx_data_ch2_q <= 'b0;
+    end
+    else begin
+        tx_data_ch1_i <= tx_data_ch1_i + 12'd1;
+        tx_data_ch1_q <= tx_data_ch1_q + 12'd2;
+        tx_data_ch2_i <= tx_data_ch2_i + 12'd3;
+        tx_data_ch2_q <= tx_data_ch2_q + 12'd4;
+    end
+end
+
+endmodule

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sim_1/new/tb_xpm_cdc_pulse.v

@@ -0,0 +1,86 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 03/29/2023 09:02:30 PM
+// Design Name:
+// Module Name: tb_xpm_cdc_pulse
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module tb_xpm_cdc_pulse;
+
+reg sys_clk = 1'b1;
+reg sys_clk_4x = 1'b1;
+reg sys_rst = 1'b1;
+
+reg src_pulse = 1'b0;
+wire dest_pulse;
+
+xpm_cdc_pulse #(
+    .DEST_SYNC_FF   (4), // DECIMAL; range: 2-10
+    .INIT_SYNC_FF   (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
+    .REG_OUTPUT     (1), // DECIMAL; 0=disable registered output, 1=enable registered output
+    .RST_USED       (1), // DECIMAL; 0=no reset, 1=implement reset
+    .SIM_ASSERT_CHK (1)  // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
+) u_xpm_cdc_pulse
+(
+    .dest_pulse (dest_pulse ), // 1-bit output: Outputs a pulse the size of one dest_clk period when a pulse
+                                       // transfer is correctly initiated on src_pulse input. This output is
+                                       // combinatorial unless REG_OUTPUT is set to 1.
+    .dest_clk   (sys_clk    ), // 1-bit input: Destination clock.
+    .dest_rst   (sys_rst    ), // 1-bit input: optional; required when RST_USED = 1
+    .src_clk    (sys_clk_4x ), // 1-bit input: Source clock.
+    .src_pulse  (src_pulse  ), // 1-bit input: Rising edge of this signal initiates a pulse transfer to the
+                               // destination clock domain. The minimum gap between each pulse transfer must be
+                               // at the minimum 2*(larger(src_clk period, dest_clk period)). This is measured
+                               // between the falling edge of a src_pulse to the rising edge of the next
+                               // src_pulse. This minimum gap will guarantee that each rising edge of src_pulse
+                               // will generate a pulse the size of one dest_clk period in the destination
+                               // clock domain. When RST_USED = 1, pulse transfers will not be guaranteed while
+                               // src_rst and/or dest_rst are asserted.
+    .src_rst    (sys_rst    )  // 1-bit input: optional; required when RST_USED = 1
+);
+
+initial begin
+    #102;
+    sys_rst = 1'b0;
+end
+
+always begin
+    #3;
+    sys_clk = ~sys_clk;
+    #37;
+end
+
+always begin
+    #5;
+    sys_clk_4x = ~sys_clk_4x;
+end
+
+reg [3:0] pulse_cnt = 'b0;
+
+always @(posedge sys_clk_4x) begin
+    if (sys_rst) begin
+        src_pulse <= 1'b0;
+        pulse_cnt <= 'b0;
+    end
+    else begin
+        pulse_cnt <= pulse_cnt + 1'b1;
+        src_pulse <= (pulse_cnt == 4'd15) ? 1'b1 : 1'b0;
+    end
+end
+
+endmodule

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ip/system_bd_axi_gpio_0_0/system_bd_axi_gpio_0_0.xci

@@ -0,0 +1,374 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_bd_axi_gpio_0_0",
+    "cell_name": "axi_gpio",
+    "component_reference": "xilinx.com:ip:axi_gpio:2.0",
+    "ip_revision": "32",
+    "gen_directory": "../../../../../../dl814_k7_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_axi_gpio_0_0",
+    "parameters": {
+      "component_parameters": {
+        "C_TRI_DEFAULT": [ { "value": "0xFFFFFFFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_GPIO_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_GPIO2_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_IS_DUAL": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_ALL_INPUTS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_TRI_DEFAULT_2": [ { "value": "0xFFFFFFFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_DOUT_DEFAULT_2": [ { "value": "0x00000000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_DOUT_DEFAULT": [ { "value": "0xFFFFFFFF", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
+        "C_ALL_INPUTS_2": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_INTERRUPT_PRESENT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Component_Name": [ { "value": "system_bd_axi_gpio_0_0", "resolve_type": "user", "usage": "all" } ],
+        "USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "GPIO_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "GPIO2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "C_ALL_OUTPUTS": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_ALL_OUTPUTS_2": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_FAMILY": [ { "value": "kintex7", "resolve_type": "generated", "usage": "all" } ],
+        "C_S_AXI_ADDR_WIDTH": [ { "value": "9", "format": "long", "usage": "all" } ],
+        "C_S_AXI_DATA_WIDTH": [ { "value": "32", "format": "long", "usage": "all" } ],
+        "C_GPIO_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_GPIO2_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ALL_INPUTS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ALL_INPUTS_2": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ALL_OUTPUTS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ALL_OUTPUTS_2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INTERRUPT_PRESENT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DOUT_DEFAULT": [ { "value": "0xFFFFFFFF", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "C_TRI_DEFAULT": [ { "value": "0xFFFFFFFF", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "C_IS_DUAL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DOUT_DEFAULT_2": [ { "value": "0x00000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "C_TRI_DEFAULT_2": [ { "value": "0xFFFFFFFF", "resolve_type": "generated", "format": "bitString", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "kintex7" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7k410t" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "32" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../dl814_k7_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_axi_gpio_0_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2023.2.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "s_axi_aclk": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_aresetn": [ { "direction": "in", "driver_value": "1" } ],
+        "s_axi_awaddr": [ { "direction": "in", "size_left": "8", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_awready": [ { "direction": "out" } ],
+        "s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_wready": [ { "direction": "out" } ],
+        "s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s_axi_bvalid": [ { "direction": "out" } ],
+        "s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_araddr": [ { "direction": "in", "size_left": "8", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_arready": [ { "direction": "out" } ],
+        "s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
+        "s_axi_rvalid": [ { "direction": "out" } ],
+        "s_axi_rready": [ { "direction": "in", "driver_value": "0" } ],
+        "gpio_io_o": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "gpio2_io_i": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ]
+      },
+      "interfaces": {
+        "S_AXI": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "slave",
+          "memory_map_ref": "S_AXI",
+          "parameters": {
+            "DATA_WIDTH": [ { "value": "32", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "25000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "9", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "/clk_wiz_25M_clk_out1", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "ARADDR": [ { "physical_name": "s_axi_araddr" } ],
+            "ARREADY": [ { "physical_name": "s_axi_arready" } ],
+            "ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
+            "AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
+            "AWREADY": [ { "physical_name": "s_axi_awready" } ],
+            "AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
+            "BREADY": [ { "physical_name": "s_axi_bready" } ],
+            "BRESP": [ { "physical_name": "s_axi_bresp" } ],
+            "BVALID": [ { "physical_name": "s_axi_bvalid" } ],
+            "RDATA": [ { "physical_name": "s_axi_rdata" } ],
+            "RREADY": [ { "physical_name": "s_axi_rready" } ],
+            "RRESP": [ { "physical_name": "s_axi_rresp" } ],
+            "RVALID": [ { "physical_name": "s_axi_rvalid" } ],
+            "WDATA": [ { "physical_name": "s_axi_wdata" } ],
+            "WREADY": [ { "physical_name": "s_axi_wready" } ],
+            "WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
+            "WVALID": [ { "physical_name": "s_axi_wvalid" } ]
+          }
+        },
+        "S_AXI_ACLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "S_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "25000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "/clk_wiz_25M_clk_out1", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "s_axi_aclk" } ]
+          }
+        },
+        "S_AXI_ARESETN": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "s_axi_aresetn" } ]
+          }
+        },
+        "GPIO": {
+          "vlnv": "xilinx.com:interface:gpio:1.0",
+          "abstraction_type": "xilinx.com:interface:gpio_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "BOARD.ASSOCIATED_PARAM": [ { "value": "GPIO_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ]
+          },
+          "port_maps": {
+            "TRI_O": [ { "physical_name": "gpio_io_o" } ]
+          }
+        },
+        "GPIO2": {
+          "vlnv": "xilinx.com:interface:gpio:1.0",
+          "abstraction_type": "xilinx.com:interface:gpio_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "BOARD.ASSOCIATED_PARAM": [ { "value": "GPIO2_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ]
+          },
+          "port_maps": {
+            "TRI_I": [ { "physical_name": "gpio2_io_i" } ]
+          }
+        }
+      },
+      "memory_maps": {
+        "S_AXI": {
+          "display_name": "S_AXI_MEM",
+          "description": "Memory Map for S_AXI",
+          "address_blocks": {
+            "Reg": {
+              "base_address": "0",
+              "range": "4096",
+              "display_name": "Reg",
+              "description": "Register Block",
+              "usage": "register",
+              "access": "read-write",
+              "registers": {
+                "GPIO_DATA": {
+                  "address_offset": "0x0",
+                  "size": 32,
+                  "display_name": "Channel_1_GPIO_DATA",
+                  "description": "Channel-1 AXI GPIO Data register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x0",
+                  "fields": {
+                    "Channel_1_GPIO_DATA": {
+                      "bit_offset": 0,
+                      "bit_width": 32,
+                      "display_name": "Channel_1_GPIO_DATA",
+                      "description": "AXI GPIO Data Register.\nFor each I/O bit programmed as input\n  R - Reads value on the input pin.\n  W - No effect.\nFor each I/O bit programmed as output\n  R - Reads value on GPIO_O pins\n  W - Writes value to the corresponding AXI GPIO \n      data register bit and output pin\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    }
+                  }
+                },
+                "GPIO_TRI": {
+                  "address_offset": "0x4",
+                  "size": 32,
+                  "display_name": "Channel_1_GPIO_TRI",
+                  "description": "Channel-1 AXI GPIO 3-State Control register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x0",
+                  "fields": {
+                    "Channel_1_GPIO_TRI": {
+                      "bit_offset": 0,
+                      "bit_width": 32,
+                      "display_name": "Channel_1_GPIO_DATA",
+                      "description": "AXI GPIO 3-State Control Register\nEach I/O pin of the AXI GPIO is individually programmable as an input or output   For each of the bits     0 - I/O pin configured as output     1 - I/O pin configured as input\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    }
+                  }
+                },
+                "GPIO2_DATA": {
+                  "address_offset": "0x8",
+                  "size": 32,
+                  "display_name": "Channel_2_GPIO_DATA",
+                  "description": "Channel-2 AXI GPIO Data register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x0",
+                  "fields": {
+                    "Channel_2_GPIO_DATA": {
+                      "bit_offset": 0,
+                      "bit_width": 32,
+                      "display_name": "Channel_2_GPIO_DATA",
+                      "description": "AXI GPIO Data Register.\nFor each I/O bit programmed as input\n  R - Reads value on the input pin.\n  W - No effect.\nFor each I/O bit programmed as output\n  R - Reads value on GPIO_O pins\n  W - Writes value to the corresponding AXI GPIO \n      data register bit and output pin\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    }
+                  }
+                },
+                "GPIO2_TRI": {
+                  "address_offset": "0xC",
+                  "size": 32,
+                  "display_name": "Channel_2_GPIO_TRI",
+                  "description": "Channel-2 AXI GPIO 3-State Control register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x0",
+                  "fields": {
+                    "Channel_2_GPIO_TRI": {
+                      "bit_offset": 0,
+                      "bit_width": 32,
+                      "display_name": "Channel_2_GPIO_DATA",
+                      "description": "AXI GPIO 3-State Control Register\nEach I/O pin of the AXI GPIO is individually programmable as an input or output   For each of the bits     0 - I/O pin configured as output     1 - I/O pin configured as input\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    }
+                  }
+                },
+                "GIER": {
+                  "address_offset": "0x11C",
+                  "size": 32,
+                  "display_name": "Global_Interrupt_Enable register",
+                  "description": "Global_Interrupt_Enable register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x0",
+                  "fields": {
+                    "Global_Interrupt_Enable": {
+                      "bit_offset": 31,
+                      "bit_width": 1,
+                      "display_name": "Global_Interrupt_Enable",
+                      "description": "Master enable for the device interrupt output\n  0 - Disabled\n  1 - Enabled\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    }
+                  }
+                },
+                "IP_IER": {
+                  "address_offset": "0x128",
+                  "size": 32,
+                  "display_name": "IP Interrupt Enable register",
+                  "description": "IP Interrupt Enable register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x0",
+                  "fields": {
+                    "Channel_1_Interrupt_Enable": {
+                      "bit_offset": 0,
+                      "bit_width": 1,
+                      "display_name": "Channel_1_Interrupt_Enable",
+                      "description": "Enable Channel 1 Interrupt\n  0 - Disabled (masked)\n  1 - Enabled\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Channel_2_Interrupt_Enable": {
+                      "bit_offset": 1,
+                      "bit_width": 1,
+                      "display_name": "Channel_2_Interrupt_Enable",
+                      "description": "Enable Channel 2 Interrupt\n  0 - Disabled (masked)\n  1 - Enabled\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    }
+                  }
+                },
+                "IP_ISR": {
+                  "address_offset": "0x120",
+                  "size": 32,
+                  "display_name": "IP Interrupt Status register",
+                  "description": "IP Interrupt Status register",
+                  "is_volatile": true,
+                  "access": "read-write",
+                  "reset_value": "0x0",
+                  "fields": {
+                    "Channel_1_Interrupt_Status": {
+                      "bit_offset": 0,
+                      "bit_width": 1,
+                      "display_name": "Channel_1_Interrupt_Status",
+                      "description": "Channel 1 Interrupt Status\n  0 - No Channel 1 input interrupt\n  1 - Channel 1 input interrupt\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    },
+                    "Channel_2_Interrupt_Status": {
+                      "bit_offset": 1,
+                      "bit_width": 1,
+                      "display_name": "Channel_2_Interrupt_Status",
+                      "description": "Channel 2 Interrupt Status\n  0 - No Channel 2 input interrupt\n  1 - Channel 2 input interrupt\n",
+                      "is_volatile": true,
+                      "access": "read-write"
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      }
+    }
+  }
+}

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xci

@@ -0,0 +1,293 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_bd_axi_spi_engine_0_0",
+    "cell_name": "axi_spi_engine/axi_spi_engine",
+    "component_reference": "analog.com:user:axi_spi_engine:1.0",
+    "ip_revision": "1",
+    "gen_directory": "../../../../../../dl814_k7_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0",
+    "parameters": {
+      "component_parameters": {
+        "CMD_FIFO_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "SYNC_FIFO_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "SDO_FIFO_ADDRESS_WIDTH": [ { "value": "5", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "SDI_FIFO_ADDRESS_WIDTH": [ { "value": "5", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MM_IF_TYPE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ASYNC_SPI_CLK": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "NUM_OFFLOAD": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "OFFLOAD0_CMD_MEM_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "OFFLOAD0_SDO_MEM_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "ID": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "DATA_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "NUM_OF_SDI": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CFG_INFO_0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CFG_INFO_1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CFG_INFO_2": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CFG_INFO_3": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Component_Name": [ { "value": "system_bd_axi_spi_engine_0_0", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "CMD_FIFO_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "SYNC_FIFO_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "SDO_FIFO_ADDRESS_WIDTH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "SDI_FIFO_ADDRESS_WIDTH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "MM_IF_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "ASYNC_SPI_CLK": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
+        "NUM_OFFLOAD": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "OFFLOAD0_CMD_MEM_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "OFFLOAD0_SDO_MEM_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "DATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "NUM_OF_SDI": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "CFG_INFO_0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "CFG_INFO_1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "CFG_INFO_2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "CFG_INFO_3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "kintex7" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7k410t" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "1" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../dl814_k7_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2023.2.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "s_axi_aclk": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_aresetn": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_awaddr": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_awready": [ { "direction": "out", "driver_value": "0" } ],
+        "s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_wready": [ { "direction": "out", "driver_value": "0" } ],
+        "s_axi_bvalid": [ { "direction": "out", "driver_value": "0" } ],
+        "s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_araddr": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_arready": [ { "direction": "out", "driver_value": "0" } ],
+        "s_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_rvalid": [ { "direction": "out", "driver_value": "0" } ],
+        "s_axi_rready": [ { "direction": "in", "driver_value": "0" } ],
+        "s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
+        "s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "irq": [ { "direction": "out" } ],
+        "spi_clk": [ { "direction": "in" } ],
+        "spi_resetn": [ { "direction": "out" } ],
+        "cmd_ready": [ { "direction": "in" } ],
+        "cmd_valid": [ { "direction": "out" } ],
+        "cmd_data": [ { "direction": "out", "size_left": "15", "size_right": "0" } ],
+        "sdo_data_ready": [ { "direction": "in", "driver_value": "0" } ],
+        "sdo_data_valid": [ { "direction": "out" } ],
+        "sdo_data": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
+        "sdi_data_ready": [ { "direction": "out" } ],
+        "sdi_data_valid": [ { "direction": "in", "driver_value": "0" } ],
+        "sdi_data": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
+        "sync_ready": [ { "direction": "out" } ],
+        "sync_valid": [ { "direction": "in" } ],
+        "sync_data": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ]
+      },
+      "interfaces": {
+        "s_axi": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "slave",
+          "memory_map_ref": "s_axi",
+          "parameters": {
+            "DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "25000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ADDR_WIDTH": [ { "value": "16", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "/clk_wiz_25M_clk_out1", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
+            "AWPROT": [ { "physical_name": "s_axi_awprot" } ],
+            "AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
+            "AWREADY": [ { "physical_name": "s_axi_awready" } ],
+            "WDATA": [ { "physical_name": "s_axi_wdata" } ],
+            "WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
+            "WVALID": [ { "physical_name": "s_axi_wvalid" } ],
+            "WREADY": [ { "physical_name": "s_axi_wready" } ],
+            "BRESP": [ { "physical_name": "s_axi_bresp" } ],
+            "BVALID": [ { "physical_name": "s_axi_bvalid" } ],
+            "BREADY": [ { "physical_name": "s_axi_bready" } ],
+            "ARADDR": [ { "physical_name": "s_axi_araddr" } ],
+            "ARPROT": [ { "physical_name": "s_axi_arprot" } ],
+            "ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
+            "ARREADY": [ { "physical_name": "s_axi_arready" } ],
+            "RDATA": [ { "physical_name": "s_axi_rdata" } ],
+            "RRESP": [ { "physical_name": "s_axi_rresp" } ],
+            "RVALID": [ { "physical_name": "s_axi_rvalid" } ],
+            "RREADY": [ { "physical_name": "s_axi_rready" } ]
+          }
+        },
+        "s_axi_aclk": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "s_axi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "s_axi_aclk" } ]
+          }
+        },
+        "s_axi_aresetn": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "s_axi_aresetn" } ]
+          }
+        },
+        "spi_engine_ctrl": {
+          "vlnv": "analog.com:interface:spi_engine_ctrl:1.0",
+          "abstraction_type": "analog.com:interface:spi_engine_ctrl_rtl:1.0",
+          "mode": "master",
+          "port_maps": {
+            "CMD_READY": [ { "physical_name": "cmd_ready" } ],
+            "CMD_VALID": [ { "physical_name": "cmd_valid" } ],
+            "CMD_DATA": [ { "physical_name": "cmd_data" } ],
+            "SDO_READY": [ { "physical_name": "sdo_data_ready" } ],
+            "SDO_VALID": [ { "physical_name": "sdo_data_valid" } ],
+            "SDO_DATA": [ { "physical_name": "sdo_data" } ],
+            "SDI_READY": [ { "physical_name": "sdi_data_ready" } ],
+            "SDI_VALID": [ { "physical_name": "sdi_data_valid" } ],
+            "SDI_DATA": [ { "physical_name": "sdi_data" } ],
+            "SYNC_READY": [ { "physical_name": "sync_ready" } ],
+            "SYNC_VALID": [ { "physical_name": "sync_valid" } ],
+            "SYNC_DATA": [ { "physical_name": "sync_data" } ]
+          }
+        },
+        "spi_engine_ctrl_signal_clock": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "spi_engine_ctrl", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "spi_resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "25000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "/clk_wiz_25M_clk_out1", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "spi_clk" } ]
+          }
+        },
+        "spi_engine_ctrl_signal_reset": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "spi_resetn" } ]
+          }
+        },
+        "spi_engine_offload_ctrl0_s_axi_signal_clock": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "spi_engine_offload_ctrl0:s_axi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "25000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "/clk_wiz_25M_clk_out1", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "s_axi_aclk" } ]
+          }
+        },
+        "spi_engine_offload_ctrl0_s_axi_signal_reset": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "s_axi_aresetn" } ]
+          }
+        }
+      },
+      "memory_maps": {
+        "s_axi": {
+          "address_blocks": {
+            "axi_lite": {
+              "base_address": "0",
+              "range": "65536"
+            }
+          }
+        }
+      }
+    }
+  }
+}

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ip/system_bd_clk_wiz_1_0/system_bd_clk_wiz_1_0.xci

@@ -0,0 +1,657 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_bd_clk_wiz_1_0",
+    "cell_name": "clk_wiz_25M",
+    "component_reference": "xilinx.com:ip:clk_wiz:6.0",
+    "ip_revision": "13",
+    "gen_directory": "../../../../../../dl814_k7_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_clk_wiz_1_0",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "system_bd_clk_wiz_1_0", "resolve_type": "user", "usage": "all" } ],
+        "USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "ENABLE_CLOCK_MONITOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ENABLE_USER_CLOCK0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ENABLE_USER_CLOCK1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ENABLE_USER_CLOCK2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ENABLE_USER_CLOCK3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_PLL0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_PLL1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
+        "PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ],
+        "CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
+        "USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_PHASE_ALIGNMENT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ],
+        "PRIM_IN_FREQ": [ { "value": "25", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ],
+        "PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "user", "usage": "all" } ],
+        "IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ],
+        "RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ],
+        "USE_INCLK_SWITCHOVER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "SECONDARY_IN_FREQ": [ { "value": "100.000", "value_permission": "bd_and_user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ],
+        "SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
+        "JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ],
+        "CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKIN1_JITTER_PS": [ { "value": "400.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT2_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT3_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT4_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "NUM_OUT_CLKS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ],
+        "DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ],
+        "DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ],
+        "DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ],
+        "DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ],
+        "DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ],
+        "DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ],
+        "DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ],
+        "PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ],
+        "PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ],
+        "PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ],
+        "PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "25", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ],
+        "PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ],
+        "SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
+        "USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
+        "USE_RESET": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ],
+        "LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ],
+        "POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ],
+        "CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ],
+        "STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ],
+        "CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ],
+        "INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ],
+        "SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ],
+        "SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
+        "MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
+        "MMCM_CLKFBOUT_MULT_F": [ { "value": "36.500", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKIN1_PERIOD": [ { "value": "40.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "user", "usage": "all" } ],
+        "MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT0_DIVIDE_F": [ { "value": "36.500", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
+        "PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
+        "PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ],
+        "PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKIN_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ],
+        "PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "RESET_TYPE": [ { "value": "ACTIVE_HIGH", "resolve_type": "user", "usage": "all" } ],
+        "USE_SAFE_CLOCK_STARTUP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_CLOCK_SEQUENCING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "DIFF_CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "DIFF_CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
+        "RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "ENABLE_CDDC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "user", "usage": "all" } ],
+        "CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ],
+        "ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_JITTER": [ { "value": "401.466", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_PHASE_ERROR": [ { "value": "245.713", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "INPUT_MODE": [ { "value": "frequency", "resolve_type": "user", "usage": "all" } ],
+        "INTERFACE_SELECTION": [ { "value": "Enable_AXI", "resolve_type": "user", "usage": "all" } ],
+        "AXI_DRP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "PHASE_DUTY_CONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_CLKOUT2_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
+        "C_USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_ENABLE_CLOCK_MONITOR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_USER_CLOCK0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_USER_CLOCK1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_USER_CLOCK2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_USER_CLOCK3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_Enable_PLL0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_Enable_PLL1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PRECISION": [ { "value": "1", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT4_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT5_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT6_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT7_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKOUT1_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKOUT2_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKOUT3_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKOUT4_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "c_component_name": [ { "value": "system_bd_clk_wiz_1_0", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_FREQ_SYNTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_PHASE_ALIGNMENT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_MIN_POWER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_MIN_O_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_MAX_I_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_DYN_PHASE_SHIFT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_INCLK_SWITCHOVER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_DYN_RECONFIG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_SPREAD_SPECTRUM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_FAST_SIMULATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIMTYPE_SEL": [ { "value": "AUTO", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_CLK_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIM_IN_FREQ": [ { "value": "25", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "generated", "usage": "all" } ],
+        "C_SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "generated", "usage": "all" } ],
+        "C_PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
+        "C_PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "generated", "usage": "all" } ],
+        "C_SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_RESET": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RESET_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_LOCKED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_INCLK_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKFB_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_POWER_DOWN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_STATUS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_FREEZE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_OUT_CLKS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_INCLK_SUM_ROW0": [ { "value": "Input Clock   Freq (MHz)    Input Jitter (UI)", "resolve_type": "generated", "usage": "all" } ],
+        "C_INCLK_SUM_ROW1": [ { "value": "__primary______________25____________0.010", "resolve_type": "generated", "usage": "all" } ],
+        "C_INCLK_SUM_ROW2": [ { "value": "no_secondary_input_clock ", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW0A": [ { "value": " Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW0B": [ { "value": "  Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__25.00000______0.000______50.0______401.466____245.713", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW2": [ { "value": "no_CLK_OUT2_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW3": [ { "value": "no_CLK_OUT3_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW4": [ { "value": "no_CLK_OUT4_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW6": [ { "value": "no_CLK_OUT6_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW7": [ { "value": "no_CLK_OUT7_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "25", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_OUT_FREQ": [ { "value": "25.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_USE_SAFE_CLOCK_STARTUP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLOCK_SEQUENCING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_NOTES": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKFBOUT_MULT_F": [ { "value": "36.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKIN1_PERIOD": [ { "value": "40.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_CASCADE": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
+        "C_MMCM_CLOCK_HOLD": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
+        "C_MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "36.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_NOTES": [ { "value": "No notes", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_CLKFBOUT_MULT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKIN_PERIOD": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLOCK_MGR_TYPE": [ { "value": "NA", "resolve_type": "generated", "usage": "all" } ],
+        "C_OVERRIDE_MMCM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OVERRIDE_PLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "generated", "usage": "all" } ],
+        "C_SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "generated", "usage": "all" } ],
+        "C_RESET_PORT": [ { "value": "reset", "resolve_type": "generated", "usage": "all" } ],
+        "C_LOCKED_PORT": [ { "value": "locked", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "generated", "usage": "all" } ],
+        "C_POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "generated", "usage": "all" } ],
+        "C_DADDR_PORT": [ { "value": "daddr", "resolve_type": "generated", "usage": "all" } ],
+        "C_DCLK_PORT": [ { "value": "dclk", "resolve_type": "generated", "usage": "all" } ],
+        "C_DRDY_PORT": [ { "value": "drdy", "resolve_type": "generated", "usage": "all" } ],
+        "C_DWE_PORT": [ { "value": "dwe", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIN_PORT": [ { "value": "din", "resolve_type": "generated", "usage": "all" } ],
+        "C_DOUT_PORT": [ { "value": "dout", "resolve_type": "generated", "usage": "all" } ],
+        "C_DEN_PORT": [ { "value": "den", "resolve_type": "generated", "usage": "all" } ],
+        "C_PSCLK_PORT": [ { "value": "psclk", "resolve_type": "generated", "usage": "all" } ],
+        "C_PSEN_PORT": [ { "value": "psen", "resolve_type": "generated", "usage": "all" } ],
+        "C_PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "generated", "usage": "all" } ],
+        "C_PSDONE_PORT": [ { "value": "psdone", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "generated", "usage": "all" } ],
+        "C_STATUS_PORT": [ { "value": "STATUS", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "generated", "usage": "all" } ],
+        "C_INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKIN1_JITTER_PS": [ { "value": "400.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
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+        "C_SS_MOD_PERIOD": [ { "value": "4000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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+        "C_CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "generated", "usage": "all" } ],
+        "C_CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUTPHY_MODE": [ { "value": "VCO", "resolve_type": "generated", "usage": "all" } ],
+        "C_ENABLE_CLKOUTPHY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INTERFACE_SELECTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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+        "C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_POWER_REG": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT0_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT0_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFBOUT_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFBOUT_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVCLK": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_LOCK_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_LOCK_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_LOCK_3": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_FILTER_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE2_AUTO": [ { "value": "0.0273972602739726", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE3_AUTO": [ { "value": "0.0273972602739726", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE4_AUTO": [ { "value": "0.0273972602739726", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE5_AUTO": [ { "value": "0.0273972602739726", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE6_AUTO": [ { "value": "0.0273972602739726", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE7_AUTO": [ { "value": "0.0273972602739726", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLLBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLLBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLLBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLLBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLLBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV5": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV6": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV7": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT0_ACTUAL_FREQ": [ { "value": "25.00000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+        "C_M_MAX": [ { "value": "64.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_M_MIN": [ { "value": "2.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_D_MAX": [ { "value": "93.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_D_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_O_MAX": [ { "value": "128.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_O_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_VCO_MIN": [ { "value": "600.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_VCO_MAX": [ { "value": "1440.000", "resolve_type": "generated", "format": "float", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "kintex7" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7k410t" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "13" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../dl814_k7_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_clk_wiz_1_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2023.2.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "clk_in1": [ { "direction": "in" } ],
+        "clk_out1": [ { "direction": "out" } ],
+        "locked": [ { "direction": "out" } ]
+      },
+      "interfaces": {
+        "clock_CLK_IN1": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "25000000", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "system_bd_clk_in1_0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
+            "BOARD.ASSOCIATED_PARAM": [ { "value": "CLK_IN1_BOARD_INTERFACE", "value_permission": "bd", "usage": "all", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK_IN1": [ { "physical_name": "clk_in1" } ]
+          }
+        },
+        "clock_CLK_OUT1": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "25000000", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "/clk_wiz_25M_clk_out1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK_OUT1": [ { "physical_name": "clk_out1" } ]
+          }
+        }
+      }
+    }
+  }
+}

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0/system_bd_dlmb_bram_if_cntlr_0.xci

@@ -0,0 +1,361 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_bd_dlmb_bram_if_cntlr_0",
+    "cell_name": "microblaze_ps_local_memory/dlmb_bram_if_cntlr",
+    "component_reference": "xilinx.com:ip:lmb_bram_if_cntlr:4.0",
+    "ip_revision": "23",
+    "gen_directory": "../../../../../../dl814_k7_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0",
+    "parameters": {
+      "component_parameters": {
+        "C_BASEADDR": [ { "value": "0x0000000000000000", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
+        "C_HIGHADDR": [ { "value": "0x000000000003FFFF", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
+        "C_MASK": [ { "value": "0x0000000040000000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
+        "C_MASK1": [ { "value": "0x0000000000800000", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_MASK2": [ { "value": "0x0000000000800000", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_MASK3": [ { "value": "0x0000000000800000", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_MASK4": [ { "value": "0x0000000000800000", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_MASK5": [ { "value": "0x0000000000800000", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_MASK6": [ { "value": "0x0000000000800000", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_MASK7": [ { "value": "0x0000000000800000", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_NUM_LMB": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_LMB_AWIDTH": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_LMB_DWIDTH": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_LMB_PROTOCOL": [ { "value": "0", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_ARBITRATION": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_ECC": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_INTERCONNECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_FAULT_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_CE_FAILING_REGISTERS": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_UE_FAILING_REGISTERS": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_ECC_STATUS_REGISTERS": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_ECC_ONOFF_REGISTER": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_ECC_ONOFF_RESET_VALUE": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_CE_COUNTER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_WRITE_ACCESS": [ { "value": "2", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_S_AXI_CTRL_ACLK_FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_S_AXI_CTRL_ADDR_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_S_AXI_CTRL_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_S_AXI_CTRL_PROTOCOL": [ { "value": "AXI4LITE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Component_Name": [ { "value": "system_bd_dlmb_bram_if_cntlr_0", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_FAMILY": [ { "value": "kintex7", "resolve_type": "generated", "usage": "all" } ],
+        "C_HIGHADDR": [ { "value": "0x000000000003FFFF", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "C_BASEADDR": [ { "value": "0x0000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "C_NUM_LMB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MASK": [ { "value": "0x0000000040000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "C_MASK1": [ { "value": "0x0000000000800000", "resolve_type": "generated", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_MASK2": [ { "value": "0x0000000000800000", "resolve_type": "generated", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_MASK3": [ { "value": "0x0000000000800000", "resolve_type": "generated", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_MASK4": [ { "value": "0x0000000000800000", "resolve_type": "generated", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_MASK5": [ { "value": "0x0000000000800000", "resolve_type": "generated", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_MASK6": [ { "value": "0x0000000000800000", "resolve_type": "generated", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_MASK7": [ { "value": "0x0000000000800000", "resolve_type": "generated", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_LMB_AWIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_LMB_DWIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_LMB_PROTOCOL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ARBITRATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INTERCONNECT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_FAULT_INJECT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_CE_FAILING_REGISTERS": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_UE_FAILING_REGISTERS": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_ECC_STATUS_REGISTERS": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_ECC_ONOFF_REGISTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_ECC_ONOFF_RESET_VALUE": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_CE_COUNTER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_WRITE_ACCESS": [ { "value": "2", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_BRAM_AWIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_CTRL_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_S_AXI_CTRL_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "kintex7" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7k410t" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "23" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../dl814_k7_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_dlmb_bram_if_cntlr_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2023.2.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "LMB_Clk": [ { "direction": "in", "driver_value": "0x0" } ],
+        "LMB_Rst": [ { "direction": "in", "driver_value": "0x0" } ],
+        "LMB_ABus": [ { "direction": "in", "size_left": "0", "size_right": "31" } ],
+        "LMB_WriteDBus": [ { "direction": "in", "size_left": "0", "size_right": "31", "driver_value": "0" } ],
+        "LMB_AddrStrobe": [ { "direction": "in" } ],
+        "LMB_ReadStrobe": [ { "direction": "in" } ],
+        "LMB_WriteStrobe": [ { "direction": "in", "driver_value": "0" } ],
+        "LMB_BE": [ { "direction": "in", "size_left": "0", "size_right": "3", "driver_value": "0" } ],
+        "Sl_DBus": [ { "direction": "out", "size_left": "0", "size_right": "31" } ],
+        "Sl_Ready": [ { "direction": "out" } ],
+        "Sl_Wait": [ { "direction": "out" } ],
+        "Sl_UE": [ { "direction": "out" } ],
+        "Sl_CE": [ { "direction": "out" } ],
+        "BRAM_Rst_A": [ { "direction": "out" } ],
+        "BRAM_Clk_A": [ { "direction": "out" } ],
+        "BRAM_Addr_A": [ { "direction": "out", "size_left": "0", "size_right": "31" } ],
+        "BRAM_EN_A": [ { "direction": "out" } ],
+        "BRAM_WEN_A": [ { "direction": "out", "size_left": "0", "size_right": "3" } ],
+        "BRAM_Dout_A": [ { "direction": "out", "size_left": "0", "size_right": "31" } ],
+        "BRAM_Din_A": [ { "direction": "in", "size_left": "0", "size_right": "31" } ]
+      },
+      "interfaces": {
+        "SLMB": {
+          "vlnv": "xilinx.com:interface:lmb:1.0",
+          "abstraction_type": "xilinx.com:interface:lmb_rtl:1.0",
+          "mode": "slave",
+          "memory_map_ref": "SLMB",
+          "parameters": {
+            "ADDR_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "STANDARD", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "ABUS": [ { "physical_name": "LMB_ABus" } ],
+            "ADDRSTROBE": [ { "physical_name": "LMB_AddrStrobe" } ],
+            "BE": [ { "physical_name": "LMB_BE" } ],
+            "CE": [ { "physical_name": "Sl_CE" } ],
+            "READDBUS": [ { "physical_name": "Sl_DBus" } ],
+            "READSTROBE": [ { "physical_name": "LMB_ReadStrobe" } ],
+            "READY": [ { "physical_name": "Sl_Ready" } ],
+            "UE": [ { "physical_name": "Sl_UE" } ],
+            "WAIT": [ { "physical_name": "Sl_Wait" } ],
+            "WRITEDBUS": [ { "physical_name": "LMB_WriteDBus" } ],
+            "WRITESTROBE": [ { "physical_name": "LMB_WriteStrobe" } ]
+          }
+        },
+        "BRAM_PORT": {
+          "vlnv": "xilinx.com:interface:bram:1.0",
+          "abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "MEM_SIZE": [ { "value": "262144", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "usage": "all" } ],
+            "MASTER_TYPE": [ { "value": "BRAM_CTRL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "MEM_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MEM_ECC": [ { "value": "NONE", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_LATENCY": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "ADDR": [ { "physical_name": "BRAM_Addr_A" } ],
+            "CLK": [ { "physical_name": "BRAM_Clk_A" } ],
+            "DIN": [ { "physical_name": "BRAM_Dout_A" } ],
+            "DOUT": [ { "physical_name": "BRAM_Din_A" } ],
+            "EN": [ { "physical_name": "BRAM_EN_A" } ],
+            "RST": [ { "physical_name": "BRAM_Rst_A" } ],
+            "WE": [ { "physical_name": "BRAM_WEN_A" } ]
+          }
+        },
+        "CLK.LMB_Clk": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "SLMB:SLMB1:SLMB2:SLMB3:SLMB4:SLMB5:SLMB6:SLMB7", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "LMB_Rst", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "25000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "/clk_wiz_25M_clk_out1", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "LMB_Clk" } ]
+          }
+        },
+        "RST.LMB_Rst": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "TYPE": [ { "value": "INTERCONNECT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "LMB_Rst" } ]
+          }
+        },
+        "CLK.S_AXI_CTRL_ACLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "S_AXI_CTRL", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "S_AXI_CTRL_ARESETN", "value_src": "constant", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "RST.S_AXI_CTRL_ARESETN": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        }
+      },
+      "memory_maps": {
+        "SLMB": {
+          "description": "SLMB memory map",
+          "address_blocks": {
+            "Mem": {
+              "base_address": "0",
+              "range": "8192",
+              "usage": "memory",
+              "access": "read-write",
+              "parameters": {
+                "OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
+                "OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
+              }
+            }
+          }
+        },
+        "SLMB1": {
+          "description": "SLMB1 memory map",
+          "address_blocks": {
+            "Mem": {
+              "base_address": "0",
+              "range": "8192",
+              "usage": "memory",
+              "access": "read-write",
+              "parameters": {
+                "OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
+                "OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
+              }
+            }
+          }
+        },
+        "SLMB2": {
+          "description": "SLMB2 memory map",
+          "address_blocks": {
+            "Mem": {
+              "base_address": "0",
+              "range": "8192",
+              "usage": "memory",
+              "access": "read-write",
+              "parameters": {
+                "OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
+                "OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
+              }
+            }
+          }
+        },
+        "SLMB3": {
+          "description": "SLMB3 memory map",
+          "address_blocks": {
+            "Mem": {
+              "base_address": "0",
+              "range": "8192",
+              "usage": "memory",
+              "access": "read-write",
+              "parameters": {
+                "OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
+                "OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
+              }
+            }
+          }
+        },
+        "SLMB4": {
+          "description": "SLMB4 memory map",
+          "address_blocks": {
+            "Mem": {
+              "base_address": "0",
+              "range": "8192",
+              "usage": "memory",
+              "access": "read-write",
+              "parameters": {
+                "OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
+                "OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
+              }
+            }
+          }
+        },
+        "SLMB5": {
+          "description": "SLMB5 memory map",
+          "address_blocks": {
+            "Mem": {
+              "base_address": "0",
+              "range": "8192",
+              "usage": "memory",
+              "access": "read-write",
+              "parameters": {
+                "OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
+                "OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
+              }
+            }
+          }
+        },
+        "SLMB6": {
+          "description": "SLMB6 memory map",
+          "address_blocks": {
+            "Mem": {
+              "base_address": "0",
+              "range": "8192",
+              "usage": "memory",
+              "access": "read-write",
+              "parameters": {
+                "OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
+                "OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
+              }
+            }
+          }
+        },
+        "SLMB7": {
+          "description": "SLMB7 memory map",
+          "address_blocks": {
+            "Mem": {
+              "base_address": "0",
+              "range": "8192",
+              "usage": "memory",
+              "access": "read-write",
+              "parameters": {
+                "OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
+                "OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
+              }
+            }
+          }
+        },
+        "S_AXI_CTRL": {
+          "description": "S_AXI_CTRL memory map",
+          "address_blocks": {
+            "Reg": {
+              "base_address": "0",
+              "range": "4096",
+              "display_name": "Reg",
+              "description": "Register Block",
+              "usage": "register",
+              "access": "read-write"
+            }
+          }
+        }
+      }
+    }
+  }
+}

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ip/system_bd_dlmb_v10_0/system_bd_dlmb_v10_0.xci

@@ -0,0 +1,162 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_bd_dlmb_v10_0",
+    "cell_name": "microblaze_ps_local_memory/dlmb_v10",
+    "component_reference": "xilinx.com:ip:lmb_v10:3.0",
+    "ip_revision": "13",
+    "gen_directory": "../../../../../../dl814_k7_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_dlmb_v10_0",
+    "parameters": {
+      "component_parameters": {
+        "C_LMB_DWIDTH": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_LMB_AWIDTH": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_LMB_PROTOCOL": [ { "value": "0", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_EXT_RESET_HIGH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_LMB_NUM_SLAVES": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Component_Name": [ { "value": "system_bd_dlmb_v10_0", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_LMB_NUM_SLAVES": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_LMB_DWIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_LMB_AWIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_LMB_PROTOCOL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EXT_RESET_HIGH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "kintex7" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7k410t" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "13" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../dl814_k7_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_dlmb_v10_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2023.2.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "LMB_Clk": [ { "direction": "in" } ],
+        "SYS_Rst": [ { "direction": "in" } ],
+        "LMB_Rst": [ { "direction": "out" } ],
+        "M_ABus": [ { "direction": "in", "size_left": "0", "size_right": "31" } ],
+        "M_ReadStrobe": [ { "direction": "in" } ],
+        "M_WriteStrobe": [ { "direction": "in", "driver_value": "0" } ],
+        "M_AddrStrobe": [ { "direction": "in" } ],
+        "M_DBus": [ { "direction": "in", "size_left": "0", "size_right": "31", "driver_value": "0" } ],
+        "M_BE": [ { "direction": "in", "size_left": "0", "size_right": "3", "driver_value": "0" } ],
+        "Sl_DBus": [ { "direction": "in", "size_left": "0", "size_right": "31" } ],
+        "Sl_Ready": [ { "direction": "in", "size_left": "0", "size_right": "0" } ],
+        "Sl_Wait": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
+        "Sl_UE": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
+        "Sl_CE": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
+        "LMB_ABus": [ { "direction": "out", "size_left": "0", "size_right": "31" } ],
+        "LMB_ReadStrobe": [ { "direction": "out" } ],
+        "LMB_WriteStrobe": [ { "direction": "out" } ],
+        "LMB_AddrStrobe": [ { "direction": "out" } ],
+        "LMB_ReadDBus": [ { "direction": "out", "size_left": "0", "size_right": "31" } ],
+        "LMB_WriteDBus": [ { "direction": "out", "size_left": "0", "size_right": "31" } ],
+        "LMB_Ready": [ { "direction": "out" } ],
+        "LMB_Wait": [ { "direction": "out" } ],
+        "LMB_UE": [ { "direction": "out" } ],
+        "LMB_CE": [ { "direction": "out" } ],
+        "LMB_BE": [ { "direction": "out", "size_left": "0", "size_right": "3" } ]
+      },
+      "interfaces": {
+        "LMB_Sl_0": {
+          "vlnv": "xilinx.com:interface:lmb:1.0",
+          "abstraction_type": "xilinx.com:interface:lmb_rtl:1.0",
+          "mode": "mirroredSlave",
+          "parameters": {
+            "ADDR_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "DATA_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "STANDARD", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "ABUS": [ { "physical_name": "LMB_ABus" } ],
+            "ADDRSTROBE": [ { "physical_name": "LMB_AddrStrobe" } ],
+            "BE": [ { "physical_name": "LMB_BE" } ],
+            "CE": [ { "physical_name": "Sl_CE", "physical_left": "0", "physical_right": "0" } ],
+            "READDBUS": [ { "physical_name": "Sl_DBus", "physical_left": "0", "physical_right": "31" } ],
+            "READSTROBE": [ { "physical_name": "LMB_ReadStrobe" } ],
+            "READY": [ { "physical_name": "Sl_Ready", "physical_left": "0", "physical_right": "0" } ],
+            "RST": [ { "physical_name": "LMB_Rst" } ],
+            "UE": [ { "physical_name": "Sl_UE", "physical_left": "0", "physical_right": "0" } ],
+            "WAIT": [ { "physical_name": "Sl_Wait", "physical_left": "0", "physical_right": "0" } ],
+            "WRITEDBUS": [ { "physical_name": "LMB_WriteDBus" } ],
+            "WRITESTROBE": [ { "physical_name": "LMB_WriteStrobe" } ]
+          }
+        },
+        "LMB_M": {
+          "vlnv": "xilinx.com:interface:lmb:1.0",
+          "abstraction_type": "xilinx.com:interface:lmb_rtl:1.0",
+          "mode": "mirroredMaster",
+          "parameters": {
+            "ADDR_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "STANDARD", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "ABUS": [ { "physical_name": "M_ABus" } ],
+            "ADDRSTROBE": [ { "physical_name": "M_AddrStrobe" } ],
+            "BE": [ { "physical_name": "M_BE" } ],
+            "CE": [ { "physical_name": "LMB_CE" } ],
+            "READDBUS": [ { "physical_name": "LMB_ReadDBus" } ],
+            "READSTROBE": [ { "physical_name": "M_ReadStrobe" } ],
+            "READY": [ { "physical_name": "LMB_Ready" } ],
+            "RST": [ { "physical_name": "LMB_Rst" } ],
+            "UE": [ { "physical_name": "LMB_UE" } ],
+            "WAIT": [ { "physical_name": "LMB_Wait" } ],
+            "WRITEDBUS": [ { "physical_name": "M_DBus" } ],
+            "WRITESTROBE": [ { "physical_name": "M_WriteStrobe" } ]
+          }
+        },
+        "CLK.LMB_Clk": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "LMB_Sl_0:LMB_Sl_1:LMB_Sl_2:LMB_Sl_3:LMB_Sl_4:LMB_Sl_5:LMB_Sl_6:LMB_Sl_7:LMB_Sl_8:LMB_Sl_9:LMB_Sl_10:LMB_Sl_11:LMB_Sl_12:LMB_Sl_13:LMB_Sl_14:LMB_Sl_15:LMB_M", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "SYS_Rst", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "25000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "/clk_wiz_25M_clk_out1", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "LMB_Clk" } ]
+          }
+        },
+        "RST.SYS_Rst": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "TYPE": [ { "value": "INTERCONNECT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "SYS_Rst" } ]
+          }
+        }
+      }
+    }
+  }
+}

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0/system_bd_ilmb_bram_if_cntlr_0.xci

@@ -0,0 +1,361 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_bd_ilmb_bram_if_cntlr_0",
+    "cell_name": "microblaze_ps_local_memory/ilmb_bram_if_cntlr",
+    "component_reference": "xilinx.com:ip:lmb_bram_if_cntlr:4.0",
+    "ip_revision": "23",
+    "gen_directory": "../../../../../../dl814_k7_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0",
+    "parameters": {
+      "component_parameters": {
+        "C_BASEADDR": [ { "value": "0x0000000000000000", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
+        "C_HIGHADDR": [ { "value": "0x000000000003FFFF", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
+        "C_MASK": [ { "value": "0x0000000000000000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
+        "C_MASK1": [ { "value": "0x0000000000800000", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_MASK2": [ { "value": "0x0000000000800000", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_MASK3": [ { "value": "0x0000000000800000", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_MASK4": [ { "value": "0x0000000000800000", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_MASK5": [ { "value": "0x0000000000800000", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_MASK6": [ { "value": "0x0000000000800000", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_MASK7": [ { "value": "0x0000000000800000", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_NUM_LMB": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_LMB_AWIDTH": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_LMB_DWIDTH": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_LMB_PROTOCOL": [ { "value": "0", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_ARBITRATION": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_ECC": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_INTERCONNECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_FAULT_INJECT": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_CE_FAILING_REGISTERS": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_UE_FAILING_REGISTERS": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_ECC_STATUS_REGISTERS": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_ECC_ONOFF_REGISTER": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_ECC_ONOFF_RESET_VALUE": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_CE_COUNTER_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_WRITE_ACCESS": [ { "value": "2", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_S_AXI_CTRL_ACLK_FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_S_AXI_CTRL_ADDR_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_S_AXI_CTRL_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_S_AXI_CTRL_PROTOCOL": [ { "value": "AXI4LITE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Component_Name": [ { "value": "system_bd_ilmb_bram_if_cntlr_0", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_FAMILY": [ { "value": "kintex7", "resolve_type": "generated", "usage": "all" } ],
+        "C_HIGHADDR": [ { "value": "0x000000000003FFFF", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "C_BASEADDR": [ { "value": "0x0000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "C_NUM_LMB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MASK": [ { "value": "0x0000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "C_MASK1": [ { "value": "0x0000000000800000", "resolve_type": "generated", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_MASK2": [ { "value": "0x0000000000800000", "resolve_type": "generated", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_MASK3": [ { "value": "0x0000000000800000", "resolve_type": "generated", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_MASK4": [ { "value": "0x0000000000800000", "resolve_type": "generated", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_MASK5": [ { "value": "0x0000000000800000", "resolve_type": "generated", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_MASK6": [ { "value": "0x0000000000800000", "resolve_type": "generated", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_MASK7": [ { "value": "0x0000000000800000", "resolve_type": "generated", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_LMB_AWIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_LMB_DWIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_LMB_PROTOCOL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ARBITRATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ECC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INTERCONNECT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_FAULT_INJECT": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_CE_FAILING_REGISTERS": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_UE_FAILING_REGISTERS": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_ECC_STATUS_REGISTERS": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_ECC_ONOFF_REGISTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_ECC_ONOFF_RESET_VALUE": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_CE_COUNTER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_WRITE_ACCESS": [ { "value": "2", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_BRAM_AWIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_CTRL_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_S_AXI_CTRL_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "kintex7" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7k410t" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "23" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../dl814_k7_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_ilmb_bram_if_cntlr_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2023.2.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "LMB_Clk": [ { "direction": "in", "driver_value": "0x0" } ],
+        "LMB_Rst": [ { "direction": "in", "driver_value": "0x0" } ],
+        "LMB_ABus": [ { "direction": "in", "size_left": "0", "size_right": "31" } ],
+        "LMB_WriteDBus": [ { "direction": "in", "size_left": "0", "size_right": "31", "driver_value": "0" } ],
+        "LMB_AddrStrobe": [ { "direction": "in" } ],
+        "LMB_ReadStrobe": [ { "direction": "in" } ],
+        "LMB_WriteStrobe": [ { "direction": "in", "driver_value": "0" } ],
+        "LMB_BE": [ { "direction": "in", "size_left": "0", "size_right": "3", "driver_value": "0" } ],
+        "Sl_DBus": [ { "direction": "out", "size_left": "0", "size_right": "31" } ],
+        "Sl_Ready": [ { "direction": "out" } ],
+        "Sl_Wait": [ { "direction": "out" } ],
+        "Sl_UE": [ { "direction": "out" } ],
+        "Sl_CE": [ { "direction": "out" } ],
+        "BRAM_Rst_A": [ { "direction": "out" } ],
+        "BRAM_Clk_A": [ { "direction": "out" } ],
+        "BRAM_Addr_A": [ { "direction": "out", "size_left": "0", "size_right": "31" } ],
+        "BRAM_EN_A": [ { "direction": "out" } ],
+        "BRAM_WEN_A": [ { "direction": "out", "size_left": "0", "size_right": "3" } ],
+        "BRAM_Dout_A": [ { "direction": "out", "size_left": "0", "size_right": "31" } ],
+        "BRAM_Din_A": [ { "direction": "in", "size_left": "0", "size_right": "31" } ]
+      },
+      "interfaces": {
+        "SLMB": {
+          "vlnv": "xilinx.com:interface:lmb:1.0",
+          "abstraction_type": "xilinx.com:interface:lmb_rtl:1.0",
+          "mode": "slave",
+          "memory_map_ref": "SLMB",
+          "parameters": {
+            "ADDR_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "STANDARD", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "ABUS": [ { "physical_name": "LMB_ABus" } ],
+            "ADDRSTROBE": [ { "physical_name": "LMB_AddrStrobe" } ],
+            "BE": [ { "physical_name": "LMB_BE" } ],
+            "CE": [ { "physical_name": "Sl_CE" } ],
+            "READDBUS": [ { "physical_name": "Sl_DBus" } ],
+            "READSTROBE": [ { "physical_name": "LMB_ReadStrobe" } ],
+            "READY": [ { "physical_name": "Sl_Ready" } ],
+            "UE": [ { "physical_name": "Sl_UE" } ],
+            "WAIT": [ { "physical_name": "Sl_Wait" } ],
+            "WRITEDBUS": [ { "physical_name": "LMB_WriteDBus" } ],
+            "WRITESTROBE": [ { "physical_name": "LMB_WriteStrobe" } ]
+          }
+        },
+        "BRAM_PORT": {
+          "vlnv": "xilinx.com:interface:bram:1.0",
+          "abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "MEM_SIZE": [ { "value": "262144", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "usage": "all" } ],
+            "MASTER_TYPE": [ { "value": "BRAM_CTRL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "MEM_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MEM_ECC": [ { "value": "NONE", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_LATENCY": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "ADDR": [ { "physical_name": "BRAM_Addr_A" } ],
+            "CLK": [ { "physical_name": "BRAM_Clk_A" } ],
+            "DIN": [ { "physical_name": "BRAM_Dout_A" } ],
+            "DOUT": [ { "physical_name": "BRAM_Din_A" } ],
+            "EN": [ { "physical_name": "BRAM_EN_A" } ],
+            "RST": [ { "physical_name": "BRAM_Rst_A" } ],
+            "WE": [ { "physical_name": "BRAM_WEN_A" } ]
+          }
+        },
+        "CLK.LMB_Clk": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "SLMB:SLMB1:SLMB2:SLMB3:SLMB4:SLMB5:SLMB6:SLMB7", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "LMB_Rst", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "25000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "/clk_wiz_25M_clk_out1", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "LMB_Clk" } ]
+          }
+        },
+        "RST.LMB_Rst": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "TYPE": [ { "value": "INTERCONNECT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "LMB_Rst" } ]
+          }
+        },
+        "CLK.S_AXI_CTRL_ACLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "S_AXI_CTRL", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "S_AXI_CTRL_ARESETN", "value_src": "constant", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "RST.S_AXI_CTRL_ARESETN": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        }
+      },
+      "memory_maps": {
+        "SLMB": {
+          "description": "SLMB memory map",
+          "address_blocks": {
+            "Mem": {
+              "base_address": "0",
+              "range": "8192",
+              "usage": "memory",
+              "access": "read-write",
+              "parameters": {
+                "OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
+                "OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
+              }
+            }
+          }
+        },
+        "SLMB1": {
+          "description": "SLMB1 memory map",
+          "address_blocks": {
+            "Mem": {
+              "base_address": "0",
+              "range": "8192",
+              "usage": "memory",
+              "access": "read-write",
+              "parameters": {
+                "OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
+                "OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
+              }
+            }
+          }
+        },
+        "SLMB2": {
+          "description": "SLMB2 memory map",
+          "address_blocks": {
+            "Mem": {
+              "base_address": "0",
+              "range": "8192",
+              "usage": "memory",
+              "access": "read-write",
+              "parameters": {
+                "OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
+                "OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
+              }
+            }
+          }
+        },
+        "SLMB3": {
+          "description": "SLMB3 memory map",
+          "address_blocks": {
+            "Mem": {
+              "base_address": "0",
+              "range": "8192",
+              "usage": "memory",
+              "access": "read-write",
+              "parameters": {
+                "OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
+                "OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
+              }
+            }
+          }
+        },
+        "SLMB4": {
+          "description": "SLMB4 memory map",
+          "address_blocks": {
+            "Mem": {
+              "base_address": "0",
+              "range": "8192",
+              "usage": "memory",
+              "access": "read-write",
+              "parameters": {
+                "OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
+                "OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
+              }
+            }
+          }
+        },
+        "SLMB5": {
+          "description": "SLMB5 memory map",
+          "address_blocks": {
+            "Mem": {
+              "base_address": "0",
+              "range": "8192",
+              "usage": "memory",
+              "access": "read-write",
+              "parameters": {
+                "OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
+                "OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
+              }
+            }
+          }
+        },
+        "SLMB6": {
+          "description": "SLMB6 memory map",
+          "address_blocks": {
+            "Mem": {
+              "base_address": "0",
+              "range": "8192",
+              "usage": "memory",
+              "access": "read-write",
+              "parameters": {
+                "OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
+                "OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
+              }
+            }
+          }
+        },
+        "SLMB7": {
+          "description": "SLMB7 memory map",
+          "address_blocks": {
+            "Mem": {
+              "base_address": "0",
+              "range": "8192",
+              "usage": "memory",
+              "access": "read-write",
+              "parameters": {
+                "OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
+                "OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
+              }
+            }
+          }
+        },
+        "S_AXI_CTRL": {
+          "description": "S_AXI_CTRL memory map",
+          "address_blocks": {
+            "Reg": {
+              "base_address": "0",
+              "range": "4096",
+              "display_name": "Reg",
+              "description": "Register Block",
+              "usage": "register",
+              "access": "read-write"
+            }
+          }
+        }
+      }
+    }
+  }
+}

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ip/system_bd_ilmb_v10_0/system_bd_ilmb_v10_0.xci

@@ -0,0 +1,162 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_bd_ilmb_v10_0",
+    "cell_name": "microblaze_ps_local_memory/ilmb_v10",
+    "component_reference": "xilinx.com:ip:lmb_v10:3.0",
+    "ip_revision": "13",
+    "gen_directory": "../../../../../../dl814_k7_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_ilmb_v10_0",
+    "parameters": {
+      "component_parameters": {
+        "C_LMB_DWIDTH": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_LMB_AWIDTH": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_LMB_PROTOCOL": [ { "value": "0", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_EXT_RESET_HIGH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_LMB_NUM_SLAVES": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Component_Name": [ { "value": "system_bd_ilmb_v10_0", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_LMB_NUM_SLAVES": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_LMB_DWIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_LMB_AWIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_LMB_PROTOCOL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EXT_RESET_HIGH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "kintex7" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7k410t" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "13" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../dl814_k7_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_ilmb_v10_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2023.2.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "LMB_Clk": [ { "direction": "in" } ],
+        "SYS_Rst": [ { "direction": "in" } ],
+        "LMB_Rst": [ { "direction": "out" } ],
+        "M_ABus": [ { "direction": "in", "size_left": "0", "size_right": "31" } ],
+        "M_ReadStrobe": [ { "direction": "in" } ],
+        "M_WriteStrobe": [ { "direction": "in", "driver_value": "0" } ],
+        "M_AddrStrobe": [ { "direction": "in" } ],
+        "M_DBus": [ { "direction": "in", "size_left": "0", "size_right": "31", "driver_value": "0" } ],
+        "M_BE": [ { "direction": "in", "size_left": "0", "size_right": "3", "driver_value": "0" } ],
+        "Sl_DBus": [ { "direction": "in", "size_left": "0", "size_right": "31" } ],
+        "Sl_Ready": [ { "direction": "in", "size_left": "0", "size_right": "0" } ],
+        "Sl_Wait": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
+        "Sl_UE": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
+        "Sl_CE": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
+        "LMB_ABus": [ { "direction": "out", "size_left": "0", "size_right": "31" } ],
+        "LMB_ReadStrobe": [ { "direction": "out" } ],
+        "LMB_WriteStrobe": [ { "direction": "out" } ],
+        "LMB_AddrStrobe": [ { "direction": "out" } ],
+        "LMB_ReadDBus": [ { "direction": "out", "size_left": "0", "size_right": "31" } ],
+        "LMB_WriteDBus": [ { "direction": "out", "size_left": "0", "size_right": "31" } ],
+        "LMB_Ready": [ { "direction": "out" } ],
+        "LMB_Wait": [ { "direction": "out" } ],
+        "LMB_UE": [ { "direction": "out" } ],
+        "LMB_CE": [ { "direction": "out" } ],
+        "LMB_BE": [ { "direction": "out", "size_left": "0", "size_right": "3" } ]
+      },
+      "interfaces": {
+        "LMB_Sl_0": {
+          "vlnv": "xilinx.com:interface:lmb:1.0",
+          "abstraction_type": "xilinx.com:interface:lmb_rtl:1.0",
+          "mode": "mirroredSlave",
+          "parameters": {
+            "ADDR_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "DATA_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "STANDARD", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "ABUS": [ { "physical_name": "LMB_ABus" } ],
+            "ADDRSTROBE": [ { "physical_name": "LMB_AddrStrobe" } ],
+            "BE": [ { "physical_name": "LMB_BE" } ],
+            "CE": [ { "physical_name": "Sl_CE", "physical_left": "0", "physical_right": "0" } ],
+            "READDBUS": [ { "physical_name": "Sl_DBus", "physical_left": "0", "physical_right": "31" } ],
+            "READSTROBE": [ { "physical_name": "LMB_ReadStrobe" } ],
+            "READY": [ { "physical_name": "Sl_Ready", "physical_left": "0", "physical_right": "0" } ],
+            "RST": [ { "physical_name": "LMB_Rst" } ],
+            "UE": [ { "physical_name": "Sl_UE", "physical_left": "0", "physical_right": "0" } ],
+            "WAIT": [ { "physical_name": "Sl_Wait", "physical_left": "0", "physical_right": "0" } ],
+            "WRITEDBUS": [ { "physical_name": "LMB_WriteDBus" } ],
+            "WRITESTROBE": [ { "physical_name": "LMB_WriteStrobe" } ]
+          }
+        },
+        "LMB_M": {
+          "vlnv": "xilinx.com:interface:lmb:1.0",
+          "abstraction_type": "xilinx.com:interface:lmb_rtl:1.0",
+          "mode": "mirroredMaster",
+          "parameters": {
+            "ADDR_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_ONLY", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "PROTOCOL": [ { "value": "STANDARD", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "ABUS": [ { "physical_name": "M_ABus" } ],
+            "ADDRSTROBE": [ { "physical_name": "M_AddrStrobe" } ],
+            "BE": [ { "physical_name": "M_BE" } ],
+            "CE": [ { "physical_name": "LMB_CE" } ],
+            "READDBUS": [ { "physical_name": "LMB_ReadDBus" } ],
+            "READSTROBE": [ { "physical_name": "M_ReadStrobe" } ],
+            "READY": [ { "physical_name": "LMB_Ready" } ],
+            "RST": [ { "physical_name": "LMB_Rst" } ],
+            "UE": [ { "physical_name": "LMB_UE" } ],
+            "WAIT": [ { "physical_name": "LMB_Wait" } ],
+            "WRITEDBUS": [ { "physical_name": "M_DBus" } ],
+            "WRITESTROBE": [ { "physical_name": "M_WriteStrobe" } ]
+          }
+        },
+        "CLK.LMB_Clk": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "LMB_Sl_0:LMB_Sl_1:LMB_Sl_2:LMB_Sl_3:LMB_Sl_4:LMB_Sl_5:LMB_Sl_6:LMB_Sl_7:LMB_Sl_8:LMB_Sl_9:LMB_Sl_10:LMB_Sl_11:LMB_Sl_12:LMB_Sl_13:LMB_Sl_14:LMB_Sl_15:LMB_M", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "SYS_Rst", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "25000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "/clk_wiz_25M_clk_out1", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "LMB_Clk" } ]
+          }
+        },
+        "RST.SYS_Rst": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "TYPE": [ { "value": "INTERCONNECT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "SYS_Rst" } ]
+          }
+        }
+      }
+    }
+  }
+}

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ip/system_bd_lmb_bram_0/system_bd_lmb_bram_0.xci

@@ -0,0 +1,292 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_bd_lmb_bram_0",
+    "cell_name": "microblaze_ps_local_memory/lmb_bram",
+    "component_reference": "xilinx.com:ip:blk_mem_gen:8.4",
+    "ip_revision": "7",
+    "gen_directory": "../../../../../../dl814_k7_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_lmb_bram_0",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "system_bd_lmb_bram_0", "resolve_type": "user", "usage": "all" } ],
+        "Interface_Type": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
+        "AXI_Type": [ { "value": "AXI4_Full", "resolve_type": "user", "usage": "all" } ],
+        "AXI_Slave_Type": [ { "value": "Memory_Slave", "resolve_type": "user", "usage": "all" } ],
+        "Use_AXI_ID": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Memory_Type": [ { "value": "True_Dual_Port_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "usage": "all" } ],
+        "Enable_32bit_Address": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ecctype": [ { "value": "No_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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+            "MASTER_TYPE": [ { "value": "BRAM_CTRL", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_LATENCY": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "ADDR": [ { "physical_name": "addra" } ],
+            "CLK": [ { "physical_name": "clka" } ],
+            "DIN": [ { "physical_name": "dina" } ],
+            "DOUT": [ { "physical_name": "douta" } ],
+            "EN": [ { "physical_name": "ena" } ],
+            "RST": [ { "physical_name": "rsta" } ],
+            "WE": [ { "physical_name": "wea" } ]
+          }
+        },
+        "BRAM_PORTB": {
+          "vlnv": "xilinx.com:interface:bram:1.0",
+          "abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "MEM_SIZE": [ { "value": "262144", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MEM_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "MEM_ECC": [ { "value": "NONE", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "MASTER_TYPE": [ { "value": "BRAM_CTRL", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "READ_LATENCY": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "ADDR": [ { "physical_name": "addrb" } ],
+            "CLK": [ { "physical_name": "clkb" } ],
+            "DIN": [ { "physical_name": "dinb" } ],
+            "DOUT": [ { "physical_name": "doutb" } ],
+            "EN": [ { "physical_name": "enb" } ],
+            "RST": [ { "physical_name": "rstb" } ],
+            "WE": [ { "physical_name": "web" } ]
+          }
+        }
+      },
+      "memory_maps": {
+        "S_1": {
+          "address_blocks": {
+            "Mem0": {
+              "base_address": "0",
+              "range": "4096",
+              "usage": "memory",
+              "access": "read-write",
+              "parameters": {
+                "OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ],
+                "OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ]
+              }
+            }
+          }
+        }
+      }
+    }
+  }
+}

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ip/system_bd_mdm_1_0/system_bd_mdm_1_0.xci

@@ -0,0 +1,168 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_bd_mdm_1_0",
+    "cell_name": "mdm",
+    "component_reference": "xilinx.com:ip:mdm:3.2",
+    "ip_revision": "25",
+    "gen_directory": "../../../../../../dl814_k7_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_mdm_1_0",
+    "parameters": {
+      "component_parameters": {
+        "C_XMTC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_BRK": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_JTAG_CHAIN": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_USE_BSCAN": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_BSCANID": [ { "value": "76547328", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_DEBUG_INTERFACE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_USE_CONFIG_RESET": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_AVOID_PRIMITIVES": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_INTERCONNECT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_S_AXI_ADDR_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_S_AXI_ACLK_FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M_AXI_ADDR_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M_AXI_THREAD_ID_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_ADDR_SIZE": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_DATA_SIZE": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_LMB_PROTOCOL": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M_AXIS_ID_WIDTH": [ { "value": "7", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_MB_DBG_PORTS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_USE_UART": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_DBG_REG_ACCESS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_DBG_MEM_ACCESS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_USE_CROSS_TRIGGER": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_TRIG_IN_PORTS": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_TRIG_OUT_PORTS": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_EXT_TRIG_RESET_VALUE": [ { "value": "0xF1234", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
+        "C_TRACE_OUTPUT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_TRACE_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_TRACE_CLK_FREQ_HZ": [ { "value": "200000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_TRACE_CLK_OUT_PHASE": [ { "value": "90", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_TRACE_ASYNC_RESET": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_TRACE_PROTOCOL": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_TRACE_ID": [ { "value": "110", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Component_Name": [ { "value": "system_bd_mdm_1_0", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_FAMILY": [ { "value": "kintex7", "resolve_type": "generated", "usage": "all" } ],
+        "C_DEVICE": [ { "value": "xc7k410t", "resolve_type": "generated", "usage": "all" } ],
+        "C_REVISION": [ { "value": "", "resolve_type": "generated", "usage": "all" } ],
+        "C_JTAG_CHAIN": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_BSCAN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_BSCANID": [ { "value": "76547328", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DEBUG_INTERFACE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CONFIG_RESET": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AVOID_PRIMITIVES": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INTERCONNECT": [ { "value": "2", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_MB_DBG_PORTS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_UART": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DBG_REG_ACCESS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DBG_MEM_ACCESS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CROSS_TRIGGER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_EXT_TRIG_RESET_VALUE": [ { "value": "0xF1234", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "C_TRACE_OUTPUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_TRACE_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_TRACE_CLK_FREQ_HZ": [ { "value": "200000000", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_TRACE_CLK_OUT_PHASE": [ { "value": "90", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_TRACE_ASYNC_RESET": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_TRACE_PROTOCOL": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_TRACE_ID": [ { "value": "110", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_S_AXI_ADDR_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_S_AXI_ACLK_FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_M_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_M_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_M_AXI_THREAD_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_ADDR_SIZE": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_DATA_SIZE": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_LMB_PROTOCOL": [ { "value": "0", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_M_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_M_AXIS_ID_WIDTH": [ { "value": "7", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "kintex7" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7k410t" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "25" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../dl814_k7_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_mdm_1_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2023.2.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "Debug_SYS_Rst": [ { "direction": "out" } ],
+        "Dbg_Clk_0": [ { "direction": "out" } ],
+        "Dbg_TDI_0": [ { "direction": "out" } ],
+        "Dbg_TDO_0": [ { "direction": "in", "driver_value": "0" } ],
+        "Dbg_Reg_En_0": [ { "direction": "out", "size_left": "0", "size_right": "7" } ],
+        "Dbg_Capture_0": [ { "direction": "out" } ],
+        "Dbg_Shift_0": [ { "direction": "out" } ],
+        "Dbg_Update_0": [ { "direction": "out" } ],
+        "Dbg_Rst_0": [ { "direction": "out" } ],
+        "Dbg_Disable_0": [ { "direction": "out" } ]
+      },
+      "interfaces": {
+        "RST.Debug_SYS_Rst": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "Debug_SYS_Rst" } ]
+          }
+        },
+        "MBDEBUG_0": {
+          "vlnv": "xilinx.com:interface:mbdebug:3.0",
+          "abstraction_type": "xilinx.com:interface:mbdebug_rtl:3.0",
+          "mode": "master",
+          "port_maps": {
+            "CAPTURE": [ { "physical_name": "Dbg_Capture_0" } ],
+            "CLK": [ { "physical_name": "Dbg_Clk_0" } ],
+            "DISABLE": [ { "physical_name": "Dbg_Disable_0" } ],
+            "REG_EN": [ { "physical_name": "Dbg_Reg_En_0" } ],
+            "RST": [ { "physical_name": "Dbg_Rst_0" } ],
+            "SHIFT": [ { "physical_name": "Dbg_Shift_0" } ],
+            "TDI": [ { "physical_name": "Dbg_TDI_0" } ],
+            "TDO": [ { "physical_name": "Dbg_TDO_0" } ],
+            "UPDATE": [ { "physical_name": "Dbg_Update_0" } ]
+          }
+        }
+      },
+      "memory_maps": {
+        "S_AXI": {
+          "description": "S_AXI memory map",
+          "address_blocks": {
+            "Reg": {
+              "base_address": "0",
+              "range": "4096",
+              "display_name": "Reg",
+              "description": "Register Block",
+              "usage": "register",
+              "access": "read-write"
+            }
+          }
+        }
+      }
+    }
+  }
+}

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ip/system_bd_microblaze_0_0/system_bd_microblaze_0_0.xci

@@ -0,0 +1,688 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_bd_microblaze_0_0",
+    "cell_name": "microblaze_ps",
+    "component_reference": "xilinx.com:ip:microblaze:11.0",
+    "ip_revision": "12",
+    "gen_directory": "../../../../../../dl814_k7_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_microblaze_0_0",
+    "parameters": {
+      "component_parameters": {
+        "C_SCO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_FREQ": [ { "value": "25000000", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_DATA_SIZE": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_LMB_DATA_SIZE": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_ADDR_SIZE": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_DYNAMIC_BUS_SIZING": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PC_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_INSTANCE": [ { "value": "microblaze", "resolve_type": "user", "usage": "all" } ],
+        "C_AVOID_PRIMITIVES": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_FAULT_TOLERANT": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_ECC_USE_CE_EXCEPTION": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_LOCKSTEP_SLAVE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_TEMPORAL_DEPTH": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_ENDIANNESS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_AREA_OPTIMIZED": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_OPTIMIZATION": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_INTERCONNECT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_BASE_VECTORS": [ { "value": "0x0000000000000000", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
+        "C_USE_CONFIG_RESET": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_NUM_SYNC_FF_CLK": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_NUM_SYNC_FF_CLK_IRQ": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_NUM_SYNC_FF_CLK_DEBUG": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_NUM_SYNC_FF_DBG_CLK": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_NUM_SYNC_FF_DBG_TRACE_CLK": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M_AXI_DP_THREAD_ID_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M_AXI_DP_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M_AXI_DP_ADDR_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M_AXI_DP_EXCLUSIVE_ACCESS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_D_AXI": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_DP_AXI_MON": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_DC_AXI_MON": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_D_LMB": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_D_LMB_PROTOCOL": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_D_LMB_MON": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M_AXI_IP_THREAD_ID_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M_AXI_IP_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M_AXI_IP_ADDR_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_I_AXI": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_IP_AXI_MON": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_IC_AXI_MON": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_I_LMB": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_I_LMB_PROTOCOL": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_I_LMB_MON": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_TRACE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_LOCKSTEP_SELECT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_ENABLE_DISCRETE_PORTS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M_AXI_DC_USER_SIGNALS": [ { "value": "0", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M_AXI_IC_USER_SIGNALS": [ { "value": "0", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "G_TEMPLATE_LIST": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "G_USE_EXCEPTIONS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_USE_MSR_INSTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_USE_PCMP_INSTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_USE_REORDER_INSTR": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_USE_BARREL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_USE_DIV": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_USE_HW_MUL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_USE_FPU": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_UNALIGNED_EXCEPTIONS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_ILL_OPCODE_EXCEPTION": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M_AXI_I_BUS_EXCEPTION": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_M_AXI_D_BUS_EXCEPTION": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_DIV_ZERO_EXCEPTION": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_FPU_EXCEPTION": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_FSL_EXCEPTION": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_USE_STACK_PROTECTION": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_IMPRECISE_EXCEPTIONS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PVR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PVR_USER1": [ { "value": "0x00", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_PVR_USER2": [ { "value": "0x00000000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_DEBUG_ENABLED": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_DEBUG_INTERFACE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_NUMBER_OF_PC_BRK": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_NUMBER_OF_RD_ADDR_BRK": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_NUMBER_OF_WR_ADDR_BRK": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_DEBUG_EVENT_COUNTERS": [ { "value": "5", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_DEBUG_LATENCY_COUNTERS": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_DEBUG_COUNTER_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_DEBUG_TRACE_SIZE": [ { "value": "8192", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_DEBUG_EXTERNAL_TRACE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_DEBUG_TRACE_ASYNC_RESET": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_DEBUG_PROFILE_SIZE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_INTERRUPT_IS_EDGE": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_EDGE_IS_POSITIVE": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_ASYNC_INTERRUPT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_ASYNC_WAKEUP": [ { "value": "3", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_RESET_MSR_IE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_RESET_MSR_BIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_RESET_MSR_ICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_RESET_MSR_DCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_RESET_MSR_EE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_RESET_MSR_EIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_OPCODE_0x0_ILLEGAL": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_FSL_LINKS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_USE_EXTENDED_FSL_INSTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_M0_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
+        "C_S0_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
+        "C_M1_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
+        "C_S1_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
+        "C_M2_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
+        "C_S2_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
+        "C_M3_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
+        "C_S3_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
+        "C_M4_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
+        "C_S4_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
+        "C_M5_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
+        "C_S5_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
+        "C_M6_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
+        "C_S6_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
+        "C_M7_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
+        "C_S7_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
+        "C_M8_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
+        "C_S8_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
+        "C_M9_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
+        "C_S9_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
+        "C_M10_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
+        "C_S10_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
+        "C_M11_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
+        "C_S11_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
+        "C_M12_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
+        "C_S12_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
+        "C_M13_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
+        "C_S13_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
+        "C_M14_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
+        "C_S14_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
+        "C_M15_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
+        "C_S15_AXIS_PROTOCOL": [ { "value": "GENERIC", "resolve_type": "user", "usage": "all" } ],
+        "C_M0_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_S0_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M1_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_S1_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M2_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_S2_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M3_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_S3_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M4_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_S4_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M5_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_S5_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M6_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_S6_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M7_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_S7_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M8_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_S8_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M9_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_S9_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M10_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_S10_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M11_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_S11_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M12_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_S12_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M13_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_S13_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M14_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_S14_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M15_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_S15_AXIS_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_ICACHE_BASEADDR": [ { "value": "0x0000000000000000", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_ICACHE_HIGHADDR": [ { "value": "0x000000003fffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_USE_ICACHE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_ALLOW_ICACHE_WR": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_ADDR_TAG_BITS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_CACHE_BYTE_SIZE": [ { "value": "8192", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_ICACHE_LINE_LEN": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_ICACHE_ALWAYS_USED": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_ICACHE_VICTIMS": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_ICACHE_STREAMS": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_ICACHE_FORCE_TAG_LUTRAM": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_ICACHE_DATA_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_M_AXI_IC_THREAD_ID_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M_AXI_IC_ADDR_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M_AXI_IC_AWUSER_WIDTH": [ { "value": "5", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M_AXI_IC_ARUSER_WIDTH": [ { "value": "5", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M_AXI_IC_WUSER_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M_AXI_IC_RUSER_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M_AXI_IC_BUSER_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M_AXI_IC_USER_VALUE": [ { "value": "31", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_DCACHE_BASEADDR": [ { "value": "0x0000000000000000", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_DCACHE_HIGHADDR": [ { "value": "0x000000003fffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ],
+        "C_USE_DCACHE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_ALLOW_DCACHE_WR": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_DCACHE_ADDR_TAG": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_DCACHE_BYTE_SIZE": [ { "value": "8192", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_DCACHE_LINE_LEN": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_DCACHE_ALWAYS_USED": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_DCACHE_USE_WRITEBACK": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_DCACHE_VICTIMS": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_DCACHE_FORCE_TAG_LUTRAM": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_DCACHE_DATA_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_M_AXI_DC_THREAD_ID_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M_AXI_DC_ADDR_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M_AXI_DC_AWUSER_WIDTH": [ { "value": "5", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M_AXI_DC_ARUSER_WIDTH": [ { "value": "5", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M_AXI_DC_WUSER_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M_AXI_DC_RUSER_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M_AXI_DC_BUSER_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M_AXI_DC_EXCLUSIVE_ACCESS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_M_AXI_DC_USER_VALUE": [ { "value": "31", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_USE_MMU": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_MMU_DTLB_SIZE": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_MMU_ITLB_SIZE": [ { "value": "2", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_MMU_TLB_ACCESS": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "C_MMU_ZONES": [ { "value": "16", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "12" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../dl814_k7_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_microblaze_0_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2023.2.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "Clk": [ { "direction": "in" } ],
+        "Reset": [ { "direction": "in" } ],
+        "Interrupt": [ { "direction": "in", "driver_value": "0" } ],
+        "Interrupt_Address": [ { "direction": "in", "size_left": "0", "size_right": "31", "driver_value": "0" } ],
+        "Interrupt_Ack": [ { "direction": "out", "size_left": "0", "size_right": "1" } ],
+        "Instr_Addr": [ { "direction": "out", "size_left": "0", "size_right": "31" } ],
+        "Instr": [ { "direction": "in", "size_left": "0", "size_right": "31", "driver_value": "0" } ],
+        "IFetch": [ { "direction": "out" } ],
+        "I_AS": [ { "direction": "out" } ],
+        "IReady": [ { "direction": "in", "driver_value": "0" } ],
+        "IWAIT": [ { "direction": "in", "driver_value": "0" } ],
+        "ICE": [ { "direction": "in", "driver_value": "0" } ],
+        "IUE": [ { "direction": "in", "driver_value": "0" } ],
+        "Data_Addr": [ { "direction": "out", "size_left": "0", "size_right": "31" } ],
+        "Data_Read": [ { "direction": "in", "size_left": "0", "size_right": "31", "driver_value": "0" } ],
+        "Data_Write": [ { "direction": "out", "size_left": "0", "size_right": "31" } ],
+        "D_AS": [ { "direction": "out" } ],
+        "Read_Strobe": [ { "direction": "out" } ],
+        "Write_Strobe": [ { "direction": "out" } ],
+        "DReady": [ { "direction": "in", "driver_value": "0" } ],
+        "DWait": [ { "direction": "in", "driver_value": "0" } ],
+        "DCE": [ { "direction": "in", "driver_value": "0" } ],
+        "DUE": [ { "direction": "in", "driver_value": "0" } ],
+        "Byte_Enable": [ { "direction": "out", "size_left": "0", "size_right": "3" } ],
+        "M_AXI_DP_AWADDR": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "M_AXI_DP_AWPROT": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
+        "M_AXI_DP_AWVALID": [ { "direction": "out" } ],
+        "M_AXI_DP_AWREADY": [ { "direction": "in", "driver_value": "0" } ],
+        "M_AXI_DP_WDATA": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "M_AXI_DP_WSTRB": [ { "direction": "out", "size_left": "3", "size_right": "0" } ],
+        "M_AXI_DP_WVALID": [ { "direction": "out" } ],
+        "M_AXI_DP_WREADY": [ { "direction": "in", "driver_value": "0" } ],
+        "M_AXI_DP_BRESP": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
+        "M_AXI_DP_BVALID": [ { "direction": "in", "driver_value": "0" } ],
+        "M_AXI_DP_BREADY": [ { "direction": "out" } ],
+        "M_AXI_DP_ARADDR": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
+        "M_AXI_DP_ARPROT": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
+        "M_AXI_DP_ARVALID": [ { "direction": "out" } ],
+        "M_AXI_DP_ARREADY": [ { "direction": "in", "driver_value": "0" } ],
+        "M_AXI_DP_RDATA": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "M_AXI_DP_RRESP": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0" } ],
+        "M_AXI_DP_RVALID": [ { "direction": "in", "driver_value": "0" } ],
+        "M_AXI_DP_RREADY": [ { "direction": "out" } ],
+        "Dbg_Clk": [ { "direction": "in", "driver_value": "0" } ],
+        "Dbg_TDI": [ { "direction": "in", "driver_value": "0" } ],
+        "Dbg_TDO": [ { "direction": "out" } ],
+        "Dbg_Reg_En": [ { "direction": "in", "size_left": "0", "size_right": "7", "driver_value": "0" } ],
+        "Dbg_Shift": [ { "direction": "in", "driver_value": "0" } ],
+        "Dbg_Capture": [ { "direction": "in", "driver_value": "0" } ],
+        "Dbg_Update": [ { "direction": "in", "driver_value": "0" } ],
+        "Debug_Rst": [ { "direction": "in", "driver_value": "0" } ],
+        "Dbg_Disable": [ { "direction": "in", "driver_value": "0" } ]
+      },
+      "interfaces": {
+        "CLK.CLK": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "M0_AXIS:S0_AXIS:M1_AXIS:S1_AXIS:M2_AXIS:S2_AXIS:M3_AXIS:S3_AXIS:M4_AXIS:S4_AXIS:M5_AXIS:S5_AXIS:M6_AXIS:S6_AXIS:M7_AXIS:S7_AXIS:M8_AXIS:S8_AXIS:M9_AXIS:S9_AXIS:M10_AXIS:S10_AXIS:M11_AXIS:S11_AXIS:M12_AXIS:S12_AXIS:M13_AXIS:S13_AXIS:M14_AXIS:S14_AXIS:M15_AXIS:S15_AXIS:DLMB:ILMB:M_AXI_DP:M_AXI_IP:M_AXI_DC:M_AXI_IC:M_ACE_DC:M_ACE_IC:MON_DLMB:MON_ILMB:MON_AXI_DP:MON_AXI_IP:MON_AXI_DC:MON_AXI_IC:MON_ACE_DC:MON_ACE_IC", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "Reset", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "25000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "/clk_wiz_25M_clk_out1", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "Clk" } ]
+          }
+        },
+        "RST.RESET": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "TYPE": [ { "value": "PROCESSOR", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "Reset" } ]
+          }
+        },
+        "INTERRUPT": {
+          "vlnv": "xilinx.com:interface:mbinterrupt:1.0",
+          "abstraction_type": "xilinx.com:interface:mbinterrupt_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_permission": "bd", "resolve_type": "generated", "usage": "all" } ],
+            "LOW_LATENCY": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "usage": "all" } ]
+          },
+          "port_maps": {
+            "ACK": [ { "physical_name": "Interrupt_Ack" } ],
+            "ADDRESS": [ { "physical_name": "Interrupt_Address" } ],
+            "INTERRUPT": [ { "physical_name": "Interrupt" } ]
+          }
+        },
+        "DLMB": {
+          "vlnv": "xilinx.com:interface:lmb:1.0",
+          "abstraction_type": "xilinx.com:interface:lmb_rtl:1.0",
+          "mode": "master",
+          "address_space_ref": "Data",
+          "parameters": {
+            "ADDR_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+            "DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+            "PROTOCOL": [ { "value": "STANDARD", "value_permission": "bd", "resolve_type": "dependent", "usage": "all" } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ]
+          },
+          "port_maps": {
+            "ABUS": [ { "physical_name": "Data_Addr" } ],
+            "ADDRSTROBE": [ { "physical_name": "D_AS" } ],
+            "BE": [ { "physical_name": "Byte_Enable" } ],
+            "CE": [ { "physical_name": "DCE" } ],
+            "READDBUS": [ { "physical_name": "Data_Read" } ],
+            "READSTROBE": [ { "physical_name": "Read_Strobe" } ],
+            "READY": [ { "physical_name": "DReady" } ],
+            "UE": [ { "physical_name": "DUE" } ],
+            "WAIT": [ { "physical_name": "DWait" } ],
+            "WRITEDBUS": [ { "physical_name": "Data_Write" } ],
+            "WRITESTROBE": [ { "physical_name": "Write_Strobe" } ]
+          }
+        },
+        "ILMB": {
+          "vlnv": "xilinx.com:interface:lmb:1.0",
+          "abstraction_type": "xilinx.com:interface:lmb_rtl:1.0",
+          "mode": "master",
+          "address_space_ref": "Instruction",
+          "parameters": {
+            "ADDR_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+            "DATA_WIDTH": [ { "value": "32", "value_permission": "bd", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+            "PROTOCOL": [ { "value": "STANDARD", "value_permission": "bd", "resolve_type": "dependent", "usage": "all" } ],
+            "READ_WRITE_MODE": [ { "value": "READ_ONLY", "value_src": "constant", "value_permission": "bd", "usage": "all" } ]
+          },
+          "port_maps": {
+            "ABUS": [ { "physical_name": "Instr_Addr" } ],
+            "ADDRSTROBE": [ { "physical_name": "I_AS" } ],
+            "CE": [ { "physical_name": "ICE" } ],
+            "READDBUS": [ { "physical_name": "Instr" } ],
+            "READSTROBE": [ { "physical_name": "IFetch" } ],
+            "READY": [ { "physical_name": "IReady" } ],
+            "UE": [ { "physical_name": "IUE" } ],
+            "WAIT": [ { "physical_name": "IWAIT" } ]
+          }
+        },
+        "M_AXI_DP": {
+          "vlnv": "xilinx.com:interface:aximm:1.0",
+          "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
+          "mode": "master",
+          "address_space_ref": "Data",
+          "parameters": {
+            "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
+            "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
+            "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
+            "HAS_LOCK": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+            "DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+            "ADDR_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+            "NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
+            "NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
+            "NUM_READ_THREADS": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
+            "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
+            "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ],
+            "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "25000000", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_CACHE": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_QOS": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_RRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "/clk_wiz_25M_clk_out1", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "ARADDR": [ { "physical_name": "M_AXI_DP_ARADDR" } ],
+            "ARPROT": [ { "physical_name": "M_AXI_DP_ARPROT" } ],
+            "ARREADY": [ { "physical_name": "M_AXI_DP_ARREADY" } ],
+            "ARVALID": [ { "physical_name": "M_AXI_DP_ARVALID" } ],
+            "AWADDR": [ { "physical_name": "M_AXI_DP_AWADDR" } ],
+            "AWPROT": [ { "physical_name": "M_AXI_DP_AWPROT" } ],
+            "AWREADY": [ { "physical_name": "M_AXI_DP_AWREADY" } ],
+            "AWVALID": [ { "physical_name": "M_AXI_DP_AWVALID" } ],
+            "BREADY": [ { "physical_name": "M_AXI_DP_BREADY" } ],
+            "BRESP": [ { "physical_name": "M_AXI_DP_BRESP" } ],
+            "BVALID": [ { "physical_name": "M_AXI_DP_BVALID" } ],
+            "RDATA": [ { "physical_name": "M_AXI_DP_RDATA" } ],
+            "RREADY": [ { "physical_name": "M_AXI_DP_RREADY" } ],
+            "RRESP": [ { "physical_name": "M_AXI_DP_RRESP" } ],
+            "RVALID": [ { "physical_name": "M_AXI_DP_RVALID" } ],
+            "WDATA": [ { "physical_name": "M_AXI_DP_WDATA" } ],
+            "WREADY": [ { "physical_name": "M_AXI_DP_WREADY" } ],
+            "WSTRB": [ { "physical_name": "M_AXI_DP_WSTRB" } ],
+            "WVALID": [ { "physical_name": "M_AXI_DP_WVALID" } ]
+          }
+        },
+        "DEBUG": {
+          "vlnv": "xilinx.com:interface:mbdebug:3.0",
+          "abstraction_type": "xilinx.com:interface:mbdebug_rtl:3.0",
+          "mode": "slave",
+          "port_maps": {
+            "CAPTURE": [ { "physical_name": "Dbg_Capture" } ],
+            "CLK": [ { "physical_name": "Dbg_Clk" } ],
+            "DISABLE": [ { "physical_name": "Dbg_Disable" } ],
+            "REG_EN": [ { "physical_name": "Dbg_Reg_En" } ],
+            "RST": [ { "physical_name": "Debug_Rst" } ],
+            "SHIFT": [ { "physical_name": "Dbg_Shift" } ],
+            "TDI": [ { "physical_name": "Dbg_TDI" } ],
+            "TDO": [ { "physical_name": "Dbg_TDO" } ],
+            "UPDATE": [ { "physical_name": "Dbg_Update" } ]
+          }
+        }
+      },
+      "address_spaces": {
+        "Data": {
+          "range": "4294967296",
+          "width": "32"
+        },
+        "Instruction": {
+          "range": "4294967296",
+          "width": "32"
+        }
+      },
+      "memory_maps": {
+        "S_AXI_DEBUG": {
+          "description": "AXI debug memory map",
+          "address_blocks": {
+            "Reg": {
+              "base_address": "0",
+              "range": "4096",
+              "display_name": "Reg",
+              "description": "Debug Register Block",
+              "usage": "register",
+              "access": "read-write"
+            }
+          }
+        }
+      }
+    },
+    "contents": {
+      "cpus": {
+        "microblaze": {
+          "address_space_refs": "Data",
+          "parameters": {
+            "endian": [ { "value": "little" } ],
+            "elf_class": [ { "value": "32-bit" } ],
+            "instance_path": [ { "value": "" } ],
+            "bootloop_file": [ { "value": "data/mb_bootloop_le.elf" } ],
+            "processor_type": [ { "value": "MICROBLAZE_LE" } ],
+            "is_visible": [ { "value": "true" } ]
+          }
+        }
+      }
+    }
+  }
+}

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ip/system_bd_microblaze_ps_axi_periph_0/system_bd_microblaze_ps_axi_periph_0.xci

@@ -0,0 +1,352 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_bd_microblaze_ps_axi_periph_0",
+    "cell_name": "microblaze_ps_axi_periph",
+    "component_reference": "xilinx.com:ip:axi_interconnect:2.1",
+    "ip_revision": "31",
+    "gen_directory": "../../../../../../dl814_k7_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_microblaze_ps_axi_periph_0",
+    "parameters": {
+      "component_parameters": {
+        "NUM_SI": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "NUM_MI": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "STRATEGY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ENABLE_ADVANCED_OPTIONS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
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+}

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ip/system_bd_rst_clk_wiz_1_100M_0/system_bd_rst_clk_wiz_1_100M_0.xci

@@ -0,0 +1,195 @@
+{
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+          "parameters": {
+            "ASSOCIATED_RESET": [ { "value": "mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "25000000", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "/clk_wiz_25M_clk_out1", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "slowest_sync_clk" } ]
+          }
+        },
+        "ext_reset": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "BOARD.ASSOCIATED_PARAM": [ { "value": "RESET_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "ext_reset_in" } ]
+          }
+        },
+        "aux_reset": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "aux_reset_in" } ]
+          }
+        },
+        "dbg_reset": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "mb_debug_sys_rst" } ]
+          }
+        },
+        "mb_rst": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "TYPE": [ { "value": "PROCESSOR", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "mb_reset" } ]
+          }
+        },
+        "bus_struct_reset": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "TYPE": [ { "value": "INTERCONNECT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "bus_struct_reset" } ]
+          }
+        },
+        "interconnect_low_rst": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "TYPE": [ { "value": "INTERCONNECT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "interconnect_aresetn" } ]
+          }
+        },
+        "peripheral_high_rst": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "TYPE": [ { "value": "PERIPHERAL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "peripheral_reset" } ]
+          }
+        },
+        "peripheral_low_rst": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "TYPE": [ { "value": "PERIPHERAL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "peripheral_aresetn" } ]
+          }
+        }
+      }
+    }
+  }
+}

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_0/system_bd_spi_engine_execution_0_0.xci

@@ -0,0 +1,175 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "system_bd_spi_engine_execution_0_0",
+    "cell_name": "axi_spi_engine/spi_engine_execution",
+    "component_reference": "analog.com:user:spi_engine_execution:1.0",
+    "ip_revision": "1",
+    "gen_directory": "../../../../../../dl814_k7_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_0",
+    "parameters": {
+      "component_parameters": {
+        "NUM_OF_CS": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "DEFAULT_SPI_CFG": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "DEFAULT_CLK_DIV": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "DATA_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "NUM_OF_SDI": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "SDO_DEFAULT": [ { "value": "\"0\"", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
+        "ECHO_SCLK": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "SDI_DELAY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Component_Name": [ { "value": "system_bd_spi_engine_execution_0_0", "resolve_type": "user", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "NUM_OF_CS": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "DEFAULT_SPI_CFG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "DEFAULT_CLK_DIV": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "DATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "NUM_OF_SDI": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "SDO_DEFAULT": [ { "value": "\"0\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
+        "ECHO_SCLK": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
+        "SDI_DELAY": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "kintex7" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7k410t" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPREVISION": [ { "value": "1" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../../../dl814_k7_cal_coarse.gen/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_0" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SWVERSION": [ { "value": "2023.2.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "clk": [ { "direction": "in" } ],
+        "resetn": [ { "direction": "in" } ],
+        "active": [ { "direction": "out" } ],
+        "cmd_ready": [ { "direction": "out" } ],
+        "cmd_valid": [ { "direction": "in" } ],
+        "cmd": [ { "direction": "in", "size_left": "15", "size_right": "0" } ],
+        "sdo_data_valid": [ { "direction": "in", "driver_value": "0" } ],
+        "sdo_data_ready": [ { "direction": "out" } ],
+        "sdo_data": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ],
+        "sdi_data_ready": [ { "direction": "in", "driver_value": "0" } ],
+        "sdi_data_valid": [ { "direction": "out" } ],
+        "sdi_data": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
+        "sync_ready": [ { "direction": "in" } ],
+        "sync_valid": [ { "direction": "out" } ],
+        "sync": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
+        "sclk": [ { "direction": "out" } ],
+        "sdo": [ { "direction": "out" } ],
+        "sdo_t": [ { "direction": "out" } ],
+        "sdi": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
+        "cs": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
+        "three_wire": [ { "direction": "out" } ]
+      },
+      "interfaces": {
+        "ctrl": {
+          "vlnv": "analog.com:interface:spi_engine_ctrl:1.0",
+          "abstraction_type": "analog.com:interface:spi_engine_ctrl_rtl:1.0",
+          "mode": "slave",
+          "port_maps": {
+            "CMD_READY": [ { "physical_name": "cmd_ready" } ],
+            "CMD_VALID": [ { "physical_name": "cmd_valid" } ],
+            "CMD_DATA": [ { "physical_name": "cmd" } ],
+            "SDO_READY": [ { "physical_name": "sdo_data_ready" } ],
+            "SDO_VALID": [ { "physical_name": "sdo_data_valid" } ],
+            "SDO_DATA": [ { "physical_name": "sdo_data" } ],
+            "SDI_READY": [ { "physical_name": "sdi_data_ready" } ],
+            "SDI_VALID": [ { "physical_name": "sdi_data_valid" } ],
+            "SDI_DATA": [ { "physical_name": "sdi_data" } ],
+            "SYNC_READY": [ { "physical_name": "sync_ready" } ],
+            "SYNC_VALID": [ { "physical_name": "sync_valid" } ],
+            "SYNC_DATA": [ { "physical_name": "sync" } ]
+          }
+        },
+        "ctrl_signal_clock": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "ctrl", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "clk" } ]
+          }
+        },
+        "ctrl_signal_reset": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "resetn" } ]
+          }
+        },
+        "spi": {
+          "vlnv": "analog.com:interface:spi_master:1.0",
+          "abstraction_type": "analog.com:interface:spi_master_rtl:1.0",
+          "mode": "master",
+          "port_maps": {
+            "SCLK": [ { "physical_name": "sclk" } ],
+            "SDI": [ { "physical_name": "sdi" } ],
+            "SDO": [ { "physical_name": "sdo" } ],
+            "SDO_T": [ { "physical_name": "sdo_t" } ],
+            "THREE_WIRE": [ { "physical_name": "three_wire" } ],
+            "CS": [ { "physical_name": "cs" } ]
+          }
+        },
+        "spi_signal_clock": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "spi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "25000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "/clk_wiz_25M_clk_out1", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "clk" } ]
+          }
+        },
+        "spi_signal_reset": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "RST": [ { "physical_name": "resetn" } ]
+          }
+        }
+      }
+    }
+  }
+}

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/system_bd.bda

@@ -0,0 +1,295 @@
+{
+    "graphjs": {
+        "version": "1.0",
+        "keys": [
+            {
+                "abrv": "VH",
+                "name": "vert_hid",
+                "type": "int",
+                "for": "node"
+            },
+            {
+                "abrv": "VM",
+                "name": "vert_name",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "VT",
+                "name": "vert_type",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "BA",
+                "name": "base_addr",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "HA",
+                "name": "high_addr",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "BP",
+                "name": "base_param",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "HP",
+                "name": "high_param",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "MA",
+                "name": "master_addrspace",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "MX",
+                "name": "master_instance",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "MI",
+                "name": "master_interface",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "MS",
+                "name": "master_segment",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "MV",
+                "name": "master_vlnv",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "SX",
+                "name": "slave_instance",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "SI",
+                "name": "slave_interface",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "MM",
+                "name": "slave_memmap",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "SS",
+                "name": "slave_segment",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "SV",
+                "name": "slave_vlnv",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "TM",
+                "name": "memory_type",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "TU",
+                "name": "usage_type",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "LT",
+                "name": "lock_type",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "BT",
+                "name": "boot_type",
+                "type": "string",
+                "for": "node"
+            },
+            {
+                "abrv": "EH",
+                "name": "edge_hid",
+                "type": "int",
+                "for": "edge"
+            }
+        ],
+        "vertice_type_order": [
+            {
+                "abrv": "BC",
+                "desc": "Block Container"
+            },
+            {
+                "abrv": "PR",
+                "desc": "Parital Reference"
+            },
+            {
+                "abrv": "VR",
+                "desc": "Variant"
+            },
+            {
+                "abrv": "PM",
+                "desc": "Variant Permutations"
+            },
+            {
+                "abrv": "CX",
+                "desc": "Boundary Connection"
+            },
+            {
+                "abrv": "AC",
+                "desc": "Assignment Coordinate"
+            },
+            {
+                "abrv": "ACE",
+                "desc": "Excluded Assign Coordinate"
+            },
+            {
+                "abrv": "APX",
+                "desc": "Boundary Aperture"
+            },
+            {
+                "abrv": "CIP",
+                "desc": "High level Processing System"
+            }
+        ],
+        "vertices": {
+            "V0": {
+                "VM": "system_bd",
+                "VT": "BC"
+            },
+            "V1": {
+                "VH": "2",
+                "VM": "system_bd",
+                "VT": "VR"
+            },
+            "V2": {
+                "VH": "2",
+                "VT": "PM",
+                "TU": "active"
+            },
+            "V3": {
+                "VT": "AC",
+                "BA": "0x00000000",
+                "HA": "0x0003FFFF",
+                "BP": "C_BASEADDR",
+                "HP": "C_HIGHADDR",
+                "MA": "Data",
+                "MX": "/microblaze_ps",
+                "MI": "DLMB",
+                "MS": "SEG_dlmb_bram_if_cntlr_Mem",
+                "MV": "xilinx.com:ip:microblaze:11.0",
+                "SX": "/microblaze_ps_local_memory/dlmb_bram_if_cntlr",
+                "SI": "SLMB",
+                "SS": "Mem",
+                "SV": "xilinx.com:ip:lmb_bram_if_cntlr:4.0",
+                "TM": "data",
+                "TU": "memory"
+            },
+            "V4": {
+                "VT": "AC",
+                "BA": "0x00000000",
+                "HA": "0x0003FFFF",
+                "BP": "C_BASEADDR",
+                "HP": "C_HIGHADDR",
+                "MA": "Instruction",
+                "MX": "/microblaze_ps",
+                "MI": "ILMB",
+                "MS": "SEG_ilmb_bram_if_cntlr_Mem",
+                "MV": "xilinx.com:ip:microblaze:11.0",
+                "SX": "/microblaze_ps_local_memory/ilmb_bram_if_cntlr",
+                "SI": "SLMB",
+                "SS": "Mem",
+                "SV": "xilinx.com:ip:lmb_bram_if_cntlr:4.0",
+                "TM": "instruction",
+                "TU": "memory"
+            },
+            "V5": {
+                "VT": "AC",
+                "BA": "0x40000000",
+                "HA": "0x4000FFFF",
+                "BP": "C_BASEADDR",
+                "HP": "C_HIGHADDR",
+                "MA": "Data",
+                "MX": "/microblaze_ps",
+                "MI": "M_AXI_DP",
+                "MS": "SEG_axi_gpio_Reg",
+                "MV": "xilinx.com:ip:microblaze:11.0",
+                "SX": "/axi_gpio",
+                "SI": "S_AXI",
+                "SS": "Reg",
+                "SV": "xilinx.com:ip:axi_gpio:2.0",
+                "TM": "data",
+                "TU": "register"
+            },
+            "V6": {
+                "VT": "AC",
+                "BA": "0x44A00000",
+                "HA": "0x44A0FFFF",
+                "BP": "C_BASEADDR",
+                "HP": "C_HIGHADDR",
+                "MA": "Data",
+                "MX": "/microblaze_ps",
+                "MI": "M_AXI_DP",
+                "MS": "SEG_axi_spi_engine_axi_lite",
+                "MV": "xilinx.com:ip:microblaze:11.0",
+                "SX": "/axi_spi_engine/axi_spi_engine",
+                "SI": "s_axi",
+                "SS": "axi_lite",
+                "SV": "analog.com:user:axi_spi_engine:1.0",
+                "TM": "data",
+                "TU": "register"
+            }
+        },
+        "edges": [
+            {
+                "src": "V0",
+                "trg": "V1"
+            },
+            {
+                "src": "V1",
+                "trg": "V2"
+            },
+            {
+                "src": "V3",
+                "trg": "V2",
+                "EH": "2"
+            },
+            {
+                "src": "V4",
+                "trg": "V2",
+                "EH": "2"
+            },
+            {
+                "src": "V5",
+                "trg": "V2",
+                "EH": "2"
+            },
+            {
+                "src": "V6",
+                "trg": "V2",
+                "EH": "2"
+            }
+        ]
+    }
+}

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ui/bd_c6d0cb12.ui

@@ -0,0 +1,45 @@
+{
+   "ActiveEmotionalView":"Default View",
+   "Default View_ScaleFactor":"0.598662",
+   "Default View_TopLeft":"-484,3",
+   "ExpandedHierarchyInLayout":"",
+   "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 TLS
+#  -string -flagsOSRD
+preplace port spi -pg 1 -lvl 3 -x 1010 -y 300 -defaultsOSRD
+preplace port port-id_clk_25MHz -pg 1 -lvl 0 -x 0 -y 650 -defaultsOSRD
+preplace port port-id_spi_active -pg 1 -lvl 3 -x 1010 -y 320 -defaultsOSRD
+preplace portBus gpio_o -pg 1 -lvl 3 -x 1010 -y 80 -defaultsOSRD
+preplace portBus gpio_i -pg 1 -lvl 3 -x 1010 -y 120 -defaultsOSRD -right
+preplace inst microblaze_ps -pg 1 -lvl 1 -x 310 -y 510 -defaultsOSRD
+preplace inst microblaze_ps_local_memory -pg 1 -lvl 2 -x 790 -y 520 -defaultsOSRD
+preplace inst mdm -pg 1 -lvl 1 -x 310 -y 770 -defaultsOSRD
+preplace inst clk_wiz_25M -pg 1 -lvl 1 -x 310 -y 650 -defaultsOSRD
+preplace inst rst_clk_wiz_25M -pg 1 -lvl 2 -x 790 -y 760 -defaultsOSRD
+preplace inst axi_spi_engine -pg 1 -lvl 2 -x 790 -y 320 -defaultsOSRD
+preplace inst microblaze_ps_axi_periph -pg 1 -lvl 1 -x 310 -y 300 -defaultsOSRD
+preplace inst axi_gpio -pg 1 -lvl 1 -x 310 -y 90 -defaultsOSRD
+preplace netloc axi_gpio_gpio_io_o 1 1 2 NJ 80 NJ
+preplace netloc axi_spi_engine_active_0 1 2 1 N 320
+preplace netloc clk_in1_0_1 1 0 1 N 650
+preplace netloc clk_wiz_1_locked 1 1 1 590 660n
+preplace netloc gpio2_io_i_0_1 1 1 2 N 120 N
+preplace netloc mdm_1_debug_sys_rst 1 1 1 N 780
+preplace netloc microblaze_ps_Clk 1 0 2 40 870 580
+preplace netloc rst_clk_wiz_1_100M_bus_struct_reset 1 1 2 610 660 970J
+preplace netloc rst_clk_wiz_1_100M_mb_reset 1 0 3 20 890 N 890 980
+preplace netloc rst_clk_wiz_25M_peripheral_aresetn 1 0 3 30 880 600 860 970
+preplace netloc axi_spi_engine_spi_0 1 2 1 N 300
+preplace netloc microblaze_ps_M_AXI_DP 1 0 2 70 840 550J
+preplace netloc microblaze_ps_axi_periph_M00_AXI 1 1 1 N 290
+preplace netloc microblaze_ps_axi_periph_M01_AXI 1 0 2 60 850 570
+preplace netloc microblaze_ps_debug 1 0 2 50 860 560J
+preplace netloc microblaze_ps_dlmb_1 1 1 1 N 490
+preplace netloc microblaze_ps_ilmb_1 1 1 1 N 510
+levelinfo -pg 1 0 310 790 1010
+pagesize -pg 1 -db -bbox -sgen -130 0 1150 900
+"
+}
+{
+   "da_axi4_cnt":"2",
+   "da_mb_cnt":"1"
+}

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/bd/system_bd/ui/bd_e4e34314.ui

@@ -0,0 +1,30 @@
+{
+   "ActiveEmotionalView":"Default View",
+   "Default View_ScaleFactor":"1.0",
+   "Default View_TopLeft":"-209,-166",
+   "ExpandedHierarchyInLayout":"",
+   "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 TLS
+#  -string -flagsOSRD
+preplace port s_axi -pg 1 -lvl 0 -x 0 -y 50 -defaultsOSRD
+preplace port spi -pg 1 -lvl 3 -x 690 -y 70 -defaultsOSRD
+preplace port port-id_s_axi_aclk -pg 1 -lvl 0 -x 0 -y 70 -defaultsOSRD
+preplace port port-id_s_axi_aresetn -pg 1 -lvl 0 -x 0 -y 90 -defaultsOSRD
+preplace port port-id_spi_clk -pg 1 -lvl 0 -x 0 -y 110 -defaultsOSRD
+preplace port port-id_active -pg 1 -lvl 3 -x 690 -y 90 -defaultsOSRD
+preplace port port-id_irq -pg 1 -lvl 3 -x 690 -y 0 -defaultsOSRD
+preplace inst axi_spi_engine -pg 1 -lvl 1 -x 320 -y 80 -defaultsOSRD
+preplace inst spi_engine_execution -pg 1 -lvl 2 -x 570 -y 80 -defaultsOSRD
+preplace netloc s_axi_aclk_0_1 1 0 1 NJ 70
+preplace netloc spi_clk_0_1 1 0 2 180 170 470J
+preplace netloc axi_spi_engine_spi_resetn 1 1 1 N 100
+preplace netloc spi_engine_execution_0_active 1 2 1 NJ 90
+preplace netloc axi_spi_engine_irq 1 1 2 460J 0 NJ
+preplace netloc s_axi_aresetn_1 1 0 1 NJ 90
+preplace netloc axi_spi_engine_spi_engine_ctrl 1 1 1 N 60
+preplace netloc Conn1 1 0 1 NJ 50
+preplace netloc Conn2 1 2 1 NJ 70
+levelinfo -pg 1 0 320 570 690
+pagesize -pg 1 -db -bbox -sgen -150 -200 790 310
+"
+}
+

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/ad9361_clk_gen_cmos_2t2r/ad9361_clk_gen_cmos_2t2r.xci

@@ -0,0 +1,713 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "ad9361_clk_gen_cmos_2t2r",
+    "component_reference": "xilinx.com:ip:clk_wiz:6.0",
+    "ip_revision": "13",
+    "gen_directory": "../../../../dl814_k7_cal_coarse.gen/sources_1/ip/ad9361_clk_gen_cmos_2t2r",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "ad9361_clk_gen_cmos_2t2r", "resolve_type": "user", "usage": "all" } ],
+        "USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "ENABLE_CLOCK_MONITOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ENABLE_USER_CLOCK0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ENABLE_USER_CLOCK1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ENABLE_USER_CLOCK2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ENABLE_USER_CLOCK3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_PLL0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_PLL1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
+        "PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ],
+        "CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
+        "USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_PHASE_ALIGNMENT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ],
+        "PRIM_IN_FREQ": [ { "value": "96", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ],
+        "PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "user", "usage": "all" } ],
+        "IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ],
+        "RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ],
+        "USE_INCLK_SWITCHOVER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ],
+        "SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
+        "JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ],
+        "CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKIN1_JITTER_PS": [ { "value": "104.16", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT2_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT3_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT4_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "NUM_OUT_CLKS": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ],
+        "DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ],
+        "DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ],
+        "DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ],
+        "DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ],
+        "DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ],
+        "DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ],
+        "DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ],
+        "PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ],
+        "PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ],
+        "PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ],
+        "PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "48", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "96", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "144", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "192", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ],
+        "PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ],
+        "SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
+        "USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
+        "USE_RESET": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ],
+        "LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ],
+        "POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ],
+        "CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ],
+        "STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ],
+        "CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ],
+        "INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ],
+        "SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ],
+        "SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
+        "MMCM_DIVCLK_DIVIDE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
+        "MMCM_CLKFBOUT_MULT_F": [ { "value": "12.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKIN1_PERIOD": [ { "value": "10.417", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKIN2_PERIOD": [ { "value": "10.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "user", "usage": "all" } ],
+        "MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT0_DIVIDE_F": [ { "value": "24.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT1_DIVIDE": [ { "value": "12", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT2_DIVIDE": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT3_DIVIDE": [ { "value": "6", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
+        "PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
+        "PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ],
+        "PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKIN_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ],
+        "PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "RESET_TYPE": [ { "value": "ACTIVE_HIGH", "resolve_type": "user", "usage": "all" } ],
+        "USE_SAFE_CLOCK_STARTUP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_CLOCK_SEQUENCING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "DIFF_CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "DIFF_CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
+        "RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "ENABLE_CDDC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "user", "usage": "all" } ],
+        "CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ],
+        "ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_JITTER": [ { "value": "139.139", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_PHASE_ERROR": [ { "value": "89.958", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_JITTER": [ { "value": "120.859", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_PHASE_ERROR": [ { "value": "89.958", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_JITTER": [ { "value": "112.241", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_PHASE_ERROR": [ { "value": "89.958", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_JITTER": [ { "value": "106.524", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_PHASE_ERROR": [ { "value": "89.958", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "INPUT_MODE": [ { "value": "frequency", "resolve_type": "user", "usage": "all" } ],
+        "INTERFACE_SELECTION": [ { "value": "Enable_AXI", "resolve_type": "user", "usage": "all" } ],
+        "AXI_DRP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "PHASE_DUTY_CONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_CLKOUT2_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
+        "C_USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_ENABLE_CLOCK_MONITOR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_USER_CLOCK0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_USER_CLOCK1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_USER_CLOCK2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_USER_CLOCK3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_Enable_PLL0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_Enable_PLL1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PRECISION": [ { "value": "1", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT4_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT5_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT6_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT7_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKOUT1_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKOUT2_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKOUT3_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKOUT4_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "c_component_name": [ { "value": "ad9361_clk_gen_cmos_2t2r", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_FREQ_SYNTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_PHASE_ALIGNMENT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_MIN_POWER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_MIN_O_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_MAX_I_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_DYN_PHASE_SHIFT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_INCLK_SWITCHOVER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_DYN_RECONFIG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_SPREAD_SPECTRUM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_FAST_SIMULATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIMTYPE_SEL": [ { "value": "AUTO", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_CLK_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIM_IN_FREQ": [ { "value": "96", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "generated", "usage": "all" } ],
+        "C_SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "generated", "usage": "all" } ],
+        "C_PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
+        "C_PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "generated", "usage": "all" } ],
+        "C_SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_RESET": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RESET_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_LOCKED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_INCLK_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKFB_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_POWER_DOWN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_STATUS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_FREEZE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_OUT_CLKS": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_INCLK_SUM_ROW0": [ { "value": "Input Clock   Freq (MHz)    Input Jitter (UI)", "resolve_type": "generated", "usage": "all" } ],
+        "C_INCLK_SUM_ROW1": [ { "value": "__primary______________96____________0.010", "resolve_type": "generated", "usage": "all" } ],
+        "C_INCLK_SUM_ROW2": [ { "value": "no_secondary_input_clock ", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW0A": [ { "value": " Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW0B": [ { "value": "  Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__48.00000______0.000______50.0______139.139_____89.958", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW2": [ { "value": "clk_out2__96.00000______0.000______50.0______120.859_____89.958", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW3": [ { "value": "clk_out3__144.00000______0.000______50.0______112.241_____89.958", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW4": [ { "value": "clk_out4__192.00000______0.000______50.0______106.524_____89.958", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW6": [ { "value": "no_CLK_OUT6_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW7": [ { "value": "no_CLK_OUT7_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "48", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "96", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "144", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "192", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_OUT_FREQ": [ { "value": "48.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_OUT_FREQ": [ { "value": "96.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_OUT_FREQ": [ { "value": "144.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_OUT_FREQ": [ { "value": "192.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_USE_SAFE_CLOCK_STARTUP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLOCK_SEQUENCING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_NOTES": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKFBOUT_MULT_F": [ { "value": "12.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKIN1_PERIOD": [ { "value": "10.417", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKIN2_PERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_CASCADE": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
+        "C_MMCM_CLOCK_HOLD": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
+        "C_MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "24.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT1_DIVIDE": [ { "value": "12", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT2_DIVIDE": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT3_DIVIDE": [ { "value": "6", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_NOTES": [ { "value": "No notes", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_CLKFBOUT_MULT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKIN_PERIOD": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLOCK_MGR_TYPE": [ { "value": "NA", "resolve_type": "generated", "usage": "all" } ],
+        "C_OVERRIDE_MMCM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OVERRIDE_PLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "generated", "usage": "all" } ],
+        "C_SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "generated", "usage": "all" } ],
+        "C_RESET_PORT": [ { "value": "reset", "resolve_type": "generated", "usage": "all" } ],
+        "C_LOCKED_PORT": [ { "value": "locked", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "generated", "usage": "all" } ],
+        "C_POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "generated", "usage": "all" } ],
+        "C_DADDR_PORT": [ { "value": "daddr", "resolve_type": "generated", "usage": "all" } ],
+        "C_DCLK_PORT": [ { "value": "dclk", "resolve_type": "generated", "usage": "all" } ],
+        "C_DRDY_PORT": [ { "value": "drdy", "resolve_type": "generated", "usage": "all" } ],
+        "C_DWE_PORT": [ { "value": "dwe", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIN_PORT": [ { "value": "din", "resolve_type": "generated", "usage": "all" } ],
+        "C_DOUT_PORT": [ { "value": "dout", "resolve_type": "generated", "usage": "all" } ],
+        "C_DEN_PORT": [ { "value": "den", "resolve_type": "generated", "usage": "all" } ],
+        "C_PSCLK_PORT": [ { "value": "psclk", "resolve_type": "generated", "usage": "all" } ],
+        "C_PSEN_PORT": [ { "value": "psen", "resolve_type": "generated", "usage": "all" } ],
+        "C_PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "generated", "usage": "all" } ],
+        "C_PSDONE_PORT": [ { "value": "psdone", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "generated", "usage": "all" } ],
+        "C_STATUS_PORT": [ { "value": "STATUS", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "generated", "usage": "all" } ],
+        "C_INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKIN1_JITTER_PS": [ { "value": "104.16", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
+        "C_SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "generated", "usage": "all" } ],
+        "C_SS_MOD_PERIOD": [ { "value": "4000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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+        "C_HAS_CDDC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "generated", "usage": "all" } ],
+        "C_CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUTPHY_MODE": [ { "value": "VCO", "resolve_type": "generated", "usage": "all" } ],
+        "C_ENABLE_CLKOUTPHY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INTERFACE_SELECTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_ADDR_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_POWER_REG": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT0_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT0_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFBOUT_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFBOUT_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVCLK": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_LOCK_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_LOCK_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_LOCK_3": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
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+        "C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE2_AUTO": [ { "value": "0.5", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE3_AUTO": [ { "value": "0.3333333333333333", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE4_AUTO": [ { "value": "0.25", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE5_AUTO": [ { "value": "0.041666666666666664", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE6_AUTO": [ { "value": "0.041666666666666664", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE7_AUTO": [ { "value": "0.041666666666666664", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLLBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLLBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLLBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLLBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
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+        "C_MMCMBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
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+        "C_MMCMBUFGCEDIV5": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV6": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV7": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT0_ACTUAL_FREQ": [ { "value": "48.00000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_ACTUAL_FREQ": [ { "value": "96.00000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_ACTUAL_FREQ": [ { "value": "144.00000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_ACTUAL_FREQ": [ { "value": "192.00000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
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+        "C_O_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_VCO_MIN": [ { "value": "600.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_VCO_MAX": [ { "value": "1440.000", "resolve_type": "generated", "format": "float", "usage": "all" } ]
+      },
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+        "ARCHITECTURE": [ { "value": "kintex7" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7k410t" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
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+        "IPREVISION": [ { "value": "13" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../dl814_k7_cal_coarse.gen/sources_1/ip/ad9361_clk_gen_cmos_2t2r" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "." } ],
+        "SWVERSION": [ { "value": "2023.2.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
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+        "clk_out1": [ { "direction": "out" } ],
+        "clk_out2": [ { "direction": "out" } ],
+        "clk_out3": [ { "direction": "out" } ],
+        "clk_out4": [ { "direction": "out" } ],
+        "locked": [ { "direction": "out" } ]
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+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
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+            "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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+          },
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+            "CLK_OUT3": [ { "physical_name": "clk_out3" } ]
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+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
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+          "parameters": {
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK_OUT4": [ { "physical_name": "clk_out4" } ]
+          }
+        }
+      }
+    }
+  }
+}

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/ant_clk_gen_stg1/ant_clk_gen_stg1.xci

@@ -0,0 +1,652 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "ant_clk_gen_stg1",
+    "component_reference": "xilinx.com:ip:clk_wiz:6.0",
+    "ip_revision": "13",
+    "gen_directory": "../../../../dl814_k7_cal_coarse.gen/sources_1/ip/ant_clk_gen_stg1",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "ant_clk_gen_stg1", "resolve_type": "user", "usage": "all" } ],
+        "USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "ENABLE_CLOCK_MONITOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ENABLE_USER_CLOCK0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ENABLE_USER_CLOCK1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ENABLE_USER_CLOCK2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ENABLE_USER_CLOCK3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_PLL0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_PLL1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
+        "PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ],
+        "CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
+        "USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_PHASE_ALIGNMENT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ],
+        "PRIM_IN_FREQ": [ { "value": "250", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ],
+        "PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "user", "usage": "all" } ],
+        "IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ],
+        "RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ],
+        "USE_INCLK_SWITCHOVER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ],
+        "SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
+        "JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ],
+        "CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKIN1_JITTER_PS": [ { "value": "40.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT2_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT3_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT4_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "NUM_OUT_CLKS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ],
+        "DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ],
+        "DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ],
+        "DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ],
+        "DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ],
+        "DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ],
+        "DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ],
+        "DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ],
+        "PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ],
+        "PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ],
+        "PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ],
+        "PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "96", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "PRIM_SOURCE": [ { "value": "Differential_clock_capable_pin", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ],
+        "PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ],
+        "SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
+        "USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
+        "USE_RESET": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ],
+        "LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ],
+        "POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ],
+        "CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ],
+        "STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ],
+        "CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ],
+        "INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ],
+        "SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ],
+        "SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
+        "MMCM_DIVCLK_DIVIDE": [ { "value": "5", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
+        "MMCM_CLKFBOUT_MULT_F": [ { "value": "18.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKIN1_PERIOD": [ { "value": "4.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "user", "usage": "all" } ],
+        "MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT0_DIVIDE_F": [ { "value": "9.375", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
+        "PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
+        "PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ],
+        "PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKIN_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ],
+        "PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "RESET_TYPE": [ { "value": "ACTIVE_HIGH", "resolve_type": "user", "usage": "all" } ],
+        "USE_SAFE_CLOCK_STARTUP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_CLOCK_SEQUENCING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "DIFF_CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "DIFF_CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
+        "RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "ENABLE_CDDC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "user", "usage": "all" } ],
+        "CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ],
+        "ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_JITTER": [ { "value": "168.397", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_PHASE_ERROR": [ { "value": "161.614", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "INPUT_MODE": [ { "value": "frequency", "resolve_type": "user", "usage": "all" } ],
+        "INTERFACE_SELECTION": [ { "value": "Enable_AXI", "resolve_type": "user", "usage": "all" } ],
+        "AXI_DRP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "PHASE_DUTY_CONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_CLKOUT2_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
+        "C_USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_ENABLE_CLOCK_MONITOR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_USER_CLOCK0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_USER_CLOCK1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_USER_CLOCK2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_USER_CLOCK3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_Enable_PLL0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_Enable_PLL1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PRECISION": [ { "value": "1", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT4_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT5_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT6_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT7_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKOUT1_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKOUT2_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKOUT3_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKOUT4_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "c_component_name": [ { "value": "ant_clk_gen_stg1", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_FREQ_SYNTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_PHASE_ALIGNMENT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_MIN_POWER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_MIN_O_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_MAX_I_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_DYN_PHASE_SHIFT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_INCLK_SWITCHOVER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_DYN_RECONFIG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_SPREAD_SPECTRUM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_FAST_SIMULATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIMTYPE_SEL": [ { "value": "AUTO", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_CLK_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIM_IN_FREQ": [ { "value": "250", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "generated", "usage": "all" } ],
+        "C_SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "generated", "usage": "all" } ],
+        "C_PRIM_SOURCE": [ { "value": "Differential_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
+        "C_PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "generated", "usage": "all" } ],
+        "C_SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_RESET": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RESET_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_LOCKED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_INCLK_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKFB_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_POWER_DOWN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_STATUS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_FREEZE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_OUT_CLKS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_INCLK_SUM_ROW0": [ { "value": "Input Clock   Freq (MHz)    Input Jitter (UI)", "resolve_type": "generated", "usage": "all" } ],
+        "C_INCLK_SUM_ROW1": [ { "value": "__primary_____________250____________0.010", "resolve_type": "generated", "usage": "all" } ],
+        "C_INCLK_SUM_ROW2": [ { "value": "no_secondary_input_clock ", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW0A": [ { "value": " Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW0B": [ { "value": "  Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__96.00000______0.000______50.0______168.397____161.614", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW2": [ { "value": "no_CLK_OUT2_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW3": [ { "value": "no_CLK_OUT3_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW4": [ { "value": "no_CLK_OUT4_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW6": [ { "value": "no_CLK_OUT6_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW7": [ { "value": "no_CLK_OUT7_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "96", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_OUT_FREQ": [ { "value": "96.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_USE_SAFE_CLOCK_STARTUP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLOCK_SEQUENCING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_NOTES": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKFBOUT_MULT_F": [ { "value": "18.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKIN1_PERIOD": [ { "value": "4.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_CASCADE": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
+        "C_MMCM_CLOCK_HOLD": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
+        "C_MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_DIVCLK_DIVIDE": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "9.375", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_NOTES": [ { "value": "No notes", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_CLKFBOUT_MULT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKIN_PERIOD": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLOCK_MGR_TYPE": [ { "value": "NA", "resolve_type": "generated", "usage": "all" } ],
+        "C_OVERRIDE_MMCM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OVERRIDE_PLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "generated", "usage": "all" } ],
+        "C_SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "generated", "usage": "all" } ],
+        "C_RESET_PORT": [ { "value": "reset", "resolve_type": "generated", "usage": "all" } ],
+        "C_LOCKED_PORT": [ { "value": "locked", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "generated", "usage": "all" } ],
+        "C_POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "generated", "usage": "all" } ],
+        "C_DADDR_PORT": [ { "value": "daddr", "resolve_type": "generated", "usage": "all" } ],
+        "C_DCLK_PORT": [ { "value": "dclk", "resolve_type": "generated", "usage": "all" } ],
+        "C_DRDY_PORT": [ { "value": "drdy", "resolve_type": "generated", "usage": "all" } ],
+        "C_DWE_PORT": [ { "value": "dwe", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIN_PORT": [ { "value": "din", "resolve_type": "generated", "usage": "all" } ],
+        "C_DOUT_PORT": [ { "value": "dout", "resolve_type": "generated", "usage": "all" } ],
+        "C_DEN_PORT": [ { "value": "den", "resolve_type": "generated", "usage": "all" } ],
+        "C_PSCLK_PORT": [ { "value": "psclk", "resolve_type": "generated", "usage": "all" } ],
+        "C_PSEN_PORT": [ { "value": "psen", "resolve_type": "generated", "usage": "all" } ],
+        "C_PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "generated", "usage": "all" } ],
+        "C_PSDONE_PORT": [ { "value": "psdone", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "generated", "usage": "all" } ],
+        "C_STATUS_PORT": [ { "value": "STATUS", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "generated", "usage": "all" } ],
+        "C_INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKIN1_JITTER_PS": [ { "value": "40.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
+        "C_SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "generated", "usage": "all" } ],
+        "C_SS_MOD_PERIOD": [ { "value": "4000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_HAS_CDDC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "generated", "usage": "all" } ],
+        "C_CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUTPHY_MODE": [ { "value": "VCO", "resolve_type": "generated", "usage": "all" } ],
+        "C_ENABLE_CLKOUTPHY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INTERFACE_SELECTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_ADDR_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_POWER_REG": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT0_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT0_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFBOUT_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFBOUT_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVCLK": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_LOCK_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_LOCK_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_LOCK_3": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_FILTER_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE2_AUTO": [ { "value": "0.10666666666666667", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE3_AUTO": [ { "value": "0.10666666666666667", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE4_AUTO": [ { "value": "0.10666666666666667", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE5_AUTO": [ { "value": "0.10666666666666667", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE6_AUTO": [ { "value": "0.10666666666666667", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE7_AUTO": [ { "value": "0.10666666666666667", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLLBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLLBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLLBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLLBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLLBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV5": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV6": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV7": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT0_ACTUAL_FREQ": [ { "value": "96.00000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+        "C_M_MAX": [ { "value": "64.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_M_MIN": [ { "value": "2.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_D_MAX": [ { "value": "93.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_D_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_O_MAX": [ { "value": "128.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_O_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_VCO_MIN": [ { "value": "600.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_VCO_MAX": [ { "value": "1440.000", "resolve_type": "generated", "format": "float", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "kintex7" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7k410t" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Flow" } ],
+        "IPREVISION": [ { "value": "13" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../dl814_k7_cal_coarse.gen/sources_1/ip/ant_clk_gen_stg1" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "." } ],
+        "SWVERSION": [ { "value": "2023.2.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "clk_in1_p": [ { "direction": "in", "driver_value": "0" } ],
+        "clk_in1_n": [ { "direction": "in", "driver_value": "0" } ],
+        "clk_out1": [ { "direction": "out" } ],
+        "locked": [ { "direction": "out" } ]
+      },
+      "interfaces": {
+        "CLK_IN1_D": {
+          "vlnv": "xilinx.com:interface:diff_clock:1.0",
+          "abstraction_type": "xilinx.com:interface:diff_clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "BOARD.ASSOCIATED_PARAM": [ { "value": "CLK_IN1_BOARD_INTERFACE", "value_src": "constant", "usage": "all" } ],
+            "CAN_DEBUG": [ { "value": "false", "resolve_type": "generated", "format": "bool", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK_N": [ { "physical_name": "clk_in1_n" } ],
+            "CLK_P": [ { "physical_name": "clk_in1_p" } ]
+          }
+        },
+        "clock_CLK_OUT1": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK_OUT1": [ { "physical_name": "clk_out1" } ]
+          }
+        }
+      }
+    }
+  }
+}

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/ant_clk_gen_stg2/ant_clk_gen_stg2.xci

@@ -0,0 +1,713 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "ant_clk_gen_stg2",
+    "component_reference": "xilinx.com:ip:clk_wiz:6.0",
+    "ip_revision": "13",
+    "gen_directory": "../../../../dl814_k7_cal_coarse.gen/sources_1/ip/ant_clk_gen_stg2",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "ant_clk_gen_stg2", "resolve_type": "user", "usage": "all" } ],
+        "USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "ENABLE_CLOCK_MONITOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ENABLE_USER_CLOCK0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ENABLE_USER_CLOCK1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ENABLE_USER_CLOCK2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ENABLE_USER_CLOCK3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_PLL0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_PLL1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
+        "PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ],
+        "CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
+        "USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_PHASE_ALIGNMENT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ],
+        "PRIM_IN_FREQ": [ { "value": "96", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ],
+        "PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "user", "usage": "all" } ],
+        "IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ],
+        "RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ],
+        "USE_INCLK_SWITCHOVER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ],
+        "SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
+        "JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ],
+        "CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKIN1_JITTER_PS": [ { "value": "104.16", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT2_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT3_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT4_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "NUM_OUT_CLKS": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ],
+        "CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ],
+        "DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ],
+        "DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ],
+        "DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ],
+        "DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ],
+        "DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ],
+        "DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ],
+        "DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ],
+        "PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ],
+        "PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ],
+        "PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ],
+        "PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "96", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "48", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "19.2", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "PRIM_SOURCE": [ { "value": "Global_buffer", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+        "FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ],
+        "PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ],
+        "SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
+        "USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
+        "USE_RESET": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ],
+        "LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ],
+        "POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ],
+        "CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ],
+        "STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ],
+        "CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ],
+        "INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ],
+        "CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ],
+        "SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ],
+        "SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
+        "MMCM_DIVCLK_DIVIDE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
+        "MMCM_CLKFBOUT_MULT_F": [ { "value": "10.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKIN1_PERIOD": [ { "value": "10.417", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKIN2_PERIOD": [ { "value": "10.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "user", "usage": "all" } ],
+        "MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT0_DIVIDE_F": [ { "value": "10.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT1_DIVIDE": [ { "value": "20", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT2_DIVIDE": [ { "value": "30", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT3_DIVIDE": [ { "value": "50", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
+        "PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
+        "PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ],
+        "PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKIN_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ],
+        "PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "RESET_TYPE": [ { "value": "ACTIVE_HIGH", "resolve_type": "user", "usage": "all" } ],
+        "USE_SAFE_CLOCK_STARTUP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "USE_CLOCK_SEQUENCING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "DIFF_CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "DIFF_CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
+        "RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+        "ENABLE_CDDC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "user", "usage": "all" } ],
+        "CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ],
+        "ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_JITTER": [ { "value": "136.435", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT1_PHASE_ERROR": [ { "value": "101.715", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_JITTER": [ { "value": "158.351", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT2_PHASE_ERROR": [ { "value": "101.715", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_JITTER": [ { "value": "172.426", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT3_PHASE_ERROR": [ { "value": "101.715", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_JITTER": [ { "value": "190.665", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT4_PHASE_ERROR": [ { "value": "101.715", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT5_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT6_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "CLKOUT7_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+        "INPUT_MODE": [ { "value": "frequency", "resolve_type": "user", "usage": "all" } ],
+        "INTERFACE_SELECTION": [ { "value": "Enable_AXI", "resolve_type": "user", "usage": "all" } ],
+        "AXI_DRP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "PHASE_DUTY_CONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_CLKOUT2_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
+        "C_USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_ENABLE_CLOCK_MONITOR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_USER_CLOCK0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_USER_CLOCK1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_USER_CLOCK2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_USER_CLOCK3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_Enable_PLL0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_Enable_PLL1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PRECISION": [ { "value": "1", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT4_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT5_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT6_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT7_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKOUT1_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKOUT2_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKOUT3_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKOUT4_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "c_component_name": [ { "value": "ant_clk_gen_stg2", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_FREQ_SYNTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_PHASE_ALIGNMENT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_MIN_POWER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_MIN_O_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_MAX_I_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_DYN_PHASE_SHIFT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_INCLK_SWITCHOVER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_DYN_RECONFIG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_SPREAD_SPECTRUM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_FAST_SIMULATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIMTYPE_SEL": [ { "value": "AUTO", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_CLK_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIM_IN_FREQ": [ { "value": "96", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "generated", "usage": "all" } ],
+        "C_SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "generated", "usage": "all" } ],
+        "C_PRIM_SOURCE": [ { "value": "Global_buffer", "resolve_type": "generated", "usage": "all" } ],
+        "C_PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "generated", "usage": "all" } ],
+        "C_SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_RESET": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RESET_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_LOCKED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_INCLK_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLKFB_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_POWER_DOWN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_STATUS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_FREEZE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_OUT_CLKS": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+        "C_INCLK_SUM_ROW0": [ { "value": "Input Clock   Freq (MHz)    Input Jitter (UI)", "resolve_type": "generated", "usage": "all" } ],
+        "C_INCLK_SUM_ROW1": [ { "value": "__primary______________96____________0.010", "resolve_type": "generated", "usage": "all" } ],
+        "C_INCLK_SUM_ROW2": [ { "value": "no_secondary_input_clock ", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW0A": [ { "value": " Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW0B": [ { "value": "  Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__96.00000______0.000______50.0______136.435____101.715", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW2": [ { "value": "clk_out2__48.00000______0.000______50.0______158.351____101.715", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW3": [ { "value": "clk_out3__32.00000______0.000______50.0______172.426____101.715", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW4": [ { "value": "clk_out4__19.20000______0.000______50.0______190.665____101.715", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW6": [ { "value": "no_CLK_OUT6_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_OUTCLK_SUM_ROW7": [ { "value": "no_CLK_OUT7_output", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "96", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "48", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "32", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "19.2", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_OUT_FREQ": [ { "value": "96.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_OUT_FREQ": [ { "value": "48.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_OUT_FREQ": [ { "value": "32.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_OUT_FREQ": [ { "value": "19.20000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT1_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT2_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT3_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT4_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT5_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT6_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKOUT7_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_USE_SAFE_CLOCK_STARTUP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_CLOCK_SEQUENCING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_NOTES": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKFBOUT_MULT_F": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKIN1_PERIOD": [ { "value": "10.417", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKIN2_PERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_CASCADE": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
+        "C_MMCM_CLOCK_HOLD": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
+        "C_MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT1_DIVIDE": [ { "value": "20", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT2_DIVIDE": [ { "value": "30", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT3_DIVIDE": [ { "value": "50", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_NOTES": [ { "value": "No notes", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_CLKFBOUT_MULT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKIN_PERIOD": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLOCK_MGR_TYPE": [ { "value": "NA", "resolve_type": "generated", "usage": "all" } ],
+        "C_OVERRIDE_MMCM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_OVERRIDE_PLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "generated", "usage": "all" } ],
+        "C_SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "generated", "usage": "all" } ],
+        "C_RESET_PORT": [ { "value": "reset", "resolve_type": "generated", "usage": "all" } ],
+        "C_LOCKED_PORT": [ { "value": "locked", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "generated", "usage": "all" } ],
+        "C_POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "generated", "usage": "all" } ],
+        "C_DADDR_PORT": [ { "value": "daddr", "resolve_type": "generated", "usage": "all" } ],
+        "C_DCLK_PORT": [ { "value": "dclk", "resolve_type": "generated", "usage": "all" } ],
+        "C_DRDY_PORT": [ { "value": "drdy", "resolve_type": "generated", "usage": "all" } ],
+        "C_DWE_PORT": [ { "value": "dwe", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIN_PORT": [ { "value": "din", "resolve_type": "generated", "usage": "all" } ],
+        "C_DOUT_PORT": [ { "value": "dout", "resolve_type": "generated", "usage": "all" } ],
+        "C_DEN_PORT": [ { "value": "den", "resolve_type": "generated", "usage": "all" } ],
+        "C_PSCLK_PORT": [ { "value": "psclk", "resolve_type": "generated", "usage": "all" } ],
+        "C_PSEN_PORT": [ { "value": "psen", "resolve_type": "generated", "usage": "all" } ],
+        "C_PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "generated", "usage": "all" } ],
+        "C_PSDONE_PORT": [ { "value": "psdone", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "generated", "usage": "all" } ],
+        "C_STATUS_PORT": [ { "value": "STATUS", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "generated", "usage": "all" } ],
+        "C_INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKIN1_JITTER_PS": [ { "value": "104.16", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
+        "C_SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "generated", "usage": "all" } ],
+        "C_SS_MOD_PERIOD": [ { "value": "4000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_HAS_CDDC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "generated", "usage": "all" } ],
+        "C_CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUTPHY_MODE": [ { "value": "VCO", "resolve_type": "generated", "usage": "all" } ],
+        "C_ENABLE_CLKOUTPHY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INTERFACE_SELECTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_ADDR_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_POWER_REG": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT0_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT0_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFBOUT_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKFBOUT_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVCLK": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_LOCK_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_LOCK_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_LOCK_3": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_FILTER_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE2_AUTO": [ { "value": "2.0", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE3_AUTO": [ { "value": "3.0", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE4_AUTO": [ { "value": "5.0", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE5_AUTO": [ { "value": "0.1", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE6_AUTO": [ { "value": "0.1", "resolve_type": "generated", "usage": "all" } ],
+        "C_DIVIDE7_AUTO": [ { "value": "0.1", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLLBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLLBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLLBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLLBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_PLLBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV5": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV6": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_MMCMBUFGCEDIV7": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT0_ACTUAL_FREQ": [ { "value": "96.00000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT1_ACTUAL_FREQ": [ { "value": "48.00000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT2_ACTUAL_FREQ": [ { "value": "32.00000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT3_ACTUAL_FREQ": [ { "value": "19.20000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT4_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT5_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+        "C_CLKOUT6_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+        "C_M_MAX": [ { "value": "64.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_M_MIN": [ { "value": "2.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_D_MAX": [ { "value": "93.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_D_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_O_MAX": [ { "value": "128.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_O_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_VCO_MIN": [ { "value": "600.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+        "C_VCO_MAX": [ { "value": "1440.000", "resolve_type": "generated", "format": "float", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "kintex7" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7k410t" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Flow" } ],
+        "IPREVISION": [ { "value": "13" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../dl814_k7_cal_coarse.gen/sources_1/ip/ant_clk_gen_stg2" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "." } ],
+        "SWVERSION": [ { "value": "2023.2.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "clk_in1": [ { "direction": "in" } ],
+        "clk_out1": [ { "direction": "out" } ],
+        "clk_out2": [ { "direction": "out" } ],
+        "clk_out3": [ { "direction": "out" } ],
+        "clk_out4": [ { "direction": "out" } ],
+        "locked": [ { "direction": "out" } ]
+      },
+      "interfaces": {
+        "clock_CLK_IN1": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
+            "BOARD.ASSOCIATED_PARAM": [ { "value": "CLK_IN1_BOARD_INTERFACE", "usage": "all", "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK_IN1": [ { "physical_name": "clk_in1" } ]
+          }
+        },
+        "clock_CLK_OUT1": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK_OUT1": [ { "physical_name": "clk_out1" } ]
+          }
+        },
+        "clock_CLK_OUT2": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK_OUT2": [ { "physical_name": "clk_out2" } ]
+          }
+        },
+        "clock_CLK_OUT3": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK_OUT3": [ { "physical_name": "clk_out3" } ]
+          }
+        },
+        "clock_CLK_OUT4": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK_OUT4": [ { "physical_name": "clk_out4" } ]
+          }
+        }
+      }
+    }
+  }
+}

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/atan2_16b/atan2_16b.xci

@@ -0,0 +1,188 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "atan2_16b",
+    "component_reference": "xilinx.com:ip:cordic:6.0",
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+}

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/cmpy_12x12/cmpy_12x12.xci

@@ -0,0 +1,212 @@
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+}

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/cmpy_16x12/cmpy_16x12.xci

@@ -0,0 +1,212 @@
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+            "HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "m_axis_dout_tdata" } ],
+            "TVALID": [ { "physical_name": "m_axis_dout_tvalid" } ]
+          }
+        },
+        "aclk_intf": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "S_AXIS_CTRL:S_AXIS_B:S_AXIS_A:M_AXIS_DOUT", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "aclk" } ]
+          }
+        },
+        "aresetn_intf": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "aclken_intf": {
+          "vlnv": "xilinx.com:signal:clockenable:1.0",
+          "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
+          }
+        },
+        "S_AXIS_A": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "s_axis_a_tdata" } ],
+            "TVALID": [ { "physical_name": "s_axis_a_tvalid" } ]
+          }
+        },
+        "S_AXIS_B": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "s_axis_b_tdata" } ],
+            "TVALID": [ { "physical_name": "s_axis_b_tvalid" } ]
+          }
+        }
+      }
+    }
+  }
+}

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/fifo_AntCtrl/fifo_AntCtrl.xci

@@ -0,0 +1,479 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "fifo_AntCtrl",
+    "component_reference": "xilinx.com:ip:fifo_generator:13.2",
+    "ip_revision": "9",
+    "gen_directory": "../../../../dl814_k7_cal_coarse.gen/sources_1/ip/fifo_AntCtrl",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "fifo_AntCtrl", "resolve_type": "user", "usage": "all" } ],
+        "Fifo_Implementation": [ { "value": "Independent_Clocks_Distributed_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "synchronization_stages": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "synchronization_stages_axi": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "INTERFACE_TYPE": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
+        "Performance_Options": [ { "value": "Standard_FIFO", "resolve_type": "user", "usage": "all" } ],
+        "asymmetric_port_width": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Data_Width": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Input_Depth": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
+        "Output_Data_Width": [ { "value": "4", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Output_Depth": [ { "value": "1024", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Enable_ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Use_Embedded_Registers": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Reset_Pin": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_Reset_Synchronization": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Reset_Type": [ { "value": "Asynchronous_Reset", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Flags_Reset_Value": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
+        "Use_Dout_Reset": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Dout_Reset_Value": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "dynamic_power_saving": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Almost_Full_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Almost_Empty_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Valid_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Valid_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Underflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Underflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Write_Acknowledge_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Write_Acknowledge_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Overflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Overflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "ecc_pipeline_reg": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Use_Extra_Logic": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Write_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Write_Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Read_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Read_Data_Count_Width": [ { "value": "10", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Disable_Timing_Violations": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Read_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Write_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "usage": "all" } ],
+        "Full_Threshold_Assert_Value": [ { "value": "1021", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Negate_Value": [ { "value": "1020", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "usage": "all" } ],
+        "Empty_Threshold_Assert_Value": [ { "value": "2", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Negate_Value": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "PROTOCOL": [ { "value": "AXI4", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Clock_Type_AXI": [ { "value": "Common_Clock", "resolve_type": "user", "usage": "all" } ],
+        "HAS_ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Clock_Enable_Type": [ { "value": "Slave_Interface_Clock_Enable", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "user", "usage": "all" } ],
+        "ID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "ADDRESS_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "DATA_WIDTH": [ { "value": "64", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "AWUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "WUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "BUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "ARUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "RUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "TDATA_NUM_BYTES": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
+        "TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "TUSER_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Enable_TREADY": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Enable_TLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "HAS_TSTRB": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "TSTRB_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "HAS_TKEEP": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "TKEEP_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "wach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_wach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_wach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_wach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_wach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_wach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_wach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_wach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "wdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_wdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_wdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_wdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_wdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_wdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_wdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_wdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "wrch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_wrch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_wrch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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+}

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/fifo_accor_cdc/fifo_accor_cdc.xci

@@ -0,0 +1,480 @@
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+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "wr_clk" } ]
+          }
+        },
+        "read_clk": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "rd_clk" } ]
+          }
+        },
+        "FIFO_WRITE": {
+          "vlnv": "xilinx.com:interface:fifo_write:1.0",
+          "abstraction_type": "xilinx.com:interface:fifo_write_rtl:1.0",
+          "mode": "slave",
+          "port_maps": {
+            "FULL": [ { "physical_name": "full" } ],
+            "WR_DATA": [ { "physical_name": "din" } ],
+            "WR_EN": [ { "physical_name": "wr_en" } ]
+          }
+        },
+        "FIFO_READ": {
+          "vlnv": "xilinx.com:interface:fifo_read:1.0",
+          "abstraction_type": "xilinx.com:interface:fifo_read_rtl:1.0",
+          "mode": "slave",
+          "port_maps": {
+            "EMPTY": [ { "physical_name": "empty" } ],
+            "RD_DATA": [ { "physical_name": "dout" } ],
+            "RD_EN": [ { "physical_name": "rd_en" } ]
+          }
+        }
+      }
+    }
+  }
+}

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/fifo_weight_cdc/fifo_weight_cdc.xci

@@ -0,0 +1,480 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "fifo_weight_cdc",
+    "component_reference": "xilinx.com:ip:fifo_generator:13.2",
+    "ip_revision": "9",
+    "gen_directory": "../../../../dl814_k7_cal_coarse.gen/sources_1/ip/fifo_weight_cdc",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "fifo_weight_cdc", "resolve_type": "user", "usage": "all" } ],
+        "Fifo_Implementation": [ { "value": "Independent_Clocks_Distributed_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "synchronization_stages": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "synchronization_stages_axi": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "INTERFACE_TYPE": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
+        "Performance_Options": [ { "value": "Standard_FIFO", "resolve_type": "user", "usage": "all" } ],
+        "asymmetric_port_width": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Data_Width": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Input_Depth": [ { "value": "16", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Output_Data_Width": [ { "value": "16", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Output_Depth": [ { "value": "16", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Enable_ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Use_Embedded_Registers": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Reset_Pin": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Enable_Reset_Synchronization": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Reset_Type": [ { "value": "Asynchronous_Reset", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Flags_Reset_Value": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
+        "Use_Dout_Reset": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Dout_Reset_Value": [ { "value": "0", "resolve_type": "user", "usage": "all" } ],
+        "dynamic_power_saving": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Almost_Full_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Almost_Empty_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Valid_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Valid_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Underflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Underflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Write_Acknowledge_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Write_Acknowledge_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Overflow_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Overflow_Sense": [ { "value": "Active_High", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "ecc_pipeline_reg": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Use_Extra_Logic": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Data_Count_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Write_Data_Count": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Write_Data_Count_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Read_Data_Count": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Read_Data_Count_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Disable_Timing_Violations": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Read_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Write_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "usage": "all" } ],
+        "Full_Threshold_Assert_Value": [ { "value": "13", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Negate_Value": [ { "value": "12", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "usage": "all" } ],
+        "Empty_Threshold_Assert_Value": [ { "value": "2", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Negate_Value": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "PROTOCOL": [ { "value": "AXI4", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Clock_Type_AXI": [ { "value": "Common_Clock", "resolve_type": "user", "usage": "all" } ],
+        "HAS_ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Clock_Enable_Type": [ { "value": "Slave_Interface_Clock_Enable", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "READ_WRITE_MODE": [ { "value": "READ_WRITE", "resolve_type": "user", "usage": "all" } ],
+        "ID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "ADDRESS_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "DATA_WIDTH": [ { "value": "64", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "AWUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "WUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "BUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "ARUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "RUSER_Width": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "TDATA_NUM_BYTES": [ { "value": "1", "resolve_type": "user", "usage": "all" } ],
+        "TID_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "TDEST_WIDTH": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "TUSER_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Enable_TREADY": [ { "value": "true", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Enable_TLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "HAS_TSTRB": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "TSTRB_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "HAS_TKEEP": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "TKEEP_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "wach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_wach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_wach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_wach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_wach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_wach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_wach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_wach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "wdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_wdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_wdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_wdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_wdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_wdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_wdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_wdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_wdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "wrch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_wrch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_wrch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_wrch": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_wrch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_wrch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_wrch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_wrch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_wrch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "rach_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_rach": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_rach": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_rach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_rach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_rach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_rach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_rach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_rach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "rdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_rdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_rdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_rdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_rdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_rdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Programmable_Empty_Type_rdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Empty_Threshold_Assert_Value_rdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "axis_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Implementation_axis": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ],
+        "FIFO_Application_Type_axis": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_ECC_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Sbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Inject_Dbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Input_Depth_axis": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ],
+        "Enable_Data_Counts_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Programmable_Full_Type_axis": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Full_Threshold_Assert_Value_axis": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
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+        "C_REG_SLICE_MODE_AXIS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
+      },
+      "project_parameters": {
+        "ARCHITECTURE": [ { "value": "kintex7" } ],
+        "BASE_BOARD_PART": [ { "value": "" } ],
+        "BOARD_CONNECTIONS": [ { "value": "" } ],
+        "DEVICE": [ { "value": "xc7k410t" } ],
+        "PACKAGE": [ { "value": "ffg900" } ],
+        "PREFHDL": [ { "value": "VERILOG" } ],
+        "SILICON_REVISION": [ { "value": "" } ],
+        "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
+        "SPEEDGRADE": [ { "value": "-2" } ],
+        "STATIC_POWER": [ { "value": "" } ],
+        "TEMPERATURE_GRADE": [ { "value": "" } ]
+      },
+      "runtime_parameters": {
+        "IPCONTEXT": [ { "value": "IP_Flow" } ],
+        "IPREVISION": [ { "value": "9" } ],
+        "MANAGED": [ { "value": "TRUE" } ],
+        "OUTPUTDIR": [ { "value": "../../../../dl814_k7_cal_coarse.gen/sources_1/ip/fifo_weight_cdc" } ],
+        "SELECTEDSIMMODEL": [ { "value": "" } ],
+        "SHAREDDIR": [ { "value": "." } ],
+        "SWVERSION": [ { "value": "2023.2.1" } ],
+        "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+      }
+    },
+    "boundary": {
+      "ports": {
+        "rst": [ { "direction": "in", "driver_value": "0" } ],
+        "wr_clk": [ { "direction": "in", "driver_value": "0" } ],
+        "rd_clk": [ { "direction": "in", "driver_value": "0" } ],
+        "din": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
+        "wr_en": [ { "direction": "in", "driver_value": "0" } ],
+        "rd_en": [ { "direction": "in", "driver_value": "0" } ],
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+        "full": [ { "direction": "out", "driver_value": "0x0" } ],
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+        "rd_data_count": [ { "direction": "out", "size_left": "3", "size_right": "0", "driver_value": "0" } ]
+      },
+      "interfaces": {
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+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
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+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
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+          }
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+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "rd_clk" } ]
+          }
+        },
+        "FIFO_WRITE": {
+          "vlnv": "xilinx.com:interface:fifo_write:1.0",
+          "abstraction_type": "xilinx.com:interface:fifo_write_rtl:1.0",
+          "mode": "slave",
+          "port_maps": {
+            "FULL": [ { "physical_name": "full" } ],
+            "WR_DATA": [ { "physical_name": "din" } ],
+            "WR_EN": [ { "physical_name": "wr_en" } ]
+          }
+        },
+        "FIFO_READ": {
+          "vlnv": "xilinx.com:interface:fifo_read:1.0",
+          "abstraction_type": "xilinx.com:interface:fifo_read_rtl:1.0",
+          "mode": "slave",
+          "port_maps": {
+            "EMPTY": [ { "physical_name": "empty" } ],
+            "RD_DATA": [ { "physical_name": "dout" } ],
+            "RD_EN": [ { "physical_name": "rd_en" } ]
+          }
+        }
+      }
+    }
+  }
+}

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/ila_rx_pre_ant/ila_rx_pre_ant.xci

@@ -1,11 +1,10 @@
 {
   "schema": "xilinx.com:schema:json_instance:1.0",
   "ip_inst": {
-    "xci_name": "system_bd_ila_0_0",
+    "xci_name": "ila_rx_pre_ant",
-    "cell_name": "ila_spi",
     "component_reference": "xilinx.com:ip:ila:6.2",
     "ip_revision": "14",
-    "gen_directory": "../../../../../../duifei_cmos_1t2r.gen/sources_1/bd/system_bd/ip/system_bd_ila_0_0",
+    "gen_directory": "../../../../dl814_k7_cal_coarse.gen/sources_1/ip/ila_rx_pre_ant",
     "parameters": {
       "component_parameters": {
         "C_PROBE1023_TYPE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -2044,21 +2043,21 @@
         "C_PROBE13_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "C_PROBE12_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "C_PROBE11_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE10_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE10_WIDTH": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "C_PROBE9_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE8_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE8_WIDTH": [ { "value": "5", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "C_PROBE7_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE6_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE6_WIDTH": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE5_WIDTH": [ { "value": "1", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE5_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE4_WIDTH": [ { "value": "1", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE4_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE3_WIDTH": [ { "value": "1", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE3_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE2_WIDTH": [ { "value": "1", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE2_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE1_WIDTH": [ { "value": "1", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE1_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE0_WIDTH": [ { "value": "1", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE0_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_DATA_DEPTH": [ { "value": "16384", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_DATA_DEPTH": [ { "value": "1024", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_NUM_OF_PROBES": [ { "value": "6", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_NUM_OF_PROBES": [ { "value": "12", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "C_XLNX_HW_PROBE_INFO": [ { "value": "DEFAULT", "resolve_type": "user", "usage": "all" } ],
-        "Component_Name": [ { "value": "system_bd_ila_0_0", "resolve_type": "user", "usage": "all" } ],
+        "Component_Name": [ { "value": "ila_rx_pre_ant", "resolve_type": "user", "usage": "all" } ],
         "C_PROBE70_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "C_TRIGOUT_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "C_EN_STRG_QUAL": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -2068,7 +2067,7 @@
         "C_EN_DDR_ILA": [ { "value": "FALSE", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "C_DDR_CLK_GEN": [ { "value": "FALSE", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "C_CLK_FREQ": [ { "value": "200", "resolve_type": "user", "format": "float", "usage": "all" } ],
-        "C_ILA_CLK_FREQ": [ { "value": "100000000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_ILA_CLK_FREQ": [ { "value": "2000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "C_CLK_PERIOD": [ { "value": "5", "resolve_type": "user", "format": "float", "usage": "all" } ],
         "C_CLKFBOUT_MULT_F": [ { "value": "10", "resolve_type": "user", "format": "float", "usage": "all" } ],
         "C_DIVCLK_DIVIDE": [ { "value": "3", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -3054,70 +3053,70 @@
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         "C_PROBE45_MU_CNT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "C_PROBE44_MU_CNT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE43_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE43_MU_CNT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE42_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE42_MU_CNT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE41_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE41_MU_CNT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE40_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE40_MU_CNT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE39_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE39_MU_CNT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE38_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE38_MU_CNT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE37_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE37_MU_CNT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE36_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE36_MU_CNT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE35_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE35_MU_CNT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE34_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
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-        "C_PROBE33_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
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-        "C_PROBE32_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
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-        "C_PROBE30_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE30_MU_CNT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE29_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE29_MU_CNT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE28_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE28_MU_CNT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE27_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE27_MU_CNT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE26_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE26_MU_CNT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE25_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE25_MU_CNT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE24_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE24_MU_CNT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE23_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE23_MU_CNT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE22_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE22_MU_CNT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE21_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE21_MU_CNT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE20_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE20_MU_CNT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE19_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE19_MU_CNT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE18_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE18_MU_CNT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE17_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE17_MU_CNT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE16_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE16_MU_CNT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE15_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE15_MU_CNT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE14_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE14_MU_CNT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE13_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE13_MU_CNT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE12_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE12_MU_CNT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "C_PROBE11_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "C_PROBE10_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "C_PROBE9_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "C_PROBE8_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "C_PROBE7_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "C_PROBE6_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE5_MU_CNT": [ { "value": "6", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE5_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE4_MU_CNT": [ { "value": "6", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE4_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE3_MU_CNT": [ { "value": "6", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE3_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE2_MU_CNT": [ { "value": "6", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE2_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE1_MU_CNT": [ { "value": "6", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE1_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_PROBE0_MU_CNT": [ { "value": "6", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_PROBE0_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "C_TRIGIN_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "EN_BRAM_DRC": [ { "value": "TRUE", "resolve_type": "user", "format": "bool", "usage": "all" } ],
         "ALL_PROBE_SAME_MU": [ { "value": "TRUE", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "ALL_PROBE_SAME_MU_CNT": [ { "value": "6", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "ALL_PROBE_SAME_MU_CNT": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "C_NUM_MONITOR_SLOTS": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
         "C_SLOT_0_AXI_ARUSER_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "C_SLOT_0_AXI_RUSER_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "C_SLOT_0_AXI_AWUSER_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "C_SLOT_0_AXI_WUSER_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "C_SLOT_0_AXI_BUSER_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_SLOT_0_AXI_ID_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_SLOT_0_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_SLOT_0_AXI_DATA_WIDTH": [ { "value": "32", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_SLOT_0_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_SLOT_0_AXI_ADDR_WIDTH": [ { "value": "32", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_SLOT_0_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "C_SLOT_0_AXI_PROTOCOL": [ { "value": "AXI4", "resolve_type": "user", "usage": "all" } ],
-        "C_SLOT_0_AXIS_TDATA_WIDTH": [ { "value": "32", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_SLOT_0_AXIS_TDATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_SLOT_0_AXIS_TID_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_SLOT_0_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_SLOT_0_AXIS_TUSER_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_SLOT_0_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
-        "C_SLOT_0_AXIS_TDEST_WIDTH": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "C_SLOT_0_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
         "C_ENABLE_ILA_AXI_MON": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
-        "C_MONITOR_TYPE": [ { "value": "Native", "value_src": "user", "resolve_type": "user", "usage": "all" } ]
+        "C_MONITOR_TYPE": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ]
       },
       "model_parameters": {
         "C_XLNX_HW_PROBE_INFO": [ { "value": "DEFAULT", "resolve_type": "generated", "usage": "all" } ],
@@ -3125,7 +3124,7 @@
         "C_XLNX_HW_PROBE_INFO_DUMMY2": [ { "value": "DEFAULT", "resolve_type": "generated", "usage": "all" } ],
         "C_XLNX_HW_PROBE_INFO_DUMMY3": [ { "value": "DEFAULT", "resolve_type": "generated", "usage": "all" } ],
         "C_XLNX_HW_PROBE_INFO_DUMMY4": [ { "value": "DEFAULT", "resolve_type": "generated", "usage": "all" } ],
-        "C_XDEVICEFAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
+        "C_XDEVICEFAMILY": [ { "value": "kintex7", "resolve_type": "generated", "usage": "all" } ],
         "C_CORE_TYPE": [ { "value": "1", "format": "long", "usage": "all" } ],
         "C_CORE_INFO1": [ { "value": "0", "format": "long", "usage": "all" } ],
         "C_CORE_INFO2": [ { "value": "0", "format": "long", "usage": "all" } ],
@@ -3135,8 +3134,8 @@
         "C_SLOT_0_AXI_PROTOCOL": [ { "value": "AXI4", "resolve_type": "generated", "usage": "all" } ],
         "C_NUM_MONITOR_SLOTS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_ENABLE_ILA_AXI_MON": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_NUM_OF_PROBES": [ { "value": "6", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_NUM_OF_PROBES": [ { "value": "12", "resolve_type": "generated", "format": "long", "usage": "all" } ],
-        "C_DATA_DEPTH": [ { "value": "16384", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DATA_DEPTH": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_MAJOR_VERSION": [ { "value": "2023", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_MINOR_VERSION": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_BUILD_REVISION": [ { "value": "0", "format": "long", "usage": "all" } ],
@@ -3152,7 +3151,7 @@
         "C_TRIGIN_EN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
         "C_SLOT_0_AXIS_TUSER_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
         "C_SLOT_0_AXIS_TDEST_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_SLOT_0_AXIS_TID_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_SLOT_0_AXIS_TID_WIDTH": [ { "value": "5", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
         "C_SLOT_0_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
         "C_SLOT_0_AXI_ARUSER_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
         "C_SLOT_0_AXI_RUSER_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
@@ -3165,11 +3164,11 @@
         "C_PROBE3_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
         "C_PROBE4_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
         "C_PROBE5_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE6_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE6_WIDTH": [ { "value": "32", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
         "C_PROBE7_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE8_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE8_WIDTH": [ { "value": "5", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
         "C_PROBE9_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE10_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE10_WIDTH": [ { "value": "16", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
         "C_PROBE11_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
         "C_PROBE12_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
         "C_PROBE13_WIDTH": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
@@ -5207,50 +5206,50 @@
         "C_PROBE1021_TYPE": [ { "value": "0", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
         "C_PROBE1022_TYPE": [ { "value": "0", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
         "C_PROBE1023_TYPE": [ { "value": "0", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE0_MU_CNT": [ { "value": "6", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE0_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE1_MU_CNT": [ { "value": "6", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE1_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE2_MU_CNT": [ { "value": "6", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE2_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE3_MU_CNT": [ { "value": "6", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE3_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE4_MU_CNT": [ { "value": "6", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE4_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE5_MU_CNT": [ { "value": "6", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE5_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
         "C_PROBE6_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
         "C_PROBE7_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
         "C_PROBE8_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
         "C_PROBE9_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
         "C_PROBE10_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
         "C_PROBE11_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE12_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE12_MU_CNT": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE13_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE13_MU_CNT": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE14_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE14_MU_CNT": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE15_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE15_MU_CNT": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE16_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE16_MU_CNT": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE17_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE17_MU_CNT": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE18_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE18_MU_CNT": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE19_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE19_MU_CNT": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE20_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE20_MU_CNT": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE21_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE21_MU_CNT": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE22_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE22_MU_CNT": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE23_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE23_MU_CNT": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE24_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE24_MU_CNT": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE25_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE25_MU_CNT": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE26_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE26_MU_CNT": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE27_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE27_MU_CNT": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE28_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE28_MU_CNT": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE29_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE29_MU_CNT": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE30_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE30_MU_CNT": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE31_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE31_MU_CNT": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE32_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE32_MU_CNT": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE33_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE33_MU_CNT": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE34_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE34_MU_CNT": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE35_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE35_MU_CNT": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE36_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE36_MU_CNT": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE37_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE37_MU_CNT": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE38_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE38_MU_CNT": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE39_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE39_MU_CNT": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE40_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE40_MU_CNT": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE41_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE41_MU_CNT": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE42_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE42_MU_CNT": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
-        "C_PROBE43_MU_CNT": [ { "value": "2", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
+        "C_PROBE43_MU_CNT": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
         "C_PROBE44_MU_CNT": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
         "C_PROBE45_MU_CNT": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
         "C_PROBE46_MU_CNT": [ { "value": "1", "resolve_type": "dependent", "format": "long", "usage": "all" } ],
@@ -6246,10 +6245,10 @@
         "C_CLKOUT0_DIVIDE_F": [ { "value": "10", "resolve_type": "generated", "format": "float", "usage": "all" } ]
       },
       "project_parameters": {
-        "ARCHITECTURE": [ { "value": "zynq" } ],
+        "ARCHITECTURE": [ { "value": "kintex7" } ],
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
-        "DEVICE": [ { "value": "xc7z100" } ],
+        "DEVICE": [ { "value": "xc7k410t" } ],
         "PACKAGE": [ { "value": "ffg900" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],
@@ -6259,12 +6258,12 @@
         "TEMPERATURE_GRADE": [ { "value": "" } ]
       },
       "runtime_parameters": {
-        "IPCONTEXT": [ { "value": "IP_Integrator" } ],
+        "IPCONTEXT": [ { "value": "IP_Flow" } ],
         "IPREVISION": [ { "value": "14" } ],
         "MANAGED": [ { "value": "TRUE" } ],
-        "OUTPUTDIR": [ { "value": "../../../../../../duifei_cmos_1t2r.gen/sources_1/bd/system_bd/ip/system_bd_ila_0_0" } ],
+        "OUTPUTDIR": [ { "value": "../../../../dl814_k7_cal_coarse.gen/sources_1/ip/ila_rx_pre_ant" } ],
         "SELECTEDSIMMODEL": [ { "value": "" } ],
-        "SHAREDDIR": [ { "value": "../../ipshared" } ],
+        "SHAREDDIR": [ { "value": "." } ],
         "SWVERSION": [ { "value": "2023.2.1" } ],
         "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
       }
@@ -6277,7 +6276,13 @@
         "probe2": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
         "probe3": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
         "probe4": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
-        "probe5": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ]
+        "probe5": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
+        "probe6": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
+        "probe7": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
+        "probe8": [ { "direction": "in", "size_left": "4", "size_right": "0", "driver_value": "0" } ],
+        "probe9": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ],
+        "probe10": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
+        "probe11": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ]
       },
       "interfaces": {
         "signal_clock": {
@@ -6285,13 +6290,13 @@
           "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
           "mode": "slave",
           "parameters": {
-            "ASSOCIATED_BUSIF": [ { "value": "SLOT_0_AXI:SLOT_0_AXIS", "value_src": "constant", "value_permission": "bd", "usage": "all" } ],
+            "ASSOCIATED_BUSIF": [ { "value": "SLOT_0_AXI:SLOT_0_AXIS", "value_src": "constant", "usage": "all" } ],
-            "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
-            "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
-            "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
-            "CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
-            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
-            "ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
             "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
           },
           "port_maps": {

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/ram_hop_data/ram_hop_data.xci

@@ -0,0 +1,256 @@
+{
+  "schema": "xilinx.com:schema:json_instance:1.0",
+  "ip_inst": {
+    "xci_name": "ram_hop_data",
+    "component_reference": "xilinx.com:ip:blk_mem_gen:8.4",
+    "ip_revision": "7",
+    "gen_directory": "../../../../dl814_k7_cal_coarse.gen/sources_1/ip/ram_hop_data",
+    "parameters": {
+      "component_parameters": {
+        "Component_Name": [ { "value": "ram_hop_data", "resolve_type": "user", "usage": "all" } ],
+        "Interface_Type": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ],
+        "AXI_Type": [ { "value": "AXI4_Full", "resolve_type": "user", "usage": "all" } ],
+        "AXI_Slave_Type": [ { "value": "Memory_Slave", "resolve_type": "user", "usage": "all" } ],
+        "Use_AXI_ID": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "Memory_Type": [ { "value": "Single_Port_RAM", "resolve_type": "user", "usage": "all" } ],
+        "PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "usage": "all" } ],
+        "Enable_32bit_Address": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "ecctype": [ { "value": "No_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "EN_SLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "EN_DEEPSLEEP_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "EN_SHUTDOWN_PIN": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "EN_ECC_PIPE": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "RD_ADDR_CHNG_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "RD_ADDR_CHNG_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Use_Error_Injection_Pins": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Error_Injection_Type": [ { "value": "Single_Bit_Error_Injection", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Use_Byte_Write_Enable": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Byte_Size": [ { "value": "9", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Algorithm": [ { "value": "Minimum_Area", "resolve_type": "user", "usage": "all" } ],
+        "Primitive": [ { "value": "8kx2", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Assume_Synchronous_Clk": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Write_Width_A": [ { "value": "96", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Write_Depth_A": [ { "value": "9728", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Read_Width_A": [ { "value": "96", "resolve_type": "user", "usage": "all" } ],
+        "Operating_Mode_A": [ { "value": "READ_FIRST", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Enable_A": [ { "value": "Always_Enabled", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+        "Write_Width_B": [ { "value": "96", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Read_Width_B": [ { "value": "96", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Operating_Mode_B": [ { "value": "WRITE_FIRST", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Enable_B": [ { "value": "Always_Enabled", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Register_PortA_Output_of_Memory_Primitives": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Register_PortA_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Use_REGCEA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Register_PortB_Output_of_Memory_Primitives": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Register_PortB_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Use_REGCEB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "register_porta_input_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "register_portb_output_of_softecc": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Pipeline_Stages": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Load_Init_File": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Coe_File": [ { "value": "no_coe_file_loaded", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Fill_Remaining_Memory_Locations": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Remaining_Memory_Locations": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Use_RSTA_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Reset_Memory_Latch_A": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Reset_Priority_A": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Output_Reset_Value_A": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Use_RSTB_Pin": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Reset_Memory_Latch_B": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "Reset_Priority_B": [ { "value": "CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Output_Reset_Value_B": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Reset_Type": [ { "value": "SYNC", "resolve_type": "user", "enabled": false, "usage": "all" } ],
+        "Additional_Inputs_for_Power_Estimation": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Port_A_Clock": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_A_Write_Rate": [ { "value": "50", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_B_Clock": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_B_Write_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_A_Enable_Rate": [ { "value": "100", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Port_B_Enable_Rate": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
+        "Collision_Warnings": [ { "value": "ALL", "resolve_type": "user", "usage": "all" } ],
+        "Disable_Collision_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "Disable_Out_of_Range_Warnings": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+        "use_bram_block": [ { "value": "Stand_Alone", "resolve_type": "user", "usage": "all" } ],
+        "MEM_FILE": [ { "value": "no_mem_loaded", "resolve_type": "user", "usage": "all" } ],
+        "CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "user", "usage": "all" } ],
+        "EN_SAFETY_CKT": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
+        "READ_LATENCY_A": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
+        "READ_LATENCY_B": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ]
+      },
+      "model_parameters": {
+        "C_FAMILY": [ { "value": "kintex7", "resolve_type": "generated", "usage": "all" } ],
+        "C_XDEVICEFAMILY": [ { "value": "kintex7", "resolve_type": "generated", "usage": "all" } ],
+        "C_ELABORATION_DIR": [ { "value": "./", "resolve_type": "generated", "usage": "all" } ],
+        "C_INTERFACE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_SLAVE_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_USE_BRAM_BLOCK": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ENABLE_32BIT_ADDRESS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_CTRL_ECC_ALGO": [ { "value": "NONE", "resolve_type": "generated", "usage": "all" } ],
+        "C_HAS_AXI_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_AXI_ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_MEM_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_BYTE_SIZE": [ { "value": "9", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_ALGORITHM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_PRIM_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_LOAD_INIT_FILE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INIT_FILE_NAME": [ { "value": "no_coe_file_loaded", "resolve_type": "generated", "usage": "all" } ],
+        "C_INIT_FILE": [ { "value": "ram_hop_data.mem", "resolve_type": "generated", "usage": "all" } ],
+        "C_USE_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_DEFAULT_DATA": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
+        "C_HAS_RSTA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_RST_PRIORITY_A": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ],
+        "C_RSTRAM_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+        "C_INITA_VAL": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
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+}

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/rom_hop_data/rom_hop_data.xci

@@ -0,0 +1,252 @@
+{
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+        "Register_PortB_Output_of_Memory_Core": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
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+        "use_bram_block": [ { "value": "Stand_Alone", "resolve_type": "user", "usage": "all" } ],
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vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/ip/rotate_16b/rotate_16b.xci

@@ -0,0 +1,214 @@
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+      },
+      "interfaces": {
+        "S_AXIS_CARTESIAN": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "s_axis_cartesian_tdata" } ],
+            "TVALID": [ { "physical_name": "s_axis_cartesian_tvalid" } ]
+          }
+        },
+        "aclk_intf": {
+          "vlnv": "xilinx.com:signal:clock:1.0",
+          "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "ASSOCIATED_BUSIF": [ { "value": "M_AXIS_DOUT:S_AXIS_PHASE:S_AXIS_CARTESIAN", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
+            "ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ],
+            "FREQ_HZ": [ { "value": "1000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
+            "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "CLK": [ { "physical_name": "aclk" } ]
+          }
+        },
+        "aresetn_intf": {
+          "vlnv": "xilinx.com:signal:reset:1.0",
+          "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          }
+        },
+        "aclken_intf": {
+          "vlnv": "xilinx.com:signal:clockenable:1.0",
+          "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
+          }
+        },
+        "S_AXIS_PHASE": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "slave",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "2", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "s_axis_phase_tdata" } ],
+            "TVALID": [ { "physical_name": "s_axis_phase_tvalid" } ]
+          }
+        },
+        "M_AXIS_DOUT": {
+          "vlnv": "xilinx.com:interface:axis:1.0",
+          "abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
+          "mode": "master",
+          "parameters": {
+            "TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+            "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+            "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+          },
+          "port_maps": {
+            "TDATA": [ { "physical_name": "m_axis_dout_tdata" } ],
+            "TVALID": [ { "physical_name": "m_axis_dout_tvalid" } ]
+          }
+        }
+      }
+    }
+  }
+}

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/ADF4351_2.v

@@ -0,0 +1,188 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    11:51:06 06/08/2020 
+// Design Name: 
+// Module Name:    test_784TR_top 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+// ??????9?byte? ?1-8?????????????????8???????????????????3?byte???5?don't care??
+// ?9byte??4bit??spi??4bit??????
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+/*************?????????*******************/
+module adf4351_2(
+input                       i_sysclk              ,
+input                       i_arstn               ,
+output                      o_cfgover             ,
+output                      o_ADF4351_SCK         ,
+output                      o_ADF4351_DATA        ,
+output                      o_ADF4351_LE          ,
+output                      o_ADF4351_CE          ,
+output                      o_ADF4351_mutel       ,
+input                       i_ADF4351_locked      
+    );
+
+
+localparam      DATA_WIDTH = 32;
+localparam      DATA_LENTH = 6;
+localparam      SYS_CLOCK  = 10;
+localparam      LOCK_PIRED = SYS_CLOCK * 100000;
+localparam      rst_time   = 16'h7fff;//16'h7fff
+reg[7:0]        cnt_word   = 8'd0;
+reg[5:0]        cnt_bits   = 6'd0;  
+
+reg  [DATA_WIDTH-1:0] cfgdata = 0;
+wire [DATA_WIDTH-1:0] regdata;
+reg           cfgover     = 1'b0 ;
+reg           pll_locked  = 1'b0 ;
+reg           load_en     = 1'b0 ;
+reg  [31:0]   cnt_lock    = 32'b0;
+(* KEEP = "TRUE" *)reg[3:0]    cfgstate = 4'b0000;
+wire        spiIdle;
+  
+reg         spi_sdi        = 1'b0,spi_csb = 1'b1            ;
+assign      o_cfgover      = cfgover                        ;
+assign      o_ADF4351_LE   = load_en                        ;
+assign      o_ADF4351_mutel= 1'b1                           ;
+assign      o_ADF4351_SCK  = o_ADF4351_CE ? 1'b0 : i_sysclk ;
+assign      o_ADF4351_CE   = spi_csb                        ; 
+assign      o_ADF4351_DATA = spi_sdi                        ;
+reg         [DATA_WIDTH-1:0] CFGREG0                        ;
+assign      regdata        = CFGREG0                        ;
+reg         cfg_start                                       ;
+reg         [15:0] counter0                                 ;
+
+always@ (posedge i_sysclk)
+if(~i_arstn)
+   CFGREG0 <= 32'b0;
+else begin
+//RFout = Fpfd*(INT + (Frac/Mod))  Fpfd = Refin*[(1+D)/(R*(1+T))]
+    case (cnt_word)   
+       8'h00:	CFGREG0 <= {32'h580005}; //reg 5
+       8'h01:	CFGREG0 <= {32'h85003C}; //reg 4
+       8'h02:	CFGREG0 <= {32'h4B3}; 	//reg 3 
+       8'h03:	CFGREG0 <= {32'h28F42}; //reg 2   {5'b0,T,R,D,12'h,reg2}  R    = 1  D   = 1  T = 1 
+	   8'h04:	CFGREG0 <= {32'h8008011}; //reg 1   {3'd0,phase adjust,prescaler,phase value,Frac,reg1}mod  = 25
+	   8'h05:	CFGREG0 <= {32'hC80000}; //reg 0  {1'b0,int,frac,reg0} int  = 52 frac= 8
+	   default :   CFGREG0 <= 32'b0;
+    endcase
+end
+
+
+
+
+
+always@(negedge i_sysclk)begin
+   if(~i_arstn)begin
+       cfgdata  <= 0;
+       cnt_word <= 8'd0;
+       cnt_bits <= 6'd0;
+       cfgover  <= 1'b0;
+       cfgstate <= 4'd0;
+       spi_csb <= 1'b1;
+       load_en <= 1'b1;
+       spi_sdi <= 1'b0;
+   end
+   else begin
+       case(cfgstate)
+       4'd0:begin
+          if(cfg_start)begin
+             cfgstate <= 4'd1;
+          end
+          else begin
+                spi_csb  <= 1'b1;
+                load_en  <= 1'b0;
+                spi_sdi  <= 1'b0;
+                cfgover  <= 1'b0; 
+                cfgstate <= 4'd0;		   
+          end  
+       end
+       4'd1:begin
+          cfgdata  <= regdata;
+          cnt_lock <= 32'd0;
+          cnt_bits <= 6'd0;
+          cfgstate <= cfgstate + 1'b1;
+       end
+       4'd2:begin
+          spi_csb <= 1'b0;
+          load_en <= 1'b0;
+          spi_sdi <= cfgdata[DATA_WIDTH-1];
+          cfgdata <= cfgdata << 1'b1;
+          cnt_bits <= cnt_bits + 1'b1;
+          if(cnt_bits == DATA_WIDTH-1)begin
+              cfgstate <= cfgstate + 1'b1;
+              cnt_word <= cnt_word + 1'b1;
+          end
+       end
+       4'd3:begin
+          spi_csb <= 1'b1;
+          load_en <= 1'b1;
+          spi_sdi <= 1'b0;
+          if(cnt_word == DATA_LENTH)
+              cfgstate <= cfgstate + 1'b1;
+          else
+              cfgstate <= 4'd0;
+       end
+       4'd4:begin
+          cfgstate <= 4'd5;
+          spi_csb  <= 1'b1;
+          load_en  <= 1'b0;
+		    spi_sdi  <= 1'b0;
+       end
+	   4'd5:begin//ftw cfg
+	      if(cnt_lock > LOCK_PIRED)
+			begin
+				pll_locked <=  i_ADF4351_locked;
+				cnt_lock   <=  cnt_lock;
+				if( (pll_locked == 1'b0) && (cnt_lock > LOCK_PIRED))
+				begin
+					cfgstate <= 4'd1;
+					cnt_word <= 8'd0;
+				end
+				else
+				begin
+					cfgstate <= 4'd5;
+					spi_csb  <= 1'b1;
+               spi_sdi  <= 1'b0;
+               cfgover  <= 1'b1;
+				end
+			end
+			else
+			begin
+				cnt_lock   <= cnt_lock + 1'b1;
+			end
+	   end
+       default:cfgstate <= 4'd0;
+       endcase
+   end
+end
+ 
+
+always@(negedge i_sysclk)begin
+   if(~i_arstn)begin
+      counter0 <= 16'd0;
+	   cfg_start <= 1'b0;
+   end
+   else begin
+      if(counter0 == rst_time)begin//16'h7fff
+	     counter0  <= counter0;
+		 cfg_start <= 1'b1;
+	  end
+	  else begin
+	     counter0 <= counter0 + 1'b1;
+		 cfg_start <= 1'b0;
+      end
+   end
+end
+
+endmodule

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/FRAC1.v

@@ -0,0 +1,441 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    14:37:16 01/15/2022 
+// Design Name: 
+// Module Name:    FRAC1 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module FRAC1(
+input   		   clka,
+input  [15:0] 	   addra,
+output reg[24:0]   douta
+    );
+
+
+reg[11:0]	addr=0;
+
+always@(posedge clka)begin
+	addr<= (addra+375) % 400 ;	
+end	
+
+always@(posedge clka)begin
+	case(addr)
+0	:	douta	<=	0         ;
+1	:	douta	<=	83886     ;
+2	:	douta	<=	167772    ;
+3	:	douta	<=	251658    ;
+4	:	douta	<=	335544    ;
+5	:	douta	<=	419430    ;
+6	:	douta	<=	503316    ;
+7	:	douta	<=	587202    ;
+8	:	douta	<=	671088    ;
+9	:	douta	<=	754974    ;
+10	:	douta	<=	838860    ;
+11	:	douta	<=	922746    ;
+12	:	douta	<=	1006632   ;
+13	:	douta	<=	1090519   ;
+14	:	douta	<=	1174405   ;
+15	:	douta	<=	1258291   ;
+16	:	douta	<=	1342177   ;
+17	:	douta	<=	1426063   ;
+18	:	douta	<=	1509949   ;
+19	:	douta	<=	1593835   ;
+20	:	douta	<=	1677721   ;
+21	:	douta	<=	1761607   ;
+22	:	douta	<=	1845493   ;
+23	:	douta	<=	1929379   ;
+24	:	douta	<=	2013265   ;
+25	:	douta	<=	2097152   ;
+26	:	douta	<=	2181038   ;
+27	:	douta	<=	2264924   ;
+28	:	douta	<=	2348810   ;
+29	:	douta	<=	2432696   ;
+30	:	douta	<=	2516582   ;
+31	:	douta	<=	2600468   ;
+32	:	douta	<=	2684354   ;
+33	:	douta	<=	2768240   ;
+34	:	douta	<=	2852126   ;
+35	:	douta	<=	2936012   ;
+36	:	douta	<=	3019898   ;
+37	:	douta	<=	3103784   ;
+38	:	douta	<=	3187671   ;
+39	:	douta	<=	3271557   ;
+40	:	douta	<=	3355443   ;
+41	:	douta	<=	3439329   ;
+42	:	douta	<=	3523215   ;
+43	:	douta	<=	3607101   ;
+44	:	douta	<=	3690987   ;
+45	:	douta	<=	3774873   ;
+46	:	douta	<=	3858759   ;
+47	:	douta	<=	3942645   ;
+48	:	douta	<=	4026531   ;
+49	:	douta	<=	4110417   ;
+50	:	douta	<=	4194304   ;
+51	:	douta	<=	4278190   ;
+52	:	douta	<=	4362076   ;
+53	:	douta	<=	4445962   ;
+54	:	douta	<=	4529848   ;
+55	:	douta	<=	4613734   ;
+56	:	douta	<=	4697620   ;
+57	:	douta	<=	4781506   ;
+58	:	douta	<=	4865392   ;
+59	:	douta	<=	4949278   ;
+60	:	douta	<=	5033164   ;
+61	:	douta	<=	5117050   ;
+62	:	douta	<=	5200936   ;
+63	:	douta	<=	5284823   ;
+64	:	douta	<=	5368709   ;
+65	:	douta	<=	5452595   ;
+66	:	douta	<=	5536481   ;
+67	:	douta	<=	5620367   ;
+68	:	douta	<=	5704253   ;
+69	:	douta	<=	5788139   ;
+70	:	douta	<=	5872025   ;
+71	:	douta	<=	5955911   ;
+72	:	douta	<=	6039797   ;
+73	:	douta	<=	6123683   ;
+74	:	douta	<=	6207569   ;
+75	:	douta	<=	6291456   ;
+76	:	douta	<=	6375342   ;
+77	:	douta	<=	6459228   ;
+78	:	douta	<=	6543114   ;
+79	:	douta	<=	6627000   ;
+80	:	douta	<=	6710886   ;
+81	:	douta	<=	6794772   ;
+82	:	douta	<=	6878658   ;
+83	:	douta	<=	6962544   ;
+84	:	douta	<=	7046430   ;
+85	:	douta	<=	7130316   ;
+86	:	douta	<=	7214202   ;
+87	:	douta	<=	7298088   ;
+88	:	douta	<=	7381975   ;
+89	:	douta	<=	7465861   ;
+90	:	douta	<=	7549747   ;
+91	:	douta	<=	7633633   ;
+92	:	douta	<=	7717519   ;
+93	:	douta	<=	7801405   ;
+94	:	douta	<=	7885291   ;
+95	:	douta	<=	7969177   ;
+96	:	douta	<=	8053063   ;
+97	:	douta	<=	8136949   ;
+98	:	douta	<=	8220835   ;
+99	:	douta	<=	8304721   ;
+100	:	douta	<=	8388608   ;
+101	:	douta	<=	8472494   ;
+102	:	douta	<=	8556380   ;
+103	:	douta	<=	8640266   ;
+104	:	douta	<=	8724152   ;
+105	:	douta	<=	8808038   ;
+106	:	douta	<=	8891924   ;
+107	:	douta	<=	8975810   ;
+108	:	douta	<=	9059696   ;
+109	:	douta	<=	9143582   ;
+110	:	douta	<=	9227468   ;
+111	:	douta	<=	9311354   ;
+112	:	douta	<=	9395240   ;
+113	:	douta	<=	9479127   ;
+114	:	douta	<=	9563013   ;
+115	:	douta	<=	9646899   ;
+116	:	douta	<=	9730785   ;
+117	:	douta	<=	9814671   ;
+118	:	douta	<=	9898557   ;
+119	:	douta	<=	9982443   ;
+120	:	douta	<=	10066329  ;
+121	:	douta	<=	10150215  ;
+122	:	douta	<=	10234101  ;
+123	:	douta	<=	10317987  ;
+124	:	douta	<=	10401873  ;
+125	:	douta	<=	10485760  ;
+126	:	douta	<=	10569646  ;
+127	:	douta	<=	10653532  ;
+128	:	douta	<=	10737418  ;
+129	:	douta	<=	10821304  ;
+130	:	douta	<=	10905190  ;
+131	:	douta	<=	10989076  ;
+132	:	douta	<=	11072962  ;
+133	:	douta	<=	11156848  ;
+134	:	douta	<=	11240734  ;
+135	:	douta	<=	11324620  ;
+136	:	douta	<=	11408506  ;
+137	:	douta	<=	11492392  ;
+138	:	douta	<=	11576279  ;
+139	:	douta	<=	11660165  ;
+140	:	douta	<=	11744051  ;
+141	:	douta	<=	11827937  ;
+142	:	douta	<=	11911823  ;
+143	:	douta	<=	11995709  ;
+144	:	douta	<=	12079595  ;
+145	:	douta	<=	12163481  ;
+146	:	douta	<=	12247367  ;
+147	:	douta	<=	12331253  ;
+148	:	douta	<=	12415139  ;
+149	:	douta	<=	12499025  ;
+150	:	douta	<=	12582912  ;
+151	:	douta	<=	12666798  ;
+152	:	douta	<=	12750684  ;
+153	:	douta	<=	12834570  ;
+154	:	douta	<=	12918456  ;
+155	:	douta	<=	13002342  ;
+156	:	douta	<=	13086228  ;
+157	:	douta	<=	13170114  ;
+158	:	douta	<=	13254000  ;
+159	:	douta	<=	13337886  ;
+160	:	douta	<=	13421772  ;
+161	:	douta	<=	13505658  ;
+162	:	douta	<=	13589544  ;
+163	:	douta	<=	13673431  ;
+164	:	douta	<=	13757317  ;
+165	:	douta	<=	13841203  ;
+166	:	douta	<=	13925089  ;
+167	:	douta	<=	14008975  ;
+168	:	douta	<=	14092861  ;
+169	:	douta	<=	14176747  ;
+170	:	douta	<=	14260633  ;
+171	:	douta	<=	14344519  ;
+172	:	douta	<=	14428405  ;
+173	:	douta	<=	14512291  ;
+174	:	douta	<=	14596177  ;
+175	:	douta	<=	14680064  ;
+176	:	douta	<=	14763950  ;
+177	:	douta	<=	14847836  ;
+178	:	douta	<=	14931722  ;
+179	:	douta	<=	15015608  ;
+180	:	douta	<=	15099494  ;
+181	:	douta	<=	15183380  ;
+182	:	douta	<=	15267266  ;
+183	:	douta	<=	15351152  ;
+184	:	douta	<=	15435038  ;
+185	:	douta	<=	15518924  ;
+186	:	douta	<=	15602810  ;
+187	:	douta	<=	15686696  ;
+188	:	douta	<=	15770583  ;
+189	:	douta	<=	15854469  ;
+190	:	douta	<=	15938355  ;
+191	:	douta	<=	16022241  ;
+192	:	douta	<=	16106127  ;
+193	:	douta	<=	16190013  ;
+194	:	douta	<=	16273899  ;
+195	:	douta	<=	16357785  ;
+196	:	douta	<=	16441671  ;
+197	:	douta	<=	16525557  ;
+198	:	douta	<=	16609443  ;
+199	:	douta	<=	16693329  ;
+200	:	douta	<=	16777216  ;
+201	:	douta	<=	16861102  ;
+202	:	douta	<=	16944988  ;
+203	:	douta	<=	17028874  ;
+204	:	douta	<=	17112760  ;
+205	:	douta	<=	17196646  ;
+206	:	douta	<=	17280532  ;
+207	:	douta	<=	17364418  ;
+208	:	douta	<=	17448304  ;
+209	:	douta	<=	17532190  ;
+210	:	douta	<=	17616076  ;
+211	:	douta	<=	17699962  ;
+212	:	douta	<=	17783848  ;
+213	:	douta	<=	17867735  ;
+214	:	douta	<=	17951621  ;
+215	:	douta	<=	18035507  ;
+216	:	douta	<=	18119393  ;
+217	:	douta	<=	18203279  ;
+218	:	douta	<=	18287165  ;
+219	:	douta	<=	18371051  ;
+220	:	douta	<=	18454937  ;
+221	:	douta	<=	18538823  ;
+222	:	douta	<=	18622709  ;
+223	:	douta	<=	18706595  ;
+224	:	douta	<=	18790481  ;
+225	:	douta	<=	18874368  ;
+226	:	douta	<=	18958254  ;
+227	:	douta	<=	19042140  ;
+228	:	douta	<=	19126026  ;
+229	:	douta	<=	19209912  ;
+230	:	douta	<=	19293798  ;
+231	:	douta	<=	19377684  ;
+232	:	douta	<=	19461570  ;
+233	:	douta	<=	19545456  ;
+234	:	douta	<=	19629342  ;
+235	:	douta	<=	19713228  ;
+236	:	douta	<=	19797114  ;
+237	:	douta	<=	19881000  ;
+238	:	douta	<=	19964887  ;
+239	:	douta	<=	20048773  ;
+240	:	douta	<=	20132659  ;
+241	:	douta	<=	20216545  ;
+242	:	douta	<=	20300431  ;
+243	:	douta	<=	20384317  ;
+244	:	douta	<=	20468203  ;
+245	:	douta	<=	20552089  ;
+246	:	douta	<=	20635975  ;
+247	:	douta	<=	20719861  ;
+248	:	douta	<=	20803747  ;
+249	:	douta	<=	20887633  ;
+250	:	douta	<=	20971520  ;
+251	:	douta	<=	21055406  ;
+252	:	douta	<=	21139292  ;
+253	:	douta	<=	21223178  ;
+254	:	douta	<=	21307064  ;
+255	:	douta	<=	21390950  ;
+256	:	douta	<=	21474836  ;
+257	:	douta	<=	21558722  ;
+258	:	douta	<=	21642608  ;
+259	:	douta	<=	21726494  ;
+260	:	douta	<=	21810380  ;
+261	:	douta	<=	21894266  ;
+262	:	douta	<=	21978152  ;
+263	:	douta	<=	22062039  ;
+264	:	douta	<=	22145925  ;
+265	:	douta	<=	22229811  ;
+266	:	douta	<=	22313697  ;
+267	:	douta	<=	22397583  ;
+268	:	douta	<=	22481469  ;
+269	:	douta	<=	22565355  ;
+270	:	douta	<=	22649241  ;
+271	:	douta	<=	22733127  ;
+272	:	douta	<=	22817013  ;
+273	:	douta	<=	22900899  ;
+274	:	douta	<=	22984785  ;
+275	:	douta	<=	23068672  ;
+276	:	douta	<=	23152558  ;
+277	:	douta	<=	23236444  ;
+278	:	douta	<=	23320330  ;
+279	:	douta	<=	23404216  ;
+280	:	douta	<=	23488102  ;
+281	:	douta	<=	23571988  ;
+282	:	douta	<=	23655874  ;
+283	:	douta	<=	23739760  ;
+284	:	douta	<=	23823646  ;
+285	:	douta	<=	23907532  ;
+286	:	douta	<=	23991418  ;
+287	:	douta	<=	24075304  ;
+288	:	douta	<=	24159191  ;
+289	:	douta	<=	24243077  ;
+290	:	douta	<=	24326963  ;
+291	:	douta	<=	24410849  ;
+292	:	douta	<=	24494735  ;
+293	:	douta	<=	24578621  ;
+294	:	douta	<=	24662507  ;
+295	:	douta	<=	24746393  ;
+296	:	douta	<=	24830279  ;
+297	:	douta	<=	24914165  ;
+298	:	douta	<=	24998051  ;
+299	:	douta	<=	25081937  ;
+300	:	douta	<=	25165824  ;
+301	:	douta	<=	25249710  ;
+302	:	douta	<=	25333596  ;
+303	:	douta	<=	25417482  ;
+304	:	douta	<=	25501368  ;
+305	:	douta	<=	25585254  ;
+306	:	douta	<=	25669140  ;
+307	:	douta	<=	25753026  ;
+308	:	douta	<=	25836912  ;
+309	:	douta	<=	25920798  ;
+310	:	douta	<=	26004684  ;
+311	:	douta	<=	26088570  ;
+312	:	douta	<=	26172456  ;
+313	:	douta	<=	26256343  ;
+314	:	douta	<=	26340229  ;
+315	:	douta	<=	26424115  ;
+316	:	douta	<=	26508001  ;
+317	:	douta	<=	26591887  ;
+318	:	douta	<=	26675773  ;
+319	:	douta	<=	26759659  ;
+320	:	douta	<=	26843545  ;
+321	:	douta	<=	26927431  ;
+322	:	douta	<=	27011317  ;
+323	:	douta	<=	27095203  ;
+324	:	douta	<=	27179089  ;
+325	:	douta	<=	27262976  ;
+326	:	douta	<=	27346862  ;
+327	:	douta	<=	27430748  ;
+328	:	douta	<=	27514634  ;
+329	:	douta	<=	27598520  ;
+330	:	douta	<=	27682406  ;
+331	:	douta	<=	27766292  ;
+332	:	douta	<=	27850178  ;
+333	:	douta	<=	27934064  ;
+334	:	douta	<=	28017950  ;
+335	:	douta	<=	28101836  ;
+336	:	douta	<=	28185722  ;
+337	:	douta	<=	28269608  ;
+338	:	douta	<=	28353495  ;
+339	:	douta	<=	28437381  ;
+340	:	douta	<=	28521267  ;
+341	:	douta	<=	28605153  ;
+342	:	douta	<=	28689039  ;
+343	:	douta	<=	28772925  ;
+344	:	douta	<=	28856811  ;
+345	:	douta	<=	28940697  ;
+346	:	douta	<=	29024583  ;
+347	:	douta	<=	29108469  ;
+348	:	douta	<=	29192355  ;
+349	:	douta	<=	29276241  ;
+350	:	douta	<=	29360128  ;
+351	:	douta	<=	29444014  ;
+352	:	douta	<=	29527900  ;
+353	:	douta	<=	29611786  ;
+354	:	douta	<=	29695672  ;
+355	:	douta	<=	29779558  ;
+356	:	douta	<=	29863444  ;
+357	:	douta	<=	29947330  ;
+358	:	douta	<=	30031216  ;
+359	:	douta	<=	30115102  ;
+360	:	douta	<=	30198988  ;
+361	:	douta	<=	30282874  ;
+362	:	douta	<=	30366760  ;
+363	:	douta	<=	30450647  ;
+364	:	douta	<=	30534533  ;
+365	:	douta	<=	30618419  ;
+366	:	douta	<=	30702305  ;
+367	:	douta	<=	30786191  ;
+368	:	douta	<=	30870077  ;
+369	:	douta	<=	30953963  ;
+370	:	douta	<=	31037849  ;
+371	:	douta	<=	31121735  ;
+372	:	douta	<=	31205621  ;
+373	:	douta	<=	31289507  ;
+374	:	douta	<=	31373393  ;
+375	:	douta	<=	31457280  ;
+376	:	douta	<=	31541166  ;
+377	:	douta	<=	31625052  ;
+378	:	douta	<=	31708938  ;
+379	:	douta	<=	31792824  ;
+380	:	douta	<=	31876710  ;
+381	:	douta	<=	31960596  ;
+382	:	douta	<=	32044482  ;
+383	:	douta	<=	32128368  ;
+384	:	douta	<=	32212254  ;
+385	:	douta	<=	32296140  ;
+386	:	douta	<=	32380026  ;
+387	:	douta	<=	32463912  ;
+388	:	douta	<=	32547799  ;
+389	:	douta	<=	32631685  ;
+390	:	douta	<=	32715571  ;
+391	:	douta	<=	32799457  ;
+392	:	douta	<=	32883343  ;
+393	:	douta	<=	32967229  ;
+394	:	douta	<=	33051115  ;
+395	:	douta	<=	33135001  ;
+396	:	douta	<=	33218887  ;
+397	:	douta	<=	33302773  ;
+398	:	douta	<=	33386659  ;
+399	:	douta	<=	33470545  ;
+		default	:	douta	<=	douta	;
+		endcase	
+end
+			
+
+endmodule

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/R_CAL_1.v

@@ -0,0 +1,348 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    17:05:24 04/08/2022 
+// Design Name: 
+// Module Name:    R_CAL 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module R_CAL_1(
+input 				i_clk       ,
+input 				i_rstn      ,
+input signed[7:0]	i_temp		,
+input 		[15:0]	fre_mode		,
+output reg[3:0]		R_CAL
+
+    );
+
+//接收通道1               
+always@(posedge i_clk,negedge i_rstn)begin	//1dB 步进
+	if(!i_rstn)
+		R_CAL<='d0;
+	else if(i_temp>=8'sd70)begin//高温校准接收通道1
+	case(fre_mode)
+	0 : R_CAL<= 	7	; //20375	~	20414
+	1 : R_CAL<= 	7	; //20415	~	20454
+	2 : R_CAL<= 	7	; //20455	~	20494
+	3 : R_CAL<= 	6	; //20495	~	20534
+	4 : R_CAL<= 	6	; //20535	~	20574
+	5 : R_CAL<= 	6	; //20575	~	20614
+	6 : R_CAL<= 	6	; //20615	~	20654
+	7 : R_CAL<= 	6	; //20655	~	20694
+	8 : R_CAL<= 	5	; //20695	~	20734
+	9 : R_CAL<= 	5	; //20735	~	20774
+	10: R_CAL<= 	6	; //20775	~	20814
+	11: R_CAL<= 	6	; //20815	~	20854
+	12: R_CAL<= 	6	; //20855	~	20894
+	13: R_CAL<= 	6	; //20895	~	20934
+	14: R_CAL<= 	6	; //20935	~	20974
+	15: R_CAL<= 	6	; //20975	~	21014
+	16: R_CAL<= 	6	; //21015	~	21054
+	17: R_CAL<= 	6	; //21055	~	21094
+	18: R_CAL<= 	6	; //21095	~	21134
+	19: R_CAL<= 	7	; //21135	~	21174
+	20: R_CAL<= 	7	; //21175	~	21214
+	21: R_CAL<= 	7	; //21215	~	21254
+	22: R_CAL<= 	8	; //21255	~	21294
+	23: R_CAL<= 	8	; //21295	~	21334
+	24: R_CAL<= 	8	; //21335	~	21374
+	25: R_CAL<= 	8	; //21375	~	21414
+	26: R_CAL<= 	8	; //21415	~	21454
+	27: R_CAL<= 	8	; //21455	~	21494
+	28: R_CAL<= 	8	; //21495	~	21534
+	29: R_CAL<= 	8	; //21535	~	21574
+	30: R_CAL<= 	8	; //21575	~	21614
+	31: R_CAL<= 	8	 ; //21615	~	21654
+	32: R_CAL<= 	8	 ; //21655	~	21694
+	33: R_CAL<= 	8	 ; //21695	~	21734
+	34: R_CAL<= 	8	 ; //21735	~	21774
+	35: R_CAL<= 	8	 ; //21775	~	21814
+	36: R_CAL<= 	8	 ; //21815	~	21854
+	37: R_CAL<= 	8	 ; //21855	~	21894
+	38: R_CAL<= 	7	 ; //21895	~	21934
+	39: R_CAL<= 	7	 ; //21935	~	21974
+	40: R_CAL<= 	7	 ; //21975	~	22014
+	41: R_CAL<= 	7	 ; //22015	~	22054
+	42: R_CAL<= 	7	 ; //22055	~	22094
+	43: R_CAL<= 	7	 ; //22095	~	22134
+	44: R_CAL<= 	7	 ; //22135	~	22174
+	45: R_CAL<= 	7	 ; //22175	~	22214
+	46: R_CAL<= 	7	 ; //22215	~	22254
+	47: R_CAL<= 	7	 ; //22255	~	22294
+	48: R_CAL<= 	7	 ; //22295	~	22334
+	49: R_CAL<= 	7	 ; //22335	~	22374
+	50: R_CAL<= 	7	 ; //22375	~	22414
+	51: R_CAL<= 	7	 ; //22415	~	22454
+	52: R_CAL<= 	7	 ; //22455	~	22494
+	53: R_CAL<= 	7    ; //22495	~	22534
+	54: R_CAL<= 	7    ; //22535	~	22574
+	55: R_CAL<= 	7    ; //22575	~	22614
+	56: R_CAL<= 	7    ; //22615	~	22654
+	57: R_CAL<= 	7    ; //22655	~	22694
+	58: R_CAL<= 	8    ; //22695	~	22734
+	59: R_CAL<= 	8    ; //22735	~	22774
+	60: R_CAL<= 	8    ; //22775	~	22814
+	61: R_CAL<= 	8    ; //22815	~	22854
+	62: R_CAL<= 	8    ; //22855	~	22894
+	63: R_CAL<= 	8    ; //22895	~	22934
+	64: R_CAL<= 	8    ; //22935	~	22974
+	65: R_CAL<= 	8    ; //22975	~	23014
+	66: R_CAL<= 	8    ; //23015	~	23054
+	67: R_CAL<= 	8    ; //23055	~	23094
+	68: R_CAL<= 	7    ; //23095	~	23134
+	69: R_CAL<= 	7    ; //23135	~	23174
+	70: R_CAL<= 	7    ; //23175	~	23214
+	71: R_CAL<= 	7    ; //23215	~	23254
+	72: R_CAL<= 	6    ; //23255	~	23294
+	73: R_CAL<= 	6    ; //23295	~	23334
+	74: R_CAL<= 	6    ; //23335	~	23374
+	75: R_CAL<= 	6    ; //23375	~	23414
+	76: R_CAL<= 	6    ; //23415	~	23454
+	77: R_CAL<= 	6    ; //23455	~	23494
+	78: R_CAL<= 	6    ; //23495	~	23534
+	79: R_CAL<= 	5    ; //23535	~	23574
+	80: R_CAL<= 	6    ; //23575	~	23614
+	81: R_CAL<= 	6    ; //23615	~	23654
+	82: R_CAL<= 	6    ; //23655	~	23694
+	83: R_CAL<= 	6    ; //23695	~	23734
+	84: R_CAL<= 	6    ; //23735	~	23774
+	85: R_CAL<= 	6    ; //23775	~	23814
+	86: R_CAL<= 	6    ; //23815	~	23854
+	87: R_CAL<= 	6    ; //23855	~	23875
+	default:R_CAL<=R_CAL;
+	endcase
+	end
+
+	else if(i_temp>=8'sd0)begin//常温校准接收通道1
+	case(fre_mode)
+	0 : R_CAL<= 	7	   	; //20375	~	20414
+	1 : R_CAL<= 	7	   	; //20415	~	20454
+	2 : R_CAL<= 	7	   	; //20455	~	20494
+	3 : R_CAL<= 	6	   	; //20495	~	20534
+	4 : R_CAL<= 	6	   	; //20535	~	20574
+	5 : R_CAL<= 	6	   	; //20575	~	20614
+	6 : R_CAL<= 	6	   	; //20615	~	20654
+	7 : R_CAL<= 	6	   	; //20655	~	20694
+	8 : R_CAL<= 	5	   	; //20695	~	20734
+	9 : R_CAL<= 	5	   	; //20735	~	20774
+	10: R_CAL<= 	6	   	; //20775	~	20814
+	11: R_CAL<= 	6	   	; //20815	~	20854
+	12: R_CAL<= 	6	   	; //20855	~	20894
+	13: R_CAL<= 	6	   	; //20895	~	20934
+	14: R_CAL<= 	6	   	; //20935	~	20974
+	15: R_CAL<= 	6	   	; //20975	~	21014
+	16: R_CAL<= 	6	   	; //21015	~	21054
+	17: R_CAL<= 	6	   	; //21055	~	21094
+	18: R_CAL<= 	6	   	; //21095	~	21134
+	19: R_CAL<= 	7	   	; //21135	~	21174
+	20: R_CAL<= 	7	   	; //21175	~	21214
+	21: R_CAL<= 	7	   	; //21215	~	21254
+	22: R_CAL<= 	8	   	; //21255	~	21294
+	23: R_CAL<= 	8	   	; //21295	~	21334
+	24: R_CAL<= 	8	   	; //21335	~	21374
+	25: R_CAL<= 	8	   	; //21375	~	21414
+	26: R_CAL<= 	8	   	; //21415	~	21454
+	27: R_CAL<= 	8	   	; //21455	~	21494
+	28: R_CAL<= 	8	   	; //21495	~	21534
+	29: R_CAL<= 	8	   	; //21535	~	21574
+	30: R_CAL<= 	8	   	; //21575	~	21614
+	31: R_CAL<= 	8	   	; //21615	~	21654
+	32: R_CAL<= 	8	   	; //21655	~	21694
+	33: R_CAL<= 	8	   	; //21695	~	21734
+	34: R_CAL<= 	8	   	; //21735	~	21774
+	35: R_CAL<= 	8	   	; //21775	~	21814
+	36: R_CAL<= 	8	   	; //21815	~	21854
+	37: R_CAL<= 	8	   	; //21855	~	21894
+	38: R_CAL<= 	7	   	; //21895	~	21934
+	39: R_CAL<= 	7	   	; //21935	~	21974
+	40: R_CAL<= 	7	   	; //21975	~	22014
+	41: R_CAL<= 	7	   	; //22015	~	22054
+	42: R_CAL<= 	7	   	; //22055	~	22094
+	43: R_CAL<= 	7	   	; //22095	~	22134
+	44: R_CAL<= 	7	   	; //22135	~	22174
+	45: R_CAL<= 	7	   	; //22175	~	22214
+	46: R_CAL<= 	7	   	; //22215	~	22254
+	47: R_CAL<= 	7	   	; //22255	~	22294
+	48: R_CAL<= 	7	   	; //22295	~	22334
+	49: R_CAL<= 	7	   	; //22335	~	22374
+	50: R_CAL<= 	7	   	; //22375	~	22414
+	51: R_CAL<= 	7	   	; //22415	~	22454
+	52: R_CAL<= 	7	   	; //22455	~	22494
+	53: R_CAL<= 	7	    ; //22495	~	22534
+	54: R_CAL<= 	7	    ; //22535	~	22574
+	55: R_CAL<= 	7	    ; //22575	~	22614
+	56: R_CAL<= 	7	    ; //22615	~	22654
+	57: R_CAL<= 	7	    ; //22655	~	22694
+	58: R_CAL<= 	8	    ; //22695	~	22734
+	59: R_CAL<= 	8	    ; //22735	~	22774
+	60: R_CAL<= 	8	    ; //22775	~	22814
+	61: R_CAL<= 	8	    ; //22815	~	22854
+	62: R_CAL<= 	8	    ; //22855	~	22894
+	63: R_CAL<= 	8	    ; //22895	~	22934
+	64: R_CAL<= 	8	    ; //22935	~	22974
+	65: R_CAL<= 	8	    ; //22975	~	23014
+	66: R_CAL<= 	8	    ; //23015	~	23054
+	67: R_CAL<= 	8	    ; //23055	~	23094
+	68: R_CAL<= 	7	    ; //23095	~	23134
+	69: R_CAL<= 	7	    ; //23135	~	23174
+	70: R_CAL<= 	7	    ; //23175	~	23214
+	71: R_CAL<= 	7	   	; //23215	~	23254
+	72: R_CAL<= 	6	   	; //23255	~	23294
+	73: R_CAL<= 	6	   	; //23295	~	23334
+	74: R_CAL<= 	6	   	; //23335	~	23374
+	75: R_CAL<= 	6	   	; //23375	~	23414
+	76: R_CAL<= 	6	   	; //23415	~	23454
+	77: R_CAL<= 	6	   	; //23455	~	23494
+	78: R_CAL<= 	6	   	; //23495	~	23534
+	79: R_CAL<= 	5	   	; //23535	~	23574
+	80: R_CAL<= 	6	   	; //23575	~	23614
+	81: R_CAL<= 	6	   	; //23615	~	23654
+	82: R_CAL<= 	6	   	; //23655	~	23694
+	83: R_CAL<= 	6	   	; //23695	~	23734
+	84: R_CAL<= 	6	    ; //23735	~	23774
+	85: R_CAL<= 	6	    ; //23775	~	23814
+	86: R_CAL<= 	6	    ; //23815	~	23854
+	87: R_CAL<= 	6	    ; //23855	~	23875
+	default:R_CAL<=R_CAL;
+	endcase
+	end
+	else begin//低温校准接收通道1
+	case(fre_mode)
+	0 : R_CAL<= 		  7			; //20375	~	20414
+	1 : R_CAL<= 		  7			; //20415	~	20454
+	2 : R_CAL<= 		  7			; //20455	~	20494
+	3 : R_CAL<= 		  6			; //20495	~	20534
+	4 : R_CAL<= 		  6			; //20535	~	20574
+	5 : R_CAL<= 		  6			; //20575	~	20614
+	6 : R_CAL<= 		  6			; //20615	~	20654
+	7 : R_CAL<= 		  6			; //20655	~	20694
+	8 : R_CAL<= 		  5			; //20695	~	20734
+	9 : R_CAL<= 		  5			; //20735	~	20774
+	10: R_CAL<= 		  6			; //20775	~	20814
+	11: R_CAL<= 		  6			; //20815	~	20854
+	12: R_CAL<= 		  6			; //20855	~	20894
+	13: R_CAL<= 		  6			; //20895	~	20934
+	14: R_CAL<= 		  6			; //20935	~	20974
+	15: R_CAL<= 		  6			; //20975	~	21014
+	16: R_CAL<= 		  6			; //21015	~	21054
+	17: R_CAL<= 		  6			; //21055	~	21094
+	18: R_CAL<= 		  6			; //21095	~	21134
+	19: R_CAL<= 		  7			; //21135	~	21174
+	20: R_CAL<= 		  7			; //21175	~	21214
+	21: R_CAL<= 		  7			; //21215	~	21254
+	22: R_CAL<= 		  8			; //21255	~	21294
+	23: R_CAL<= 		  8			; //21295	~	21334
+	24: R_CAL<= 		  8			; //21335	~	21374
+	25: R_CAL<= 		  8			; //21375	~	21414
+	26: R_CAL<= 		  8			; //21415	~	21454
+	27: R_CAL<= 		  8			; //21455	~	21494
+	28: R_CAL<= 		  8			; //21495	~	21534
+	29: R_CAL<= 		  8			; //21535	~	21574
+	30: R_CAL<= 		  8			; //21575	~	21614
+	31: R_CAL<= 		  8			 ; //21615	~	21654
+	32: R_CAL<= 		  8			 ; //21655	~	21694
+	33: R_CAL<= 		  8			 ; //21695	~	21734
+	34: R_CAL<= 		  8			 ; //21735	~	21774
+	35: R_CAL<= 		  8			 ; //21775	~	21814
+	36: R_CAL<= 		  8			; //21815	~	21854
+	37: R_CAL<= 		  8			; //21855	~	21894
+	38: R_CAL<= 		  7			; //21895	~	21934
+	39: R_CAL<= 		  7			; //21935	~	21974
+	40: R_CAL<= 		  7			; //21975	~	22014
+	41: R_CAL<= 		  7			; //22015	~	22054
+	42: R_CAL<= 		  7			; //22055	~	22094
+	43: R_CAL<= 		  7			; //22095	~	22134
+	44: R_CAL<= 		  7			; //22135	~	22174
+	45: R_CAL<= 		  7			; //22175	~	22214
+	46: R_CAL<= 		  7			; //22215	~	22254
+	47: R_CAL<= 		  7			; //22255	~	22294
+	48: R_CAL<= 		  7			; //22295	~	22334
+	49: R_CAL<= 		  7			; //22335	~	22374
+	50: R_CAL<= 		  7			; //22375	~	22414
+	51: R_CAL<= 		  7			; //22415	~	22454
+	52: R_CAL<= 		  7			; //22455	~	22494
+	53: R_CAL<= 		  7		    ; //22495	~	22534
+	54: R_CAL<= 		  7		    ; //22535	~	22574
+	55: R_CAL<= 		  7		    ; //22575	~	22614
+	56: R_CAL<= 		  7		    ; //22615	~	22654
+	57: R_CAL<= 		  7		    ; //22655	~	22694
+	58: R_CAL<= 		  8		    ; //22695	~	22734
+	59: R_CAL<= 		  8		    ; //22735	~	22774
+	60: R_CAL<= 		  8		    ; //22775	~	22814
+	61: R_CAL<= 		  8		    ; //22815	~	22854
+	62: R_CAL<= 		  8		    ; //22855	~	22894
+	63: R_CAL<= 		  8		    ; //22895	~	22934
+	64: R_CAL<= 		  8		    ; //22935	~	22974
+	65: R_CAL<= 		  8		    ; //22975	~	23014
+	66: R_CAL<= 		  8		    ; //23015	~	23054
+	67: R_CAL<= 		  8		    ; //23055	~	23094
+	68: R_CAL<= 		  7		    ; //23095	~	23134
+	69: R_CAL<= 		  7		    ; //23135	~	23174
+	70: R_CAL<= 		  7		    ; //23175	~	23214
+	71: R_CAL<= 		  7			 ; //23215	~	23254
+	72: R_CAL<= 		  6			; //23255	~	23294
+	73: R_CAL<= 		  6			; //23295	~	23334
+	74: R_CAL<= 		  6			; //23335	~	23374
+	75: R_CAL<= 		  6			; //23375	~	23414
+	76: R_CAL<= 		  6			; //23415	~	23454
+	77: R_CAL<= 		  6			; //23455	~	23494
+	78: R_CAL<= 		  6			; //23495	~	23534
+	79: R_CAL<= 		  5			; //23535	~	23574
+	80: R_CAL<= 		  6			; //23575	~	23614
+	81: R_CAL<= 		  6			; //23615	~	23654
+	82: R_CAL<= 		  6			; //23655	~	23694
+	83: R_CAL<= 		  6			; //23695	~	23734
+	84: R_CAL<= 		  6		    ; //23735	~	23774
+	85: R_CAL<= 		  6		    ; //23775	~	23814
+	86: R_CAL<= 		  6		    ; //23815	~	23854
+	87: R_CAL<= 		  6		    ; //23855	~	23875
+	default:R_CAL<=R_CAL;
+	endcase
+	end
+end
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+endmodule

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/R_CAL_2.v

@@ -0,0 +1,349 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    17:05:24 04/08/2022 
+// Design Name: 
+// Module Name:    R_CAL 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module R_CAL_2(
+input 				i_clk       ,
+input 				i_rstn      ,
+input signed[7:0]	i_temp		,
+input 		[15:0]	fre_mode		,
+output reg[3:0]		R_CAL
+
+    );
+
+
+//接收通道2               
+always@(posedge i_clk,negedge i_rstn)begin	//1dB 步进
+	if(!i_rstn)
+		R_CAL<='d0;
+	else if(i_temp>=8'sd70)begin//高温校准接收通道2
+	case(fre_mode)
+	0 : R_CAL<= 		   6	; //20375	~	20414
+	1 : R_CAL<= 		   6	; //20415	~	20454
+	2 : R_CAL<= 		   6	; //20455	~	20494
+	3 : R_CAL<= 		   5	; //20495	~	20534
+	4 : R_CAL<= 		   5	; //20535	~	20574
+	5 : R_CAL<= 		   5	; //20575	~	20614
+	6 : R_CAL<= 		   5	; //20615	~	20654
+	7 : R_CAL<= 		   5	; //20655	~	20694
+	8 : R_CAL<= 		   5	; //20695	~	20734
+	9 : R_CAL<= 		   5	; //20735	~	20774
+	10: R_CAL<= 		   5	; //20775	~	20814
+	11: R_CAL<= 		   5	; //20815	~	20854
+	12: R_CAL<= 		   5	; //20855	~	20894
+	13: R_CAL<= 		   5	; //20895	~	20934
+	14: R_CAL<= 		   5	; //20935	~	20974
+	15: R_CAL<= 		   6	; //20975	~	21014
+	16: R_CAL<= 		   6	; //21015	~	21054
+	17: R_CAL<= 		   6	; //21055	~	21094
+	18: R_CAL<= 		   6	; //21095	~	21134
+	19: R_CAL<= 		   6	; //21135	~	21174
+	20: R_CAL<= 		   6	; //21175	~	21214
+	21: R_CAL<= 		   7	; //21215	~	21254
+	22: R_CAL<= 		   7	; //21255	~	21294
+	23: R_CAL<= 		   7	; //21295	~	21334
+	24: R_CAL<= 		   8	; //21335	~	21374
+	25: R_CAL<= 		   8	; //21375	~	21414
+	26: R_CAL<= 		   8	; //21415	~	21454
+	27: R_CAL<= 		   8	; //21455	~	21494
+	28: R_CAL<= 		   8	; //21495	~	21534
+	29: R_CAL<= 		   8	; //21535	~	21574
+	30: R_CAL<= 		   8	; //21575	~	21614
+	31: R_CAL<= 		   8	 ; //21615	~	21654
+	32: R_CAL<= 		   8	 ; //21655	~	21694
+	33: R_CAL<= 		   8	 ; //21695	~	21734
+	34: R_CAL<= 		   8	 ; //21735	~	21774
+	35: R_CAL<= 		   8	 ; //21775	~	21814
+	36: R_CAL<= 		   8	; //21815	~	21854
+	37: R_CAL<= 		   8	; //21855	~	21894
+	38: R_CAL<= 		   7	; //21895	~	21934
+	39: R_CAL<= 		   7	; //21935	~	21974
+	40: R_CAL<= 		   7	; //21975	~	22014
+	41: R_CAL<= 		   7	; //22015	~	22054
+	42: R_CAL<= 		   7	; //22055	~	22094
+	43: R_CAL<= 		   7	; //22095	~	22134
+	44: R_CAL<= 		   7	; //22135	~	22174
+	45: R_CAL<= 		   7	; //22175	~	22214
+	46: R_CAL<= 		   7	; //22215	~	22254
+	47: R_CAL<= 		   7	; //22255	~	22294
+	48: R_CAL<= 		   7	; //22295	~	22334
+	49: R_CAL<= 		   7	; //22335	~	22374
+	50: R_CAL<= 		   7	; //22375	~	22414
+	51: R_CAL<= 		   7	; //22415	~	22454
+	52: R_CAL<= 		   7	; //22455	~	22494
+	53: R_CAL<= 		   7    ; //22495	~	22534
+	54: R_CAL<= 		   7    ; //22535	~	22574
+	55: R_CAL<= 		   7    ; //22575	~	22614
+	56: R_CAL<= 		   7    ; //22615	~	22654
+	57: R_CAL<= 		   7    ; //22655	~	22694
+	58: R_CAL<= 		   7    ; //22695	~	22734
+	59: R_CAL<= 		   7    ; //22735	~	22774
+	60: R_CAL<= 		   7    ; //22775	~	22814
+	61: R_CAL<= 		   7    ; //22815	~	22854
+	62: R_CAL<= 		   7    ; //22855	~	22894
+	63: R_CAL<= 		   8    ; //22895	~	22934
+	64: R_CAL<= 		   8    ; //22935	~	22974
+	65: R_CAL<= 		   8    ; //22975	~	23014
+	66: R_CAL<= 		   8    ; //23015	~	23054
+	67: R_CAL<= 		   7    ; //23055	~	23094
+	68: R_CAL<= 		   7    ; //23095	~	23134
+	69: R_CAL<= 		   7    ; //23135	~	23174
+	70: R_CAL<= 		   7    ; //23175	~	23214
+	71: R_CAL<= 		   7	 ; //23215	~	23254
+	72: R_CAL<= 		   7	; //23255	~	23294
+	73: R_CAL<= 		   6	; //23295	~	23334
+	74: R_CAL<= 		   6	; //23335	~	23374
+	75: R_CAL<= 		   6	; //23375	~	23414
+	76: R_CAL<= 		   6	; //23415	~	23454
+	77: R_CAL<= 		   6	; //23455	~	23494
+	78: R_CAL<= 		   5	; //23495	~	23534
+	79: R_CAL<= 		   5	; //23535	~	23574
+	80: R_CAL<= 		   6	; //23575	~	23614
+	81: R_CAL<= 		   5	; //23615	~	23654
+	82: R_CAL<= 		   5	; //23655	~	23694
+	83: R_CAL<= 		   6	; //23695	~	23734
+	84: R_CAL<= 		   5    ; //23735	~	23774
+	85: R_CAL<= 		   6    ; //23775	~	23814
+	86: R_CAL<= 		   6    ; //23815	~	23854
+	87: R_CAL<= 		   6    ; //23855	~	23875
+	default:R_CAL<=R_CAL;
+	endcase
+	end
+
+	else if(i_temp>=8'sd0)begin//常温校准接收通道2
+	case(fre_mode)
+	0 : R_CAL<= 		   6	; //20375	~	20414
+	1 : R_CAL<= 		   6	; //20415	~	20454
+	2 : R_CAL<= 		   6	; //20455	~	20494
+	3 : R_CAL<= 		   5	; //20495	~	20534
+	4 : R_CAL<= 		   5	; //20535	~	20574
+	5 : R_CAL<= 		   5	; //20575	~	20614
+	6 : R_CAL<= 		   5	; //20615	~	20654
+	7 : R_CAL<= 		   5	; //20655	~	20694
+	8 : R_CAL<= 		   5	; //20695	~	20734
+	9 : R_CAL<= 		   5	; //20735	~	20774
+	10: R_CAL<= 		   5	; //20775	~	20814
+	11: R_CAL<= 		   5	; //20815	~	20854
+	12: R_CAL<= 		   5	; //20855	~	20894
+	13: R_CAL<= 		   5	; //20895	~	20934
+	14: R_CAL<= 		   5	; //20935	~	20974
+	15: R_CAL<= 		   6	; //20975	~	21014
+	16: R_CAL<= 		   6	; //21015	~	21054
+	17: R_CAL<= 		   6	; //21055	~	21094
+	18: R_CAL<= 		   6	; //21095	~	21134
+	19: R_CAL<= 		   6	; //21135	~	21174
+	20: R_CAL<= 		   6	; //21175	~	21214
+	21: R_CAL<= 		   7	; //21215	~	21254
+	22: R_CAL<= 		   7	; //21255	~	21294
+	23: R_CAL<= 		   7	; //21295	~	21334
+	24: R_CAL<= 		   8	; //21335	~	21374
+	25: R_CAL<= 		   8	; //21375	~	21414
+	26: R_CAL<= 		   8	; //21415	~	21454
+	27: R_CAL<= 		   8	; //21455	~	21494
+	28: R_CAL<= 		   8	; //21495	~	21534
+	29: R_CAL<= 		   8	; //21535	~	21574
+	30: R_CAL<= 		   8	; //21575	~	21614
+	31: R_CAL<= 		   8	 ; //21615	~	21654
+	32: R_CAL<= 		   8	 ; //21655	~	21694
+	33: R_CAL<= 		   8	 ; //21695	~	21734
+	34: R_CAL<= 		   8	 ; //21735	~	21774
+	35: R_CAL<= 		   8	 ; //21775	~	21814
+	36: R_CAL<= 		   8	; //21815	~	21854
+	37: R_CAL<= 		   8	; //21855	~	21894
+	38: R_CAL<= 		   7	; //21895	~	21934
+	39: R_CAL<= 		   7	; //21935	~	21974
+	40: R_CAL<= 		   7	; //21975	~	22014
+	41: R_CAL<= 		   7	; //22015	~	22054
+	42: R_CAL<= 		   7	; //22055	~	22094
+	43: R_CAL<= 		   7	; //22095	~	22134
+	44: R_CAL<= 		   7	; //22135	~	22174
+	45: R_CAL<= 		   7	; //22175	~	22214
+	46: R_CAL<= 		   7	; //22215	~	22254
+	47: R_CAL<= 		   7	; //22255	~	22294
+	48: R_CAL<= 		   7	; //22295	~	22334
+	49: R_CAL<= 		   7	; //22335	~	22374
+	50: R_CAL<= 		   7	; //22375	~	22414
+	51: R_CAL<= 		   7	; //22415	~	22454
+	52: R_CAL<= 		   7	; //22455	~	22494
+	53: R_CAL<= 		   7   ; //22495	~	22534
+	54: R_CAL<= 		   7   ; //22535	~	22574
+	55: R_CAL<= 		   7   ; //22575	~	22614
+	56: R_CAL<= 		   7   ; //22615	~	22654
+	57: R_CAL<= 		   7   ; //22655	~	22694
+	58: R_CAL<= 		   7   ; //22695	~	22734
+	59: R_CAL<= 		   7   ; //22735	~	22774
+	60: R_CAL<= 		   7   ; //22775	~	22814
+	61: R_CAL<= 		   7   ; //22815	~	22854
+	62: R_CAL<= 		   7   ; //22855	~	22894
+	63: R_CAL<= 		   8   ; //22895	~	22934
+	64: R_CAL<= 		   8   ; //22935	~	22974
+	65: R_CAL<= 		   8   ; //22975	~	23014
+	66: R_CAL<= 		   8   ; //23015	~	23054
+	67: R_CAL<= 		   7   ; //23055	~	23094
+	68: R_CAL<= 		   7   ; //23095	~	23134
+	69: R_CAL<= 		   7   ; //23135	~	23174
+	70: R_CAL<= 		   7   ; //23175	~	23214
+	71: R_CAL<= 		   7	 ; //23215	~	23254
+	72: R_CAL<= 		   7	; //23255	~	23294
+	73: R_CAL<= 		   6	; //23295	~	23334
+	74: R_CAL<= 		   6	; //23335	~	23374
+	75: R_CAL<= 		   6	; //23375	~	23414
+	76: R_CAL<= 		   6	; //23415	~	23454
+	77: R_CAL<= 		   6	; //23455	~	23494
+	78: R_CAL<= 		   5	; //23495	~	23534
+	79: R_CAL<= 		   5	; //23535	~	23574
+	80: R_CAL<= 		   6	; //23575	~	23614
+	81: R_CAL<= 		   5	; //23615	~	23654
+	82: R_CAL<= 		   5	; //23655	~	23694
+	83: R_CAL<= 		   6	; //23695	~	23734
+	84: R_CAL<= 		   5   ; //23735	~	23774
+	85: R_CAL<= 		   6   ; //23775	~	23814
+	86: R_CAL<= 		   6   ; //23815	~	23854
+	87: R_CAL<= 		   6   ; //23855	~	23875
+	default:R_CAL<=R_CAL;
+	endcase
+	end
+	else begin//低温校准接收通道2
+	case(fre_mode)
+	0 : R_CAL<= 		  6			; //20375	~	20414
+	1 : R_CAL<= 		  6			; //20415	~	20454
+	2 : R_CAL<= 		  6			; //20455	~	20494
+	3 : R_CAL<= 		  5			; //20495	~	20534
+	4 : R_CAL<= 		  5			; //20535	~	20574
+	5 : R_CAL<= 		  5			; //20575	~	20614
+	6 : R_CAL<= 		  5			; //20615	~	20654
+	7 : R_CAL<= 		  5			; //20655	~	20694
+	8 : R_CAL<= 		  5			; //20695	~	20734
+	9 : R_CAL<= 		  5			; //20735	~	20774
+	10: R_CAL<= 		  5			; //20775	~	20814
+	11: R_CAL<= 		  5			; //20815	~	20854
+	12: R_CAL<= 		  5			; //20855	~	20894
+	13: R_CAL<= 		  5			; //20895	~	20934
+	14: R_CAL<= 		  5			; //20935	~	20974
+	15: R_CAL<= 		  6			; //20975	~	21014
+	16: R_CAL<= 		  6			; //21015	~	21054
+	17: R_CAL<= 		  6			; //21055	~	21094
+	18: R_CAL<= 		  6			; //21095	~	21134
+	19: R_CAL<= 		  6			; //21135	~	21174
+	20: R_CAL<= 		  6			; //21175	~	21214
+	21: R_CAL<= 		  7			; //21215	~	21254
+	22: R_CAL<= 		  7			; //21255	~	21294
+	23: R_CAL<= 		  7			; //21295	~	21334
+	24: R_CAL<= 		  8			; //21335	~	21374
+	25: R_CAL<= 		  8			; //21375	~	21414
+	26: R_CAL<= 		  8			; //21415	~	21454
+	27: R_CAL<= 		  8			; //21455	~	21494
+	28: R_CAL<= 		  8			; //21495	~	21534
+	29: R_CAL<= 		  8			; //21535	~	21574
+	30: R_CAL<= 		  8			; //21575	~	21614
+	31: R_CAL<= 		  8			 ; //21615	~	21654
+	32: R_CAL<= 		  8			 ; //21655	~	21694
+	33: R_CAL<= 		  8			 ; //21695	~	21734
+	34: R_CAL<= 		  8			 ; //21735	~	21774
+	35: R_CAL<= 		  8			 ; //21775	~	21814
+	36: R_CAL<= 		  8			; //21815	~	21854
+	37: R_CAL<= 		  8			; //21855	~	21894
+	38: R_CAL<= 		  7			; //21895	~	21934
+	39: R_CAL<= 		  7			; //21935	~	21974
+	40: R_CAL<= 		  7			; //21975	~	22014
+	41: R_CAL<= 		  7			; //22015	~	22054
+	42: R_CAL<= 		  7			; //22055	~	22094
+	43: R_CAL<= 		  7			; //22095	~	22134
+	44: R_CAL<= 		  7			; //22135	~	22174
+	45: R_CAL<= 		  7			; //22175	~	22214
+	46: R_CAL<= 		  7			; //22215	~	22254
+	47: R_CAL<= 		  7			; //22255	~	22294
+	48: R_CAL<= 		  7			; //22295	~	22334
+	49: R_CAL<= 		  7			; //22335	~	22374
+	50: R_CAL<= 		  7			; //22375	~	22414
+	51: R_CAL<= 		  7			; //22415	~	22454
+	52: R_CAL<= 		  7			; //22455	~	22494
+	53: R_CAL<= 		  7		    ; //22495	~	22534
+	54: R_CAL<= 		  7		    ; //22535	~	22574
+	55: R_CAL<= 		  7		    ; //22575	~	22614
+	56: R_CAL<= 		  7		    ; //22615	~	22654
+	57: R_CAL<= 		  7		    ; //22655	~	22694
+	58: R_CAL<= 		  7		    ; //22695	~	22734
+	59: R_CAL<= 		  7		    ; //22735	~	22774
+	60: R_CAL<= 		  7		    ; //22775	~	22814
+	61: R_CAL<= 		  7		    ; //22815	~	22854
+	62: R_CAL<= 		  7		    ; //22855	~	22894
+	63: R_CAL<= 		  8		    ; //22895	~	22934
+	64: R_CAL<= 		  8		    ; //22935	~	22974
+	65: R_CAL<= 		  8		    ; //22975	~	23014
+	66: R_CAL<= 		  8		    ; //23015	~	23054
+	67: R_CAL<= 		  7		    ; //23055	~	23094
+	68: R_CAL<= 		  7		    ; //23095	~	23134
+	69: R_CAL<= 		  7		    ; //23135	~	23174
+	70: R_CAL<= 		  7		    ; //23175	~	23214
+	71: R_CAL<= 		  7			 ; //23215	~	23254
+	72: R_CAL<= 		  7			; //23255	~	23294
+	73: R_CAL<= 		  6			; //23295	~	23334
+	74: R_CAL<= 		  6			; //23335	~	23374
+	75: R_CAL<= 		  6			; //23375	~	23414
+	76: R_CAL<= 		  6			; //23415	~	23454
+	77: R_CAL<= 		  6			; //23455	~	23494
+	78: R_CAL<= 		  5			; //23495	~	23534
+	79: R_CAL<= 		  5			; //23535	~	23574
+	80: R_CAL<= 		  6			; //23575	~	23614
+	81: R_CAL<= 		  5			; //23615	~	23654
+	82: R_CAL<= 		  5			; //23655	~	23694
+	83: R_CAL<= 		  6			; //23695	~	23734
+	84: R_CAL<= 		  5		    ; //23735	~	23774
+	85: R_CAL<= 		  6		    ; //23775	~	23814
+	86: R_CAL<= 		  6		    ; //23815	~	23854
+	87: R_CAL<= 		  6		    ; //23855	~	23875
+	default:R_CAL<=R_CAL;
+	endcase
+	end
+end
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+endmodule

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/R_CAL_3.v

@@ -0,0 +1,348 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    17:05:24 04/08/2022 
+// Design Name: 
+// Module Name:    R_CAL 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module R_CAL_3(
+input 				i_clk       ,
+input 				i_rstn      ,
+input signed[7:0]	i_temp		,
+input 		[15:0]	fre_mode		,
+output reg[3:0]		R_CAL
+
+    );
+
+//接收通道3               
+always@(posedge i_clk,negedge i_rstn)begin	//1dB 步进
+	if(!i_rstn)
+		R_CAL<='d0;
+	else if(i_temp>=8'sd70)begin//高温校准接收通道3
+	case(fre_mode)
+	0 : R_CAL<= 		   7	; //20375	~	20414
+	1 : R_CAL<= 		   7	; //20415	~	20454
+	2 : R_CAL<= 		   7	; //20455	~	20494
+	3 : R_CAL<= 		   7	; //20495	~	20534
+	4 : R_CAL<= 		   7	; //20535	~	20574
+	5 : R_CAL<= 		   7	; //20575	~	20614
+	6 : R_CAL<= 		   6	; //20615	~	20654
+	7 : R_CAL<= 		   6	; //20655	~	20694
+	8 : R_CAL<= 		   6	; //20695	~	20734
+	9 : R_CAL<= 		   6	; //20735	~	20774
+	10: R_CAL<= 		   6	; //20775	~	20814
+	11: R_CAL<= 		   6	; //20815	~	20854
+	12: R_CAL<= 		   6	; //20855	~	20894
+	13: R_CAL<= 		   6	; //20895	~	20934
+	14: R_CAL<= 		   6	; //20935	~	20974
+	15: R_CAL<= 		   6	; //20975	~	21014
+	16: R_CAL<= 		   6	; //21015	~	21054
+	17: R_CAL<= 		   7	; //21055	~	21094
+	18: R_CAL<= 		   7	; //21095	~	21134
+	19: R_CAL<= 		   7	; //21135	~	21174
+	20: R_CAL<= 		   8	; //21175	~	21214
+	21: R_CAL<= 		   8	; //21215	~	21254
+	22: R_CAL<= 		   8	; //21255	~	21294
+	23: R_CAL<= 		   8	; //21295	~	21334
+	24: R_CAL<= 		   8	; //21335	~	21374
+	25: R_CAL<= 		   8	; //21375	~	21414
+	26: R_CAL<= 		   9	; //21415	~	21454
+	27: R_CAL<= 		   9	; //21455	~	21494
+	28: R_CAL<= 		   9	; //21495	~	21534
+	29: R_CAL<= 		   9	; //21535	~	21574
+	30: R_CAL<= 		   9	; //21575	~	21614
+	31: R_CAL<= 		   9	 ; //21615	~	21654
+	32: R_CAL<= 		   9	 ; //21655	~	21694
+	33: R_CAL<= 		   9	 ; //21695	~	21734
+	34: R_CAL<= 		   9	 ; //21735	~	21774
+	35: R_CAL<= 		   9	 ; //21775	~	21814
+	36: R_CAL<= 		   9	; //21815	~	21854
+	37: R_CAL<= 		   9	; //21855	~	21894
+	38: R_CAL<= 		   9	; //21895	~	21934
+	39: R_CAL<= 		   9	; //21935	~	21974
+	40: R_CAL<= 		   8	; //21975	~	22014
+	41: R_CAL<= 		   8	; //22015	~	22054
+	42: R_CAL<= 		   8	; //22055	~	22094
+	43: R_CAL<= 		   8	; //22095	~	22134
+	44: R_CAL<= 		   8	; //22135	~	22174
+	45: R_CAL<= 		   8	; //22175	~	22214
+	46: R_CAL<= 		   8	; //22215	~	22254
+	47: R_CAL<= 		   8	; //22255	~	22294
+	48: R_CAL<= 		   8	; //22295	~	22334
+	49: R_CAL<= 		   8	; //22335	~	22374
+	50: R_CAL<= 		   8	; //22375	~	22414
+	51: R_CAL<= 		   8	; //22415	~	22454
+	52: R_CAL<= 		   8	; //22455	~	22494
+	53: R_CAL<= 		   8    ; //22495	~	22534
+	54: R_CAL<= 		   8    ; //22535	~	22574
+	55: R_CAL<= 		   8    ; //22575	~	22614
+	56: R_CAL<= 		   8    ; //22615	~	22654
+	57: R_CAL<= 		   8    ; //22655	~	22694
+	58: R_CAL<= 		   8    ; //22695	~	22734
+	59: R_CAL<= 		   8    ; //22735	~	22774
+	60: R_CAL<= 		   8    ; //22775	~	22814
+	61: R_CAL<= 		   8    ; //22815	~	22854
+	62: R_CAL<= 		   8    ; //22855	~	22894
+	63: R_CAL<= 		   9    ; //22895	~	22934
+	64: R_CAL<= 		   9    ; //22935	~	22974
+	65: R_CAL<= 		   9    ; //22975	~	23014
+	66: R_CAL<= 		   9    ; //23015	~	23054
+	67: R_CAL<= 		   9    ; //23055	~	23094
+	68: R_CAL<= 		   8    ; //23095	~	23134
+	69: R_CAL<= 		   8    ; //23135	~	23174
+	70: R_CAL<= 		   8    ; //23175	~	23214
+	71: R_CAL<= 		   8	 ; //23215	~	23254
+	72: R_CAL<= 		   8	; //23255	~	23294
+	73: R_CAL<= 		   7	; //23295	~	23334
+	74: R_CAL<= 		   7	; //23335	~	23374
+	75: R_CAL<= 		   7	; //23375	~	23414
+	76: R_CAL<= 		   7	; //23415	~	23454
+	77: R_CAL<= 		   7	; //23455	~	23494
+	78: R_CAL<= 		   7	; //23495	~	23534
+	79: R_CAL<= 		   7	; //23535	~	23574
+	80: R_CAL<= 		   7	; //23575	~	23614
+	81: R_CAL<= 		   7	; //23615	~	23654
+	82: R_CAL<= 		   7	; //23655	~	23694
+	83: R_CAL<= 		   7	; //23695	~	23734
+	84: R_CAL<= 		   7    ; //23735	~	23774
+	85: R_CAL<= 		   7    ; //23775	~	23814
+	86: R_CAL<= 		   7    ; //23815	~	23854
+	87: R_CAL<= 		   7    ; //23855	~	23875
+	default:R_CAL<=R_CAL;
+	endcase
+	end
+
+	else if(i_temp>=8'sd0)begin//常温校准接收通道3
+	case(fre_mode)
+	0 : R_CAL<= 	7			; //20375	~	20414
+	1 : R_CAL<= 	7			; //20415	~	20454
+	2 : R_CAL<= 	7			; //20455	~	20494
+	3 : R_CAL<= 	7			; //20495	~	20534
+	4 : R_CAL<= 	7			; //20535	~	20574
+	5 : R_CAL<= 	7			; //20575	~	20614
+	6 : R_CAL<= 	6			; //20615	~	20654
+	7 : R_CAL<= 	6			; //20655	~	20694
+	8 : R_CAL<= 	6			; //20695	~	20734
+	9 : R_CAL<= 	6			; //20735	~	20774
+	10: R_CAL<= 	6			; //20775	~	20814
+	11: R_CAL<= 	6			; //20815	~	20854
+	12: R_CAL<= 	6			; //20855	~	20894
+	13: R_CAL<= 	6			; //20895	~	20934
+	14: R_CAL<= 	6			; //20935	~	20974
+	15: R_CAL<= 	6			; //20975	~	21014
+	16: R_CAL<= 	6			; //21015	~	21054
+	17: R_CAL<= 	7			; //21055	~	21094
+	18: R_CAL<= 	7			; //21095	~	21134
+	19: R_CAL<= 	7			; //21135	~	21174
+	20: R_CAL<= 	8			; //21175	~	21214
+	21: R_CAL<= 	8			; //21215	~	21254
+	22: R_CAL<= 	8			; //21255	~	21294
+	23: R_CAL<= 	8			; //21295	~	21334
+	24: R_CAL<= 	8			; //21335	~	21374
+	25: R_CAL<= 	8			; //21375	~	21414
+	26: R_CAL<= 	9			; //21415	~	21454
+	27: R_CAL<= 	9			; //21455	~	21494
+	28: R_CAL<= 	9			; //21495	~	21534
+	29: R_CAL<= 	9			; //21535	~	21574
+	30: R_CAL<= 	9			; //21575	~	21614
+	31: R_CAL<= 	9			 ; //21615	~	21654
+	32: R_CAL<= 	9			 ; //21655	~	21694
+	33: R_CAL<= 	9			 ; //21695	~	21734
+	34: R_CAL<= 	9			 ; //21735	~	21774
+	35: R_CAL<= 	9			 ; //21775	~	21814
+	36: R_CAL<= 	9			; //21815	~	21854
+	37: R_CAL<= 	9			; //21855	~	21894
+	38: R_CAL<= 	9			; //21895	~	21934
+	39: R_CAL<= 	9			; //21935	~	21974
+	40: R_CAL<= 	8			; //21975	~	22014
+	41: R_CAL<= 	8			; //22015	~	22054
+	42: R_CAL<= 	8			; //22055	~	22094
+	43: R_CAL<= 	8			; //22095	~	22134
+	44: R_CAL<= 	8			; //22135	~	22174
+	45: R_CAL<= 	8			; //22175	~	22214
+	46: R_CAL<= 	8			; //22215	~	22254
+	47: R_CAL<= 	8			; //22255	~	22294
+	48: R_CAL<= 	8			; //22295	~	22334
+	49: R_CAL<= 	8			; //22335	~	22374
+	50: R_CAL<= 	8			; //22375	~	22414
+	51: R_CAL<= 	8			; //22415	~	22454
+	52: R_CAL<= 	8			; //22455	~	22494
+	53: R_CAL<= 	8			   ; //22495	~	22534
+	54: R_CAL<= 	8			   ; //22535	~	22574
+	55: R_CAL<= 	8			   ; //22575	~	22614
+	56: R_CAL<= 	8			   ; //22615	~	22654
+	57: R_CAL<= 	8			   ; //22655	~	22694
+	58: R_CAL<= 	8			   ; //22695	~	22734
+	59: R_CAL<= 	8			   ; //22735	~	22774
+	60: R_CAL<= 	8			   ; //22775	~	22814
+	61: R_CAL<= 	8			   ; //22815	~	22854
+	62: R_CAL<= 	8			   ; //22855	~	22894
+	63: R_CAL<= 	9			   ; //22895	~	22934
+	64: R_CAL<= 	9			   ; //22935	~	22974
+	65: R_CAL<= 	9			   ; //22975	~	23014
+	66: R_CAL<= 	9			   ; //23015	~	23054
+	67: R_CAL<= 	9			   ; //23055	~	23094
+	68: R_CAL<= 	8			   ; //23095	~	23134
+	69: R_CAL<= 	8			   ; //23135	~	23174
+	70: R_CAL<= 	8			   ; //23175	~	23214
+	71: R_CAL<= 	8			 ; //23215	~	23254
+	72: R_CAL<= 	8			; //23255	~	23294
+	73: R_CAL<= 	7			; //23295	~	23334
+	74: R_CAL<= 	7			; //23335	~	23374
+	75: R_CAL<= 	7			; //23375	~	23414
+	76: R_CAL<= 	7			; //23415	~	23454
+	77: R_CAL<= 	7			; //23455	~	23494
+	78: R_CAL<= 	7			; //23495	~	23534
+	79: R_CAL<= 	7			; //23535	~	23574
+	80: R_CAL<= 	7			; //23575	~	23614
+	81: R_CAL<= 	7			; //23615	~	23654
+	82: R_CAL<= 	7			; //23655	~	23694
+	83: R_CAL<= 	7			; //23695	~	23734
+	84: R_CAL<= 	7			   ; //23735	~	23774
+	85: R_CAL<= 	7			   ; //23775	~	23814
+	86: R_CAL<= 	7			   ; //23815	~	23854
+	87: R_CAL<= 	7			   ; //23855	~	23875
+	default:R_CAL<=R_CAL;
+	endcase
+	end
+	else begin//低温校准接收通道3
+	case(fre_mode)
+	0 : R_CAL<= 		  7				; //20375	~	20414
+	1 : R_CAL<= 		  7				; //20415	~	20454
+	2 : R_CAL<= 		  7				; //20455	~	20494
+	3 : R_CAL<= 		  7				; //20495	~	20534
+	4 : R_CAL<= 		  7				; //20535	~	20574
+	5 : R_CAL<= 		  7				; //20575	~	20614
+	6 : R_CAL<= 		  6				; //20615	~	20654
+	7 : R_CAL<= 		  6				; //20655	~	20694
+	8 : R_CAL<= 		  6				; //20695	~	20734
+	9 : R_CAL<= 		  6				; //20735	~	20774
+	10: R_CAL<= 		  6				; //20775	~	20814
+	11: R_CAL<= 		  6				; //20815	~	20854
+	12: R_CAL<= 		  6				; //20855	~	20894
+	13: R_CAL<= 		  6				; //20895	~	20934
+	14: R_CAL<= 		  6				; //20935	~	20974
+	15: R_CAL<= 		  6				; //20975	~	21014
+	16: R_CAL<= 		  6				; //21015	~	21054
+	17: R_CAL<= 		  7				; //21055	~	21094
+	18: R_CAL<= 		  7				; //21095	~	21134
+	19: R_CAL<= 		  7				; //21135	~	21174
+	20: R_CAL<= 		  8				; //21175	~	21214
+	21: R_CAL<= 		  8				; //21215	~	21254
+	22: R_CAL<= 		  8				; //21255	~	21294
+	23: R_CAL<= 		  8				; //21295	~	21334
+	24: R_CAL<= 		  8				; //21335	~	21374
+	25: R_CAL<= 		  8				; //21375	~	21414
+	26: R_CAL<= 		  9				; //21415	~	21454
+	27: R_CAL<= 		  9				; //21455	~	21494
+	28: R_CAL<= 		  9				; //21495	~	21534
+	29: R_CAL<= 		  9				; //21535	~	21574
+	30: R_CAL<= 		  9				; //21575	~	21614
+	31: R_CAL<= 		  9				 ; //21615	~	21654
+	32: R_CAL<= 		  9				 ; //21655	~	21694
+	33: R_CAL<= 		  9				 ; //21695	~	21734
+	34: R_CAL<= 		  9				 ; //21735	~	21774
+	35: R_CAL<= 		  9				 ; //21775	~	21814
+	36: R_CAL<= 		  9				; //21815	~	21854
+	37: R_CAL<= 		  9				; //21855	~	21894
+	38: R_CAL<= 		  9				; //21895	~	21934
+	39: R_CAL<= 		  9				; //21935	~	21974
+	40: R_CAL<= 		  8				; //21975	~	22014
+	41: R_CAL<= 		  8				; //22015	~	22054
+	42: R_CAL<= 		  8				; //22055	~	22094
+	43: R_CAL<= 		  8				; //22095	~	22134
+	44: R_CAL<= 		  8				; //22135	~	22174
+	45: R_CAL<= 		  8				; //22175	~	22214
+	46: R_CAL<= 		  8				; //22215	~	22254
+	47: R_CAL<= 		  8				; //22255	~	22294
+	48: R_CAL<= 		  8				; //22295	~	22334
+	49: R_CAL<= 		  8				; //22335	~	22374
+	50: R_CAL<= 		  8				; //22375	~	22414
+	51: R_CAL<= 		  8				; //22415	~	22454
+	52: R_CAL<= 		  8				; //22455	~	22494
+	53: R_CAL<= 		  8			    ; //22495	~	22534
+	54: R_CAL<= 		  8			    ; //22535	~	22574
+	55: R_CAL<= 		  8			    ; //22575	~	22614
+	56: R_CAL<= 		  8			    ; //22615	~	22654
+	57: R_CAL<= 		  8			    ; //22655	~	22694
+	58: R_CAL<= 		  8			    ; //22695	~	22734
+	59: R_CAL<= 		  8			    ; //22735	~	22774
+	60: R_CAL<= 		  8			    ; //22775	~	22814
+	61: R_CAL<= 		  8			    ; //22815	~	22854
+	62: R_CAL<= 		  8			    ; //22855	~	22894
+	63: R_CAL<= 		  9			    ; //22895	~	22934
+	64: R_CAL<= 		  9			    ; //22935	~	22974
+	65: R_CAL<= 		  9			    ; //22975	~	23014
+	66: R_CAL<= 		  9			    ; //23015	~	23054
+	67: R_CAL<= 		  9			    ; //23055	~	23094
+	68: R_CAL<= 		  8			    ; //23095	~	23134
+	69: R_CAL<= 		  8			    ; //23135	~	23174
+	70: R_CAL<= 		  8			    ; //23175	~	23214
+	71: R_CAL<= 		  8				 ; //23215	~	23254
+	72: R_CAL<= 		  8				; //23255	~	23294
+	73: R_CAL<= 		  7				; //23295	~	23334
+	74: R_CAL<= 		  7				; //23335	~	23374
+	75: R_CAL<= 		  7				; //23375	~	23414
+	76: R_CAL<= 		  7				; //23415	~	23454
+	77: R_CAL<= 		  7				; //23455	~	23494
+	78: R_CAL<= 		  7				; //23495	~	23534
+	79: R_CAL<= 		  7				; //23535	~	23574
+	80: R_CAL<= 		  7				; //23575	~	23614
+	81: R_CAL<= 		  7				; //23615	~	23654
+	82: R_CAL<= 		  7				; //23655	~	23694
+	83: R_CAL<= 		  7				; //23695	~	23734
+	84: R_CAL<= 		  7			    ; //23735	~	23774
+	85: R_CAL<= 		  7			    ; //23775	~	23814
+	86: R_CAL<= 		  7			    ; //23815	~	23854
+	87: R_CAL<= 		  7			    ; //23855	~	23875
+	default:R_CAL<=R_CAL;
+	endcase
+	end
+end
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+endmodule

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/R_CAL_4.v

@@ -0,0 +1,349 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    17:05:24 04/08/2022 
+// Design Name: 
+// Module Name:    R_CAL 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module R_CAL_4(
+input 				i_clk       ,
+input 				i_rstn      ,
+input signed[7:0]	i_temp		,
+input 		[15:0]	fre_mode		,
+output reg[3:0]		R_CAL
+
+    );
+
+
+//接收通道4               
+always@(posedge i_clk,negedge i_rstn)begin	//1dB 步进
+	if(!i_rstn)
+		R_CAL<='d0;
+	else if(i_temp>=8'sd70)begin//高温校准接收通道4
+	case(fre_mode)
+	0 : R_CAL<= 		   7	; //20375	~	20414
+	1 : R_CAL<= 		   7	; //20415	~	20454
+	2 : R_CAL<= 		   7	; //20455	~	20494
+	3 : R_CAL<= 		   7	; //20495	~	20534
+	4 : R_CAL<= 		   7	; //20535	~	20574
+	5 : R_CAL<= 		   7	; //20575	~	20614
+	6 : R_CAL<= 		   7	; //20615	~	20654
+	7 : R_CAL<= 		   7	; //20655	~	20694
+	8 : R_CAL<= 		   7	; //20695	~	20734
+	9 : R_CAL<= 		   7	; //20735	~	20774
+	10: R_CAL<= 		   7	; //20775	~	20814
+	11: R_CAL<= 		   7	; //20815	~	20854
+	12: R_CAL<= 		   7	; //20855	~	20894
+	13: R_CAL<= 		   7	; //20895	~	20934
+	14: R_CAL<= 		   7	; //20935	~	20974
+	15: R_CAL<= 		   7	; //20975	~	21014
+	16: R_CAL<= 		   7	; //21015	~	21054
+	17: R_CAL<= 		   7	; //21055	~	21094
+	18: R_CAL<= 		   7	; //21095	~	21134
+	19: R_CAL<= 		   7	; //21135	~	21174
+	20: R_CAL<= 		   7	; //21175	~	21214
+	21: R_CAL<= 		   7	; //21215	~	21254
+	22: R_CAL<= 		   7	; //21255	~	21294
+	23: R_CAL<= 		   8	; //21295	~	21334
+	24: R_CAL<= 		   8	; //21335	~	21374
+	25: R_CAL<= 		   8	; //21375	~	21414
+	26: R_CAL<= 		   8	; //21415	~	21454
+	27: R_CAL<= 		   8	; //21455	~	21494
+	28: R_CAL<= 		   8	; //21495	~	21534
+	29: R_CAL<= 		   8	; //21535	~	21574
+	30: R_CAL<= 		   8	; //21575	~	21614
+	31: R_CAL<= 		   8	 ; //21615	~	21654
+	32: R_CAL<= 		   8	 ; //21655	~	21694
+	33: R_CAL<= 		   8	 ; //21695	~	21734
+	34: R_CAL<= 		   8	 ; //21735	~	21774
+	35: R_CAL<= 		   8	 ; //21775	~	21814
+	36: R_CAL<= 		   8	; //21815	~	21854
+	37: R_CAL<= 		   8	; //21855	~	21894
+	38: R_CAL<= 		   8	; //21895	~	21934
+	39: R_CAL<= 		   8	; //21935	~	21974
+	40: R_CAL<= 		   8	; //21975	~	22014
+	41: R_CAL<= 		   8	; //22015	~	22054
+	42: R_CAL<= 		   7	; //22055	~	22094
+	43: R_CAL<= 		   7	; //22095	~	22134
+	44: R_CAL<= 		   7	; //22135	~	22174
+	45: R_CAL<= 		   7	; //22175	~	22214
+	46: R_CAL<= 		   7	; //22215	~	22254
+	47: R_CAL<= 		   7	; //22255	~	22294
+	48: R_CAL<= 		   7	; //22295	~	22334
+	49: R_CAL<= 		   7	; //22335	~	22374
+	50: R_CAL<= 		   7	; //22375	~	22414
+	51: R_CAL<= 		   7	; //22415	~	22454
+	52: R_CAL<= 		   7	; //22455	~	22494
+	53: R_CAL<= 		   7    ; //22495	~	22534
+	54: R_CAL<= 		   7    ; //22535	~	22574
+	55: R_CAL<= 		   7    ; //22575	~	22614
+	56: R_CAL<= 		   7    ; //22615	~	22654
+	57: R_CAL<= 		   7    ; //22655	~	22694
+	58: R_CAL<= 		   7    ; //22695	~	22734
+	59: R_CAL<= 		   7    ; //22735	~	22774
+	60: R_CAL<= 		   8    ; //22775	~	22814
+	61: R_CAL<= 		   8    ; //22815	~	22854
+	62: R_CAL<= 		   8    ; //22855	~	22894
+	63: R_CAL<= 		   8    ; //22895	~	22934
+	64: R_CAL<= 		   8    ; //22935	~	22974
+	65: R_CAL<= 		   8    ; //22975	~	23014
+	66: R_CAL<= 		   8    ; //23015	~	23054
+	67: R_CAL<= 		   8    ; //23055	~	23094
+	68: R_CAL<= 		   8    ; //23095	~	23134
+	69: R_CAL<= 		   8    ; //23135	~	23174
+	70: R_CAL<= 		   7    ; //23175	~	23214
+	71: R_CAL<= 		   7	 ; //23215	~	23254
+	72: R_CAL<= 		   7	; //23255	~	23294
+	73: R_CAL<= 		   7	; //23295	~	23334
+	74: R_CAL<= 		   7	; //23335	~	23374
+	75: R_CAL<= 		   7	; //23375	~	23414
+	76: R_CAL<= 		   6	; //23415	~	23454
+	77: R_CAL<= 		   6	; //23455	~	23494
+	78: R_CAL<= 		   6	; //23495	~	23534
+	79: R_CAL<= 		   6	; //23535	~	23574
+	80: R_CAL<= 		   6	; //23575	~	23614
+	81: R_CAL<= 		   6	; //23615	~	23654
+	82: R_CAL<= 		   6	; //23655	~	23694
+	83: R_CAL<= 		   6	; //23695	~	23734
+	84: R_CAL<= 		   6    ; //23735	~	23774
+	85: R_CAL<= 		   6    ; //23775	~	23814
+	86: R_CAL<= 		   6    ; //23815	~	23854
+	87: R_CAL<= 		   6    ; //23855	~	23875
+	default:R_CAL<=R_CAL;
+	endcase
+	end
+
+	else if(i_temp>=8'sd0)begin//常温校准接收通道4
+	case(fre_mode)
+	0 : R_CAL<= 	 7		 ; //20375	~	20414
+	1 : R_CAL<= 	 7		 ; //20415	~	20454
+	2 : R_CAL<= 	 7		 ; //20455	~	20494
+	3 : R_CAL<= 	 7		 ; //20495	~	20534
+	4 : R_CAL<= 	 7		 ; //20535	~	20574
+	5 : R_CAL<= 	 7		 ; //20575	~	20614
+	6 : R_CAL<= 	 7		 ; //20615	~	20654
+	7 : R_CAL<= 	 7		 ; //20655	~	20694
+	8 : R_CAL<= 	 7		 ; //20695	~	20734
+	9 : R_CAL<= 	 7		 ; //20735	~	20774
+	10: R_CAL<= 	 7		 ; //20775	~	20814
+	11: R_CAL<= 	 7		 ; //20815	~	20854
+	12: R_CAL<= 	 7		 ; //20855	~	20894
+	13: R_CAL<= 	 7		 ; //20895	~	20934
+	14: R_CAL<= 	 7		 ; //20935	~	20974
+	15: R_CAL<= 	 7		 ; //20975	~	21014
+	16: R_CAL<= 	 7		 ; //21015	~	21054
+	17: R_CAL<= 	 7		 ; //21055	~	21094
+	18: R_CAL<= 	 7		 ; //21095	~	21134
+	19: R_CAL<= 	 7		 ; //21135	~	21174
+	20: R_CAL<= 	 7		 ; //21175	~	21214
+	21: R_CAL<= 	 7		 ; //21215	~	21254
+	22: R_CAL<= 	 7		 ; //21255	~	21294
+	23: R_CAL<= 	 8		 ; //21295	~	21334
+	24: R_CAL<= 	 8		 ; //21335	~	21374
+	25: R_CAL<= 	 8		 ; //21375	~	21414
+	26: R_CAL<= 	 8		 ; //21415	~	21454
+	27: R_CAL<= 	 8		 ; //21455	~	21494
+	28: R_CAL<= 	 8		 ; //21495	~	21534
+	29: R_CAL<= 	 8		 ; //21535	~	21574
+	30: R_CAL<= 	 8		 ; //21575	~	21614
+	31: R_CAL<= 	 8		  ; //21615	~	21654
+	32: R_CAL<= 	 8		  ; //21655	~	21694
+	33: R_CAL<= 	 8		  ; //21695	~	21734
+	34: R_CAL<= 	 8		  ; //21735	~	21774
+	35: R_CAL<= 	 8		  ; //21775	~	21814
+	36: R_CAL<= 	 8		 ; //21815	~	21854
+	37: R_CAL<= 	 8		 ; //21855	~	21894
+	38: R_CAL<= 	 8		 ; //21895	~	21934
+	39: R_CAL<= 	 8		 ; //21935	~	21974
+	40: R_CAL<= 	 8		 ; //21975	~	22014
+	41: R_CAL<= 	 8		 ; //22015	~	22054
+	42: R_CAL<= 	 7		 ; //22055	~	22094
+	43: R_CAL<= 	 7		 ; //22095	~	22134
+	44: R_CAL<= 	 7		 ; //22135	~	22174
+	45: R_CAL<= 	 7		 ; //22175	~	22214
+	46: R_CAL<= 	 7		 ; //22215	~	22254
+	47: R_CAL<= 	 7		 ; //22255	~	22294
+	48: R_CAL<= 	 7		 ; //22295	~	22334
+	49: R_CAL<= 	 7		 ; //22335	~	22374
+	50: R_CAL<= 	 7		 ; //22375	~	22414
+	51: R_CAL<= 	 7		 ; //22415	~	22454
+	52: R_CAL<= 	 7		 ; //22455	~	22494
+	53: R_CAL<= 	 7		   ; //22495	~	22534
+	54: R_CAL<= 	 7	   ; //22535	~	22574
+	55: R_CAL<= 	 7		   ; //22575	~	22614
+	56: R_CAL<= 	 7	   ; //22615	~	22654
+	57: R_CAL<= 	 7	   ; //22655	~	22694
+	58: R_CAL<= 	 7	   ; //22695	~	22734
+	59: R_CAL<= 	 7	   ; //22735	~	22774
+	60: R_CAL<= 	 8	   ; //22775	~	22814
+	61: R_CAL<= 	 8	   ; //22815	~	22854
+	62: R_CAL<= 	 8	   ; //22855	~	22894
+	63: R_CAL<= 	 8	   ; //22895	~	22934
+	64: R_CAL<= 	 8	   ; //22935	~	22974
+	65: R_CAL<= 	 8	   ; //22975	~	23014
+	66: R_CAL<= 	 8	   ; //23015	~	23054
+	67: R_CAL<= 	 8	   ; //23055	~	23094
+	68: R_CAL<= 	 8	   ; //23095	~	23134
+	69: R_CAL<= 	 8	   ; //23135	~	23174
+	70: R_CAL<= 	 7		   ; //23175	~	23214
+	71: R_CAL<= 	 7		  ; //23215	~	23254
+	72: R_CAL<= 	 7		 ; //23255	~	23294
+	73: R_CAL<= 	 7		 ; //23295	~	23334
+	74: R_CAL<= 	 7		 ; //23335	~	23374
+	75: R_CAL<= 	 7		 ; //23375	~	23414
+	76: R_CAL<= 	 6		 ; //23415	~	23454
+	77: R_CAL<= 	 6		 ; //23455	~	23494
+	78: R_CAL<= 	 6		 ; //23495	~	23534
+	79: R_CAL<= 	 6		 ; //23535	~	23574
+	80: R_CAL<= 	 6		 ; //23575	~	23614
+	81: R_CAL<= 	 6		 ; //23615	~	23654
+	82: R_CAL<= 	 6		 ; //23655	~	23694
+	83: R_CAL<= 	 6		 ; //23695	~	23734
+	84: R_CAL<= 	 6		   ; //23735	~	23774
+	85: R_CAL<= 	 6	   ; //23775	~	23814
+	86: R_CAL<= 	 6	   ; //23815	~	23854
+	87: R_CAL<= 	 6	   ; //23855	~	23875
+	default:R_CAL<=R_CAL;
+	endcase
+	end
+	else begin//低温校准接收通道4
+	case(fre_mode)
+	0 : R_CAL<= 		  7				; //20375	~	20414
+	1 : R_CAL<= 		  7				; //20415	~	20454
+	2 : R_CAL<= 		  7				; //20455	~	20494
+	3 : R_CAL<= 		  7				; //20495	~	20534
+	4 : R_CAL<= 		  7				; //20535	~	20574
+	5 : R_CAL<= 		  7				; //20575	~	20614
+	6 : R_CAL<= 		  7				; //20615	~	20654
+	7 : R_CAL<= 		  7				; //20655	~	20694
+	8 : R_CAL<= 		  7				; //20695	~	20734
+	9 : R_CAL<= 		  7				; //20735	~	20774
+	10: R_CAL<= 		  7				; //20775	~	20814
+	11: R_CAL<= 		  7				; //20815	~	20854
+	12: R_CAL<= 		  7				; //20855	~	20894
+	13: R_CAL<= 		  7				; //20895	~	20934
+	14: R_CAL<= 		  7				; //20935	~	20974
+	15: R_CAL<= 		  7				; //20975	~	21014
+	16: R_CAL<= 		  7				; //21015	~	21054
+	17: R_CAL<= 		  7				; //21055	~	21094
+	18: R_CAL<= 		  7				; //21095	~	21134
+	19: R_CAL<= 		  7				; //21135	~	21174
+	20: R_CAL<= 		  7				; //21175	~	21214
+	21: R_CAL<= 		  7				; //21215	~	21254
+	22: R_CAL<= 		  7				; //21255	~	21294
+	23: R_CAL<= 		  8				; //21295	~	21334
+	24: R_CAL<= 		  8				; //21335	~	21374
+	25: R_CAL<= 		  8				; //21375	~	21414
+	26: R_CAL<= 		  8				; //21415	~	21454
+	27: R_CAL<= 		  8				; //21455	~	21494
+	28: R_CAL<= 		  8				; //21495	~	21534
+	29: R_CAL<= 		  8				; //21535	~	21574
+	30: R_CAL<= 		  8				; //21575	~	21614
+	31: R_CAL<= 		  8				 ; //21615	~	21654
+	32: R_CAL<= 		  8				 ; //21655	~	21694
+	33: R_CAL<= 		  8				 ; //21695	~	21734
+	34: R_CAL<= 		  8				 ; //21735	~	21774
+	35: R_CAL<= 		  8				 ; //21775	~	21814
+	36: R_CAL<= 		  8				; //21815	~	21854
+	37: R_CAL<= 		  8				; //21855	~	21894
+	38: R_CAL<= 		  8				; //21895	~	21934
+	39: R_CAL<= 		  8				; //21935	~	21974
+	40: R_CAL<= 		  8				; //21975	~	22014
+	41: R_CAL<= 		  8				; //22015	~	22054
+	42: R_CAL<= 		  7				; //22055	~	22094
+	43: R_CAL<= 		  7				; //22095	~	22134
+	44: R_CAL<= 		  7				; //22135	~	22174
+	45: R_CAL<= 		  7				; //22175	~	22214
+	46: R_CAL<= 		  7				; //22215	~	22254
+	47: R_CAL<= 		  7				; //22255	~	22294
+	48: R_CAL<= 		  7				; //22295	~	22334
+	49: R_CAL<= 		  7				; //22335	~	22374
+	50: R_CAL<= 		  7				; //22375	~	22414
+	51: R_CAL<= 		  7				; //22415	~	22454
+	52: R_CAL<= 		  7				; //22455	~	22494
+	53: R_CAL<= 		  7			    ; //22495	~	22534
+	54: R_CAL<= 		  7			    ; //22535	~	22574
+	55: R_CAL<= 		  7			    ; //22575	~	22614
+	56: R_CAL<= 		  7			    ; //22615	~	22654
+	57: R_CAL<= 		  7			    ; //22655	~	22694
+	58: R_CAL<= 		  7			    ; //22695	~	22734
+	59: R_CAL<= 		  7			    ; //22735	~	22774
+	60: R_CAL<= 		  8			    ; //22775	~	22814
+	61: R_CAL<= 		  8			    ; //22815	~	22854
+	62: R_CAL<= 		  8			    ; //22855	~	22894
+	63: R_CAL<= 		  8			    ; //22895	~	22934
+	64: R_CAL<= 		  8			    ; //22935	~	22974
+	65: R_CAL<= 		  8			    ; //22975	~	23014
+	66: R_CAL<= 		  8			    ; //23015	~	23054
+	67: R_CAL<= 		  8			    ; //23055	~	23094
+	68: R_CAL<= 		  8			    ; //23095	~	23134
+	69: R_CAL<= 		  8			    ; //23135	~	23174
+	70: R_CAL<= 		  7			    ; //23175	~	23214
+	71: R_CAL<= 		  7				 ; //23215	~	23254
+	72: R_CAL<= 		  7				; //23255	~	23294
+	73: R_CAL<= 		  7				; //23295	~	23334
+	74: R_CAL<= 		  7				; //23335	~	23374
+	75: R_CAL<= 		  7				; //23375	~	23414
+	76: R_CAL<= 		  6				; //23415	~	23454
+	77: R_CAL<= 		  6				; //23455	~	23494
+	78: R_CAL<= 		  6				; //23495	~	23534
+	79: R_CAL<= 		  6				; //23535	~	23574
+	80: R_CAL<= 		  6				; //23575	~	23614
+	81: R_CAL<= 		  6				; //23615	~	23654
+	82: R_CAL<= 		  6				; //23655	~	23694
+	83: R_CAL<= 		  6				; //23695	~	23734
+	84: R_CAL<= 		  6			    ; //23735	~	23774
+	85: R_CAL<= 		  6			    ; //23775	~	23814
+	86: R_CAL<= 		  6			    ; //23815	~	23854
+	87: R_CAL<= 		  6			    ; //23855	~	23875
+	default:R_CAL<=R_CAL;
+	endcase
+	end
+end
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+endmodule

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/Sisyif.v

@@ -0,0 +1,301 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: Chengdu Tiger
+// Engineer: Tangxy
+// 
+// Create Date:    14:14:49 09/06/2021 
+// Design Name: 
+// Module Name:    top 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module Sisyif(
+input	clk_40m         ,
+input	clk_20m         ,
+input	rst_n           ,
+//调零至信处接口
+input	SPI_CLK_F		,//SPI控制，时钟暂定50MHz，用来发送跳频频点、发射MGC值、接收MGC值
+input	SPI_SYN_F		,//片选
+input	SPI_MOSI_F		,
+output	SPI_MISO_F		,
+input	TP_EN_F			,//跳频使能控制(上升沿更新)
+input	TR_MGC_F		,//接收发射MGC使能控制(上升沿更新)
+input	CAL_F			,//校准MGC使能(上升沿更新)
+input	PRF				,//高发低收，默认接收
+
+//信处至射频接口
+output	standby          ,//高开低待机，默认待机
+output	SW_PLL           ,//乒乓频率源选择0：频率源A —— 1：频率源B
+output	T			     ,//发射电源控制
+output	R			     ,//接收电源控制
+output	SW_BPF		     ,//开关滤波器选择
+output	SCLK1            ,//锁相环A控制
+output	SDIO1            ,//
+output	CS1              ,//
+input	LD1              ,//
+output	SCLK2            ,//锁相环B控制
+output	SDIO2            ,//
+output	CS2              ,//
+input	LD2              ,//
+output	SCLK3            ,//点频源控制
+output	SDIO3            ,//
+output	CS3              ,//
+input	LD3              ,//
+output	TMGC_16db        ,//发射通道MGC控制,高电平衰减
+output	TMGC_8db         ,//
+output	TMGC_4db         ,//
+output	TMGC_2db         ,//
+output	TMGC_1db         ,//
+output	RMGC_16db        ,//四个接收通道MGC控制，同时控制，高电平衰减
+output	RMGC_8db         ,//
+output	RMGC_4db         ,//
+output	RMGC_2db         ,//
+output	RMGC_1db         ,//
+output	ENABLE           ,//SPI控制四个接收通道增益校准
+output	SC               ,//
+output	SD               ,//
+output	END_SYN          ,//
+input 	SDOUT            ,//
+inout 	DQ_WD            ,//温度传感器
+output 	SW_RX             //接收监测控制
+
+);
+	
+wire 			vio_rstn	;
+wire [9:0]		SYNC_OUT	;
+wire [35:0]		CONTROL0	;
+wire [35:0]		CONTROL1	;
+wire [150:0]	TRIG0		;
+	
+wire[15:0]		temp_data	;//LSB =0.625 C    
+wire[7:0]		temp		;//LSB =1°C 
+wire[11:0]		hop_fre_code;	 
+wire			adf4371_hop1 ;
+wire			adf4371_hop2 ;
+wire	[15:0]	fre_code ;
+wire	[7:0]	tx_mgc	 ;
+wire	[7:0]	rx1_mgc	 ;
+wire	[7:0]	rx2_mgc	 ;
+wire	[7:0]	rx3_mgc	 ;
+wire	[7:0]	rx4_mgc	 ;
+wire	[3:0]	cal1_mgc ;
+wire	[3:0]	cal2_mgc ;
+wire	[3:0]	cal3_mgc ;
+wire	[3:0]	cal4_mgc ;
+wire	[7:0]	tx_cal_mgc ;
+wire	[3:0]	model  	 ;
+wire	[3:0]	rf_en  	 ;
+wire	[31:0]	frame_count;
+wire	[3:0]	ceshi_model;
+wire	[15:0]	current_fre_code ;
+wire	[15:0]	cal_fre_code ;
+wire	[7:0]	R_MGC_1 ;
+
+wire			SW_C1;
+wire			SW;
+wire			SW2;
+wire			SW3;
+
+wire	[3:0]	R_CAL1;
+wire	[3:0]	R_CAL2;
+wire	[3:0]	R_CAL3;
+wire	[3:0]	R_CAL4;
+wire	[4:0]	T_CAL ;
+
+assign		temp		= 	temp_data[11:4]					;
+assign		RMGC_16db   =	R_MGC_1[4] 						;
+assign		RMGC_8db    =	R_MGC_1[3] 						;
+assign		RMGC_4db    =	R_MGC_1[2] 						;
+assign		RMGC_2db    =	R_MGC_1[1] 						;
+assign		RMGC_1db    =	R_MGC_1[0] 						;
+assign		standby     =	rf_en	== 4'b0  			    ;
+assign		T    	    =	PRF    							;
+assign		R    		=	~PRF   							;
+assign		SW_BPF    	=	SW_C1   						;
+assign		SW_PLL    	=	SW		    					;
+assign		SW_RX    	=	rx2_mgc == 8'b0 ? 1'b0 :1'b1 	;
+	
+ 
+spi_slave u_spi_slave (
+    .i_sys_clk(clk_40m), 
+    .i_sys_rst_n(rst_n), 
+    .i_spi_sck(SPI_CLK_F), 
+    .i_spi_cs(SPI_SYN_F), 
+    .i_spi_sdi(SPI_MOSI_F), 
+    .o_frame_count(frame_count), 
+    .o_fre_code(fre_code), 
+    .o_tx_mgc(tx_mgc), 
+    .o_model(model), 
+    .o_rf_en(rf_en), 
+    .o_cal1_mgc(cal1_mgc), 
+    .o_cal2_mgc(cal2_mgc), 
+    .o_cal3_mgc(cal3_mgc), 
+    .o_cal4_mgc(cal4_mgc), 
+    .o_tx_cal_mgc(tx_cal_mgc), 
+    .o_rx1_mgc(rx1_mgc),
+    .o_rx2_mgc(rx2_mgc),
+    .o_rx3_mgc(rx3_mgc),
+    .o_rx4_mgc(rx4_mgc),
+    .o_ceshi_model(ceshi_model)	
+    );
+	
+spi_master u_spi_master (
+.i_sys_rst_n		(rst_n)           ,
+.i_clk				(clk_40m)           ,
+//.debug_clk			(clk_80m)           ,
+.i_spi_sck			(SPI_CLK_F)       ,
+.i_spi_cs			(SPI_SYN_F)       ,
+.o_spi_sdo			(SPI_MISO_F)      ,
+.i_spi_sdi			(SPI_MOSI_F)      ,
+.i_LD_LO3			(LD3)          ,
+.i_LD1				(LD1)             ,
+.i_LD2				(LD2)             ,
+.i_cal1_mgc         (R_CAL4)      		,
+.i_cal2_mgc         (R_CAL3)      		,
+.i_cal3_mgc         (R_CAL2)      		,
+.i_cal4_mgc         (R_CAL1)      		,
+.i_temp				(temp	) ,
+.i_frame_count		(frame_count)
+ );
+
+mgc_ctrl u_mgc_ctrl(
+	.i_sys_clk			(clk_40m			),
+	.i_rst_n			(rst_n				),
+	.i_TR_SW_F			(PRF				),
+	.i_TP_EN_F			(TP_EN_F			),	
+	.i_T_MGC_EN_F		(TR_MGC_F			),	
+	.i_R_MGC_EN_F		(TR_MGC_F			),	
+	.i_CAL_F			(CAL_F				),	
+	.i_fre_code			(fre_code			),	
+	.i_tx_mgc			(tx_mgc				),
+	.i_rx1_mgc			(rx1_mgc			),
+	.i_rx2_mgc			(rx2_mgc			),
+	.i_rx3_mgc			(rx3_mgc			),
+	.i_rx4_mgc			(rx4_mgc			),
+	.i_ceshi_module		(ceshi_model		),
+	.o_current_fre_code	(current_fre_code	),	
+	.o_cal_fre_code		(cal_fre_code		),	
+	.o_hop_fre_code		(hop_fre_code		),	//0(20.375GHz)~3500(23.875GHz)
+	.o_adf4371_hop1		(adf4371_hop1		),	//high active
+	.o_adf4371_hop2		(adf4371_hop2		),
+	.o_SW				(SW					),
+	.o_SW2				(SW2				),
+	.o_SW3				(SW3				),
+	.o_SW_C1			(SW_C1				),
+	.o_T_MGC_1dB		(TMGC_1db			), 
+	.o_T_MGC_2dB		(TMGC_2db			), 
+	.o_T_MGC_4dB		(TMGC_4db			), 
+	.o_T_MGC_8dB		(TMGC_8db			), 
+	.o_T_MGC_16dB		(TMGC_16db			), 
+	.o_R_MGC_1			(R_MGC_1			) 
+	//.o_R_MGC_2		(R_MGC_2			), 
+	//.o_R_MGC_3		(R_MGC_3			), 
+	//.o_R_MGC_4		(R_MGC_4			)
+);
+ 
+wire  cfgover;
+adf4371_a u_adf4371_a (
+    .sysclk		(clk_40m 	 ),  
+    .arstn 		(rst_n&vio_rstn	), 
+    .cs			(CS1	 	 ), 
+    .mux_out	(LD1	 	 ), 
+    .sclk		(SCLK1	 	 ), 
+    .sdio		(SDIO1	 	 ),  
+    .rf_en		(rf_en	 	 ), 
+    .SW_PLL		(SW_PLL	 	 ), 
+    .CAL_F		(CAL_F	 	 ), 
+    .o_cfgover	(cfgover	 ), 
+    .ceshi_model(ceshi_model ), 
+    .adf4371_hop(adf4371_hop1), 
+    .fre_code	(hop_fre_code)
+    );
+	
+adf4371_b u_adf4371_b (
+    .sysclk		(clk_40m	 ),  
+    .arstn		(rst_n&vio_rstn),
+    .cs			(CS2		 ), 
+    .mux_out	(LD2		 ), 
+    .sclk		(SCLK2		 ), 
+    .sdio		(SDIO2		 ), 
+    .rf_en		(rf_en	 	 ), 
+    .SW_PLL		(SW_PLL		 ), 
+    .CAL_F		(CAL_F	 	 ), 
+    .i_cfgover	(cfgover	 ), 
+    .ceshi_model(ceshi_model ), 
+    .adf4371_hop(adf4371_hop2), 
+    .fre_code	(hop_fre_code)
+    );
+
+fre_caliatt u_fre_caliatt (
+    .i_clk			(clk_40m			), 
+    .i_rstn			(rst_n				), 
+    .ENABLE   		(ENABLE   			), 
+    .SC       		(SC       			), 
+    .SD       		(SD       			), 
+    .END_SYN  		(END_SYN  			), 
+    .SDOUT    		(SDOUT    			), 
+    .CAL_F    		(CAL_F				), 
+    .i_temp			(temp				), 
+    .i_fre_mode 	(current_fre_code	),
+    .i_cal_fre_code (cal_fre_code		),
+   // .SYNC_OUT		(SYNC_OUT			), 
+    .SW				(SW					), 
+	.cal1_mgc   	(cal1_mgc			),
+	.cal2_mgc   	(cal2_mgc			),
+	.cal3_mgc   	(cal3_mgc			),
+	.cal4_mgc   	(cal4_mgc			),
+	.tx_cal_mgc  	(tx_cal_mgc			),
+	.tx_mgc   		(tx_mgc				),
+	.i_ceshi_module	(ceshi_model		),
+    .R_CAL1			(R_CAL1				), 
+    .R_CAL2			(R_CAL2				), 
+    .R_CAL3			(R_CAL3				), 
+    .R_CAL4			(R_CAL4				), 
+    .T_CAL 			(T_CAL 				)
+    ); 
+
+
+adf4351_2 u_adf4351 (
+    .i_sysclk(clk_20m), 
+    .i_arstn(rst_n),  
+    .o_ADF4351_SCK(SCLK3), 
+    .o_ADF4351_DATA(SDIO3), 
+    .o_ADF4351_LE(CS3), 
+    .i_ADF4351_locked(LD3)
+    );
+
+	
+ ds18b20_temp u_temp (
+    .clk(clk_40m), 
+    .rstn(rst_n), 
+    .dq(DQ_WD), 
+    .temp_data(temp_data)
+    );
+
+
+
+		
+
+
+assign		vio_rstn	= 	1'b1;
+	  
+				  
+					  
+			  
+					  
+					  
+					  
+					  
+					  
+					  
+
+ endmodule

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/T_CAL.v

@@ -0,0 +1,631 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    17:05:24 04/08/2022 
+// Design Name: 
+// Module Name:    T_CAL_ 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module T_CAL(
+input 				i_clk       ,
+input 				i_rstn      ,
+input 				SW      ,
+input signed[7:0]	i_temp		,
+input 		[31:0]	hop_fre_mode		,
+output reg[4:0]		T_CAL_
+
+    );
+
+
+
+//发射通道
+always@(posedge i_clk,negedge i_rstn)begin//1dB 步进
+	if(!i_rstn)
+		T_CAL_<='d0;
+	else if(SW==1'b1)//B环校准值
+	begin
+		if(i_temp>=8'sd70)//B环高温校准值
+		begin
+			 if(hop_fre_mode<=20414)	T_CAL_<= 14  ;	
+		else if(hop_fre_mode<=20454)	T_CAL_<= 14  ;	                           
+		else if(hop_fre_mode<=20494)	T_CAL_<= 14  ;	                           
+		else if(hop_fre_mode<=20534)	T_CAL_<= 14  ;	                           
+		else if(hop_fre_mode<=20574)	T_CAL_<= 15  ;	                           
+		else if(hop_fre_mode<=20614)	T_CAL_<= 15  ;	                           
+		else if(hop_fre_mode<=20654)	T_CAL_<= 15  ;	                           
+		else if(hop_fre_mode<=20694)	T_CAL_<= 15  ;	                           
+		else if(hop_fre_mode<=20734)	T_CAL_<= 15  ;	                           
+		else if(hop_fre_mode<=20774)	T_CAL_<= 16  ;	                           
+		else if(hop_fre_mode<=20814)	T_CAL_<= 16  ;	                           
+		else if(hop_fre_mode<=20854)	T_CAL_<= 16  ;	                           
+		else if(hop_fre_mode<=20894)	T_CAL_<= 16  ;	                           
+		else if(hop_fre_mode<=20934)	T_CAL_<= 16  ;	                           
+		else if(hop_fre_mode<=20974)	T_CAL_<= 16  ;	                           
+		else if(hop_fre_mode<=21014)	T_CAL_<= 16  ;	                           
+		else if(hop_fre_mode<=21054)	T_CAL_<= 16  ;	                           
+		else if(hop_fre_mode<=21094)	T_CAL_<= 15  ;	                           
+		else if(hop_fre_mode<=21134)	T_CAL_<= 14  ;	                           
+		else if(hop_fre_mode<=21174)	T_CAL_<= 14  ;	                           
+		else if(hop_fre_mode<=21214)	T_CAL_<= 13  ;	                           
+		else if(hop_fre_mode<=21254)	T_CAL_<= 13  ;	                           
+		else if(hop_fre_mode<=21294)	T_CAL_<= 13  ;	                           
+		else if(hop_fre_mode<=21334)	T_CAL_<= 13  ;	                           
+		else if(hop_fre_mode<=21374)	T_CAL_<= 14  ;	                           
+		else if(hop_fre_mode<=21414)	T_CAL_<= 14  ;	                           
+		else if(hop_fre_mode<=21454)	T_CAL_<= 15  ;	                           
+		else if(hop_fre_mode<=21494)	T_CAL_<= 15  ;	                           
+		else if(hop_fre_mode<=21534)	T_CAL_<= 15  ;	                           
+		else if(hop_fre_mode<=21574)	T_CAL_<= 15  ;	                           
+		else if(hop_fre_mode<=21614)	T_CAL_<= 15  ;	                           
+		else if(hop_fre_mode<=21654)	T_CAL_<= 15  ;	                           
+		else if(hop_fre_mode<=21694)	T_CAL_<= 15  ;	                           
+		else if(hop_fre_mode<=21734)	T_CAL_<= 14  ;	                           
+		else if(hop_fre_mode<=21774)	T_CAL_<= 14  ;	                           
+		else if(hop_fre_mode<=21814)	T_CAL_<= 13  ;	                           
+		else if(hop_fre_mode<=21854)	T_CAL_<= 13  ;	                           
+		else if(hop_fre_mode<=21875)	T_CAL_<= 13  ;
+		else if(hop_fre_mode<=21894)	T_CAL_<= 11  ;		//21894                    
+		else if(hop_fre_mode<=21934)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=21974)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22014)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22054)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22094)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22134)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22174)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22214)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22254)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22294)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22334)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22374)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22414)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22454)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22494)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22534)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22574)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22614)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22654)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22694)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22734)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22774)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22814)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22854)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22894)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22934)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22974)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=23014)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=23054)	T_CAL_<= 10  ;	                           
+		else if(hop_fre_mode<=23094)	T_CAL_<= 10  ;	                           
+		else if(hop_fre_mode<=23134)	T_CAL_<= 10  ;	                           
+		else if(hop_fre_mode<=23174)	T_CAL_<= 10  ;	                           
+		else if(hop_fre_mode<=23214)	T_CAL_<= 10  ;	                           
+		else if(hop_fre_mode<=23254)	T_CAL_<= 10  ;	                           
+		else if(hop_fre_mode<=23294)	T_CAL_<= 10  ;	                           
+		else if(hop_fre_mode<=23334)	T_CAL_<= 10  ;	                           
+		else if(hop_fre_mode<=23374)	T_CAL_<= 10  ;	                           
+		else if(hop_fre_mode<=23414)	T_CAL_<= 10  ;	                           
+		else if(hop_fre_mode<=23454)	T_CAL_<= 10  ;	                           
+		else if(hop_fre_mode<=23494)	T_CAL_<= 10  ;	                           
+		else if(hop_fre_mode<=23534)	T_CAL_<= 10  ;	                           
+		else if(hop_fre_mode<=23574)	T_CAL_<= 10  ;	                           
+		else if(hop_fre_mode<=23614)	T_CAL_<= 9  ;	                           
+		else if(hop_fre_mode<=23654)	T_CAL_<= 9  ;	                           
+		else if(hop_fre_mode<=23694)	T_CAL_<= 9  ;	                           
+		else if(hop_fre_mode<=23734)	T_CAL_<= 9  ;	                          
+		else if(hop_fre_mode<=23774)	T_CAL_<= 9  ;                             
+		else if(hop_fre_mode<=23814)	T_CAL_<= 9  ;  	                           
+		else if(hop_fre_mode<=23854)	T_CAL_<= 9  ;                            
+		else if(hop_fre_mode<=23875)	T_CAL_<= 9  ;			                   
+		end                            
+
+        else if(i_temp>=8'sd0)//B环常温校准值
+		begin
+			 if(hop_fre_mode<=20414)	T_CAL_<= 14  ;	
+		else if(hop_fre_mode<=20454)	T_CAL_<= 14  ;	                           
+		else if(hop_fre_mode<=20494)	T_CAL_<= 14  ;	                           
+		else if(hop_fre_mode<=20534)	T_CAL_<= 14  ;	                           
+		else if(hop_fre_mode<=20574)	T_CAL_<= 15  ;	                           
+		else if(hop_fre_mode<=20614)	T_CAL_<= 15  ;	                           
+		else if(hop_fre_mode<=20654)	T_CAL_<= 15  ;	                           
+		else if(hop_fre_mode<=20694)	T_CAL_<= 15  ;	                           
+		else if(hop_fre_mode<=20734)	T_CAL_<= 15  ;	                           
+		else if(hop_fre_mode<=20774)	T_CAL_<= 16  ;	                           
+		else if(hop_fre_mode<=20814)	T_CAL_<= 16  ;	                           
+		else if(hop_fre_mode<=20854)	T_CAL_<= 16  ;	                           
+		else if(hop_fre_mode<=20894)	T_CAL_<= 16  ;	                           
+		else if(hop_fre_mode<=20934)	T_CAL_<= 16  ;	                           
+		else if(hop_fre_mode<=20974)	T_CAL_<= 16  ;	                           
+		else if(hop_fre_mode<=21014)	T_CAL_<= 16  ;	                           
+		else if(hop_fre_mode<=21054)	T_CAL_<= 16  ;	                           
+		else if(hop_fre_mode<=21094)	T_CAL_<= 15  ;	                           
+		else if(hop_fre_mode<=21134)	T_CAL_<= 14  ;	                           
+		else if(hop_fre_mode<=21174)	T_CAL_<= 14  ;	                           
+		else if(hop_fre_mode<=21214)	T_CAL_<= 13  ;	                           
+		else if(hop_fre_mode<=21254)	T_CAL_<= 13  ;	                           
+		else if(hop_fre_mode<=21294)	T_CAL_<= 13  ;	                           
+		else if(hop_fre_mode<=21334)	T_CAL_<= 13  ;	                           
+		else if(hop_fre_mode<=21374)	T_CAL_<= 14  ;	                           
+		else if(hop_fre_mode<=21414)	T_CAL_<= 14  ;	                           
+		else if(hop_fre_mode<=21454)	T_CAL_<= 15  ;	                           
+		else if(hop_fre_mode<=21494)	T_CAL_<= 15  ;	                           
+		else if(hop_fre_mode<=21534)	T_CAL_<= 15  ;	                           
+		else if(hop_fre_mode<=21574)	T_CAL_<= 15  ;	                           
+		else if(hop_fre_mode<=21614)	T_CAL_<= 15  ;	                           
+		else if(hop_fre_mode<=21654)	T_CAL_<= 15  ;	                           
+		else if(hop_fre_mode<=21694)	T_CAL_<= 15  ;	                           
+		else if(hop_fre_mode<=21734)	T_CAL_<= 14  ;	                           
+		else if(hop_fre_mode<=21774)	T_CAL_<= 14  ;	                           
+		else if(hop_fre_mode<=21814)	T_CAL_<= 13  ;	                           
+		else if(hop_fre_mode<=21854)	T_CAL_<= 13  ;	                           
+		else if(hop_fre_mode<=21875)	T_CAL_<= 13  ;
+		else if(hop_fre_mode<=21894)	T_CAL_<= 11  ;		//21894                    
+		else if(hop_fre_mode<=21934)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=21974)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22014)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22054)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22094)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22134)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22174)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22214)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22254)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22294)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22334)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22374)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22414)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22454)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22494)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22534)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22574)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22614)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22654)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22694)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22734)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22774)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22814)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22854)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22894)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22934)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=22974)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=23014)	T_CAL_<= 11  ;	                           
+		else if(hop_fre_mode<=23054)	T_CAL_<= 10  ;	                           
+		else if(hop_fre_mode<=23094)	T_CAL_<= 10  ;	                           
+		else if(hop_fre_mode<=23134)	T_CAL_<= 10  ;	                           
+		else if(hop_fre_mode<=23174)	T_CAL_<= 10  ;	                           
+		else if(hop_fre_mode<=23214)	T_CAL_<= 10  ;	                           
+		else if(hop_fre_mode<=23254)	T_CAL_<= 10  ;	                           
+		else if(hop_fre_mode<=23294)	T_CAL_<= 10  ;	                           
+		else if(hop_fre_mode<=23334)	T_CAL_<= 10  ;	                           
+		else if(hop_fre_mode<=23374)	T_CAL_<= 10  ;	                           
+		else if(hop_fre_mode<=23414)	T_CAL_<= 10  ;	                           
+		else if(hop_fre_mode<=23454)	T_CAL_<= 10  ;	                           
+		else if(hop_fre_mode<=23494)	T_CAL_<= 10  ;	                           
+		else if(hop_fre_mode<=23534)	T_CAL_<= 10  ;	                           
+		else if(hop_fre_mode<=23574)	T_CAL_<= 10  ;	                           
+		else if(hop_fre_mode<=23614)	T_CAL_<= 9   ;	                           
+		else if(hop_fre_mode<=23654)	T_CAL_<= 9   ;	                           
+		else if(hop_fre_mode<=23694)	T_CAL_<= 9   ;	                           
+		else if(hop_fre_mode<=23734)	T_CAL_<= 9   ;	                          
+		else if(hop_fre_mode<=23774)	T_CAL_<= 9   ;                             
+		else if(hop_fre_mode<=23814)	T_CAL_<= 9   ;  	                           
+		else if(hop_fre_mode<=23854)	T_CAL_<= 9   ;                            
+		else if(hop_fre_mode<=23875)	T_CAL_<= 9   ;			                   
+		end                                                                            
+		
+		else	//B环低温校准值
+		begin
+			 if(hop_fre_mode<=20414)	T_CAL_<= 14    ;	
+		else if(hop_fre_mode<=20454)	T_CAL_<= 14    ;	                           
+		else if(hop_fre_mode<=20494)	T_CAL_<= 14    ;	                           
+		else if(hop_fre_mode<=20534)	T_CAL_<= 14    ;	                           
+		else if(hop_fre_mode<=20574)	T_CAL_<= 15    ;	                           
+		else if(hop_fre_mode<=20614)	T_CAL_<= 15    ;	                           
+		else if(hop_fre_mode<=20654)	T_CAL_<= 15    ;	                           
+		else if(hop_fre_mode<=20694)	T_CAL_<= 15    ;	                           
+		else if(hop_fre_mode<=20734)	T_CAL_<= 15    ;	                           
+		else if(hop_fre_mode<=20774)	T_CAL_<= 16    ;	                           
+		else if(hop_fre_mode<=20814)	T_CAL_<= 16    ;	                           
+		else if(hop_fre_mode<=20854)	T_CAL_<= 16    ;	                           
+		else if(hop_fre_mode<=20894)	T_CAL_<= 16    ;	                           
+		else if(hop_fre_mode<=20934)	T_CAL_<= 16    ;	                           
+		else if(hop_fre_mode<=20974)	T_CAL_<= 16    ;	                           
+		else if(hop_fre_mode<=21014)	T_CAL_<= 16    ;	                           
+		else if(hop_fre_mode<=21054)	T_CAL_<= 16    ;	                           
+		else if(hop_fre_mode<=21094)	T_CAL_<= 15    ;	                           
+		else if(hop_fre_mode<=21134)	T_CAL_<= 14    ;	                           
+		else if(hop_fre_mode<=21174)	T_CAL_<= 14    ;	                           
+		else if(hop_fre_mode<=21214)	T_CAL_<= 13    ;	                           
+		else if(hop_fre_mode<=21254)	T_CAL_<= 13    ;	                           
+		else if(hop_fre_mode<=21294)	T_CAL_<= 13    ;	                           
+		else if(hop_fre_mode<=21334)	T_CAL_<= 13    ;	                           
+		else if(hop_fre_mode<=21374)	T_CAL_<= 14    ;	                           
+		else if(hop_fre_mode<=21414)	T_CAL_<= 14    ;	                           
+		else if(hop_fre_mode<=21454)	T_CAL_<= 15    ;	                           
+		else if(hop_fre_mode<=21494)	T_CAL_<= 15    ;	                           
+		else if(hop_fre_mode<=21534)	T_CAL_<= 15    ;	                           
+		else if(hop_fre_mode<=21574)	T_CAL_<= 15    ;	                           
+		else if(hop_fre_mode<=21614)	T_CAL_<= 15    ;	                           
+		else if(hop_fre_mode<=21654)	T_CAL_<= 15    ;	                           
+		else if(hop_fre_mode<=21694)	T_CAL_<= 15    ;	                           
+		else if(hop_fre_mode<=21734)	T_CAL_<= 14    ;	                           
+		else if(hop_fre_mode<=21774)	T_CAL_<= 14    ;	                           
+		else if(hop_fre_mode<=21814)	T_CAL_<= 13    ;	                           
+		else if(hop_fre_mode<=21854)	T_CAL_<= 13    ;	                           
+		else if(hop_fre_mode<=21875)	T_CAL_<= 13    ;
+		else if(hop_fre_mode<=21894)	T_CAL_<= 11    ;		//21894                    
+		else if(hop_fre_mode<=21934)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=21974)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22014)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22054)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22094)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22134)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22174)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22214)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22254)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22294)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22334)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22374)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22414)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22454)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22494)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22534)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22574)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22614)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22654)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22694)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22734)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22774)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22814)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22854)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22894)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22934)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22974)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=23014)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=23054)	T_CAL_<= 10    ;	                           
+		else if(hop_fre_mode<=23094)	T_CAL_<= 10    ;	                           
+		else if(hop_fre_mode<=23134)	T_CAL_<= 10    ;	                           
+		else if(hop_fre_mode<=23174)	T_CAL_<= 10    ;	                           
+		else if(hop_fre_mode<=23214)	T_CAL_<= 10    ;	                           
+		else if(hop_fre_mode<=23254)	T_CAL_<= 10    ;	                           
+		else if(hop_fre_mode<=23294)	T_CAL_<= 10    ;	                           
+		else if(hop_fre_mode<=23334)	T_CAL_<= 10    ;	                           
+		else if(hop_fre_mode<=23374)	T_CAL_<= 10    ;	                           
+		else if(hop_fre_mode<=23414)	T_CAL_<= 10    ;	                           
+		else if(hop_fre_mode<=23454)	T_CAL_<= 10    ;	                           
+		else if(hop_fre_mode<=23494)	T_CAL_<= 10    ;	                           
+		else if(hop_fre_mode<=23534)	T_CAL_<= 10    ;	                           
+		else if(hop_fre_mode<=23574)	T_CAL_<= 10    ;	                           
+		else if(hop_fre_mode<=23614)	T_CAL_<= 9     ;	                           
+		else if(hop_fre_mode<=23654)	T_CAL_<= 9     ;	                           
+		else if(hop_fre_mode<=23694)	T_CAL_<= 9     ;	                           
+		else if(hop_fre_mode<=23734)	T_CAL_<= 9     ;	                          
+		else if(hop_fre_mode<=23774)	T_CAL_<= 9     ;                             
+		else if(hop_fre_mode<=23814)	T_CAL_<= 9     ;  	                           
+		else if(hop_fre_mode<=23854)	T_CAL_<= 9     ;                            
+		else if(hop_fre_mode<=23875)	T_CAL_<= 9     ;			                   
+		end                            
+	end	
+	else	//A环校准值
+	begin
+		if(i_temp>=8'sd70)//A环高温校准值
+		begin
+			 if(hop_fre_mode<=20414)	T_CAL_<= 14   ;	
+		else if(hop_fre_mode<=20454)	T_CAL_<= 14   ;	                           
+		else if(hop_fre_mode<=20494)	T_CAL_<= 14   ;	                           
+		else if(hop_fre_mode<=20534)	T_CAL_<= 14   ;	                           
+		else if(hop_fre_mode<=20574)	T_CAL_<= 15   ;	                           
+		else if(hop_fre_mode<=20614)	T_CAL_<= 15   ;	                           
+		else if(hop_fre_mode<=20654)	T_CAL_<= 15   ;	                           
+		else if(hop_fre_mode<=20694)	T_CAL_<= 15   ;	                           
+		else if(hop_fre_mode<=20734)	T_CAL_<= 15   ;	                           
+		else if(hop_fre_mode<=20774)	T_CAL_<= 16   ;	                           
+		else if(hop_fre_mode<=20814)	T_CAL_<= 16   ;	                           
+		else if(hop_fre_mode<=20854)	T_CAL_<= 16   ;	                           
+		else if(hop_fre_mode<=20894)	T_CAL_<= 16   ;	                           
+		else if(hop_fre_mode<=20934)	T_CAL_<= 16   ;	                           
+		else if(hop_fre_mode<=20974)	T_CAL_<= 16   ;	                           
+		else if(hop_fre_mode<=21014)	T_CAL_<= 16   ;	                           
+		else if(hop_fre_mode<=21054)	T_CAL_<= 16   ;	                           
+		else if(hop_fre_mode<=21094)	T_CAL_<= 15   ;	                           
+		else if(hop_fre_mode<=21134)	T_CAL_<= 14   ;	                           
+		else if(hop_fre_mode<=21174)	T_CAL_<= 14   ;	                           
+		else if(hop_fre_mode<=21214)	T_CAL_<= 13   ;	                           
+		else if(hop_fre_mode<=21254)	T_CAL_<= 13   ;	                           
+		else if(hop_fre_mode<=21294)	T_CAL_<= 13   ;	                           
+		else if(hop_fre_mode<=21334)	T_CAL_<= 13   ;	                           
+		else if(hop_fre_mode<=21374)	T_CAL_<= 14   ;	                           
+		else if(hop_fre_mode<=21414)	T_CAL_<= 14   ;	                           
+		else if(hop_fre_mode<=21454)	T_CAL_<= 15   ;	                           
+		else if(hop_fre_mode<=21494)	T_CAL_<= 15   ;	                           
+		else if(hop_fre_mode<=21534)	T_CAL_<= 15   ;	                           
+		else if(hop_fre_mode<=21574)	T_CAL_<= 15   ;	                           
+		else if(hop_fre_mode<=21614)	T_CAL_<= 15   ;	                           
+		else if(hop_fre_mode<=21654)	T_CAL_<= 15   ;	                           
+		else if(hop_fre_mode<=21694)	T_CAL_<= 15   ;	                           
+		else if(hop_fre_mode<=21734)	T_CAL_<= 14   ;	                           
+		else if(hop_fre_mode<=21774)	T_CAL_<= 14   ;	                           
+		else if(hop_fre_mode<=21814)	T_CAL_<= 13   ;	                           
+		else if(hop_fre_mode<=21854)	T_CAL_<= 13   ;	                           
+		else if(hop_fre_mode<=21875)	T_CAL_<= 13   ;
+		else if(hop_fre_mode<=21894)	T_CAL_<= 11   ;		//21894                    
+		else if(hop_fre_mode<=21934)	T_CAL_<= 11   ;	                           
+		else if(hop_fre_mode<=21974)	T_CAL_<= 11   ;	                           
+		else if(hop_fre_mode<=22014)	T_CAL_<= 11   ;	                           
+		else if(hop_fre_mode<=22054)	T_CAL_<= 11   ;	                           
+		else if(hop_fre_mode<=22094)	T_CAL_<= 11   ;	                           
+		else if(hop_fre_mode<=22134)	T_CAL_<= 11   ;	                           
+		else if(hop_fre_mode<=22174)	T_CAL_<= 11   ;	                           
+		else if(hop_fre_mode<=22214)	T_CAL_<= 11   ;	                           
+		else if(hop_fre_mode<=22254)	T_CAL_<= 11   ;	                           
+		else if(hop_fre_mode<=22294)	T_CAL_<= 11   ;	                           
+		else if(hop_fre_mode<=22334)	T_CAL_<= 11   ;	                           
+		else if(hop_fre_mode<=22374)	T_CAL_<= 11   ;	                           
+		else if(hop_fre_mode<=22414)	T_CAL_<= 11   ;	                           
+		else if(hop_fre_mode<=22454)	T_CAL_<= 11   ;	                           
+		else if(hop_fre_mode<=22494)	T_CAL_<= 11   ;	                           
+		else if(hop_fre_mode<=22534)	T_CAL_<= 11   ;	                           
+		else if(hop_fre_mode<=22574)	T_CAL_<= 11   ;	                           
+		else if(hop_fre_mode<=22614)	T_CAL_<= 11   ;	                           
+		else if(hop_fre_mode<=22654)	T_CAL_<= 11   ;	                           
+		else if(hop_fre_mode<=22694)	T_CAL_<= 11   ;	                           
+		else if(hop_fre_mode<=22734)	T_CAL_<= 11   ;	                           
+		else if(hop_fre_mode<=22774)	T_CAL_<= 11   ;	                           
+		else if(hop_fre_mode<=22814)	T_CAL_<= 11   ;	                           
+		else if(hop_fre_mode<=22854)	T_CAL_<= 11   ;	                           
+		else if(hop_fre_mode<=22894)	T_CAL_<= 11   ;	                           
+		else if(hop_fre_mode<=22934)	T_CAL_<= 11   ;	                           
+		else if(hop_fre_mode<=22974)	T_CAL_<= 11   ;	                           
+		else if(hop_fre_mode<=23014)	T_CAL_<= 11   ;	                           
+		else if(hop_fre_mode<=23054)	T_CAL_<= 10   ;	                           
+		else if(hop_fre_mode<=23094)	T_CAL_<= 10   ;	                           
+		else if(hop_fre_mode<=23134)	T_CAL_<= 10   ;	                           
+		else if(hop_fre_mode<=23174)	T_CAL_<= 10   ;	                           
+		else if(hop_fre_mode<=23214)	T_CAL_<= 10   ;	                           
+		else if(hop_fre_mode<=23254)	T_CAL_<= 10   ;	                           
+		else if(hop_fre_mode<=23294)	T_CAL_<= 10   ;	                           
+		else if(hop_fre_mode<=23334)	T_CAL_<= 10   ;	                           
+		else if(hop_fre_mode<=23374)	T_CAL_<= 10   ;	                           
+		else if(hop_fre_mode<=23414)	T_CAL_<= 10   ;	                           
+		else if(hop_fre_mode<=23454)	T_CAL_<= 10   ;	                           
+		else if(hop_fre_mode<=23494)	T_CAL_<= 10   ;	                           
+		else if(hop_fre_mode<=23534)	T_CAL_<= 10   ;	                           
+		else if(hop_fre_mode<=23574)	T_CAL_<= 10   ;	                           
+		else if(hop_fre_mode<=23614)	T_CAL_<= 9    ;	                           
+		else if(hop_fre_mode<=23654)	T_CAL_<= 9    ;	                           
+		else if(hop_fre_mode<=23694)	T_CAL_<= 9    ;	                           
+		else if(hop_fre_mode<=23734)	T_CAL_<= 9    ;	                          
+		else if(hop_fre_mode<=23774)	T_CAL_<= 9    ;                             
+		else if(hop_fre_mode<=23814)	T_CAL_<= 9    ;  	                           
+		else if(hop_fre_mode<=23854)	T_CAL_<= 9    ;                            
+		else if(hop_fre_mode<=23875)	T_CAL_<= 9    ;			                   
+		end                            
+		
+		else if(i_temp>=8'sd0)//A环常温校准值
+		begin
+			 if(hop_fre_mode<=20414)	T_CAL_<=    14   ; //20375	~	20414
+		else if(hop_fre_mode<=20454)	T_CAL_<=    14   ; //20415	~	20454
+		else if(hop_fre_mode<=20494)	T_CAL_<=    14   ; //20455	~	20494
+		else if(hop_fre_mode<=20534)	T_CAL_<=    14   ; //20495	~	20534
+		else if(hop_fre_mode<=20574)	T_CAL_<=    15   ; //20535	~	20574
+		else if(hop_fre_mode<=20614)	T_CAL_<=    15   ; //20575	~	20614
+		else if(hop_fre_mode<=20654)	T_CAL_<=    15   ; //20615	~	20654
+		else if(hop_fre_mode<=20694)	T_CAL_<=    15   ; //20655	~	20694
+		else if(hop_fre_mode<=20734)	T_CAL_<=    15   ; //20695	~	20734
+		else if(hop_fre_mode<=20774)	T_CAL_<=    16   ; //20735	~	20774
+		else if(hop_fre_mode<=20814)	T_CAL_<=    16   ; //20775	~	20814
+		else if(hop_fre_mode<=20854)	T_CAL_<=    16   ; //20815	~	20854
+		else if(hop_fre_mode<=20894)	T_CAL_<=    16   ; //20855	~	20894
+		else if(hop_fre_mode<=20934)	T_CAL_<=    16   ; //20895	~	20934
+		else if(hop_fre_mode<=20974)	T_CAL_<=    16   ; //20935	~	20974
+		else if(hop_fre_mode<=21014)	T_CAL_<=    16   ; //20975	~	21014
+		else if(hop_fre_mode<=21054)	T_CAL_<=    16   ; //21015	~	21054
+		else if(hop_fre_mode<=21094)	T_CAL_<=    15   ; //21055	~	21094
+		else if(hop_fre_mode<=21134)	T_CAL_<=    14   ; //21095	~	21134
+		else if(hop_fre_mode<=21174)	T_CAL_<=    14   ; //21135	~	21174
+		else if(hop_fre_mode<=21214)	T_CAL_<=    13   ; //21175	~	21214
+		else if(hop_fre_mode<=21254)	T_CAL_<=    13   ; //21215	~	21254
+		else if(hop_fre_mode<=21294)	T_CAL_<=    13   ; //21255	~	21294
+		else if(hop_fre_mode<=21334)	T_CAL_<=    13   ; //21295	~	21334
+		else if(hop_fre_mode<=21374)	T_CAL_<=    14   ; //21335	~	21374
+		else if(hop_fre_mode<=21414)	T_CAL_<=    14   ; //21375	~	21414
+		else if(hop_fre_mode<=21454)	T_CAL_<=    15   ; //21415	~	21454
+		else if(hop_fre_mode<=21494)	T_CAL_<=    15   ; //21455	~	21494
+		else if(hop_fre_mode<=21534)	T_CAL_<=    15   ; //21495	~	21534
+		else if(hop_fre_mode<=21574)	T_CAL_<=    15   ; //21535	~	21574
+		else if(hop_fre_mode<=21614)	T_CAL_<=    15   ; //21575	~	21614
+		else if(hop_fre_mode<=21654)	T_CAL_<=    15   ; //21615	~	21654
+		else if(hop_fre_mode<=21694)	T_CAL_<=    15   ; //21655	~	21694
+		else if(hop_fre_mode<=21734)	T_CAL_<=    14   ; //21695	~	21734
+		else if(hop_fre_mode<=21774)	T_CAL_<=    14   ; //21735	~	21774
+		else if(hop_fre_mode<=21814)	T_CAL_<=    13   ; //21775	~	21814
+		else if(hop_fre_mode<=21854)	T_CAL_<=    13   ; //21815	~	21854
+		else if(hop_fre_mode<=21875)	T_CAL_<=    13   ; //21855	~	21875
+		else if(hop_fre_mode<=21894)	T_CAL_<=    11   ; //21874	~	21894		
+		else if(hop_fre_mode<=21934)	T_CAL_<=    11   ; //21895	~	21934
+		else if(hop_fre_mode<=21974)	T_CAL_<=    11   ; //21935	~	21974
+		else if(hop_fre_mode<=22014)	T_CAL_<=    11   ; //21975	~	22014
+		else if(hop_fre_mode<=22054)	T_CAL_<=    11   ; //22015	~	22054
+		else if(hop_fre_mode<=22094)	T_CAL_<=    11   ; //22055	~	22094
+		else if(hop_fre_mode<=22134)	T_CAL_<=    11   ; //22095	~	22134
+		else if(hop_fre_mode<=22174)	T_CAL_<=    11   ; //22135	~	22174
+		else if(hop_fre_mode<=22214)	T_CAL_<=    11   ; //22175	~	22214
+		else if(hop_fre_mode<=22254)	T_CAL_<=    11   ; //22215	~	22254
+		else if(hop_fre_mode<=22294)	T_CAL_<=    11   ; //22255	~	22294
+		else if(hop_fre_mode<=22334)	T_CAL_<=    11   ; //22295	~	22334
+		else if(hop_fre_mode<=22374)	T_CAL_<=    11   ; //22335	~	22374
+		else if(hop_fre_mode<=22414)	T_CAL_<=    11   ; //22375	~	22414
+		else if(hop_fre_mode<=22454)	T_CAL_<=    11   ; //22415	~	22454
+		else if(hop_fre_mode<=22494)	T_CAL_<=    11   ; //22455	~	22494
+		else if(hop_fre_mode<=22534)	T_CAL_<=    11   ; //22495	~	22534
+		else if(hop_fre_mode<=22574)	T_CAL_<=    11   ; //22535	~	22574
+		else if(hop_fre_mode<=22614)	T_CAL_<=    11   ; //22575	~	22614
+		else if(hop_fre_mode<=22654)	T_CAL_<=    11   ; //22615	~	22654
+		else if(hop_fre_mode<=22694)	T_CAL_<=    11   ; //22655	~	22694
+		else if(hop_fre_mode<=22734)	T_CAL_<=    11   ; //22695	~	22734
+		else if(hop_fre_mode<=22774)	T_CAL_<=    11   ; //22735	~	22774
+		else if(hop_fre_mode<=22814)	T_CAL_<=    11   ; //22775	~	22814
+		else if(hop_fre_mode<=22854)	T_CAL_<=    11   ; //22815	~	22854
+		else if(hop_fre_mode<=22894)	T_CAL_<=    11   ; //22855	~	22894
+		else if(hop_fre_mode<=22934)	T_CAL_<=    11   ; //22895	~	22934
+		else if(hop_fre_mode<=22974)	T_CAL_<=    11   ; //22935	~	22974
+		else if(hop_fre_mode<=23014)	T_CAL_<=    11   ; //22975	~	23014
+		else if(hop_fre_mode<=23054)	T_CAL_<=    10   ; //23015	~	23054
+		else if(hop_fre_mode<=23094)	T_CAL_<=    10   ; //23055	~	23094
+		else if(hop_fre_mode<=23134)	T_CAL_<=    10   ; //23095	~	23134
+		else if(hop_fre_mode<=23174)	T_CAL_<=    10   ; //23135	~	23174
+		else if(hop_fre_mode<=23214)	T_CAL_<=    10   ; //23175	~	23214
+		else if(hop_fre_mode<=23254)	T_CAL_<=    10   ; //23215	~	23254
+		else if(hop_fre_mode<=23294)	T_CAL_<=    10   ; //23255	~	23294
+		else if(hop_fre_mode<=23334)	T_CAL_<=    10   ; //23295	~	23334
+		else if(hop_fre_mode<=23374)	T_CAL_<=    10   ; //23335	~	23374
+		else if(hop_fre_mode<=23414)	T_CAL_<=    10   ; //23375	~	23414
+		else if(hop_fre_mode<=23454)	T_CAL_<=    10   ; //23415	~	23454
+		else if(hop_fre_mode<=23494)	T_CAL_<=    10   ; //23455	~	23494
+		else if(hop_fre_mode<=23534)	T_CAL_<=    10   ; //23495	~	23534
+		else if(hop_fre_mode<=23574)	T_CAL_<=    10   ; //23535	~	23574
+		else if(hop_fre_mode<=23614)	T_CAL_<=    9    ; //23575	~	23614
+		else if(hop_fre_mode<=23654)	T_CAL_<=    9    ; //23615	~	23654
+		else if(hop_fre_mode<=23694)	T_CAL_<=    9    ; //23655	~	23694
+		else if(hop_fre_mode<=23734)	T_CAL_<=    9    ; //23695	~	23734
+		else if(hop_fre_mode<=23774)	T_CAL_<=    9    ; //23735	~	23774
+		else if(hop_fre_mode<=23814)	T_CAL_<=    9    ; //23775	~	23814
+		else if(hop_fre_mode<=23854)	T_CAL_<=    9    ; //23815	~	23854
+		else if(hop_fre_mode<=23875)	T_CAL_<=    9    ; //23855	~	23875
+		end
+		else	//A环低温校准值
+		begin
+			 if(hop_fre_mode<=20414)	T_CAL_<= 14    ;	
+		else if(hop_fre_mode<=20454)	T_CAL_<= 14    ;	                           
+		else if(hop_fre_mode<=20494)	T_CAL_<= 14    ;	                           
+		else if(hop_fre_mode<=20534)	T_CAL_<= 14    ;	                           
+		else if(hop_fre_mode<=20574)	T_CAL_<= 15    ;	                           
+		else if(hop_fre_mode<=20614)	T_CAL_<= 15    ;	                           
+		else if(hop_fre_mode<=20654)	T_CAL_<= 15    ;	                           
+		else if(hop_fre_mode<=20694)	T_CAL_<= 15    ;	                           
+		else if(hop_fre_mode<=20734)	T_CAL_<= 15    ;	                           
+		else if(hop_fre_mode<=20774)	T_CAL_<= 16    ;	                           
+		else if(hop_fre_mode<=20814)	T_CAL_<= 16    ;	                           
+		else if(hop_fre_mode<=20854)	T_CAL_<= 16    ;	                           
+		else if(hop_fre_mode<=20894)	T_CAL_<= 16    ;	                           
+		else if(hop_fre_mode<=20934)	T_CAL_<= 16    ;	                           
+		else if(hop_fre_mode<=20974)	T_CAL_<= 16    ;	                           
+		else if(hop_fre_mode<=21014)	T_CAL_<= 16    ;	                           
+		else if(hop_fre_mode<=21054)	T_CAL_<= 16    ;	                           
+		else if(hop_fre_mode<=21094)	T_CAL_<= 15    ;	                           
+		else if(hop_fre_mode<=21134)	T_CAL_<= 14    ;	                           
+		else if(hop_fre_mode<=21174)	T_CAL_<= 14    ;	                           
+		else if(hop_fre_mode<=21214)	T_CAL_<= 13    ;	                           
+		else if(hop_fre_mode<=21254)	T_CAL_<= 13    ;	                           
+		else if(hop_fre_mode<=21294)	T_CAL_<= 13    ;	                           
+		else if(hop_fre_mode<=21334)	T_CAL_<= 13    ;	                           
+		else if(hop_fre_mode<=21374)	T_CAL_<= 14    ;	                           
+		else if(hop_fre_mode<=21414)	T_CAL_<= 14    ;	                           
+		else if(hop_fre_mode<=21454)	T_CAL_<= 15    ;	                           
+		else if(hop_fre_mode<=21494)	T_CAL_<= 15    ;	                           
+		else if(hop_fre_mode<=21534)	T_CAL_<= 15    ;	                           
+		else if(hop_fre_mode<=21574)	T_CAL_<= 15    ;	                           
+		else if(hop_fre_mode<=21614)	T_CAL_<= 15    ;	                           
+		else if(hop_fre_mode<=21654)	T_CAL_<= 15    ;	                           
+		else if(hop_fre_mode<=21694)	T_CAL_<= 15    ;	                           
+		else if(hop_fre_mode<=21734)	T_CAL_<= 14    ;	                           
+		else if(hop_fre_mode<=21774)	T_CAL_<= 14    ;	                           
+		else if(hop_fre_mode<=21814)	T_CAL_<= 13    ;	                           
+		else if(hop_fre_mode<=21854)	T_CAL_<= 13    ;	                           
+		else if(hop_fre_mode<=21875)	T_CAL_<= 13    ;
+		else if(hop_fre_mode<=21894)	T_CAL_<= 11    ;		//21894                    
+		else if(hop_fre_mode<=21934)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=21974)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22014)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22054)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22094)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22134)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22174)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22214)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22254)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22294)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22334)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22374)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22414)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22454)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22494)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22534)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22574)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22614)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22654)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22694)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22734)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22774)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22814)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22854)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22894)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22934)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=22974)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=23014)	T_CAL_<= 11    ;	                           
+		else if(hop_fre_mode<=23054)	T_CAL_<= 10    ;	                           
+		else if(hop_fre_mode<=23094)	T_CAL_<= 10    ;	                           
+		else if(hop_fre_mode<=23134)	T_CAL_<= 10    ;	                           
+		else if(hop_fre_mode<=23174)	T_CAL_<= 10    ;	                           
+		else if(hop_fre_mode<=23214)	T_CAL_<= 10    ;	                           
+		else if(hop_fre_mode<=23254)	T_CAL_<= 10    ;	                           
+		else if(hop_fre_mode<=23294)	T_CAL_<= 10    ;	                           
+		else if(hop_fre_mode<=23334)	T_CAL_<= 10    ;	                           
+		else if(hop_fre_mode<=23374)	T_CAL_<= 10    ;	                           
+		else if(hop_fre_mode<=23414)	T_CAL_<= 10    ;	                           
+		else if(hop_fre_mode<=23454)	T_CAL_<= 10    ;	                           
+		else if(hop_fre_mode<=23494)	T_CAL_<= 10    ;	                           
+		else if(hop_fre_mode<=23534)	T_CAL_<= 10    ;	                           
+		else if(hop_fre_mode<=23574)	T_CAL_<= 10    ;	                           
+		else if(hop_fre_mode<=23614)	T_CAL_<= 9     ;	                           
+		else if(hop_fre_mode<=23654)	T_CAL_<= 9     ;	                           
+		else if(hop_fre_mode<=23694)	T_CAL_<= 9     ;	                           
+		else if(hop_fre_mode<=23734)	T_CAL_<= 9     ;	                          
+		else if(hop_fre_mode<=23774)	T_CAL_<= 9     ;                             
+		else if(hop_fre_mode<=23814)	T_CAL_<= 9     ;  	                           
+		else if(hop_fre_mode<=23854)	T_CAL_<= 9     ;                            
+		else if(hop_fre_mode<=23875)	T_CAL_<= 9     ;			                   
+		end                            
+	end	
+	
+end
+
+
+
+
+
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+
+
+
+
+
+
+
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+
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+
+
+
+endmodule

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/adf4371_a.v

@@ -0,0 +1,633 @@
+
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2021/8/13 00:24:20
+// Design Name: 
+// Module Name: LMX2595
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+
+// fRFOUT= (INT+ (FRAC1+FRAC2/MOD2)/MOD1)× (fPFD/R)
+// fPFD	 = fPFD = REFIN × ((1 + D)/(R × (1 + T))) 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module adf4371_a(//20.375Ghz ~ 23.875Ghz
+input               sysclk    ,//40MHZ
+input               arstn     ,
+output              cs        ,
+input               mux_out   ,
+output              sclk      ,
+output              sdio      ,    
+input [3:0]			rf_en	  , 			    
+input 				SW_PLL	  , 			    
+input 				CAL_F	  , 			    
+input [3:0]			ceshi_model	  , 			    
+input               adf4371_hop  ,    			    
+output    	       o_cfgover      ,    			    
+input[11:0]         fre_code          			    
+    );
+
+localparam      DATA_WIDTH = 24			;
+localparam      DATA_LENTH = 72		;
+localparam      WAIT_ld   = 40000		;					
+//*****************************************************************************											
+reg[7:0]                cnt_word    = 8'd0					;
+reg	    				csb_reg	    = 1'b1					;
+reg[5:0]                cnt_bits    = 6'd0					;  
+reg[DATA_WIDTH-1:0]     cfgdata     = 0,        regdata = 0	;
+reg[3:0]                state	    = 4'b000				;
+reg                     spi_sdo     = 1'b0,     spi_csb = 1'b1;
+wire                    pll_locked  						;
+reg    				   cfgover      						;    
+reg[31:0]               cnt_lock    = 32'd0					;
+reg[31:0]               cnt_locked  = 32'd0					;
+wire[15:0]              band  								;
+assign					o_cfgover	=cfgover				;
+//-----------------------------------
+assign      pll_locked		 = mux_out						;
+assign      sclk  	  		 = spi_csb ? 1'b0 : ~sysclk		;
+assign      cs     	  		 = spi_csb & csb_reg			;
+assign      sdio      		 = spi_sdo						;
+//-----------------------------------
+
+wire [7:0]	SI_BAND_SEL    ;		//VCO频段
+wire [7:0]	SI_VCO_SEL_BIAS_CODE    ; //[7:4]=VCO内核, [3:0]=VCO偏置
+reg[13:0]	MOD2		;
+reg[13:0]	FRAC2		;
+reg[24:0]	FRAC1		;
+reg[15:0]	INT			;
+
+assign		SI_BAND_SEL            =  band[15:8]   ;
+assign		SI_VCO_SEL_BIAS_CODE   =  band[7:0]  ;
+
+reg[2:0]	hop_en		;	
+reg[15:0]	code		;	
+reg[11:0]	pre_fre_code		;	
+reg[3:0]	rf_en_r		;	
+reg[2:0]	CAL_F_R		;	
+
+reg	[3:0]	R_DIV 		;
+reg	[3:0]	D	 		;
+wire[13:0]	douta3		;
+wire[13:0]	douta4		;
+wire[24:0]	douta2		;
+wire[15:0]	douta1			;
+//----------------------------------- 
+
+INT_ROMb int_rom (
+    .sysclk(sysclk), 
+    .addra(code), 
+    .douta(douta1)
+    );
+	
+// Instantiate the module
+FRAC1 frac1_rom (
+    .clka(sysclk), 
+    .addra(code), 
+    .douta(douta2)
+    );
+
+	
+// FRAC1_ROM FRAC1_ROM (
+//  .clka(sysclk), // input clka
+//  .addra(code), // input [11 : 0] addra
+//  .douta(douta2) // output [24 : 0] douta
+//); 
+	
+frac2_rom frac2_rom (
+    .sysclk(sysclk), 
+    .addra(code), 
+    .douta(douta4)
+    );
+
+mod2_rom mod2_rom (
+    .sysclk(sysclk), 
+    .addra(code), 
+    .douta(douta3)
+    );
+
+
+band_rom_a band_rom_a (
+    .sysclk(sysclk), 
+    .addra(code),
+	.douta(band) // output [15 : 0] douta
+    );	
+
+
+//-------------------整数边界杂散用66.666666Mhz鉴相----------------------------------
+always@(posedge sysclk,negedge arstn)
+begin
+	if(!arstn)
+		INT<=douta1;
+	else if(code==24 || code==26 )  
+		INT<=76;
+	else if(code==424 )  
+		INT<=77;
+	else if(code==426 )  
+		INT<=78;
+	else if(code==824 || code==826 )  
+		INT<=79;
+	else if(code==1224) 
+		INT<=80;
+	else if(code==1226 )  
+		INT<=81;
+	else if(code==1624 || code==1626 )  
+		INT<=82;
+	else if(code==2024 )  
+		INT<=83;
+	else if(code==2026 )  
+		INT<=84;	
+	else if(code==2424 || code==2426 )  
+		INT<=85;
+	else if(code==2824 )  
+		INT<=86;
+	else if( code==2826 )  
+		INT<=87;
+	else
+		INT<=douta1;	
+end
+
+always@(posedge sysclk,negedge arstn)
+begin
+	if(!arstn)
+		FRAC1<=douta2;
+	else if(code==24 )  
+		FRAC1<=16651386;
+	else if(code==26 )  
+		FRAC1<=16903045;
+	else if(code==424 )  
+		FRAC1<=33428602;
+	else if(code==426 )  
+		FRAC1<=125829;
+	else if(code==824 )  
+		FRAC1<=16651386;
+	else if(code==826 )  
+		FRAC1<=16903045;
+	else if(code==1224) 
+		FRAC1<=33428602;
+	else if(code==1226 )  
+		FRAC1<=125829;
+	else if(code==1624)  
+		FRAC1<=16651386;
+	else if(code==1626 )  
+		FRAC1<=16903045;
+	else if(code==2024 )  
+		FRAC1<=33428602;
+	else if(code==2026 )  
+		FRAC1<=125829;	
+	else if(code==2424 )  
+		FRAC1<=16651386;
+	else if(code==2426 )  
+		FRAC1<=16903045;
+	else if(code==2824 )  
+		FRAC1<=33428602;
+	else if( code==2826 )  
+		FRAC1<=125829;
+	else
+		FRAC1<=douta2;	
+end
+
+always@(posedge sysclk,negedge arstn)
+begin
+	if(!arstn)
+		MOD2<=douta3;
+	else if(code==24 )  
+		MOD2<=25;
+	else if(code==26 )  
+		MOD2<=25;
+	else if(code==424 )  
+		MOD2<=25;
+	else if(code==426 )  
+		MOD2<=25;
+	else if(code==824 )  
+		MOD2<=25;
+	else if(code==826 )  
+		MOD2<=25;
+	else if(code==1224) 
+		MOD2<=25;
+	else if(code==1226 )  
+		MOD2<=25;
+	else if(code==1624)  
+		MOD2<=25;
+	else if(code==1626 )  
+		MOD2<=25;
+	else if(code==2024 )  
+		MOD2<=25;
+	else if(code==2026 )  
+		MOD2<=25;	
+	else if(code==2424 )  
+		MOD2<=25;
+	else if(code==2426 )  
+		MOD2<=25;
+	else if(code==2824 )  
+		MOD2<=25;
+	else if( code==2826 )  
+		MOD2<=25;
+	else
+		MOD2<=douta3;	
+end
+
+always@(posedge sysclk,negedge arstn)
+begin
+	if(!arstn)
+		FRAC2<=douta4;
+	else if(code==24 )  
+		FRAC2<=22;
+	else if(code==26 )  
+		FRAC2<=3;
+	else if(code==424 )  
+		FRAC2<=22;
+	else if(code==426 )  
+		FRAC2<=3;
+	else if(code==824 )  
+		FRAC2<=22;
+	else if(code==826 )  
+		FRAC2<=3;
+	else if(code==1224) 
+		FRAC2<=22;
+	else if(code==1226 )  
+		FRAC2<=3;
+	else if(code==1624)  
+		FRAC2<=22;
+	else if(code==1626 )  
+		FRAC2<=3;
+	else if(code==2024 )  
+		FRAC2<=22;
+	else if(code==2026 )  
+		FRAC2<=3;	
+	else if(code==2424 )  
+		FRAC2<=22;
+	else if(code==2426 )  
+		FRAC2<=3;
+	else if(code==2824 )  
+		FRAC2<=22;
+	else if( code==2826 )  
+		FRAC2<=3;
+	else
+		FRAC2<=douta4;	
+end
+
+always@(posedge sysclk,negedge arstn)
+begin
+	if(!arstn)begin
+		R_DIV<=4'b1;
+		D<=4'b0;
+	end
+	else if(code==24 || code==26 ||   code==424 ||  code==426 || code==824 ||  code==826|| code==1224 ||  code==1226 || code==1624 ||  code==1626 ||code==2024 ||  code==2026 ||code==2424 ||  code==2426 ||code==2824 ||  code==2826 )
+	begin
+		R_DIV<=	4'd3;
+		D<=4'd2;
+	end
+	else
+	begin
+		R_DIV<=4'b1;
+		D<=4'b0;
+	end	
+end
+
+//----------------------------------------------------------------
+
+always@(posedge sysclk,negedge arstn)begin
+if(~arstn)
+	pre_fre_code<=11'h6d6;
+else if(CAL_F_R==3'b011)
+	pre_fre_code<=fre_code;
+else
+	pre_fre_code<=pre_fre_code;
+end
+
+
+always@(posedge sysclk,negedge arstn)begin
+if(~arstn)
+	code<=16'h0;
+else if(hop_en==2'b01)
+	code<=fre_code;
+else
+	code<=code;
+end
+
+
+always@(posedge sysclk,negedge arstn)begin
+if(~arstn)begin
+    hop_en 	<= 3'b0;
+    rf_en_r <= 4'b0;
+    CAL_F_R <= 3'b0;
+end
+else  begin
+	hop_en	<= {hop_en[1:0],adf4371_hop};
+	CAL_F_R	<= {CAL_F_R[1:0],CAL_F};
+	rf_en_r	<= rf_en	;
+end
+end
+
+
+always@(posedge sysclk,negedge arstn)begin
+if(~arstn)
+    csb_reg 	<= 1'b1;
+else  
+	csb_reg		<= spi_csb;
+end
+
+
+always@(posedge sysclk,negedge arstn)begin
+if(~arstn)	
+	cnt_locked<=32'b0;
+else if(cnt_locked==WAIT_ld)
+	cnt_locked<=32'b0;
+else if(!pll_locked)
+	cnt_locked<=cnt_locked+1'b1;
+else
+	cnt_locked<=32'b0;
+end
+
+always@(posedge sysclk,negedge arstn)begin
+if(~arstn)begin
+    cfgdata  <= 0;
+    cnt_word <= 7'd0;
+    cnt_bits <= 6'd0;
+    state	 <= 4'b0;
+    cnt_lock <= 32'd0;
+    spi_csb  <= 1'b1;
+    cfgover  <= 1'b0;
+    spi_sdo  <= 1'b0;
+end
+else begin
+    case(state)
+    4'd0:begin
+			cnt_word <= 7'd0;		
+		if(rf_en==1'b1)
+            state <= 4'd0;
+		else if(cnt_lock >= 32'd4000) 
+			state <= 4'd1;
+		else
+			state <= state;
+			
+		if(rf_en==1'b0)
+			cnt_lock <= cnt_lock + 1'b1;
+		else
+			cnt_lock<=32'd0;
+		
+    end
+    4'd1:begin
+        spi_csb <= 1'b1;
+        spi_sdo <= 1'b0;
+		if(rf_en==1'b1)
+            state <= 4'd0;	
+		else
+			state 	<= 4'd2;
+    end
+    4'd2:begin
+        cfgdata  <= regdata;
+        cnt_bits <= 6'd0;
+        state    <= 4'd3;
+    end
+    4'd3:begin
+        spi_csb <= 1'b0;
+        spi_sdo <= cfgdata[DATA_WIDTH-1];
+        cfgdata <= cfgdata << 1'b1;
+        cnt_bits <= cnt_bits + 1'b1;
+        if(cnt_bits == DATA_WIDTH-1)begin
+            state 	 <= 4'd4;
+            cnt_word <= cnt_word + 1'b1;
+        end
+			cnt_lock <= 32'd0;
+    end
+    4'd4:begin
+        spi_csb  <= 1'b1;
+        spi_sdo  <= 1'b0;
+        cnt_lock <= 32'd0;
+        cnt_bits <= 32'd0;
+        if(cnt_word == DATA_LENTH)begin
+            state <= 4'd5;
+        end
+        else
+            state <= 4'd1;
+    end
+	4'd5:begin
+			if(cnt_lock>=40000 || pll_locked)begin
+				cnt_lock <=	32'd0	;
+				state	 <= 4'd6 ;
+			end
+			else begin
+				cnt_lock <=cnt_lock+1'b1;
+				state 	 <= state ;
+			end
+		end
+	4'd6:begin
+			    cnt_word <= 7'd0;
+			if(pll_locked)
+				state 	 <= 4'd7 ;
+			else
+				state 	 <= 4'b1 ;
+		end
+//----------------------------------------------------------------
+    4'd7:begin//IDLE
+		 cnt_word	<= DATA_LENTH;
+		 spi_csb 	<= 1'b1;
+         spi_sdo 	<= 1'b0;
+		 cnt_bits 	<= 6'd0;
+		 cfgover	<= 1'b0;
+		if(rf_en==4'b1)
+			state 	<= state;
+		else if(rf_en==4'b0 && rf_en_r==4'b1 )
+			state   <= 4'd0;
+		else if(hop_en==2'b10 || cnt_locked==WAIT_ld )	
+			state 	<= 4'd8;
+		else if(CAL_F_R==3'b011 && (pre_fre_code!=fre_code))//打开RF_OUT
+			state 	<= 4'd12;
+		else
+			state 	<= state;
+    end
+    4'd8:begin
+        spi_csb <= 1'b1;
+        spi_sdo <= 1'b0;    
+		state 	<= 4'd9;
+    end
+    4'd9:begin
+        cfgdata  <= regdata;
+        cnt_bits <= 6'd0;
+        state 	 <= 4'd10;
+    end
+    4'd10:begin
+        spi_csb <= 1'b0;
+        spi_sdo <= cfgdata[DATA_WIDTH-1];
+        cfgdata <= cfgdata << 1'b1;
+        cnt_bits <= cnt_bits + 1'b1;
+        if(cnt_bits == DATA_WIDTH-1)begin
+            state 	 <= 4'd11;
+            cnt_word <= cnt_word + 1'b1;
+        end
+    end
+	4'd11:begin
+        spi_csb  <= 1'b1;
+        spi_sdo  <= 1'b0;
+        cnt_lock <= 32'd0;
+        cnt_bits <= 32'd0;
+        if(cnt_word == 8'd85)begin
+            state <= 4'd7;
+        end
+        else
+            state <= 4'd8;
+    end
+	4'd12:begin
+        spi_csb <= 1'b1;
+        spi_sdo <= 1'b0;    
+		state 	<= 4'd13;
+    end
+    4'd13:begin
+	        cnt_bits <= 6'd0;
+			state 	 <= 4'd14;
+		if(ceshi_model==4'ha)
+			cfgdata<={16'h0025,8'h13};
+		else if(ceshi_model==4'hb)
+			cfgdata<={16'h0025,8'h00};
+		else if(SW_PLL)
+			cfgdata<={16'h0025,8'h13};
+		else 
+			cfgdata<={16'h0025,8'h00};
+    end
+    4'd14:begin
+        spi_csb <= 1'b0;
+        spi_sdo <= cfgdata[DATA_WIDTH-1];
+        cfgdata <= cfgdata << 1'b1;
+        cnt_bits <= cnt_bits + 1'b1;
+        if(cnt_bits == DATA_WIDTH-1)begin
+            state 	 <= 4'd7;
+			cfgover	<= 1'b1;
+            cnt_word <= cnt_word ;
+        end
+    end
+	
+//&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#//
+    default: begin  
+        spi_csb  <= 1'b1; 
+        state	 <= 4'd0;
+        cnt_lock <= 32'd0;
+        cnt_word <= 8'd0;
+    end
+    endcase
+end
+end
+
+always@(posedge sysclk,negedge arstn)
+begin
+	if(!arstn)
+		 regdata <=  {16'h0000,8'h18  };
+	else case(cnt_word)
+		8'd0  : regdata <=  {16'h0000,8'h18  };
+		8'd1  : regdata <=  {16'h0001,8'h00  };
+		8'd2  : regdata <=  {16'h0003,8'h00  };
+		8'd3  : regdata <=  {16'h0004,8'h00  };
+		8'd4  : regdata <=  {16'h0005,8'h00  };
+		8'd5  : regdata <=  {16'h0006,8'hFF  };
+		8'd6  : regdata <=  {16'h000C,8'h00  };
+		8'd7  : regdata <=  {16'h000D,8'h00  };
+		8'd8  : regdata <=  {16'h0010 ,INT[7:0]  	 			}  ;
+		8'd9  : regdata <=  {16'h0011 ,INT[15:8] 	 			}  ;
+		8'd10 : regdata <=  {16'h0012,8'h00  };//[6]No Autocalibration 
+		//8'd10 : regdata <=  {16'h0012,8'h40  };//[6]Autocalibration 
+		8'd11 : regdata <=  {16'h0014 ,FRAC1[7:0]}  ;
+		8'd12 : regdata <=  {16'h0015 ,FRAC1[15:8]}  ;
+		8'd13 : regdata <=  {16'h0016 ,FRAC1[23:16]}  ;
+		8'd14 : regdata <=  {16'h0017 ,FRAC2[6:0],FRAC1[24]}  ;
+		8'd15 : regdata <=  {16'h0018 ,1'b0,FRAC2[13:7]	}  ;
+		8'd16 : regdata <=  {16'h0019 ,MOD2[7:0]}  ;
+		8'd17 : regdata <=  {16'h001A ,2'b0,MOD2[13:8]}	;
+		8'd18 : regdata <=  {16'h001B,8'h00  };
+		8'd19 : regdata <=  {16'h001C,8'h00  };
+		8'd20 : regdata <=  {16'h001D,8'h00  };
+		8'd21 : regdata <=  {16'h001E,8'h18  };//CP_CURRENT 电荷泵
+	//	8'd21 : regdata <= { 16'h001E,cp,4'h8  };//CP_CURRENT 电荷泵
+		8'd22 : regdata <= { 16'h001F,4'h0,R_DIV  };//R DIV  R分频器
+		8'd23 : regdata <=  {16'h0020,8'h1c  };//digital lock detect  数字锁定ld
+		8'd24 : regdata <=  {16'h0021,8'h00  };
+		8'd25 : regdata <=  {16'h0022,D,4'd0  };//[4]2分频 		 [5]double   2倍频器
+		8'd26 : regdata <=  {16'h0023,8'h00  };
+		8'd27 : regdata <=  {16'h0024,8'h80  };//Fout_clk  DIV_SEL
+		8'd28 : regdata <=  {16'h0025,8'h13  };//X4_EN 
+		8'd29 : regdata <=  {16'h0026,8'h1F  };
+		8'd30 : regdata <=  {16'h0027,8'hCD  };
+		//8'd30 : regdata <=  {16'h0027,8'hCD  };
+		8'd31 : regdata <=  {16'h0028,8'h83  };
+		8'd32 : regdata <=  {16'h002A,8'h00  };
+		8'd33 : regdata <=  {16'h002B,8'h00  };
+		8'd34 : regdata <=  {16'h002C,8'h44  };
+		8'd35 : regdata <=  {16'h002D,8'h11  };
+		8'd36 : regdata <=  {16'h002E,8'h12  };
+		8'd37 : regdata <=  {16'h002F,8'h94  };
+		8'd38 : regdata <=  {16'h0030,8'h2A  };
+		8'd39 : regdata <=  {16'h0031,8'h02  };
+		8'd40 : regdata <=  {16'h0032,8'h04  };
+		8'd41 : regdata <=  {16'h0033,8'h22  };
+		8'd42 : regdata <=  {16'h0034,8'h25  };
+		8'd43 : regdata <=  {16'h0035,8'hFA  };
+		8'd44 : regdata <=  {16'h0036,8'h30  };
+		8'd45 : regdata <=  {16'h0037,SI_BAND_SEL}  ;//VCO频段
+		8'd46 : regdata <=  {16'h0038,SI_VCO_SEL_BIAS_CODE 	};//[7:4]=VCO内核,[3:0]VCO偏置
+		8'd47 : regdata <=  {16'h0039,8'h07  };
+		8'd48 : regdata <=  {16'h003A,8'h55  };
+		8'd49 : regdata <=  {16'h003D,8'h00  };
+		8'd50 : regdata <=  {16'h003E,8'h0C  };
+		8'd51 : regdata <=  {16'h003F,8'h80  };
+		8'd52 : regdata <=  {16'h0040,8'h50  };
+		8'd53 : regdata <=  {16'h0041,8'h28  };
+		8'd54 : regdata <=  {16'h0042,8'h00  };
+		8'd55 : regdata <=  {16'h0043,8'h00  };
+		8'd56 : regdata <=  {16'h0044,8'h00  };
+		8'd57 : regdata <=  {16'h0045,8'h00  };
+		8'd58 : regdata <=  {16'h0046,8'h00  };
+		8'd59 : regdata <=  {16'h0047,8'hC0  };
+		8'd60 : regdata <=  {16'h0052,8'hF4  };
+		8'd61 : regdata <=  {16'h006C,8'h00  };
+		8'd62 : regdata <=  {16'h006E,8'h00  };
+		8'd63 : regdata <=  {16'h006F,8'h00  };
+		8'd64 : regdata <=  {16'h0070,8'hE3  };
+		8'd65 : regdata <=  {16'h0071,8'h60  };
+		8'd66 : regdata <=  {16'h0072,8'h32  };
+		8'd67 : regdata <=  {16'h0073,8'h00  };
+		8'd68 : regdata <=  {16'h0079,8'h00  };
+		8'd69 : regdata <=  {16'h007A,8'h00  };
+		8'd70 : regdata <=  {16'h007B,8'h00  };
+		8'd71 : regdata <=  {16'h007C,8'h00  };
+
+		//跳频
+		8'd72:regdata <= { 16'h0022,D,4'd0  };//double    D倍频器
+		8'd73:regdata <= { 16'h001F,4'h0,R_DIV  };//R DIV  R分频器
+		8'd74:regdata <= { 16'h001A ,2'b0,MOD2[13:8]		}  ;
+		8'd75:regdata <= { 16'h0019 ,MOD2[7:0] 		 		}  ;
+		8'd76:regdata <= { 16'h0018 ,1'b0,FRAC2[13:7]	 	}  ;
+		8'd77:regdata <= { 16'h0017 ,FRAC2[6:0],FRAC1[24]	}  ;
+		8'd78:regdata <= { 16'h0016 ,FRAC1[23:16] 			}  ;
+		8'd79:regdata <= { 16'h0015 ,FRAC1[15:8] 			}  ;
+		8'd80:regdata <= { 16'h0014 ,FRAC1[7:0]	 			}  ;
+		8'd81:regdata <= { 16'h0037 ,SI_BAND_SEL 		 	}  ;
+		8'd82:regdata <= { 16'h0038 ,SI_VCO_SEL_BIAS_CODE 	}  ;
+		8'd83:regdata <= { 16'h0011 ,INT[15:8] 	 			}  ;
+		8'd84:regdata <= { 16'h0010 ,INT[7:0]  	 			}  ;
+		
+	default:   regdata <= regdata;
+endcase
+end
+
+
+
+
+
+
+
+
+
+
+
+endmodule

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/adf4371_b.v

@@ -0,0 +1,622 @@
+
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2021/8/13 00:24:20
+// Design Name: 
+// Module Name: LMX2595
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+
+// fRFOUT= (INT+ (FRAC1+FRAC2/MOD2)/MOD1)× (fPFD/R)
+// fPFD	 = fPFD = REFIN × ((1 + D)/(R × (1 + T))) 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module adf4371_b(//20.375Ghz ~ 23.875Ghz
+input               sysclk    ,//40MHZ
+input               arstn     ,
+output              cs        ,
+input               mux_out   ,
+output              sclk      ,
+output              sdio      ,     
+input [3:0]			rf_en	  , 			    
+input 				CAL_F	  , 			    
+input 				SW_PLL	  , 			    
+input 				i_cfgover	  , 			    
+input [3:0]			ceshi_model	  , 			    
+input               adf4371_hop      ,    			    
+input[11:0]         fre_code          			    
+    );
+
+localparam      DATA_WIDTH = 24			;
+localparam      DATA_LENTH = 72		;
+localparam      WAIT_ld   = 40000		;					
+//***********************************************************************************************************//												
+reg[7:0]                cnt_word    = 8'd0					;
+reg	    				csb_reg	    = 1'b1					;
+reg[5:0]                cnt_bits    = 6'd0					;  
+reg[DATA_WIDTH-1:0]     cfgdata     = 0,        regdata = 0	;
+reg[3:0]                state	    = 4'b000				;
+reg                     spi_sdo     = 1'b0,     spi_csb = 1'b1;
+wire                    pll_locked  						;
+reg[31:0]               cnt_lock    = 32'd0					;
+reg[31:0]               cnt_locked  = 32'd0					;
+wire[15:0]              band  							;
+
+//-----------------------------------
+assign      pll_locked		 = mux_out							;
+assign      sclk  	  		 = spi_csb ? 1'b0 : ~sysclk		;
+assign      cs     	  		 = spi_csb & csb_reg			;
+assign      sdio      		 = spi_sdo						;
+//-----------------------------------
+
+wire [7:0]	SI_BAND_SEL    ;		//VCO频段
+wire [7:0]	SI_VCO_SEL_BIAS_CODE    ; //[7:4]=VCO内核, [3:0]=VCO偏置
+reg[13:0]	MOD2		;
+reg[13:0]	FRAC2		;
+reg[24:0]	FRAC1		;
+reg[15:0]	INT			;
+
+assign		SI_BAND_SEL            =  band[15:8]   ;
+assign		SI_VCO_SEL_BIAS_CODE   =  band[7:0]  ;
+
+reg[2:0]	hop_en;	
+reg[15:0]	code;	
+reg[11:0]	pre_fre_code;
+reg[3:0]	cp_r;	
+reg[3:0]	rf_en_r;	
+reg[2:0]	CAL_F_R;	
+
+reg	[3:0]	R_DIV ;
+reg	[3:0]	D	 ;
+wire[13:0]	douta3		;
+wire[13:0]	douta4		;
+wire[24:0]	douta2		;
+wire[15:0]	douta1			;
+
+//----------------------------------- 
+INT_ROMb int_rom (
+    .sysclk(sysclk), 
+    .addra(code), 
+    .douta(douta1)
+    );
+
+FRAC1 frac1_rom (
+    .clka(sysclk), 
+    .addra(code), 
+    .douta(douta2)
+    );
+	
+// FRAC1_ROM FRAC1_ROM (
+//  .clka(sysclk), // input clka
+//  .addra(code), // input [11 : 0] addra
+//  .douta(douta2) // output [24 : 0] douta
+//); 
+	
+frac2_rom frac2_rom (
+    .sysclk(sysclk), 
+    .addra(code), 
+    .douta(douta4)
+    );
+
+mod2_rom mod2_rom (
+    .sysclk(sysclk), 
+    .addra(code), 
+    .douta(douta3)
+    );
+
+
+band_rom_b band_rom_b (
+    .sysclk(sysclk), 
+    .addra(code),
+	.douta(band) // output [15 : 0] douta
+    );	
+
+//-------------------整数边界杂散用66.666666Mhz鉴相----------------------------------
+
+always@(posedge sysclk,negedge arstn)
+begin
+	if(!arstn)
+		INT<=douta1;
+	else if(code==24 || code==26 )  
+		INT<=76;
+	else if(code==424 )  
+		INT<=77;
+	else if(code==426 )  
+		INT<=78;
+	else if(code==824 || code==826 )  
+		INT<=79;
+	else if(code==1224) 
+		INT<=80;
+	else if(code==1226 )  
+		INT<=81;
+	else if(code==1624 || code==1626 )  
+		INT<=82;
+	else if(code==2024 )  
+		INT<=83;
+	else if(code==2026 )  
+		INT<=84;	
+	else if(code==2424 || code==2426 )  
+		INT<=85;
+	else if(code==2824 )  
+		INT<=86;
+	else if( code==2826 )  
+		INT<=87;
+	else
+		INT<=douta1;	
+end
+
+always@(posedge sysclk,negedge arstn)
+begin
+	if(!arstn)
+		FRAC1<=douta2;
+	else if(code==24 )  
+		FRAC1<=16651386;
+	else if(code==26 )  
+		FRAC1<=16903045;
+	else if(code==424 )  
+		FRAC1<=33428602;
+	else if(code==426 )  
+		FRAC1<=125829;
+	else if(code==824 )  
+		FRAC1<=16651386;
+	else if(code==826 )  
+		FRAC1<=16903045;
+	else if(code==1224) 
+		FRAC1<=33428602;
+	else if(code==1226 )  
+		FRAC1<=125829;
+	else if(code==1624)  
+		FRAC1<=16651386;
+	else if(code==1626 )  
+		FRAC1<=16903045;
+	else if(code==2024 )  
+		FRAC1<=33428602;
+	else if(code==2026 )  
+		FRAC1<=125829;	
+	else if(code==2424 )  
+		FRAC1<=16651386;
+	else if(code==2426 )  
+		FRAC1<=16903045;
+	else if(code==2824 )  
+		FRAC1<=33428602;
+	else if( code==2826 )  
+		FRAC1<=125829;
+	else
+		FRAC1<=douta2;	
+end
+
+always@(posedge sysclk,negedge arstn)
+begin
+	if(!arstn)
+		MOD2<=douta3;
+	else if(code==24 )  
+		MOD2<=25;
+	else if(code==26 )  
+		MOD2<=25;
+	else if(code==424 )  
+		MOD2<=25;
+	else if(code==426 )  
+		MOD2<=25;
+	else if(code==824 )  
+		MOD2<=25;
+	else if(code==826 )  
+		MOD2<=25;
+	else if(code==1224) 
+		MOD2<=25;
+	else if(code==1226 )  
+		MOD2<=25;
+	else if(code==1624)  
+		MOD2<=25;
+	else if(code==1626 )  
+		MOD2<=25;
+	else if(code==2024 )  
+		MOD2<=25;
+	else if(code==2026 )  
+		MOD2<=25;	
+	else if(code==2424 )  
+		MOD2<=25;
+	else if(code==2426 )  
+		MOD2<=25;
+	else if(code==2824 )  
+		MOD2<=25;
+	else if( code==2826 )  
+		MOD2<=25;
+	else
+		MOD2<=douta3;	
+end
+
+always@(posedge sysclk,negedge arstn)
+begin
+	if(!arstn)
+		FRAC2<=douta4;
+	else if(code==24 )  
+		FRAC2<=22;
+	else if(code==26 )  
+		FRAC2<=3;
+	else if(code==424 )  
+		FRAC2<=22;
+	else if(code==426 )  
+		FRAC2<=3;
+	else if(code==824 )  
+		FRAC2<=22;
+	else if(code==826 )  
+		FRAC2<=3;
+	else if(code==1224) 
+		FRAC2<=22;
+	else if(code==1226 )  
+		FRAC2<=3;
+	else if(code==1624)  
+		FRAC2<=22;
+	else if(code==1626 )  
+		FRAC2<=3;
+	else if(code==2024 )  
+		FRAC2<=22;
+	else if(code==2026 )  
+		FRAC2<=3;	
+	else if(code==2424 )  
+		FRAC2<=22;
+	else if(code==2426 )  
+		FRAC2<=3;
+	else if(code==2824 )  
+		FRAC2<=22;
+	else if( code==2826 )  
+		FRAC2<=3;
+	else
+		FRAC2<=douta4;	
+end
+
+always@(posedge sysclk,negedge arstn)
+begin
+	if(!arstn)begin
+		R_DIV<=4'b1;
+		D<=4'b0;
+	end
+	else if(code==24 || code==26 ||   code==424 ||  code==426 || code==824 ||  code==826|| code==1224 ||  code==1226 || code==1624 ||  code==1626 ||code==2024 ||  code==2026 ||code==2424 ||  code==2426 ||code==2824 ||  code==2826 )
+	begin
+		R_DIV<=	4'd3;
+		D<=4'd2;
+	end
+	else
+	begin
+		R_DIV<=4'b1;
+		D<=4'b0;
+	end	
+end
+
+
+always@(posedge sysclk,negedge arstn)begin
+if(~arstn)
+	pre_fre_code<=11'h6d6;
+else if(CAL_F_R==3'b011)
+	pre_fre_code<=fre_code;
+else
+	pre_fre_code<=pre_fre_code;
+end
+
+always@(posedge sysclk,negedge arstn)begin
+if(~arstn)
+	code<=16'h6d6;
+else if(hop_en==2'b01)
+	code<=fre_code;
+else
+	code<=code;
+end
+
+always@(posedge sysclk,negedge arstn)begin
+if(~arstn)begin
+    hop_en 	<= 3'b0;
+    CAL_F_R 	<= 3'b0;
+    rf_en_r <= 4'b0;
+end
+else  begin
+	hop_en	<= {hop_en[1:0],adf4371_hop};
+	CAL_F_R	<= {CAL_F_R[1:0],CAL_F};
+	rf_en_r	<= rf_en	;
+end
+end
+
+
+always@(posedge sysclk,negedge arstn)begin
+if(~arstn)
+    csb_reg 	<= 1'b1;
+else  
+	csb_reg		<= spi_csb;
+end
+
+
+always@(posedge sysclk,negedge arstn)begin
+if(~arstn)	
+	cnt_locked<=32'b0;
+else if(cnt_locked==WAIT_ld)
+	cnt_locked<=32'b0;
+else if(!pll_locked)
+	cnt_locked<=cnt_locked+1'b1;
+else
+	cnt_locked<=32'b0;
+end
+
+always@(posedge sysclk,negedge arstn)begin
+if(~arstn)begin
+    cfgdata  <= 0;
+    cnt_word <= 7'd0;
+    cnt_bits <= 6'd0;
+    state	 <= 4'b0;
+    cnt_lock <= 32'd0;
+    spi_csb  <= 1'b1;
+    spi_sdo  <= 1'b0;
+end
+else begin
+    case(state)
+    4'd0:begin
+			cnt_word <= 7'd0;		
+		if(rf_en==1'b1)
+            state <= 4'd0;
+		else if(cnt_lock >= 32'd6000) 
+			state <= 4'd1;
+		else
+			state <= state;
+			
+		if(rf_en==1'b0)
+			cnt_lock <= cnt_lock + 1'b1;
+		else
+			cnt_lock<=32'd0;
+		
+    end
+    4'd1:begin
+        spi_csb <= 1'b1;
+        spi_sdo <= 1'b0;      
+        state 	<= 4'd2;
+    end
+    4'd2:begin
+        cfgdata  <= regdata;
+        cnt_bits <= 6'd0;
+        state    <= 4'd3;
+    end
+    4'd3:begin
+        spi_csb <= 1'b0;
+        spi_sdo <= cfgdata[DATA_WIDTH-1];
+        cfgdata <= cfgdata << 1'b1;
+        cnt_bits <= cnt_bits + 1'b1;
+        if(cnt_bits == DATA_WIDTH-1)begin
+            state 	 <= 4'd4;
+            cnt_word <= cnt_word + 1'b1;
+        end
+			cnt_lock <= 32'd0;
+    end
+    4'd4:begin
+        spi_csb  <= 1'b1;
+        spi_sdo  <= 1'b0;
+        cnt_lock <= 32'd0;
+        cnt_bits <= 32'd0;
+        if(cnt_word == DATA_LENTH)begin
+            state <= 4'd5;
+        end
+        else
+            state <= 4'd1;
+    end
+	4'd5:begin
+			if(cnt_lock>=40000 || pll_locked)begin
+				cnt_lock <=	32'd0	;
+				state	 <= 4'd6 ;
+			end
+			else begin
+				cnt_lock <=cnt_lock+1'b1;
+				state 	 <= state ;
+			end
+		end
+	4'd6:begin
+			    cnt_word <= 7'd0;
+			if(pll_locked)
+				state 	 <= 4'd7 ;
+			else
+				state 	 <= 4'b1 ;
+		end
+//&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#//
+    4'd7:begin//IDLE
+		 cnt_word	<= DATA_LENTH;
+		 spi_csb 	<= 1'b1;
+         spi_sdo 	<= 1'b0;
+		 cnt_bits 	<= 6'd0;
+		if(rf_en==4'b1)
+			state 	<= state;
+		else if(rf_en==4'b0 && rf_en_r==4'b1 )
+			state   <= 4'd0;
+		else if(hop_en==2'b10 || cnt_locked==WAIT_ld  )
+			state 	<= 4'd8;
+		//else if(CAL_F_R==3'b011 && (pre_fre_code!=fre_code))//打开RF_OUT
+		else if(i_cfgover)
+			state 	<= 4'd12;
+		else
+			state 	<= state;
+    end
+    4'd8:begin
+        spi_csb <= 1'b1;
+        spi_sdo <= 1'b0;    
+		state 	<= 4'd9;
+    end
+    4'd9:begin
+        cfgdata  <= regdata;
+        cnt_bits <= 6'd0;
+        state 	 <= 4'd10;
+    end
+    4'd10:begin
+        spi_csb <= 1'b0;
+        spi_sdo <= cfgdata[DATA_WIDTH-1];
+        cfgdata <= cfgdata << 1'b1;
+        cnt_bits <= cnt_bits + 1'b1;
+        if(cnt_bits == DATA_WIDTH-1)begin
+            state 	 <= 4'd11;
+            cnt_word <= cnt_word + 1'b1;
+        end
+    end
+	4'd11:begin
+        spi_csb  <= 1'b1;
+        spi_sdo  <= 1'b0;
+        cnt_lock <= 32'd0;
+        cnt_bits <= 32'd0;
+        if(cnt_word == 8'd85)begin
+            state <= 4'd7;
+        end
+        else
+            state <= 4'd8;
+    end
+	4'd12:begin
+        spi_csb <= 1'b1;
+        spi_sdo <= 1'b0;    
+		state 	<= 4'd13;
+    end
+    4'd13:begin
+        cnt_bits <= 6'd0;
+        state 	 <= 4'd14;
+		if(ceshi_model==4'hb)
+			cfgdata  <= {16'h0025,8'h13};
+		else if(ceshi_model==4'ha)
+			cfgdata  <= {16'h0025,8'h00};
+		else if	(SW_PLL)
+			cfgdata  <= {16'h0025,8'h00};
+		else	
+			cfgdata  <= {16'h0025,8'h13};
+    end
+    4'd14:begin
+        spi_csb <= 1'b0;
+        spi_sdo <= cfgdata[DATA_WIDTH-1];
+        cfgdata <= cfgdata << 1'b1;
+        cnt_bits <= cnt_bits + 1'b1;
+        if(cnt_bits == DATA_WIDTH-1)begin
+            state 	 <= 4'd7;
+            cnt_word <= cnt_word ;
+        end
+    end
+//&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#//
+    default: begin  
+        spi_csb  <= 1'b1; 
+        state	 <= 4'd0;
+        cnt_lock <= 32'd0;
+        cnt_word <= 8'd0;
+    end
+    endcase
+end
+end
+
+always@(posedge sysclk,negedge arstn)
+begin
+	if(!arstn)
+		 regdata <=  {16'h0000,8'h18  };
+	else case(cnt_word)
+		8'd0  : regdata <=  {16'h0000,8'h18  };
+		8'd1  : regdata <=  {16'h0001,8'h00  };
+		8'd2  : regdata <=  {16'h0003,8'h00  };
+		8'd3  : regdata <=  {16'h0004,8'h00  };
+		8'd4  : regdata <=  {16'h0005,8'h00  };
+		8'd5  : regdata <=  {16'h0006,8'hFF  };
+		8'd6  : regdata <=  {16'h000C,8'h00  };
+		8'd7  : regdata <=  {16'h000D,8'h00  };
+		8'd8  : regdata <=  {16'h0010 ,INT[7:0]  	 			}  ;
+		8'd9  : regdata <=  {16'h0011 ,INT[15:8] 	 			}  ;
+		8'd10 : regdata <=  {16'h0012,8'h00  };//[6]Autocalibration 
+		//8'd10 : regdata <=  {16'h0012,8'h40  };//[6]Autocalibration 
+		8'd11 : regdata <=  {16'h0014 ,FRAC1[7:0]}  ;
+		8'd12 : regdata <=  {16'h0015 ,FRAC1[15:8]}  ;
+		8'd13 : regdata <=  {16'h0016 ,FRAC1[23:16]}  ;
+		8'd14 : regdata <=  {16'h0017 ,FRAC2[6:0],FRAC1[24]}  ;
+		8'd15 : regdata <=  {16'h0018 ,1'b0,FRAC2[13:7]	}  ;
+		8'd16 : regdata <=  {16'h0019 ,MOD2[7:0]}  ;
+		8'd17 : regdata <=  {16'h001A ,2'b0,MOD2[13:8]}	;
+		8'd18 : regdata <=  {16'h001B,8'h00  };
+		8'd19 : regdata <=  {16'h001C,8'h00  };
+		8'd20 : regdata <=  {16'h001D,8'h00  };
+		8'd21 : regdata <=  {16'h001E,8'h18  };//CP_CURRENT 电荷泵
+		//8'd21 : regdata <=  {16'h001E,cp,4'h8  };//CP_CURRENT 电荷泵
+		8'd22 : regdata <= { 16'h001F,4'h0,R_DIV  };//R DIV  R分频器
+		8'd23 : regdata <=  {16'h0020,8'h1c  };//digital lock detect  数字锁定ld
+		8'd24 : regdata <=  {16'h0021,8'h00  };
+		8'd25 : regdata <= { 16'h0022,D,4'd0  };//double    D倍频器
+		8'd26 : regdata <=  {16'h0023,8'h00  };
+		8'd27 : regdata <=  {16'h0024,8'h80  };//DIV_SEL
+		8'd28 : regdata <=  {16'h0025,8'h13  };//X4_EN 
+		8'd29 : regdata <=  {16'h0026,8'h1F  };
+		8'd30 : regdata <=  {16'h0027,8'hCD  };
+		//8'd30 : regdata <=  {16'h0027,8'hCD  };
+		8'd31 : regdata <=  {16'h0028,8'h83  };
+		8'd32 : regdata <=  {16'h002A,8'h00  };
+		8'd33 : regdata <=  {16'h002B,8'h00  };
+		8'd34 : regdata <=  {16'h002C,8'h44  };
+		8'd35 : regdata <=  {16'h002D,8'h11  };
+		8'd36 : regdata <=  {16'h002E,8'h12  };
+		8'd37 : regdata <=  {16'h002F,8'h94  };
+		8'd38 : regdata <=  {16'h0030,8'h2A  };
+		8'd39 : regdata <=  {16'h0031,8'h02  };
+		8'd40 : regdata <=  {16'h0032,8'h04  };
+		8'd41 : regdata <=  {16'h0033,8'h22  };
+		8'd42 : regdata <=  {16'h0034,8'h25  };
+		8'd43 : regdata <=  {16'h0035,8'hFA  };
+		8'd44 : regdata <=  {16'h0036,8'h30  };
+		8'd45 : regdata <=  {16'h0037,SI_BAND_SEL}  ;//VCO频段
+		8'd46 : regdata <=  {16'h0038,SI_VCO_SEL_BIAS_CODE 	};//[7:4]=VCO内核,[3:0]VCO偏置
+		8'd47 : regdata <=  {16'h0039,8'h07  };
+		8'd48 : regdata <=  {16'h003A,8'h55  };
+		8'd49 : regdata <=  {16'h003D,8'h00  };
+		8'd50 : regdata <=  {16'h003E,8'h0C  };
+		8'd51 : regdata <=  {16'h003F,8'h80  };
+		8'd52 : regdata <=  {16'h0040,8'h50  };
+		8'd53 : regdata <=  {16'h0041,8'h28  };
+		8'd54 : regdata <=  {16'h0042,8'h00  };
+		8'd55 : regdata <=  {16'h0043,8'h00  };
+		8'd56 : regdata <=  {16'h0044,8'h00  };
+		8'd57 : regdata <=  {16'h0045,8'h00  };
+		8'd58 : regdata <=  {16'h0046,8'h00  };
+		8'd59 : regdata <=  {16'h0047,8'hC0  };
+		8'd60 : regdata <=  {16'h0052,8'hF4  };
+		8'd61 : regdata <=  {16'h006C,8'h00  };
+		8'd62 : regdata <=  {16'h006E,8'h00  };
+		8'd63 : regdata <=  {16'h006F,8'h00  };
+		8'd64 : regdata <=  {16'h0070,8'hE3  };
+		8'd65 : regdata <=  {16'h0071,8'h60  };
+		8'd66 : regdata <=  {16'h0072,8'h32  };
+		8'd67 : regdata <=  {16'h0073,8'h00  };
+		8'd68 : regdata <=  {16'h0079,8'h00  };
+		8'd69 : regdata <=  {16'h007A,8'h00  };
+		8'd70 : regdata <=  {16'h007B,8'h00  };
+		8'd71 : regdata <=  {16'h007C,8'h00  };
+
+		//跳频
+		8'd72:regdata <= { 16'h0022,D,4'd0  };//double    D倍频器
+		8'd73:regdata <= { 16'h001F,4'h0,R_DIV  };//R DIV  R分频器
+		8'd74:regdata <= { 16'h001A ,2'b0,MOD2[13:8]		}  ;
+		8'd75:regdata <= { 16'h0019 ,MOD2[7:0] 		 		}  ;
+		8'd76:regdata <= { 16'h0018 ,1'b0,FRAC2[13:7]	 	}  ;
+		8'd77:regdata <= { 16'h0017 ,FRAC2[6:0],FRAC1[24]	}  ;
+		8'd78:regdata <= { 16'h0016 ,FRAC1[23:16] 			}  ;
+		8'd79:regdata <= { 16'h0015 ,FRAC1[15:8] 			}  ;
+		8'd80:regdata <= { 16'h0014 ,FRAC1[7:0]	 			}  ;
+		8'd81:regdata <= { 16'h0037 ,SI_BAND_SEL 		 	}  ;
+		8'd82:regdata <= { 16'h0038 ,SI_VCO_SEL_BIAS_CODE 	}  ;
+		8'd83:regdata <= { 16'h0011 ,INT[15:8] 	 			}  ;
+		8'd84:regdata <= { 16'h0010 ,INT[7:0]  	 			}  ;
+		
+	default:   regdata <= regdata;
+endcase
+end
+
+
+
+
+
+
+
+
+
+
+
+endmodule

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/ds18b20_temp.v

@@ -0,0 +1,368 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    13:59:21 10/19/2020 
+// Design Name: 
+// Module Name:    DS18B20 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+
+//+125  	0000 0111 1101 0000  07D0h 
+//+85*  	0000 0101 0101 0000  0550h 
+//+25.0625  0000 0001 1001 0001  0191h 
+//+10.125   0000 0000 1010 0010  00A2h 
+//+0.5 	    0000 0000 0000 1000  0008h 
+//0  		0000 0000 0000 0000  0000h 
+//-0.5  	1111 1111 1111 1000  FFF8h 
+//-10.125   1111 1111 0101 1110  FF5Eh 
+//-25.0625  1111 1110 0110 1111  FE6Fh 
+//-55  		1111 1100 1001 0000  FC90h 
+//////////////////////////////////////////////////////////////////////////////////
+module ds18b20_temp(
+	input    					clk			,    //40_000_000
+	input    					rstn		,
+	inout 	 					dq   		,
+	output reg signed[15:0]     temp_data	     //LSB =0.625 C    
+);
+
+parameter	 FRE		=	40	    ;// //clk为40M时钟，若clk为50M，则 FRE=50；
+
+parameter    INIT		=	3'b000	,    //Gray code
+			 WR_CMD 	=	3'b001	,
+			 WAIT		=	3'b011	,
+			 INIT_AGAIN =	3'b010	,
+			 RD_CMD		=	3'b110	,
+			 RD_TEMP	=	3'b111	;
+	 
+localparam	 WR_CC_44		=	16'h44cc		;
+localparam	 WR_CC_BE		=	16'hbecc		;
+localparam   cnt_max	  	=	FRE[31:1]-1		;
+localparam   WAIT_TEMP_CNT	=	20'd750_000		;//750ms
+
+reg 		 flag			;
+reg [15:0]	 data_reg		;
+reg [2:0]	 state			;
+reg 		 clk_1us		;
+reg [31:0]	 cnt_1us		;
+reg 		 dq_en			;
+reg 		 dq_reg			;
+reg [19:0] 	 cnt			;
+reg [3:0]  	 bit_cnt		;
+
+assign  	 dq = dq_en ? dq_reg : 1'bz;
+
+always@(posedge clk,negedge rstn)
+	if(!rstn)
+		cnt_1us<=32'b0;
+	else if(cnt_1us==cnt_max)
+		cnt_1us<=32'b0;
+	else
+		cnt_1us<=cnt_1us+1'b1;
+
+always@(posedge clk,negedge rstn)
+	if(!rstn)
+		clk_1us<=1'b0;
+	else if(cnt_1us==cnt_max)
+		clk_1us<=~clk_1us;
+	else
+		clk_1us<=clk_1us;
+
+always@(posedge clk_1us,negedge rstn)
+	if(!rstn)
+		begin
+			dq_en	 <=1'b1;
+			dq_reg	 <=1'b0;
+			state	 <=INIT;
+			cnt		 <=20'd0;
+			flag	 <=1'b0;
+			bit_cnt  <=4'b0;
+			data_reg <=16'd0;
+			temp_data<=12'b0;
+		end 
+	else case(state)
+			INIT	  :begin
+						//if(cnt==16'd999)begin //for sim
+							if(cnt==16'd9999)
+								cnt  <=20'd0;
+							else if(cnt==16'd999&&flag)begin
+								cnt  <=20'd0;
+								state<=WR_CMD;
+							end
+							else  begin
+								cnt	 <=cnt+1'd1;
+								state<=INIT;
+							end
+							//------------------
+							if(cnt==16'd9999)begin
+								dq_en <=1'b1;
+								dq_reg<=1'b0;
+							end
+							//else if(cnt==16'd499)begin
+							else if(cnt==16'd599)begin
+								dq_en <=1'b0;
+								dq_reg<=1'b0;
+							end
+							else begin
+								dq_en <=dq_en;
+								dq_reg<=dq_reg;
+							end
+							//------------------
+						//	if(cnt==20'd570)//&&dq==1'b0)
+							if(cnt==20'd670)//&&dq==1'b0)
+								flag<= ~dq;
+							else if(cnt==20'd999) 
+								flag<=1'b0;
+							else 
+								flag<=flag;
+					   end
+	/* 		INIT	  :begin
+						//if(cnt==16'd999)begin //for sim
+							if(cnt==16'd999&&flag)begin
+								cnt  <=20'd0;
+								state<=WR_CMD;
+							end
+							else  begin
+								cnt	 <=cnt+1'd1;
+								state<=INIT;
+							end
+							//------------------
+							if(cnt==16'd499)begin
+								dq_en <=1'b0;
+								dq_reg<=1'b0;
+							end
+							else begin
+								dq_en <=dq_en;
+								dq_reg<=dq_reg;
+							end
+							//------------------
+							if(cnt==20'd570)//&&dq==1'b0)
+								flag<= ~dq;
+							else if(cnt==20'd999) 
+								flag<=1'b0;
+							else 
+								flag<=flag;
+					   end */			
+			WR_CMD 	   :begin
+							if(cnt==20'd64 && bit_cnt==4'd15)
+								begin
+									bit_cnt<=4'd0;
+									state<=WAIT;
+								end
+							else if(cnt==20'd64)
+								begin
+									bit_cnt<=bit_cnt+1'd1;
+									state<=WR_CMD;
+								end
+							else 
+								begin
+									bit_cnt<=bit_cnt;
+									state<=WR_CMD;
+								end
+							//------------------	
+							if(cnt==20'd64 && bit_cnt==4'd15)
+								cnt<=20'd0;
+							else if(cnt==20'd64)
+								cnt<=20'd0;
+							else 
+								cnt<=cnt+1'd1;
+							//------------------
+							if(WR_CC_44[bit_cnt]==1'b0 && cnt<=20'd62)
+								begin
+									dq_en <=1'b1;
+									dq_reg<=1'b0;
+								end
+							else if(WR_CC_44[bit_cnt]==1'b1 && cnt<=20'd1)
+								begin
+									dq_en <=1'b1;
+									dq_reg<=1'b0;
+								end
+							else
+								begin
+									dq_en <=1'b0;
+									dq_reg<=1'b0;
+								end			
+						end
+			WAIT	   : 	if(cnt==WAIT_TEMP_CNT)
+								begin
+									dq_en <=1'b1;
+									dq_reg<=1'b0;
+									cnt<=20'd0;
+									state<=INIT_AGAIN;
+								end
+							else 
+							begin
+								dq_en <=1'b1;
+								dq_reg<=1'b1;
+								cnt<=cnt+1'd1;
+								state<=WAIT;
+							end	
+			INIT_AGAIN :begin
+							if(cnt==16'd999&&flag)
+							//if(cnt==16'd999) //for sim
+								begin
+									cnt  <=20'd0;
+									state<=RD_CMD;
+								end
+							else 
+								begin
+									cnt	 <=cnt+1'd1;
+									state<=INIT_AGAIN;
+								end
+							//------------------
+							if(cnt==16'd499)
+								begin
+									dq_en <=1'b0;
+									dq_reg<=1'b0;
+								end
+							else 
+								begin
+									dq_en <=dq_en;
+									dq_reg<=dq_reg;
+								end
+							//------------------
+							if(cnt==20'd570)//&&dq==1'b0)
+								flag<=~dq;
+							else if(cnt==20'd999) 
+								flag<=1'b0;
+							else 
+								flag<=flag;
+						end
+			RD_CMD	   :begin
+							if(cnt==20'd64 && bit_cnt==4'd15)
+								begin
+									bit_cnt<=4'd0;
+									state<=RD_TEMP;
+								end
+							else if(cnt==20'd64)
+								begin
+									bit_cnt<=bit_cnt+1'd1;
+									state<=RD_CMD;
+								end
+							else 
+								begin
+									bit_cnt<=bit_cnt;
+									state<=RD_CMD;
+								end
+							//------------------
+							if(cnt==20'd64 && bit_cnt==4'd15)
+								cnt<=20'd0;
+							else if(cnt==20'd64)
+								cnt<=20'd0;
+							else 
+								cnt<=cnt+1'd1;
+							//------------------
+							if(WR_CC_BE[bit_cnt]==1'b0 && cnt<=20'd62)
+								begin
+									dq_en <=1'b1;
+									dq_reg<=1'b0;
+								end
+							else if(WR_CC_BE[bit_cnt]==1'b1 && cnt<=20'd1)
+								begin
+									dq_en <=1'b1;
+									dq_reg<=1'b0;
+								end
+							else
+								begin
+									dq_en <=1'b0;
+									dq_reg<=1'b0;
+								end
+						end
+			RD_TEMP	   :begin
+							if(cnt==20'd64 && bit_cnt==4'd15)
+								cnt	  <=20'd0;
+							else if(cnt==20'd64)
+								cnt<=20'd0;
+							else 
+								cnt<=cnt+1'd1;
+							//------------------	
+							if(cnt<=20'd1|| (cnt==20'd64 && bit_cnt==4'd15))
+								begin
+									dq_en <=1'b1;
+									dq_reg<=1'b0;
+								end
+							else
+								begin
+									dq_en <=1'b0;
+									dq_reg<=1'b0;
+								end
+							//------------------
+							if(cnt==20'd64 && bit_cnt==4'd15)
+								begin
+									bit_cnt<=4'd0;
+									state<=INIT;
+								end
+							else if(cnt==20'd64)
+								begin
+									bit_cnt<=bit_cnt+1'd1;
+									state<=RD_TEMP;
+								end
+							else 
+								begin
+									bit_cnt<=bit_cnt;
+									state<=RD_TEMP;
+								end
+							//------------------
+							if(cnt==20'd8)
+								data_reg<={dq,data_reg[15:1]};
+							else
+								data_reg<=data_reg;	
+							//------------------
+							if(cnt==20'd64 && bit_cnt==4'd15)
+								temp_data<=data_reg;
+							else
+								temp_data<=temp_data;
+						end
+			default:	state<=INIT;
+			endcase
+
+			
+/* wire[33:0]SYNC_OUT;
+wire[35:0]CONTROL0;
+wire[35:0]CONTROL1;
+wire[149:0]TRIG0;
+
+ vio u_vio (
+    .CONTROL	(CONTROL0),	// INOUT BUS [35:0]
+    .CLK		(clk),	// IN
+    .SYNC_OUT	(SYNC_OUT)	// OUT BUS [33:0]
+);
+
+
+icon u_icon (
+    .CONTROL0	(CONTROL0),	// INOUT BUS [35:0]
+    .CONTROL1	(CONTROL1)	// INOUT BUS [35:0]
+);
+
+
+ila u_ila (
+    .CONTROL	(CONTROL1), // INOUT BUS [35:0]
+    .CLK		(clk), // IN
+    .TRIG0		(TRIG0) // IN BUS [39:0]
+);
+
+
+assign TRIG0[2:0]	=	state          ;
+assign TRIG0[21:3]	=	cnt           ;
+assign TRIG0[22]	=	dq           ;	
+ */	
+
+
+
+
+
+
+
+
+
+	
+			
+			
+			
+			
+			
+			
+endmodule

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/frac2_rom.v

@@ -0,0 +1,72 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    15:35:03 01/27/2022 
+// Design Name: 
+// Module Name:    mod2_rom 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module frac2_rom(
+input   		sysclk,
+input [11 : 0]   addra,
+output reg[13:0] douta
+);
+
+
+reg[11:0]	addr=0;
+
+always@(posedge sysclk)begin
+	addr<=addra%25;	
+end
+
+always@(posedge sysclk)begin
+	case(addr)
+0	:	douta	<=	0;
+1	:	douta	<=	2;
+2	:	douta	<=	4;
+3	:	douta	<=	6;
+4	:	douta	<=	8;
+5	:	douta	<=	2;
+6	:	douta	<=	12;
+7	:	douta	<=	14;
+8	:	douta	<=	16;
+9	:	douta	<=	18;
+10	:	douta	<=	4;
+11	:	douta	<=	22;
+12	:	douta	<=	24;
+13	:	douta	<=	1;
+14	:	douta	<=	3;
+15	:	douta	<=	1;
+16	:	douta	<=	7;
+17	:	douta	<=	9;
+18	:	douta	<=	11;
+19	:	douta	<=	13;
+20	:	douta	<=	3;
+21	:	douta	<=	17;
+22	:	douta	<=	19;
+23	:	douta	<=	21;
+24	:	douta	<=	23;
+default:douta	<=	douta	;
+endcase
+
+end
+
+
+
+
+
+
+
+endmodule

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/fre_caliatt.v

@@ -0,0 +1,210 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    10:03:33 09/24/2021 
+// Design Name: 
+// Module Name:    fre_caliatt 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module 		fre_caliatt(
+input				i_clk			,
+input				i_rstn			,
+output				ENABLE   	    ,
+output				SC       	    ,
+output				SD       	    ,
+output				END_SYN  	    ,
+input				SDOUT    	    ,
+input				CAL_F    	    ,
+input signed[7:0]	i_temp			,
+input[15:0]			i_fre_mode		,
+input[15:0]			i_cal_fre_code		,
+input  [3:0]		cal1_mgc       ,
+input  [3:0]		cal2_mgc       ,
+input  [3:0]		cal3_mgc       ,
+input  [3:0]		cal4_mgc       ,
+input  [3:0]		i_ceshi_module       ,
+input [40:0] 		SYNC_OUT		,
+input 				SW				,
+output [3:0]		R_CAL1			,
+output [3:0]		R_CAL2			,
+output [3:0]		R_CAL3			,	
+output [3:0]		R_CAL4			,	
+input [4:0]			tx_mgc			,	
+input [4:0]			tx_cal_mgc			,	
+output [4:0]		T_CAL			
+ );
+ 
+ 
+wire[15:0]	fre_mode		;
+wire[31:0]	hop_fre_mode		;
+assign		fre_mode		=	i_cal_fre_code/40		;//20.375Ghz~23.875Ghz
+assign		hop_fre_mode	=	i_cal_fre_code+20375	;//20.375Ghz~23.875Ghz
+
+
+wire [3:0]	R_CAL4_r    	    ;
+wire [3:0]	R_CAL3_r    	    ;
+wire [3:0]	R_CAL2_r    	    ;
+wire [3:0]	R_CAL1_r    	    ;
+wire [4:0]	T_CAL_r    	   	    ;
+wire [31:0]	data_in	   		    ;
+reg	 [31:0]	data_in_r	        ;
+reg			R_CAL_F	   		    ;
+wire[15:0]	cal_mgc_r	   		    ;
+reg	[15:0]	cal_mgc_rr	   		    ;
+reg			tx_en	   		    ;
+reg 		vio_en		        ;
+
+
+
+
+always@(posedge i_clk)
+begin
+	cal_mgc_rr	<=	cal_mgc_r;
+end
+//------------------vio_debug------------------------//
+/* always@(posedge i_clk)
+begin
+	vio_R_CAL_4	<=	SYNC_OUT[4:0];
+	vio_R_CAL_3	<=	SYNC_OUT[9:5];
+	vio_R_CAL_2	<=	SYNC_OUT[14:10];
+	vio_R_CAL_1	<=	SYNC_OUT[19:15];
+	vio_T_CAL  	<=	SYNC_OUT[24:20];
+	vio_en		<=	SYNC_OUT[25]; 	
+end */
+
+//------------------vio_debug------------------------//
+assign R_CAL1	= R_CAL1_r + cal1_mgc ;//通道1 
+assign R_CAL2	= R_CAL2_r + cal2_mgc ;//通道2 
+assign R_CAL3	= R_CAL3_r + cal3_mgc ;//通道3 
+assign R_CAL4	= R_CAL4_r + cal4_mgc ;//通道4 
+assign T_CAL	= ( i_ceshi_module==4'ha || i_ceshi_module==4'hb) ? (tx_mgc[4:0] + tx_cal_mgc) :  (T_CAL_r + tx_cal_mgc) ;//发射通道，低衰减
+
+assign		cal_mgc_r	=	{cal1_mgc,cal2_mgc,cal3_mgc,cal4_mgc};
+assign		data_in = {	4'h0,3'b0,
+						T_CAL	,  //发射通道
+                        R_CAL1[0], //接收通道1_1dB
+						R_CAL1[1], //接收通道1_2dB
+						R_CAL1[2], //接收通道1_4dB
+						R_CAL1[3], //接收通道1_8dB
+					    R_CAL2[0], //接收通道2_1dB
+						R_CAL2[1], //接收通道2_2dB
+						R_CAL2[2], //接收通道2_4dB
+						R_CAL2[3], //接收通道2_8dB
+						R_CAL3[0], //接收通道3_1dB
+						R_CAL3[1], //接收通道3_2dB
+						R_CAL3[2], //接收通道3_4dB
+						R_CAL3[3], //接收通道3_8dB
+						R_CAL4   , //
+						4'b0   	};
+reg [31:0] cnt5us=0;
+
+always@(posedge i_clk)begin
+	if(cnt5us==2000)
+		cnt5us<=2000;
+	else
+		cnt5us<=cnt5us+1'b1;
+end	
+
+always@(posedge i_clk or negedge i_rstn)begin
+if(!i_rstn)
+    R_CAL_F 	<= 1'b0;
+else 
+	R_CAL_F 	<= CAL_F;
+end
+
+always@(posedge i_clk or negedge i_rstn)begin
+	if(!i_rstn)
+		tx_en<=1'b0;
+	else if(cnt5us==1999)
+		tx_en<=1'b1;
+	else if({R_CAL_F,CAL_F}==2'b01 ||  cal_mgc_rr!=cal_mgc_r)
+		tx_en<=1'b1;
+	else
+		tx_en<=1'b0;
+end
+
+
+	
+R_CAL_1 R_CAL_1 (
+    .i_clk(i_clk), 
+    .i_rstn(i_rstn), 
+    .i_temp(i_temp), 
+    .fre_mode(fre_mode), 
+    .R_CAL(R_CAL1_r)
+    );
+
+R_CAL_2 R_CAL_2 (
+    .i_clk(i_clk), 
+    .i_rstn(i_rstn), 
+    .i_temp(i_temp), 
+    .fre_mode(fre_mode), 
+    .R_CAL(R_CAL2_r)
+    );
+
+R_CAL_3 R_CAL_3 (
+    .i_clk(i_clk), 
+    .i_rstn(i_rstn), 
+    .i_temp(i_temp), 
+    .fre_mode(fre_mode), 
+    .R_CAL(R_CAL3_r)
+    );
+
+R_CAL_4 R_CAL_4 (
+    .i_clk(i_clk), 
+    .i_rstn(i_rstn), 
+    .i_temp(i_temp), 
+    .fre_mode(fre_mode), 
+    .R_CAL(R_CAL4_r)
+    );
+
+
+T_CAL T_CAL__ (
+    .i_clk(i_clk), 
+    .i_rstn(i_rstn), 
+    .SW(SW), 
+    .i_temp(i_temp), 
+    .hop_fre_mode(hop_fre_mode), 
+    .T_CAL_(T_CAL_r)
+    );
+
+
+spi_tx SPI_TX (
+    .clk		(i_clk			)	, 
+    .rstn		(i_rstn			)	, 
+    .tx_en		(tx_en			)	, 
+    .data_in	(data_in		)	, 
+    .spi_cs		(ENABLE			)	, 
+    .spi_sclk	(SC				)	, 
+    .spi_sdo	(SD				)	,
+    .DARY		(END_SYN		)		
+    );
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+endmodule

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/mgc_ctrl.v

@@ -0,0 +1,434 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    19:54:29 09/06/2021 
+// Design Name: 
+// Module Name:    mgc_ctrl 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module mgc_ctrl(
+input			i_sys_clk		,
+input			i_rst_n			,
+input			i_TR_SW_F		,
+input			i_TP_EN_F		,	
+input			i_CAL_F			,	
+input			i_T_MGC_EN_F	,	
+input			i_R_MGC_EN_F	,	
+
+input	[15:0]	i_fre_code	,	
+input	[7:0]	i_tx_mgc	,
+input	[7:0]	i_rx1_mgc	,
+input	[7:0]	i_rx2_mgc	,
+input	[7:0]	i_rx3_mgc	,
+input	[7:0]	i_rx4_mgc	,
+input   [3:0]	i_ceshi_module,
+output	[15:0]	o_current_fre_code,
+output	[15:0]	o_cal_fre_code,
+output	[15:0]	o_hop_fre_code,
+output			o_adf4371_hop1,
+output			o_adf4371_hop2,
+
+output			o_SW,
+output			o_SW2,
+output			o_SW3,
+output			o_SW_C1,
+
+//发射通道MGC控制，高衰。31dB，步进1dB。初始态直通（全置1）
+output	o_T_MGC_1dB,
+output	o_T_MGC_2dB,
+output	o_T_MGC_4dB,
+output	o_T_MGC_8dB,
+output	o_T_MGC_16dB,
+//接收通道1MGC控制，高衰。31dB，步进1dB。初始态直通（全置1）
+output reg[7:0]	o_R_MGC_1,
+
+//接收通道2MGC控制，高衰。31dB，步进1dB。初始态直通（全置1）
+output reg[7:0]	o_R_MGC_2,
+
+//接收通道3MGC控制，高衰。31dB，步进1dB。初始态直通（全置1）
+output reg[7:0]	o_R_MGC_3,
+//接收通道4MGC控制，高衰。31dB，步进1dB。初始态直通（全置1）
+output reg[7:0]	o_R_MGC_4
+
+);
+
+
+reg				TR_SW_F;
+reg		[2:0]	TP_EN_r;
+reg		[2:0]	T_MGC_EN_r;
+reg		[2:0]	R_MGC_EN_r;
+reg		[2:0]	R_CAL_F;
+reg		[15:0]	hop_fre_code;
+reg		[15:0]	current_fre_code;
+wire		[15:0]	cal_fre_code;
+reg		[47:0]	fre_code_a_b;
+reg				hop_en;
+reg				hop_en_r;
+reg				hop_en_rr;
+reg				cfg_en;
+reg				cfg_en_r;
+reg				cfg_en_rr;
+reg				hmc704_1_hop;
+reg				hmc704_2_hop;
+reg		[1:0]	cnt_cfg;
+reg		[1:0]	cnt_hop;
+
+
+reg		sw1;
+reg		sw2;
+reg		sw3;
+reg		SW_C1;
+
+reg		T_MGC_1dB_r	;
+reg		T_MGC_2dB_r	;
+reg		T_MGC_4dB_r	;
+reg		T_MGC_8dB_r	;
+reg		T_MGC_16dB_r;
+
+assign o_SW				= sw1;
+assign o_SW2			= sw2;
+assign o_SW3			= sw3;
+assign o_SW_C1			= SW_C1;
+
+assign o_current_fre_code= current_fre_code;
+assign o_cal_fre_code	= cal_fre_code;
+assign o_hop_fre_code	= hop_fre_code;
+assign o_adf4371_hop1	= hmc704_1_hop;
+assign o_adf4371_hop2	= hmc704_2_hop;
+
+assign	o_T_MGC_1dB		= T_MGC_1dB_r	;
+assign	o_T_MGC_2dB		= T_MGC_2dB_r	;
+assign	o_T_MGC_4dB		= T_MGC_4dB_r	;
+assign	o_T_MGC_8dB		= T_MGC_8dB_r	;
+assign	o_T_MGC_16dB	= T_MGC_16dB_r	;
+
+
+always@(posedge i_sys_clk or negedge i_rst_n)begin
+if(!i_rst_n)begin
+    TR_SW_F 	<= 1'b0;
+    TP_EN_r 	<= 3'b0;
+	T_MGC_EN_r	<= 3'b0;
+	R_MGC_EN_r	<= 3'b0;
+	R_CAL_F		<= 3'b0;
+end
+else begin
+	TR_SW_F 	<= i_TR_SW_F;
+	TP_EN_r		<= {TP_EN_r[1:0]	,i_TP_EN_F};
+	T_MGC_EN_r	<= {T_MGC_EN_r[1:0]	,i_T_MGC_EN_F};
+	R_MGC_EN_r	<= {R_MGC_EN_r[1:0]	,i_R_MGC_EN_F};
+	R_CAL_F		<= {R_CAL_F[1:0]	,i_CAL_F};
+end
+end
+
+always@(posedge i_sys_clk or negedge i_rst_n)begin
+if(!i_rst_n)begin
+	SW_C1	<= 1'b0;
+	current_fre_code <= 16'h6d6 ;
+end
+else begin
+	current_fre_code <= hop_en ? hop_fre_code : current_fre_code ;
+	if(TR_SW_F==1'b1)begin
+		if(current_fre_code<=1500)//20.375Ghz~21.875Ghz
+			SW_C1	<= 1'b1;
+		else 				 //21.875Ghz~23.875Ghz
+			SW_C1	<= 1'b0;
+	end
+	else begin
+		SW_C1	<= SW_C1;
+	end
+end
+end
+
+
+assign	cal_fre_code = R_CAL_F==3'b001 ? hop_fre_code : cal_fre_code ;
+
+
+
+
+always@(posedge i_sys_clk or negedge i_rst_n)begin
+if(!i_rst_n)begin
+	fre_code_a_b	<= 48'h0000000006d6;
+end
+else if(cfg_en)begin
+	fre_code_a_b	<= {fre_code_a_b[31:0],i_fre_code};
+end
+else begin
+	fre_code_a_b <= fre_code_a_b;
+end
+end
+
+always@(posedge i_sys_clk or negedge i_rst_n)begin
+if(!i_rst_n)begin
+	hop_en	<= 1'b0;
+end
+else if(TP_EN_r==3'b011)begin
+	hop_en	<= 1'b1;
+end
+else begin
+	hop_en <= 1'b0;
+end
+end
+
+always@(posedge i_sys_clk or negedge i_rst_n)begin
+if(!i_rst_n)begin
+    hop_fre_code <= 16'h6d6;
+end
+else begin
+    hop_fre_code <= i_fre_code;
+end
+end
+
+
+always@(posedge i_sys_clk or negedge i_rst_n)begin
+if(!i_rst_n)begin
+    cfg_en <= 1'b0;
+end
+else if(hop_fre_code != i_fre_code)begin
+    cfg_en <= 1'b1;
+end
+else begin
+    cfg_en <= 1'b0;
+end
+end
+
+
+always @ (posedge i_sys_clk or negedge i_rst_n)begin
+if(!i_rst_n)begin
+	hop_en_r <= 1'b0;
+	hop_en_rr <= 1'b0;
+end
+else begin
+	hop_en_r <= hop_en;
+	hop_en_rr <= hop_en_r;
+end
+end
+
+always @ (posedge i_sys_clk or negedge i_rst_n)begin
+if(!i_rst_n)begin
+	cfg_en_r <= 1'b0;
+	cfg_en_rr <= 1'b0;
+end
+else begin
+	cfg_en_r <= cfg_en;
+	cfg_en_rr <= cfg_en_r;
+end
+end
+
+reg [15:0] pre_hop_fre_code;
+always @ (posedge i_sys_clk or negedge i_rst_n)begin
+if(!i_rst_n)begin
+	cnt_hop <= 2'b00;
+end
+else if(cnt_hop == 2'b10)begin
+	cnt_hop <= 2'b00;
+end
+else if(~hop_en_r & hop_en && (pre_hop_fre_code!=hop_fre_code ))begin
+	cnt_hop <= cnt_hop + 1'b1;
+end
+else begin
+	cnt_hop <= cnt_hop;
+end
+end
+
+always @ (posedge i_sys_clk or negedge i_rst_n)begin
+if(!i_rst_n)begin
+	cnt_cfg <= 2'b00;
+end
+else if(cnt_cfg == 2'b10)begin
+	cnt_cfg <= 2'b00;
+end
+else if(~cfg_en_r&cfg_en)begin
+	cnt_cfg <= cnt_cfg + 1'b1;
+end
+else begin
+	cnt_cfg <= cnt_cfg;
+end
+end
+
+always @ (posedge i_sys_clk or negedge i_rst_n)begin
+if(!i_rst_n)
+	pre_hop_fre_code<=16'h6d6;
+else if(hop_en_rr)
+	pre_hop_fre_code<=hop_fre_code;
+else
+	pre_hop_fre_code<=pre_hop_fre_code;
+end
+	
+always @ (posedge i_sys_clk or negedge i_rst_n)begin
+if(!i_rst_n)begin
+	sw1 <= 1'b1;
+	sw2 <= 1'b1;
+	sw3 <= 1'b0;
+end
+else if(i_ceshi_module==4'ha)//自动校准开关到a
+begin
+	sw1 <= 1'b0;
+	sw2 <= 1'b0;
+	sw3 <= 1'b1;
+end
+else if(i_ceshi_module==4'hb)//自动校准开关到b
+begin
+	sw1 <= 1'b1;
+	sw2 <= 1'b1;
+	sw3 <= 1'b0;
+end
+else if(hop_en_rr && pre_hop_fre_code != hop_fre_code)begin
+	if(cnt_hop == 2'b01)begin
+		sw1 <= 1'b0;
+		sw2 <= 1'b0;
+		sw3 <= 1'b1;
+	end
+	else begin
+		sw1 <= 1'b1;
+		sw2 <= 1'b1;
+		sw3 <= 1'b0;
+	end
+end
+else begin
+	sw1 <= sw1;
+	sw2 <= sw2;
+	sw3 <= sw3;
+end
+end 
+
+always @ (posedge i_sys_clk or negedge i_rst_n)begin
+if(!i_rst_n)begin
+	hmc704_1_hop <= 1'b0;
+	hmc704_2_hop <= 1'b0;
+end
+else if(i_ceshi_module==4'ha&&cfg_en_rr)begin
+	hmc704_1_hop <= 1'b1;
+	hmc704_2_hop <= 1'b0;
+end	
+else if(i_ceshi_module==4'hb&&cfg_en_rr)begin
+	hmc704_1_hop <= 1'b0;
+	hmc704_2_hop <= 1'b1;
+end
+else if(cfg_en_rr)begin
+	if(fre_code_a_b[47:32]==fre_code_a_b[15:0])begin
+		hmc704_1_hop <= 1'b0;
+		hmc704_2_hop <= 1'b0;
+	end	
+	else if(cnt_cfg == 2'b01)begin
+		hmc704_1_hop <= 1'b1;
+		hmc704_2_hop <= 1'b0;
+	end
+	else begin
+		hmc704_1_hop <= 1'b0;
+		hmc704_2_hop <= 1'b1;
+	end
+end
+else begin
+	hmc704_1_hop <= 1'b0;
+	hmc704_2_hop <= 1'b0;
+end
+end  
+
+/*   always @ (posedge i_sys_clk or negedge i_rst_n)begin
+if(!i_rst_n)begin
+	sw1 <= 1'b1;
+	sw2 <= 1'b1;
+	sw3 <= 1'b0;
+end
+end
+
+always @ (posedge i_sys_clk or negedge i_rst_n)begin
+if(!i_rst_n)begin
+	hmc704_1_hop <= 1'b0;
+	hmc704_2_hop <= 1'b0;
+end
+else if(cfg_en_rr)begin
+	hmc704_1_hop <= 1'b0;
+	hmc704_2_hop <= 1'b1;
+end
+else begin
+	hmc704_1_hop <= 1'b0;
+	hmc704_2_hop <= 1'b0;
+end
+end  */ 
+ 
+
+
+
+always@(posedge i_sys_clk or negedge i_rst_n)begin
+if(!i_rst_n)begin
+    T_MGC_1dB_r		<= 1'b0;
+	T_MGC_2dB_r		<= 1'b0;
+	T_MGC_4dB_r		<= 1'b0;
+	T_MGC_8dB_r		<= 1'b0;
+	T_MGC_16dB_r	<= 1'b0;
+end
+else if(i_ceshi_module==4'ha || i_ceshi_module==4'hb )begin
+    T_MGC_1dB_r		<= 1'b0;
+	T_MGC_2dB_r		<= 1'b0;
+	T_MGC_4dB_r		<= 1'b0;
+	T_MGC_8dB_r		<= 1'b0;
+	T_MGC_16dB_r	<= 1'b0;
+end
+else if(T_MGC_EN_r==3'b011)begin
+    T_MGC_1dB_r		<= i_tx_mgc[0];	
+	T_MGC_2dB_r		<= i_tx_mgc[1];
+	T_MGC_4dB_r		<= i_tx_mgc[2];
+	T_MGC_8dB_r		<= i_tx_mgc[3];
+	T_MGC_16dB_r	<= i_tx_mgc[4];
+end
+else begin
+    T_MGC_1dB_r		<= T_MGC_1dB_r	;
+	T_MGC_2dB_r		<= T_MGC_2dB_r	;
+	T_MGC_4dB_r		<= T_MGC_4dB_r	;
+	T_MGC_8dB_r		<= T_MGC_8dB_r	;
+	T_MGC_16dB_r	<= T_MGC_16dB_r	;
+end
+end
+
+always@(posedge i_sys_clk or negedge i_rst_n)begin
+if(!i_rst_n)begin
+    o_R_MGC_1	<= 1'b0;
+end
+else if(R_MGC_EN_r==3'b011)begin
+    o_R_MGC_1	<= i_rx1_mgc;
+end
+end
+
+always@(posedge i_sys_clk or negedge i_rst_n)begin
+if(!i_rst_n)begin
+    o_R_MGC_2	<= 1'b0;
+end
+else if(R_MGC_EN_r==3'b011)begin
+    o_R_MGC_2	<= i_rx2_mgc;
+end
+end
+
+always@(posedge i_sys_clk or negedge i_rst_n)begin
+if(!i_rst_n)begin
+    o_R_MGC_3	<= 1'b0;
+end
+else if(R_MGC_EN_r==3'b011)begin
+    o_R_MGC_3	<= i_rx3_mgc;
+end
+end
+
+always@(posedge i_sys_clk or negedge i_rst_n)begin
+if(!i_rst_n)begin
+    o_R_MGC_4	<= 1'b0;
+end
+else if(R_MGC_EN_r==3'b011)begin
+    o_R_MGC_4	<= i_rx4_mgc;
+
+end
+end
+
+
+endmodule

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/mod2_rom.v

@@ -0,0 +1,71 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    15:35:03 01/27/2022 
+// Design Name: 
+// Module Name:    mod2_rom 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module mod2_rom(
+input   sysclk,
+input [11 : 0] addra,
+
+output reg[13:0] douta
+);
+
+reg[11:0]	addr=0;
+always@(posedge sysclk)begin
+	addr<=addra%25;	
+end
+
+always@(posedge sysclk)begin
+	case(addr)
+0	:	douta	<=	1	;
+1	:	douta	<=	25	;
+2	:	douta	<=	25	;
+3	:	douta	<=	25	;
+4	:	douta	<=	25	;
+5	:	douta	<=	5	;
+6	:	douta	<=	25	;
+7	:	douta	<=	25	;
+8	:	douta	<=	25	;
+9	:	douta	<=	25	;
+10	:	douta	<=	5	;
+11	:	douta	<=	25	;
+12	:	douta	<=	25	;
+13	:	douta	<=	25	;
+14	:	douta	<=	25	;
+15	:	douta	<=	5	;
+16	:	douta	<=	25	;
+17	:	douta	<=	25	;
+18	:	douta	<=	25	;
+19	:	douta	<=	25	;
+20	:	douta	<=	5	;
+21	:	douta	<=	25	;
+22	:	douta	<=	25	;
+23	:	douta	<=	25	;
+24	:	douta	<=	25	;
+default:douta	<=	douta	;
+endcase
+
+end
+
+
+
+
+
+
+
+endmodule

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/spi_master.v

@@ -0,0 +1,150 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    20:42:39 09/29/2021 
+// Design Name: 
+// Module Name:    spi_master 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module spi_master #(parameter    BIT_NUM  = 95	)(
+	input			i_clk				,
+	input			debug_clk			,
+	input			i_sys_rst_n			,
+	input			i_spi_sck			,
+	input			i_spi_cs			,
+	output			o_spi_sdo			,
+	input			i_spi_sdi			,
+	input			i_LD_LO3			,
+	input   		i_LD1				, 
+    input			i_LD2				,
+    input[3:0]		i_cal1_mgc			,
+    input[3:0]		i_cal2_mgc			,
+    input[3:0]		i_cal3_mgc			,
+    input[3:0]		i_cal4_mgc			,
+	input[7:0]		i_temp				,
+	input[31:0]		i_frame_count
+
+);
+  
+wire [BIT_NUM:0]  data		;
+reg [BIT_NUM:0]  data_r	;
+reg [BIT_NUM:0]  data_reg	;
+assign 		data={	8'hAA					,
+					i_temp					,
+					7'b0,i_LD_LO3			,
+					7'b0,i_LD1				,
+					7'b0,i_LD2				,
+					i_cal1_mgc,i_cal2_mgc	,
+					i_cal3_mgc,i_cal4_mgc	,
+					i_frame_count			,
+					8'hCC						}		;
+					
+wire		spi_sck		;	 
+wire		spi_cs		;
+reg			spi_sdo		;
+reg	[2:0]	reg_cs		;
+reg	[31:0]	cnt			;
+
+assign	spi_sck		=	i_spi_sck;
+assign	spi_cs 		=	i_spi_cs;
+assign	o_spi_sdo 	=	spi_sdo;
+
+always@(negedge spi_sck,negedge i_sys_rst_n)begin
+	if(!i_sys_rst_n)
+		reg_cs<=3'b111;
+	else 	
+		reg_cs<={reg_cs[1:0],i_spi_cs};
+end
+
+always@(negedge spi_sck,negedge i_sys_rst_n)begin
+	if(!i_sys_rst_n)
+		data_r<={8'hAA,80'b0,8'hCC};
+	else if(reg_cs[2:1]==2'b10)
+		data_r<={8'hAA,data[87:8],8'hCC};
+end
+	
+always@(negedge spi_sck,negedge i_sys_rst_n)begin
+	if(!i_sys_rst_n)
+		spi_sdo	<=	1'b0	;
+	else if(!spi_cs)
+		spi_sdo <= data_r[cnt];
+	else
+		spi_sdo	<=	1'b0	;
+end
+
+always@(posedge spi_sck,negedge i_sys_rst_n)begin
+	if(!i_sys_rst_n)
+		cnt<=BIT_NUM;
+	else if(spi_cs==1 | cnt==0)
+		cnt<=BIT_NUM;
+	else 
+		cnt<=cnt-1;
+end
+
+//------------debug------------
+always@(posedge  spi_sck,negedge i_sys_rst_n)begin
+	if(!i_sys_rst_n)
+		data_reg	<=	0	;
+	else if(!spi_cs)
+		data_reg <= {data_reg,spi_sdo}	;
+	else
+		data_reg	<=	data_reg	;
+end
+//------------debug------------	 
+
+/*  
+wire [40:0]		SYNC_OUT		;
+wire [35:0]		CONTROL0	;
+wire [35:0]		CONTROL1	;
+wire [150:0]	TRIG0		;
+
+vio u_vio (
+    .CONTROL	(CONTROL0),	// INOUT BUS [35:0]
+    .CLK		(i_clk),	// IN
+    .SYNC_OUT	(SYNC_OUT)	// OUT BUS [33:0]
+);
+
+
+icon u_icon (
+    .CONTROL0	(CONTROL0),	// INOUT BUS [35:0]
+    .CONTROL1	(CONTROL1)	// INOUT BUS [35:0]
+);
+
+
+ila u_ila (
+    .CONTROL	(CONTROL1), // INOUT BUS [35:0]
+    .CLK		(debug_clk), // IN
+    .TRIG0		(TRIG0) // IN BUS [39:0]
+);
+
+
+assign TRIG0[0]				= i_LD_LO3;
+assign TRIG0[1]				= i_LD1	;
+assign TRIG0[2]				= i_LD2	;
+assign TRIG0[98:3]			= data_r		;
+assign TRIG0[101:99]		= reg_cs		;
+assign TRIG0[132:102]		= cnt		;
+assign TRIG0[133]		= i_spi_sck					;
+assign TRIG0[134]		= i_spi_cs					;
+assign TRIG0[135]		= o_spi_sdo					;
+assign TRIG0[136]		= i_spi_sdi					;
+
+ */
+
+
+
+
+
+endmodule

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/spi_salve.v

@@ -0,0 +1,171 @@
+
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2020/09/02 10:48:55
+// Design Name: 
+// Module Name: d
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// SPI时钟频率50MHz。每一帧数据12个字节，共96bit数据。
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module spi_slave#(
+    parameter              BIT_NUM  = 96
+)
+(
+input			i_sys_clk,
+input			i_sys_rst_n,
+			
+input			i_spi_sck,		//从机在时钟下降沿采样数据
+input			i_spi_cs,		//低电平时从机接收数据指令
+input			i_spi_sdi,
+output	[31:0]	o_frame_count,  //帧计数
+output	[15:0]	o_fre_code	 , 	//天线频率
+output	[7:0]	o_tx_mgc,   	//发射MGC
+output	[3:0]	o_model,    	//模式字
+output	[3:0]	o_rf_en,    	//射频使能
+output	[3:0]	o_cal1_mgc, 	//接收校准1mgc
+output	[3:0]	o_cal2_mgc, 	//接收校准2mgc
+output	[3:0]	o_cal3_mgc, 	//接收校准3mgc
+output	[3:0]	o_cal4_mgc, 	//接收校准4mgc
+output	[7:0]	o_tx_cal_mgc, 	//发射校准mgc
+output	[7:0]	o_rx1_mgc,  	//接收1mgc
+output	[7:0]	o_rx2_mgc,  	//接收2mgc
+output	[7:0]	o_rx3_mgc,  	//接收3mgc
+output	[7:0]	o_rx4_mgc  , 	//接收4mgc
+
+output	[3:0]	o_ceshi_model  	  	
+);
+        
+reg	[BIT_NUM -1:0]			receive_data;
+reg		[3:0]				rf_en 	 ;
+reg		[3:0]				model;
+reg		[31:0]				frame_count;
+reg		[11:0]				fre_code;
+reg		[7:0]				tx_mgc;
+reg		[7:0]				rx1_mgc;
+reg		[7:0]				rx2_mgc;
+reg		[7:0]				rx3_mgc;
+reg		[7:0]				rx4_mgc;
+reg		[3:0]				cal1_mgc;
+reg		[3:0]				cal2_mgc;
+reg		[3:0]				cal3_mgc;
+reg		[3:0]				cal4_mgc;
+reg		[7:0]				tx_cal_mgc;
+reg		[3:0]				ceshi_module;
+
+
+assign o_frame_count= frame_count;
+assign o_fre_code	= {4'b0,fre_code};
+assign o_rf_en		= rf_en;
+assign o_model		= model;
+assign o_tx_mgc		= tx_mgc;
+assign o_cal1_mgc	= cal1_mgc;
+assign o_cal2_mgc	= cal2_mgc;
+assign o_cal3_mgc	= cal3_mgc;
+assign o_cal4_mgc	= cal4_mgc;
+assign o_tx_cal_mgc	= tx_cal_mgc;
+assign o_rx1_mgc	= rx1_mgc;
+assign o_rx2_mgc	= rx2_mgc;
+assign o_rx3_mgc	= rx3_mgc;
+assign o_rx4_mgc	= rx4_mgc;
+assign o_ceshi_model	= ceshi_module;
+
+always @ ( negedge  i_spi_sck or negedge i_sys_rst_n)begin
+if( !i_sys_rst_n )
+    receive_data <= 'b0;
+else if(i_spi_cs == 1'b0)
+	receive_data <= {receive_data,i_spi_sdi}; 
+else 
+	receive_data <= receive_data;
+end
+
+
+reg [2:0]  cs_reg;
+
+always @ ( posedge  i_sys_clk or negedge i_sys_rst_n)begin
+if( !i_sys_rst_n )
+    cs_reg <= 3'b111;
+else  
+	cs_reg <= {cs_reg[1:0],i_spi_cs}; 
+end
+
+
+
+always @ ( posedge  i_sys_clk or negedge i_sys_rst_n)begin
+if(!i_sys_rst_n)begin
+	tx_cal_mgc<=8'h0;
+end
+else if(cs_reg[2:1]==2'b01 && (receive_data[95:88] == 8'hbb) && (receive_data[7:0] == 8'hdd))begin
+	tx_cal_mgc<=receive_data[15:8];
+end
+else begin
+	tx_cal_mgc<=tx_cal_mgc;
+end
+end
+
+always @ ( posedge  i_sys_clk or negedge i_sys_rst_n)begin
+if(!i_sys_rst_n)begin
+	fre_code	<= 12'h6d6;
+	tx_mgc		<= 8'h00;
+	rf_en		<= 4'b1;
+	model		<= 4'b0;
+	frame_count	<= 32'd1;
+	rx1_mgc		<= 4'h0;
+	rx2_mgc		<= 4'h0;
+	rx3_mgc		<= 4'h0;
+	rx4_mgc		<= 4'h0;
+	cal1_mgc	<= 4'h0;
+	cal2_mgc	<= 4'h0;
+	cal3_mgc	<= 4'h0;
+	cal4_mgc	<= 4'h0;	
+	ceshi_module	<= 4'h0;	
+end
+else if(cs_reg[2:1]==2'b01 && (receive_data[95:88] == 8'haa) && (receive_data[7:0] == 8'hcc))begin
+	frame_count <= frame_count+1'b1;
+	rf_en		<= receive_data[87:84];
+	model		<= receive_data[83:80];
+	ceshi_module<= receive_data[79:76];
+	fre_code	<= receive_data[75:64];
+	tx_mgc		<= receive_data[63:56];
+	cal1_mgc	<= receive_data[55:52];
+	cal2_mgc	<= receive_data[51:48];
+	cal3_mgc	<= receive_data[47:44];
+	cal4_mgc	<= receive_data[43:40];
+	rx1_mgc		<= receive_data[39:32];
+	rx2_mgc		<= receive_data[31:24];
+	rx3_mgc		<= receive_data[23:16];
+	rx4_mgc		<= receive_data[15:8];
+end
+else begin
+	frame_count <= frame_count     ;
+	rf_en		<= rf_en		      ;
+	model		<= model		      ;
+	fre_code	<= fre_code	      ;
+	tx_mgc		<= tx_mgc		  ;
+	cal1_mgc	<= cal1_mgc	      ;
+	cal2_mgc	<= cal2_mgc	      ;
+	cal3_mgc	<= cal3_mgc	      ;
+	cal4_mgc	<= cal4_mgc	      ;
+	rx1_mgc		<= rx1_mgc		  ;
+	rx2_mgc		<= rx2_mgc		  ;
+	rx3_mgc		<= rx3_mgc		  ;
+	rx4_mgc		<= rx4_mgc		  ;
+end
+end
+   
+               
+endmodule

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/Sisyif_src/spi_tx.v

@@ -0,0 +1,118 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    15:23:58 10/12/2020 
+// Design Name:    spi发送模块
+// Module Name:    spi 
+// Project Name:   
+// Target Devices: 
+// Tool versions: 
+// Description: 
+// 
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module spi_tx #(parameter WHITH=32)(  
+input 				clk,//系统时钟
+input 				rstn,//异步复位
+input 				tx_en,//发送使能
+input [WHITH-1:0]   data_in,//待发送数据
+output reg 			spi_cs, //片选 
+output reg 			spi_sclk, //同步时钟，等于clk/2
+output reg 			spi_sdo, //发送数据的线
+output reg 			DARY 	
+);					
+
+//localparam [1:0] polaeity = 2'b10;//negedge 数据下降沿保持
+localparam [1:0] polaeity = 2'b01;//posedge 数据上降沿保持
+reg  [2:0] 		 	state ; //状态机
+reg  [WHITH-1:0] 	reg_data;//移位寄存器
+reg  [5:0]		 	cnt;//计数器，必须大于数据位宽
+
+wire	CPOL      			 ;	//时钟空闲时电平				
+wire	CPHA      			 ;	//极性
+assign 	CPOL = polaeity[0]	 ;		
+assign 	CPHA = polaeity[1]	 ;
+
+always @(posedge clk,negedge rstn)begin
+if(!rstn)begin
+	state 	 <= 3'd0;
+	spi_cs   <= 1'b1;
+	spi_sclk <= CPOL;
+	reg_data <= 1'd0;
+	cnt      <=	5'b0;
+	spi_sdo  <= 1'b0;
+	DARY  <= 1'b1;
+end
+else begin 
+	case(state)
+	3'd0:begin//空闲态
+		spi_sclk 	<=  CPOL			;
+		spi_cs		<=	1'b1			;
+		spi_sdo     <=  1'b0			;
+		DARY    	 <=  1'b1			;
+		cnt      	<=	5'b0			;
+		reg_data    <=	data_in			;
+		if(tx_en)//发送使能跳下一个状态
+			state	<=	3'd1            ;
+		else                         
+			state	<=	state           ;
+	end
+	3'd1:begin
+		spi_cs	 <=	1'b0					 ;
+		state	 <=	3'd2				;
+		reg_data    <=	data_in			;
+	end
+	3'd2:begin//数据移位态
+		spi_cs	 <=	1'b0					 ;
+		reg_data <= reg_data<<1'b1			 ;
+		spi_sdo  <= reg_data[WHITH-1]		 ;
+		spi_sclk <= CPHA					 ;
+		state	 <= (cnt >= WHITH-1) ? 3'd4:3'd3;
+	end
+	3'd3:begin//时钟翻转		 
+		cnt      <= cnt+1'b1				 ;
+		spi_sclk <= ~CPHA					 ;
+		state	 <= 3'd2					 ;
+	end
+	3'd4:begin//结束态
+		state 	 <= 3'd5;
+		spi_sclk <= ~CPHA;
+	end
+	3'd5:begin//结束态
+		state 	 <= 3'd6;
+		DARY <= 0;	
+		spi_sdo  <=  1'b0			;
+		spi_cs		<=	1'b1			;
+	end	
+	3'd6:begin//结束态
+		state 	 <= 3'd7;
+		DARY <= 1;	
+		spi_cs		<=	1'b1			;
+	end
+	3'd7:begin//结束态
+		state 	 <= 3'd8;
+		DARY <= 0;
+	end
+	3'd8:begin//结束态
+		state 	 <= 3'd0;
+		DARY <= 1;			
+	end	
+	default :state<=3'd0;
+	endcase
+end
+end
+
+
+
+
+
+
+
+endmodule

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/ant_rf/ant_rf_ctrl.v

@@ -0,0 +1,515 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 2022/07/13 14:20:24
+// Design Name:
+// Module Name: ant_rf_ctrl
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module ant_rf_ctrl
+(
+    input           clk_48m         ,
+    input           clk_96m         ,
+    input           clk_32m         ,
+    input           clk_19p2m       ,
+    input           sys_rst         ,
+
+    output          ant_clk         ,
+    output          ant_en          ,
+    output          ant_data        ,
+    output          ant_tr          ,
+    output          ant_dary        ,
+    input           ant_dout        ,
+
+    output          rf_standby      ,
+    output          rf_sw_pll       ,
+    output          rf_t            ,
+    output          rf_r            ,
+    output          rf_sw_bpf       ,
+    output          rf_sclk1        ,
+    output          rf_sdio1        ,
+    output          rf_cs1          ,
+    input           rf_ld1          ,
+    output          rf_sclk2        ,
+    output          rf_sdio2        ,
+    output          rf_cs2          ,
+    input           rf_ld2          ,
+    output          rf_sclk3        ,
+    output          rf_sdio3        ,
+    output          rf_cs3          ,
+    input           rf_ld3          ,
+    output          rf_tmgc_16      ,
+    output          rf_tmgc_8       ,
+    output          rf_tmgc_4       ,
+    output          rf_tmgc_2       ,
+    output          rf_tmgc_1       ,
+    output          rf_rmgc_16      ,
+    output          rf_rmgc_8       ,
+    output          rf_rmgc_4       ,
+    output          rf_rmgc_2       ,
+    output          rf_rmgc_1       ,
+    output          rf_enable       ,
+    output          rf_sc           ,
+    output          rf_sd           ,
+    output          rf_endsyn       ,
+    input           rf_sdout        ,
+    inout           rf_dq_wd        ,
+    output          rf_sw_rx
+);
+
+
+(*dont_touch = "true"*) wire        vio_switch      ; // 键控开关，沿有效
+(*dont_touch = "true"*) wire        vio_trdirection ; // 收发方向
+(*dont_touch = "true"*) wire [15:0] vio_frequency   ; // 收发频率
+(*dont_touch = "true"*) wire [ 7:0] vio_emitMGC     ; // 发送MGC
+(*dont_touch = "true"*) wire [ 3:0] vio_ch01MGC     ; // 1通道校准MGC
+(*dont_touch = "true"*) wire [ 3:0] vio_ch02MGC     ; // 2通道校准MGC
+(*dont_touch = "true"*) wire [ 3:0] vio_ch03MGC     ; // 3通道校准MGC
+(*dont_touch = "true"*) wire [ 3:0] vio_ch04MGC     ; // 4通道校准MGC
+(*dont_touch = "true"*) wire [ 7:0] vio_recvMGC     ; // 接收MGC
+(*dont_touch = "true"*) wire [ 7:0] vio_AntMod      ; // 天线工作模式
+(*dont_touch = "true"*) wire [15:0] vio_AntOffAxis  ; // 天线离轴角
+(*dont_touch = "true"*) wire [15:0] vio_AntYaw      ; // 天线偏航角
+(*dont_touch = "true"*) wire [15:0] vio_PrecessTime ; // 处理时间，从EN拉低到DARY拉低
+
+(*dont_touch = "true"*)wire         vio_mode_ant    ; // 0定频手动，1扫频模式
+(*dont_touch = "true"*)wire         vio_hop_start   ; // 0跳频终止，1重新跳频
+(*dont_touch = "true"*)wire         vio_standby     ; // 1待机模式，0工作模式
+(*dont_touch = "true"*)wire  [15:0] vio_hoptime     ; // 单跳时间计数器
+
+reg Ant_switch_D1 = 0;
+reg data_valid = 0;
+reg switch_valid = 0;
+reg [95:0] RF_CtrlWord = 0;
+reg [127:0] Ant_CtrlWord = 0;
+reg [15:0] data_valid_countdown = 0;
+reg [15:0] rst_countdown = 100;
+reg [95:0] RF_CtrlWord_running = 0;
+reg [127:0] Ant_CtrlWord_running = 0;
+reg rst_n = 0;
+reg SPI_SYN_F = 1;
+reg SPI_MOSI_F = 1;
+reg TP_EN_F = 0;
+reg TR_MGC_F = 0;
+reg CAL_F = 0;
+reg PRF = 0;
+wire SPI_MISO_F;
+reg Ant_DATA = 0;
+reg Ant_EN = 0;
+reg Ant_DARY = 0;
+reg Ant_TR = 0;
+
+
+
+//相控阵测试程序
+reg 	[15:0] 	cnt_freq_change = 16'd0;
+
+reg  			Ant_switch	 ; // 键控开关，沿有效
+reg  	[15:0] 	Ant_frequency; // 收发频率
+reg		[ 7:0]  Ant_mode	 ; // 相控阵模式
+reg		[ 7:0]  RF_mode		 ; // 射频模式
+
+always @ (posedge clk_48m) begin
+    if(sys_rst) begin
+        Ant_switch            <=  1'b0;
+        cnt_freq_change[15:0] <= 16'd0;
+        Ant_frequency[15:0]   <= 16'd0;
+        RF_mode[7:0]          <= 8'h10;
+        Ant_mode[7:0]         <= 8'h0f;
+    end
+    else begin
+        if(vio_mode_ant) begin
+            if(vio_hop_start) begin
+                if(cnt_freq_change[15:0] == (vio_hoptime[15:0] - 16'd1)) begin
+                    Ant_switch            <= ~Ant_switch;
+                    if(Ant_frequency[15:0] == 16'd3500) begin
+                        Ant_frequency[15:0]   <= 16'd0;
+                    end
+                    else begin
+                        Ant_frequency[15:0]   <= Ant_frequency[15:0] + 16'd1;
+                    end
+                    cnt_freq_change[15:0] <= 16'd0;
+                end
+                else begin
+                    Ant_switch            <= Ant_switch;
+                    Ant_frequency[15:0]   <= Ant_frequency[15:0];
+                    cnt_freq_change[15:0] <= cnt_freq_change[15:0] + 16'd1;
+                end
+            end
+            else begin
+                Ant_switch            <= Ant_switch;
+                Ant_frequency[15:0]   <= 16'd0;
+                cnt_freq_change[15:0] <= 16'd0;
+            end
+        end
+        else begin
+            Ant_switch            <= vio_switch;
+            Ant_frequency[15:0]   <= vio_frequency[15:0];
+            cnt_freq_change[15:0] <= 16'd0;
+        end
+
+        if(vio_standby) begin
+            RF_mode[7:0]  <= 8'h10;
+            Ant_mode[7:0] <= 8'h0f;
+        end
+        else begin
+            RF_mode[7:0]  <= 8'h00;
+            Ant_mode[7:0] <= vio_AntMod[7:0];
+        end
+    end
+
+end
+
+always @(posedge clk_48m)
+	begin
+		Ant_switch_D1 <= Ant_switch;
+		if(Ant_switch_D1 != Ant_switch)
+			switch_valid <= 1'b1;
+		else
+			switch_valid <= 1'b0;
+
+		if(switch_valid)
+			begin
+			RF_CtrlWord[95:88] <= 8'hAA;
+			RF_CtrlWord[87:80] <= RF_mode[7:0];
+			RF_CtrlWord[79:64] <= Ant_frequency[15:0];
+			RF_CtrlWord[63:56] <= vio_emitMGC[7:0];
+			RF_CtrlWord[55:52] <= vio_ch01MGC[3:0];
+			RF_CtrlWord[51:48] <= vio_ch02MGC[3:0];
+			RF_CtrlWord[47:44] <= vio_ch03MGC[3:0];
+			RF_CtrlWord[43:40] <= vio_ch04MGC[3:0];
+			RF_CtrlWord[39:32] <= vio_recvMGC[7:0];
+			RF_CtrlWord[31:8] <= 24'h00_0000;
+			RF_CtrlWord[7:0] <= 8'hCC;
+
+			Ant_CtrlWord[127:120] <= 8'hAA;
+			Ant_CtrlWord[119:112] <= 8'h00;
+			Ant_CtrlWord[111:104] <= Ant_mode[7:0];
+			Ant_CtrlWord[103: 88] <= vio_AntOffAxis[15:0];
+			Ant_CtrlWord[ 87: 72] <= vio_AntYaw[15:0];
+			Ant_CtrlWord[ 71: 56] <= Ant_frequency[15:0];
+			Ant_CtrlWord[ 55:  8] <= 48'h00_00_00_00_00_00;
+			Ant_CtrlWord[  7:  0] <= 8'hCC;
+			end
+		else
+			begin
+			RF_CtrlWord[95:0] <= RF_CtrlWord[95:0];
+			// Ant_CtrlWord[127:0] <= Ant_CtrlWord[127:0];
+			end
+
+		if(switch_valid)
+			data_valid_countdown[15:0] <= vio_PrecessTime[15:0];
+		else if(data_valid_countdown[15:0] != 16'd0)
+			data_valid_countdown[15:0] <= data_valid_countdown[15:0] - 16'd1;
+
+
+		// RF控制
+		if(data_valid_countdown[15:0] == vio_PrecessTime[15:0])
+			RF_CtrlWord_running[95:0] <= RF_CtrlWord[95:0];
+		else
+			RF_CtrlWord_running[95:0] <= {RF_CtrlWord_running[94:0],1'b0};
+
+		if(data_valid_countdown[15:0] >= vio_PrecessTime[15:0]-16'd96 && data_valid_countdown[15:0] < vio_PrecessTime[15:0])
+			begin
+				SPI_SYN_F <= 1'b0;
+				SPI_MOSI_F <= RF_CtrlWord_running[95];
+			end
+		else
+			begin
+				SPI_SYN_F <= 1'b1;
+				SPI_MOSI_F <= 1'b0;
+			end
+
+
+		if(data_valid_countdown[15:0] <= 16'd128 && data_valid_countdown[15:0] > 16'd80)
+			CAL_F <= 1'b1;
+		else
+			CAL_F <= 1'b0;
+
+		if(data_valid_countdown[15:0] <= 16'd48 && data_valid_countdown[15:0] > 16'd0)
+			begin
+				TP_EN_F <= 1'b1;
+				TR_MGC_F <= 1'b1;
+			end
+		else
+			begin
+				TP_EN_F <= 1'b0;
+				TR_MGC_F <= 1'b0;
+			end
+
+		if(data_valid_countdown[15:0] == 16'd48)
+			PRF <= vio_trdirection;
+		else
+			PRF <= PRF;
+
+		if(sys_rst)
+			rst_countdown[15:0] <= 16'd100;
+		else if(rst_countdown[15:0] != 0)
+			begin
+			rst_countdown[15:0] <= rst_countdown[15:0] - 16'd1;
+			rst_n <= 1'b0;
+			end
+		else
+			begin
+			rst_countdown[15:0] <= rst_countdown[15:0];
+			rst_n <= 1'b1;
+			end
+
+		// 天线控制
+		if(data_valid_countdown[15:0] == vio_PrecessTime[15:0])
+			Ant_CtrlWord_running[127:0] <= Ant_CtrlWord[127:0];
+		else
+			Ant_CtrlWord_running[127:0] <= {Ant_CtrlWord_running[126:0],1'b0};
+
+		if(data_valid_countdown[15:0] >= vio_PrecessTime[15:0]-16'd128 && data_valid_countdown[15:0] < vio_PrecessTime[15:0])
+			begin
+				Ant_EN <= 1'b0;
+				Ant_DATA <= Ant_CtrlWord_running[127];
+			end
+		else
+			begin
+				Ant_EN <= 1'b1;
+				Ant_DATA <= 1'b0;
+			end
+
+		if(data_valid_countdown[15:0] <= 16'd48 && data_valid_countdown[15:0] > 16'd0)
+			Ant_DARY <= 1'b0;
+		else
+			Ant_DARY <= 1'b1;
+
+		if(data_valid_countdown[15:0] == 16'd48)
+			Ant_TR <= vio_trdirection;
+		else
+			Ant_TR <= Ant_TR;
+	end
+
+
+//RF recv_data
+reg [1:0] state_rfdata;
+reg SPI_SYN_F_d1 = 1'b0;
+reg [15:0] cnt_rfdata = 16'd0;
+reg [95:0] RF_RecvWord = 96'd0;
+reg [95:0] RF_RecvWord_last = 96'd0;
+
+reg [7:0]  RF_temperature = 8'd0  ;
+reg [7:0]  RF_IFlocked    = 8'd0  ;
+reg [7:0]  RF_RFAlocked   = 8'd0  ;
+reg [7:0]  RF_RFBlocked   = 8'd0  ;
+reg [3:0]  RF_ch1mgc      = 4'd0  ;
+reg [3:0]  RF_ch2mgc      = 4'd0  ;
+reg [3:0]  RF_ch3mgc      = 4'd0  ;
+reg [3:0]  RF_ch4mgc      = 4'd0  ;
+reg [31:0] RF_Framecount  = 32'd0 ;
+
+always @ (posedge clk_48m) begin
+    if(sys_rst) begin
+        state_rfdata[1:0]    <= 2'd0;
+        SPI_SYN_F_d1         <= 1'b0;
+		RF_RecvWord[95:0]    <= 96'd0;
+		cnt_rfdata[15:0]     <= 16'd0;
+		RF_temperature[7:0]  <= 8'd0 ;
+        RF_IFlocked[7:0]     <= 8'd0 ;
+        RF_RFAlocked[7:0]    <= 8'd0 ;
+        RF_RFBlocked[7:0]    <= 8'd0 ;
+        RF_ch1mgc[3:0]       <= 4'd0 ;
+        RF_ch2mgc[3:0]       <= 4'd0 ;
+        RF_ch3mgc[3:0]       <= 4'd0 ;
+        RF_ch4mgc[3:0]       <= 4'd0 ;
+        RF_Framecount[31:0]  <= 32'd0;
+    end
+    else begin
+		RF_RecvWord[95:0] <= {RF_RecvWord[94:0],SPI_MISO_F};
+
+		if (RF_RecvWord[95:88] == 8'hAA && RF_RecvWord[7:0] == 8'hCC) begin//校验帧头帧尾
+			RF_temperature[7:0]  <= RF_RecvWord[87:80];
+			RF_IFlocked[7:0]     <= RF_RecvWord[79:72];
+			RF_RFAlocked[7:0]    <= RF_RecvWord[71:64];
+			RF_RFBlocked[7:0]    <= RF_RecvWord[63:56];
+			RF_ch1mgc[3:0]       <= RF_RecvWord[55:52];
+			RF_ch2mgc[3:0]       <= RF_RecvWord[51:48];
+			RF_ch3mgc[3:0]       <= RF_RecvWord[47:44];
+			RF_ch4mgc[3:0]       <= RF_RecvWord[43:40];
+			RF_Framecount[31:0]  <= RF_RecvWord[39:8];
+			RF_RecvWord_last <= RF_RecvWord;
+		end
+		else begin // hold otherwise
+			RF_temperature[7:0]  <= RF_temperature[7:0];
+			RF_IFlocked[7:0]     <= RF_IFlocked[7:0]   ;
+			RF_RFAlocked[7:0]    <= RF_RFAlocked[7:0]  ;
+			RF_RFBlocked[7:0]    <= RF_RFBlocked[7:0]  ;
+			RF_ch1mgc[3:0]       <= RF_ch1mgc[3:0]     ;
+			RF_ch2mgc[3:0]       <= RF_ch2mgc[3:0]     ;
+			RF_ch3mgc[3:0]       <= RF_ch3mgc[3:0]     ;
+			RF_ch4mgc[3:0]       <= RF_ch4mgc[3:0]     ;
+			RF_Framecount[31:0]  <= RF_Framecount[31:0];
+			RF_RecvWord_last <= RF_RecvWord_last;
+		end
+    end
+end
+// 天线的输出时钟转换
+reg Ant_dclk_96m = 1;
+wire [3:0] fifo_wr_din, fifo_rd_dout;
+wire fifo_full, fifo_empty;
+reg Ant_EN_96m = 0;
+reg Ant_DATA_96m = 0;
+reg Ant_DARY_96m = 1;
+reg Ant_TR_96m = 0;
+assign fifo_wr_din[3] = Ant_EN;
+assign fifo_wr_din[2] = Ant_DATA;
+assign fifo_wr_din[1] = Ant_DARY;
+assign fifo_wr_din[0] = Ant_TR;
+reg fifo_rd_en = 0;
+reg fifo_rst = 0;
+reg [8:0] Ant_clk_countdown = 0;
+always @(posedge clk_96m)
+	begin
+		fifo_rst <= sys_rst;
+
+		fifo_rd_en <= (fifo_rst == 1'b1)? 1'b0:!fifo_rd_en;
+
+		if(fifo_rd_en)
+			{Ant_EN_96m,Ant_DATA_96m,Ant_DARY_96m,Ant_TR_96m} <= fifo_rd_dout[3:0];
+		else
+			{Ant_EN_96m,Ant_DATA_96m,Ant_DARY_96m,Ant_TR_96m} <= {Ant_EN_96m,Ant_DATA_96m,Ant_DARY_96m,Ant_TR_96m};
+
+		if(fifo_rd_en && Ant_EN_96m && !fifo_rd_dout[3])
+			Ant_clk_countdown[8:0] <= 9'd276;
+		else if(Ant_clk_countdown[8:0] != 9'd0)
+			Ant_clk_countdown[8:0] <= Ant_clk_countdown[8:0] - 9'd1;
+		else
+			Ant_clk_countdown[8:0] <= Ant_clk_countdown[8:0];
+	end
+assign ant_clk = !Ant_clk_countdown[0];
+assign ant_en = Ant_EN_96m;
+assign ant_data = Ant_DATA_96m;
+assign ant_tr = Ant_TR_96m;
+assign ant_dary = Ant_DARY_96m;
+
+fifo_AntCtrl fifo_AntCtrl
+(
+    .rst    (fifo_rst           ), // input wire rst
+    .wr_clk (clk_48m            ), // input wire wr_clk
+    .rd_clk (clk_96m            ), // input wire rd_clk
+    .din    (fifo_wr_din[3:0]   ), // input wire [3 : 0] din
+    .wr_en  (!fifo_rst          ), // input wire wr_en
+    .rd_en  (fifo_rd_en         ), // input wire rd_en
+    .dout   (fifo_rd_dout[3:0]  ), // output wire [3 : 0] dout
+    .full   (fifo_full          ), // output wire full
+    .empty  (fifo_empty         )  // output wire empty
+);
+//Ant recv_data
+reg [1:0] state_antdata;
+reg Ant_EN_96m_d1 = 1'b0;
+reg [15:0] cnt_antdata = 16'd0;
+reg [127:0] Ant_RecvWord = 128'b0;
+reg [127:0] Ant_RecvWord_last = 128'b0;
+
+reg [7:0]  Ant_Ant_Volt    = 8'd0  ;
+reg [7:0]  Ant_RF_Volt     = 8'd0  ;
+reg [7:0]  Ant_IF_Volt     = 8'd0  ;
+reg [7:0]  Ant_state       = 8'd0  ;
+reg [31:0] Ant_Framecount  = 32'd0 ;
+
+always @ (posedge clk_96m) begin
+    if(sys_rst) begin
+        state_antdata[1:0]   <= 2'd0;
+        Ant_EN_96m_d1        <= 1'b0;
+		Ant_RecvWord[127:0]   <= 128'd0;
+		cnt_antdata[15:0]    <= 16'd0;
+		Ant_Ant_Volt[7:0]    <= 8'd0 ;
+        Ant_RF_Volt[7:0]     <= 8'd0 ;
+        Ant_IF_Volt[7:0]     <= 8'd0 ;
+        Ant_state[7:0]       <= 8'd0 ;
+        Ant_Framecount[31:0] <= 32'd0;
+        Ant_RecvWord_last[127:0] <= 128'd0;
+    end
+    else begin
+        if(!ant_clk) begin
+            Ant_RecvWord[127:0] <= {Ant_RecvWord[126:0],ant_dout};
+        end
+		else begin
+            Ant_RecvWord[127:0] <= Ant_RecvWord[127:0];
+        end
+
+		if(Ant_RecvWord[127:120] == 8'hAA && Ant_RecvWord[7:0] == 8'hCC) begin//校验帧头帧尾
+			Ant_Ant_Volt[7:0]    <= Ant_RecvWord[119:112];
+			Ant_RF_Volt[7:0]     <= Ant_RecvWord[111:104];
+			Ant_IF_Volt[7:0]     <= Ant_RecvWord[103:96];
+			Ant_state[7:0]       <= Ant_RecvWord[47:40];
+			Ant_Framecount[31:0] <= Ant_RecvWord[39:8] ;
+            Ant_RecvWord_last[127:0] <= Ant_RecvWord[127:0];
+		end
+		else begin // hold otherwise
+			Ant_Ant_Volt[7:0]    <= Ant_Ant_Volt[7:0]    ;
+			Ant_RF_Volt[7:0]     <= Ant_RF_Volt[7:0]     ;
+			Ant_IF_Volt[7:0]     <= Ant_IF_Volt[7:0]     ;
+			Ant_state[7:0]       <= Ant_state[7:0]       ;
+			Ant_Framecount[31:0] <= Ant_Framecount[31:0] ;
+            Ant_RecvWord_last[127:0] <= Ant_RecvWord_last[127:0];
+		end
+    end
+
+end
+Sisyif uut(
+	.clk_40m(clk_32m),
+	.clk_20m(clk_19p2m),
+	.SPI_CLK_F(clk_48m),
+	.rst_n(rst_n),
+	.SPI_SYN_F(SPI_SYN_F),
+	.SPI_MOSI_F(SPI_MOSI_F),
+	.SPI_MISO_F(SPI_MISO_F),
+	.TP_EN_F(TP_EN_F),
+	.TR_MGC_F(TR_MGC_F),
+	.CAL_F(CAL_F),
+	.PRF(PRF),
+	.standby(rf_standby),
+	.SW_PLL(rf_sw_pll),
+	.T(rf_t),
+	.R(rf_r),
+	.SW_BPF(rf_sw_bpf),
+	.SCLK1(rf_sclk1),
+	.SDIO1(rf_sdio1),
+	.CS1(rf_cs1),
+	.LD1(rf_ld1),
+	.SCLK2(rf_sclk2),
+	.SDIO2(rf_sdio2),
+	.CS2(rf_cs2),
+	.LD2(rf_ld2),
+	.SCLK3(rf_sclk3),
+	.SDIO3(rf_sdio3),
+	.CS3(rf_cs3),
+	.LD3(rf_ld3),
+	.TMGC_16db(rf_tmgc_16),
+	.TMGC_8db(rf_tmgc_8),
+	.TMGC_4db(rf_tmgc_4),
+	.TMGC_2db(rf_tmgc_2),
+	.TMGC_1db(rf_tmgc_1),
+	.RMGC_16db(rf_rmgc_16),
+	.RMGC_8db(rf_rmgc_8),
+	.RMGC_4db(rf_rmgc_4),
+	.RMGC_2db(rf_rmgc_2),
+	.RMGC_1db(rf_rmgc_1),
+	.ENABLE(rf_enable),
+	.SC(rf_sc),
+	.SD(rf_sd),
+	.END_SYN(rf_endsyn),
+	.SDOUT(rf_sdout),
+	.DQ_WD(rf_dq_wd),
+	.SW_RX(rf_sw_rx)
+	);
+
+endmodule

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/hdwr/clk_dist.v

@@ -0,0 +1,133 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+//
+// Create Date: 2022/11/01 11:15:25
+// Design Name:
+// Module Name: clk_dist
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description: Clock distribution module
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module clk_dist
+(
+    // input clocks
+    input           clk_250m_p          , // generated by ad9516, 250mhz
+    input           clk_250m_n          ,
+    input           ad9361_1_rx_data_clk, // ad9361 rx data clock, 83.3333mhz
+    input           ad9361_2_rx_data_clk, // ad9361 rx data clock, 83.3333mhz
+
+    // output clocks & reset
+    // global reset
+    output          sys_rst             , // global reset signal, active high
+    output          ant_rst             , // phased-array & rf control reset signal, active high
+
+    // pl signal processing clock
+    output          sys_clk             , // 41.6667mhz
+    output          sys_clk_2x          , // 83.3333mhz
+    output          sys_clk_3x          , // 125mhz
+    output          sys_clk_4x          , // 166.6667mhz
+    output          sys_clk_ld          , // system main clock locked indicator
+
+    // ad9361-1 clocks
+    output          ad9361_1_clk        , // 41.6667mhz
+    output          ad9361_1_clk_2x     , // 83.3333mhz
+    output          ad9361_1_clk_3x     , // 125mhz
+    output          ad9361_1_clk_4x     , // 166.6667mhz
+    output          ad9361_1_clk_ld     , // ad9361-1 clock group locked indicator
+
+    // ad9361-2 clocks
+    output          ad9361_2_clk        , // 41.6667mhz
+    output          ad9361_2_clk_2x     , // 83.3333mhz
+    output          ad9361_2_clk_3x     , // 125mhz
+    output          ad9361_2_clk_4x     , // 166.6667mhz
+    output          ad9361_2_clk_ld     , // ad9361-2 clock group locked indicator
+
+    // phased-array & rf control clocks
+    output          clk_96m             ,
+    output          clk_48m             ,
+    output          clk_32m             ,
+    output          clk_19p2m
+);
+
+assign sys_clk    = ad9361_1_clk   ;
+assign sys_clk_2x = ad9361_1_clk_2x;
+assign sys_clk_3x = ad9361_1_clk_3x;
+assign sys_clk_4x = ad9361_1_clk_4x;
+assign sys_clk_ld = ad9361_1_clk_ld;
+
+assign sys_rst = ~sys_clk_ld;
+
+ad9361_clk_gen_cmos_2t2r u_ad9361_1_clk_gen
+(
+    // Clock out ports
+    .clk_out1   (ad9361_1_clk           ), // output clk_out1
+    .clk_out2   (ad9361_1_clk_2x        ), // output clk_out2
+    .clk_out3   (ad9361_1_clk_3x        ), // output clk_out3
+    .clk_out4   (ad9361_1_clk_4x        ), // output clk_out4
+    // Status and control signals
+    .locked     (ad9361_1_clk_ld        ), // output locked
+    // Clock in ports
+    .clk_in1    (ad9361_1_rx_data_clk   )  // input clk_in1
+);
+
+ad9361_clk_gen_cmos_2t2r u_ad9361_2_clk_gen
+(
+    // Clock out ports
+    .clk_out1   (ad9361_2_clk           ), // output clk_out1
+    .clk_out2   (ad9361_2_clk_2x        ), // output clk_out2
+    .clk_out3   (ad9361_2_clk_3x        ), // output clk_out3
+    .clk_out4   (ad9361_2_clk_4x        ), // output clk_out4
+    // Status and control signals
+    .locked     (ad9361_2_clk_ld        ), // output locked
+    // Clock in ports
+    .clk_in1    (ad9361_2_rx_data_clk   )  // input clk_in1
+);
+
+wire            ant_clk_stg1_96m;
+wire            ant_clk_stg1_ld;
+wire            ant_clk_stg2_ld;
+
+assign ant_rst = ~ant_clk_stg2_ld;
+
+ant_clk_gen_stg1 u_ant_clk_gen_stg1
+(
+    // Clock out ports
+    .clk_out1   (ant_clk_stg1_96m       ), // output clk_out1
+    // Status and control signals
+    .locked     (ant_clk_stg1_ld        ), // output locked
+    // Clock in ports
+    .clk_in1_p  (clk_250m_p             ), // input clk_in1_p
+    .clk_in1_n  (clk_250m_n             )  // input clk_in1_n
+);
+
+ant_clk_gen_stg2 u_ant_clk_gen_stg2
+(
+    // Clock out ports
+    .clk_out1   (clk_96m                ), // output clk_out1
+    .clk_out2   (clk_48m                ), // output clk_out2
+    .clk_out3   (clk_32m                ), // output clk_out3
+    .clk_out4   (clk_19p2m              ), // output clk_out4
+    // Status and control signals
+    .locked     (ant_clk_stg2_ld        ), // output locked
+    // Clock in ports
+    .clk_in1    (ant_clk_stg1_96m       )  // input clk_in1
+);
+
+endmodule

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/accor_mat_formatting.v

@@ -0,0 +1,426 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+//
+// Create Date: 2022/11/06 15:24:48
+// Design Name:
+// Module Name: accor_mat_formatting
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description: Formmat the input complex matrix to 1-bit stream.
+// Parameter:
+//   ROW_NUM: Row number of input matrix.
+//   COL_NUM: Column number of input matrix.
+//   DATA_I_WIDTH: Bit width of input matrix element.
+//   FRAME_HEAD: Frame head indicate autocorrelation matrix frame.
+// Data format:
+//   din_valid: Indicate [din_real/imag] data are valid.
+//   din_real/imag: Suppose the input matrix x = [x11 x12; x21 x22], then
+//     din_real = {Re{x22}, Re{x21}, Re{x12}, Re{x11}}
+//     din_imag = {Im{x22}, Im{x21}, Im{x12}, Im{x11}}
+//   dout_valid: Indicate [dout_data] is valid. The latency is set to 2 clock
+//     cycles by default.
+//   dout_data:
+//     dout_data = {FRAME_HEAD[msb], ..., FRAME_HEAD[lsb], FRAME_LEN[msb],
+//     ..., FRAME_LEN[lsb], Re{x11}[msb], ..., Re{x11}[lsb], Im{x11}[msb], ...,
+//     Im{x11}[lsb], ..., Re{x12}[msb], ......, Im{x22}[lsb]}
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module accor_mat_formatting
+#(
+  parameter ROW_NUM = 4,
+  parameter COL_NUM = 4,
+  parameter DATA_I_WIDTH = 32,
+  parameter FRAME_HEAD = 32'h7E7E7E7E
+)
+(
+  // clock & reset
+  input sys_clk,
+  input sys_rst,
+  input clk_96m,
+  input ant_rst,
+
+  // input data
+  input din_valid,
+  input [ROW_NUM*COL_NUM*DATA_I_WIDTH-1 : 0] din_real,
+  input [ROW_NUM*COL_NUM*DATA_I_WIDTH-1 : 0] din_imag,
+  input fifo_cdc_rst,
+
+  // output data
+  output dout_valid,
+  output dout_data
+);
+
+localparam CMPLX_DIM = 2;
+localparam FRAME_LEN = ROW_NUM*COL_NUM*CMPLX_DIM; // 32-bit data number per frame
+localparam BYTE_LEN = 4 * (ROW_NUM*COL_NUM*CMPLX_DIM + 2); // byte number per frame, plus frame head and frame length
+
+// available state
+localparam STATE_NUM = 4;
+localparam STATE_IDLE = 0;
+localparam STATE_HEAD = 1;
+localparam STATE_LEN  = 2;
+localparam STATE_DATA = 3;
+
+genvar i;
+integer m;
+
+// format input data to array
+wire [DATA_I_WIDTH-1 : 0] din_array [0 : ROW_NUM*COL_NUM*CMPLX_DIM-1];
+reg [DATA_I_WIDTH-1 : 0] din_array_cdc [0 : ROW_NUM*COL_NUM*CMPLX_DIM-1];
+
+generate
+for (i = 0; i < ROW_NUM*COL_NUM; i = i + 1) begin: input_mat_reshape
+  assign din_array[i*2]   = din_real[i*DATA_I_WIDTH +: DATA_I_WIDTH];
+  assign din_array[i*2+1] = din_imag[i*DATA_I_WIDTH +: DATA_I_WIDTH];
+end
+endgenerate
+
+// clock domain crossing fifo, write channel
+reg fifo_wr_start = 'b0;
+reg fifo_wr_en = 'b0;
+reg [$clog2(ROW_NUM*COL_NUM*CMPLX_DIM)-1 : 0] fifo_wr_cnt = 'b0;
+reg [DATA_I_WIDTH-1 : 0] fifo_din = 'b0;
+
+always @(posedge sys_clk) begin
+  if (sys_rst) begin
+    fifo_wr_start <= 'b0;
+  end
+  else if (din_valid) begin
+    fifo_wr_start <= 1'b1;
+  end
+  else if (fifo_wr_cnt == ROW_NUM*COL_NUM*CMPLX_DIM-1) begin
+    fifo_wr_start <= 1'b0;
+  end
+  else begin
+    fifo_wr_start <= fifo_wr_start;
+  end
+end
+
+always @(posedge sys_clk) begin
+  if (sys_rst) begin
+    fifo_wr_en  <= 'b0;
+    fifo_wr_cnt <= 'b0;
+    fifo_din    <= 'b0;
+  end
+  else if (fifo_wr_start) begin
+    fifo_wr_en  <= 1'b1;
+    fifo_wr_cnt <= fifo_wr_cnt + 1'b1;
+    fifo_din    <= din_array[fifo_wr_cnt];
+  end
+  else begin
+    fifo_wr_en  <= 'b0;
+    fifo_wr_cnt <= 'b0;
+    fifo_din    <= 'b0;
+  end
+end
+
+// clock domain crossing fifo, read channel
+reg fifo_rd_en = 'b0;
+reg fifo_rd_en_d1 = 'b0;
+reg [$clog2(ROW_NUM*COL_NUM*CMPLX_DIM)-1 : 0] fifo_rd_cnt = 'b0;
+reg [$clog2(ROW_NUM*COL_NUM*CMPLX_DIM)-1 : 0] fifo_rd_cnt_d1 = 'b0; // read data latency
+reg fifo_rd_valid = 'b0;
+wire [DATA_I_WIDTH-1 : 0] fifo_dout;
+wire [$clog2(ROW_NUM*COL_NUM*CMPLX_DIM*2)-1 : 0] fifo_rd_num;
+wire fifo_full;
+wire fifo_empty;
+
+always @(posedge clk_96m) begin
+  if (ant_rst) begin
+    fifo_rd_en <= 'b0;
+  end
+  else if (fifo_rd_num == ROW_NUM*COL_NUM*CMPLX_DIM-1) begin
+    fifo_rd_en <= 1'b1;
+  end
+  else if (fifo_rd_cnt == ROW_NUM*COL_NUM*CMPLX_DIM-1) begin
+    fifo_rd_en <= 'b0;
+  end
+  else begin
+    fifo_rd_en <= fifo_rd_en;
+  end
+end
+
+always @(posedge clk_96m) begin
+  if (ant_rst) begin
+    fifo_rd_en_d1 <= 'b0;
+  end
+  else begin
+    fifo_rd_en_d1 <= fifo_rd_en;
+  end
+end
+
+always @(posedge clk_96m) begin
+  if (ant_rst) begin
+    fifo_rd_cnt <= 'b0;
+  end
+  else if (fifo_rd_en) begin
+    fifo_rd_cnt <= fifo_rd_cnt + 1'b1;
+  end
+  else begin
+    fifo_rd_cnt <= 'b0;
+  end
+end
+
+always @(posedge clk_96m) begin
+  if (ant_rst) begin
+    fifo_rd_cnt_d1 <= 'b0;
+  end
+  else begin
+    fifo_rd_cnt_d1 <= fifo_rd_cnt;
+  end
+end
+
+always @(posedge clk_96m) begin
+  if (ant_rst) begin
+    fifo_rd_valid <= 'b0;
+  end
+  else if (fifo_rd_cnt_d1 == ROW_NUM*COL_NUM*CMPLX_DIM-1) begin
+    fifo_rd_valid <= 1'b1;
+  end
+  else begin
+    fifo_rd_valid <= 'b0;
+  end
+end
+
+always @(posedge clk_96m) begin
+  if (ant_rst) begin
+  for (m = 0; m < ROW_NUM*COL_NUM*CMPLX_DIM; m = m + 1) begin
+    din_array_cdc[m] <= 'b0;
+  end
+  end
+  else if (fifo_rd_en_d1) begin
+    din_array_cdc[fifo_rd_cnt_d1] <= fifo_dout;
+  end
+  else begin
+  for (m = 0; m < ROW_NUM*COL_NUM*CMPLX_DIM; m = m + 1) begin
+    din_array_cdc[m] <= din_array_cdc[m];
+  end
+  end
+end
+
+// clock domain crossing fifo, interface
+fifo_accor_cdc u_fifo_accor_cdc
+(
+  .rst            (fifo_cdc_rst   ), // input wire wr_rst
+  .wr_clk         (sys_clk        ), // input wire wr_clk
+  .rd_clk         (clk_96m        ), // input wire rd_clk
+  .din            (fifo_din       ), // input wire [31 : 0] din
+  .wr_en          (fifo_wr_en     ), // input wire wr_en
+  .rd_en          (fifo_rd_en     ), // input wire rd_en
+  .dout           (fifo_dout      ), // output wire [31 : 0] dout
+  .full           (fifo_full      ), // output wire full
+  .empty          (fifo_empty     ), // output wire empty
+  .rd_data_count  (fifo_rd_num    )  // output wire [5 : 0] rd_data_count
+);
+
+// center state machine & counter
+reg [$clog2(STATE_NUM)-1 : 0] state = STATE_IDLE;
+reg [$clog2(DATA_I_WIDTH)-1 : 0] bit_cnt = 'b0; // bit counter within one frame
+reg [$clog2(FRAME_LEN)-1 : 0] frame_cnt = 'b0; // frame counter
+
+always @(posedge clk_96m) begin
+  if (ant_rst) begin
+    state <= STATE_IDLE;
+  end
+  else begin
+    case (state)
+      STATE_IDLE: state <= fifo_rd_valid ? STATE_HEAD : STATE_IDLE;
+      STATE_HEAD: state <= (bit_cnt == DATA_I_WIDTH-1) ? STATE_LEN : STATE_HEAD;
+      STATE_LEN : state <= (bit_cnt == DATA_I_WIDTH-1) ? STATE_DATA : STATE_LEN;
+      STATE_DATA: state <= (frame_cnt == FRAME_LEN-1 && bit_cnt == DATA_I_WIDTH-1) ? STATE_IDLE : STATE_DATA;
+      default: state <= STATE_IDLE;
+    endcase
+  end
+end
+
+always @(posedge clk_96m) begin
+  if (ant_rst) begin
+    bit_cnt <= 'b0;
+  end
+  else if (state == STATE_IDLE) begin
+    bit_cnt <= 'b0;
+  end
+  else begin
+    bit_cnt <= (bit_cnt == DATA_I_WIDTH-1) ? 'b0 : bit_cnt + 1'b1;
+  end
+end
+
+always @(posedge clk_96m) begin
+  if (ant_rst) begin
+    frame_cnt <= 'b0;
+  end
+  else if (state == STATE_IDLE) begin
+    frame_cnt <= 'b0;
+  end
+  else if (state == STATE_DATA && bit_cnt == DATA_I_WIDTH-1) begin
+    frame_cnt <= frame_cnt + 1'b1;
+  end
+  else begin
+    frame_cnt <= frame_cnt;
+  end
+end
+
+
+// output data
+reg dout_valid_buf = 'b0;
+reg dout_data_buf = 'b0;
+
+assign dout_valid = dout_valid_buf;
+assign dout_data = dout_data_buf;
+
+always @(posedge clk_96m) begin
+  if (ant_rst) begin
+    dout_valid_buf <= 'b0;
+    dout_data_buf <= 'b0;
+  end
+  else case (state)
+    STATE_IDLE: begin dout_valid_buf <= 'b0 ; dout_data_buf <= 'b0; end
+    STATE_HEAD: begin dout_valid_buf <= 1'b1; dout_data_buf <= FRAME_HEAD[DATA_I_WIDTH-1 - bit_cnt]; end
+    STATE_LEN : begin dout_valid_buf <= 1'b1; dout_data_buf <= BYTE_LEN[DATA_I_WIDTH-1 - bit_cnt]; end
+    STATE_DATA: begin dout_valid_buf <= 1'b1; dout_data_buf <= din_array_cdc[frame_cnt][DATA_I_WIDTH-1 - bit_cnt]; end
+    default: begin dout_valid_buf <= 'b0 ; dout_data_buf <= 'b0; end
+  endcase
+end
+
+endmodule
+
+
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+//
+// Create Date: 2022/10/30 20:46:26
+// Design Name:
+// Module Name: tb_accum
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description: Testbench for [accor_mat_formatting]
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+// -------------------------------
+// MATLAB Code for data generation
+// -------------------------------
+// COLUMN_NUM = 4;
+// DATA_I_WIDTH = 12;
+// ACC_NUM = 10;
+
+// rng(0);
+// data = rand(4,2)*2-1;
+// d_12b = round(data.*(2^(DATA_I_WIDTH-1)-1));
+// d_12b_cmplx = d_12b(:,1) + 1i*d_12b(:,2);
+// d_12b_cmplx = d_12b_cmplx(end:-1:1,:);
+// d_12b_acorr = d_12b_cmplx*d_12b_cmplx';
+// d_12b_acorr_real_sim = reshape(flip(reshape(real(d_12b_acorr)',1,16)),4,4);
+// d_12b_acorr_imag_sim = reshape(flip(reshape(imag(d_12b_acorr)',1,16)),4,4);
+// d_12b_acorr_real_sim_sum = ACC_NUM*d_12b_acorr_real_sim;
+// d_12b_acorr_imag_sim_sum = ACC_NUM*d_12b_acorr_imag_sim;
+
+
+// module tb_accor_format;
+
+// localparam DATA_I_WIDTH  = 32;
+// localparam ROW_NUM  = 4;
+// localparam COL_NUM  = 4;
+
+// reg  sys_clk = 1'b1;
+// reg  sys_rst = 1'b1;
+// reg  clk_96m = 1'b1;
+// reg  ant_rst = 1'b1;
+// reg din_valid = 'b0;
+// reg [ROW_NUM*COL_NUM*DATA_I_WIDTH-1:0] din_real = 'b0, din_imag = 'b0;
+
+// wire dout_valid;
+// wire dout_data;
+
+// accor_mat_formatting #(
+//     .ROW_NUM        (ROW_NUM),
+//     .COL_NUM        (COL_NUM),
+//     .DATA_I_WIDTH   (DATA_I_WIDTH)
+// ) u_accor_mat_formatting
+// (
+//     // clock & reset
+//     .sys_clk    (sys_clk    ), // input           sys_clk
+//     .sys_rst    (sys_rst    ), // input           sys_rst
+//     .clk_96m    (clk_96m    ), // input           clk_96m
+//     .ant_rst    (ant_rst    ), // input           ant_rst
+
+//     // input data
+//     .din_valid  (din_valid  ),
+//     .din_real   (din_real   ),
+//     .din_imag   (din_imag   ),
+
+//     // output data
+//     .dout_valid (dout_valid ),
+//     .dout_data  (dout_data  )
+// );
+
+
+// initial begin
+//     #102
+//     sys_rst = 1'b0;
+//     ant_rst = 1'b0;
+
+//     #222;
+//     @(posedge sys_clk)
+//     din_valid = 1'b1;
+//     din_real = {
+//      32'd1952708,     32'd1246152,    -32'd2458370,     32'd2283360,
+//      32'd1246152,     32'd5474825,    -32'd1041611,     32'd2493996,
+//     -32'd2458370,    -32'd1041611,     32'd3154378,    -32'd2757828,
+//      32'd2283360,     32'd2493996,    -32'd2757828,     32'd2899728
+//      };
+
+//      din_imag = {
+//            32'd1,    -32'd3022886,     -32'd340582,     -32'd669768,
+//      32'd3022886,           32'd2,    -32'd4023023,     32'd3107328,
+//       32'd340582,     32'd4023023,           32'd3,     32'd1241460,
+//       32'd669768,    -32'd3107328,    -32'd1241460,           32'd4
+//      };
+
+//     @(posedge sys_clk)
+//     din_valid = 1'b0;
+
+// end
+
+// always begin
+//     #20 sys_clk = ~sys_clk;
+// end
+
+// always begin
+//     #7;
+//     clk_96m = ~clk_96m;
+//     #3;
+// end
+
+
+// endmodule

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/accum_cmplx_mat.v

@@ -0,0 +1,365 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+//
+// Create Date: 2022/11/02 11:06:43
+// Design Name:
+// Module Name: accum_cmplx_mat
+// Project Name:
+// Target Devices:
+// Tool Versions: 2019.1.3
+// Description: Compute the accumulation of complex matrices. The parameters are
+//    fully adjustable.
+// Parameter:
+//   ROW_NUM: Row number of input matrix.
+//   COL_NUM: Column number of input matrix.
+//   ACC_NUM: Accumulation number of input matrix.
+//   DATA_I_WIDTH: Bit width of input matrix element.
+//   DATA_O_WIDTH: Bit width of output matrix element. If [DATA_O_WIDTH] <=
+//     [ACC_WIDTH], MSB of accumulation result will be truncated, or zeros will
+//     be appended.
+//   ACC_WIDTH (local): Accumulation adder output data width, determined by
+//     [DATA_I_WIDTH] and [ACC_NUM].
+//
+// Dependencies:
+//
+// Revision:
+//   Revision 0.01 - File Created
+//   20230717-1552 - 修改程序使得快拍数可以大于 256，具体修改有：1. 将累加位宽
+//     改为内部参数；2. 移除加法器，变为手写加法；3. 修改 Generate 结构，always
+//     块中不应出现 generate 块。
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module accum_cmplx_mat
+#(
+    parameter ROW_NUM = 4,
+    parameter COL_NUM = 4,
+    parameter ACC_NUM = 256,
+    parameter DATA_I_WIDTH = 24,
+    parameter DATA_O_WIDTH = 32
+)
+(
+    // clock & reset
+    input clk,
+    input rst,
+    input acc_rst, // [acc_rst] should assert before accumulation starts
+
+    // input data
+    input din_valid,
+    input [ROW_NUM*COL_NUM*DATA_I_WIDTH-1:0] din_real,
+    input [ROW_NUM*COL_NUM*DATA_I_WIDTH-1:0] din_imag,
+
+    // output data
+    output dout_valid,
+    output [ROW_NUM*COL_NUM*DATA_O_WIDTH-1:0] dout_real,
+    output [ROW_NUM*COL_NUM*DATA_O_WIDTH-1:0] dout_imag
+);
+
+localparam  ACC_WIDTH = $clog2(ACC_NUM) + DATA_I_WIDTH;
+
+integer i;
+genvar m;
+
+// prepare adder input & output data
+wire signed [DATA_I_WIDTH-1:0] din_real_array [0:ROW_NUM*COL_NUM-1];
+wire signed [DATA_I_WIDTH-1:0] din_imag_array [0:ROW_NUM*COL_NUM-1];
+
+for (m = 0; m < ROW_NUM*COL_NUM; m = m + 1) begin: array_conversion
+    // Array split
+    assign din_real_array[m] = din_real[m*DATA_I_WIDTH +: DATA_I_WIDTH];
+    assign din_imag_array[m] = din_imag[m*DATA_I_WIDTH +: DATA_I_WIDTH];
+end
+
+// accumulation counter
+reg [$clog2(ACC_NUM)-1:0] accum_cnt = 'b0;
+reg accum_full_flag = 'b0;
+reg accum_full_flag_d = 'b0;
+
+// accumulation
+reg signed [ACC_WIDTH-1:0] acc_real_array [0:ROW_NUM*COL_NUM-1];
+reg signed [ACC_WIDTH-1:0] acc_imag_array [0:ROW_NUM*COL_NUM-1];
+
+if (ACC_NUM > 1) begin
+    // accumulation counter
+    always @(posedge clk) begin
+        if (rst || acc_rst) begin
+            accum_cnt <= 'b0;
+        end
+        else if (din_valid) begin
+            accum_cnt <= accum_cnt + 1'b1;
+        end
+        else begin
+            accum_cnt <= accum_cnt;
+        end
+    end
+
+    always @(posedge clk) begin
+        if (rst || acc_rst) begin
+            accum_full_flag <= 'b0;
+        end
+        else begin
+            accum_full_flag <= (accum_cnt == ACC_NUM - 1) ? 1'b1 : accum_full_flag;
+        end
+
+        accum_full_flag_d <= accum_full_flag;
+    end
+
+    // accumulation
+    for (m = 0; m < ROW_NUM*COL_NUM; m = m + 1) begin: accumulation
+        always @(posedge clk) begin
+            if (rst || acc_rst) begin
+                acc_real_array[m] <= 'b0;
+                acc_imag_array[m] <= 'b0;
+            end
+            else if (din_valid && ~accum_full_flag) begin
+                acc_real_array[m] <= acc_real_array[m] + din_real_array[m];
+                acc_imag_array[m] <= acc_imag_array[m] + din_imag_array[m];
+            end
+            else begin
+                acc_real_array[m] <= acc_real_array[m];
+                acc_imag_array[m] <= acc_imag_array[m];
+            end
+        end
+    end
+end
+
+// output control
+reg dout_valid_buf;
+reg [DATA_O_WIDTH-1:0] dout_real_array [0:ROW_NUM*COL_NUM-1];
+reg [DATA_O_WIDTH-1:0] dout_imag_array [0:ROW_NUM*COL_NUM-1];
+
+assign dout_valid = dout_valid_buf;
+
+if (ACC_NUM > 1) begin
+    always @(posedge clk) begin
+        if (rst || acc_rst) begin
+            dout_valid_buf <= 'b0;
+        end
+        else begin
+            dout_valid_buf <= ~accum_full_flag_d & accum_full_flag;
+        end
+    end
+end
+else begin
+    always @(posedge clk) begin
+        if (rst || acc_rst) begin
+            dout_valid_buf <= 'b0;
+        end
+        else begin
+            dout_valid_buf <= din_valid;
+        end
+    end
+end
+
+for (m = 0; m < ROW_NUM*COL_NUM; m = m + 1) begin: output_data
+    if (ACC_NUM > 1) begin
+        if (DATA_O_WIDTH <= ACC_WIDTH) begin
+            // truncate msb
+            always @(posedge clk) begin
+                if (rst || acc_rst) begin
+                    dout_real_array[m] <= 'b0;
+                    dout_imag_array[m] <= 'b0;
+                end
+                else if (~accum_full_flag_d & accum_full_flag) begin
+                    dout_real_array[m] <= acc_real_array[m][ACC_WIDTH-1 -: DATA_O_WIDTH];
+                    dout_imag_array[m] <= acc_imag_array[m][ACC_WIDTH-1 -: DATA_O_WIDTH];
+                end
+                else begin
+                    dout_real_array[m] <= dout_real_array[m];
+                    dout_imag_array[m] <= dout_imag_array[m];
+                end
+            end
+        end
+        else begin // if (DATA_O_WIDTH > ACC_WIDTH)
+            // append zeros to fit output data width
+            always @(posedge clk) begin
+                if (rst || acc_rst) begin
+                    dout_real_array[m] <= 'b0;
+                    dout_imag_array[m] <= 'b0;
+                end
+                else if (~accum_full_flag_d & accum_full_flag) begin
+                    dout_real_array[m] <= {acc_real_array[m],{(DATA_O_WIDTH-ACC_WIDTH){1'b0}}};
+                    dout_imag_array[m] <= {acc_imag_array[m],{(DATA_O_WIDTH-ACC_WIDTH){1'b0}}};
+                end
+                else begin
+                    dout_real_array[m] <= dout_real_array[m];
+                    dout_imag_array[m] <= dout_imag_array[m];
+                end
+            end
+        end
+    end
+    else begin
+        if (DATA_O_WIDTH <= DATA_I_WIDTH) begin
+            // truncate msb
+            always @(posedge clk) begin
+                if (rst || acc_rst) begin
+                    dout_real_array[m] <= 'b0;
+                    dout_imag_array[m] <= 'b0;
+                end
+                else if (din_valid) begin
+                    dout_real_array[m] <= din_real_array[m][DATA_I_WIDTH-1 -: DATA_O_WIDTH];
+                    dout_imag_array[m] <= din_imag_array[m][DATA_I_WIDTH-1 -: DATA_O_WIDTH];
+                end
+                else begin
+                    dout_real_array[m] <= dout_real_array[m];
+                    dout_imag_array[m] <= dout_imag_array[m];
+                end
+            end
+        end
+        else begin // if (DATA_O_WIDTH > DATA_I_WIDTH)
+            // append zeros to fit output data width
+            always @(posedge clk) begin
+                if (rst || acc_rst) begin
+                    dout_real_array[m] <= 'b0;
+                    dout_imag_array[m] <= 'b0;
+                end
+                else if (din_valid) begin
+                    dout_real_array[m] <= {din_real_array[m],{(DATA_O_WIDTH-DATA_I_WIDTH){1'b0}}};
+                    dout_imag_array[m] <= {din_imag_array[m],{(DATA_O_WIDTH-DATA_I_WIDTH){1'b0}}};
+                end
+                else begin
+                    dout_real_array[m] <= dout_real_array[m];
+                    dout_imag_array[m] <= dout_imag_array[m];
+                end
+            end
+        end
+    end
+end
+
+// output mapping
+for (m = 0; m < ROW_NUM*COL_NUM; m = m + 1) begin: output_mapping
+    assign dout_real[m*DATA_O_WIDTH +: DATA_O_WIDTH] = dout_real_array[m];
+    assign dout_imag[m*DATA_O_WIDTH +: DATA_O_WIDTH] = dout_imag_array[m];
+end
+
+endmodule
+
+
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+//
+// Create Date: 2022/10/30 20:46:26
+// Design Name:
+// Module Name: tb_accum
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description: Testbench for [accum_cmplx_mat]
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+// -------------------------------
+// MATLAB Code for data generation
+// -------------------------------
+// COLUMN_NUM = 4;
+// DATA_I_WIDTH = 12;
+// ACC_NUM = 10;
+
+// rng(0);
+// data = rand(4,2)*2-1;
+// d_12b = round(data.*(2^(DATA_I_WIDTH-1)-1));
+// d_12b_cmplx = d_12b(:,1) + 1i*d_12b(:,2);
+// d_12b_cmplx = d_12b_cmplx(end:-1:1,:);
+// d_12b_acorr = d_12b_cmplx*d_12b_cmplx';
+// d_12b_acorr_real_sim = reshape(flip(reshape(real(d_12b_acorr)',1,16)),4,4);
+// d_12b_acorr_imag_sim = reshape(flip(reshape(imag(d_12b_acorr)',1,16)),4,4);
+// d_12b_acorr_real_sim_sum = ACC_NUM*d_12b_acorr_real_sim;
+// d_12b_acorr_imag_sim_sum = ACC_NUM*d_12b_acorr_imag_sim;
+
+
+// module tb_accum;
+
+// localparam DATA_I_WIDTH  = 24;
+// localparam ACC_WIDTH  = 32;
+// localparam DATA_O_WIDTH = 35;
+// localparam ROW_NUM  = 4;
+// localparam COL_NUM  = 4;
+
+// reg acc_rst = 1'b0;
+
+// reg clk = 1'b1;
+// reg rst = 1'b1;
+// reg din_valid = 'b0;
+// reg [ROW_NUM*COL_NUM*DATA_I_WIDTH-1:0] din_real = 'b0, din_imag = 'b0;
+
+// wire dout_valid;
+// wire [ROW_NUM*COL_NUM*DATA_O_WIDTH-1:0] dout_real, dout_imag;
+
+// accum_cmplx_mat #(
+//     .ROW_NUM        (ROW_NUM),
+//     .COL_NUM        (COL_NUM),
+//     .DATA_I_WIDTH   (DATA_I_WIDTH),
+//     .ACC_WIDTH (ACC_WIDTH),
+//     .DATA_O_WIDTH   (DATA_O_WIDTH),
+//     .ACC_NUM        (1)
+// ) u_accum_cmplx_mat
+// (
+//     // clock & reset
+//     .clk        (clk        ),
+//     .rst        (rst        ),
+//     .acc_rst    (acc_rst    ), // [acc_rst] should assert before accumulation starts
+
+//     // input data
+//     .din_valid  (din_valid  ),
+//     .din_real   (din_real   ),
+//     .din_imag   (din_imag   ),
+
+//     // output data
+//     .dout_valid (dout_valid ),
+//     .dout_real  (dout_real  ),
+//     .dout_imag  (dout_imag  )
+// );
+
+
+// initial begin
+//     #102 rst = 1'b0;
+//     #222;
+//     @(posedge clk)
+//     din_valid = 1'b1;
+//     din_real = {
+//      24'd1952708,     24'd1246152,    -24'd2458370,     24'd2283360,
+//      24'd1246152,     24'd5474825,    -24'd1041611,     24'd2493996,
+//     -24'd2458370,    -24'd1041611,     24'd3154378,    -24'd2757828,
+//      24'd2283360,     24'd2493996,    -24'd2757828,     24'd2899728
+//      };
+
+//      din_imag = {
+//            24'd0,    -24'd3022886,     -24'd340582,     -24'd669768,
+//      24'd3022886,           24'd0,    -24'd4023023,     24'd3107328,
+//       24'd340582,     24'd4023023,           24'd0,     24'd1241460,
+//       24'd669768,    -24'd3107328,    -24'd1241460,           24'd0
+//      };
+
+//     #1002
+//     acc_rst = 1'b1;
+//     #20
+//     acc_rst = 1'b0;
+
+// end
+
+// always #10 clk = ~clk;
+
+
+// endmodule

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/acorr_cmplx_col_vec.v

@@ -0,0 +1,283 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+//
+// Create Date: 2022/10/30 19:27:01
+// Design Name:
+// Module Name: acorr_cmplx_col_vec
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description: Compute the autocorrelation of a complex column vector. The
+//     computation is conducted in fully parallel style.
+// Parameter:
+//   DATA_I_WIDTH: Width of input vector element, the same as of complex
+//      multiplication input data.
+//   CMPY_P_FULL_WIDTH (local): Width of unsigned complex multiplication
+//     output data (The cmpy LogiCore IP does not care whether the input data
+//     are signed or unsigned), which equals to (2*[DATA_MULT_WIDTH]+1).
+//   CMPY_P_VALID_WIDTH (local): Width of signed complex multiplication, which
+//     equals to 2*[DATA_MULT_WIDTH].
+//   DATA_O_WIDTH: Width of output matrix element. If [DATA_O_WIDTH] <=
+//     [DATA_MULT_WIDTH], MSB of valid complex multiplication output will be
+//     truncated; or zeros will be appended.
+// Data format:
+//   din_valid: Indicate [din_real/imag] data are valid.
+//   din_real/imag: Suppose the input column vector x = [x1 x2 x3 x4]^T, then
+//     din_real = {Re{x4}, Re{x3}, Re{x2}, Re{x1}}
+//     din_imag = {Im{x4}, Im{x3}, Im{x2}, Im{x1}}
+//   dout_valid: Indicate [dout_real/imag] data are valid. The latency is
+//     determined by the configuration of the cmpy ip core, which is set to 5
+//     clock cycles by default.
+//   dout_real/imag:
+//     dout_real = {Re{x4*x4^H}, Re{x4*x3^H}, ..., Re{x1*x2^H}, Re{x1*x1^H}}
+//     dout_imag = {Im{x4*x4^H}, Im{x4*x3^H}, ..., Im{x1*x2^H}, Im{x1*x1^H}}
+//
+// Latency: 5 clock cycles for CMPY using LUTs, 6 for DSPs.
+//
+// Dependencies:
+//
+// Revision:
+//   Revision 0.01 - File Created
+//   20230713-1557 - 1. 增加 AXIS 格式转换前后中间变量，便于观察中间结果；2. 输
+//     出位宽大于计算位宽时从符号为扩展变为末尾补零；3. 修改部分变量名称，提升
+//     可读性。
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module acorr_cmplx_col_vec
+#(
+    parameter DATA_I_WIDTH  = 12,
+    parameter DATA_O_WIDTH  = 24,
+    parameter COL_NUM = 4
+)
+(
+    // clock & reset
+    input clk,
+    input rst,
+
+    // input data
+    input din_valid,
+    input [COL_NUM*DATA_I_WIDTH-1:0] din_real,
+    input [COL_NUM*DATA_I_WIDTH-1:0] din_imag,
+
+    // output data
+    output dout_valid,
+    output [COL_NUM*COL_NUM*DATA_O_WIDTH-1:0] dout_real,
+    output [COL_NUM*COL_NUM*DATA_O_WIDTH-1:0] dout_imag
+);
+
+// local parameters
+localparam CMPY_P_FULL_WIDTH = 2*DATA_I_WIDTH+1;
+localparam CMPY_P_VALID_WIDTH = 2*DATA_I_WIDTH;
+localparam AXIS_CMPY_I_WIDTH = 8*((DATA_I_WIDTH-1)/8+1)     ; // axis data width of input real/image data
+localparam AXIS_CMPY_P_WIDTH = 8*((CMPY_P_FULL_WIDTH-1)/8+1); // axis data width of cmpy output real/image data
+
+genvar i,j;
+
+
+// prepare cmpy input data
+wire [DATA_I_WIDTH-1:0] din_real_array [0:COL_NUM-1];
+wire [DATA_I_WIDTH-1:0] din_imag_array [0:COL_NUM-1];
+
+wire [AXIS_CMPY_I_WIDTH-1:0] din_real_array_axis [0:COL_NUM-1];
+wire [AXIS_CMPY_I_WIDTH-1:0] din_imag_array_axis [0:COL_NUM-1];
+
+for(i = 0; i < COL_NUM; i = i + 1) begin: array_conversion
+    // Array split
+    assign din_real_array[i] = din_real[i*DATA_I_WIDTH +: DATA_I_WIDTH];
+    assign din_imag_array[i] = din_imag[i*DATA_I_WIDTH +: DATA_I_WIDTH];
+
+    // Sign extension to fit 8-bit axis data format
+    assign din_real_array_axis[i] = {{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH){din_real_array[i][DATA_I_WIDTH-1]}},din_real[i*DATA_I_WIDTH +: DATA_I_WIDTH]};
+    assign din_imag_array_axis[i] = {{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH){din_imag_array[i][DATA_I_WIDTH-1]}},din_imag[i*DATA_I_WIDTH +: DATA_I_WIDTH]};
+end
+
+
+// complex multiplication
+wire [AXIS_CMPY_P_WIDTH-1:0] cmpy_real_array_axis [0:COL_NUM*COL_NUM-1];
+wire [AXIS_CMPY_P_WIDTH-1:0] cmpy_imag_array_axis [0:COL_NUM*COL_NUM-1];
+
+wire [CMPY_P_VALID_WIDTH-1:0] cmpy_real_array [0:COL_NUM*COL_NUM-1];
+wire [CMPY_P_VALID_WIDTH-1:0] cmpy_imag_array [0:COL_NUM*COL_NUM-1];
+
+wire [DATA_O_WIDTH-1:0] dout_real_array [0:COL_NUM*COL_NUM-1];
+wire [DATA_O_WIDTH-1:0] dout_imag_array [0:COL_NUM*COL_NUM-1];
+
+for(i = 0; i < COL_NUM; i = i + 1) begin: acorr_cmpy_col
+    for(j = 0; j < COL_NUM; j = j + 1) begin: acorr_cmpy_row
+        // cmpy interface
+        wire [2*AXIS_CMPY_I_WIDTH-1:0] cmpy_a;
+        wire [2*AXIS_CMPY_I_WIDTH-1:0] cmpy_b;
+        wire [2*AXIS_CMPY_P_WIDTH-1:0] cmpy_p;
+        wire cmpy_p_vld;
+
+        assign cmpy_a = {din_imag_array_axis[i],din_real_array_axis[i]};
+        assign cmpy_b = {-din_imag_array_axis[j],din_real_array_axis[j]};
+        assign {cmpy_imag_array_axis[i*COL_NUM+j],cmpy_real_array_axis[i*COL_NUM+j]} = cmpy_p;
+
+        assign cmpy_real_array[i*COL_NUM+j] = cmpy_real_array_axis[i*COL_NUM+j][0 +: CMPY_P_VALID_WIDTH];
+        assign cmpy_imag_array[i*COL_NUM+j] = cmpy_imag_array_axis[i*COL_NUM+j][0 +: CMPY_P_VALID_WIDTH];
+
+        cmpy_12x12 u_cmpy_12x12
+        (
+            .aclk               (clk        ), // input wire aclk
+            .s_axis_a_tvalid    (din_valid  ), // input wire s_axis_a_tvalid
+            .s_axis_a_tdata     (cmpy_a     ), // input wire [31 : 0] s_axis_a_tdata
+            .s_axis_b_tvalid    (din_valid  ), // input wire s_axis_b_tvalid
+            .s_axis_b_tdata     (cmpy_b     ), // input wire [31 : 0] s_axis_b_tdata
+            .m_axis_dout_tvalid (cmpy_p_vld ), // output wire m_axis_dout_tvalid
+            .m_axis_dout_tdata  (cmpy_p     )  // output wire [63 : 0] m_axis_dout_tdata
+        );
+
+
+        // output data interface
+        if (DATA_O_WIDTH <= CMPY_P_VALID_WIDTH) begin
+            // truncate msb of the valid part
+            assign dout_real_array[i*COL_NUM+j] = cmpy_real_array[i*COL_NUM+j][CMPY_P_VALID_WIDTH-1 -: DATA_O_WIDTH];
+            assign dout_imag_array[i*COL_NUM+j] = cmpy_imag_array[i*COL_NUM+j][CMPY_P_VALID_WIDTH-1 -: DATA_O_WIDTH];
+        end
+        else begin
+            // append zeros to fit output data width
+            assign dout_real_array[i*COL_NUM+j] = {cmpy_real_array[i*COL_NUM+j],{(DATA_O_WIDTH-CMPY_P_VALID_WIDTH){1'b0}}};
+            assign dout_imag_array[i*COL_NUM+j] = {cmpy_imag_array[i*COL_NUM+j],{(DATA_O_WIDTH-CMPY_P_VALID_WIDTH){1'b0}}};
+        end
+
+        assign dout_real[(i*COL_NUM+j)*DATA_O_WIDTH +: DATA_O_WIDTH] = dout_real_array[i*COL_NUM+j];
+        assign dout_imag[(i*COL_NUM+j)*DATA_O_WIDTH +: DATA_O_WIDTH] = dout_imag_array[i*COL_NUM+j];
+    end
+end
+
+// output mapping
+assign dout_valid = acorr_cmpy_col[0].acorr_cmpy_row[0].cmpy_p_vld;
+
+endmodule
+
+
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+//
+// Create Date: 2022/10/30 20:46:26
+// Design Name:
+// Module Name: acorr_tb
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description: Testbench for [acorr_cmplx_col_vec]
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+// -------------------------------
+// MATLAB Code for data generation
+// -------------------------------
+// COLUMN_NUM = 4;
+// DATA_I_WIDTH = 12;
+
+// rng(0);
+// data = (rand(4,2)*2-1) + 1i*(rand(4,2)*2-1);
+// d_12b = round(data/max(max(abs(data)))*(2^11-1));
+// d_12b_real = real(d_12b(end:-1:1,:));
+// d_12b_imag = imag(d_12b(end:-1:1,:));
+// d_12b_acorr(:,:,1) = d_12b(:,1)*d_12b(:,1)';
+// d_12b_acorr(:,:,2) = d_12b(:,2)*d_12b(:,2)';
+
+
+// module tb_acorr;
+
+// localparam ROW_NUM  = 1;
+// localparam COL_NUM  = 4;
+// localparam DATA_I_WIDTH  = 12;
+// localparam DATA_O_WIDTH  = 23;
+
+// reg acc_rst = 1'b0;
+
+// reg clk = 1'b1;
+// reg rst = 1'b1;
+// reg din_valid = 'b0;
+// reg [COL_NUM*DATA_I_WIDTH-1:0] din_real = 'b0, din_imag = 'b0;
+
+// wire dout_valid;
+// wire [COL_NUM*COL_NUM*DATA_O_WIDTH-1:0] dout_real, dout_imag;
+
+// acorr_cmplx_col_vec #(
+//     .COL_NUM        (COL_NUM),
+//     .DATA_I_WIDTH   (DATA_I_WIDTH),
+//     .DATA_O_WIDTH   (DATA_O_WIDTH)
+// ) u_acorr_cmplx_col_vec
+// (
+//     // clock & reset
+//     .clk        (clk        ),
+//     .rst        (rst        ),
+
+//     // input data
+//     .din_valid  (din_valid  ),
+//     .din_real   (din_real   ),
+//     .din_imag   (din_imag   ),
+
+//     // output data
+//     .dout_valid (dout_valid ),
+//     .dout_real  (dout_real  ),
+//     .dout_imag  (dout_imag  )
+// );
+
+
+// initial begin
+//     #102 rst = 1'b0;
+//     #222;
+//     @(posedge clk)
+//     din_valid = 1'b1;
+//     din_real = {
+//      12'd1351,
+//     -12'd1219,
+//      12'd1326,
+//      12'd1029};
+
+//     din_imag = {
+//     12'd1538,
+//     -12'd1119,
+//     12'd1519,
+//     12'd1495};
+
+//     @(posedge clk)
+//     din_valid = 1'b0;
+
+//     @(posedge clk)
+//     din_valid = 1'b1;
+//     din_real = {
+//      12'd153 ,
+//     -12'd724 ,
+//     -12'd1315,
+//      12'd433 };
+
+//     din_imag = {
+//     -12'd1170,
+//     12'd981 ,
+//     -12'd48  ,
+//     12'd1494};
+// end
+
+// always #10 clk = ~clk;
+
+
+// endmodule

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/ad9361_phase_cal_coarse.v

@@ -0,0 +1,443 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+//
+// Create Date: 2022/09/14 16:45:10
+// Last Modified Data: 2023/02/12 17:10
+// Design Name:
+// Module Name: ad9361_phase_cal_coarse
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+//   2022/09/14 16:45:10 - File Created
+//   2023/02/12 17:10 - 修改：校准未完成时，将输入信号寄存输出。
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module ad9361_phase_cal_coarse
+#(
+    parameter COUNTER_MOD = 48,
+    parameter PEAK_POS = 12,
+    parameter ADC_DATA_WIDTH = 12
+)
+(
+    // clock & reset
+    input           clk                     ,
+    input           rst                     ,
+    // control interface
+    input           ad9361_1_cal_start      ,
+    output          ad9361_1_cal_done       ,
+    input           ad9361_2_cal_start      ,
+    output          ad9361_2_cal_done       ,
+    output          ad9361_cal_result       ,
+    output          ad9361_cal_valid        ,
+    input           ad9361_recal            ,
+    // input data interface
+    input [ADC_DATA_WIDTH-1:0] rx_ch1_i     ,
+    input [ADC_DATA_WIDTH-1:0] rx_ch1_q     ,
+    input [ADC_DATA_WIDTH-1:0] rx_ch2_i     ,
+    input [ADC_DATA_WIDTH-1:0] rx_ch2_q     ,
+    input [ADC_DATA_WIDTH-1:0] rx_ch3_i     ,
+    input [ADC_DATA_WIDTH-1:0] rx_ch3_q     ,
+    input [ADC_DATA_WIDTH-1:0] rx_ch4_i     ,
+    input [ADC_DATA_WIDTH-1:0] rx_ch4_q     ,
+    // output data interface
+    output [ADC_DATA_WIDTH-1:0] rx_cal_ch1_i,
+    output [ADC_DATA_WIDTH-1:0] rx_cal_ch1_q,
+    output [ADC_DATA_WIDTH-1:0] rx_cal_ch2_i,
+    output [ADC_DATA_WIDTH-1:0] rx_cal_ch2_q,
+    output [ADC_DATA_WIDTH-1:0] rx_cal_ch3_i,
+    output [ADC_DATA_WIDTH-1:0] rx_cal_ch3_q,
+    output [ADC_DATA_WIDTH-1:0] rx_cal_ch4_i,
+    output [ADC_DATA_WIDTH-1:0] rx_cal_ch4_q
+);
+
+localparam STATE_IDLE = 2'd0;
+localparam STATE_CAL_1 = 2'd1;
+localparam STATE_CAL_2 = 2'd2;
+localparam STATE_DONE = 2'd3;
+
+// buffer input control signals
+reg             ad9361_1_cal_start_d1 = 'b0;
+reg             ad9361_1_cal_start_d2 = 'b0;
+reg             ad9361_2_cal_start_d1 = 'b0;
+reg             ad9361_2_cal_start_d2 = 'b0;
+reg             ad9361_recal_d1 = 'b0;
+reg             ad9361_recal_d2 = 'b0;
+
+always @(posedge clk) begin
+    ad9361_1_cal_start_d1 <= ad9361_1_cal_start;
+    ad9361_1_cal_start_d2 <= ad9361_1_cal_start_d1;
+
+    ad9361_2_cal_start_d1 <= ad9361_2_cal_start;
+    ad9361_2_cal_start_d2 <= ad9361_2_cal_start_d1;
+
+    ad9361_recal_d1 <= ad9361_recal;
+    ad9361_recal_d2 <= ad9361_recal_d1;
+end
+
+// center state machine
+reg     [ 1:0]  curr_state = STATE_IDLE;
+
+always @(posedge clk) begin
+    if (rst) begin
+        curr_state <= STATE_IDLE;
+    end
+    else begin
+        case (curr_state)
+            STATE_IDLE: begin
+                // move to next state when [ad9361_1_cal_start] asserts
+                curr_state <= ad9361_1_cal_start_d2 ? STATE_CAL_1 : STATE_IDLE;
+            end
+            STATE_CAL_1: begin
+                // move to next state when 1st cal finishes [ad9361_2_cal_start] asserts
+                curr_state <= (ad9361_1_cal_done && ad9361_2_cal_start_d2) ? STATE_CAL_2 : STATE_CAL_1;
+            end
+            STATE_CAL_2: begin
+                // move to next state when 2nd cal finishes
+                curr_state <= ad9361_2_cal_done ? STATE_DONE : STATE_CAL_2;
+            end
+            STATE_DONE: begin
+                // move to ILDA state when it needs to recal
+                curr_state <= (ad9361_recal_d2) ? STATE_IDLE : STATE_DONE;
+            end
+            default: begin
+                curr_state <= STATE_IDLE;
+            end
+        endcase
+    end
+end
+
+//
+reg rx_ch2_i_msb_d1 = 'b0;
+reg cnt_start = 'b0;
+reg cnt_start_flag = 'b0;
+reg [$clog2(COUNTER_MOD)-1:0] cnt = 'b0;
+reg [ADC_DATA_WIDTH-1:0] rx_ch2_i_rec = 'b0;
+reg rx_ch2_i_rec_flag = 'b0;
+
+assign ad9361_1_cal_done = rx_ch2_i_rec_flag;
+
+always @(posedge clk) begin
+    if (rst) begin
+        rx_ch2_i_msb_d1 <= 'b0;
+    end
+    else if (curr_state == STATE_IDLE) begin
+        // reset at IDLE state
+        rx_ch2_i_msb_d1 <= 'b0;
+    end
+    else if (curr_state == STATE_CAL_1) begin
+        rx_ch2_i_msb_d1 <= rx_ch2_i[ADC_DATA_WIDTH-1];
+    end
+    else begin
+        rx_ch2_i_msb_d1 <= rx_ch2_i_msb_d1;
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        cnt_start <= 'b0;
+    end
+    else if (curr_state == STATE_IDLE) begin
+        // reset at IDLE state
+        cnt_start <= 'b0;
+    end
+    else if (curr_state == STATE_CAL_1 && ~cnt_start) begin
+        // assert when the 1st falling edge of msb of rx_ch2_i is detected
+        cnt_start <= (rx_ch2_i_msb_d1 & ~rx_ch2_i[ADC_DATA_WIDTH-1]) ? 1'b1 : 1'b0;
+    end
+    else begin
+        cnt_start <= cnt_start;
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        cnt <= 'b0;
+    end
+    else if (curr_state == STATE_IDLE) begin
+        // reset at IDLE state
+        cnt <= 'b0;
+    end
+    else if (cnt_start) begin
+        cnt <= (cnt == COUNTER_MOD - 1) ? 'b0 : cnt + 1'b1;
+    end
+    else begin
+        cnt <= cnt;
+    end
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        rx_ch2_i_rec <= 'b0;
+        rx_ch2_i_rec_flag <= 'b0;
+    end
+    else if (curr_state == STATE_IDLE) begin
+        // reset at IDLE state
+        rx_ch2_i_rec <= 'b0;
+        rx_ch2_i_rec_flag <= 'b0;
+    end
+    else if (curr_state == STATE_CAL_1 && cnt == PEAK_POS && ~rx_ch2_i_rec_flag) begin
+        rx_ch2_i_rec <= rx_ch2_i;
+        rx_ch2_i_rec_flag <= 1'b1;
+    end
+    else begin
+        rx_ch2_i_rec <= rx_ch2_i_rec;
+        rx_ch2_i_rec_flag <= rx_ch2_i_rec_flag;
+    end
+end
+
+//
+reg [ADC_DATA_WIDTH-1:0] rx_ch4_i_rec = 'b0;
+reg rx_ch4_i_rec_flag = 'b0;
+
+assign ad9361_2_cal_done = rx_ch4_i_rec_flag;
+
+always @(posedge clk) begin
+    if (rst) begin
+        rx_ch4_i_rec <= 'b0;
+        rx_ch4_i_rec_flag <= 'b0;
+    end
+    else if (curr_state == STATE_IDLE) begin
+        // reset at IDLE state
+        rx_ch4_i_rec <= 'b0;
+        rx_ch4_i_rec_flag <= 'b0;
+    end
+    else if (curr_state == STATE_CAL_2 && cnt == COUNTER_MOD/4 && ~rx_ch4_i_rec_flag) begin
+        rx_ch4_i_rec <= rx_ch4_i;
+        rx_ch4_i_rec_flag <= 1'b1;
+    end
+    else begin
+        rx_ch4_i_rec <= rx_ch4_i_rec;
+        rx_ch4_i_rec_flag <= rx_ch4_i_rec_flag;
+    end
+end
+
+
+reg ad9361_cal_valid_buf = 'b0;
+reg ad9361_cal_result_buf = 'b0;
+reg [ADC_DATA_WIDTH-1:0] rx_cal_ch1_i_buf = 'b0;
+reg [ADC_DATA_WIDTH-1:0] rx_cal_ch2_i_buf = 'b0;
+reg [ADC_DATA_WIDTH-1:0] rx_cal_ch3_i_buf = 'b0;
+reg [ADC_DATA_WIDTH-1:0] rx_cal_ch4_i_buf = 'b0;
+reg [ADC_DATA_WIDTH-1:0] rx_cal_ch1_q_buf = 'b0;
+reg [ADC_DATA_WIDTH-1:0] rx_cal_ch2_q_buf = 'b0;
+reg [ADC_DATA_WIDTH-1:0] rx_cal_ch3_q_buf = 'b0;
+reg [ADC_DATA_WIDTH-1:0] rx_cal_ch4_q_buf = 'b0;
+
+assign ad9361_cal_valid = ad9361_cal_valid_buf;
+assign ad9361_cal_result = ad9361_cal_result_buf;
+assign rx_cal_ch1_i = rx_cal_ch1_i_buf;
+assign rx_cal_ch2_i = rx_cal_ch2_i_buf;
+assign rx_cal_ch3_i = rx_cal_ch3_i_buf;
+assign rx_cal_ch4_i = rx_cal_ch4_i_buf;
+assign rx_cal_ch1_q = rx_cal_ch1_q_buf;
+assign rx_cal_ch2_q = rx_cal_ch2_q_buf;
+assign rx_cal_ch3_q = rx_cal_ch3_q_buf;
+assign rx_cal_ch4_q = rx_cal_ch4_q_buf;
+
+always @(posedge clk) begin
+    if (rst) begin
+        ad9361_cal_valid_buf <= 'b0;
+        ad9361_cal_result_buf <= 'b0;
+        rx_cal_ch1_i_buf <= 'b0;
+        rx_cal_ch2_i_buf <= 'b0;
+        rx_cal_ch3_i_buf <= 'b0;
+        rx_cal_ch4_i_buf <= 'b0;
+        rx_cal_ch1_q_buf <= 'b0;
+        rx_cal_ch2_q_buf <= 'b0;
+        rx_cal_ch3_q_buf <= 'b0;
+        rx_cal_ch4_q_buf <= 'b0;
+    end
+    else if (curr_state == STATE_DONE) begin
+        ad9361_cal_valid_buf <= 1'b1;
+
+        if (rx_ch2_i_rec[ADC_DATA_WIDTH-1] == rx_ch4_i_rec[ADC_DATA_WIDTH-1]) begin
+            ad9361_cal_result_buf <= 'b0;
+            rx_cal_ch1_i_buf <=  rx_ch1_i;
+            rx_cal_ch1_q_buf <=  rx_ch1_q;
+            rx_cal_ch2_i_buf <= -rx_ch2_i;
+            rx_cal_ch2_q_buf <= -rx_ch2_q;
+            rx_cal_ch3_i_buf <=  rx_ch3_i;
+            rx_cal_ch3_q_buf <=  rx_ch3_q;
+            rx_cal_ch4_i_buf <= -rx_ch4_i;
+            rx_cal_ch4_q_buf <= -rx_ch4_q;
+        end
+        else begin
+            ad9361_cal_result_buf <= 'b1;
+            rx_cal_ch1_i_buf <=  rx_ch1_i;
+            rx_cal_ch1_q_buf <=  rx_ch1_q;
+            rx_cal_ch2_i_buf <= -rx_ch2_i;
+            rx_cal_ch2_q_buf <= -rx_ch2_q;
+            rx_cal_ch3_i_buf <= -rx_ch3_i;
+            rx_cal_ch3_q_buf <= -rx_ch3_q;
+            rx_cal_ch4_i_buf <=  rx_ch4_i;
+            rx_cal_ch4_q_buf <=  rx_ch4_q;
+        end
+    end
+    else begin
+        ad9361_cal_valid_buf <= 1'b0;
+        ad9361_cal_result_buf <= ad9361_cal_result_buf;
+        rx_cal_ch1_i_buf <= rx_ch1_i;
+        rx_cal_ch2_i_buf <= rx_ch2_i;
+        rx_cal_ch3_i_buf <= rx_ch3_i;
+        rx_cal_ch4_i_buf <= rx_ch4_i;
+        rx_cal_ch1_q_buf <= rx_ch1_q;
+        rx_cal_ch2_q_buf <= rx_ch2_q;
+        rx_cal_ch3_q_buf <= rx_ch3_q;
+        rx_cal_ch4_q_buf <= rx_ch4_q;
+    end
+end
+
+endmodule
+
+
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+//
+// Create Date: 2022/09/15 11:12:45
+// Last Modified Data: 2022/11/02
+// Design Name:
+// Module Name: tb_ad9361_cal_coarse
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description: testbench for [ad9361_phase_cal_coarse]
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+// module tb_ad9361_cal_coarse;
+
+// reg  clk = 'b0;
+// reg  rst = 1'b1;
+
+// reg  ad9361_1_cal_start = 'b0;
+// wire ad9361_1_cal_done ;
+// reg  ad9361_2_cal_start = 'b0;
+// wire ad9361_2_cal_done ;
+// wire ad9361_cal_result ;
+// wire ad9361_cal_valid;
+// reg  ad9361_recal       = 'b0;
+
+// // phase difference of 180 degree
+// reg [11:0] rx_ch1_i  = 12'd2047;
+// reg [11:0] rx_ch1_q  = 12'd2047;
+// reg [11:0] rx_ch2_i  = -12'd2047;
+// reg [11:0] rx_ch2_q  = -12'd2047;
+// reg [11:0] rx_ch3_q  = -12'd2047;
+// reg [11:0] rx_ch3_i  = -12'd2047;
+// reg [11:0] rx_ch4_i  = 12'd2047;
+// reg [11:0] rx_ch4_q  = 12'd2047;
+
+// wire [11:0] rx_cal_ch1_i;
+// wire [11:0] rx_cal_ch2_i;
+// wire [11:0] rx_cal_ch3_i;
+// wire [11:0] rx_cal_ch4_i;
+// wire [11:0] rx_cal_ch1_q;
+// wire [11:0] rx_cal_ch2_q;
+// wire [11:0] rx_cal_ch3_q;
+// wire [11:0] rx_cal_ch4_q;
+
+// ad9361_phase_cal #(
+//     .COUNTER_MOD    (48),
+//     .PEAK_POS       (12)
+// ) u_ad9361_phase_cal
+// (
+//     // clock & reset
+//     .clk                (clk                ), // input           clk
+//     .rst                (rst                ), // input           rst
+//     // control interface
+//     .ad9361_1_cal_start (ad9361_1_cal_start ), // input           ad9361_1_cal_start
+//     .ad9361_1_cal_done  (ad9361_1_cal_done  ), // output          ad9361_1_cal_done
+//     .ad9361_2_cal_start (ad9361_2_cal_start ), // input           ad9361_2_cal_start
+//     .ad9361_2_cal_done  (ad9361_2_cal_done  ), // output          ad9361_2_cal_done
+//     .ad9361_cal_result  (ad9361_cal_result  ), // output          ad9361_cal_result
+//     .ad9361_cal_valid   (ad9361_cal_valid   ), // output          ad9361_cal_valid
+//     .ad9361_recal       (ad9361_recal       ), // input           ad9361_recal
+//     // input data interface
+//     .rx_ch1_i           (rx_ch1_i           ), // input   [11:0]  rx_ch1_i
+//     .rx_ch2_i           (rx_ch2_i           ), // input   [11:0]  rx_ch2_i
+//     .rx_ch3_i           (rx_ch3_i           ), // input   [11:0]  rx_ch3_i
+//     .rx_ch4_i           (rx_ch4_i           ), // input   [11:0]  rx_ch4_i
+//     .rx_ch1_q           (rx_ch1_q           ), // input   [11:0]  rx_ch1_q
+//     .rx_ch2_q           (rx_ch2_q           ), // input   [11:0]  rx_ch2_q
+//     .rx_ch3_q           (rx_ch3_q           ), // input   [11:0]  rx_ch3_q
+//     .rx_ch4_q           (rx_ch4_q           ), // input   [11:0]  rx_ch4_q
+//     // output data interface
+//     .rx_cal_ch1_i       (rx_cal_ch1_i       ), // output  [11:0]  rx_cal_ch1_i
+//     .rx_cal_ch2_i       (rx_cal_ch2_i       ), // output  [11:0]  rx_cal_ch2_i
+//     .rx_cal_ch3_i       (rx_cal_ch3_i       ), // output  [11:0]  rx_cal_ch3_i
+//     .rx_cal_ch4_i       (rx_cal_ch4_i       ), // output  [11:0]  rx_cal_ch4_i
+//     .rx_cal_ch1_q       (rx_cal_ch1_q       ), // output  [11:0]  rx_cal_ch1_q
+//     .rx_cal_ch2_q       (rx_cal_ch2_q       ), // output  [11:0]  rx_cal_ch2_q
+//     .rx_cal_ch3_q       (rx_cal_ch3_q       ), // output  [11:0]  rx_cal_ch3_q
+//     .rx_cal_ch4_q       (rx_cal_ch4_q       )  // output  [11:0]  rx_cal_ch4_q
+// );
+
+// initial begin
+//     #102
+//     rst = 1'b0;
+//     #100
+//     ad9361_1_cal_start = 1'b1;
+// end
+
+// initial begin
+//     #10000
+//     ad9361_recal = 1'b1;
+//     #20
+//     ad9361_recal = 1'b0;
+// end
+
+// always begin
+//     #2 clk = ~clk;
+// end
+
+// always begin
+//     #72
+//     rx_ch1_i = ~rx_ch1_i;
+//     rx_ch2_i = ~rx_ch2_i;
+//     rx_ch3_i = ~rx_ch3_i;
+//     rx_ch4_i = ~rx_ch4_i;
+//     #24
+//     rx_ch1_q = ~rx_ch1_q;
+//     rx_ch2_q = ~rx_ch2_q;
+//     rx_ch3_q = ~rx_ch3_q;
+//     rx_ch4_q = ~rx_ch4_q;
+// end
+
+// always @(posedge clk) begin
+//     if (ad9361_1_cal_done) begin
+//         ad9361_2_cal_start <= 1'b1;
+//     end
+//     else begin
+//         ad9361_2_cal_start <= 1'b0;
+//     end
+// end
+
+// endmodule

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/null_ctrl.v

@@ -0,0 +1,800 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+//
+// Create Date: 07/17/2023 05:26:54 PM
+// Design Name:
+// Module Name: null_ctrl
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module null_ctrl
+#(
+  parameter ADC_WIDTH      = 12       ,
+  parameter CH_NUM         = 4        ,
+  parameter SYNC_HOP_INTVL = 48*1000  , // 1 ms of 48M clock, must > 48*200
+  parameter STABLE_CNT_MOD = 48*5     , // 5 us of 48M clock
+  parameter SNAPSHOT_NUM   = 2048     ,
+  parameter GUARD_CNT_MOD  = 48*50    , // 50 us of 48M clock
+  parameter ACCUM_WIDTH    = 32       ,
+  parameter ACORR_WIDTH    = 2*ADC_WIDTH,
+  parameter WEIGHT_WIDTH   = 16 ,
+  parameter OUTPUT_WIDTH   = ADC_WIDTH,
+  parameter LCMV_WIDTH     = ADC_WIDTH + WEIGHT_WIDTH + $clog2(CH_NUM)
+)
+(
+  // ***************************************************************************
+  // ***************************** clock & reset *******************************
+  // ***************************************************************************
+  input clk                                                 ,
+  input clk_phy                                             ,
+  input rst                                                 ,
+
+  //
+  input hop_flag_in_phy                                     ,
+  input sync_flag_phy                                       ,
+  input lcmv_en_phy                                         ,
+  output hop_flag_out                                       ,
+  // ***************************************************************************
+  // **************************** ADC Input Data *******************************
+  // ***************************************************************************
+  input adc_din_valid                                       ,
+  input [CH_NUM*ADC_WIDTH-1 : 0] adc_din_real               ,
+  input [CH_NUM*ADC_WIDTH-1 : 0] adc_din_imag               ,
+
+  // ***************************************************************************
+  // **************************** Autocorrelation ******************************
+  // ***************************************************************************
+  output acorr_din_valid                                    ,
+  output [CH_NUM*ADC_WIDTH-1 : 0] acorr_din_real            ,
+  output [CH_NUM*ADC_WIDTH-1 : 0] acorr_din_imag            ,
+
+  input acorr_dout_valid                                    ,
+  input [CH_NUM*CH_NUM*ACORR_WIDTH-1:0] acorr_dout_real     ,
+  input [CH_NUM*CH_NUM*ACORR_WIDTH-1:0] acorr_dout_imag     ,
+
+  // ***************************************************************************
+  // **************************** Accumulation *********************************
+  // ***************************************************************************
+  output accum_rst                                          ,
+
+  output accum_din_valid                                    ,
+  output [CH_NUM*CH_NUM*ACORR_WIDTH-1:0] accum_din_real     ,
+  output [CH_NUM*CH_NUM*ACORR_WIDTH-1:0] accum_din_imag     ,
+
+  input accum_dout_valid                                    ,
+  input [CH_NUM*CH_NUM*ACCUM_WIDTH-1:0] accum_dout_real     ,
+  input [CH_NUM*CH_NUM*ACCUM_WIDTH-1:0] accum_dout_imag     ,
+
+  // ***************************************************************************
+  // ************************* Parallel to Serial ******************************
+  // ***************************************************************************
+  output stream_fifo_rst                                    ,
+
+  output stream_din_valid                                   ,
+  output [CH_NUM*CH_NUM*ACCUM_WIDTH-1 : 0] stream_din_real  ,
+  output [CH_NUM*CH_NUM*ACCUM_WIDTH-1 : 0] stream_din_imag  ,
+
+  // ***************************************************************************
+  // ************************* Serial to Parallel ******************************
+  // ***************************************************************************
+  output weight_fifo_rst                                    ,
+
+  input weight_dout_valid                                   ,
+  input [CH_NUM*WEIGHT_WIDTH-1 : 0] weight_dout_real        ,
+  input [CH_NUM*WEIGHT_WIDTH-1 : 0] weight_dout_imag        ,
+
+  // ***************************************************************************
+  // **************************** Spatial Filter *******************************
+  // ***************************************************************************
+  // input weight vector
+  output filter_weight_valid                                ,
+  output [CH_NUM*WEIGHT_WIDTH-1 : 0] filter_weight_real     ,
+  output [CH_NUM*WEIGHT_WIDTH-1 : 0] filter_weight_imag     ,
+
+  // input adc data
+  output filter_din_valid                                   ,
+  output [CH_NUM*ADC_WIDTH-1 : 0] filter_din_real           ,
+  output [CH_NUM*ADC_WIDTH-1 : 0] filter_din_imag           ,
+
+  // output data
+  input filter_dout_valid                                   ,
+  input [LCMV_WIDTH-1 : 0] filter_dout_real                 ,
+  input [LCMV_WIDTH-1 : 0] filter_dout_imag                 ,
+
+  // ***************************************************************************
+  // *************************** Output Data Port ******************************
+  // ***************************************************************************
+  output null_dout_valid                                    ,
+  output [OUTPUT_WIDTH-1 : 0] null_dout_real                ,
+  output [OUTPUT_WIDTH-1 : 0] null_dout_imag
+);
+
+localparam RAM_HOP_DEPTH = 9600;
+
+// hop flag delay of data segment when lcmv is enabled
+//   1 for rom addr reset
+//   1 for rom read data
+//   7 for spatial filter
+//   1 for buffering spatial filter input data - whether last or current hop
+//   1 for buffering spatial filter output data - whether lcmv or das
+localparam LCMV_DELAY = RAM_HOP_DEPTH + 11;
+
+// hop flag delay of data segment when lcmv is enabled
+//   2 for multi-channel addition
+//   1 for buffering output data
+localparam DAS_DELAY = 3;
+
+localparam CMPLX_DIM = 2;
+localparam NULL_DELAY = RAM_HOP_DEPTH + 6;
+localparam DAS_WIDTH = ADC_WIDTH + $clog2(CH_NUM);
+// autocorrelation state machine
+localparam ACORR_STATE_NUM    = 4;
+localparam ACORR_STATE_IDLE   = 0;
+localparam ACORR_STATE_STABLE = 1; // wait until rf is stable
+localparam ACORR_STATE_CALC   = 2; // autocorrelation calculation and formatting
+localparam ACORR_STATE_GUARD  = 3; // guard for data transmission and inverse calculation
+
+integer i;
+
+////////////////////////////////////////////////////////////////////////////////
+//////////////////////////// Clock Domain Crossing /////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+wire hop_flag_in ; // input hop flag, pulse, level detection
+wire sync_flag   ; // input sync segment indicator, 1 for sync segment, 0 for
+                   //   data segment, level, level detection
+wire lcmv_en     ; // input nulling algorithm enable control, 1 for enable, 2
+                   //   for disable, level, level detection. If frequency
+                   //   hopping is enabled in sync segment, nulling should be
+                   //   turned off, because spatial anti-jamming cannot work
+                   //   properly in this scenario.
+// wire hop_flag_out; // output hop flag, pulse
+
+// hop_flag_in, input
+xpm_cdc_pulse #(
+  .DEST_SYNC_FF   (4), // DECIMAL; range: 2-10
+  .INIT_SYNC_FF   (1), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
+  .REG_OUTPUT     (1), // DECIMAL; 0=disable registered output, 1=enable registered output
+  .RST_USED       (0), // DECIMAL; 0=no reset, 1=implement reset
+  .SIM_ASSERT_CHK (1)  // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
+) u_hop_flag_in
+(
+  .dest_pulse (hop_flag_in    ), // 1-bit output: Outputs a pulse the size of one dest_clk period when a pulse
+                                 // transfer is correctly initiated on src_pulse input. This output is
+                                 // combinatorial unless REG_OUTPUT is set to 1.
+  .dest_clk   (clk            ), // 1-bit input: Destination clock.
+  .dest_rst   (1'b1           ), // 1-bit input: optional; required when RST_USED = 1
+  .src_clk    (clk_phy        ), // 1-bit input: Source clock.
+  .src_pulse  (hop_flag_in_phy), // 1-bit input: Rising edge of this signal initiates a pulse transfer to the
+                                 // destination clock domain. The minimum gap between each pulse transfer must be
+                                 // at the minimum 2*(larger(src_clk period, dest_clk period)). This is measured
+                                 // between the falling edge of a src_pulse to the rising edge of the next
+                                 // src_pulse. This minimum gap will guarantee that each rising edge of src_pulse
+                                 // will generate a pulse the size of one dest_clk period in the destination
+                                 // clock domain. When RST_USED = 1, pulse transfers will not be guaranteed while
+                                 // src_rst and/or dest_rst are asserted.
+  .src_rst    (1'b1           )  // 1-bit input: optional; required when RST_USED = 1
+);
+
+// sync_flag, input
+xpm_cdc_single #(
+  .DEST_SYNC_FF   (4), // DECIMAL; range: 2-10
+  .INIT_SYNC_FF   (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
+  .SIM_ASSERT_CHK (0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
+  .SRC_INPUT_REG  (1)  // DECIMAL; 0=do not register input, 1=register input
+)
+u_sync_flag (
+  .dest_out (sync_flag      ), // 1-bit output: src_in synchronized to the destination clock domain. This output is
+                               // registered.
+  .dest_clk (clk            ), // 1-bit input: Clock signal for the destination clock domain.
+  .src_clk  (clk_phy        ), // 1-bit input: optional; required when SRC_INPUT_REG = 1
+  .src_in   (sync_flag_phy  )  // 1-bit input: Input signal to be synchronized to dest_clk domain.
+);
+
+// lcmv_en, input
+xpm_cdc_single #(
+  .DEST_SYNC_FF   (4), // DECIMAL; range: 2-10
+  .INIT_SYNC_FF   (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
+  .SIM_ASSERT_CHK (0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
+  .SRC_INPUT_REG  (1)  // DECIMAL; 0=do not register input, 1=register input
+)
+u_lcmv_en (
+  .dest_out (lcmv_en      ), // 1-bit output: src_in synchronized to the destination clock domain. This output is
+                               // registered.
+  .dest_clk (clk          ), // 1-bit input: Clock signal for the destination clock domain.
+  .src_clk  (clk_phy      ), // 1-bit input: optional; required when SRC_INPUT_REG = 1
+  .src_in   (lcmv_en_phy  )  // 1-bit input: Input signal to be synchronized to dest_clk domain.
+);
+
+// hop_flag_out, output
+// xpm_cdc_pulse #(
+//   .DEST_SYNC_FF   (4),  // DECIMAL; range: 2-10
+//   .INIT_SYNC_FF   (1),  // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
+//   .REG_OUTPUT     (1),  // DECIMAL; 0=disable registered output, 1=enable registered output
+//   .RST_USED       (0),  // DECIMAL; 0=no reset, 1=implement reset
+//   .SIM_ASSERT_CHK (1)   // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
+// ) u_hop_flag_out
+// (
+//   .dest_pulse (hop_flag_out_phy ),
+//   .dest_clk   (clk_phy          ),
+//   .dest_rst   (1'b1             ),
+//   .src_clk    (clk              ),
+//   .src_pulse  (hop_flag_out     ),
+//   .src_rst    (1'b1             )
+// );
+
+
+////////////////////////////////////////////////////////////////////////////////
+/////////////////////////// Autocorrelation Control ////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+
+// <--------------------------------------------------------------------------->
+// <-------------------- sync segment hop flag generation --------------------->
+// <--------------------------------------------------------------------------->
+reg [$clog2(SYNC_HOP_INTVL)-1 : 0] sync_hop_cnt = 'b0;
+reg sync_hop_flag = 'b0;
+
+always @(posedge clk) begin
+  if (rst) begin
+    sync_hop_cnt  <= 'b0;
+    sync_hop_flag <= 'b0;
+  end
+  else if (sync_flag && lcmv_en) begin
+    // During sync segment and when nulling algorithm is enabled
+
+    // Counter period is controlled by [SYNC_HOP_INTVL]
+    sync_hop_cnt  <= (sync_hop_cnt == SYNC_HOP_INTVL - 1) ? 'b0 : sync_hop_cnt + 1'b1;
+    // For protection, assert 10 us after entering sync segment
+    sync_hop_flag <= (sync_hop_cnt == 48*10 - 1) ? 1'b1 : 'b0;
+  end
+  else begin
+    sync_hop_cnt  <= 'b0;
+    sync_hop_flag <= 'b0;
+  end
+end
+
+// <--------------------------------------------------------------------------->
+// <---------------------- autocorrelation state machine ---------------------->
+// <--------------------------------------------------------------------------->
+reg [$clog2(ACORR_STATE_NUM)-1 : 0] acorr_curr_state = ACORR_STATE_IDLE;
+reg [$clog2(ACORR_STATE_NUM)-1 : 0] acorr_next_state = ACORR_STATE_IDLE;
+reg [$clog2(STABLE_CNT_MOD)-1 : 0] stable_cnt = 'b0;
+reg [$clog2(SNAPSHOT_NUM)-1 : 0] snapshot_cnt = 'b0;
+reg [$clog2(GUARD_CNT_MOD)-1 : 0] guard_cnt = 'b0;
+reg snapshot_valid = 'b0;
+reg accum_rst_buf = 'b0;
+reg fifo_cdc_rst_buf = 'b0;
+
+// 1st always block, sequential state transition
+always @(posedge clk) begin
+  if (rst) begin
+    acorr_curr_state <= ACORR_STATE_IDLE;
+  end
+  else begin
+    acorr_curr_state <= acorr_next_state;
+  end
+end
+
+// 2nd always block, combinational condition judgment
+always @(*) begin
+  case (acorr_curr_state)
+    ACORR_STATE_IDLE:   begin
+                          if (adc_din_valid && lcmv_en) begin
+                            // if adc data is valid & lcmv is enabled
+                            if ((sync_flag && sync_hop_flag) || (~sync_flag && hop_flag_in)) begin
+                              acorr_next_state = ACORR_STATE_STABLE;
+                            end
+                            else begin
+                              acorr_next_state = ACORR_STATE_IDLE;
+                            end
+                          end
+                          else begin
+                            acorr_next_state = ACORR_STATE_IDLE;
+                          end
+                        end
+    ACORR_STATE_STABLE: begin
+                          if (stable_cnt == STABLE_CNT_MOD-1) begin
+                            acorr_next_state = ACORR_STATE_CALC;
+                          end
+                          else begin
+                            acorr_next_state = ACORR_STATE_STABLE;
+                          end
+                        end
+    ACORR_STATE_CALC:   begin
+                          if (snapshot_cnt == SNAPSHOT_NUM-1) begin
+                            acorr_next_state = ACORR_STATE_GUARD;
+                          end
+                          else begin
+                            acorr_next_state = ACORR_STATE_CALC;
+                          end
+                        end
+    ACORR_STATE_GUARD:  begin
+                          if (guard_cnt == GUARD_CNT_MOD-1) begin
+                            acorr_next_state = ACORR_STATE_IDLE;
+                          end
+                          else begin
+                            acorr_next_state = ACORR_STATE_GUARD;
+                          end
+                        end
+    default:            begin
+                          acorr_next_state = ACORR_STATE_IDLE;
+                        end
+  endcase
+end
+
+// 3rd always block, the sequential FSM output
+always @(posedge clk) begin
+  if (rst) begin
+    stable_cnt     <= 'b0;
+    snapshot_cnt   <= 'b0;
+    guard_cnt      <= 'b0;
+    snapshot_valid <= 'b0;
+    accum_rst_buf  <= 'b0;
+  end
+  else begin
+    case (acorr_curr_state)
+      ACORR_STATE_STABLE: begin
+                            stable_cnt   <= stable_cnt + 1'b1;
+                            snapshot_cnt <= 'b0;
+                            guard_cnt    <= 'b0;
+                          end
+      ACORR_STATE_CALC:   begin
+                            stable_cnt   <= stable_cnt;
+                            snapshot_cnt <= snapshot_cnt + 1'b1;
+                            guard_cnt    <= 'b0;
+                          end
+      ACORR_STATE_GUARD:  begin
+                            stable_cnt   <= stable_cnt;
+                            snapshot_cnt <= snapshot_cnt;
+                            guard_cnt    <= guard_cnt + 1'b1;
+                          end
+      default:            begin
+                            stable_cnt   <= 'b0;
+                            snapshot_cnt <= 'b0;
+                            guard_cnt    <= 'b0;
+                          end
+    endcase
+
+    case (acorr_next_state)
+      ACORR_STATE_CALC:   begin
+                            snapshot_valid <= 1'b1;
+                          end
+      default:            begin
+                            snapshot_valid <= 'b0;
+                          end
+    endcase
+
+    case (acorr_curr_state)
+      ACORR_STATE_STABLE: begin
+                            accum_rst_buf    <= 1'b1;
+                            fifo_cdc_rst_buf <= 1'b1;
+                          end
+      default:            begin
+                            accum_rst_buf    <= 'b0;
+                            fifo_cdc_rst_buf <= 'b0;
+                          end
+    endcase
+  end
+end
+
+
+////////////////////////////////////////////////////////////////////////////////
+//////////////////////////// Data Buffering Control ////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+
+// <--------------------------------------------------------------------------->
+// <--------------- store current hop & restore last hop weight --------------->
+// <--------------------------------------------------------------------------->
+reg sync_hop_flag_d = 'b0; // wait for ram data
+reg hop_flag_in_d   = 'b0; // wait for ram data
+reg curr_weight_valid = 'b0;
+reg [CH_NUM*WEIGHT_WIDTH-1 : 0] curr_weight_real = 'b0;
+reg [CH_NUM*WEIGHT_WIDTH-1 : 0] curr_weight_imag = 'b0;
+reg last_weight_valid = 'b0;
+reg [CH_NUM*WEIGHT_WIDTH-1 : 0] last_weight_real = 'b0;
+reg [CH_NUM*WEIGHT_WIDTH-1 : 0] last_weight_imag = 'b0;
+
+always @(posedge clk) begin
+  if (rst) begin
+    sync_hop_flag_d   <= 'b0;
+    hop_flag_in_d     <= 'b0;
+
+    curr_weight_valid <= 'b0;
+    curr_weight_real  <= 'b0;
+    curr_weight_imag  <= 'b0;
+
+    last_weight_valid <= 'b0;
+    last_weight_real  <= 'b0;
+    last_weight_imag  <= 'b0;
+  end
+  else if (lcmv_en) begin
+    // If lcmv is enabled
+
+    // Delay 1 clock cycle for adc data read
+    sync_hop_flag_d <= sync_hop_flag;
+    hop_flag_in_d   <= hop_flag_in;
+
+    curr_weight_valid <= (weight_dout_valid) ? 1'b1 : 'b0;
+    curr_weight_real  <= (weight_dout_valid) ? weight_dout_real : curr_weight_real;
+    curr_weight_imag  <= (weight_dout_valid) ? weight_dout_imag : curr_weight_imag;
+
+    if ((sync_flag && sync_hop_flag_d) || (~sync_flag && hop_flag_in_d)) begin
+      last_weight_valid <= 1'b1;
+      last_weight_real  <= curr_weight_real;
+      last_weight_imag  <= curr_weight_imag;
+    end
+    else begin
+      last_weight_valid <= last_weight_valid;
+      last_weight_real  <= last_weight_real;
+      last_weight_imag  <= last_weight_imag;
+    end
+
+  end
+  else begin
+    sync_hop_flag_d   <= 'b0;
+    hop_flag_in_d     <= 'b0;
+
+    curr_weight_valid <= 'b0;
+    curr_weight_real  <= 'b0;
+    curr_weight_imag  <= 'b0;
+
+    last_weight_valid <= 'b0;
+    last_weight_real  <= 'b0;
+    last_weight_imag  <= 'b0;
+  end
+end
+
+// <--------------------------------------------------------------------------->
+// <---------------- store current hop & restore last hop data ---------------->
+// <--------------------------------------------------------------------------->
+// address counter
+reg [$clog2(RAM_HOP_DEPTH)-1 : 0] hop_data_cnt = 'b0;
+
+always @(posedge clk) begin
+  if (rst) begin
+    hop_data_cnt <= 'b0;
+  end
+  else if(adc_din_valid && lcmv_en && ~sync_flag) begin
+    // if adc data is valid & lcmv is enabled & during data segment
+    if (hop_flag_in) begin
+      hop_data_cnt <= 'b0;
+    end
+    else begin
+      hop_data_cnt <= (hop_data_cnt == RAM_HOP_DEPTH-1) ? 'b0 : hop_data_cnt + 1'b1;
+    end
+  end
+  else begin
+      hop_data_cnt <= 'b0;
+  end
+end
+
+// data interface
+wire [CMPLX_DIM*CH_NUM*ADC_WIDTH-1 : 0] curr_hop_data;
+wire [CMPLX_DIM*CH_NUM*ADC_WIDTH-1 : 0] last_hop_data;
+reg last_hop_valid = 'b0;
+
+wire [CH_NUM*ADC_WIDTH-1 : 0] last_data_real;
+wire [CH_NUM*ADC_WIDTH-1 : 0] last_data_imag;
+
+assign curr_hop_data = {adc_din_imag,adc_din_real};
+assign {last_data_imag,last_data_real} = last_hop_data;
+
+always @(posedge clk) begin
+  if (rst) begin
+    last_hop_valid <= 'b0;
+  end
+  else if(adc_din_valid && lcmv_en && ~sync_flag) begin
+    // if adc data is valid & lcmv is enabled & during data segment
+    last_hop_valid <= adc_din_valid;
+  end
+  else begin
+    last_hop_valid <= 'b0;
+  end
+end
+
+ram_hop_data u_ram_hop_data
+(
+  .clka (clk            ), // input wire clka
+  .wea  (adc_din_valid  ), // input wire [0 : 0] wea
+  .addra(hop_data_cnt   ), // input wire [13 : 0] addra
+  .dina (curr_hop_data  ), // input wire [95 : 0] dina
+  .douta(last_hop_data  )  // output wire [95 : 0] douta
+);
+
+// <--------------------------------------------------------------------------->
+// <----------------- hop flag buffering when lcmv is enabled ----------------->
+// <--------------------------------------------------------------------------->
+reg [$clog2(LCMV_DELAY)-1 : 0] lcmv_hop_cnt_1 = 'b0;
+reg [$clog2(LCMV_DELAY)-1 : 0] lcmv_hop_cnt_2 = 'b0;
+
+always @(posedge clk) begin
+  if (rst) begin
+    lcmv_hop_cnt_1 <= 'b0;
+    lcmv_hop_cnt_2 <= 'b0;
+  end
+  else if (lcmv_en && ~sync_flag) begin
+    if (hop_flag_in) begin
+      if (lcmv_hop_cnt_1 == 'b0 && lcmv_hop_cnt_2 == 'b0) begin
+        lcmv_hop_cnt_1 <= 1'b1;
+        lcmv_hop_cnt_2 <= 'b0;
+      end
+      else if (lcmv_hop_cnt_1 != 'b0 && lcmv_hop_cnt_2 == 'b0) begin
+        lcmv_hop_cnt_1 <= (lcmv_hop_cnt_1 == LCMV_DELAY-1) ? 'b0 : lcmv_hop_cnt_1 + 1'b1;
+        lcmv_hop_cnt_2 <= 1'b1;
+      end
+      else if (lcmv_hop_cnt_1 == 'b0 && lcmv_hop_cnt_2 != 'b0) begin
+        lcmv_hop_cnt_1 <= 1'b1;
+        lcmv_hop_cnt_2 <= (lcmv_hop_cnt_2 == LCMV_DELAY-1) ? 'b0 : lcmv_hop_cnt_2 + 1'b1;
+      end
+      else begin
+        lcmv_hop_cnt_1 <= (lcmv_hop_cnt_1 == LCMV_DELAY-1) ? 'b0 : lcmv_hop_cnt_1 + 1'b1;
+        lcmv_hop_cnt_2 <= (lcmv_hop_cnt_2 == LCMV_DELAY-1) ? 'b0 : lcmv_hop_cnt_2 + 1'b1;
+      end
+    end
+    else begin
+      // behaviour of [lcmv_hop_cnt_1] when [hop_flag_in] does not assert
+      if (lcmv_hop_cnt_1 != 'b0) begin
+        lcmv_hop_cnt_1 <= (lcmv_hop_cnt_1 == LCMV_DELAY-1) ? 'b0 : lcmv_hop_cnt_1 + 1'b1;
+      end
+      else begin
+        lcmv_hop_cnt_1 <= 'b0;
+      end
+      // behaviour of [lcmv_hop_cnt_2] when [hop_flag_in] does not assert
+      if (lcmv_hop_cnt_2 != 'b0) begin
+        lcmv_hop_cnt_2 <= (lcmv_hop_cnt_2 == LCMV_DELAY-1) ? 'b0 : lcmv_hop_cnt_2 + 1'b1;
+      end
+      else begin
+        lcmv_hop_cnt_2 <= 'b0;
+      end
+
+    end
+  end
+  else begin
+    lcmv_hop_cnt_1 <= 'b0;
+    lcmv_hop_cnt_2 <= 'b0;
+  end
+end
+
+// <--------------------------------------------------------------------------->
+// <----------------- hop flag buffering when das is enabled ------------------>
+// <--------------------------------------------------------------------------->
+reg [$clog2(DAS_DELAY)-1 : 0] das_hop_cnt = 'b0;
+
+always @(posedge clk) begin
+  if (rst) begin
+    das_hop_cnt <= 'b0;
+  end
+  else if (~lcmv_en && ~sync_flag) begin
+    if (hop_flag_in) begin
+      das_hop_cnt <= 1'b1;
+    end
+    else if (das_hop_cnt != 0) begin
+      das_hop_cnt <= (das_hop_cnt == DAS_DELAY-1) ? 'b0 : das_hop_cnt + 1'b1;
+    end
+    else begin
+      das_hop_cnt <= 'b0;
+    end
+  end
+  else begin
+    das_hop_cnt <= 'b0;
+  end
+end
+
+reg hop_flag_out_buf = 'b0;
+
+assign hop_flag_out = hop_flag_out_buf;
+
+always @(posedge clk) begin
+  if (rst) begin
+    hop_flag_out_buf <= 'b0;
+  end
+  else if (lcmv_hop_cnt_1 == LCMV_DELAY-1 || lcmv_hop_cnt_2 == LCMV_DELAY-1 || das_hop_cnt == DAS_DELAY-1) begin
+    hop_flag_out_buf <= 1'b1;
+  end
+  else begin
+    hop_flag_out_buf <= 'b0;
+  end
+end
+
+
+////////////////////////////////////////////////////////////////////////////////
+//////////////////////////////// Delay and Sum /////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+wire das_valid;
+wire [DAS_WIDTH-1 : 0] das_real;
+wire [DAS_WIDTH-1 : 0] das_imag;
+
+wire [LCMV_WIDTH-1 : 0] das_real_ext;
+wire [LCMV_WIDTH-1 : 0] das_imag_ext;
+
+assign das_real_ext = {das_real,{(LCMV_WIDTH-DAS_WIDTH){1'b0}}};
+assign das_imag_ext = {das_imag,{(LCMV_WIDTH-DAS_WIDTH){1'b0}}};
+
+adder_tree_ppl #(
+  .DATA_I_WIDTH (ADC_WIDTH      ),
+  .DATA_NUM     (CH_NUM         )
+) u_das_add_ppl_real (
+  // clock & reset
+  .clk          (clk            ),
+  .rst          (rst            ),
+
+  // input data
+  .din_valid    (adc_din_valid  ),
+  .din_data     (adc_din_real   ),
+
+  // output data
+  .dout_valid   (das_valid      ),
+  .dout_data    (das_real       )
+);
+
+adder_tree_ppl #(
+  .DATA_I_WIDTH (ADC_WIDTH      ),
+  .DATA_NUM     (CH_NUM         )
+) u_das_add_ppl_imag (
+  // clock & reset
+  .clk          (clk            ),
+  .rst          (rst            ),
+
+  // input data
+  .din_valid    (adc_din_valid  ),
+  .din_data     (adc_din_imag   ),
+
+  // output data
+  .dout_valid   (               ),
+  .dout_data    (das_imag       )
+);
+
+
+////////////////////////////////////////////////////////////////////////////////
+///////////////////////////// Output Data Control //////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+reg null_dout_valid_buf = 'b0;
+reg [OUTPUT_WIDTH-1 : 0] null_dout_real_buf = 'b0;
+reg [OUTPUT_WIDTH-1 : 0] null_dout_imag_buf = 'b0;
+
+assign null_dout_valid = null_dout_valid_buf;
+assign null_dout_real  = null_dout_real_buf ;
+assign null_dout_imag  = null_dout_imag_buf ;
+
+if (OUTPUT_WIDTH <= LCMV_WIDTH) begin
+  // truncate msb
+  always @(posedge clk) begin
+    if (rst) begin
+      null_dout_valid_buf <= 'b0;
+      null_dout_real_buf  <= 'b0;
+      null_dout_imag_buf  <= 'b0;
+    end
+    else if (lcmv_en) begin
+      null_dout_valid_buf <= filter_dout_valid;
+      null_dout_real_buf  <= filter_dout_real[LCMV_WIDTH-1 -: OUTPUT_WIDTH];
+      null_dout_imag_buf  <= filter_dout_imag[LCMV_WIDTH-1 -: OUTPUT_WIDTH];
+    end
+    else begin
+      null_dout_valid_buf <= das_valid;
+      null_dout_real_buf  <= das_real_ext[LCMV_WIDTH-1 -: OUTPUT_WIDTH];
+      null_dout_imag_buf  <= das_imag_ext[LCMV_WIDTH-1 -: OUTPUT_WIDTH];
+    end
+  end
+end
+else begin // if (OUTPUT_WIDTH > LCMV_WIDTH)
+  // append zeros to fit output data width
+  always @(posedge clk) begin
+    if (rst) begin
+      null_dout_valid_buf <= 'b0;
+      null_dout_real_buf  <= 'b0;
+      null_dout_imag_buf  <= 'b0;
+    end
+    else if (lcmv_en) begin
+      null_dout_valid_buf <= filter_dout_valid;
+      null_dout_real_buf  <= {filter_dout_real,{(OUTPUT_WIDTH-LCMV_WIDTH){1'b0}}};
+      null_dout_imag_buf  <= {filter_dout_imag,{(OUTPUT_WIDTH-LCMV_WIDTH){1'b0}}};
+    end
+    else begin
+      null_dout_valid_buf <= das_valid;
+      null_dout_real_buf  <= {das_real_ext,{(OUTPUT_WIDTH-LCMV_WIDTH){1'b0}}};
+      null_dout_imag_buf  <= {das_imag_ext,{(OUTPUT_WIDTH-LCMV_WIDTH){1'b0}}};
+    end
+  end
+end
+
+
+////////////////////////////////////////////////////////////////////////////////
+///////////////////////////// Submodule Interface //////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+
+// ADC Input Data -> Autocorrelation
+assign acorr_din_valid = snapshot_valid;
+assign acorr_din_real = adc_din_real;
+assign acorr_din_imag = adc_din_imag;
+
+// Autocorrelation -> Accumulation
+assign accum_rst = accum_rst_buf;
+assign accum_din_valid = acorr_dout_valid;
+assign accum_din_real = acorr_dout_real;
+assign accum_din_imag = acorr_dout_imag;
+
+// Accumulation -> Parallel to Serial
+assign stream_fifo_rst = fifo_cdc_rst_buf;
+assign stream_din_valid = accum_dout_valid;
+assign stream_din_real = accum_dout_real;
+assign stream_din_imag = accum_dout_imag;
+
+// Serial to Parallel
+assign weight_fifo_rst = fifo_cdc_rst_buf;
+
+// Spatial Filter
+reg filter_weight_valid_buf = 'b0;
+reg [CH_NUM*WEIGHT_WIDTH-1 : 0] filter_weight_real_buf = 'b0;
+reg [CH_NUM*WEIGHT_WIDTH-1 : 0] filter_weight_imag_buf = 'b0;
+
+reg filter_din_valid_buf = 'b0;
+reg [CH_NUM*ADC_WIDTH-1 : 0] filter_din_real_buf = 'b0;
+reg [CH_NUM*ADC_WIDTH-1 : 0] filter_din_imag_buf = 'b0;
+
+assign filter_weight_valid = filter_weight_valid_buf;
+assign filter_weight_real  = filter_weight_real_buf ;
+assign filter_weight_imag  = filter_weight_imag_buf ;
+
+assign filter_din_valid = filter_din_valid_buf;
+assign filter_din_real  = filter_din_real_buf ;
+assign filter_din_imag  = filter_din_imag_buf ;
+
+always @(posedge clk) begin
+  if (rst) begin
+    filter_weight_valid_buf <= 'b0;
+    filter_weight_real_buf  <= 'b0;
+    filter_weight_imag_buf  <= 'b0;
+
+    filter_din_valid_buf    <= 'b0;
+    filter_din_real_buf     <= 'b0;
+    filter_din_imag_buf     <= 'b0;
+  end
+  else if (lcmv_en) begin
+    if (sync_flag) begin
+      filter_weight_valid_buf <= curr_weight_valid;
+      filter_weight_real_buf  <= curr_weight_real ;
+      filter_weight_imag_buf  <= curr_weight_imag ;
+
+      filter_din_valid_buf    <= adc_din_valid    ;
+      filter_din_real_buf     <= adc_din_real     ;
+      filter_din_imag_buf     <= adc_din_imag     ;
+    end
+    else begin
+      filter_weight_valid_buf <= last_weight_valid;
+      filter_weight_real_buf  <= last_weight_real ;
+      filter_weight_imag_buf  <= last_weight_imag ;
+
+      filter_din_valid_buf    <= last_hop_valid;
+      filter_din_real_buf     <= last_data_real ;
+      filter_din_imag_buf     <= last_data_imag ;
+    end
+  end
+  else begin
+    filter_weight_valid_buf <= 'b0;
+    filter_weight_real_buf  <= 'b0;
+    filter_weight_imag_buf  <= 'b0;
+
+    filter_din_valid_buf    <= 'b0;
+    filter_din_real_buf     <= 'b0;
+    filter_din_imag_buf     <= 'b0;
+  end
+end
+
+endmodule

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/phase_comp.v

@@ -0,0 +1,130 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 05/17/2023 03:30:04 PM
+// Design Name:
+// Module Name: phase_comp
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+//   Revision 0.01 - File Created
+//   20230713-1529 - 由于 Cordic IP 核会将输入信号进行缩放，为避免缩放后溢出，将
+//     Cordic 的输入改为至少两个符号位。
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module phase_comp
+#(
+    parameter DATA_WIDTH   = 12,
+    parameter CORDIC_WIDTH = 16,
+    parameter CH_NUM       = 4
+)
+(
+    // clock & reset
+    input clk                               ,
+    input rst                               ,
+
+    // input data
+    input din_valid                         ,
+    input [CH_NUM*CORDIC_WIDTH-1:0] phase   ,
+    input [CH_NUM*DATA_WIDTH-1:0] din_real  ,
+    input [CH_NUM*DATA_WIDTH-1:0] din_imag  ,
+
+    // output data
+    output dout_valid                       ,
+    output [CH_NUM*DATA_WIDTH-1:0] dout_real,
+    output [CH_NUM*DATA_WIDTH-1:0] dout_imag
+);
+
+genvar m;
+
+localparam AXIS_CORDIC_WIDTH = 8*((CORDIC_WIDTH-1)/8+1);
+
+// prepare cordic input data
+wire [AXIS_CORDIC_WIDTH-1:0] din_real_array [0:CH_NUM-1];
+wire [AXIS_CORDIC_WIDTH-1:0] din_imag_array [0:CH_NUM-1];
+wire [AXIS_CORDIC_WIDTH-1:0] phase_array [0:CH_NUM-1];
+
+for(m = 0; m < CH_NUM; m = m + 1) begin: array_convert
+    if (CORDIC_WIDTH > DATA_WIDTH+1) begin
+        // append zeros to fit cordic input with, sign-bit extension to fit 8 bit axis format, keep at least 2 sign-bits for cordic scaling
+        assign din_real_array[m] = {{(AXIS_CORDIC_WIDTH-CORDIC_WIDTH+1){din_real[(m+1)*DATA_WIDTH-1]}},din_real[m*DATA_WIDTH +: DATA_WIDTH],{(CORDIC_WIDTH-DATA_WIDTH-1){1'b0}}};
+        assign din_imag_array[m] = {{(AXIS_CORDIC_WIDTH-CORDIC_WIDTH+1){din_imag[(m+1)*DATA_WIDTH-1]}},din_imag[m*DATA_WIDTH +: DATA_WIDTH],{(CORDIC_WIDTH-DATA_WIDTH-1){1'b0}}};
+    end
+    else begin
+        // truncate msb, keep at least 2 sign-bits for cordic scaling
+        assign din_real_array[m] = {din_real[(m+1)*DATA_WIDTH-1],din_real[(m+1)*DATA_WIDTH-1 -: (AXIS_CORDIC_WIDTH-1)]};
+        assign din_imag_array[m] = {din_imag[(m+1)*DATA_WIDTH-1],din_imag[(m+1)*DATA_WIDTH-1 -: (AXIS_CORDIC_WIDTH-1)]};
+    end
+
+    if (AXIS_CORDIC_WIDTH > CORDIC_WIDTH) begin
+        // sign-bit extension to fit 8 bit axis format
+        assign phase_array[m] = {{(AXIS_CORDIC_WIDTH-CORDIC_WIDTH){phase[(m+1)*CORDIC_WIDTH-1]}},phase[m*CORDIC_WIDTH +: CORDIC_WIDTH]};
+    end
+    else begin
+        // truncate msb
+        assign phase_array[m] = phase[(m+1)*CORDIC_WIDTH-1 -: AXIS_CORDIC_WIDTH];
+    end
+end
+
+// output data & cordic interface
+wire [AXIS_CORDIC_WIDTH-1:0] rotate_real_array [0:CH_NUM-1];
+wire [AXIS_CORDIC_WIDTH-1:0] rotate_imag_array [0:CH_NUM-1];
+
+wire [DATA_WIDTH-1:0] dout_real_array [0:CH_NUM-1];
+wire [DATA_WIDTH-1:0] dout_imag_array [0:CH_NUM-1];
+
+for(m = 0; m < CH_NUM; m = m + 1) begin: cordic
+
+    wire        rotate_phase_valid;
+    wire [15:0] rotate_phase_data ;
+    wire        rotate_cart_valid ;
+    wire [31:0] rotate_cart_data  ;
+    wire        rotate_dout_valid ;
+    wire [31:0] rotate_dout_data  ;
+
+    assign rotate_phase_valid = din_valid;
+    assign rotate_phase_data = phase_array[m];
+    assign rotate_cart_valid = din_valid;
+    assign rotate_cart_data = {din_imag_array[m],din_real_array[m]};
+    assign {rotate_imag_array[m],rotate_real_array[m]} = rotate_dout_data;
+
+    if (DATA_WIDTH > AXIS_CORDIC_WIDTH) begin
+        // append zeros
+        assign dout_real_array[m] = {rotate_real_array[m],{(DATA_WIDTH-AXIS_CORDIC_WIDTH){1'b0}}};
+        assign dout_imag_array[m] = {rotate_imag_array[m],{(DATA_WIDTH-AXIS_CORDIC_WIDTH){1'b0}}};
+    end
+    else begin
+        // truncate msb
+        assign dout_real_array[m] = rotate_real_array[m][AXIS_CORDIC_WIDTH-1 -: DATA_WIDTH];
+        assign dout_imag_array[m] = rotate_imag_array[m][AXIS_CORDIC_WIDTH-1 -: DATA_WIDTH];
+    end
+
+    assign dout_real[m*DATA_WIDTH +: DATA_WIDTH] = dout_real_array[m];
+    assign dout_imag[m*DATA_WIDTH +: DATA_WIDTH] = dout_imag_array[m];
+
+    rotate_16b u_rotate_16b
+    (
+        .aclk                   (clk                ), // input wire aclk
+        .s_axis_phase_tvalid    (rotate_phase_valid ), // input wire s_axis_phase_tvalid
+        .s_axis_phase_tdata     (rotate_phase_data  ), // input wire [15 : 0] s_axis_phase_tdata
+        .s_axis_cartesian_tvalid(rotate_cart_valid  ), // input wire s_axis_cartesian_tvalid
+        .s_axis_cartesian_tdata (rotate_cart_data   ), // input wire [31 : 0] s_axis_cartesian_tdata
+        .m_axis_dout_tvalid     (rotate_dout_valid  ), // output wire m_axis_dout_tvalid
+        .m_axis_dout_tdata      (rotate_dout_data   )  // output wire [31 : 0] m_axis_dout_tdata
+    );
+
+    end
+
+assign dout_valid = cordic[0].rotate_dout_valid;
+
+endmodule

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/phase_compensate.v

@@ -0,0 +1,196 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 2023/05/16 02:00:43
+// Design Name:
+// Module Name: phase_compensate
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module phase_compensate(
+    input               clk                     ,
+    input               rst                     ,
+    input       [11:0]  vio_sin_0               ,
+    input       [11:0]  vio_sin_1               ,
+    input       [11:0]  vio_sin_2               ,
+    input       [11:0]  vio_sin_3               ,
+    input       [11:0]  vio_cos_0               ,
+    input       [11:0]  vio_cos_1               ,
+    input       [11:0]  vio_cos_2               ,
+    input       [11:0]  vio_cos_3               ,
+    input       [11:0]  din_i_0                 ,
+    input       [11:0]  din_i_1                 ,
+    input       [11:0]  din_i_2                 ,
+    input       [11:0]  din_i_3                 ,
+    input       [11:0]  din_q_0                 ,
+    input       [11:0]  din_q_1                 ,
+    input       [11:0]  din_q_2                 ,
+    input       [11:0]  din_q_3                 ,
+    input       [4:0]   vio_trunc               ,
+
+    output      [11:0]  dout_0_i                ,
+    output      [11:0]  dout_1_i                ,
+    output      [11:0]  dout_2_i                ,
+    output      [11:0]  dout_3_i                ,
+    output      [11:0]  dout_0_q                ,
+    output      [11:0]  dout_1_q                ,
+    output      [11:0]  dout_2_q                ,
+    output      [11:0]  dout_3_q                ,
+    output              trunc_overflow
+);
+
+    wire [63:0] dout_comp_0;
+    wire [63:0] dout_comp_1;
+    wire [63:0] dout_comp_2;
+    wire [63:0] dout_comp_3;
+    cmpy_12x12 cmpy_12x12_0 (
+    .aclk(clk),                              // input wire aclk
+    .s_axis_a_tvalid(1'd1),        // input wire s_axis_a_tvalid
+    .s_axis_a_tdata({{4{vio_sin_0[11]}},vio_sin_0[11:0],{4{vio_cos_0[11]}},vio_cos_0[11:0]}),          // input wire [31 : 0] s_axis_a_tdata
+    .s_axis_b_tvalid(1'd1),        // input wire s_axis_b_tvalid
+    .s_axis_b_tdata({{4{din_q_0[11]}},din_q_0[11:0],{4{din_i_0[11]}},din_i_0[11:0]}),          // input wire [31 : 0] s_axis_b_tdata
+    .m_axis_dout_tvalid(),  // output wire m_axis_dout_tvalid
+    .m_axis_dout_tdata(dout_comp_0)    // output wire [63 : 0] m_axis_dout_tdata
+    );
+
+    cmpy_12x12 cmpy_12x12_1 (
+    .aclk(clk),                              // input wire aclk
+    .s_axis_a_tvalid(1'd1),        // input wire s_axis_a_tvalid
+    .s_axis_a_tdata({{4{vio_sin_1[11]}},vio_sin_1[11:0],{4{vio_cos_1[11]}},vio_cos_1[11:0]}),          // input wire [31 : 0] s_axis_a_tdata
+    .s_axis_b_tvalid(1'd1),        // input wire s_axis_b_tvalid
+    .s_axis_b_tdata({{4{din_q_1[11]}},din_q_1[11:0],{4{din_i_1[11]}},din_i_1[11:0]}),          // input wire [31 : 0] s_axis_b_tdata
+    .m_axis_dout_tvalid(),  // output wire m_axis_dout_tvalid
+    .m_axis_dout_tdata(dout_comp_1)    // output wire [63 : 0] m_axis_dout_tdata
+    );
+
+    cmpy_12x12 cmpy_12x12_2 (
+    .aclk(clk),                              // input wire aclk
+    .s_axis_a_tvalid(1'd1),        // input wire s_axis_a_tvalid
+    .s_axis_a_tdata({{4{vio_sin_2[11]}},vio_sin_2[11:0],{4{vio_cos_2[11]}},vio_cos_2[11:0]}),          // input wire [31 : 0] s_axis_a_tdata
+    .s_axis_b_tvalid(1'd1),        // input wire s_axis_b_tvalid
+    .s_axis_b_tdata({{4{din_q_2[11]}},din_q_2[11:0],{4{din_i_2[11]}},din_i_2[11:0]}),          // input wire [31 : 0] s_axis_b_tdata
+    .m_axis_dout_tvalid(),  // output wire m_axis_dout_tvalid
+    .m_axis_dout_tdata(dout_comp_2)    // output wire [63 : 0] m_axis_dout_tdata
+    );
+
+    cmpy_12x12 cmpy_12x12_3 (
+    .aclk(clk),                              // input wire aclk
+    .s_axis_a_tvalid(1'd1),        // input wire s_axis_a_tvalid
+    .s_axis_a_tdata({{4{vio_sin_3[11]}},vio_sin_3[11:0],{4{vio_cos_3[11]}},vio_cos_3[11:0]}),          // input wire [31 : 0] s_axis_a_tdata
+    .s_axis_b_tvalid(1'd1),        // input wire s_axis_b_tvalid
+    .s_axis_b_tdata({{4{din_q_3[11]}},din_q_3[11:0],{4{din_i_3[11]}},din_i_3[11:0]}),          // input wire [31 : 0] s_axis_b_tdata
+    .m_axis_dout_tvalid(),  // output wire m_axis_dout_tvalid
+    .m_axis_dout_tdata(dout_comp_3)    // output wire [63 : 0] m_axis_dout_tdata
+    );
+    wire [11:0] dout_trunc_0i, dout_trunc_0q;
+    wire [11:0] dout_trunc_1i, dout_trunc_1q;
+    wire [11:0] dout_trunc_2i, dout_trunc_2q;
+    wire [11:0] dout_trunc_3i, dout_trunc_3q;
+    wire [11:0] trunc_overflow_0i, trunc_overflow_0q;
+    wire [11:0] trunc_overflow_1i, trunc_overflow_1q;
+    wire [11:0] trunc_overflow_2i, trunc_overflow_2q;
+    wire [11:0] trunc_overflow_3i, trunc_overflow_3q;
+    trunc_32bit_to_12bit trunc_32bit_to_12bit_0i(
+    .clk(clk),
+    .rst(rst),
+    .trunc_32bit_in({{7{dout_comp_0[24]}},dout_comp_0[24:0]}),
+    .vio_trunc(vio_trunc),
+
+    .trunc_12bit_out(dout_trunc_0i),
+    .trunc_overflow(trunc_overflow_0i)
+    );
+
+    trunc_32bit_to_12bit trunc_32bit_to_12bit_0q(
+    .clk(clk),
+    .rst(rst),
+    .trunc_32bit_in({{7{dout_comp_0[56]}},dout_comp_0[56:32]}),
+    .vio_trunc(vio_trunc),
+
+    .trunc_12bit_out(dout_trunc_0q),
+    .trunc_overflow(trunc_overflow_0q)
+    );
+
+    trunc_32bit_to_12bit trunc_32bit_to_12bit_1i(
+    .clk(clk),
+    .rst(rst),
+    .trunc_32bit_in({{7{dout_comp_1[24]}},dout_comp_1[24:0]}),
+    .vio_trunc(vio_trunc),
+
+    .trunc_12bit_out(dout_trunc_1i),
+    .trunc_overflow(trunc_overflow_1i)
+    );
+
+    trunc_32bit_to_12bit trunc_32bit_to_12bit_1q(
+    .clk(clk),
+    .rst(rst),
+    .trunc_32bit_in({{7{dout_comp_1[56]}},dout_comp_1[56:32]}),
+    .vio_trunc(vio_trunc),
+
+    .trunc_12bit_out(dout_trunc_1q),
+    .trunc_overflow(trunc_overflow_1q)
+    );
+
+    trunc_32bit_to_12bit trunc_32bit_to_12bit_2i(
+    .clk(clk),
+    .rst(rst),
+    .trunc_32bit_in({{7{dout_comp_2[24]}},dout_comp_2[24:0]}),
+    .vio_trunc(vio_trunc),
+
+    .trunc_12bit_out(dout_trunc_2i),
+    .trunc_overflow(trunc_overflow_2i)
+    );
+
+    trunc_32bit_to_12bit trunc_32bit_to_12bit_2q(
+    .clk(clk),
+    .rst(rst),
+    .trunc_32bit_in({{7{dout_comp_2[56]}},dout_comp_2[56:32]}),
+    .vio_trunc(vio_trunc),
+
+    .trunc_12bit_out(dout_trunc_2q),
+    .trunc_overflow(trunc_overflow_2q)
+    );
+
+    trunc_32bit_to_12bit trunc_32bit_to_12bit_3i(
+    .clk(clk),
+    .rst(rst),
+    .trunc_32bit_in({{7{dout_comp_3[24]}},dout_comp_3[24:0]}),
+    .vio_trunc(vio_trunc),
+
+    .trunc_12bit_out(dout_trunc_3i),
+    .trunc_overflow(trunc_overflow_3i)
+    );
+
+    trunc_32bit_to_12bit trunc_32bit_to_12bit_3q(
+    .clk(clk),
+    .rst(rst),
+    .trunc_32bit_in({{7{dout_comp_3[56]}},dout_comp_3[56:32]}),
+    .vio_trunc(vio_trunc),
+
+    .trunc_12bit_out(dout_trunc_3q),
+    .trunc_overflow(trunc_overflow_3q)
+    );
+
+    assign dout_0_i = dout_trunc_0i;
+    assign dout_1_i = dout_trunc_1i;
+    assign dout_2_i = dout_trunc_2i;
+    assign dout_3_i = dout_trunc_3i;
+    assign dout_0_q = dout_trunc_0q;
+    assign dout_1_q = dout_trunc_1q;
+    assign dout_2_q = dout_trunc_2q;
+    assign dout_3_q = dout_trunc_3q;
+
+    assign trunc_overflow = trunc_overflow_3q || trunc_overflow_2q || trunc_overflow_1q || trunc_overflow_0q || trunc_overflow_3i || trunc_overflow_2i || trunc_overflow_1i || trunc_overflow_0i;
+endmodule

vivado_pvt/projects/dl814_k7/dl814_k7_cal_coarse/dl814_k7_cal_coarse.srcs/sources_1/new/rx_pre_process/rx_pre_process.v

@@ -0,0 +1,573 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//      _           _        ____
+//     | | ___  ___| |__    / ___| __ _  ___
+//  _  | |/ _ \/ __| '_ \  | |  _ / _` |/ _ \
+// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
+//  \___/ \___/|___/_| |_|  \____|\__,_|\___/
+//
+// Create Date: 2022/10/30 18:09:20
+// Design Name:
+// Module Name: rx_pre_process
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description: Pre-process rx data, including ad9361 mcs & implementing nulling
+//     algorithm on rx data. The latency of autocorrelation is consisted of 2
+//     parts: 1. [STABLE_CNT_MOD] + [SNAPSHOT_NUM] + several intermediate delay
+//     of [sys_clk] clock cycles; 2. ([CH_NUM]*[CH_NUM]*[CMPLX_DIM] +
+//     1 frame head + 1 frame length)*[ACCUM_WIDTH] of [clk_96m] clock cycles.
+//     The simulation result shows delay of about 30us when [sys_clk] is 48m.
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+/*******************************************************************************
+  * Contents
+  * 01. AD9361 Rx Multi-Channel Calibration
+  * 02. Autocorrelation of Snapshot Vector
+  * 03. Accumulation of Snapshot Autocorrelation Matrices
+  * 04. 32-bit Matrix Element to 1-bit Stream Conversion
+  * 05. 1-bit Stream to 32-bit Vector Element Conversion
+  * 06. RF Synthesizer Control
+  * 07. Debug IO
+  * 08. DDR and Fixed-io (Do NOT Modify)
+*******************************************************************************/
+
+module rx_pre_process
+#(
+    parameter CAL_CNT_MOD       = 48  ,
+    parameter CAL_PEAK_POS      = 12  ,
+    parameter STABLE_CNT_MOD    = 96  ,
+    parameter ADC_WIDTH         = 12  ,
+    parameter CH_NUM            = 4   ,
+    parameter PHASE_WIDTH       = 16  ,
+    parameter SYNC_HOP_INTVL    = 48*1000, // 1 ms of 48M clock, must > 48*200
+    parameter SNAPSHOT_NUM      = 2048,
+    parameter PS_PL_WIDTH       = 32  ,
+    parameter WEIGHT_WIDTH      = 16  ,
+    parameter OUTPUT_WIDTH      = ADC_WIDTH,
+    parameter ACCOR_FRAME_HEAD  = 32'h7E7E7E7E,
+    parameter WEIGHT_FRAME_HEAD = ACCOR_FRAME_HEAD // Same head is required by [c2c_bridge] module
+)
+(
+    // clock & reset
+    input sys_clk                       , // sync to adc data
+    input sys_clk_phy                   , // sync to adc data
+    input sys_rst                       , // sync to [sys_clk]
+    input clk_96m                       , // sync to c2c data
+    input ant_rst                       , // sync to [clk_96m]
+
+    // input un-calibrated data
+    input [ADC_WIDTH-1:0] rx_ch1_i      ,
+    input [ADC_WIDTH-1:0] rx_ch1_q      ,
+    input [ADC_WIDTH-1:0] rx_ch2_i      ,
+    input [ADC_WIDTH-1:0] rx_ch2_q      ,
+    input [ADC_WIDTH-1:0] rx_ch3_i      ,
+    input [ADC_WIDTH-1:0] rx_ch3_q      ,
+    input [ADC_WIDTH-1:0] rx_ch4_i      ,
+    input [ADC_WIDTH-1:0] rx_ch4_q      ,
+
+    // input channel phase
+    input [PHASE_WIDTH-1:0] phase_ch1   , // sync to [sys_clk]
+    input [PHASE_WIDTH-1:0] phase_ch2   , // sync to [sys_clk]
+    input [PHASE_WIDTH-1:0] phase_ch3   , // sync to [sys_clk]
+    input [PHASE_WIDTH-1:0] phase_ch4   , // sync to [sys_clk]
+
+    // ad9361 calibration interface
+    input   ad9361_1_cal_start          ,
+    output  ad9361_1_cal_done           ,
+    input   ad9361_2_cal_start          ,
+    output  ad9361_2_cal_done           ,
+    output  ad9361_cal_result           ,
+    output  ad9361_cal_valid            ,
+    input   ad9361_recal                ,
+
+    // nulling algorithm interface
+    input hop_flag_in_phy               , // sync to [sys_clk_phy], hop flag that drives lcmv algorithm and hop data buffering
+    input sync_flag_phy                 , // sync to [sys_clk_phy], 1: sync segment; 0: guard/data segment
+    input lcmv_en_phy                   , // sync to [sys_clk_phy], 1: lcmv; 0: das (delay and sum)
+    output hop_flag_out                 , // sync to [sys_clk], hop flag that drives physical receiver
+
+    output accor_stream_valid           , // sync to [clk_96m]
+    output accor_stream_data            , // sync to [clk_96m]
+    input  weight_stream_data           , // sync to [clk_96m]
+    output rx_data_valid                , // sync to [sys_clk]
+    output [OUTPUT_WIDTH-1:0] rx_data_i , // sync to [sys_clk]
+    output [OUTPUT_WIDTH-1:0] rx_data_q   // sync to [sys_clk]
+);
+
+localparam CMPLX_DIM = 2;
+localparam ACORR_WIDTH = 2*ADC_WIDTH;
+localparam ACCUM_WIDTH = PS_PL_WIDTH;
+localparam LCMV_WIDTH = ADC_WIDTH + WEIGHT_WIDTH + $clog2(CH_NUM);
+
+////////////////////////////////////////////////////////////////////////////////
+///////////////////// AD9361 Rx Multi-Channel Calibration //////////////////////
+////////////////////////////////////////////////////////////////////////////////
+wire    [11:0]  rx_cal_ch1_i, rx_cal_ch1_q;
+wire    [11:0]  rx_cal_ch2_i, rx_cal_ch2_q;
+wire    [11:0]  rx_cal_ch3_i, rx_cal_ch3_q;
+wire    [11:0]  rx_cal_ch4_i, rx_cal_ch4_q;
+
+ad9361_phase_cal_coarse u_ad9361_phase_cal
+(
+    // clock & reset
+    .clk                (sys_clk           ), // input           clk
+    .rst                (sys_rst           ), // input           rst
+    // control interface
+    .ad9361_1_cal_start (ad9361_1_cal_start ), // input           ad9361_1_cal_start
+    .ad9361_1_cal_done  (ad9361_1_cal_done  ), // output          ad9361_1_cal_done
+    .ad9361_2_cal_start (ad9361_2_cal_start ), // input           ad9361_2_cal_start
+    .ad9361_2_cal_done  (ad9361_2_cal_done  ), // output          ad9361_2_cal_done
+    .ad9361_cal_result  (ad9361_cal_result  ), // output          ad9361_cal_result
+    .ad9361_cal_valid   (ad9361_cal_valid   ), // output          ad9361_cal_valid
+    .ad9361_recal       (ad9361_recal       ), // input           ad9361_recal
+    // input data interface
+    .rx_ch1_i           (rx_ch1_i           ), // input [ADC_WIDTH-1:0] rx_ch1_i
+    .rx_ch1_q           (rx_ch1_q           ), // input [ADC_WIDTH-1:0] rx_ch1_q
+    .rx_ch2_i           (rx_ch2_i           ), // input [ADC_WIDTH-1:0] rx_ch2_i
+    .rx_ch2_q           (rx_ch2_q           ), // input [ADC_WIDTH-1:0] rx_ch2_q
+    .rx_ch3_i           (rx_ch3_i           ), // input [ADC_WIDTH-1:0] rx_ch3_i
+    .rx_ch3_q           (rx_ch3_q           ), // input [ADC_WIDTH-1:0] rx_ch3_q
+    .rx_ch4_i           (rx_ch4_i           ), // input [ADC_WIDTH-1:0] rx_ch4_i
+    .rx_ch4_q           (rx_ch4_q           ), // input [ADC_WIDTH-1:0] rx_ch4_q
+    // output data interface
+    .rx_cal_ch1_i       (rx_cal_ch1_i       ), // output [ADC_WIDTH-1:0] rx_cal_ch1_i
+    .rx_cal_ch1_q       (rx_cal_ch1_q       ), // output [ADC_WIDTH-1:0] rx_cal_ch1_q
+    .rx_cal_ch2_i       (rx_cal_ch2_i       ), // output [ADC_WIDTH-1:0] rx_cal_ch2_i
+    .rx_cal_ch2_q       (rx_cal_ch2_q       ), // output [ADC_WIDTH-1:0] rx_cal_ch2_q
+    .rx_cal_ch3_i       (rx_cal_ch3_i       ), // output [ADC_WIDTH-1:0] rx_cal_ch3_i
+    .rx_cal_ch3_q       (rx_cal_ch3_q       ), // output [ADC_WIDTH-1:0] rx_cal_ch3_q
+    .rx_cal_ch4_i       (rx_cal_ch4_i       ), // output [ADC_WIDTH-1:0] rx_cal_ch4_i
+    .rx_cal_ch4_q       (rx_cal_ch4_q       )  // output [ADC_WIDTH-1:0] rx_cal_ch4_q
+);
+
+
+////////////////////////////////////////////////////////////////////////////////
+////////////////////////////// Phase Compensation //////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+// input data
+wire phase_comp_din_valid;
+wire [CH_NUM*PHASE_WIDTH-1 : 0] phase_comp_phase;
+wire [CH_NUM*ADC_WIDTH-1 : 0] phase_comp_din_real;
+wire [CH_NUM*ADC_WIDTH-1 : 0] phase_comp_din_imag;
+
+assign phase_comp_din_valid = ad9361_cal_valid;
+assign phase_comp_phase = {phase_ch4, phase_ch3, phase_ch2, phase_ch1};
+assign phase_comp_din_real = {rx_cal_ch4_i, rx_cal_ch3_i, rx_cal_ch2_i, rx_cal_ch1_i};
+assign phase_comp_din_imag = {rx_cal_ch4_q, rx_cal_ch3_q, rx_cal_ch2_q, rx_cal_ch1_q};
+
+// output data
+(*dont_touch = "true"*) wire [11:0] rx_comp_ch1_i;
+(*dont_touch = "true"*) wire [11:0] rx_comp_ch1_q;
+(*dont_touch = "true"*) wire [11:0] rx_comp_ch2_i;
+(*dont_touch = "true"*) wire [11:0] rx_comp_ch2_q;
+(*dont_touch = "true"*) wire [11:0] rx_comp_ch3_i;
+(*dont_touch = "true"*) wire [11:0] rx_comp_ch3_q;
+(*dont_touch = "true"*) wire [11:0] rx_comp_ch4_i;
+(*dont_touch = "true"*) wire [11:0] rx_comp_ch4_q;
+
+wire phase_comp_dout_valid;
+wire [CH_NUM*ADC_WIDTH-1:0] phase_comp_dout_real;
+wire [CH_NUM*ADC_WIDTH-1:0] phase_comp_dout_imag;
+
+// assign phase_comp_dout_valid = ad9361_cal_valid;
+assign {rx_comp_ch4_i, rx_comp_ch3_i, rx_comp_ch2_i, rx_comp_ch1_i} = phase_comp_dout_real;
+assign {rx_comp_ch4_q, rx_comp_ch3_q, rx_comp_ch2_q, rx_comp_ch1_q} = phase_comp_dout_imag;
+
+phase_comp #(
+    .DATA_WIDTH     (ADC_WIDTH          ),
+    .CORDIC_WIDTH   (PHASE_WIDTH        ),
+    .CH_NUM         (CH_NUM             )
+) u_phase_comp
+(
+    // clock & reset
+    .clk        (sys_clk                ),
+    .rst        (sys_rst                ),
+
+    // input data
+    .din_valid  (phase_comp_din_valid   ),
+    .phase      (phase_comp_phase       ),
+    .din_real   (phase_comp_din_real    ),
+    .din_imag   (phase_comp_din_imag    ),
+
+    // output data
+    .dout_valid (phase_comp_dout_valid  ),
+    .dout_real  (phase_comp_dout_real   ),
+    .dout_imag  (phase_comp_dout_imag   )
+);
+
+
+// (*dont_touch = "true"*) wire [11:0] vio_sin_0;
+// (*dont_touch = "true"*) wire [11:0] vio_sin_1;
+// (*dont_touch = "true"*) wire [11:0] vio_sin_2;
+// (*dont_touch = "true"*) wire [11:0] vio_sin_3;
+// (*dont_touch = "true"*) wire [11:0] vio_cos_0;
+// (*dont_touch = "true"*) wire [11:0] vio_cos_1;
+// (*dont_touch = "true"*) wire [11:0] vio_cos_2;
+// (*dont_touch = "true"*) wire [11:0] vio_cos_3;
+// (*dont_touch = "true"*) wire [ 4:0] vio_trunc;
+// (*dont_touch = "true"*) wire trunc_overflow;
+
+// phase_compensate u_phase_compensate
+// (
+//     .clk            (sys_clk        ),
+//     .rst            (sys_rst        ),
+
+//     .vio_sin_0      (vio_sin_0      ),
+//     .vio_sin_1      (vio_sin_1      ),
+//     .vio_sin_2      (vio_sin_2      ),
+//     .vio_sin_3      (vio_sin_3      ),
+//     .vio_cos_0      (vio_cos_0      ),
+//     .vio_cos_1      (vio_cos_1      ),
+//     .vio_cos_2      (vio_cos_2      ),
+//     .vio_cos_3      (vio_cos_3      ),
+
+//     .din_i_0        (rx_cal_ch1_i   ),
+//     .din_i_1        (rx_cal_ch2_i   ),
+//     .din_i_2        (rx_cal_ch3_i   ),
+//     .din_i_3        (rx_cal_ch4_i   ),
+//     .din_q_0        (rx_cal_ch1_q   ),
+//     .din_q_1        (rx_cal_ch2_q   ),
+//     .din_q_2        (rx_cal_ch3_q   ),
+//     .din_q_3        (rx_cal_ch4_q   ),
+//     .vio_trunc      (vio_trunc      ),
+
+//     .dout_0_i       (rx_comp_ch1_i  ),
+//     .dout_1_i       (rx_comp_ch2_i  ),
+//     .dout_2_i       (rx_comp_ch3_i  ),
+//     .dout_3_i       (rx_comp_ch4_i  ),
+//     .dout_0_q       (rx_comp_ch1_q  ),
+//     .dout_1_q       (rx_comp_ch2_q  ),
+//     .dout_2_q       (rx_comp_ch3_q  ),
+//     .dout_3_q       (rx_comp_ch4_q  ),
+//     .trunc_overflow (trunc_overflow )
+// );
+
+////////////////////////////////////////////////////////////////////////////////
+/////////////////////////////// Nulling Control ////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+// adc input
+wire adc_din_valid                        ;
+wire [CH_NUM*ADC_WIDTH-1 : 0] adc_din_real;
+wire [CH_NUM*ADC_WIDTH-1 : 0] adc_din_imag;
+
+assign adc_din_valid = phase_comp_dout_valid;
+assign adc_din_real  = phase_comp_dout_real ;
+assign adc_din_imag  = phase_comp_dout_imag ;
+
+// autocorrelation
+wire acorr_din_valid                        ;
+wire [CH_NUM*ADC_WIDTH-1 : 0] acorr_din_real;
+wire [CH_NUM*ADC_WIDTH-1 : 0] acorr_din_imag;
+
+wire acorr_dout_valid                               ;
+wire [CH_NUM*CH_NUM*ACORR_WIDTH-1:0] acorr_dout_real;
+wire [CH_NUM*CH_NUM*ACORR_WIDTH-1:0] acorr_dout_imag;
+
+// accumulation
+wire accum_rst                                     ;
+
+wire accum_din_valid                               ;
+wire [CH_NUM*CH_NUM*ACORR_WIDTH-1:0] accum_din_real;
+wire [CH_NUM*CH_NUM*ACORR_WIDTH-1:0] accum_din_imag;
+
+wire accum_dout_valid                               ;
+wire [CH_NUM*CH_NUM*ACCUM_WIDTH-1:0] accum_dout_real;
+wire [CH_NUM*CH_NUM*ACCUM_WIDTH-1:0] accum_dout_imag;
+
+// Parallel to Serial
+wire stream_fifo_rst                                  ;
+
+wire stream_din_valid                                 ;
+wire [CH_NUM*CH_NUM*ACCUM_WIDTH-1 : 0] stream_din_real;
+wire [CH_NUM*CH_NUM*ACCUM_WIDTH-1 : 0] stream_din_imag;
+
+// Serial to Parallel
+wire weight_fifo_rst                             ;
+
+wire weight_dout_valid                           ;
+wire [CH_NUM*WEIGHT_WIDTH-1 : 0] weight_dout_real;
+wire [CH_NUM*WEIGHT_WIDTH-1 : 0] weight_dout_imag;
+
+// spatial filter
+wire filter_weight_valid                           ;
+wire [CH_NUM*WEIGHT_WIDTH-1 : 0] filter_weight_real;
+wire [CH_NUM*WEIGHT_WIDTH-1 : 0] filter_weight_imag;
+
+wire filter_din_valid                        ;
+wire [CH_NUM*ADC_WIDTH-1 : 0] filter_din_real;
+wire [CH_NUM*ADC_WIDTH-1 : 0] filter_din_imag;
+
+wire filter_dout_valid                  ;
+wire [LCMV_WIDTH-1 : 0] filter_dout_real;
+wire [LCMV_WIDTH-1 : 0] filter_dout_imag;
+
+// output data port
+wire null_dout_valid                    ;
+wire [OUTPUT_WIDTH-1 : 0] null_dout_real;
+wire [OUTPUT_WIDTH-1 : 0] null_dout_imag;
+
+assign rx_data_valid = null_dout_valid;
+assign rx_data_i = null_dout_real;
+assign rx_data_q = null_dout_imag;
+
+null_ctrl #(
+    .ADC_WIDTH      (ADC_WIDTH      ),
+    .CH_NUM         (CH_NUM         ),
+    .STABLE_CNT_MOD (STABLE_CNT_MOD ),
+    .SYNC_HOP_INTVL (SYNC_HOP_INTVL ),
+    .SNAPSHOT_NUM   (SNAPSHOT_NUM   ),
+    .ACCUM_WIDTH    (ACCUM_WIDTH    ),
+    .ACORR_WIDTH    (ACORR_WIDTH    ),
+    .WEIGHT_WIDTH   (WEIGHT_WIDTH   ),
+    .OUTPUT_WIDTH   (OUTPUT_WIDTH   )
+) u_null_ctrl (
+    // *************************************************************************
+    // ***************************** clock & reset *****************************
+    // *************************************************************************
+    .clk                    (sys_clk                ), // input clk
+    .clk_phy                (sys_clk_phy            ), // input clk_phy
+    .rst                    (sys_rst                ), // input rst
+
+    //
+    .hop_flag_in_phy        (hop_flag_in_phy        ), // input hop_flag_in_phy
+    .sync_flag_phy          (sync_flag_phy          ), // input sync_flag_phy
+    .lcmv_en_phy            (lcmv_en_phy            ), // input lcmv_en_phy
+    .hop_flag_out           (hop_flag_out           ), // output hop_flag_out
+    // *************************************************************************
+    // **************************** ADC Input Data *****************************
+    // *************************************************************************
+    .adc_din_valid          (adc_din_valid          ), // input adc_din_valid
+    .adc_din_real           (adc_din_real           ), // input [CH_NUM*ADC_WIDTH-1 : 0] adc_din_real
+    .adc_din_imag           (adc_din_imag           ), // input [CH_NUM*ADC_WIDTH-1 : 0] adc_din_imag
+
+    // *************************************************************************
+    // **************************** Autocorrelation ****************************
+    // *************************************************************************
+    .acorr_din_valid        (acorr_din_valid        ), // output acorr_din_valid
+    .acorr_din_real         (acorr_din_real         ), // output [CH_NUM*ADC_WIDTH-1 : 0] acorr_din_real
+    .acorr_din_imag         (acorr_din_imag         ), // output [CH_NUM*ADC_WIDTH-1 : 0] acorr_din_imag
+
+    .acorr_dout_valid       (acorr_dout_valid       ), // input acorr_dout_valid
+    .acorr_dout_real        (acorr_dout_real        ), // input [CH_NUM*CH_NUM*ACORR_WIDTH-1:0] acorr_dout_real
+    .acorr_dout_imag        (acorr_dout_imag        ), // input [CH_NUM*CH_NUM*ACORR_WIDTH-1:0] acorr_dout_imag
+
+    // *************************************************************************
+    // **************************** Accumulation *******************************
+    // *************************************************************************
+    .accum_rst              (accum_rst              ), // output accum_rst
+
+    .accum_din_valid        (accum_din_valid        ), // output accum_din_valid
+    .accum_din_real         (accum_din_real         ), // output [CH_NUM*CH_NUM*ACORR_WIDTH-1:0] accum_din_real
+    .accum_din_imag         (accum_din_imag         ), // output [CH_NUM*CH_NUM*ACORR_WIDTH-1:0] accum_din_imag
+
+    .accum_dout_valid       (accum_dout_valid       ), // input accum_dout_valid
+    .accum_dout_real        (accum_dout_real        ), // input [CH_NUM*CH_NUM*ACCUM_WIDTH-1:0] accum_dout_real
+    .accum_dout_imag        (accum_dout_imag        ), // input [CH_NUM*CH_NUM*ACCUM_WIDTH-1:0] accum_dout_imag
+
+    // *************************************************************************
+    // ************************* Parallel to Serial ****************************
+    // *************************************************************************
+    .stream_fifo_rst        (stream_fifo_rst        ), // output stream_fifo_rst
+
+    .stream_din_valid       (stream_din_valid       ), // output stream_din_valid
+    .stream_din_real        (stream_din_real        ), // output [CH_NUM*CH_NUM*ACCUM_WIDTH-1 : 0] stream_din_real
+    .stream_din_imag        (stream_din_imag        ), // output [CH_NUM*CH_NUM*ACCUM_WIDTH-1 : 0] stream_din_imag
+
+    // *************************************************************************
+    // ************************* Serial to Parallel ****************************
+    // *************************************************************************
+    .weight_fifo_rst        (weight_fifo_rst        ), // output weight_fifo_rst
+
+    .weight_dout_valid      (weight_dout_valid      ), // input weight_dout_valid
+    .weight_dout_real       (weight_dout_real       ), // input [CH_NUM*WEIGHT_WIDTH-1 : 0] weight_dout_real
+    .weight_dout_imag       (weight_dout_imag       ), // input [CH_NUM*WEIGHT_WIDTH-1 : 0] weight_dout_imag
+
+    // *************************************************************************
+    // **************************** Spatial Filter *****************************
+    // *************************************************************************
+    // input weight vector
+    .filter_weight_valid    (filter_weight_valid    ), // output filter_weight_valid
+    .filter_weight_real     (filter_weight_real     ), // output [CH_NUM*WEIGHT_WIDTH-1 : 0] filter_weight_real
+    .filter_weight_imag     (filter_weight_imag     ), // output [CH_NUM*WEIGHT_WIDTH-1 : 0] filter_weight_imag
+
+    // input adc data
+    .filter_din_valid       (filter_din_valid       ), // output filter_din_valid
+    .filter_din_real        (filter_din_real        ), // output [CH_NUM*ADC_WIDTH-1 : 0] filter_din_real
+    .filter_din_imag        (filter_din_imag        ), // output [CH_NUM*ADC_WIDTH-1 : 0] filter_din_imag
+
+    // output data
+    .filter_dout_valid      (filter_dout_valid      ), // input filter_dout_valid
+    .filter_dout_real       (filter_dout_real       ), // input [LCMV_WIDTH-1 : 0] filter_dout_real
+    .filter_dout_imag       (filter_dout_imag       ), // input [LCMV_WIDTH-1 : 0] filter_dout_imag
+
+    // *************************************************************************
+    // *************************** Output Data Port ****************************
+    // *************************************************************************
+    .null_dout_valid        (null_dout_valid        ), // output null_dout_valid
+    .null_dout_real         (null_dout_real         ), // output [OUTPUT_WIDTH-1 : 0] null_dout_real
+    .null_dout_imag         (null_dout_imag         )  // output [OUTPUT_WIDTH-1 : 0] null_dout_imag
+);
+
+
+////////////////////////////////////////////////////////////////////////////////
+////////////////////// Autocorrelation of Snapshot Vector //////////////////////
+////////////////////////////////////////////////////////////////////////////////
+acorr_cmplx_col_vec #(
+    .DATA_I_WIDTH   (ADC_WIDTH      ),
+    .DATA_O_WIDTH   (ACORR_WIDTH    ),
+    .COL_NUM        (CH_NUM         )
+) u_acorr (
+    // clock & reset
+    .clk            (sys_clk            ),
+    .rst            (sys_rst            ),
+
+    // input data
+    .din_valid      (acorr_din_valid    ),
+    .din_real       (acorr_din_real     ),
+    .din_imag       (acorr_din_imag     ),
+
+    // output data
+    .dout_valid     (acorr_dout_valid   ),
+    .dout_real      (acorr_dout_real    ),
+    .dout_imag      (acorr_dout_imag    )
+);
+
+
+////////////////////////////////////////////////////////////////////////////////
+////////////// Accumulation of Snapshot Autocorrelation Matrices ///////////////
+////////////////////////////////////////////////////////////////////////////////
+accum_cmplx_mat #(
+    .ROW_NUM        (CH_NUM         ),
+    .COL_NUM        (CH_NUM         ),
+    .ACC_NUM        (SNAPSHOT_NUM   ),
+    .DATA_I_WIDTH   (ACORR_WIDTH    ),
+    .DATA_O_WIDTH   (PS_PL_WIDTH    )
+) u_accum_cmplx_mat
+(
+    // clock & reset
+    .clk        (sys_clk            ),
+    .rst        (sys_rst            ),
+    .acc_rst    (accum_rst          ), // [accum_rst] should assert before accumulation starts
+
+    // input data
+    .din_valid  (accum_din_valid    ),
+    .din_real   (accum_din_real     ),
+    .din_imag   (accum_din_imag     ),
+
+    // output data
+    .dout_valid (accum_dout_valid   ),
+    .dout_real  (accum_dout_real    ),
+    .dout_imag  (accum_dout_imag    )
+);
+
+
+////////////////////////////////////////////////////////////////////////////////
+/////////////// 32-bit Matrix Element to 1-bit Stream Conversion ///////////////
+////////////////////////////////////////////////////////////////////////////////
+// output data
+wire stream_dout_valid;
+wire stream_dout_data;
+
+assign accor_stream_valid = stream_dout_valid; // to module port
+assign accor_stream_data = stream_dout_data; // to module port
+
+accor_mat_formatting #(
+    .ROW_NUM        (CH_NUM             ),
+    .COL_NUM        (CH_NUM             ),
+    .DATA_I_WIDTH   (PS_PL_WIDTH        ),
+    .FRAME_HEAD     (ACCOR_FRAME_HEAD   )
+) u_accor_mat_stream
+(
+    // clock & reset
+    .sys_clk        (sys_clk            ),
+    .sys_rst        (sys_rst            ),
+    .clk_96m        (clk_96m            ),
+    .ant_rst        (ant_rst            ),
+
+    // input data, sync to [sys_clk]
+    .din_valid      (stream_din_valid   ),
+    .din_real       (stream_din_real    ),
+    .din_imag       (stream_din_imag    ),
+    .fifo_cdc_rst   (stream_fifo_rst    ),
+
+    // output data, sync to [clk_96m]
+    .dout_valid     (stream_dout_valid  ),
+    .dout_data      (stream_dout_data   )
+);
+
+
+////////////////////////////////////////////////////////////////////////////////
+/////////////// 1-bit Stream to 32-bit Vector Element Conversion ///////////////
+////////////////////////////////////////////////////////////////////////////////
+// input data
+wire weight_din_data;
+
+assign weight_din_data = weight_stream_data;
+
+weight_vec_formatting #(
+    .COL_NUM        (CH_NUM             ),
+    .WEIGHT_WIDTH   (PS_PL_WIDTH        ),
+    .DATA_O_WIDTH   (WEIGHT_WIDTH       ),
+    .FRAME_HEAD     (WEIGHT_FRAME_HEAD  )
+) u_weight_vec_formatting
+(
+    // clock & reset
+    .sys_clk        (sys_clk            ),
+    .sys_rst        (sys_rst            ),
+    .clk_96m        (clk_96m            ),
+    .ant_rst        (ant_rst            ),
+
+    // input data, sync to [clk_96m]
+    .din_data       (weight_din_data    ),
+
+    // sync to [sys_clk]
+    .fifo_cdc_rst   (weight_fifo_rst    ),
+
+    // output data, sync to [sys_clk]
+    .dout_valid     (weight_dout_valid  ),
+    .dout_real      (weight_dout_real   ),
+    .dout_imag      (weight_dout_imag   )
+);
+
+
+////////////////////////////////////////////////////////////////////////////////
+//////////////////////////////// Spatial Filter ////////////////////////////////
+////////////////////////////////////////////////////////////////////////////////
+spatial_filter #(
+    .CH_NUM         (CH_NUM         ),
+    .WEIGHT_WIDTH   (WEIGHT_WIDTH   ),
+    .ADC_WIDTH      (ADC_WIDTH      ),
+    .FILTER_O_WIDTH (OUTPUT_WIDTH   )
+) u_spatial_filter
+(
+    // clock & reset
+    .clk                (sys_clk            ),
+    .rst                (sys_rst            ),
+
+    // input weight vector
+    .din_weight_valid   (filter_weight_valid),
+    .din_weight_real    (filter_weight_real ),
+    .din_weight_imag    (filter_weight_imag ),
+
+    // input adc data
+    .din_adc_valid      (filter_din_valid   ),
+    .din_adc_real       (filter_din_real    ),
+    .din_adc_imag       (filter_din_imag    ),
+
+    // output data
+    .dout_valid         (filter_dout_valid  ),
+    .dout_real          (filter_dout_real   ),
+    .dout_imag          (filter_dout_imag   )
+);
+
+endmodule