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update adi_library to vivado 2024.1

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compile adi_library with latest hdl commit and vivado 2024.1
This commit is contained in:
josh
2024-06-06 11:22:50 +08:00
parent 3c6c573f6a
commit 24cc6b9ee9
695 changed files with 17906 additions and 9982 deletions
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adi_library/axi_ad7606x/axi_ad7606x.v
+122 -122
View File
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
@@ -37,142 +37,142 @@
module axi_ad7606x #(
parameter ID = 0,
parameter DEV_CONFIG = 0,
parameter ADC_CH_DW = 16,
parameter ADC_N_BITS = 16,
parameter EXTERNAL_CLK = 0
parameter ID = 0,
parameter DEV_CONFIG = 0,
parameter ADC_TO_DMA_N_BITS = 16,
parameter ADC_N_BITS = 16,
parameter EXTERNAL_CLK = 0
) (
// physical data interface
output rx_cs_n,
output [15:0] rx_db_o,
input [15:0] rx_db_i,
output rx_db_t,
output rx_rd_n,
output rx_wr_n,
input external_clk,
output rx_cs_n,
output [15:0] rx_db_o,
input [15:0] rx_db_i,
output rx_db_t,
output rx_rd_n,
output rx_wr_n,
input external_clk,
// physical control interface
input rx_busy,
input first_data,
input rx_busy,
input first_data,
// AXI Slave Memory Map
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [15:0] s_axi_awaddr,
input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [15:0] s_axi_araddr,
input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready,
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [15:0] s_axi_awaddr,
input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [15:0] s_axi_araddr,
input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready,
input adc_dovf,
output adc_clk,
input adc_dovf,
output adc_clk,
output adc_valid,
output [ADC_CH_DW-1:0] adc_data_0,
output [ADC_CH_DW-1:0] adc_data_1,
output [ADC_CH_DW-1:0] adc_data_2,
output [ADC_CH_DW-1:0] adc_data_3,
output [ADC_CH_DW-1:0] adc_data_4,
output [ADC_CH_DW-1:0] adc_data_5,
output [ADC_CH_DW-1:0] adc_data_6,
output [ADC_CH_DW-1:0] adc_data_7,
output adc_enable_0,
output adc_enable_1,
output adc_enable_2,
output adc_enable_3,
output adc_enable_4,
output adc_enable_5,
output adc_enable_6,
output adc_enable_7,
output adc_reset
output adc_valid,
output [ADC_TO_DMA_N_BITS-1:0] adc_data_0,
output [ADC_TO_DMA_N_BITS-1:0] adc_data_1,
output [ADC_TO_DMA_N_BITS-1:0] adc_data_2,
output [ADC_TO_DMA_N_BITS-1:0] adc_data_3,
output [ADC_TO_DMA_N_BITS-1:0] adc_data_4,
output [ADC_TO_DMA_N_BITS-1:0] adc_data_5,
output [ADC_TO_DMA_N_BITS-1:0] adc_data_6,
output [ADC_TO_DMA_N_BITS-1:0] adc_data_7,
output adc_enable_0,
output adc_enable_1,
output adc_enable_2,
output adc_enable_3,
output adc_enable_4,
output adc_enable_5,
output adc_enable_6,
output adc_enable_7,
output adc_reset
);
localparam [31:0] RD_RAW_CAP = 32'h2000;
localparam AD7606B = 1'b0;
localparam AD7606C_16 = 1'b1;
localparam [31:0] RD_RAW_CAP = 32'h2000;
localparam AD7606B = 1'b0;
localparam AD7606C_16 = 1'b1;
// internal registers
reg up_wack = 1'b0;
reg up_rack = 1'b0;
reg [31:0] up_rdata = 32'b0;
reg [31:0] up_rdata_r;
reg up_rack_r;
reg up_wack_r;
reg up_wack = 1'b0;
reg up_rack = 1'b0;
reg [31:0] up_rdata = 32'b0;
reg [31:0] up_rdata_r;
reg up_rack_r;
reg up_wack_r;
// internal signals
wire [ADC_N_BITS-1:0] adc_data_0_s;
wire [ADC_N_BITS-1:0] adc_data_1_s;
wire [ADC_N_BITS-1:0] adc_data_2_s;
wire [ADC_N_BITS-1:0] adc_data_3_s;
wire [ADC_N_BITS-1:0] adc_data_4_s;
wire [ADC_N_BITS-1:0] adc_data_5_s;
wire [ADC_N_BITS-1:0] adc_data_6_s;
wire [ADC_N_BITS-1:0] adc_data_7_s;
wire [(8*ADC_N_BITS)-1:0] adc_data_s;
wire [ 7:0] adc_status_header[0:7];
wire adc_status;
wire [15:0] adc_crc;
wire [15:0] adc_crc_res;
wire adc_crc_err;
wire adc_mode_en;
wire [ 7:0] adc_custom_control;
wire [ADC_N_BITS-1:0] adc_data_0_s;
wire [ADC_N_BITS-1:0] adc_data_1_s;
wire [ADC_N_BITS-1:0] adc_data_2_s;
wire [ADC_N_BITS-1:0] adc_data_3_s;
wire [ADC_N_BITS-1:0] adc_data_4_s;
wire [ADC_N_BITS-1:0] adc_data_5_s;
wire [ADC_N_BITS-1:0] adc_data_6_s;
wire [ADC_N_BITS-1:0] adc_data_7_s;
wire [(8*ADC_N_BITS)-1:0] adc_data_s;
wire [ 7:0] adc_status_header[0:7];
wire adc_status;
wire [15:0] adc_crc;
wire [15:0] adc_crc_res;
wire adc_crc_err;
wire adc_mode_en;
wire [ 7:0] adc_custom_control;
wire adc_dfmt_enable_s[0:7];
wire adc_dfmt_type_s[0:7];
wire adc_dfmt_se_s[0:7];
wire adc_dfmt_enable_s[0:7];
wire adc_dfmt_type_s[0:7];
wire adc_dfmt_se_s[0:7];
wire adc_clk_s;
wire [ 7:0] adc_enable;
wire adc_reset_s;
wire adc_clk_s;
wire [ 7:0] adc_enable;
wire adc_reset_s;
wire [(8*ADC_CH_DW)-1:0] dma_data;
wire dma_dvalid;
wire [(8*ADC_TO_DMA_N_BITS)-1:0] dma_data;
wire dma_dvalid;
wire up_clk;
wire up_rstn;
wire up_rreq_s;
wire [13:0] up_raddr_s;
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_rdata_s[0:8];
wire [8:0] up_rack_s;
wire [8:0] up_wack_s;
wire up_clk;
wire up_rstn;
wire up_rreq_s;
wire [13:0] up_raddr_s;
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_rdata_s[0:8];
wire [8:0] up_rack_s;
wire [8:0] up_wack_s;
wire up_wack_cntrl_s;
wire up_rack_cntrl_s;
wire [31:0] up_rdata_cntrl_s;
wire up_wack_cntrl_s;
wire up_rack_cntrl_s;
wire [31:0] up_rdata_cntrl_s;
wire [31:0] wr_data_s;
wire [15:0] rd_data_s;
wire rd_valid_s;
wire [31:0] adc_config_ctrl_s;
wire adc_ctrl_status_s;
wire m_axis_ready_s;
wire m_axis_valid_s;
wire [15:0] m_axis_data_s;
wire m_axis_xfer_req_s;
wire [31:0] wr_data_s;
wire [15:0] rd_data_s;
wire rd_valid_s;
wire [31:0] adc_config_ctrl_s;
wire adc_ctrl_status_s;
wire m_axis_ready_s;
wire m_axis_valid_s;
wire [15:0] m_axis_data_s;
wire m_axis_xfer_req_s;
// defaults
@@ -287,13 +287,13 @@ module axi_ad7606x #(
for (k = 0;k < 8;k = k + 1) begin
ad_datafmt #(
.DATA_WIDTH (ADC_N_BITS),
.BITS_PER_SAMPLE (ADC_CH_DW)
.BITS_PER_SAMPLE (ADC_TO_DMA_N_BITS)
) i_datafmt (
.clk (adc_clk),
.valid (1'b1),
.data (adc_data_s[k*ADC_N_BITS+(ADC_N_BITS-1):k*ADC_N_BITS]),
.valid_out (dma_dvalid),
.data_out (dma_data[k*ADC_CH_DW+(ADC_CH_DW-1):k*ADC_CH_DW]),
.data_out (dma_data[k*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):k*ADC_TO_DMA_N_BITS]),
.dfmt_enable (adc_dfmt_enable_s[k]),
.dfmt_type (adc_dfmt_type_s[k]),
.dfmt_se (adc_dfmt_se_s[k]));
@@ -385,14 +385,14 @@ module axi_ad7606x #(
endgenerate
assign adc_data_s = {adc_data_0_s,adc_data_1_s,adc_data_2_s,adc_data_3_s,adc_data_4_s,adc_data_5_s,adc_data_6_s,adc_data_7_s};
assign adc_data_7 = dma_data[0*ADC_CH_DW+(ADC_CH_DW-1):0*ADC_CH_DW];
assign adc_data_6 = dma_data[1*ADC_CH_DW+(ADC_CH_DW-1):1*ADC_CH_DW];
assign adc_data_5 = dma_data[2*ADC_CH_DW+(ADC_CH_DW-1):2*ADC_CH_DW];
assign adc_data_4 = dma_data[3*ADC_CH_DW+(ADC_CH_DW-1):3*ADC_CH_DW];
assign adc_data_3 = dma_data[4*ADC_CH_DW+(ADC_CH_DW-1):4*ADC_CH_DW];
assign adc_data_2 = dma_data[5*ADC_CH_DW+(ADC_CH_DW-1):5*ADC_CH_DW];
assign adc_data_1 = dma_data[6*ADC_CH_DW+(ADC_CH_DW-1):6*ADC_CH_DW];
assign adc_data_0 = dma_data[7*ADC_CH_DW+(ADC_CH_DW-1):7*ADC_CH_DW];
assign adc_data_7 = dma_data[0*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):0*ADC_TO_DMA_N_BITS];
assign adc_data_6 = dma_data[1*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):1*ADC_TO_DMA_N_BITS];
assign adc_data_5 = dma_data[2*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):2*ADC_TO_DMA_N_BITS];
assign adc_data_4 = dma_data[3*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):3*ADC_TO_DMA_N_BITS];
assign adc_data_3 = dma_data[4*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):4*ADC_TO_DMA_N_BITS];
assign adc_data_2 = dma_data[5*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):5*ADC_TO_DMA_N_BITS];
assign adc_data_1 = dma_data[6*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):6*ADC_TO_DMA_N_BITS];
assign adc_data_0 = dma_data[7*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):7*ADC_TO_DMA_N_BITS];
up_adc_common #(
.ID (ID),
adi_library/axi_ad7606x/axi_ad7606x.xpr
+13 -14
View File
@@ -1,13 +1,13 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
<!-- Product Version: Vivado v2024.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_ad7606x/axi_ad7606x.xpr">
<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_ad7606x/axi_ad7606x.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="f98c19d8f31b4047a3ade4396f117f50"/>
<Option Name="Id" Val="40df9cdf569447488e830fd95f23701b"/>
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
<Option Name="SimulatorVersionXsim" Val="2024.1"/>
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
<Option Name="SimulatorVersionRiviera" Val="2023.04"/>
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -271,21 +270,21 @@
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="21">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Runs Version="1" Minor="22">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
@@ -298,7 +297,7 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
adi_library/axi_ad7606x/axi_ad7606x_16b_pif.v
+1 -1
View File
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
adi_library/axi_ad7606x/axi_ad7606x_18b_pif.v
+1 -1
View File
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
adi_library/axi_ad7606x/component.xml
+25 -25
View File
@@ -301,7 +301,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>499fbfb9</spirit:value>
<spirit:value>a633c222</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -317,7 +317,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>b5e2e2ed</spirit:value>
<spirit:value>630b2c18</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -331,7 +331,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>c7c7b169</spirit:value>
<spirit:value>3717393a</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -861,7 +861,7 @@
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ADC_CH_DW&apos;)) - 1)">15</spirit:left>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ADC_TO_DMA_N_BITS&apos;)) - 1)">15</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
@@ -878,7 +878,7 @@
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ADC_CH_DW&apos;)) - 1)">15</spirit:left>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ADC_TO_DMA_N_BITS&apos;)) - 1)">15</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
@@ -895,7 +895,7 @@
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ADC_CH_DW&apos;)) - 1)">15</spirit:left>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ADC_TO_DMA_N_BITS&apos;)) - 1)">15</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
@@ -912,7 +912,7 @@
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ADC_CH_DW&apos;)) - 1)">15</spirit:left>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ADC_TO_DMA_N_BITS&apos;)) - 1)">15</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
@@ -929,7 +929,7 @@
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ADC_CH_DW&apos;)) - 1)">15</spirit:left>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ADC_TO_DMA_N_BITS&apos;)) - 1)">15</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
@@ -946,7 +946,7 @@
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ADC_CH_DW&apos;)) - 1)">15</spirit:left>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ADC_TO_DMA_N_BITS&apos;)) - 1)">15</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
@@ -963,7 +963,7 @@
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ADC_CH_DW&apos;)) - 1)">15</spirit:left>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ADC_TO_DMA_N_BITS&apos;)) - 1)">15</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
@@ -980,7 +980,7 @@
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ADC_CH_DW&apos;)) - 1)">15</spirit:left>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ADC_TO_DMA_N_BITS&apos;)) - 1)">15</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
@@ -1122,9 +1122,9 @@
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DEV_CONFIG">0</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>ADC_CH_DW</spirit:name>
<spirit:displayName>Adc Ch Dw</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ADC_CH_DW">16</spirit:value>
<spirit:name>ADC_TO_DMA_N_BITS</spirit:name>
<spirit:displayName>Adc To Dma N Bits</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ADC_TO_DMA_N_BITS">16</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>ADC_N_BITS</spirit:name>
@@ -1217,7 +1217,7 @@
<spirit:file>
<spirit:name>axi_ad7606x.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_461f9622</spirit:userFileType>
<spirit:userFileType>CHECKSUM_32b3b7fc</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
@@ -1276,7 +1276,7 @@
<spirit:file>
<spirit:name>xgui/axi_ad7606x_v1_0.tcl</spirit:name>
<spirit:fileType>tclSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_3f71ec0b</spirit:userFileType>
<spirit:userFileType>CHECKSUM_b9f13221</spirit:userFileType>
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
@@ -1294,9 +1294,9 @@
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_CONFIG" spirit:choiceRef="choice_pairs_5f95957e">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ADC_CH_DW</spirit:name>
<spirit:displayName>Adc Ch Dw</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ADC_CH_DW">16</spirit:value>
<spirit:name>ADC_TO_DMA_N_BITS</spirit:name>
<spirit:displayName>Adc To Dma N Bits</spirit:displayName>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ADC_TO_DMA_N_BITS">16</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>ADC_N_BITS</spirit:name>
@@ -1351,14 +1351,14 @@
<xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
<xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/axi_ad7606x</xilinx:vendorURL>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2024-01-14T03:38:47Z</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>2024-06-06T02:54:24Z</xilinx:coreCreationDateTime>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="d8c51c8e"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="ca30ecb6"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="e88a6568"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="5ea7cf2e"/>
<xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="ee06b4eb"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="52e2ee87"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="8453a226"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="2909d2ed"/>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
</spirit:component>
adi_library/axi_ad7606x/xgui/axi_ad7606x_v1_0.tcl
+11 -11
View File
@@ -10,15 +10,6 @@ proc init_gui { IPINST } {
}
proc update_PARAM_VALUE.ADC_CH_DW { PARAM_VALUE.ADC_CH_DW } {
# Procedure called to update ADC_CH_DW when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.ADC_CH_DW { PARAM_VALUE.ADC_CH_DW } {
# Procedure called to validate ADC_CH_DW
return true
}
proc update_PARAM_VALUE.ADC_N_BITS { PARAM_VALUE.ADC_N_BITS } {
# Procedure called to update ADC_N_BITS when any of the dependent parameters in the arguments change
}
@@ -28,6 +19,15 @@ proc validate_PARAM_VALUE.ADC_N_BITS { PARAM_VALUE.ADC_N_BITS } {
return true
}
proc update_PARAM_VALUE.ADC_TO_DMA_N_BITS { PARAM_VALUE.ADC_TO_DMA_N_BITS } {
# Procedure called to update ADC_TO_DMA_N_BITS when any of the dependent parameters in the arguments change
}
proc validate_PARAM_VALUE.ADC_TO_DMA_N_BITS { PARAM_VALUE.ADC_TO_DMA_N_BITS } {
# Procedure called to validate ADC_TO_DMA_N_BITS
return true
}
proc update_PARAM_VALUE.DEV_CONFIG { PARAM_VALUE.DEV_CONFIG } {
# Procedure called to update DEV_CONFIG when any of the dependent parameters in the arguments change
}
@@ -66,9 +66,9 @@ proc update_MODELPARAM_VALUE.DEV_CONFIG { MODELPARAM_VALUE.DEV_CONFIG PARAM_VALU
set_property value [get_property value ${PARAM_VALUE.DEV_CONFIG}] ${MODELPARAM_VALUE.DEV_CONFIG}
}
proc update_MODELPARAM_VALUE.ADC_CH_DW { MODELPARAM_VALUE.ADC_CH_DW PARAM_VALUE.ADC_CH_DW } {
proc update_MODELPARAM_VALUE.ADC_TO_DMA_N_BITS { MODELPARAM_VALUE.ADC_TO_DMA_N_BITS PARAM_VALUE.ADC_TO_DMA_N_BITS } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.ADC_CH_DW}] ${MODELPARAM_VALUE.ADC_CH_DW}
set_property value [get_property value ${PARAM_VALUE.ADC_TO_DMA_N_BITS}] ${MODELPARAM_VALUE.ADC_TO_DMA_N_BITS}
}
proc update_MODELPARAM_VALUE.ADC_N_BITS { MODELPARAM_VALUE.ADC_N_BITS PARAM_VALUE.ADC_N_BITS } {