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update adi_library to vivado 2024.1

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compile adi_library with latest hdl commit and vivado 2024.1
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josh
2024-06-06 11:22:50 +08:00
parent 3c6c573f6a
commit 24cc6b9ee9
695 changed files with 17906 additions and 9982 deletions
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adi_library/axi_ad7616/component.xml
+6 -6
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@@ -241,7 +241,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>c191877d</spirit:value>
<spirit:value>a15f1752</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -257,7 +257,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>c191877d</spirit:value>
<spirit:value>a15f1752</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -798,7 +798,7 @@
<spirit:file>
<spirit:name>axi_ad7616.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_2739560c</spirit:userFileType>
<spirit:userFileType>CHECKSUM_b233ad5c</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
@@ -880,11 +880,11 @@
<xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
<xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/axi_ad7616</xilinx:vendorURL>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2024-01-14T03:38:56Z</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>2024-06-06T02:54:34Z</xilinx:coreCreationDateTime>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="ac532484"/>
<xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="ed2489c8"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="6614b440"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="3313f287"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="1d0290c9"/>