update adi_library to vivado 2024.1

compile adi_library with latest hdl commit and vivado 2024.1

adi_library/axi_ad9963/axi_ad9963_if.v

@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
@@ -228,8 +228,8 @@ module axi_ad9963_if #(
     .R (dac_rst),
     .S (1'b0),
     .C (dac_clk),
-    .D1 (tx_data_p[l_inst]),
-    .D2 (tx_data_n[l_inst]),
+    .D1 (tx_data_n[l_inst]),
+    .D2 (tx_data_p[l_inst]),
     .Q (tx_data[l_inst]));
     end
   endgenerate
@@ -243,8 +243,8 @@ module axi_ad9963_if #(
     .R (dac_rst),
     .S (1'b0),
     .C (dac_clk),
-    .D1 (1'b1),
-    .D2 (1'b0),
+    .D1 (1'b0),
+    .D2 (1'b1),
     .Q (tx_iq));
 
 endmodule