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update adi_library to vivado 2024.1

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compile adi_library with latest hdl commit and vivado 2024.1
This commit is contained in:
josh
2024-06-06 11:22:50 +08:00
parent 3c6c573f6a
commit 24cc6b9ee9
695 changed files with 17906 additions and 9982 deletions
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adi_library/axi_clock_monitor/axi_clock_monitor.v
+25 -32
View File
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
@@ -112,11 +112,9 @@ module axi_clock_monitor #(
wire clock [0:15];
wire [20:0] clk_mon_count [0:15];
wire up_wreq_i_s;
wire [13:0] up_waddr_i_s;
wire [31:0] up_wdata_i_s;
wire up_wack_o_s;
wire up_rreq_i_s;
wire [13:0] up_raddr_i_s;
wire [31:0] up_rdata_o_s;
wire up_rack_o_s;
@@ -148,11 +146,6 @@ module axi_clock_monitor #(
assign up_rstn = s_axi_aresetn;
assign reset = up_reset_core;
// decode block select
assign up_wreq_s = (up_waddr_i_s[13:8] == ID) ? up_wreq_i_s : 1'b0;
assign up_rreq_s = (up_raddr_i_s[13:8] == ID) ? up_rreq_i_s : 1'b0;
// processor write interface
assign up_wack_o_s = up_wack_int;
@@ -184,32 +177,32 @@ module axi_clock_monitor #(
end else begin
up_rack_int <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr_i_s)
case (up_raddr_i_s[4:0])
/* Standard registers */
14'h000: up_rdata_int <= PCORE_VERSION;
14'h001: up_rdata_int <= ID;
5'h00: up_rdata_int <= PCORE_VERSION;
5'h01: up_rdata_int <= ID;
/* Core configuration */
14'h003: up_rdata_int <= NUM_OF_CLOCKS;
14'h004: up_rdata_int <= {31'h00, up_reset_core};
5'h03: up_rdata_int <= NUM_OF_CLOCKS;
5'h04: up_rdata_int <= {31'h00, up_reset_core};
/* Clock ratios registers*/
14'h010: up_rdata_int <= {11'h00, clk_mon_count[ 0]};
14'h011: up_rdata_int <= {11'h00, clk_mon_count[ 1]};
14'h012: up_rdata_int <= {11'h00, clk_mon_count[ 2]};
14'h013: up_rdata_int <= {11'h00, clk_mon_count[ 3]};
14'h014: up_rdata_int <= {11'h00, clk_mon_count[ 4]};
14'h015: up_rdata_int <= {11'h00, clk_mon_count[ 5]};
14'h016: up_rdata_int <= {11'h00, clk_mon_count[ 6]};
14'h017: up_rdata_int <= {11'h00, clk_mon_count[ 7]};
14'h018: up_rdata_int <= {11'h00, clk_mon_count[ 8]};
14'h019: up_rdata_int <= {11'h00, clk_mon_count[ 9]};
14'h01a: up_rdata_int <= {11'h00, clk_mon_count[10]};
14'h01b: up_rdata_int <= {11'h00, clk_mon_count[11]};
14'h01c: up_rdata_int <= {11'h00, clk_mon_count[12]};
14'h01d: up_rdata_int <= {11'h00, clk_mon_count[13]};
14'h01e: up_rdata_int <= {11'h00, clk_mon_count[14]};
14'h01f: up_rdata_int <= {11'h00, clk_mon_count[15]};
5'h10: up_rdata_int <= {11'h00, clk_mon_count[ 0]};
5'h11: up_rdata_int <= {11'h00, clk_mon_count[ 1]};
5'h12: up_rdata_int <= {11'h00, clk_mon_count[ 2]};
5'h13: up_rdata_int <= {11'h00, clk_mon_count[ 3]};
5'h14: up_rdata_int <= {11'h00, clk_mon_count[ 4]};
5'h15: up_rdata_int <= {11'h00, clk_mon_count[ 5]};
5'h16: up_rdata_int <= {11'h00, clk_mon_count[ 6]};
5'h17: up_rdata_int <= {11'h00, clk_mon_count[ 7]};
5'h18: up_rdata_int <= {11'h00, clk_mon_count[ 8]};
5'h19: up_rdata_int <= {11'h00, clk_mon_count[ 9]};
5'h1a: up_rdata_int <= {11'h00, clk_mon_count[10]};
5'h1b: up_rdata_int <= {11'h00, clk_mon_count[11]};
5'h1c: up_rdata_int <= {11'h00, clk_mon_count[12]};
5'h1d: up_rdata_int <= {11'h00, clk_mon_count[13]};
5'h1e: up_rdata_int <= {11'h00, clk_mon_count[14]};
5'h1f: up_rdata_int <= {11'h00, clk_mon_count[15]};
default: up_rdata_int <= 'h00;
endcase
@@ -257,11 +250,11 @@ module axi_clock_monitor #(
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_i_s),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_i_s),
.up_wdata (up_wdata_i_s),
.up_wack (up_wack_o_s),
.up_rreq (up_rreq_i_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_i_s),
.up_rdata (up_rdata_o_s),
.up_rack (up_rack_o_s));
adi_library/axi_clock_monitor/axi_clock_monitor.xpr
+13 -14
View File
@@ -1,13 +1,13 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
<!-- Product Version: Vivado v2024.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_clock_monitor/axi_clock_monitor.xpr">
<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_clock_monitor/axi_clock_monitor.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="697ae42879c74323ae18ea01dab35596"/>
<Option Name="Id" Val="421f2aaaf4104f74967bdf5a42647752"/>
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
<Option Name="SimulatorVersionXsim" Val="2024.1"/>
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
<Option Name="SimulatorVersionRiviera" Val="2023.04"/>
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -174,21 +173,21 @@
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="21">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Runs Version="1" Minor="22">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
@@ -201,7 +200,7 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
adi_library/axi_clock_monitor/component.xml
+6 -6
View File
@@ -257,7 +257,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>17b5e71c</spirit:value>
<spirit:value>c0944db9</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -273,7 +273,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>b0e420e2</spirit:value>
<spirit:value>b16a94ea</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1000,7 +1000,7 @@
<spirit:file>
<spirit:name>axi_clock_monitor.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_3b1ac4a2</spirit:userFileType>
<spirit:userFileType>CHECKSUM_7a2faf0d</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
@@ -1083,11 +1083,11 @@
<xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
<xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/axi_clock_monitor</xilinx:vendorURL>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2024-01-14T03:45:20Z</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>2024-06-06T03:01:25Z</xilinx:coreCreationDateTime>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="c6e366c8"/>
<xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="1e4179a7"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="164310c9"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="e8384fdb"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="ce8ad7eb"/>