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update adi_library to vivado 2024.1

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compile adi_library with latest hdl commit and vivado 2024.1
This commit is contained in:
josh
2024-06-06 11:22:50 +08:00
parent 3c6c573f6a
commit 24cc6b9ee9
695 changed files with 17906 additions and 9982 deletions
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adi_library/axi_dmac/address_generator.v
+6 -7
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@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
@@ -43,7 +43,8 @@ module address_generator #(
parameter BEATS_PER_BURST_WIDTH = 4,
parameter BYTES_PER_BEAT_WIDTH = $clog2(DMA_DATA_WIDTH/8),
parameter LENGTH_WIDTH = 8,
parameter CACHE_COHERENT = 0
parameter [3:0] AXI_AXCACHE = 4'b0011,
parameter [2:0] AXI_AXPROT = 3'b000
) (
input clk,
input resetn,
@@ -80,10 +81,8 @@ module address_generator #(
`include "inc_id.vh"
assign burst = 2'b01;
assign prot = 3'b000;
// If CACHE_COHERENT is set, signal downstream that this transaction must be
// looked up in cache. Otherwise default to "normal non-cachable bufferable".
assign cache = CACHE_COHERENT ? 4'b1110 : 4'b0011;
assign prot = AXI_AXPROT;
assign cache = AXI_AXCACHE;
assign size = DMA_DATA_WIDTH == 1024 ? 3'b111 :
DMA_DATA_WIDTH == 512 ? 3'b110 :
DMA_DATA_WIDTH == 256 ? 3'b101 :
adi_library/axi_dmac/axi_dmac.v
+10 -5
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@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
@@ -70,7 +70,9 @@ module axi_dmac #(
parameter DISABLE_DEBUG_REGISTERS = 0,
parameter ENABLE_DIAGNOSTICS_IF = 0,
parameter ALLOW_ASYM_MEM = 0,
parameter CACHE_COHERENT_DEST = 0
parameter CACHE_COHERENT = 0,
parameter [3:0] AXI_AXCACHE = 4'b0011,
parameter [2:0] AXI_AXPROT = 3'b000
) (
// Slave AXI interface
@@ -447,7 +449,9 @@ module axi_dmac #(
.DMA_2D_TRANSFER(DMA_2D_TRANSFER),
.DMA_SG_TRANSFER(DMA_SG_TRANSFER),
.SYNC_TRANSFER_START(SYNC_TRANSFER_START),
.CACHE_COHERENT_DEST(CACHE_COHERENT_DEST)
.CACHE_COHERENT(CACHE_COHERENT),
.AXI_AXCACHE(AXI_AXCACHE),
.AXI_AXPROT(AXI_AXPROT)
) i_regmap (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
@@ -537,7 +541,8 @@ module axi_dmac #(
.AXI_LENGTH_WIDTH_SG(8-(4*DMA_AXI_PROTOCOL_SG)),
.ENABLE_DIAGNOSTICS_IF(ENABLE_DIAGNOSTICS_IF),
.ALLOW_ASYM_MEM(ALLOW_ASYM_MEM),
.CACHE_COHERENT_DEST(CACHE_COHERENT_DEST)
.AXI_AXCACHE(AXI_AXCACHE),
.AXI_AXPROT(AXI_AXPROT)
) i_transfer (
.ctrl_clk(s_axi_aclk),
.ctrl_resetn(s_axi_aresetn),
adi_library/axi_dmac/axi_dmac.xpr
+13 -14
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@@ -1,13 +1,13 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
<!-- Product Version: Vivado v2024.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_dmac/axi_dmac.xpr">
<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_dmac/axi_dmac.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="9452152444d94dd49704b10ff32911da"/>
<Option Name="Id" Val="3e1cb6fd4c2b4f769f8b27662b0ad072"/>
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
<Option Name="SimulatorVersionXsim" Val="2024.1"/>
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
<Option Name="SimulatorVersionRiviera" Val="2023.04"/>
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -359,21 +358,21 @@
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="21">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Runs Version="1" Minor="22">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
@@ -386,7 +385,7 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
adi_library/axi_dmac/axi_dmac_burst_memory.v
+1 -1
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@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
adi_library/axi_dmac/axi_dmac_hw.tcl
+74 -7
View File
@@ -1,5 +1,5 @@
###############################################################################
## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
@@ -92,6 +92,46 @@ set_parameter_property DMA_AXI_ADDR_WIDTH HDL_PARAMETER true
set_parameter_property DMA_AXI_ADDR_WIDTH ALLOWED_RANGES {16:64}
set_parameter_property DMA_AXI_ADDR_WIDTH GROUP $group
add_parameter AXI_AXCACHE_AUTO BOOLEAN 1
set_parameter_property AXI_AXCACHE_AUTO DISPLAY_NAME "ARCACHE/AWCACHE Automatically Set"
set_parameter_property AXI_AXCACHE_AUTO HDL_PARAMETER false
set_parameter_property AXI_AXCACHE_AUTO GROUP $group
add_parameter AXI_AXPROT_AUTO BOOLEAN 1
set_parameter_property AXI_AXPROT_AUTO DISPLAY_NAME "ARPROT/AWPROT Automatically Set"
set_parameter_property AXI_AXPROT_AUTO HDL_PARAMETER false
set_parameter_property AXI_AXPROT_AUTO GROUP $group
add_parameter AXI_AXCACHE_MANUAL STD_LOGIC_VECTOR
set_parameter_property AXI_AXCACHE_MANUAL WIDTH 4
set_parameter_property AXI_AXCACHE_MANUAL DISPLAY_NAME "ARCACHE/AWCACHE"
set_parameter_property AXI_AXCACHE_MANUAL HDL_PARAMETER false
set_parameter_property AXI_AXCACHE_MANUAL ALLOWED_RANGES {0x0:0xF}
set_parameter_property AXI_AXCACHE_MANUAL GROUP $group
add_parameter AXI_AXPROT_MANUAL STD_LOGIC_VECTOR
set_parameter_property AXI_AXPROT_MANUAL WIDTH 3
set_parameter_property AXI_AXPROT_MANUAL DISPLAY_NAME "ARPROT/AWPROT"
set_parameter_property AXI_AXPROT_MANUAL HDL_PARAMETER false
set_parameter_property AXI_AXPROT_MANUAL ALLOWED_RANGES {0x0:0x7}
set_parameter_property AXI_AXPROT_MANUAL GROUP $group
add_parameter AXI_AXCACHE STD_LOGIC_VECTOR
set_parameter_property AXI_AXCACHE WIDTH 4
set_parameter_property AXI_AXCACHE DISPLAY_NAME "ARCACHE/AWCACHE"
set_parameter_property AXI_AXCACHE HDL_PARAMETER true
set_parameter_property AXI_AXCACHE ALLOWED_RANGES {0x0:0xF}
set_parameter_property AXI_AXCACHE DERIVED true
set_parameter_property AXI_AXCACHE GROUP $group
add_parameter AXI_AXPROT STD_LOGIC_VECTOR
set_parameter_property AXI_AXPROT WIDTH 3
set_parameter_property AXI_AXPROT DISPLAY_NAME "ARPROT/AWPROT"
set_parameter_property AXI_AXPROT HDL_PARAMETER true
set_parameter_property AXI_AXPROT ALLOWED_RANGES {0x0:0x7}
set_parameter_property AXI_AXPROT DERIVED true
set_parameter_property AXI_AXPROT GROUP $group
foreach {suffix group} { \
"SRC" "Source" \
"DEST" "Destination" \
@@ -153,24 +193,31 @@ set_parameter_property CYCLIC DISPLAY_HINT boolean
set_parameter_property CYCLIC HDL_PARAMETER true
set_parameter_property CYCLIC GROUP $group
add_parameter DMA_2D_TRANSFER INTEGER 0
set_parameter_property DMA_2D_TRANSFER DISPLAY_NAME "2D Transfer Support"
set_parameter_property DMA_2D_TRANSFER DISPLAY_HINT boolean
set_parameter_property DMA_2D_TRANSFER HDL_PARAMETER true
set_parameter_property DMA_2D_TRANSFER GROUP $group
add_parameter DMA_SG_TRANSFER INTEGER 0
set_parameter_property DMA_SG_TRANSFER DISPLAY_NAME "SG Transfer Support"
set_parameter_property DMA_SG_TRANSFER DISPLAY_HINT boolean
set_parameter_property DMA_SG_TRANSFER HDL_PARAMETER true
set_parameter_property DMA_SG_TRANSFER GROUP $group
add_parameter DMA_2D_TRANSFER INTEGER 0
set_parameter_property DMA_2D_TRANSFER DISPLAY_NAME "2D Transfer Support"
set_parameter_property DMA_2D_TRANSFER DISPLAY_HINT boolean
set_parameter_property DMA_2D_TRANSFER HDL_PARAMETER true
set_parameter_property DMA_2D_TRANSFER GROUP $group
add_parameter SYNC_TRANSFER_START INTEGER 0
set_parameter_property SYNC_TRANSFER_START DISPLAY_NAME "Transfer Start Synchronization Support"
set_parameter_property SYNC_TRANSFER_START DISPLAY_HINT boolean
set_parameter_property SYNC_TRANSFER_START HDL_PARAMETER true
set_parameter_property SYNC_TRANSFER_START GROUP $group
add_parameter CACHE_COHERENT BOOLEAN 0
set_parameter_property CACHE_COHERENT DISPLAY_NAME "Cache Coherent"
set_parameter_property CACHE_COHERENT DESCRIPTION "Assume DMA ports ensure cache coherence"
set_parameter_property CACHE_COHERENT DISPLAY_HINT boolean
set_parameter_property CACHE_COHERENT HDL_PARAMETER true
set_parameter_property CACHE_COHERENT GROUP $group
set group "Clock Domain Configuration"
add_parameter AUTO_ASYNC_CLK BOOLEAN 1
@@ -328,6 +375,26 @@ proc axi_dmac_validate {} {
}
set_parameter_property MAX_BYTES_PER_BURST ALLOWED_RANGES "1:$max_burst"
set cache_coherent [get_parameter_value CACHE_COHERENT]
set axcache_auto [get_parameter_value AXI_AXCACHE_AUTO]
set axprot_auto [get_parameter_value AXI_AXPROT_AUTO]
set axcache_manual [get_parameter_value AXI_AXCACHE_MANUAL]
set axprot_manual [get_parameter_value AXI_AXPROT_MANUAL]
set axcache_default [expr {$cache_coherent == true} ? 0xF : 0x3]
set axprot_default [expr {$cache_coherent == true} ? 0x2 : 0x0]
set_parameter_property AXI_AXCACHE_AUTO ENABLED $cache_coherent
set_parameter_property AXI_AXPROT_AUTO ENABLED $cache_coherent
set_parameter_property AXI_AXCACHE_MANUAL ENABLED $cache_coherent
set_parameter_property AXI_AXPROT_MANUAL ENABLED $cache_coherent
set_parameter_property AXI_AXCACHE_MANUAL VISIBLE [expr {$cache_coherent == true} ? [expr {$axcache_auto == true} ? false : true] : false]
set_parameter_property AXI_AXPROT_MANUAL VISIBLE [expr {$cache_coherent == true} ? [expr {$axprot_auto == true} ? false : true] : false]
set_parameter_property AXI_AXCACHE VISIBLE [expr {$cache_coherent == true} ? $axcache_auto : true]
set_parameter_property AXI_AXPROT VISIBLE [expr {$cache_coherent == true} ? $axprot_auto : true]
set_parameter_value AXI_AXCACHE [expr {$cache_coherent == true} ? [expr {$axcache_auto == true} ? $axcache_default : $axcache_manual] : $axcache_default]
set_parameter_value AXI_AXPROT [expr {$cache_coherent == true} ? [expr {$axprot_auto == true} ? $axprot_default : $axprot_manual] : $axprot_default]
}
# conditional interfaces
adi_library/axi_dmac/axi_dmac_ip.tcl
+35 -19
View File
@@ -1,5 +1,5 @@
###############################################################################
## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
@@ -274,14 +274,14 @@ foreach {k v} { \
"ASYNC_CLK_SRC_SG" "true" \
"ASYNC_CLK_DEST_SG" "true" \
"CYCLIC" "false" \
"DMA_2D_TRANSFER" "false" \
"DMA_SG_TRANSFER" "false" \
"DMA_2D_TRANSFER" "false" \
"SYNC_TRANSFER_START" "false" \
"AXI_SLICE_SRC" "false" \
"AXI_SLICE_DEST" "false" \
"DISABLE_DEBUG_REGISTERS" "false" \
"ENABLE_DIAGNOSTICS_IF" "false" \
"CACHE_COHERENT_DEST" "false" \
"CACHE_COHERENT" "false" \
} { \
set_property -dict [list \
"value_format" "bool" \
@@ -369,18 +369,6 @@ set_property -dict [list \
"enablement_tcl_expr" "\$DMA_TYPE_SRC != 0" \
] [ipx::get_user_parameters SYNC_TRANSFER_START -of_objects $cc]
set p [ipgui::get_guiparamspec -name "CACHE_COHERENT_DEST" -component $cc]
ipgui::move_param -component $cc -order 4 $p -parent $dest_group
set_property -dict [list \
"tooltip" "Assume destination port ensures cache coherency (e.g. Ultrascale HPC port)" \
] $p
set_property -dict [list \
"display_name" "Assume cache coherent" \
"enablement_tcl_expr" "\$DMA_TYPE_DEST == 0 && \$DMA_AXI_PROTOCOL_DEST == 0" \
"value_tcl_expr" "\$DMA_TYPE_DEST == 0 && \$DMA_AXI_PROTOCOL_DEST == 0" \
"enablement_value" "false" \
] [ipx::get_user_parameters CACHE_COHERENT_DEST -of_objects $cc]
set p [ipgui::get_guiparamspec -name "DMA_AXI_PROTOCOL_SG" -component $cc]
ipgui::move_param -component $cc -order 0 $p -parent $sg_group
set_property -dict [list \
@@ -441,6 +429,24 @@ set_property -dict [list \
"display_name" "DMA AXI Address Width" \
] $p
set p [ipgui::get_guiparamspec -name "AXI_AXCACHE" -component $cc]
ipgui::move_param -component $cc -order 5 $p -parent $general_group
set_property -dict [list \
"display_name" "ARCACHE/AWCACHE" \
] $p
set_property -dict [list \
"enablement_tcl_expr" "\$CACHE_COHERENT == true" \
] [ipx::get_user_parameters AXI_AXCACHE -of_objects $cc]
set p [ipgui::get_guiparamspec -name "AXI_AXPROT" -component $cc]
ipgui::move_param -component $cc -order 6 $p -parent $general_group
set_property -dict [list \
"display_name" "ARPROT/AWPROT" \
] $p
set_property -dict [list \
"enablement_tcl_expr" "\$CACHE_COHERENT == true" \
] [ipx::get_user_parameters AXI_AXPROT -of_objects $cc]
set feature_group [ipgui::add_group -name "Features" -component $cc \
-parent $page0 -display_name "Features"]
@@ -450,17 +456,27 @@ set_property -dict [list \
"display_name" "Cyclic Transfer Support" \
] $p
set p [ipgui::get_guiparamspec -name "DMA_2D_TRANSFER" -component $cc]
set p [ipgui::get_guiparamspec -name "DMA_SG_TRANSFER" -component $cc]
ipgui::move_param -component $cc -order 1 $p -parent $feature_group
set_property -dict [list \
"display_name" "SG Transfer Support" \
] $p
set p [ipgui::get_guiparamspec -name "DMA_2D_TRANSFER" -component $cc]
ipgui::move_param -component $cc -order 2 $p -parent $feature_group
set_property -dict [list \
"display_name" "2D Transfer Support" \
] $p
set p [ipgui::get_guiparamspec -name "DMA_SG_TRANSFER" -component $cc]
ipgui::move_param -component $cc -order 2 $p -parent $feature_group
set p [ipgui::get_guiparamspec -name "CACHE_COHERENT" -component $cc]
ipgui::move_param -component $cc -order 3 $p -parent $feature_group
set_property -dict [list \
"display_name" "SG Transfer Support" \
"tooltip" "Assume DMA ports ensure cache coherence (e.g. Ultrascale HPC port)" \
] $p
set_property -dict [list \
"display_name" "Cache Coherent" \
"enablement_tcl_expr" "\$DMA_TYPE_SRC == 0 || \$DMA_TYPE_DEST == 0" \
] [ipx::get_user_parameters CACHE_COHERENT -of_objects $cc]
set clk_group [ipgui::add_group -name {Clock Domain Configuration} -component $cc \
-parent $page0 -display_name {Clock Domain Configuration}]
adi_library/axi_dmac/axi_dmac_regmap.v
+10 -5
View File
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
@@ -53,7 +53,9 @@ module axi_dmac_regmap #(
parameter DMA_2D_TRANSFER = 0,
parameter DMA_SG_TRANSFER = 0,
parameter SYNC_TRANSFER_START = 0,
parameter CACHE_COHERENT_DEST = 0
parameter CACHE_COHERENT = 0,
parameter [3:0] AXI_AXCACHE = 4'b0011,
parameter [2:0] AXI_AXPROT = 3'b000
) (
// Slave AXI interface
@@ -121,7 +123,7 @@ module axi_dmac_regmap #(
input [31:0] dbg_ids1
);
localparam PCORE_VERSION = 'h00040561;
localparam PCORE_VERSION = 'h00040562;
localparam HAS_ADDR_HIGH = DMA_AXI_ADDR_WIDTH > 32;
localparam ADDR_LOW_MSB = HAS_ADDR_HIGH ? 31 : DMA_AXI_ADDR_WIDTH-1;
@@ -223,7 +225,10 @@ module axi_dmac_regmap #(
4'b0,BYTES_PER_BURST_WIDTH[3:0],
2'b0,DMA_TYPE_SRC[1:0],BYTES_PER_BEAT_WIDTH_SRC[3:0],
2'b0,DMA_TYPE_DEST[1:0],BYTES_PER_BEAT_WIDTH_DEST[3:0]};
9'h005: up_rdata <= {31'd0, CACHE_COHERENT_DEST};
9'h005: up_rdata <= {20'b0,
1'b0,AXI_AXPROT,
AXI_AXCACHE,
3'b0,CACHE_COHERENT};
9'h020: up_rdata <= up_irq_mask;
9'h021: up_rdata <= up_irq_pending;
9'h022: up_rdata <= up_irq_source;
adi_library/axi_dmac/axi_dmac_regmap_request.v
+1 -1
View File
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
adi_library/axi_dmac/axi_dmac_reset_manager.v
+1 -1
View File
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
adi_library/axi_dmac/axi_dmac_resize_dest.v
+1 -1
View File
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
adi_library/axi_dmac/axi_dmac_resize_src.v
+1 -1
View File
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
adi_library/axi_dmac/axi_dmac_response_manager.v
+1 -1
View File
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
adi_library/axi_dmac/axi_dmac_transfer.v
+9 -5
View File
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
@@ -64,7 +64,8 @@ module axi_dmac_transfer #(
parameter AXI_LENGTH_WIDTH_SG = 8,
parameter ENABLE_DIAGNOSTICS_IF = 0,
parameter ALLOW_ASYM_MEM = 0,
parameter CACHE_COHERENT_DEST = 0
parameter [3:0] AXI_AXCACHE = 4'b0011,
parameter [2:0] AXI_AXPROT = 3'b000
) (
input ctrl_clk,
input ctrl_resetn,
@@ -321,7 +322,9 @@ module axi_dmac_transfer #(
.BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST),
.BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC),
.BYTES_PER_BEAT_WIDTH_SG(BYTES_PER_BEAT_WIDTH_SG),
.ASYNC_CLK_REQ_SG(ASYNC_CLK_REQ_SG)
.ASYNC_CLK_REQ_SG(ASYNC_CLK_REQ_SG),
.AXI_AXCACHE(AXI_AXCACHE),
.AXI_AXPROT(AXI_AXPROT)
) i_dmac_sg (
.req_clk(req_clk),
.req_resetn(req_resetn),
@@ -500,7 +503,8 @@ module axi_dmac_transfer #(
.AXI_LENGTH_WIDTH_SRC (AXI_LENGTH_WIDTH_SRC),
.ENABLE_DIAGNOSTICS_IF(ENABLE_DIAGNOSTICS_IF),
.ALLOW_ASYM_MEM (ALLOW_ASYM_MEM),
.CACHE_COHERENT_DEST(CACHE_COHERENT_DEST)
.AXI_AXCACHE(AXI_AXCACHE),
.AXI_AXPROT(AXI_AXPROT)
) i_request_arb (
.req_clk (req_clk),
.req_resetn (req_resetn),
adi_library/axi_dmac/axi_register_slice.v
+1 -1
View File
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
adi_library/axi_dmac/bd/bd.tcl
+8 -1
View File
@@ -1,5 +1,5 @@
###############################################################################
## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2015-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
@@ -203,4 +203,11 @@ proc post_propagate {cellpath otherinfo} {
}
set_property "CONFIG.DMA_AXI_ADDR_WIDTH" $addr_width $ip
# AXCACHE/AXPROT configuration
set cache_coherent [get_property "CONFIG.CACHE_COHERENT" $ip]
set axcache [expr {$cache_coherent == true} ? 0b1111 : 0b0011]
set axprot [expr {$cache_coherent == true} ? 0b010 : 0b000]
set_property "CONFIG.AXI_AXCACHE" $axcache $ip
set_property "CONFIG.AXI_AXPROT" $axprot $ip
}
adi_library/axi_dmac/component.xml
+65 -17
View File
@@ -1798,7 +1798,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>4406b039</spirit:value>
<spirit:value>13fa364a</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1820,7 +1820,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>4406b039</spirit:value>
<spirit:value>13fa364a</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1840,7 +1840,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>a3380b44</spirit:value>
<spirit:value>8b30a977</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -6184,9 +6184,33 @@
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ALLOW_ASYM_MEM">0</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>CACHE_COHERENT_DEST</spirit:name>
<spirit:displayName>Cache Coherent Dest</spirit:displayName>
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CACHE_COHERENT_DEST">true</spirit:value>
<spirit:name>CACHE_COHERENT</spirit:name>
<spirit:displayName>Cache Coherent</spirit:displayName>
<spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CACHE_COHERENT">false</spirit:value>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>AXI_AXCACHE</spirit:name>
<spirit:displayName>Axi Axcache</spirit:displayName>
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXI_AXCACHE" spirit:bitStringLength="4">&quot;0011&quot;</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.AXI_AXCACHE">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:modelParameter>
<spirit:modelParameter spirit:dataType="integer">
<spirit:name>AXI_AXPROT</spirit:name>
<spirit:displayName>Axi Axprot</spirit:displayName>
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXI_AXPROT" spirit:bitStringLength="3">&quot;000&quot;</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.AXI_AXPROT">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:modelParameter>
</spirit:modelParameters>
</spirit:model>
@@ -6366,7 +6390,7 @@
<spirit:file>
<spirit:name>axi_dmac.v</spirit:name>
<spirit:fileType>verilogSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_b602bf53</spirit:userFileType>
<spirit:userFileType>CHECKSUM_9c4d9b37</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
@@ -6543,7 +6567,7 @@
<spirit:file>
<spirit:name>xgui/axi_dmac_v1_0.tcl</spirit:name>
<spirit:fileType>tclSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_57e931f4</spirit:userFileType>
<spirit:userFileType>CHECKSUM_6f5028ec</spirit:userFileType>
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
@@ -6797,13 +6821,37 @@
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ALLOW_ASYM_MEM">0</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>CACHE_COHERENT_DEST</spirit:name>
<spirit:displayName>Assume cache coherent</spirit:displayName>
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CACHE_COHERENT_DEST">true</spirit:value>
<spirit:name>CACHE_COHERENT</spirit:name>
<spirit:displayName>Cache Coherent</spirit:displayName>
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CACHE_COHERENT">false</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.CACHE_COHERENT_DEST">true</xilinx:isEnabled>
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.CACHE_COHERENT">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>AXI_AXCACHE</spirit:name>
<spirit:displayName>ARCACHE/AWCACHE</spirit:displayName>
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_AXCACHE" spirit:bitStringLength="4">&quot;0011&quot;</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.AXI_AXCACHE">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
</spirit:parameter>
<spirit:parameter>
<spirit:name>AXI_AXPROT</spirit:name>
<spirit:displayName>ARPROT/AWPROT</spirit:displayName>
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_AXPROT" spirit:bitStringLength="3">&quot;000&quot;</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.AXI_AXPROT">false</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
@@ -6827,15 +6875,15 @@
<xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
<xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/axi_dmac</xilinx:vendorURL>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:coreCreationDateTime>2024-01-14T03:46:09Z</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>2024-06-06T03:02:18Z</xilinx:coreCreationDateTime>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
<xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="addressSpaces" xilinx:value="8f64214e"/>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="171a117c"/>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="b8e5e594"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="694663ae"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="623ef345"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="3f338230"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="ab308b95"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="42e5d39a"/>
</xilinx:packagingInfo>
</spirit:vendorExtensions>
</spirit:component>
adi_library/axi_dmac/data_mover.v
+1 -1
View File
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
adi_library/axi_dmac/dest_axi_mm.v
+6 -4
View File
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
@@ -45,7 +45,8 @@ module dest_axi_mm #(
parameter MAX_BYTES_PER_BURST = 128,
parameter BYTES_PER_BURST_WIDTH = $clog2(MAX_BYTES_PER_BURST),
parameter AXI_LENGTH_WIDTH = 8,
parameter CACHE_COHERENT = 0
parameter [3:0] AXI_AXCACHE = 4'b0011,
parameter [2:0] AXI_AXPROT = 3'b000
) (
input m_axi_aclk,
input m_axi_aresetn,
@@ -117,7 +118,8 @@ module dest_axi_mm #(
.DMA_DATA_WIDTH(DMA_DATA_WIDTH),
.LENGTH_WIDTH(AXI_LENGTH_WIDTH),
.DMA_ADDR_WIDTH(DMA_ADDR_WIDTH),
.CACHE_COHERENT(CACHE_COHERENT)
.AXI_AXCACHE(AXI_AXCACHE),
.AXI_AXPROT(AXI_AXPROT)
) i_addr_gen (
.clk(m_axi_aclk),
.resetn(m_axi_aresetn),
adi_library/axi_dmac/dest_axi_stream.v
+1 -1
View File
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
adi_library/axi_dmac/dest_fifo_inf.v
+1 -1
View File
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
adi_library/axi_dmac/dmac_2d_transfer.v
+1 -1
View File
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
adi_library/axi_dmac/dmac_sg.v
+7 -5
View File
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
@@ -43,7 +43,9 @@ module dmac_sg #(
parameter BYTES_PER_BEAT_WIDTH_DEST = 3,
parameter BYTES_PER_BEAT_WIDTH_SRC = 3,
parameter BYTES_PER_BEAT_WIDTH_SG = 3,
parameter ASYNC_CLK_REQ_SG = 1
parameter ASYNC_CLK_REQ_SG = 1,
parameter [3:0] AXI_AXCACHE = 4'b0011,
parameter [2:0] AXI_AXPROT = 3'b000
) (
input req_clk,
input req_resetn,
@@ -147,8 +149,8 @@ module dmac_sg #(
assign m_axi_arsize = 3'h3;
assign m_axi_arburst = 2'h1;
assign m_axi_arprot = 3'h0;
assign m_axi_arcache = 4'h3;
assign m_axi_arprot = AXI_AXPROT;
assign m_axi_arcache = AXI_AXCACHE;
assign m_axi_arlen = 'h5;
assign m_axi_araddr = {next_desc_addr, {BYTES_PER_BEAT_WIDTH_SG{1'b0}}};
adi_library/axi_dmac/gui/axi_dmac_v1_0.gtcl
+3 -2
View File
@@ -4,5 +4,6 @@ proc gen_USERPARAMETER_SYNC_TRANSFER_START_ENABLEMENT {DMA_TYPE_SRC } {expr $DMA
proc gen_USERPARAMETER_DMA_AXI_PROTOCOL_DEST_ENABLEMENT {DMA_TYPE_DEST } {expr $DMA_TYPE_DEST == 0}
proc gen_USERPARAMETER_DMA_AXI_PROTOCOL_SRC_ENABLEMENT {DMA_TYPE_SRC } {expr $DMA_TYPE_SRC == 0}
proc gen_USERPARAMETER_DMA_AXI_PROTOCOL_SG_ENABLEMENT {DMA_SG_TRANSFER } {expr $DMA_SG_TRANSFER == true}
proc gen_USERPARAMETER_CACHE_COHERENT_DEST_ENABLEMENT {DMA_TYPE_DEST DMA_AXI_PROTOCOL_DEST } {expr $DMA_TYPE_DEST == 0 && $DMA_AXI_PROTOCOL_DEST == 0}
proc gen_USERPARAMETER_CACHE_COHERENT_DEST_VALUE {DMA_TYPE_DEST DMA_AXI_PROTOCOL_DEST } {expr $DMA_TYPE_DEST == 0 && $DMA_AXI_PROTOCOL_DEST == 0}
proc gen_USERPARAMETER_CACHE_COHERENT_ENABLEMENT {DMA_TYPE_SRC DMA_TYPE_DEST } {expr $DMA_TYPE_SRC == 0 || $DMA_TYPE_DEST == 0}
proc gen_USERPARAMETER_AXI_AXCACHE_ENABLEMENT {CACHE_COHERENT } {expr $CACHE_COHERENT == true}
proc gen_USERPARAMETER_AXI_AXPROT_ENABLEMENT {CACHE_COHERENT } {expr $CACHE_COHERENT == true}
adi_library/axi_dmac/request_arb.v
+9 -5
View File
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
@@ -58,7 +58,8 @@ module request_arb #(
parameter AXI_LENGTH_WIDTH_DEST = 8,
parameter ENABLE_DIAGNOSTICS_IF = 0,
parameter ALLOW_ASYM_MEM = 0,
parameter CACHE_COHERENT_DEST = 0
parameter [3:0] AXI_AXCACHE = 4'b0011,
parameter [2:0] AXI_AXPROT = 3'b000
) (
input req_clk,
input req_resetn,
@@ -357,7 +358,8 @@ module request_arb #(
.MAX_BYTES_PER_BURST(MAX_BYTES_PER_BURST),
.BYTES_PER_BURST_WIDTH(BYTES_PER_BURST_WIDTH),
.AXI_LENGTH_WIDTH(AXI_LENGTH_WIDTH_DEST),
.CACHE_COHERENT(CACHE_COHERENT_DEST)
.AXI_AXCACHE(AXI_AXCACHE),
.AXI_AXPROT(AXI_AXPROT)
) i_dest_dma_mm (
.m_axi_aclk(m_dest_axi_aclk),
.m_axi_aresetn(dest_resetn),
@@ -619,7 +621,9 @@ module request_arb #(
.DMA_ADDR_WIDTH(DMA_AXI_ADDR_WIDTH),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC),
.BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH_SRC),
.AXI_LENGTH_WIDTH(AXI_LENGTH_WIDTH_SRC)
.AXI_LENGTH_WIDTH(AXI_LENGTH_WIDTH_SRC),
.AXI_AXCACHE(AXI_AXCACHE),
.AXI_AXPROT(AXI_AXPROT)
) i_src_dma_mm (
.m_axi_aclk(m_src_axi_aclk),
.m_axi_aresetn(src_resetn),
adi_library/axi_dmac/request_generator.v
+1 -1
View File
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
adi_library/axi_dmac/response_generator.v
+1 -1
View File
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
adi_library/axi_dmac/response_handler.v
+1 -1
View File
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
adi_library/axi_dmac/splitter.v
+1 -1
View File
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
adi_library/axi_dmac/src_axi_mm.v
+8 -4
View File
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
@@ -42,7 +42,9 @@ module src_axi_mm #(
parameter DMA_ADDR_WIDTH = 32,
parameter BYTES_PER_BEAT_WIDTH = 3,
parameter BEATS_PER_BURST_WIDTH = 4,
parameter AXI_LENGTH_WIDTH = 8
parameter AXI_LENGTH_WIDTH = 8,
parameter [3:0] AXI_AXCACHE = 4'b0011,
parameter [2:0] AXI_AXPROT = 3'b000
) (
input m_axi_aclk,
input m_axi_aresetn,
@@ -148,7 +150,9 @@ module src_axi_mm #(
.BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH),
.DMA_DATA_WIDTH(DMA_DATA_WIDTH),
.LENGTH_WIDTH(AXI_LENGTH_WIDTH),
.DMA_ADDR_WIDTH(DMA_ADDR_WIDTH)
.DMA_ADDR_WIDTH(DMA_ADDR_WIDTH),
.AXI_AXCACHE(AXI_AXCACHE),
.AXI_AXPROT(AXI_AXPROT)
) i_addr_gen (
.clk(m_axi_aclk),
.resetn(m_axi_aresetn),
adi_library/axi_dmac/src_axi_stream.v
+1 -1
View File
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
adi_library/axi_dmac/src_fifo_inf.v
+1 -1
View File
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
adi_library/axi_dmac/tb/axi_read_slave.v
+1 -1
View File
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
adi_library/axi_dmac/tb/axi_slave.v
+1 -1
View File
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
adi_library/axi_dmac/tb/axi_write_slave.v
+1 -1
View File
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
adi_library/axi_dmac/tb/dma_read_shutdown_tb.v
+1 -1
View File
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
adi_library/axi_dmac/tb/dma_read_tb.v
+1 -1
View File
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
adi_library/axi_dmac/tb/dma_write_shutdown_tb.v
+1 -1
View File
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
adi_library/axi_dmac/tb/dma_write_tb.v
+1 -1
View File
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
adi_library/axi_dmac/tb/regmap_tb.v
+1 -1
View File
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
adi_library/axi_dmac/tb/reset_manager_tb.v
+1 -1
View File
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
adi_library/axi_dmac/tb/tb_base.v
+1 -1
View File
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
adi_library/axi_dmac/xgui/axi_dmac_v1_0.tcl
+65 -18
View File
@@ -25,8 +25,6 @@ proc init_gui { IPINST } {
set DMA_DATA_WIDTH_DEST [ipgui::add_param $IPINST -name "DMA_DATA_WIDTH_DEST" -parent ${Destination}]
set_property tooltip {Bus Width: For Memory-Mapped interface the valid range is 32-1024 bits} ${DMA_DATA_WIDTH_DEST}
ipgui::add_param $IPINST -name "AXI_SLICE_DEST" -parent ${Destination}
set CACHE_COHERENT_DEST [ipgui::add_param $IPINST -name "CACHE_COHERENT_DEST" -parent ${Destination}]
set_property tooltip {Assume destination port ensures cache coherency (e.g. Ultrascale HPC port)} ${CACHE_COHERENT_DEST}
#Adding Group
set Scatter-Gather [ipgui::add_group $IPINST -name "Scatter-Gather" -parent ${DMA_Endpoint_Configuration}]
@@ -41,12 +39,16 @@ proc init_gui { IPINST } {
ipgui::add_param $IPINST -name "FIFO_SIZE" -parent ${General_Configuration} -widget comboBox
ipgui::add_param $IPINST -name "MAX_BYTES_PER_BURST" -parent ${General_Configuration}
ipgui::add_param $IPINST -name "DMA_AXI_ADDR_WIDTH" -parent ${General_Configuration}
ipgui::add_param $IPINST -name "AXI_AXCACHE" -parent ${General_Configuration}
ipgui::add_param $IPINST -name "AXI_AXPROT" -parent ${General_Configuration}
#Adding Group
set Features [ipgui::add_group $IPINST -name "Features" -parent ${Page_0}]
ipgui::add_param $IPINST -name "CYCLIC" -parent ${Features}
ipgui::add_param $IPINST -name "DMA_2D_TRANSFER" -parent ${Features}
ipgui::add_param $IPINST -name "DMA_SG_TRANSFER" -parent ${Features}
ipgui::add_param $IPINST -name "DMA_2D_TRANSFER" -parent ${Features}
set CACHE_COHERENT [ipgui::add_param $IPINST -name "CACHE_COHERENT" -parent ${Features}]
set_property tooltip {Assume DMA ports ensure cache coherence (e.g. Ultrascale HPC port)} ${CACHE_COHERENT}
#Adding Group
set Clock_Domain_Configuration [ipgui::add_group $IPINST -name "Clock Domain Configuration" -parent ${Page_0}]
@@ -66,24 +68,59 @@ proc init_gui { IPINST } {
}
proc update_PARAM_VALUE.CACHE_COHERENT_DEST { PARAM_VALUE.CACHE_COHERENT_DEST PARAM_VALUE.DMA_TYPE_DEST PARAM_VALUE.DMA_AXI_PROTOCOL_DEST } {
# Procedure called to update CACHE_COHERENT_DEST when any of the dependent parameters in the arguments change
proc update_PARAM_VALUE.AXI_AXCACHE { PARAM_VALUE.AXI_AXCACHE PARAM_VALUE.CACHE_COHERENT } {
# Procedure called to update AXI_AXCACHE when any of the dependent parameters in the arguments change
set CACHE_COHERENT_DEST ${PARAM_VALUE.CACHE_COHERENT_DEST}
set DMA_TYPE_DEST ${PARAM_VALUE.DMA_TYPE_DEST}
set DMA_AXI_PROTOCOL_DEST ${PARAM_VALUE.DMA_AXI_PROTOCOL_DEST}
set values(DMA_TYPE_DEST) [get_property value $DMA_TYPE_DEST]
set values(DMA_AXI_PROTOCOL_DEST) [get_property value $DMA_AXI_PROTOCOL_DEST]
if { [gen_USERPARAMETER_CACHE_COHERENT_DEST_ENABLEMENT $values(DMA_TYPE_DEST) $values(DMA_AXI_PROTOCOL_DEST)] } {
set_property enabled true $CACHE_COHERENT_DEST
set AXI_AXCACHE ${PARAM_VALUE.AXI_AXCACHE}
set CACHE_COHERENT ${PARAM_VALUE.CACHE_COHERENT}
set values(CACHE_COHERENT) [get_property value $CACHE_COHERENT]
if { [gen_USERPARAMETER_AXI_AXCACHE_ENABLEMENT $values(CACHE_COHERENT)] } {
set_property enabled true $AXI_AXCACHE
} else {
set_property enabled false $CACHE_COHERENT_DEST
set_property value [gen_USERPARAMETER_CACHE_COHERENT_DEST_VALUE $values(DMA_TYPE_DEST) $values(DMA_AXI_PROTOCOL_DEST)] $CACHE_COHERENT_DEST
set_property enabled false $AXI_AXCACHE
}
}
proc validate_PARAM_VALUE.CACHE_COHERENT_DEST { PARAM_VALUE.CACHE_COHERENT_DEST } {
# Procedure called to validate CACHE_COHERENT_DEST
proc validate_PARAM_VALUE.AXI_AXCACHE { PARAM_VALUE.AXI_AXCACHE } {
# Procedure called to validate AXI_AXCACHE
return true
}
proc update_PARAM_VALUE.AXI_AXPROT { PARAM_VALUE.AXI_AXPROT PARAM_VALUE.CACHE_COHERENT } {
# Procedure called to update AXI_AXPROT when any of the dependent parameters in the arguments change
set AXI_AXPROT ${PARAM_VALUE.AXI_AXPROT}
set CACHE_COHERENT ${PARAM_VALUE.CACHE_COHERENT}
set values(CACHE_COHERENT) [get_property value $CACHE_COHERENT]
if { [gen_USERPARAMETER_AXI_AXPROT_ENABLEMENT $values(CACHE_COHERENT)] } {
set_property enabled true $AXI_AXPROT
} else {
set_property enabled false $AXI_AXPROT
}
}
proc validate_PARAM_VALUE.AXI_AXPROT { PARAM_VALUE.AXI_AXPROT } {
# Procedure called to validate AXI_AXPROT
return true
}
proc update_PARAM_VALUE.CACHE_COHERENT { PARAM_VALUE.CACHE_COHERENT PARAM_VALUE.DMA_TYPE_SRC PARAM_VALUE.DMA_TYPE_DEST } {
# Procedure called to update CACHE_COHERENT when any of the dependent parameters in the arguments change
set CACHE_COHERENT ${PARAM_VALUE.CACHE_COHERENT}
set DMA_TYPE_SRC ${PARAM_VALUE.DMA_TYPE_SRC}
set DMA_TYPE_DEST ${PARAM_VALUE.DMA_TYPE_DEST}
set values(DMA_TYPE_SRC) [get_property value $DMA_TYPE_SRC]
set values(DMA_TYPE_DEST) [get_property value $DMA_TYPE_DEST]
if { [gen_USERPARAMETER_CACHE_COHERENT_ENABLEMENT $values(DMA_TYPE_SRC) $values(DMA_TYPE_DEST)] } {
set_property enabled true $CACHE_COHERENT
} else {
set_property enabled false $CACHE_COHERENT
}
}
proc validate_PARAM_VALUE.CACHE_COHERENT { PARAM_VALUE.CACHE_COHERENT } {
# Procedure called to validate CACHE_COHERENT
return true
}
@@ -595,8 +632,18 @@ proc update_MODELPARAM_VALUE.ALLOW_ASYM_MEM { MODELPARAM_VALUE.ALLOW_ASYM_MEM PA
set_property value [get_property value ${PARAM_VALUE.ALLOW_ASYM_MEM}] ${MODELPARAM_VALUE.ALLOW_ASYM_MEM}
}
proc update_MODELPARAM_VALUE.CACHE_COHERENT_DEST { MODELPARAM_VALUE.CACHE_COHERENT_DEST PARAM_VALUE.CACHE_COHERENT_DEST } {
proc update_MODELPARAM_VALUE.CACHE_COHERENT { MODELPARAM_VALUE.CACHE_COHERENT PARAM_VALUE.CACHE_COHERENT } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.CACHE_COHERENT_DEST}] ${MODELPARAM_VALUE.CACHE_COHERENT_DEST}
set_property value [get_property value ${PARAM_VALUE.CACHE_COHERENT}] ${MODELPARAM_VALUE.CACHE_COHERENT}
}
proc update_MODELPARAM_VALUE.AXI_AXCACHE { MODELPARAM_VALUE.AXI_AXCACHE PARAM_VALUE.AXI_AXCACHE } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.AXI_AXCACHE}] ${MODELPARAM_VALUE.AXI_AXCACHE}
}
proc update_MODELPARAM_VALUE.AXI_AXPROT { MODELPARAM_VALUE.AXI_AXPROT PARAM_VALUE.AXI_AXPROT } {
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
set_property value [get_property value ${PARAM_VALUE.AXI_AXPROT}] ${MODELPARAM_VALUE.AXI_AXPROT}
}