update adi_library to vivado 2024.1
compile adi_library with latest hdl commit and vivado 2024.1
This commit is contained in:
@@ -1,6 +1,6 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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@@ -26,7 +26,7 @@
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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@@ -70,7 +70,9 @@ module axi_dmac #(
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parameter DISABLE_DEBUG_REGISTERS = 0,
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parameter ENABLE_DIAGNOSTICS_IF = 0,
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parameter ALLOW_ASYM_MEM = 0,
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parameter CACHE_COHERENT_DEST = 0
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parameter CACHE_COHERENT = 0,
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parameter [3:0] AXI_AXCACHE = 4'b0011,
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parameter [2:0] AXI_AXPROT = 3'b000
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) (
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// Slave AXI interface
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@@ -447,7 +449,9 @@ module axi_dmac #(
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.DMA_2D_TRANSFER(DMA_2D_TRANSFER),
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.DMA_SG_TRANSFER(DMA_SG_TRANSFER),
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.SYNC_TRANSFER_START(SYNC_TRANSFER_START),
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.CACHE_COHERENT_DEST(CACHE_COHERENT_DEST)
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.CACHE_COHERENT(CACHE_COHERENT),
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.AXI_AXCACHE(AXI_AXCACHE),
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.AXI_AXPROT(AXI_AXPROT)
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) i_regmap (
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.s_axi_aclk(s_axi_aclk),
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.s_axi_aresetn(s_axi_aresetn),
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@@ -537,7 +541,8 @@ module axi_dmac #(
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.AXI_LENGTH_WIDTH_SG(8-(4*DMA_AXI_PROTOCOL_SG)),
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.ENABLE_DIAGNOSTICS_IF(ENABLE_DIAGNOSTICS_IF),
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.ALLOW_ASYM_MEM(ALLOW_ASYM_MEM),
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.CACHE_COHERENT_DEST(CACHE_COHERENT_DEST)
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.AXI_AXCACHE(AXI_AXCACHE),
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.AXI_AXPROT(AXI_AXPROT)
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) i_transfer (
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.ctrl_clk(s_axi_aclk),
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.ctrl_resetn(s_axi_aresetn),
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