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update adi_library to vivado 2024.1

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compile adi_library with latest hdl commit and vivado 2024.1
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josh
2024-06-06 11:22:50 +08:00
parent 3c6c573f6a
commit 24cc6b9ee9
695 changed files with 17906 additions and 9982 deletions
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adi_library/axi_dmac/axi_dmac_regmap.v
+10 -5
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@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
@@ -53,7 +53,9 @@ module axi_dmac_regmap #(
parameter DMA_2D_TRANSFER = 0,
parameter DMA_SG_TRANSFER = 0,
parameter SYNC_TRANSFER_START = 0,
parameter CACHE_COHERENT_DEST = 0
parameter CACHE_COHERENT = 0,
parameter [3:0] AXI_AXCACHE = 4'b0011,
parameter [2:0] AXI_AXPROT = 3'b000
) (
// Slave AXI interface
@@ -121,7 +123,7 @@ module axi_dmac_regmap #(
input [31:0] dbg_ids1
);
localparam PCORE_VERSION = 'h00040561;
localparam PCORE_VERSION = 'h00040562;
localparam HAS_ADDR_HIGH = DMA_AXI_ADDR_WIDTH > 32;
localparam ADDR_LOW_MSB = HAS_ADDR_HIGH ? 31 : DMA_AXI_ADDR_WIDTH-1;
@@ -223,7 +225,10 @@ module axi_dmac_regmap #(
4'b0,BYTES_PER_BURST_WIDTH[3:0],
2'b0,DMA_TYPE_SRC[1:0],BYTES_PER_BEAT_WIDTH_SRC[3:0],
2'b0,DMA_TYPE_DEST[1:0],BYTES_PER_BEAT_WIDTH_DEST[3:0]};
9'h005: up_rdata <= {31'd0, CACHE_COHERENT_DEST};
9'h005: up_rdata <= {20'b0,
1'b0,AXI_AXPROT,
AXI_AXCACHE,
3'b0,CACHE_COHERENT};
9'h020: up_rdata <= up_irq_mask;
9'h021: up_rdata <= up_irq_pending;
9'h022: up_rdata <= up_irq_source;