update adi_library to vivado 2024.1
compile adi_library with latest hdl commit and vivado 2024.1
This commit is contained in:
@@ -1,6 +1,6 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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@@ -26,7 +26,7 @@
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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@@ -58,7 +58,8 @@ module request_arb #(
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parameter AXI_LENGTH_WIDTH_DEST = 8,
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parameter ENABLE_DIAGNOSTICS_IF = 0,
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parameter ALLOW_ASYM_MEM = 0,
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parameter CACHE_COHERENT_DEST = 0
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parameter [3:0] AXI_AXCACHE = 4'b0011,
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parameter [2:0] AXI_AXPROT = 3'b000
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) (
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input req_clk,
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input req_resetn,
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@@ -357,7 +358,8 @@ module request_arb #(
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.MAX_BYTES_PER_BURST(MAX_BYTES_PER_BURST),
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.BYTES_PER_BURST_WIDTH(BYTES_PER_BURST_WIDTH),
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.AXI_LENGTH_WIDTH(AXI_LENGTH_WIDTH_DEST),
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.CACHE_COHERENT(CACHE_COHERENT_DEST)
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.AXI_AXCACHE(AXI_AXCACHE),
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.AXI_AXPROT(AXI_AXPROT)
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) i_dest_dma_mm (
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.m_axi_aclk(m_dest_axi_aclk),
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.m_axi_aresetn(dest_resetn),
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@@ -619,7 +621,9 @@ module request_arb #(
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.DMA_ADDR_WIDTH(DMA_AXI_ADDR_WIDTH),
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.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC),
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.BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH_SRC),
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.AXI_LENGTH_WIDTH(AXI_LENGTH_WIDTH_SRC)
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.AXI_LENGTH_WIDTH(AXI_LENGTH_WIDTH_SRC),
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.AXI_AXCACHE(AXI_AXCACHE),
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.AXI_AXPROT(AXI_AXPROT)
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) i_src_dma_mm (
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.m_axi_aclk(m_src_axi_aclk),
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.m_axi_aresetn(src_resetn),
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