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update adi_library to vivado 2024.1

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compile adi_library with latest hdl commit and vivado 2024.1
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josh
2024-06-06 11:22:50 +08:00
parent 3c6c573f6a
commit 24cc6b9ee9
695 changed files with 17906 additions and 9982 deletions
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adi_library/axi_logic_analyzer/axi_logic_analyzer.v
+15 -3
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@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2017-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
@@ -90,6 +90,7 @@ module axi_logic_analyzer (
// internal registers
reg [15:0] data_r = 'd0;
reg [15:0] data_src_select = 'd0;
reg [ 1:0] trigger_m1 = 'd0;
reg [31:0] downsampler_counter_la = 'd0;
reg [31:0] upsampler_counter_pg = 'd0;
@@ -238,11 +239,22 @@ module axi_logic_analyzer (
for (i = 0 ; i < 16; i = i + 1) begin
assign data_t[i] = od_pp_n[i] ? io_selection[i] | data_o[i] : io_selection[i];
always @(posedge clk_out) begin
data_o[i] <= overwrite_enable[i] ? overwrite_data[i] : data_r[i];
data_o[i] <= data_src_select[i] ? overwrite_data[i] : data_r[i];
end
always @(posedge clk_out) begin
data_src_select[i] <= data_src_select[i] ?
(~dac_valid) | overwrite_enable[i]:
overwrite_enable[i];
end
always @(posedge clk_out) begin
if(dac_valid == 1'b1) begin
data_r[i] <= dac_data[i];
end else begin
if (data_src_select[i] == 1'b1) begin
data_r[i] <= overwrite_data[i];
end
end
if (io_selection_s[i] == 1'b1) begin
io_selection[i] <= 1'b1;