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update adi_library to vivado 2024.1

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compile adi_library with latest hdl commit and vivado 2024.1
This commit is contained in:
josh
2024-06-06 11:22:50 +08:00
parent 3c6c573f6a
commit 24cc6b9ee9
695 changed files with 17906 additions and 9982 deletions
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adi_library/axi_pwm_gen/Makefile
+2 -1
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@@ -1,5 +1,5 @@
####################################################################################
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
## Copyright (c) 2018 - 2024 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
@@ -21,6 +21,7 @@ XILINX_LIB_DEPS += util_cdc
INTEL_DEPS += ../intel/common/up_rst_constr.sdc
INTEL_DEPS += ../util_cdc/sync_bits.v
INTEL_DEPS += ../util_cdc/sync_data.v
INTEL_DEPS += ../util_cdc/sync_event.v
INTEL_DEPS += axi_pwm_gen_constr.sdc
INTEL_DEPS += axi_pwm_gen_hw.tcl
adi_library/axi_pwm_gen/axi_pwm_gen.sv
+107 -29
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@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
@@ -41,6 +41,10 @@ module axi_pwm_gen #(
parameter N_PWMS = 1,
parameter PWM_EXT_SYNC = 0,
parameter EXT_ASYNC_SYNC = 0,
parameter SOFTWARE_BRINGUP = 1,
parameter EXT_SYNC_PHASE_ALIGN = 0,
parameter FORCE_ALIGN = 0,
parameter START_AT_SYNC = 1,
parameter PULSE_0_WIDTH = 7,
parameter PULSE_1_WIDTH = 7,
parameter PULSE_2_WIDTH = 7,
@@ -139,8 +143,8 @@ module axi_pwm_gen #(
localparam PWMS = N_PWMS-1;
localparam [31:0] CORE_VERSION = {16'h0002, /* MAJOR */
8'h00, /* MINOR */
8'h00}; /* PATCH */
8'h01, /* MINOR */
8'h01}; /* PATCH */
localparam [31:0] CORE_MAGIC = 32'h601a3471; // PLSG
localparam reg [31:0] PULSE_WIDTH_G[15:0] = '{PULSE_0_WIDTH,
PULSE_1_WIDTH,
@@ -197,8 +201,9 @@ module axi_pwm_gen #(
reg [PWMS:0] sync;
reg [31:0] offset_cnt = 32'd0;
reg offset_alignment = 1'b0;
reg pause_cnt_d = 1'b0;
reg offset_alignment = 1'b1;
reg [31:0] pwm_offset_d[0:PWMS];
reg [31:0] pwm_offset_read[0:PWMS];
// internal signals
@@ -219,9 +224,17 @@ module axi_pwm_gen #(
wire [ 31:0] pwm_offset_s[0:PWMS];
wire [ 15:0] pwm_armed;
wire load_config_s;
wire start_at_sync_s;
wire force_align_s;
wire ext_sync_align_s;
wire [ 15:0] ready_to_align_s;
wire [ 15:0] active_channel_s;
wire pwm_gen_resetn;
wire ext_sync_s;
wire new_alignment;
wire pause_cnt;
wire enable_wait;
wire wait_for_all;
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
@@ -229,6 +242,10 @@ module axi_pwm_gen #(
axi_pwm_gen_regmap #(
.ID (ID),
.ASYNC_CLK_EN (ASYNC_CLK_EN),
.SOFTWARE_BRINGUP (SOFTWARE_BRINGUP),
.EXT_SYNC_PHASE_ALIGN (EXT_SYNC_PHASE_ALIGN),
.FORCE_ALIGN (FORCE_ALIGN),
.START_AT_SYNC (START_AT_SYNC),
.CORE_MAGIC (CORE_MAGIC),
.CORE_VERSION (CORE_VERSION),
.N_PWMS (PWMS),
@@ -243,6 +260,9 @@ module axi_pwm_gen #(
.pwm_period (pwm_period_s),
.pwm_offset (pwm_offset_s),
.load_config (load_config_s),
.start_at_sync (start_at_sync_s),
.force_align (force_align_s),
.ext_sync_align (ext_sync_align_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
@@ -278,45 +298,95 @@ module axi_pwm_gen #(
endgenerate
assign new_alignment = load_config_s | ext_sync_s & ext_sync_align_s;
// offset counter
always @(posedge clk) begin
if (offset_alignment == 1'b1 || pwm_gen_resetn == 1'b0) begin
if (offset_alignment == 1'b1 || pwm_gen_resetn == 1'b0 || ext_sync_s == 1'b1) begin
offset_cnt <= 32'd0;
end else begin
offset_cnt <= offset_cnt + 1'b1;
end
if (pwm_gen_resetn == 1'b0) begin
offset_alignment <= 1'b0;
offset_alignment <= 1'b1;
end else begin
// when using external sync an offset alignment can be done only
// after all pwm counters are paused(load_config)/reseated
offset_alignment <= (load_config_s == 1'b1) ? 1'b1 :
// the offset alignment by external sync has two options
// 1. event on a faster clock(2'nd async clk) cannot be sampled on the base
// external clock.
// 2. fall edge
// when using external sync an offset alignment can only be done
// after all pwm counters are paused(load_config)/reseated while the
// external sync is held high
offset_alignment <= (new_alignment == 1'b1) ? 1'b1 :
offset_alignment &
(ext_sync_s ? 1'b1 : !pause_cnt);
(ext_sync_s ? 1'b1 : pause_cnt);
end
end
assign pause_cnt = ((pwm_armed[1] |
pwm_armed[2] |
pwm_armed[3] |
pwm_armed[4] |
pwm_armed[5] |
pwm_armed[6] |
pwm_armed[7] |
pwm_armed[8] |
pwm_armed[9] |
pwm_armed[10] |
pwm_armed[11] |
pwm_armed[12] |
pwm_armed[13] |
pwm_armed[14] |
pwm_armed[15] ) ? 1'b1 : 1'b0);
assign enable_wait = ((pwm_armed[0] & active_channel_s[0]) |
(pwm_armed[1] & active_channel_s[1]) |
(pwm_armed[2] & active_channel_s[2]) |
(pwm_armed[3] & active_channel_s[3]) |
(pwm_armed[4] & active_channel_s[4]) |
(pwm_armed[5] & active_channel_s[5]) |
(pwm_armed[6] & active_channel_s[6]) |
(pwm_armed[7] & active_channel_s[7]) |
(pwm_armed[8] & active_channel_s[8]) |
(pwm_armed[9] & active_channel_s[9]) |
(pwm_armed[10] & active_channel_s[10]) |
(pwm_armed[11] & active_channel_s[11]) |
(pwm_armed[12] & active_channel_s[12]) |
(pwm_armed[13] & active_channel_s[13]) |
(pwm_armed[14] & active_channel_s[14]) |
(pwm_armed[15] & active_channel_s[15]));
assign wait_for_all = (pwm_armed[0] &
pwm_armed[1] &
pwm_armed[2] &
pwm_armed[3] &
pwm_armed[4] &
pwm_armed[5] &
pwm_armed[6] &
pwm_armed[7] &
pwm_armed[8] &
pwm_armed[9] &
pwm_armed[10] &
pwm_armed[11] &
pwm_armed[12] &
pwm_armed[13] &
pwm_armed[14] &
pwm_armed[15]);
assign pause_cnt = !(enable_wait & wait_for_all);
genvar i;
generate
for (i = 0; i <= 15; i = i + 1) begin: pwm_cnt
if (i <= PWMS) begin
// flop the desired offset
always @(posedge clk) begin
if (pwm_gen_resetn == 1'b0) begin
pwm_offset_d[i] <= pwm_offset_s[i];
pwm_offset_read[i] <= pwm_offset_s[i];
end else begin
// load the input period/width values
if (load_config_s) begin
pwm_offset_read[i] <= pwm_offset_s[i];
if (force_align_s == 1) begin
pwm_offset_d[i] <= pwm_offset_s[i];
end
end
// update the current period/width at the end of the period
if (ready_to_align_s[i]) begin
pwm_offset_d[i] <= pwm_offset_read[i];
end
end
end
axi_pwm_gen_1 #(
.PULSE_WIDTH (PULSE_WIDTH_G[i]),
.PULSE_PERIOD (PULSE_PERIOD_G[i])
@@ -326,19 +396,27 @@ module axi_pwm_gen #(
.pulse_width (pwm_width_s[i]),
.pulse_period (pwm_period_s[i]),
.load_config (load_config_s),
.start_at_sync_en (start_at_sync_s),
.force_align_en (force_align_s),
.ext_sync_align_en (ext_sync_align_s),
.ext_sync (ext_sync_s),
.sync (sync[i]),
.pulse (pwm[i]),
.active_channel (active_channel_s[i]),
.ready_to_align (ready_to_align_s[i]),
.pulse_armed (pwm_armed[i]));
always @(posedge clk) begin
if (pwm_gen_resetn == 1'b0) begin
sync[i] <= 1'b1;
end else begin
sync[i] <= (offset_cnt == pwm_offset_s[i]) ? offset_alignment : 1'b1;
sync[i] <= (offset_cnt == pwm_offset_d[i]) ? offset_alignment : 1'b1;
end
end
end else begin
assign pwm[i] = 1'b0;
assign pwm_armed[i] = 1'b0;
assign pwm_armed[i] = 1'b1;
assign active_channel_s[i] = 1'b0;
assign ready_to_align_s[i] = 1'b1;
end
end
endgenerate
adi_library/axi_pwm_gen/axi_pwm_gen.xpr
+13 -14
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@@ -1,13 +1,13 @@
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2023.2.1 (64-bit) -->
<!-- Product Version: Vivado v2024.1 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_pwm_gen/axi_pwm_gen.xpr">
<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_pwm_gen/axi_pwm_gen.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="c1f58724adcf46cba87c475145902d53"/>
<Option Name="Id" Val="4f5bf7a24ec54b409d5b2a8cfa41cf19"/>
<Option Name="Part" Val="xc7vx485tffg1157-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
<Option Name="SimulatorVersionXsim" Val="2024.1"/>
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
<Option Name="SimulatorVersionRiviera" Val="2023.04"/>
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -189,21 +188,21 @@
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="21">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Runs Version="1" Minor="22">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
@@ -216,7 +215,7 @@
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
adi_library/axi_pwm_gen/axi_pwm_gen_1.v
+72 -18
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@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
@@ -45,12 +45,21 @@ module axi_pwm_gen_1 #(
input [31:0] pulse_width,
input [31:0] pulse_period,
input load_config,
input start_at_sync_en,
input force_align_en,
input ext_sync_align_en,
input ext_sync,
input sync,
output pulse,
output active_channel,
output ready_to_align,
output pulse_armed
);
localparam [0:0] ARM = 0;
localparam [0:0] RUN = 1;
// internal registers
reg [31:0] pulse_period_cnt = 32'h0;
@@ -60,19 +69,28 @@ module axi_pwm_gen_1 #(
reg [31:0] pulse_width_d = PULSE_WIDTH;
reg phase_align_armed = 1'b1;
reg pulse_i = 1'b0;
reg busy = 1'b0;
reg run_sm = ARM;
reg run_sm_next = ARM;
reg pulse_start;
reg pulse_stop;
// internal wires
wire ext_sync_align;
wire phase_align;
wire end_of_period;
wire end_of_pulse;
wire pulse_enable;
wire align_pulse;
wire align_period;
wire start_at_sync;
// enable pwm
assign pulse_enable = (pulse_period_d != 32'd0) ? 1'b1 : 1'b0;
assign ext_sync_align = ext_sync & ext_sync_align_en;
// flop the desired period
always @(posedge clk) begin
@@ -86,6 +104,10 @@ module axi_pwm_gen_1 #(
if (load_config) begin
pulse_period_read <= pulse_period;
pulse_width_read <= pulse_width;
if (force_align_en == 1 && start_at_sync_en == 1) begin
pulse_period_d <= pulse_period;
pulse_width_d <= pulse_width;
end
end
// update the current period/width at the end of the period
if (end_of_period | ~pulse_enable) begin
@@ -103,30 +125,47 @@ module axi_pwm_gen_1 #(
end else begin
if (load_config == 1'b1) begin
phase_align_armed <= sync;
end else if (ext_sync_align == 1'b1) begin
phase_align_armed <= sync;
end else begin
phase_align_armed <= phase_align_armed & sync;
end
end
end
// phase align SM
always @(posedge clk) begin
if (rstn == 1'b0) begin
busy <= 1'b0;
run_sm <= ARM;
run_sm_next <= ARM;
end else begin
if (end_of_period) begin
busy <= 1'b0;
end else if ( ~(phase_align_armed & sync)) begin
busy <= 1'b1;
end
case (run_sm)
ARM: begin
if (sync == 1'b0) begin
run_sm_next <= RUN;
end
end
RUN: begin
if (force_align_en == 1) begin
if (ext_sync_align == 1'b1 || load_config == 1'b1) begin
run_sm_next <= ARM;
end
end else if (phase_align_armed == 1'b1 && end_of_period == 1'b1) begin
run_sm_next <= ARM;
end else if (end_of_period == 1'b1) begin
run_sm_next <= RUN;
end
end
endcase
run_sm <= run_sm_next;
end
end
assign phase_align = phase_align_armed & sync & busy;
// a free running counter
assign align_pulse = ext_sync_align & force_align_en;
assign align_period = align_pulse == 1 || run_sm_next <= ARM || end_of_period == 1'b1;
always @(posedge clk) begin
if (rstn == 1'b0 || phase_align == 1'b1 || end_of_period == 1'b1) begin
if (rstn == 1'b0 || align_period) begin
pulse_period_cnt <= 32'd1;
end else begin
if (pulse_enable == 1'b1) begin
@@ -138,17 +177,32 @@ module axi_pwm_gen_1 #(
assign end_of_period = (pulse_period_cnt == pulse_period_d) ? 1'b1 : 1'b0;
assign end_of_pulse = (pulse_period_cnt == pulse_width_d) ? 1'b1 : 1'b0;
assign start_at_sync = start_at_sync_en == 1 ? ~run_sm & ~sync : 1'b0;
always @(posedge clk) begin
pulse_start <= start_at_sync == 1'b1 ||
end_of_period & !phase_align_armed & |pulse_width_d;
pulse_stop <= rstn == 1'b0 ||
align_pulse == 1'b1 ||
pulse_enable == 1'b0 ||
pulse_width_d == 32'd0 ||
end_of_pulse ? !end_of_period : 1'b0;
end
// generate pulse with a specified width
always @ (posedge clk) begin
if ((rstn == 1'b0) || (end_of_pulse == 1'b1)) begin
always @(posedge clk) begin
if (pulse_stop) begin
pulse_i <= 1'b0;
end else if ((end_of_period == 1'b1 || phase_align == 1'b1) && pulse_enable == 1'b1) begin
end else if (pulse_start) begin
pulse_i <= 1'b1;
end
end
assign pulse = pulse_i & !(phase_align_armed & sync);
assign pulse_armed = phase_align_armed;
assign pulse = pulse_i;
assign active_channel = pulse_enable;
assign ready_to_align = end_of_period | ~pulse_enable;
assign pulse_armed = phase_align_armed & ~run_sm | ~pulse_enable;
endmodule
adi_library/axi_pwm_gen/axi_pwm_gen_constr.sdc
+1 -1
View File
@@ -1,5 +1,5 @@
###############################################################################
## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
adi_library/axi_pwm_gen/axi_pwm_gen_constr.ttcl
+13 -1
View File
@@ -1,5 +1,5 @@
###############################################################################
## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
# SPDX short identifier: ADIBSD
###############################################################################
@@ -34,4 +34,16 @@ set_property ASYNC_REG TRUE \
-from [get_pins -hierarchical * -filter {NAME=~*i_load_config_sync/in_toggle_d1_reg/C}] \
-to [get_pins -hierarchical * -filter {NAME=~*i_load_config_sync/i_sync_out/cdc_sync_stage1_reg[0]/D}]
set_false_path \
-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/*i_pwm_controls/cdc_hold_reg*}] \
-to [get_cells -hierarchical * -filter {NAME=~*i_regmap/*i_pwm_controls/out_data_reg*}]
set_false_path \
-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/*i_pwm_controls/in_toggle_d1_reg}] \
-to [get_cells -hierarchical * -filter {NAME=~*i_regmap/*i_pwm_controls/i_sync_out/cdc_sync_stage1_reg[*]}]
set_false_path \
-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/*i_pwm_controls/out_toggle_d1_reg}] \
-to [get_cells -hierarchical * -filter {NAME=~*i_regmap/*i_pwm_controls/i_sync_in/cdc_sync_stage1_reg[*]}]
<: } :>
adi_library/axi_pwm_gen/axi_pwm_gen_hw.tcl
Regular → Executable
+5 -1
View File
@@ -1,5 +1,5 @@
###############################################################################
## Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
@@ -30,6 +30,10 @@ ad_ip_parameter ASYNC_CLK_EN INTEGER 1
ad_ip_parameter N_PWMS INTEGER 1
ad_ip_parameter PWM_EXT_SYNC INTEGER 0
ad_ip_parameter EXT_ASYNC_SYNC INTEGER 0
ad_ip_parameter EXT_SYNC_PHASE_ALIGN INTEGER 0
ad_ip_parameter SOFTWARE_BRINGUP INTEGER 1
ad_ip_parameter FORCE_ALIGN INTEGER 0
ad_ip_parameter START_AT_SYNC INTEGER 1
ad_ip_parameter PULSE_0_WIDTH INTEGER 7
ad_ip_parameter PULSE_1_WIDTH INTEGER 7
ad_ip_parameter PULSE_2_WIDTH INTEGER 7
adi_library/axi_pwm_gen/axi_pwm_gen_ip.tcl
+53 -19
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@@ -1,5 +1,5 @@
###############################################################################
## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
@@ -67,45 +67,76 @@ ipx::save_core $cc
ipgui::add_page -name {AXI PWM Generator} -component $cc -display_name {AXI PWM Generator}
set page0 [ipgui::get_pagespec -name "AXI PWM Generator" -component $cc]
ipgui::add_param -name "ASYNC_CLK_EN" -component $cc -parent $page0
set_property -dict [list \
"display_name" "ASYNC_CLK_EN" \
"tooltip" "External clock for the counter" \
"widget" "checkBox" \
] [ipgui::get_guiparamspec -name "ASYNC_CLK_EN" -component $cc]
ipgui::add_param -name "EXT_ASYNC_SYNC" -component $cc -parent $page0
set_property -dict [list \
"display_name" "External sync signal is asynchronous" \
"tooltip" "NOTE: If active the ext_sync will be delayed 2 clock cycles." \
"widget" "checkBox" \
] [ipgui::get_guiparamspec -name "EXT_ASYNC_SYNC" -component $cc]
# N_PWMs
ipgui::add_param -name "N_PWMS" -component $cc -parent $page0
set_property -dict [list \
"display_name" "Number of pwms" \
] [ipgui::get_guiparamspec -name "N_PWMS" -component $cc]
# ASYNC_CLK_EN
ipgui::add_param -name "ASYNC_CLK_EN" -component $cc -parent $page0
set_property -dict [list \
"display_name" "ASYNC_CLK_EN" \
"tooltip" "The logic and PWMs will be driven by ext_clk. Otherwise the axi clock will be used" \
"widget" "checkBox" \
] [ipgui::get_guiparamspec -name "ASYNC_CLK_EN" -component $cc]
# PWM_EXT_SYNC
ipgui::add_param -name "PWM_EXT_SYNC" -component $cc -parent $page0
set_property -dict [list \
"display_name" "External sync" \
"tooltip" "NOTE: If active the whole pwm gen module will be waiting for the ext_sync to be set low. A load config or reset must be used before deaserting the ext_sync" \
"tooltip" "If active the whole pwm gen module will be waiting for the ext_sync to be set low. A load config or reset must be used before de-asserting the ext_sync to retrigger the sync process" \
"widget" "checkBox" \
] [ipgui::get_guiparamspec -name "PWM_EXT_SYNC" -component $cc]
# EXT_ASYNC_SYNC
ipgui::add_param -name "EXT_ASYNC_SYNC" -component $cc -parent $page0
set_property -dict [list \
"display_name" "External sync signal is asynchronous" \
"tooltip" "NOTE: If active the ext_sync will be delayed 2 clock cycles." \
"widget" "checkBox" \
] [ipgui::get_guiparamspec -name "EXT_ASYNC_SYNC" -component $cc]
set_property enablement_tcl_expr {expr $PWM_EXT_SYNC == 1} [ipx::get_user_parameters EXT_ASYNC_SYNC -of_objects $cc]
# SOFTWARE_BRINGUP
ipgui::add_param -name "SOFTWARE_BRINGUP" -component $cc -parent $page0
set_property -dict [list \
"display_name" "Require software bringup" \
"tooltip" "If active the software must bring the core out of soft reset, after a system reset, in order for the pwm signals to be generated" \
"widget" "checkBox" \
] [ipgui::get_guiparamspec -name "SOFTWARE_BRINGUP" -component $cc]
# EXT_SYNC_PHASE_ALIGN
ipgui::add_param -name "EXT_SYNC_PHASE_ALIGN" -component $cc -parent $page0
set_property -dict [list \
"display_name" "External sync enable phase align" \
"tooltip" "If active the ext_sync will trigger a phase align at each neg-edge. Otherwise the phase align will be armed by a load config toggle. Software over writable at runtime." \
"widget" "checkBox" \
] [ipgui::get_guiparamspec -name "EXT_SYNC_PHASE_ALIGN" -component $cc]
set_property enablement_tcl_expr {expr $PWM_EXT_SYNC == 1} [ipx::get_user_parameters EXT_SYNC_PHASE_ALIGN -of_objects $cc]
# FORCE_ALIGN
ipgui::add_param -name "FORCE_ALIGN" -component $cc -parent $page0
set_property -dict [list \
"display_name" "Force align" \
"tooltip" "If active the current active pulses are immediately stopped and realigned. Otherwise, the synchronized pulses will start only after all running pulse periods end. Software over writable at runtime." \
"widget" "checkBox" \
] [ipgui::get_guiparamspec -name "FORCE_ALIGN" -component $cc]
# START_AT_SYNC
ipgui::add_param -name "START_AT_SYNC" -component $cc -parent $page0
set_property -dict [list \
"display_name" "Start at sync" \
"tooltip" "If active, the pulses will start after the trigger event. Otherwise each pulse will start after a period equal to the one for which it is set. Software over writable at runtime." \
"widget" "checkBox" \
] [ipgui::get_guiparamspec -name "START_AT_SYNC" -component $cc]
# Maximum 16 pwms
for {set i 0} {$i < 16} {incr i} {
ipgui::add_param -name "PULSE_${i}_WIDTH" -component $cc -parent $page0
set_property -dict [list \
"display_name" "PULSE $i width" \
"tooltip" "PULSE width of the generated signal. The unit interval is the system or external clock period." \
"tooltip" "PULSE width of the generated signal. The unit interval represents a period the system or external clock period." \
] [ipgui::get_guiparamspec -name "PULSE_${i}_WIDTH" -component $cc]
set_property -dict [list \
@@ -114,11 +145,12 @@ for {set i 0} {$i < 16} {incr i} {
"value_validation_range_maximum" "2147483647" \
] \
[ipx::get_user_parameters PULSE_${i}_WIDTH -of_objects $cc]
set_property enablement_tcl_expr "expr \$N_PWMS >= $i" [ipx::get_user_parameters PULSE_${i}_WIDTH -of_objects $cc]
ipgui::add_param -name "PULSE_${i}_PERIOD" -component $cc -parent $page0
set_property -dict [list \
"display_name" "PULSE ${i} period" \
"tooltip" "Period of the generated signal. The unit interval is the system or external clock period." \
"tooltip" "Period of the generated signal. The unit interval represents a period the system or external clock period." \
] [ipgui::get_guiparamspec -name "PULSE_${i}_PERIOD" -component $cc]
set_property -dict [list \
@@ -127,11 +159,12 @@ for {set i 0} {$i < 16} {incr i} {
"value_validation_range_maximum" "2147483647" \
] \
[ipx::get_user_parameters PULSE_${i}_PERIOD -of_objects $cc]
set_property enablement_tcl_expr "expr \$N_PWMS >= $i" [ipx::get_user_parameters PULSE_${i}_PERIOD -of_objects $cc]
ipgui::add_param -name "PULSE_${i}_OFFSET" -component $cc -parent $page0
set_property -dict [list \
"display_name" "PULSE ${i} offset" \
"tooltip" "Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period." \
"tooltip" "Offset of the generated signal referenced to PULSE 1. The unit interval represents a period the system or external clock period." \
] [ipgui::get_guiparamspec -name "PULSE_${i}_OFFSET" -component $cc]
set_property -dict [list \
@@ -140,6 +173,7 @@ for {set i 0} {$i < 16} {incr i} {
"value_validation_range_maximum" "2147483647" \
] \
[ipx::get_user_parameters PULSE_${i}_OFFSET -of_objects $cc]
set_property enablement_tcl_expr "expr \$N_PWMS >= $i" [ipx::get_user_parameters PULSE_${i}_OFFSET -of_objects $cc]
}
for {set i 0} {$i < 16} {incr i} {
adi_library/axi_pwm_gen/axi_pwm_gen_regmap.sv
+38 -8
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@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
@@ -40,6 +40,10 @@ module axi_pwm_gen_regmap #(
parameter CORE_MAGIC = 0,
parameter CORE_VERSION = 0,
parameter ASYNC_CLK_EN = 1,
parameter SOFTWARE_BRINGUP = 1,
parameter EXT_SYNC_PHASE_ALIGN = 0,
parameter FORCE_ALIGN = 0,
parameter START_AT_SYNC = 1,
parameter N_PWMS = 0,
parameter reg [31:0] PULSE_WIDTH_G[0:15] = '{16{32'd0}},
parameter reg [31:0] PULSE_PERIOD_G[0:15] = '{16{32'd0}},
@@ -58,6 +62,9 @@ module axi_pwm_gen_regmap #(
output [31:0] pwm_period[0:N_PWMS],
output [31:0] pwm_offset[0:N_PWMS],
output load_config,
output start_at_sync,
output force_align,
output ext_sync_align,
// processor interface
@@ -80,7 +87,16 @@ module axi_pwm_gen_regmap #(
reg [31:0] up_pwm_period[0:N_PWMS] = PULSE_PERIOD_G[0:N_PWMS];
reg [31:0] up_pwm_offset[0:N_PWMS] = PULSE_OFFSET_G[0:N_PWMS];
reg up_load_config = 1'b0;
reg up_reset = 1'b1;
reg up_reset = SOFTWARE_BRINGUP[0];
reg [ 2:0] up_control = {EXT_SYNC_PHASE_ALIGN[0],FORCE_ALIGN[0],START_AT_SYNC[0]};
// internal signals
wire [ 2:0] control;
assign start_at_sync = control[0];
assign force_align = control[1];
assign ext_sync_align = control[2];
genvar n;
@@ -88,11 +104,12 @@ module axi_pwm_gen_regmap #(
if (up_rstn == 0) begin
up_wack <= 'd0;
up_scratch <= 'd0;
up_pwm_width = PULSE_WIDTH_G[0:N_PWMS];
up_pwm_period = PULSE_PERIOD_G[0:N_PWMS];
up_pwm_offset = PULSE_OFFSET_G[0:N_PWMS];
up_pwm_width <= PULSE_WIDTH_G[0:N_PWMS];
up_pwm_period <= PULSE_PERIOD_G[0:N_PWMS];
up_pwm_offset <= PULSE_OFFSET_G[0:N_PWMS];
up_load_config <= 1'b0;
up_reset <= 1'b1;
up_reset <= SOFTWARE_BRINGUP[0];
up_control <= {EXT_SYNC_PHASE_ALIGN[0],FORCE_ALIGN[0],START_AT_SYNC[0]};
end else begin
up_wack <= up_wreq;
if ((up_wreq == 1'b1) && (up_waddr == 14'h2)) begin
@@ -104,6 +121,9 @@ module axi_pwm_gen_regmap #(
end else begin
up_load_config <= 1'b0;
end
if ((up_wreq == 1'b1) && (up_waddr == 14'h6)) begin
up_control <= up_wdata[2:0];
end
for (int i = 0; i <= N_PWMS; i++) begin
if ((up_wreq == 1'b1) && (up_waddr == 14'h10 + i)) begin
up_pwm_period[i] <= up_wdata;
@@ -133,6 +153,7 @@ module axi_pwm_gen_regmap #(
14'h3: up_rdata <= CORE_MAGIC;
14'h4: up_rdata <= up_reset;
14'h5: up_rdata <= N_PWMS +1;
14'h6: up_rdata <= {29'd0, up_control};
default: up_rdata <= 0;
endcase
end else if (up_raddr[3:0] > N_PWMS) begin
@@ -161,7 +182,16 @@ module axi_pwm_gen_regmap #(
.rstn (pwm_gen_resetn),
.rst ());
for (n = 0; n <= N_PWMS; n = n + 1) begin: up_to_adc_cdc
sync_data #(
.NUM_OF_BITS (3),
.ASYNC_CLK (1))
i_pwm_controls (
.in_clk (up_clk),
.in_data (up_control),
.out_clk (clk_out),
.out_data (control));
for (n = 0; n <= N_PWMS; n = n + 1) begin: pwm_cdc
sync_data #(
.NUM_OF_BITS (96),
.ASYNC_CLK (1))
adi_library/axi_pwm_gen/component.xml
+723 -10
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adi_library/axi_pwm_gen/gui/axi_pwm_gen_v1_0.gtcl
+51
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@@ -0,0 +1,51 @@
# This file is automatically written. Do not modify.
proc gen_USERPARAMETER_EXT_ASYNC_SYNC_ENABLEMENT {PWM_EXT_SYNC } {expr $PWM_EXT_SYNC == 1}
proc gen_USERPARAMETER_EXT_SYNC_PHASE_ALIGN_ENABLEMENT {PWM_EXT_SYNC } {expr $PWM_EXT_SYNC == 1}
proc gen_USERPARAMETER_PULSE_0_WIDTH_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 0}
proc gen_USERPARAMETER_PULSE_1_WIDTH_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 1}
proc gen_USERPARAMETER_PULSE_2_WIDTH_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 2}
proc gen_USERPARAMETER_PULSE_3_WIDTH_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 3}
proc gen_USERPARAMETER_PULSE_4_WIDTH_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 4}
proc gen_USERPARAMETER_PULSE_5_WIDTH_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 5}
proc gen_USERPARAMETER_PULSE_6_WIDTH_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 6}
proc gen_USERPARAMETER_PULSE_7_WIDTH_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 7}
proc gen_USERPARAMETER_PULSE_8_WIDTH_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 8}
proc gen_USERPARAMETER_PULSE_9_WIDTH_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 9}
proc gen_USERPARAMETER_PULSE_10_WIDTH_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 10}
proc gen_USERPARAMETER_PULSE_11_WIDTH_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 11}
proc gen_USERPARAMETER_PULSE_12_WIDTH_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 12}
proc gen_USERPARAMETER_PULSE_13_WIDTH_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 13}
proc gen_USERPARAMETER_PULSE_14_WIDTH_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 14}
proc gen_USERPARAMETER_PULSE_15_WIDTH_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 15}
proc gen_USERPARAMETER_PULSE_0_PERIOD_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 0}
proc gen_USERPARAMETER_PULSE_1_PERIOD_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 1}
proc gen_USERPARAMETER_PULSE_2_PERIOD_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 2}
proc gen_USERPARAMETER_PULSE_3_PERIOD_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 3}
proc gen_USERPARAMETER_PULSE_4_PERIOD_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 4}
proc gen_USERPARAMETER_PULSE_5_PERIOD_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 5}
proc gen_USERPARAMETER_PULSE_6_PERIOD_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 6}
proc gen_USERPARAMETER_PULSE_7_PERIOD_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 7}
proc gen_USERPARAMETER_PULSE_8_PERIOD_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 8}
proc gen_USERPARAMETER_PULSE_9_PERIOD_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 9}
proc gen_USERPARAMETER_PULSE_10_PERIOD_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 10}
proc gen_USERPARAMETER_PULSE_11_PERIOD_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 11}
proc gen_USERPARAMETER_PULSE_12_PERIOD_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 12}
proc gen_USERPARAMETER_PULSE_13_PERIOD_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 13}
proc gen_USERPARAMETER_PULSE_14_PERIOD_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 14}
proc gen_USERPARAMETER_PULSE_15_PERIOD_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 15}
proc gen_USERPARAMETER_PULSE_0_OFFSET_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 0}
proc gen_USERPARAMETER_PULSE_1_OFFSET_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 1}
proc gen_USERPARAMETER_PULSE_2_OFFSET_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 2}
proc gen_USERPARAMETER_PULSE_3_OFFSET_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 3}
proc gen_USERPARAMETER_PULSE_4_OFFSET_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 4}
proc gen_USERPARAMETER_PULSE_5_OFFSET_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 5}
proc gen_USERPARAMETER_PULSE_6_OFFSET_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 6}
proc gen_USERPARAMETER_PULSE_7_OFFSET_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 7}
proc gen_USERPARAMETER_PULSE_8_OFFSET_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 8}
proc gen_USERPARAMETER_PULSE_9_OFFSET_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 9}
proc gen_USERPARAMETER_PULSE_10_OFFSET_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 10}
proc gen_USERPARAMETER_PULSE_11_OFFSET_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 11}
proc gen_USERPARAMETER_PULSE_12_OFFSET_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 12}
proc gen_USERPARAMETER_PULSE_13_OFFSET_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 13}
proc gen_USERPARAMETER_PULSE_14_OFFSET_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 14}
proc gen_USERPARAMETER_PULSE_15_OFFSET_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 15}
adi_library/axi_pwm_gen/xgui/axi_pwm_gen_v1_0.tcl
+1006 -488
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